src/share/vm/opto/macro.cpp
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8153340 Cdiff src/share/vm/opto/macro.cpp
src/share/vm/opto/macro.cpp
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*** 1895,1905 ****
// adding prefetches
pf_phi_abio->init_req( fall_in_path, i_o );
Node *prefetch_adr;
Node *prefetch;
! uint lines = AllocatePrefetchDistance / AllocatePrefetchStepSize;
uint step_size = AllocatePrefetchStepSize;
uint distance = 0;
for ( uint i = 0; i < lines; i++ ) {
prefetch_adr = new AddPNode( old_pf_wm, new_pf_wmt,
--- 1895,1905 ----
// adding prefetches
pf_phi_abio->init_req( fall_in_path, i_o );
Node *prefetch_adr;
Node *prefetch;
! uint lines = (length != NULL) ? AllocatePrefetchLines : AllocateInstancePrefetchLines;
uint step_size = AllocatePrefetchStepSize;
uint distance = 0;
for ( uint i = 0; i < lines; i++ ) {
prefetch_adr = new AddPNode( old_pf_wm, new_pf_wmt,
*** 1924,1951 ****
needgc_false = pf_region;
contended_phi_rawmem = pf_phi_rawmem;
i_o = pf_phi_abio;
} else if( UseTLAB && AllocatePrefetchStyle == 3 ) {
! // Insert a prefetch for each allocation.
! // This code is used for Sparc with BIS.
! Node *pf_region = new RegionNode(3);
! Node *pf_phi_rawmem = new PhiNode( pf_region, Type::MEMORY,
! TypeRawPtr::BOTTOM );
! transform_later(pf_region);
// Generate several prefetch instructions.
uint lines = (length != NULL) ? AllocatePrefetchLines : AllocateInstancePrefetchLines;
uint step_size = AllocatePrefetchStepSize;
uint distance = AllocatePrefetchDistance;
// Next cache address.
Node *cache_adr = new AddPNode(old_eden_top, old_eden_top,
! _igvn.MakeConX(distance));
transform_later(cache_adr);
cache_adr = new CastP2XNode(needgc_false, cache_adr);
transform_later(cache_adr);
Node* mask = _igvn.MakeConX(~(intptr_t)(step_size-1));
cache_adr = new AndXNode(cache_adr, mask);
transform_later(cache_adr);
cache_adr = new CastX2PNode(cache_adr);
transform_later(cache_adr);
--- 1924,1952 ----
needgc_false = pf_region;
contended_phi_rawmem = pf_phi_rawmem;
i_o = pf_phi_abio;
} else if( UseTLAB && AllocatePrefetchStyle == 3 ) {
! // Insert a prefetch instruction for each allocation.
! // This code is used for SPARC with BIS.
// Generate several prefetch instructions.
uint lines = (length != NULL) ? AllocatePrefetchLines : AllocateInstancePrefetchLines;
uint step_size = AllocatePrefetchStepSize;
uint distance = AllocatePrefetchDistance;
// Next cache address.
Node *cache_adr = new AddPNode(old_eden_top, old_eden_top,
! _igvn.MakeConX(step_size + distance));
transform_later(cache_adr);
cache_adr = new CastP2XNode(needgc_false, cache_adr);
transform_later(cache_adr);
+ // For BIS instructions to be emitted, the address must be aligned at cache line size.
+ // (The VM sets AllocatePrefetchStepSize to the cache line size, unless a value is
+ // specified at the command line.) If the address is not aligned at cache line size
+ // boundary, a standard store instruction is triggered (instead of the BIS). For the
+ // latter, 8-byte alignment is necessary.
Node* mask = _igvn.MakeConX(~(intptr_t)(step_size-1));
cache_adr = new AndXNode(cache_adr, mask);
transform_later(cache_adr);
cache_adr = new CastX2PNode(cache_adr);
transform_later(cache_adr);
src/share/vm/opto/macro.cpp
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