32 #include "vm_version_sparc.hpp"
33
34 unsigned int VM_Version::_L2_data_cache_line_size = 0;
35
36 void VM_Version::initialize() {
37 assert(_features != 0, "System pre-initialization is not complete.");
38 guarantee(VM_Version::has_v9(), "only SPARC v9 is supported");
39
40 PrefetchCopyIntervalInBytes = prefetch_copy_interval_in_bytes();
41 PrefetchScanIntervalInBytes = prefetch_scan_interval_in_bytes();
42 PrefetchFieldsAhead = prefetch_fields_ahead();
43
44 // Allocation prefetch settings
45 intx cache_line_size = prefetch_data_size();
46 if( cache_line_size > AllocatePrefetchStepSize )
47 AllocatePrefetchStepSize = cache_line_size;
48
49 AllocatePrefetchDistance = allocate_prefetch_distance();
50 AllocatePrefetchStyle = allocate_prefetch_style();
51
52 if (AllocatePrefetchStyle == 3 && !has_blk_init()) {
53 warning("BIS instructions are not available on this CPU");
54 FLAG_SET_DEFAULT(AllocatePrefetchStyle, 1);
55 }
56
57 UseSSE = 0; // Only on x86 and x64
58
59 _supports_cx8 = has_v9();
60 _supports_atomic_getset4 = true; // swap instruction
61
62 if (is_niagara()) {
63 // Indirect branch is the same cost as direct
64 if (FLAG_IS_DEFAULT(UseInlineCaches)) {
65 FLAG_SET_DEFAULT(UseInlineCaches, false);
66 }
67 // Align loops on a single instruction boundary.
68 if (FLAG_IS_DEFAULT(OptoLoopAlignment)) {
69 FLAG_SET_DEFAULT(OptoLoopAlignment, 4);
70 }
71 #ifdef _LP64
72 // 32-bit oops don't make sense for the 64-bit VM on sparc
73 // since the 32-bit VM has the same registers and smaller objects.
74 Universe::set_narrow_oop_shift(LogMinObjAlignmentInBytes);
75 Universe::set_narrow_klass_shift(LogKlassAlignmentInBytes);
76 #endif // _LP64
77 #ifdef COMPILER2
78 // Indirect branch is the same cost as direct
79 if (FLAG_IS_DEFAULT(UseJumpTables)) {
80 FLAG_SET_DEFAULT(UseJumpTables, true);
81 }
82 // Single-issue, so entry and loop tops are
83 // aligned on a single instruction boundary
84 if (FLAG_IS_DEFAULT(InteriorEntryAlignment)) {
85 FLAG_SET_DEFAULT(InteriorEntryAlignment, 4);
86 }
87 if (is_niagara_plus()) {
88 if (has_blk_init() && UseTLAB &&
89 FLAG_IS_DEFAULT(AllocatePrefetchInstr)) {
90 // Use BIS instruction for TLAB allocation prefetch.
91 FLAG_SET_ERGO(intx, AllocatePrefetchInstr, 1);
92 if (FLAG_IS_DEFAULT(AllocatePrefetchStyle)) {
93 FLAG_SET_ERGO(intx, AllocatePrefetchStyle, 3);
94 }
95 if (FLAG_IS_DEFAULT(AllocatePrefetchDistance)) {
96 // Use smaller prefetch distance with BIS
97 FLAG_SET_DEFAULT(AllocatePrefetchDistance, 64);
98 }
99 }
100 if (is_T4()) {
101 // Double number of prefetched cache lines on T4
102 // since L2 cache line size is smaller (32 bytes).
103 if (FLAG_IS_DEFAULT(AllocatePrefetchLines)) {
104 FLAG_SET_ERGO(intx, AllocatePrefetchLines, AllocatePrefetchLines*2);
105 }
106 if (FLAG_IS_DEFAULT(AllocateInstancePrefetchLines)) {
107 FLAG_SET_ERGO(intx, AllocateInstancePrefetchLines, AllocateInstancePrefetchLines*2);
108 }
109 }
110 if (AllocatePrefetchStyle != 3 && FLAG_IS_DEFAULT(AllocatePrefetchDistance)) {
111 // Use different prefetch distance without BIS
112 FLAG_SET_DEFAULT(AllocatePrefetchDistance, 256);
113 }
114 if (AllocatePrefetchInstr == 1) {
115 // Need extra space at the end of TLAB for BIS, otherwise prefetching
116 // instructions will fault (due to accessing memory outside of heap).
117 // The amount of space is the max of the number of lines to
118 // prefetch for array and for instance allocations. (Extra space must be
119 // reserved to accomodate both types of allocations.)
120
121 // +1 for rounding up to next cache line, +1 to be safe
122 int lines = MAX2(AllocatePrefetchLines, AllocateInstancePrefetchLines) + 2;
123 int step_size = AllocatePrefetchStepSize;
124 int distance = AllocatePrefetchDistance;
125 _reserve_for_allocation_prefetch = (distance + step_size*lines)/(int)HeapWordSize;
126 }
127 }
128 #endif
129 }
130
131 // Use hardware population count instruction if available.
132 if (has_hardware_popc()) {
133 if (FLAG_IS_DEFAULT(UsePopCountInstruction)) {
134 FLAG_SET_DEFAULT(UsePopCountInstruction, true);
135 }
136 } else if (UsePopCountInstruction) {
137 warning("POPC instruction is not available on this CPU");
138 FLAG_SET_DEFAULT(UsePopCountInstruction, false);
139 }
140
141 // T4 and newer Sparc cpus have new compare and branch instruction.
142 if (has_cbcond()) {
143 if (FLAG_IS_DEFAULT(UseCBCond)) {
144 FLAG_SET_DEFAULT(UseCBCond, true);
145 }
146 } else if (UseCBCond) {
147 warning("CBCOND instruction is not available on this CPU");
148 FLAG_SET_DEFAULT(UseCBCond, false);
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32 #include "vm_version_sparc.hpp"
33
34 unsigned int VM_Version::_L2_data_cache_line_size = 0;
35
36 void VM_Version::initialize() {
37 assert(_features != 0, "System pre-initialization is not complete.");
38 guarantee(VM_Version::has_v9(), "only SPARC v9 is supported");
39
40 PrefetchCopyIntervalInBytes = prefetch_copy_interval_in_bytes();
41 PrefetchScanIntervalInBytes = prefetch_scan_interval_in_bytes();
42 PrefetchFieldsAhead = prefetch_fields_ahead();
43
44 // Allocation prefetch settings
45 intx cache_line_size = prefetch_data_size();
46 if( cache_line_size > AllocatePrefetchStepSize )
47 AllocatePrefetchStepSize = cache_line_size;
48
49 AllocatePrefetchDistance = allocate_prefetch_distance();
50 AllocatePrefetchStyle = allocate_prefetch_style();
51
52 if (!has_blk_init()) {
53 if (AllocatePrefetchInstr == 1) {
54 warning("BIS instructions required for AllocatePrefetchInstr 1 unavailable");
55 FLAG_SET_DEFAULT(AllocatePrefetchInstr, 0);
56 }
57 }
58
59 UseSSE = 0; // Only on x86 and x64
60
61 _supports_cx8 = has_v9();
62 _supports_atomic_getset4 = true; // swap instruction
63
64 if (is_niagara()) {
65 // Indirect branch is the same cost as direct
66 if (FLAG_IS_DEFAULT(UseInlineCaches)) {
67 FLAG_SET_DEFAULT(UseInlineCaches, false);
68 }
69 // Align loops on a single instruction boundary.
70 if (FLAG_IS_DEFAULT(OptoLoopAlignment)) {
71 FLAG_SET_DEFAULT(OptoLoopAlignment, 4);
72 }
73 #ifdef _LP64
74 // 32-bit oops don't make sense for the 64-bit VM on sparc
75 // since the 32-bit VM has the same registers and smaller objects.
76 Universe::set_narrow_oop_shift(LogMinObjAlignmentInBytes);
77 Universe::set_narrow_klass_shift(LogKlassAlignmentInBytes);
78 #endif // _LP64
79 #ifdef COMPILER2
80 // Indirect branch is the same cost as direct
81 if (FLAG_IS_DEFAULT(UseJumpTables)) {
82 FLAG_SET_DEFAULT(UseJumpTables, true);
83 }
84 // Single-issue, so entry and loop tops are
85 // aligned on a single instruction boundary
86 if (FLAG_IS_DEFAULT(InteriorEntryAlignment)) {
87 FLAG_SET_DEFAULT(InteriorEntryAlignment, 4);
88 }
89 if (is_niagara_plus()) {
90 if (has_blk_init() && UseTLAB &&
91 FLAG_IS_DEFAULT(AllocatePrefetchInstr)) {
92 // Use BIS instruction for TLAB allocation prefetch.
93 FLAG_SET_DEFAULT(AllocatePrefetchInstr, 1);
94 }
95 if (FLAG_IS_DEFAULT(AllocatePrefetchDistance)) {
96 if (AllocatePrefetchInstr == 0) {
97 // Use different prefetch distance without BIS
98 FLAG_SET_DEFAULT(AllocatePrefetchDistance, 256);
99 } else {
100 // Use smaller prefetch distance with BIS
101 FLAG_SET_DEFAULT(AllocatePrefetchDistance, 64);
102 }
103 }
104 if (is_T4()) {
105 // Double number of prefetched cache lines on T4
106 // since L2 cache line size is smaller (32 bytes).
107 if (FLAG_IS_DEFAULT(AllocatePrefetchLines)) {
108 FLAG_SET_ERGO(intx, AllocatePrefetchLines, AllocatePrefetchLines*2);
109 }
110 if (FLAG_IS_DEFAULT(AllocateInstancePrefetchLines)) {
111 FLAG_SET_ERGO(intx, AllocateInstancePrefetchLines, AllocateInstancePrefetchLines*2);
112 }
113 }
114 }
115
116 if (AllocatePrefetchInstr == 1) {
117 // Use allocation prefetch style 3 because BIS instructions
118 // require aligned memory addresses.
119 FLAG_SET_DEFAULT(AllocatePrefetchStyle, 3);
120 }
121 #endif /* COMPILER2 */
122 }
123
124 // Use hardware population count instruction if available.
125 if (has_hardware_popc()) {
126 if (FLAG_IS_DEFAULT(UsePopCountInstruction)) {
127 FLAG_SET_DEFAULT(UsePopCountInstruction, true);
128 }
129 } else if (UsePopCountInstruction) {
130 warning("POPC instruction is not available on this CPU");
131 FLAG_SET_DEFAULT(UsePopCountInstruction, false);
132 }
133
134 // T4 and newer Sparc cpus have new compare and branch instruction.
135 if (has_cbcond()) {
136 if (FLAG_IS_DEFAULT(UseCBCond)) {
137 FLAG_SET_DEFAULT(UseCBCond, true);
138 }
139 } else if (UseCBCond) {
140 warning("CBCOND instruction is not available on this CPU");
141 FLAG_SET_DEFAULT(UseCBCond, false);
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