1 /*
2 * Copyright (c) 1997, 2016, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #include "precompiled.hpp"
26 #include "asm/macroAssembler.inline.hpp"
27 #include "logging/log.hpp"
28 #include "memory/resourceArea.hpp"
29 #include "runtime/java.hpp"
30 #include "runtime/os.hpp"
31 #include "runtime/stubCodeGenerator.hpp"
32 #include "vm_version_sparc.hpp"
33
34 unsigned int VM_Version::_L2_data_cache_line_size = 0;
35
36 void VM_Version::initialize() {
37 assert(_features != 0, "System pre-initialization is not complete.");
38 guarantee(VM_Version::has_v9(), "only SPARC v9 is supported");
39
40 PrefetchCopyIntervalInBytes = prefetch_copy_interval_in_bytes();
41 PrefetchScanIntervalInBytes = prefetch_scan_interval_in_bytes();
42 PrefetchFieldsAhead = prefetch_fields_ahead();
43
44 // Allocation prefetch settings
45 intx cache_line_size = prefetch_data_size();
46 if( cache_line_size > AllocatePrefetchStepSize )
47 AllocatePrefetchStepSize = cache_line_size;
48
49 AllocatePrefetchDistance = allocate_prefetch_distance();
50 AllocatePrefetchStyle = allocate_prefetch_style();
51
52 if (AllocatePrefetchStyle == 3 && !has_blk_init()) {
53 warning("BIS instructions are not available on this CPU");
54 FLAG_SET_DEFAULT(AllocatePrefetchStyle, 1);
55 }
56
57 UseSSE = 0; // Only on x86 and x64
58
59 _supports_cx8 = has_v9();
60 _supports_atomic_getset4 = true; // swap instruction
61
62 if (is_niagara()) {
63 // Indirect branch is the same cost as direct
64 if (FLAG_IS_DEFAULT(UseInlineCaches)) {
65 FLAG_SET_DEFAULT(UseInlineCaches, false);
66 }
67 // Align loops on a single instruction boundary.
68 if (FLAG_IS_DEFAULT(OptoLoopAlignment)) {
69 FLAG_SET_DEFAULT(OptoLoopAlignment, 4);
70 }
71 #ifdef _LP64
72 // 32-bit oops don't make sense for the 64-bit VM on sparc
73 // since the 32-bit VM has the same registers and smaller objects.
74 Universe::set_narrow_oop_shift(LogMinObjAlignmentInBytes);
75 Universe::set_narrow_klass_shift(LogKlassAlignmentInBytes);
76 #endif // _LP64
77 #ifdef COMPILER2
78 // Indirect branch is the same cost as direct
79 if (FLAG_IS_DEFAULT(UseJumpTables)) {
80 FLAG_SET_DEFAULT(UseJumpTables, true);
81 }
82 // Single-issue, so entry and loop tops are
83 // aligned on a single instruction boundary
84 if (FLAG_IS_DEFAULT(InteriorEntryAlignment)) {
85 FLAG_SET_DEFAULT(InteriorEntryAlignment, 4);
86 }
87 if (is_niagara_plus()) {
88 if (has_blk_init() && UseTLAB &&
89 FLAG_IS_DEFAULT(AllocatePrefetchInstr)) {
90 // Use BIS instruction for TLAB allocation prefetch.
91 FLAG_SET_ERGO(intx, AllocatePrefetchInstr, 1);
92 if (FLAG_IS_DEFAULT(AllocatePrefetchStyle)) {
93 FLAG_SET_ERGO(intx, AllocatePrefetchStyle, 3);
94 }
95 if (FLAG_IS_DEFAULT(AllocatePrefetchDistance)) {
96 // Use smaller prefetch distance with BIS
97 FLAG_SET_DEFAULT(AllocatePrefetchDistance, 64);
98 }
99 }
100 if (is_T4()) {
101 // Double number of prefetched cache lines on T4
102 // since L2 cache line size is smaller (32 bytes).
103 if (FLAG_IS_DEFAULT(AllocatePrefetchLines)) {
104 FLAG_SET_ERGO(intx, AllocatePrefetchLines, AllocatePrefetchLines*2);
105 }
106 if (FLAG_IS_DEFAULT(AllocateInstancePrefetchLines)) {
107 FLAG_SET_ERGO(intx, AllocateInstancePrefetchLines, AllocateInstancePrefetchLines*2);
108 }
109 }
110 if (AllocatePrefetchStyle != 3 && FLAG_IS_DEFAULT(AllocatePrefetchDistance)) {
111 // Use different prefetch distance without BIS
112 FLAG_SET_DEFAULT(AllocatePrefetchDistance, 256);
113 }
114 if (AllocatePrefetchInstr == 1) {
115 // Need extra space at the end of TLAB for BIS, otherwise prefetching
116 // instructions will fault (due to accessing memory outside of heap).
117 // The amount of space is the max of the number of lines to
118 // prefetch for array and for instance allocations. (Extra space must be
119 // reserved to accomodate both types of allocations.)
120
121 // +1 for rounding up to next cache line, +1 to be safe
122 int lines = MAX2(AllocatePrefetchLines, AllocateInstancePrefetchLines) + 2;
123 int step_size = AllocatePrefetchStepSize;
124 int distance = AllocatePrefetchDistance;
125 _reserve_for_allocation_prefetch = (distance + step_size*lines)/(int)HeapWordSize;
126 }
127 }
128 #endif
129 }
130
131 // Use hardware population count instruction if available.
132 if (has_hardware_popc()) {
133 if (FLAG_IS_DEFAULT(UsePopCountInstruction)) {
134 FLAG_SET_DEFAULT(UsePopCountInstruction, true);
135 }
136 } else if (UsePopCountInstruction) {
137 warning("POPC instruction is not available on this CPU");
138 FLAG_SET_DEFAULT(UsePopCountInstruction, false);
139 }
140
141 // T4 and newer Sparc cpus have new compare and branch instruction.
142 if (has_cbcond()) {
143 if (FLAG_IS_DEFAULT(UseCBCond)) {
144 FLAG_SET_DEFAULT(UseCBCond, true);
145 }
146 } else if (UseCBCond) {
147 warning("CBCOND instruction is not available on this CPU");
148 FLAG_SET_DEFAULT(UseCBCond, false);
149 }
150
151 assert(BlockZeroingLowLimit > 0, "invalid value");
152 if (has_block_zeroing() && cache_line_size > 0) {
153 if (FLAG_IS_DEFAULT(UseBlockZeroing)) {
154 FLAG_SET_DEFAULT(UseBlockZeroing, true);
155 }
156 } else if (UseBlockZeroing) {
157 warning("BIS zeroing instructions are not available on this CPU");
158 FLAG_SET_DEFAULT(UseBlockZeroing, false);
159 }
160
161 assert(BlockCopyLowLimit > 0, "invalid value");
162 if (has_block_zeroing() && cache_line_size > 0) { // has_blk_init() && is_T4(): core's local L2 cache
163 if (FLAG_IS_DEFAULT(UseBlockCopy)) {
164 FLAG_SET_DEFAULT(UseBlockCopy, true);
165 }
166 } else if (UseBlockCopy) {
167 warning("BIS instructions are not available or expensive on this CPU");
168 FLAG_SET_DEFAULT(UseBlockCopy, false);
169 }
170
171 #ifdef COMPILER2
172 // T4 and newer Sparc cpus have fast RDPC.
173 if (has_fast_rdpc() && FLAG_IS_DEFAULT(UseRDPCForConstantTableBase)) {
174 FLAG_SET_DEFAULT(UseRDPCForConstantTableBase, true);
175 }
176
177 // Currently not supported anywhere.
178 FLAG_SET_DEFAULT(UseFPUForSpilling, false);
179
180 MaxVectorSize = 8;
181
182 assert((InteriorEntryAlignment % relocInfo::addr_unit()) == 0, "alignment is not a multiple of NOP size");
183 #endif
184
185 assert((CodeEntryAlignment % relocInfo::addr_unit()) == 0, "alignment is not a multiple of NOP size");
186 assert((OptoLoopAlignment % relocInfo::addr_unit()) == 0, "alignment is not a multiple of NOP size");
187
188 char buf[512];
189 jio_snprintf(buf, sizeof(buf), "%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s",
190 (has_v9() ? ", v9" : (has_v8() ? ", v8" : "")),
191 (has_hardware_popc() ? ", popc" : ""),
192 (has_vis1() ? ", vis1" : ""),
193 (has_vis2() ? ", vis2" : ""),
194 (has_vis3() ? ", vis3" : ""),
195 (has_blk_init() ? ", blk_init" : ""),
196 (has_cbcond() ? ", cbcond" : ""),
197 (has_aes() ? ", aes" : ""),
198 (has_sha1() ? ", sha1" : ""),
199 (has_sha256() ? ", sha256" : ""),
200 (has_sha512() ? ", sha512" : ""),
201 (has_crc32c() ? ", crc32c" : ""),
202 (is_ultra3() ? ", ultra3" : ""),
203 (is_sun4v() ? ", sun4v" : ""),
204 (is_niagara_plus() ? ", niagara_plus" : (is_niagara() ? ", niagara" : "")),
205 (is_sparc64() ? ", sparc64" : ""),
206 (!has_hardware_mul32() ? ", no-mul32" : ""),
207 (!has_hardware_div32() ? ", no-div32" : ""),
208 (!has_hardware_fsmuld() ? ", no-fsmuld" : ""));
209
210 // buf is started with ", " or is empty
211 _features_string = os::strdup(strlen(buf) > 2 ? buf + 2 : buf);
212
213 // UseVIS is set to the smallest of what hardware supports and what
214 // the command line requires. I.e., you cannot set UseVIS to 3 on
215 // older UltraSparc which do not support it.
216 if (UseVIS > 3) UseVIS=3;
217 if (UseVIS < 0) UseVIS=0;
218 if (!has_vis3()) // Drop to 2 if no VIS3 support
219 UseVIS = MIN2((intx)2,UseVIS);
220 if (!has_vis2()) // Drop to 1 if no VIS2 support
221 UseVIS = MIN2((intx)1,UseVIS);
222 if (!has_vis1()) // Drop to 0 if no VIS1 support
223 UseVIS = 0;
224
225 // SPARC T4 and above should have support for AES instructions
226 if (has_aes()) {
227 if (FLAG_IS_DEFAULT(UseAES)) {
228 FLAG_SET_DEFAULT(UseAES, true);
229 }
230 if (!UseAES) {
231 if (UseAESIntrinsics && !FLAG_IS_DEFAULT(UseAESIntrinsics)) {
232 warning("AES intrinsics require UseAES flag to be enabled. Intrinsics will be disabled.");
233 }
234 FLAG_SET_DEFAULT(UseAESIntrinsics, false);
235 } else {
236 // The AES intrinsic stubs require AES instruction support (of course)
237 // but also require VIS3 mode or higher for instructions it use.
238 if (UseVIS > 2) {
239 if (FLAG_IS_DEFAULT(UseAESIntrinsics)) {
240 FLAG_SET_DEFAULT(UseAESIntrinsics, true);
241 }
242 } else {
243 if (UseAESIntrinsics && !FLAG_IS_DEFAULT(UseAESIntrinsics)) {
244 warning("SPARC AES intrinsics require VIS3 instructions. Intrinsics will be disabled.");
245 }
246 FLAG_SET_DEFAULT(UseAESIntrinsics, false);
247 }
248 }
249 } else if (UseAES || UseAESIntrinsics) {
250 if (UseAES && !FLAG_IS_DEFAULT(UseAES)) {
251 warning("AES instructions are not available on this CPU");
252 FLAG_SET_DEFAULT(UseAES, false);
253 }
254 if (UseAESIntrinsics && !FLAG_IS_DEFAULT(UseAESIntrinsics)) {
255 warning("AES intrinsics are not available on this CPU");
256 FLAG_SET_DEFAULT(UseAESIntrinsics, false);
257 }
258 }
259
260 if (UseAESCTRIntrinsics) {
261 warning("AES/CTR intrinsics are not available on this CPU");
262 FLAG_SET_DEFAULT(UseAESCTRIntrinsics, false);
263 }
264
265 // GHASH/GCM intrinsics
266 if (has_vis3() && (UseVIS > 2)) {
267 if (FLAG_IS_DEFAULT(UseGHASHIntrinsics)) {
268 UseGHASHIntrinsics = true;
269 }
270 } else if (UseGHASHIntrinsics) {
271 if (!FLAG_IS_DEFAULT(UseGHASHIntrinsics))
272 warning("GHASH intrinsics require VIS3 instruction support. Intrinsics will be disabled");
273 FLAG_SET_DEFAULT(UseGHASHIntrinsics, false);
274 }
275
276 // SHA1, SHA256, and SHA512 instructions were added to SPARC T-series at different times
277 if (has_sha1() || has_sha256() || has_sha512()) {
278 if (UseVIS > 0) { // SHA intrinsics use VIS1 instructions
279 if (FLAG_IS_DEFAULT(UseSHA)) {
280 FLAG_SET_DEFAULT(UseSHA, true);
281 }
282 } else {
283 if (UseSHA) {
284 warning("SPARC SHA intrinsics require VIS1 instruction support. Intrinsics will be disabled.");
285 FLAG_SET_DEFAULT(UseSHA, false);
286 }
287 }
288 } else if (UseSHA) {
289 warning("SHA instructions are not available on this CPU");
290 FLAG_SET_DEFAULT(UseSHA, false);
291 }
292
293 if (UseSHA && has_sha1()) {
294 if (FLAG_IS_DEFAULT(UseSHA1Intrinsics)) {
295 FLAG_SET_DEFAULT(UseSHA1Intrinsics, true);
296 }
297 } else if (UseSHA1Intrinsics) {
298 warning("Intrinsics for SHA-1 crypto hash functions not available on this CPU.");
299 FLAG_SET_DEFAULT(UseSHA1Intrinsics, false);
300 }
301
302 if (UseSHA && has_sha256()) {
303 if (FLAG_IS_DEFAULT(UseSHA256Intrinsics)) {
304 FLAG_SET_DEFAULT(UseSHA256Intrinsics, true);
305 }
306 } else if (UseSHA256Intrinsics) {
307 warning("Intrinsics for SHA-224 and SHA-256 crypto hash functions not available on this CPU.");
308 FLAG_SET_DEFAULT(UseSHA256Intrinsics, false);
309 }
310
311 if (UseSHA && has_sha512()) {
312 if (FLAG_IS_DEFAULT(UseSHA512Intrinsics)) {
313 FLAG_SET_DEFAULT(UseSHA512Intrinsics, true);
314 }
315 } else if (UseSHA512Intrinsics) {
316 warning("Intrinsics for SHA-384 and SHA-512 crypto hash functions not available on this CPU.");
317 FLAG_SET_DEFAULT(UseSHA512Intrinsics, false);
318 }
319
320 if (!(UseSHA1Intrinsics || UseSHA256Intrinsics || UseSHA512Intrinsics)) {
321 FLAG_SET_DEFAULT(UseSHA, false);
322 }
323
324 // SPARC T4 and above should have support for CRC32C instruction
325 if (has_crc32c()) {
326 if (UseVIS > 2) { // CRC32C intrinsics use VIS3 instructions
327 if (FLAG_IS_DEFAULT(UseCRC32CIntrinsics)) {
328 FLAG_SET_DEFAULT(UseCRC32CIntrinsics, true);
329 }
330 } else {
331 if (UseCRC32CIntrinsics) {
332 warning("SPARC CRC32C intrinsics require VIS3 instruction support. Intrinsics will be disabled.");
333 FLAG_SET_DEFAULT(UseCRC32CIntrinsics, false);
334 }
335 }
336 } else if (UseCRC32CIntrinsics) {
337 warning("CRC32C instruction is not available on this CPU");
338 FLAG_SET_DEFAULT(UseCRC32CIntrinsics, false);
339 }
340
341 if (UseVIS > 2) {
342 if (FLAG_IS_DEFAULT(UseAdler32Intrinsics)) {
343 FLAG_SET_DEFAULT(UseAdler32Intrinsics, true);
344 }
345 } else if (UseAdler32Intrinsics) {
346 warning("SPARC Adler32 intrinsics require VIS3 instruction support. Intrinsics will be disabled.");
347 FLAG_SET_DEFAULT(UseAdler32Intrinsics, false);
348 }
349
350 if (UseVIS > 2) {
351 if (FLAG_IS_DEFAULT(UseCRC32Intrinsics)) {
352 FLAG_SET_DEFAULT(UseCRC32Intrinsics, true);
353 }
354 } else if (UseCRC32Intrinsics) {
355 warning("SPARC CRC32 intrinsics require VIS3 insructions support. Intriniscs will be disabled");
356 FLAG_SET_DEFAULT(UseCRC32Intrinsics, false);
357 }
358
359 if (UseVectorizedMismatchIntrinsic) {
360 warning("UseVectorizedMismatchIntrinsic specified, but not available on this CPU.");
361 FLAG_SET_DEFAULT(UseVectorizedMismatchIntrinsic, false);
362 }
363
364 if (FLAG_IS_DEFAULT(ContendedPaddingWidth) &&
365 (cache_line_size > ContendedPaddingWidth))
366 ContendedPaddingWidth = cache_line_size;
367
368 // This machine does not allow unaligned memory accesses
369 if (UseUnalignedAccesses) {
370 if (!FLAG_IS_DEFAULT(UseUnalignedAccesses))
371 warning("Unaligned memory access is not available on this CPU");
372 FLAG_SET_DEFAULT(UseUnalignedAccesses, false);
373 }
374
375 if (log_is_enabled(Info, os, cpu)) {
376 ResourceMark rm;
377 outputStream* log = Log(os, cpu)::info_stream();
378 log->print_cr("L1 data cache line size: %u", L1_data_cache_line_size());
379 log->print_cr("L2 data cache line size: %u", L2_data_cache_line_size());
380 log->print("Allocation");
381 if (AllocatePrefetchStyle <= 0) {
382 log->print(": no prefetching");
383 } else {
384 log->print(" prefetching: ");
385 if (AllocatePrefetchInstr == 0) {
386 log->print("PREFETCH");
387 } else if (AllocatePrefetchInstr == 1) {
388 log->print("BIS");
389 }
390 if (AllocatePrefetchLines > 1) {
391 log->print_cr(" at distance %d, %d lines of %d bytes", (int) AllocatePrefetchDistance, (int) AllocatePrefetchLines, (int) AllocatePrefetchStepSize);
392 } else {
393 log->print_cr(" at distance %d, one line of %d bytes", (int) AllocatePrefetchDistance, (int) AllocatePrefetchStepSize);
394 }
395 }
396 if (PrefetchCopyIntervalInBytes > 0) {
397 log->print_cr("PrefetchCopyIntervalInBytes %d", (int) PrefetchCopyIntervalInBytes);
398 }
399 if (PrefetchScanIntervalInBytes > 0) {
400 log->print_cr("PrefetchScanIntervalInBytes %d", (int) PrefetchScanIntervalInBytes);
401 }
402 if (PrefetchFieldsAhead > 0) {
403 log->print_cr("PrefetchFieldsAhead %d", (int) PrefetchFieldsAhead);
404 }
405 if (ContendedPaddingWidth > 0) {
406 log->print_cr("ContendedPaddingWidth %d", (int) ContendedPaddingWidth);
407 }
408 }
409 }
410
411 void VM_Version::print_features() {
412 tty->print_cr("Version:%s", _features);
413 }
414
415 int VM_Version::determine_features() {
416 if (UseV8InstrsOnly) {
417 log_info(os, cpu)("Version is Forced-V8");
418 return generic_v8_m;
419 }
420
421 int features = platform_features(unknown_m); // platform_features() is os_arch specific
422
423 if (features == unknown_m) {
424 features = generic_v9_m;
425 log_info(os)("Cannot recognize SPARC version. Default to V9");
426 }
427
428 assert(is_T_family(features) == is_niagara(features), "Niagara should be T series");
429 if (UseNiagaraInstrs) { // Force code generation for Niagara
430 if (is_T_family(features)) {
431 // Happy to accomodate...
432 } else {
433 log_info(os, cpu)("Version is Forced-Niagara");
434 features |= T_family_m;
435 }
436 } else {
437 if (is_T_family(features) && !FLAG_IS_DEFAULT(UseNiagaraInstrs)) {
438 log_info(os, cpu)("Version is Forced-Not-Niagara");
439 features &= ~(T_family_m | T1_model_m);
440 } else {
441 // Happy to accomodate...
442 }
443 }
444
445 return features;
446 }
447
448 static uint64_t saved_features = 0;
449
450 void VM_Version::allow_all() {
451 saved_features = _features;
452 _features = all_features_m;
453 }
454
455 void VM_Version::revert() {
456 _features = saved_features;
457 }
458
459 unsigned int VM_Version::calc_parallel_worker_threads() {
460 unsigned int result;
461 if (is_M_series()) {
462 // for now, use same gc thread calculation for M-series as for niagara-plus
463 // in future, we may want to tweak parameters for nof_parallel_worker_thread
464 result = nof_parallel_worker_threads(5, 16, 8);
465 } else if (is_niagara_plus()) {
466 result = nof_parallel_worker_threads(5, 16, 8);
467 } else {
468 result = nof_parallel_worker_threads(5, 8, 8);
469 }
470 return result;
471 }
472
473
474 int VM_Version::parse_features(const char* implementation) {
475 int features = unknown_m;
476 // Convert to UPPER case before compare.
477 char* impl = os::strdup_check_oom(implementation);
478
479 for (int i = 0; impl[i] != 0; i++)
480 impl[i] = (char)toupper((uint)impl[i]);
481
482 if (strstr(impl, "SPARC64") != NULL) {
483 features |= sparc64_family_m;
484 } else if (strstr(impl, "SPARC-M") != NULL) {
485 // M-series SPARC is based on T-series.
486 features |= (M_family_m | T_family_m);
487 } else if (strstr(impl, "SPARC-T") != NULL) {
488 features |= T_family_m;
489 if (strstr(impl, "SPARC-T1") != NULL) {
490 features |= T1_model_m;
491 }
492 } else {
493 if (strstr(impl, "SPARC") == NULL) {
494 #ifndef PRODUCT
495 // kstat on Solaris 8 virtual machines (branded zones)
496 // returns "(unsupported)" implementation. Solaris 8 is not
497 // supported anymore, but include this check to be on the
498 // safe side.
499 warning("Can't parse CPU implementation = '%s', assume generic SPARC", impl);
500 #endif
501 }
502 }
503 os::free((void*)impl);
504 return features;
505 }