src/share/vm/opto/macro.cpp
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*** old/src/share/vm/opto/macro.cpp Tue Apr 26 13:47:37 2016
--- new/src/share/vm/opto/macro.cpp Tue Apr 26 13:47:37 2016
*** 1895,1905 ****
--- 1895,1905 ----
// adding prefetches
pf_phi_abio->init_req( fall_in_path, i_o );
Node *prefetch_adr;
Node *prefetch;
! uint lines = AllocatePrefetchDistance / AllocatePrefetchStepSize;
! uint lines = (length != NULL) ? AllocatePrefetchLines : AllocateInstancePrefetchLines;
uint step_size = AllocatePrefetchStepSize;
uint distance = 0;
for ( uint i = 0; i < lines; i++ ) {
prefetch_adr = new AddPNode( old_pf_wm, new_pf_wmt,
*** 1924,1939 ****
--- 1924,1935 ----
needgc_false = pf_region;
contended_phi_rawmem = pf_phi_rawmem;
i_o = pf_phi_abio;
} else if( UseTLAB && AllocatePrefetchStyle == 3 ) {
! // Insert a prefetch instruction for each allocation.
! // This code is used for Sparc with BIS.
Node *pf_region = new RegionNode(3);
Node *pf_phi_rawmem = new PhiNode( pf_region, Type::MEMORY,
TypeRawPtr::BOTTOM );
transform_later(pf_region);
! // This code is used for SPARC with BIS.
// Generate several prefetch instructions.
uint lines = (length != NULL) ? AllocatePrefetchLines : AllocateInstancePrefetchLines;
uint step_size = AllocatePrefetchStepSize;
uint distance = AllocatePrefetchDistance;
*** 1942,1952 ****
--- 1938,1949 ----
Node *cache_adr = new AddPNode(old_eden_top, old_eden_top,
_igvn.MakeConX(distance));
transform_later(cache_adr);
cache_adr = new CastP2XNode(needgc_false, cache_adr);
transform_later(cache_adr);
Node* mask = _igvn.MakeConX(~(intptr_t)(step_size-1));
+ // BIS instructions require 8-byte aligned addresses
+ Node* mask = _igvn.MakeConX(~(intptr_t)(wordSize - 1));
cache_adr = new AndXNode(cache_adr, mask);
transform_later(cache_adr);
cache_adr = new CastX2PNode(cache_adr);
transform_later(cache_adr);
src/share/vm/opto/macro.cpp
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