1 /*
2 * Copyright (c) 1997, 2016, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #include "precompiled.hpp"
26 #include "asm/macroAssembler.inline.hpp"
27 #include "logging/log.hpp"
28 #include "memory/resourceArea.hpp"
29 #include "runtime/java.hpp"
30 #include "runtime/os.hpp"
31 #include "runtime/stubCodeGenerator.hpp"
32 #include "vm_version_sparc.hpp"
33
34 unsigned int VM_Version::_L2_data_cache_line_size = 0;
35
36 void VM_Version::initialize() {
37 assert(_features != 0, "System pre-initialization is not complete.");
38 guarantee(VM_Version::has_v9(), "only SPARC v9 is supported");
39
40 PrefetchCopyIntervalInBytes = prefetch_copy_interval_in_bytes();
41 PrefetchScanIntervalInBytes = prefetch_scan_interval_in_bytes();
42 PrefetchFieldsAhead = prefetch_fields_ahead();
43
44 // Allocation prefetch settings
45 intx cache_line_size = prefetch_data_size();
46 if( cache_line_size > AllocatePrefetchStepSize )
47 AllocatePrefetchStepSize = cache_line_size;
48
49 AllocatePrefetchDistance = allocate_prefetch_distance();
50 AllocatePrefetchStyle = allocate_prefetch_style();
51
52 if (!has_blk_init()) {
53 if (AllocatePrefetchStyle == 3) {
54 warning("BIS instructions required for AllocatePrefetchStyle 3 unavailable");
55 FLAG_SET_DEFAULT(AllocatePrefetchStyle, 1);
56 }
57 if (AllocatePrefetchInstr == 1) {
58 warning("BIS instructions required for AllocatePrefetchInstr 1 unavailable");
59 FLAG_SET_DEFAULT(AllocatePrefetchInstr, 0);
60 }
61 }
62
63 UseSSE = 0; // Only on x86 and x64
64
65 _supports_cx8 = has_v9();
66 _supports_atomic_getset4 = true; // swap instruction
67
68 if (is_niagara()) {
69 // Indirect branch is the same cost as direct
70 if (FLAG_IS_DEFAULT(UseInlineCaches)) {
71 FLAG_SET_DEFAULT(UseInlineCaches, false);
72 }
73 // Align loops on a single instruction boundary.
74 if (FLAG_IS_DEFAULT(OptoLoopAlignment)) {
75 FLAG_SET_DEFAULT(OptoLoopAlignment, 4);
76 }
77 #ifdef _LP64
78 // 32-bit oops don't make sense for the 64-bit VM on sparc
79 // since the 32-bit VM has the same registers and smaller objects.
80 Universe::set_narrow_oop_shift(LogMinObjAlignmentInBytes);
81 Universe::set_narrow_klass_shift(LogKlassAlignmentInBytes);
82 #endif // _LP64
83 #ifdef COMPILER2
84 // Indirect branch is the same cost as direct
85 if (FLAG_IS_DEFAULT(UseJumpTables)) {
86 FLAG_SET_DEFAULT(UseJumpTables, true);
87 }
88 // Single-issue, so entry and loop tops are
89 // aligned on a single instruction boundary
90 if (FLAG_IS_DEFAULT(InteriorEntryAlignment)) {
91 FLAG_SET_DEFAULT(InteriorEntryAlignment, 4);
92 }
93 if (is_niagara_plus()) {
94 if (has_blk_init() && UseTLAB &&
95 FLAG_IS_DEFAULT(AllocatePrefetchInstr)) {
96 // Use BIS instruction for TLAB allocation prefetch.
97 FLAG_SET_DEFAULT(AllocatePrefetchInstr, 1);
98 }
99 if (FLAG_IS_DEFAULT(AllocatePrefetchDistance)) {
100 if (AllocatePrefetchInstr == 0) {
101 // Use different prefetch distance without BIS
102 FLAG_SET_DEFAULT(AllocatePrefetchDistance, 256);
103 } else {
104 // Use smaller prefetch distance with BIS
105 FLAG_SET_DEFAULT(AllocatePrefetchDistance, 64);
106 }
107 }
108 if (is_T4()) {
109 // Double number of prefetched cache lines on T4
110 // since L2 cache line size is smaller (32 bytes).
111 if (FLAG_IS_DEFAULT(AllocatePrefetchLines)) {
112 FLAG_SET_ERGO(intx, AllocatePrefetchLines, AllocatePrefetchLines*2);
113 }
114 if (FLAG_IS_DEFAULT(AllocateInstancePrefetchLines)) {
115 FLAG_SET_ERGO(intx, AllocateInstancePrefetchLines, AllocateInstancePrefetchLines*2);
116 }
117 }
118 }
119 if (AllocatePrefetchInstr == 1) {
120 // Use allocation prefetch style 3 because BIS instructions
121 // require aligned memory addresses.
122 FLAG_SET_DEFAULT(AllocatePrefetchStyle, 3);
123
124 // Need extra space at the end of TLAB for BIS, otherwise prefetching
125 // instructions will fault (due to accessing memory outside of heap).
126 // The amount of space is the max of the number of lines to
127 // prefetch for array and for instance allocations. (Extra space must be
128 // reserved to accomodate both types of allocations.)
129
130 // +1 for rounding up to next cache line, +1 to be safe
131 int lines = MAX2(AllocatePrefetchLines, AllocateInstancePrefetchLines) + 2;
132 int step_size = AllocatePrefetchStepSize;
133 int distance = AllocatePrefetchDistance;
134 _reserve_for_allocation_prefetch = (distance + step_size*lines)/(int)HeapWordSize;
135 }
136 #endif /* COMPILER2 */
137 }
138
139 // Use hardware population count instruction if available.
140 if (has_hardware_popc()) {
141 if (FLAG_IS_DEFAULT(UsePopCountInstruction)) {
142 FLAG_SET_DEFAULT(UsePopCountInstruction, true);
143 }
144 } else if (UsePopCountInstruction) {
145 warning("POPC instruction is not available on this CPU");
146 FLAG_SET_DEFAULT(UsePopCountInstruction, false);
147 }
148
149 // T4 and newer Sparc cpus have new compare and branch instruction.
150 if (has_cbcond()) {
151 if (FLAG_IS_DEFAULT(UseCBCond)) {
152 FLAG_SET_DEFAULT(UseCBCond, true);
153 }
154 } else if (UseCBCond) {
155 warning("CBCOND instruction is not available on this CPU");
156 FLAG_SET_DEFAULT(UseCBCond, false);
157 }
158
159 assert(BlockZeroingLowLimit > 0, "invalid value");
160 if (has_block_zeroing() && cache_line_size > 0) {
161 if (FLAG_IS_DEFAULT(UseBlockZeroing)) {
162 FLAG_SET_DEFAULT(UseBlockZeroing, true);
163 }
164 } else if (UseBlockZeroing) {
165 warning("BIS zeroing instructions are not available on this CPU");
166 FLAG_SET_DEFAULT(UseBlockZeroing, false);
167 }
168
169 assert(BlockCopyLowLimit > 0, "invalid value");
170 if (has_block_zeroing() && cache_line_size > 0) { // has_blk_init() && is_T4(): core's local L2 cache
171 if (FLAG_IS_DEFAULT(UseBlockCopy)) {
172 FLAG_SET_DEFAULT(UseBlockCopy, true);
173 }
174 } else if (UseBlockCopy) {
175 warning("BIS instructions are not available or expensive on this CPU");
176 FLAG_SET_DEFAULT(UseBlockCopy, false);
177 }
178
179 #ifdef COMPILER2
180 // T4 and newer Sparc cpus have fast RDPC.
181 if (has_fast_rdpc() && FLAG_IS_DEFAULT(UseRDPCForConstantTableBase)) {
182 FLAG_SET_DEFAULT(UseRDPCForConstantTableBase, true);
183 }
184
185 // Currently not supported anywhere.
186 FLAG_SET_DEFAULT(UseFPUForSpilling, false);
187
188 MaxVectorSize = 8;
189
190 assert((InteriorEntryAlignment % relocInfo::addr_unit()) == 0, "alignment is not a multiple of NOP size");
191 #endif
192
193 assert((CodeEntryAlignment % relocInfo::addr_unit()) == 0, "alignment is not a multiple of NOP size");
194 assert((OptoLoopAlignment % relocInfo::addr_unit()) == 0, "alignment is not a multiple of NOP size");
195
196 char buf[512];
197 jio_snprintf(buf, sizeof(buf), "%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s",
198 (has_v9() ? ", v9" : (has_v8() ? ", v8" : "")),
199 (has_hardware_popc() ? ", popc" : ""),
200 (has_vis1() ? ", vis1" : ""),
201 (has_vis2() ? ", vis2" : ""),
202 (has_vis3() ? ", vis3" : ""),
203 (has_blk_init() ? ", blk_init" : ""),
204 (has_cbcond() ? ", cbcond" : ""),
205 (has_aes() ? ", aes" : ""),
206 (has_sha1() ? ", sha1" : ""),
207 (has_sha256() ? ", sha256" : ""),
208 (has_sha512() ? ", sha512" : ""),
209 (has_crc32c() ? ", crc32c" : ""),
210 (is_ultra3() ? ", ultra3" : ""),
211 (is_sun4v() ? ", sun4v" : ""),
212 (is_niagara_plus() ? ", niagara_plus" : (is_niagara() ? ", niagara" : "")),
213 (is_sparc64() ? ", sparc64" : ""),
214 (!has_hardware_mul32() ? ", no-mul32" : ""),
215 (!has_hardware_div32() ? ", no-div32" : ""),
216 (!has_hardware_fsmuld() ? ", no-fsmuld" : ""));
217
218 // buf is started with ", " or is empty
219 _features_string = os::strdup(strlen(buf) > 2 ? buf + 2 : buf);
220
221 // UseVIS is set to the smallest of what hardware supports and what
222 // the command line requires. I.e., you cannot set UseVIS to 3 on
223 // older UltraSparc which do not support it.
224 if (UseVIS > 3) UseVIS=3;
225 if (UseVIS < 0) UseVIS=0;
226 if (!has_vis3()) // Drop to 2 if no VIS3 support
227 UseVIS = MIN2((intx)2,UseVIS);
228 if (!has_vis2()) // Drop to 1 if no VIS2 support
229 UseVIS = MIN2((intx)1,UseVIS);
230 if (!has_vis1()) // Drop to 0 if no VIS1 support
231 UseVIS = 0;
232
233 // SPARC T4 and above should have support for AES instructions
234 if (has_aes()) {
235 if (FLAG_IS_DEFAULT(UseAES)) {
236 FLAG_SET_DEFAULT(UseAES, true);
237 }
238 if (!UseAES) {
239 if (UseAESIntrinsics && !FLAG_IS_DEFAULT(UseAESIntrinsics)) {
240 warning("AES intrinsics require UseAES flag to be enabled. Intrinsics will be disabled.");
241 }
242 FLAG_SET_DEFAULT(UseAESIntrinsics, false);
243 } else {
244 // The AES intrinsic stubs require AES instruction support (of course)
245 // but also require VIS3 mode or higher for instructions it use.
246 if (UseVIS > 2) {
247 if (FLAG_IS_DEFAULT(UseAESIntrinsics)) {
248 FLAG_SET_DEFAULT(UseAESIntrinsics, true);
249 }
250 } else {
251 if (UseAESIntrinsics && !FLAG_IS_DEFAULT(UseAESIntrinsics)) {
252 warning("SPARC AES intrinsics require VIS3 instructions. Intrinsics will be disabled.");
253 }
254 FLAG_SET_DEFAULT(UseAESIntrinsics, false);
255 }
256 }
257 } else if (UseAES || UseAESIntrinsics) {
258 if (UseAES && !FLAG_IS_DEFAULT(UseAES)) {
259 warning("AES instructions are not available on this CPU");
260 FLAG_SET_DEFAULT(UseAES, false);
261 }
262 if (UseAESIntrinsics && !FLAG_IS_DEFAULT(UseAESIntrinsics)) {
263 warning("AES intrinsics are not available on this CPU");
264 FLAG_SET_DEFAULT(UseAESIntrinsics, false);
265 }
266 }
267
268 if (UseAESCTRIntrinsics) {
269 warning("AES/CTR intrinsics are not available on this CPU");
270 FLAG_SET_DEFAULT(UseAESCTRIntrinsics, false);
271 }
272
273 // GHASH/GCM intrinsics
274 if (has_vis3() && (UseVIS > 2)) {
275 if (FLAG_IS_DEFAULT(UseGHASHIntrinsics)) {
276 UseGHASHIntrinsics = true;
277 }
278 } else if (UseGHASHIntrinsics) {
279 if (!FLAG_IS_DEFAULT(UseGHASHIntrinsics))
280 warning("GHASH intrinsics require VIS3 instruction support. Intrinsics will be disabled");
281 FLAG_SET_DEFAULT(UseGHASHIntrinsics, false);
282 }
283
284 // SHA1, SHA256, and SHA512 instructions were added to SPARC T-series at different times
285 if (has_sha1() || has_sha256() || has_sha512()) {
286 if (UseVIS > 0) { // SHA intrinsics use VIS1 instructions
287 if (FLAG_IS_DEFAULT(UseSHA)) {
288 FLAG_SET_DEFAULT(UseSHA, true);
289 }
290 } else {
291 if (UseSHA) {
292 warning("SPARC SHA intrinsics require VIS1 instruction support. Intrinsics will be disabled.");
293 FLAG_SET_DEFAULT(UseSHA, false);
294 }
295 }
296 } else if (UseSHA) {
297 warning("SHA instructions are not available on this CPU");
298 FLAG_SET_DEFAULT(UseSHA, false);
299 }
300
301 if (UseSHA && has_sha1()) {
302 if (FLAG_IS_DEFAULT(UseSHA1Intrinsics)) {
303 FLAG_SET_DEFAULT(UseSHA1Intrinsics, true);
304 }
305 } else if (UseSHA1Intrinsics) {
306 warning("Intrinsics for SHA-1 crypto hash functions not available on this CPU.");
307 FLAG_SET_DEFAULT(UseSHA1Intrinsics, false);
308 }
309
310 if (UseSHA && has_sha256()) {
311 if (FLAG_IS_DEFAULT(UseSHA256Intrinsics)) {
312 FLAG_SET_DEFAULT(UseSHA256Intrinsics, true);
313 }
314 } else if (UseSHA256Intrinsics) {
315 warning("Intrinsics for SHA-224 and SHA-256 crypto hash functions not available on this CPU.");
316 FLAG_SET_DEFAULT(UseSHA256Intrinsics, false);
317 }
318
319 if (UseSHA && has_sha512()) {
320 if (FLAG_IS_DEFAULT(UseSHA512Intrinsics)) {
321 FLAG_SET_DEFAULT(UseSHA512Intrinsics, true);
322 }
323 } else if (UseSHA512Intrinsics) {
324 warning("Intrinsics for SHA-384 and SHA-512 crypto hash functions not available on this CPU.");
325 FLAG_SET_DEFAULT(UseSHA512Intrinsics, false);
326 }
327
328 if (!(UseSHA1Intrinsics || UseSHA256Intrinsics || UseSHA512Intrinsics)) {
329 FLAG_SET_DEFAULT(UseSHA, false);
330 }
331
332 // SPARC T4 and above should have support for CRC32C instruction
333 if (has_crc32c()) {
334 if (UseVIS > 2) { // CRC32C intrinsics use VIS3 instructions
335 if (FLAG_IS_DEFAULT(UseCRC32CIntrinsics)) {
336 FLAG_SET_DEFAULT(UseCRC32CIntrinsics, true);
337 }
338 } else {
339 if (UseCRC32CIntrinsics) {
340 warning("SPARC CRC32C intrinsics require VIS3 instruction support. Intrinsics will be disabled.");
341 FLAG_SET_DEFAULT(UseCRC32CIntrinsics, false);
342 }
343 }
344 } else if (UseCRC32CIntrinsics) {
345 warning("CRC32C instruction is not available on this CPU");
346 FLAG_SET_DEFAULT(UseCRC32CIntrinsics, false);
347 }
348
349 if (UseVIS > 2) {
350 if (FLAG_IS_DEFAULT(UseAdler32Intrinsics)) {
351 FLAG_SET_DEFAULT(UseAdler32Intrinsics, true);
352 }
353 } else if (UseAdler32Intrinsics) {
354 warning("SPARC Adler32 intrinsics require VIS3 instruction support. Intrinsics will be disabled.");
355 FLAG_SET_DEFAULT(UseAdler32Intrinsics, false);
356 }
357
358 if (UseVIS > 2) {
359 if (FLAG_IS_DEFAULT(UseCRC32Intrinsics)) {
360 FLAG_SET_DEFAULT(UseCRC32Intrinsics, true);
361 }
362 } else if (UseCRC32Intrinsics) {
363 warning("SPARC CRC32 intrinsics require VIS3 insructions support. Intriniscs will be disabled");
364 FLAG_SET_DEFAULT(UseCRC32Intrinsics, false);
365 }
366
367 if (UseVectorizedMismatchIntrinsic) {
368 warning("UseVectorizedMismatchIntrinsic specified, but not available on this CPU.");
369 FLAG_SET_DEFAULT(UseVectorizedMismatchIntrinsic, false);
370 }
371
372 if (FLAG_IS_DEFAULT(ContendedPaddingWidth) &&
373 (cache_line_size > ContendedPaddingWidth))
374 ContendedPaddingWidth = cache_line_size;
375
376 // This machine does not allow unaligned memory accesses
377 if (UseUnalignedAccesses) {
378 if (!FLAG_IS_DEFAULT(UseUnalignedAccesses))
379 warning("Unaligned memory access is not available on this CPU");
380 FLAG_SET_DEFAULT(UseUnalignedAccesses, false);
381 }
382
383 if (log_is_enabled(Info, os, cpu)) {
384 ResourceMark rm;
385 outputStream* log = Log(os, cpu)::info_stream();
386 log->print_cr("L1 data cache line size: %u", L1_data_cache_line_size());
387 log->print_cr("L2 data cache line size: %u", L2_data_cache_line_size());
388 log->print("Allocation");
389 if (AllocatePrefetchStyle <= 0) {
390 log->print(": no prefetching");
391 } else {
392 log->print(" prefetching: ");
393 if (AllocatePrefetchInstr == 0) {
394 log->print("PREFETCH");
395 } else if (AllocatePrefetchInstr == 1) {
396 log->print("BIS");
397 }
398 if (AllocatePrefetchLines > 1) {
399 log->print_cr(" at distance %d, %d lines of %d bytes", (int) AllocatePrefetchDistance, (int) AllocatePrefetchLines, (int) AllocatePrefetchStepSize);
400 } else {
401 log->print_cr(" at distance %d, one line of %d bytes", (int) AllocatePrefetchDistance, (int) AllocatePrefetchStepSize);
402 }
403 }
404 if (PrefetchCopyIntervalInBytes > 0) {
405 log->print_cr("PrefetchCopyIntervalInBytes %d", (int) PrefetchCopyIntervalInBytes);
406 }
407 if (PrefetchScanIntervalInBytes > 0) {
408 log->print_cr("PrefetchScanIntervalInBytes %d", (int) PrefetchScanIntervalInBytes);
409 }
410 if (PrefetchFieldsAhead > 0) {
411 log->print_cr("PrefetchFieldsAhead %d", (int) PrefetchFieldsAhead);
412 }
413 if (ContendedPaddingWidth > 0) {
414 log->print_cr("ContendedPaddingWidth %d", (int) ContendedPaddingWidth);
415 }
416 }
417 }
418
419 void VM_Version::print_features() {
420 tty->print_cr("Version:%s", _features);
421 }
422
423 int VM_Version::determine_features() {
424 if (UseV8InstrsOnly) {
425 log_info(os, cpu)("Version is Forced-V8");
426 return generic_v8_m;
427 }
428
429 int features = platform_features(unknown_m); // platform_features() is os_arch specific
430
431 if (features == unknown_m) {
432 features = generic_v9_m;
433 log_info(os)("Cannot recognize SPARC version. Default to V9");
434 }
435
436 assert(is_T_family(features) == is_niagara(features), "Niagara should be T series");
437 if (UseNiagaraInstrs) { // Force code generation for Niagara
438 if (is_T_family(features)) {
439 // Happy to accomodate...
440 } else {
441 log_info(os, cpu)("Version is Forced-Niagara");
442 features |= T_family_m;
443 }
444 } else {
445 if (is_T_family(features) && !FLAG_IS_DEFAULT(UseNiagaraInstrs)) {
446 log_info(os, cpu)("Version is Forced-Not-Niagara");
447 features &= ~(T_family_m | T1_model_m);
448 } else {
449 // Happy to accomodate...
450 }
451 }
452
453 return features;
454 }
455
456 static uint64_t saved_features = 0;
457
458 void VM_Version::allow_all() {
459 saved_features = _features;
460 _features = all_features_m;
461 }
462
463 void VM_Version::revert() {
464 _features = saved_features;
465 }
466
467 unsigned int VM_Version::calc_parallel_worker_threads() {
468 unsigned int result;
469 if (is_M_series()) {
470 // for now, use same gc thread calculation for M-series as for niagara-plus
471 // in future, we may want to tweak parameters for nof_parallel_worker_thread
472 result = nof_parallel_worker_threads(5, 16, 8);
473 } else if (is_niagara_plus()) {
474 result = nof_parallel_worker_threads(5, 16, 8);
475 } else {
476 result = nof_parallel_worker_threads(5, 8, 8);
477 }
478 return result;
479 }
480
481
482 int VM_Version::parse_features(const char* implementation) {
483 int features = unknown_m;
484 // Convert to UPPER case before compare.
485 char* impl = os::strdup_check_oom(implementation);
486
487 for (int i = 0; impl[i] != 0; i++)
488 impl[i] = (char)toupper((uint)impl[i]);
489
490 if (strstr(impl, "SPARC64") != NULL) {
491 features |= sparc64_family_m;
492 } else if (strstr(impl, "SPARC-M") != NULL) {
493 // M-series SPARC is based on T-series.
494 features |= (M_family_m | T_family_m);
495 } else if (strstr(impl, "SPARC-T") != NULL) {
496 features |= T_family_m;
497 if (strstr(impl, "SPARC-T1") != NULL) {
498 features |= T1_model_m;
499 }
500 } else {
501 if (strstr(impl, "SPARC") == NULL) {
502 #ifndef PRODUCT
503 // kstat on Solaris 8 virtual machines (branded zones)
504 // returns "(unsupported)" implementation. Solaris 8 is not
505 // supported anymore, but include this check to be on the
506 // safe side.
507 warning("Can't parse CPU implementation = '%s', assume generic SPARC", impl);
508 #endif
509 }
510 }
511 os::free((void*)impl);
512 return features;
513 }