149 RDI, RDI_H,
150 RDX, RDX_H,
151 RSI, RSI_H,
152 RAX, RAX_H,
153 RBP, RBP_H,
154 R13, R13_H,
155 R14, R14_H,
156 R15, R15_H,
157 RSP, RSP_H);
158
159
160 //----------Architecture Description Register Classes--------------------------
161 // Several register classes are automatically defined based upon information in
162 // this architecture description.
163 // 1) reg_class inline_cache_reg ( /* as def'd in frame section */ )
164 // 2) reg_class compiler_method_oop_reg ( /* as def'd in frame section */ )
165 // 2) reg_class interpreter_method_oop_reg ( /* as def'd in frame section */ )
166 // 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ )
167 //
168
169 // Class for all pointer registers (including RSP)
170 reg_class any_reg(RAX, RAX_H,
171 RDX, RDX_H,
172 RBP, RBP_H,
173 RDI, RDI_H,
174 RSI, RSI_H,
175 RCX, RCX_H,
176 RBX, RBX_H,
177 RSP, RSP_H,
178 R8, R8_H,
179 R9, R9_H,
180 R10, R10_H,
181 R11, R11_H,
182 R12, R12_H,
183 R13, R13_H,
184 R14, R14_H,
185 R15, R15_H);
186
187 // Class for all pointer registers except RSP
188 reg_class ptr_reg(RAX, RAX_H,
189 RDX, RDX_H,
190 RBP, RBP_H,
191 RDI, RDI_H,
192 RSI, RSI_H,
193 RCX, RCX_H,
194 RBX, RBX_H,
195 R8, R8_H,
196 R9, R9_H,
197 R10, R10_H,
198 R11, R11_H,
199 R13, R13_H,
200 R14, R14_H);
201
202 // Class for all pointer registers except RAX and RSP
203 reg_class ptr_no_rax_reg(RDX, RDX_H,
204 RBP, RBP_H,
205 RDI, RDI_H,
206 RSI, RSI_H,
207 RCX, RCX_H,
208 RBX, RBX_H,
209 R8, R8_H,
210 R9, R9_H,
211 R10, R10_H,
212 R11, R11_H,
213 R13, R13_H,
214 R14, R14_H);
215
216 reg_class ptr_no_rbp_reg(RDX, RDX_H,
217 RAX, RAX_H,
218 RDI, RDI_H,
219 RSI, RSI_H,
220 RCX, RCX_H,
221 RBX, RBX_H,
222 R8, R8_H,
223 R9, R9_H,
224 R10, R10_H,
225 R11, R11_H,
226 R13, R13_H,
227 R14, R14_H);
228
229 // Class for all pointer registers except RAX, RBX and RSP
230 reg_class ptr_no_rax_rbx_reg(RDX, RDX_H,
231 RBP, RBP_H,
232 RDI, RDI_H,
233 RSI, RSI_H,
234 RCX, RCX_H,
235 R8, R8_H,
236 R9, R9_H,
237 R10, R10_H,
238 R11, R11_H,
239 R13, R13_H,
240 R14, R14_H);
241
242 // Singleton class for RAX pointer register
243 reg_class ptr_rax_reg(RAX, RAX_H);
244
245 // Singleton class for RBX pointer register
246 reg_class ptr_rbx_reg(RBX, RBX_H);
247
248 // Singleton class for RSI pointer register
249 reg_class ptr_rsi_reg(RSI, RSI_H);
250
251 // Singleton class for RDI pointer register
252 reg_class ptr_rdi_reg(RDI, RDI_H);
253
254 // Singleton class for RBP pointer register
255 reg_class ptr_rbp_reg(RBP, RBP_H);
256
257 // Singleton class for stack pointer
258 reg_class ptr_rsp_reg(RSP, RSP_H);
259
260 // Singleton class for TLS pointer
261 reg_class ptr_r15_reg(R15, R15_H);
262
263 // Class for all long registers (except RSP)
264 reg_class long_reg(RAX, RAX_H,
265 RDX, RDX_H,
266 RBP, RBP_H,
267 RDI, RDI_H,
268 RSI, RSI_H,
269 RCX, RCX_H,
270 RBX, RBX_H,
271 R8, R8_H,
272 R9, R9_H,
273 R10, R10_H,
274 R11, R11_H,
275 R13, R13_H,
276 R14, R14_H);
277
278 // Class for all long registers except RAX, RDX (and RSP)
279 reg_class long_no_rax_rdx_reg(RBP, RBP_H,
280 RDI, RDI_H,
281 RSI, RSI_H,
282 RCX, RCX_H,
283 RBX, RBX_H,
284 R8, R8_H,
285 R9, R9_H,
286 R10, R10_H,
287 R11, R11_H,
288 R13, R13_H,
289 R14, R14_H);
290
291 // Class for all long registers except RCX (and RSP)
292 reg_class long_no_rcx_reg(RBP, RBP_H,
293 RDI, RDI_H,
294 RSI, RSI_H,
295 RAX, RAX_H,
296 RDX, RDX_H,
297 RBX, RBX_H,
298 R8, R8_H,
299 R9, R9_H,
300 R10, R10_H,
301 R11, R11_H,
302 R13, R13_H,
303 R14, R14_H);
304
305 // Class for all long registers except RAX (and RSP)
306 reg_class long_no_rax_reg(RBP, RBP_H,
307 RDX, RDX_H,
308 RDI, RDI_H,
309 RSI, RSI_H,
310 RCX, RCX_H,
311 RBX, RBX_H,
312 R8, R8_H,
313 R9, R9_H,
314 R10, R10_H,
315 R11, R11_H,
316 R13, R13_H,
317 R14, R14_H);
318
319 // Singleton class for RAX long register
320 reg_class long_rax_reg(RAX, RAX_H);
321
322 // Singleton class for RCX long register
323 reg_class long_rcx_reg(RCX, RCX_H);
324
325 // Singleton class for RDX long register
326 reg_class long_rdx_reg(RDX, RDX_H);
327
328 // Class for all int registers (except RSP)
329 reg_class int_reg(RAX,
330 RDX,
331 RBP,
332 RDI,
333 RSI,
334 RCX,
335 RBX,
336 R8,
337 R9,
338 R10,
339 R11,
340 R13,
341 R14);
342
343 // Class for all int registers except RCX (and RSP)
344 reg_class int_no_rcx_reg(RAX,
345 RDX,
346 RBP,
347 RDI,
348 RSI,
349 RBX,
350 R8,
351 R9,
352 R10,
353 R11,
354 R13,
355 R14);
356
357 // Class for all int registers except RAX, RDX (and RSP)
358 reg_class int_no_rax_rdx_reg(RBP,
359 RDI,
360 RSI,
361 RCX,
362 RBX,
363 R8,
364 R9,
365 R10,
366 R11,
367 R13,
368 R14);
369
370 // Singleton class for RAX int register
371 reg_class int_rax_reg(RAX);
372
373 // Singleton class for RBX int register
374 reg_class int_rbx_reg(RBX);
375
376 // Singleton class for RCX int register
377 reg_class int_rcx_reg(RCX);
378
379 // Singleton class for RCX int register
380 reg_class int_rdx_reg(RDX);
381
382 // Singleton class for RCX int register
383 reg_class int_rdi_reg(RDI);
384
385 // Singleton class for instruction pointer
386 // reg_class ip_reg(RIP);
387
388 %}
389
390 //----------SOURCE BLOCK-------------------------------------------------------
391 // This is a block of C++ code which provides values, functions, and
392 // definitions necessary in the rest of the architecture description
393 source %{
394 #define RELOC_IMM64 Assembler::imm_operand
395 #define RELOC_DISP32 Assembler::disp32_operand
396
397 #define __ _masm.
398
399 static int preserve_SP_size() {
400 return 3; // rex.w, op, rm(reg/reg)
401 }
402 static int clear_avx_size() {
403 return (Compile::current()->max_vector_size() > 16) ? 3 : 0; // vzeroupper
404 }
405
406 // !!!!! Special hack to get all types of calls to specify the byte offset
407 // from the start of the call to the point where the return address
408 // will point.
409 int MachCallStaticJavaNode::ret_addr_offset()
410 {
411 int offset = 5; // 5 bytes from start of call to where return address points
412 offset += clear_avx_size();
413 if (_method_handle_invoke)
414 offset += preserve_SP_size();
415 return offset;
416 }
417
418 int MachCallDynamicJavaNode::ret_addr_offset()
419 {
420 int offset = 15; // 15 bytes from start of call to where return address points
421 offset += clear_avx_size();
422 return offset;
423 }
424
425 int MachCallRuntimeNode::ret_addr_offset() {
426 int offset = 13; // movq r10,#addr; callq (r10)
427 offset += clear_avx_size();
428 return offset;
429 }
430
431 // Indicate if the safepoint node needs the polling page as an input,
432 // it does if the polling page is more than disp32 away.
433 bool SafePointNode::needs_polling_address_input()
434 {
435 return Assembler::is_polling_page_far();
436 }
437
438 //
439 // Compute padding required for nodes which need alignment
440 //
441
442 // The address of the call instruction needs to be 4-byte aligned to
443 // ensure that it does not span a cache line so that it can be patched.
444 int CallStaticJavaDirectNode::compute_padding(int current_offset) const
445 {
446 current_offset += clear_avx_size(); // skip vzeroupper
447 current_offset += 1; // skip call opcode byte
448 return round_to(current_offset, alignment_required()) - current_offset;
449 }
450
451 // The address of the call instruction needs to be 4-byte aligned to
452 // ensure that it does not span a cache line so that it can be patched.
453 int CallStaticJavaHandleNode::compute_padding(int current_offset) const
454 {
455 current_offset += preserve_SP_size(); // skip mov rbp, rsp
456 current_offset += clear_avx_size(); // skip vzeroupper
457 current_offset += 1; // skip call opcode byte
458 return round_to(current_offset, alignment_required()) - current_offset;
459 }
460
461 // The address of the call instruction needs to be 4-byte aligned to
462 // ensure that it does not span a cache line so that it can be patched.
463 int CallDynamicJavaDirectNode::compute_padding(int current_offset) const
464 {
465 current_offset += clear_avx_size(); // skip vzeroupper
466 current_offset += 11; // skip movq instruction + call opcode byte
467 return round_to(current_offset, alignment_required()) - current_offset;
468 }
469
470 // EMIT_RM()
471 void emit_rm(CodeBuffer &cbuf, int f1, int f2, int f3) {
472 unsigned char c = (unsigned char) ((f1 << 6) | (f2 << 3) | f3);
473 cbuf.insts()->emit_int8(c);
474 }
475
476 // EMIT_CC()
477 void emit_cc(CodeBuffer &cbuf, int f1, int f2) {
478 unsigned char c = (unsigned char) (f1 | f2);
479 cbuf.insts()->emit_int8(c);
480 }
481
482 // EMIT_OPCODE()
707 }
708 #endif
709
710
711 //=============================================================================
712 #ifndef PRODUCT
713 void MachPrologNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
714 Compile* C = ra_->C;
715
716 int framesize = C->frame_size_in_bytes();
717 int bangsize = C->bang_size_in_bytes();
718 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
719 // Remove wordSize for return addr which is already pushed.
720 framesize -= wordSize;
721
722 if (C->need_stack_bang(bangsize)) {
723 framesize -= wordSize;
724 st->print("# stack bang (%d bytes)", bangsize);
725 st->print("\n\t");
726 st->print("pushq rbp\t# Save rbp");
727 if (framesize) {
728 st->print("\n\t");
729 st->print("subq rsp, #%d\t# Create frame",framesize);
730 }
731 } else {
732 st->print("subq rsp, #%d\t# Create frame",framesize);
733 st->print("\n\t");
734 framesize -= wordSize;
735 st->print("movq [rsp + #%d], rbp\t# Save rbp",framesize);
736 }
737
738 if (VerifyStackAtCalls) {
739 st->print("\n\t");
740 framesize -= wordSize;
741 st->print("movq [rsp + #%d], 0xbadb100d\t# Majik cookie for stack depth check",framesize);
742 #ifdef ASSERT
743 st->print("\n\t");
744 st->print("# stack alignment check");
745 #endif
746 }
747 st->cr();
748 }
749 #endif
750
751 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
752 Compile* C = ra_->C;
753 MacroAssembler _masm(&cbuf);
754
755 int framesize = C->frame_size_in_bytes();
1581 // Register for DIVI projection of divmodI
1582 RegMask Matcher::divI_proj_mask() {
1583 return INT_RAX_REG_mask();
1584 }
1585
1586 // Register for MODI projection of divmodI
1587 RegMask Matcher::modI_proj_mask() {
1588 return INT_RDX_REG_mask();
1589 }
1590
1591 // Register for DIVL projection of divmodL
1592 RegMask Matcher::divL_proj_mask() {
1593 return LONG_RAX_REG_mask();
1594 }
1595
1596 // Register for MODL projection of divmodL
1597 RegMask Matcher::modL_proj_mask() {
1598 return LONG_RDX_REG_mask();
1599 }
1600
1601 const RegMask Matcher::method_handle_invoke_SP_save_mask() {
1602 return PTR_RBP_REG_mask();
1603 }
1604
1605 %}
1606
1607 //----------ENCODING BLOCK-----------------------------------------------------
1608 // This block specifies the encoding classes used by the compiler to
1609 // output byte streams. Encoding classes are parameterized macros
1610 // used by Machine Instruction Nodes in order to generate the bit
1611 // encoding of the instruction. Operands specify their base encoding
1612 // interface with the interface keyword. There are currently
1613 // supported four interfaces, REG_INTER, CONST_INTER, MEMORY_INTER, &
1614 // COND_INTER. REG_INTER causes an operand to generate a function
1615 // which returns its register number when queried. CONST_INTER causes
1616 // an operand to generate a function which returns the value of the
1617 // constant when queried. MEMORY_INTER causes an operand to generate
1618 // four functions which return the Base Register, the Index Register,
1619 // the Scale Value, and the Offset Value of the operand when queried.
1620 // COND_INTER causes an operand to generate six functions which return
1621 // the encoding code (ie - encoding bits for the instruction)
1622 // associated with each basic boolean condition for a conditional
3207 match(rax_RegP);
3208 match(rbx_RegP);
3209 match(rdi_RegP);
3210 match(rsi_RegP);
3211 match(rbp_RegP);
3212 match(r15_RegP);
3213 match(rRegP);
3214
3215 format %{ %}
3216 interface(REG_INTER);
3217 %}
3218
3219 operand rRegP()
3220 %{
3221 constraint(ALLOC_IN_RC(ptr_reg));
3222 match(RegP);
3223 match(rax_RegP);
3224 match(rbx_RegP);
3225 match(rdi_RegP);
3226 match(rsi_RegP);
3227 match(rbp_RegP);
3228 match(r15_RegP); // See Q&A below about r15_RegP.
3229
3230 format %{ %}
3231 interface(REG_INTER);
3232 %}
3233
3234 operand rRegN() %{
3235 constraint(ALLOC_IN_RC(int_reg));
3236 match(RegN);
3237
3238 format %{ %}
3239 interface(REG_INTER);
3240 %}
3241
3242 // Question: Why is r15_RegP (the read-only TLS register) a match for rRegP?
3243 // Answer: Operand match rules govern the DFA as it processes instruction inputs.
3244 // It's fine for an instruction input which expects rRegP to match a r15_RegP.
3245 // The output of an instruction is controlled by the allocator, which respects
3246 // register class masks, not match rules. Unless an instruction mentions
3247 // r15_RegP or any_RegP explicitly as its output, r15 will not be considered
3248 // by the allocator as an input.
3249
3250 operand no_rax_RegP()
3251 %{
3252 constraint(ALLOC_IN_RC(ptr_no_rax_reg));
3253 match(RegP);
3254 match(rbx_RegP);
3255 match(rsi_RegP);
3256 match(rdi_RegP);
3257
3258 format %{ %}
3259 interface(REG_INTER);
3260 %}
3261
3262 operand no_rbp_RegP()
3263 %{
3264 constraint(ALLOC_IN_RC(ptr_no_rbp_reg));
3265 match(RegP);
3266 match(rbx_RegP);
3267 match(rsi_RegP);
3268 match(rdi_RegP);
3269
3270 format %{ %}
3271 interface(REG_INTER);
3272 %}
3273
3274 operand no_rax_rbx_RegP()
3275 %{
3276 constraint(ALLOC_IN_RC(ptr_no_rax_rbx_reg));
3277 match(RegP);
3278 match(rsi_RegP);
3279 match(rdi_RegP);
3280
3281 format %{ %}
3282 interface(REG_INTER);
3283 %}
3284
3321 %{
3322 constraint(ALLOC_IN_RC(ptr_rsi_reg));
3323 match(RegP);
3324 match(rRegP);
3325
3326 format %{ %}
3327 interface(REG_INTER);
3328 %}
3329
3330 // Used in rep stosq
3331 operand rdi_RegP()
3332 %{
3333 constraint(ALLOC_IN_RC(ptr_rdi_reg));
3334 match(RegP);
3335 match(rRegP);
3336
3337 format %{ %}
3338 interface(REG_INTER);
3339 %}
3340
3341 operand rbp_RegP()
3342 %{
3343 constraint(ALLOC_IN_RC(ptr_rbp_reg));
3344 match(RegP);
3345 match(rRegP);
3346
3347 format %{ %}
3348 interface(REG_INTER);
3349 %}
3350
3351 operand r15_RegP()
3352 %{
3353 constraint(ALLOC_IN_RC(ptr_r15_reg));
3354 match(RegP);
3355 match(rRegP);
3356
3357 format %{ %}
3358 interface(REG_INTER);
3359 %}
3360
3361 operand rRegL()
3362 %{
3363 constraint(ALLOC_IN_RC(long_reg));
3364 match(RegL);
3365 match(rax_RegL);
3366 match(rdx_RegL);
3367
3368 format %{ %}
3369 interface(REG_INTER);
3370 %}
11397 match(SafePoint poll);
11398 effect(KILL cr, USE poll);
11399
11400 format %{ "testl rax, [$poll]\t"
11401 "# Safepoint: poll for GC" %}
11402 ins_cost(125);
11403 ins_encode %{
11404 __ relocate(relocInfo::poll_type);
11405 __ testl(rax, Address($poll$$Register, 0));
11406 %}
11407 ins_pipe(ialu_reg_mem);
11408 %}
11409
11410 // ============================================================================
11411 // Procedure Call/Return Instructions
11412 // Call Java Static Instruction
11413 // Note: If this code changes, the corresponding ret_addr_offset() and
11414 // compute_padding() functions will have to be adjusted.
11415 instruct CallStaticJavaDirect(method meth) %{
11416 match(CallStaticJava);
11417 predicate(!((CallStaticJavaNode*) n)->is_method_handle_invoke());
11418 effect(USE meth);
11419
11420 ins_cost(300);
11421 format %{ "call,static " %}
11422 opcode(0xE8); /* E8 cd */
11423 ins_encode(clear_avx, Java_Static_Call(meth), call_epilog);
11424 ins_pipe(pipe_slow);
11425 ins_alignment(4);
11426 %}
11427
11428 // Call Java Static Instruction (method handle version)
11429 // Note: If this code changes, the corresponding ret_addr_offset() and
11430 // compute_padding() functions will have to be adjusted.
11431 instruct CallStaticJavaHandle(method meth, rbp_RegP rbp_mh_SP_save) %{
11432 match(CallStaticJava);
11433 predicate(((CallStaticJavaNode*) n)->is_method_handle_invoke());
11434 effect(USE meth);
11435 // RBP is saved by all callees (for interpreter stack correction).
11436 // We use it here for a similar purpose, in {preserve,restore}_SP.
11437
11438 ins_cost(300);
11439 format %{ "call,static/MethodHandle " %}
11440 opcode(0xE8); /* E8 cd */
11441 ins_encode(clear_avx, preserve_SP,
11442 Java_Static_Call(meth),
11443 restore_SP,
11444 call_epilog);
11445 ins_pipe(pipe_slow);
11446 ins_alignment(4);
11447 %}
11448
11449 // Call Java Dynamic Instruction
11450 // Note: If this code changes, the corresponding ret_addr_offset() and
11451 // compute_padding() functions will have to be adjusted.
11452 instruct CallDynamicJavaDirect(method meth)
11453 %{
11454 match(CallDynamicJava);
11455 effect(USE meth);
11456
11457 ins_cost(300);
11458 format %{ "movq rax, #Universe::non_oop_word()\n\t"
11459 "call,dynamic " %}
11460 ins_encode(clear_avx, Java_Dynamic_Call(meth), call_epilog);
11461 ins_pipe(pipe_slow);
11462 ins_alignment(4);
11463 %}
11464
|
149 RDI, RDI_H,
150 RDX, RDX_H,
151 RSI, RSI_H,
152 RAX, RAX_H,
153 RBP, RBP_H,
154 R13, R13_H,
155 R14, R14_H,
156 R15, R15_H,
157 RSP, RSP_H);
158
159
160 //----------Architecture Description Register Classes--------------------------
161 // Several register classes are automatically defined based upon information in
162 // this architecture description.
163 // 1) reg_class inline_cache_reg ( /* as def'd in frame section */ )
164 // 2) reg_class compiler_method_oop_reg ( /* as def'd in frame section */ )
165 // 2) reg_class interpreter_method_oop_reg ( /* as def'd in frame section */ )
166 // 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ )
167 //
168
169 // Empty register class.
170 reg_class no_reg();
171
172 // Class for all pointer registers (including RSP and RBP)
173 reg_class any_reg_with_rbp(RAX, RAX_H,
174 RDX, RDX_H,
175 RBP, RBP_H,
176 RDI, RDI_H,
177 RSI, RSI_H,
178 RCX, RCX_H,
179 RBX, RBX_H,
180 RSP, RSP_H,
181 R8, R8_H,
182 R9, R9_H,
183 R10, R10_H,
184 R11, R11_H,
185 R12, R12_H,
186 R13, R13_H,
187 R14, R14_H,
188 R15, R15_H);
189
190 // Class for all pointer registers (including RSP, but excluding RBP)
191 reg_class any_reg_no_rbp(RAX, RAX_H,
192 RDX, RDX_H,
193 RDI, RDI_H,
194 RSI, RSI_H,
195 RCX, RCX_H,
196 RBX, RBX_H,
197 RSP, RSP_H,
198 R8, R8_H,
199 R9, R9_H,
200 R10, R10_H,
201 R11, R11_H,
202 R12, R12_H,
203 R13, R13_H,
204 R14, R14_H,
205 R15, R15_H);
206
207 // Dynamic register class that selects at runtime between register classes
208 // any_reg_no_rbp and any_reg_with_rbp (depending on the value of the flag PreserveFramePointer).
209 // Equivalent to: return PreserveFramePointer ? any_reg_no_rbp : any_reg_with_rbp;
210 reg_class_dynamic any_reg(any_reg_no_rbp, any_reg_with_rbp, %{ PreserveFramePointer %});
211
212 // Class for all pointer registers (excluding RSP)
213 reg_class ptr_reg_with_rbp(RAX, RAX_H,
214 RDX, RDX_H,
215 RBP, RBP_H,
216 RDI, RDI_H,
217 RSI, RSI_H,
218 RCX, RCX_H,
219 RBX, RBX_H,
220 R8, R8_H,
221 R9, R9_H,
222 R10, R10_H,
223 R11, R11_H,
224 R13, R13_H,
225 R14, R14_H);
226
227 // Class for all pointer registers (excluding RSP and RBP)
228 reg_class ptr_reg_no_rbp(RAX, RAX_H,
229 RDX, RDX_H,
230 RDI, RDI_H,
231 RSI, RSI_H,
232 RCX, RCX_H,
233 RBX, RBX_H,
234 R8, R8_H,
235 R9, R9_H,
236 R10, R10_H,
237 R11, R11_H,
238 R13, R13_H,
239 R14, R14_H);
240
241 // Dynamic register class that selects between ptr_reg_no_rbp and ptr_reg_with_rbp.
242 reg_class_dynamic ptr_reg(ptr_reg_no_rbp, ptr_reg_with_rbp, %{ PreserveFramePointer %});
243
244 // Class for all pointer registers (excluding RAX and RSP)
245 reg_class ptr_no_rax_reg_with_rbp(RDX, RDX_H,
246 RBP, RBP_H,
247 RDI, RDI_H,
248 RSI, RSI_H,
249 RCX, RCX_H,
250 RBX, RBX_H,
251 R8, R8_H,
252 R9, R9_H,
253 R10, R10_H,
254 R11, R11_H,
255 R13, R13_H,
256 R14, R14_H);
257
258 // Class for all pointer registers (excluding RAX, RSP, and RBP)
259 reg_class ptr_no_rax_reg_no_rbp(RDX, RDX_H,
260 RDI, RDI_H,
261 RSI, RSI_H,
262 RCX, RCX_H,
263 RBX, RBX_H,
264 R8, R8_H,
265 R9, R9_H,
266 R10, R10_H,
267 R11, R11_H,
268 R13, R13_H,
269 R14, R14_H);
270
271 // Dynamic register class that selects between ptr_no_rax_reg_no_rbp and ptr_no_rax_reg_with_rbp.
272 reg_class_dynamic ptr_no_rax_reg(ptr_no_rax_reg_no_rbp, ptr_no_rax_reg_with_rbp, %{ PreserveFramePointer %});
273
274 // Class for all pointer registers (excluding RAX, RBX, and RSP)
275 reg_class ptr_no_rax_rbx_reg_with_rbp(RDX, RDX_H,
276 RBP, RBP_H,
277 RDI, RDI_H,
278 RSI, RSI_H,
279 RCX, RCX_H,
280 R8, R8_H,
281 R9, R9_H,
282 R10, R10_H,
283 R11, R11_H,
284 R13, R13_H,
285 R14, R14_H);
286
287 // Class for all pointer registers (excluding RAX, RBX, RSP, and RBP)
288 reg_class ptr_no_rax_rbx_reg_no_rbp(RDX, RDX_H,
289 RDI, RDI_H,
290 RSI, RSI_H,
291 RCX, RCX_H,
292 R8, R8_H,
293 R9, R9_H,
294 R10, R10_H,
295 R11, R11_H,
296 R13, R13_H,
297 R14, R14_H);
298
299 // Dynamic register class that selects between ptr_no_rax_rbx_reg_no_rbp and ptr_no_rax_rbx_reg_with_rbp.
300 reg_class_dynamic ptr_no_rax_rbx_reg(ptr_no_rax_rbx_reg_no_rbp, ptr_no_rax_rbx_reg_with_rbp, %{ PreserveFramePointer %});
301
302 // Singleton class for RAX pointer register
303 reg_class ptr_rax_reg(RAX, RAX_H);
304
305 // Singleton class for RBX pointer register
306 reg_class ptr_rbx_reg(RBX, RBX_H);
307
308 // Singleton class for RSI pointer register
309 reg_class ptr_rsi_reg(RSI, RSI_H);
310
311 // Singleton class for RDI pointer register
312 reg_class ptr_rdi_reg(RDI, RDI_H);
313
314 // Singleton class for stack pointer
315 reg_class ptr_rsp_reg(RSP, RSP_H);
316
317 // Singleton class for TLS pointer
318 reg_class ptr_r15_reg(R15, R15_H);
319
320 // Class for all long registers (excluding RSP)
321 reg_class long_reg_with_rbp(RAX, RAX_H,
322 RDX, RDX_H,
323 RBP, RBP_H,
324 RDI, RDI_H,
325 RSI, RSI_H,
326 RCX, RCX_H,
327 RBX, RBX_H,
328 R8, R8_H,
329 R9, R9_H,
330 R10, R10_H,
331 R11, R11_H,
332 R13, R13_H,
333 R14, R14_H);
334
335 // Class for all long registers (excluding RSP and RBP)
336 reg_class long_reg_no_rbp(RAX, RAX_H,
337 RDX, RDX_H,
338 RDI, RDI_H,
339 RSI, RSI_H,
340 RCX, RCX_H,
341 RBX, RBX_H,
342 R8, R8_H,
343 R9, R9_H,
344 R10, R10_H,
345 R11, R11_H,
346 R13, R13_H,
347 R14, R14_H);
348
349 // Dynamic register class that selects between long_reg_no_rbp and long_reg_with_rbp.
350 reg_class_dynamic long_reg(long_reg_no_rbp, long_reg_with_rbp, %{ PreserveFramePointer %});
351
352 // Class for all long registers (excluding RAX, RDX and RSP)
353 reg_class long_no_rax_rdx_reg_with_rbp(RBP, RBP_H,
354 RDI, RDI_H,
355 RSI, RSI_H,
356 RCX, RCX_H,
357 RBX, RBX_H,
358 R8, R8_H,
359 R9, R9_H,
360 R10, R10_H,
361 R11, R11_H,
362 R13, R13_H,
363 R14, R14_H);
364
365 // Class for all long registers (excluding RAX, RDX, RSP, and RBP)
366 reg_class long_no_rax_rdx_reg_no_rbp(RDI, RDI_H,
367 RSI, RSI_H,
368 RCX, RCX_H,
369 RBX, RBX_H,
370 R8, R8_H,
371 R9, R9_H,
372 R10, R10_H,
373 R11, R11_H,
374 R13, R13_H,
375 R14, R14_H);
376
377 // Dynamic register class that selects between long_no_rax_rdx_reg_no_rbp and long_no_rax_rdx_reg_with_rbp.
378 reg_class_dynamic long_no_rax_rdx_reg(long_no_rax_rdx_reg_no_rbp, long_no_rax_rdx_reg_with_rbp, %{ PreserveFramePointer %});
379
380 // Class for all long registers (excluding RCX and RSP)
381 reg_class long_no_rcx_reg_with_rbp(RBP, RBP_H,
382 RDI, RDI_H,
383 RSI, RSI_H,
384 RAX, RAX_H,
385 RDX, RDX_H,
386 RBX, RBX_H,
387 R8, R8_H,
388 R9, R9_H,
389 R10, R10_H,
390 R11, R11_H,
391 R13, R13_H,
392 R14, R14_H);
393
394 // Class for all long registers (excluding RCX, RSP, and RBP)
395 reg_class long_no_rcx_reg_no_rbp(RDI, RDI_H,
396 RSI, RSI_H,
397 RAX, RAX_H,
398 RDX, RDX_H,
399 RBX, RBX_H,
400 R8, R8_H,
401 R9, R9_H,
402 R10, R10_H,
403 R11, R11_H,
404 R13, R13_H,
405 R14, R14_H);
406
407 // Dynamic register class that selects between long_no_rcx_reg_no_rbp and long_no_rcx_reg_with_rbp.
408 reg_class_dynamic long_no_rcx_reg(long_no_rcx_reg_no_rbp, long_no_rcx_reg_with_rbp, %{ PreserveFramePointer %});
409
410 // Singleton class for RAX long register
411 reg_class long_rax_reg(RAX, RAX_H);
412
413 // Singleton class for RCX long register
414 reg_class long_rcx_reg(RCX, RCX_H);
415
416 // Singleton class for RDX long register
417 reg_class long_rdx_reg(RDX, RDX_H);
418
419 // Class for all int registers (excluding RSP)
420 reg_class int_reg_with_rbp(RAX,
421 RDX,
422 RBP,
423 RDI,
424 RSI,
425 RCX,
426 RBX,
427 R8,
428 R9,
429 R10,
430 R11,
431 R13,
432 R14);
433
434 // Class for all int registers (excluding RSP and RBP)
435 reg_class int_reg_no_rbp(RAX,
436 RDX,
437 RDI,
438 RSI,
439 RCX,
440 RBX,
441 R8,
442 R9,
443 R10,
444 R11,
445 R13,
446 R14);
447
448 // Dynamic register class that selects between int_reg_no_rbp and int_reg_with_rbp.
449 reg_class_dynamic int_reg(int_reg_no_rbp, int_reg_with_rbp, %{ PreserveFramePointer %});
450
451 // Class for all int registers (excluding RCX and RSP)
452 reg_class int_no_rcx_reg_with_rbp(RAX,
453 RDX,
454 RBP,
455 RDI,
456 RSI,
457 RBX,
458 R8,
459 R9,
460 R10,
461 R11,
462 R13,
463 R14);
464
465 // Class for all int registers (excluding RCX, RSP, and RBP)
466 reg_class int_no_rcx_reg_no_rbp(RAX,
467 RDX,
468 RDI,
469 RSI,
470 RBX,
471 R8,
472 R9,
473 R10,
474 R11,
475 R13,
476 R14);
477
478 // Dynamic register class that selects between int_no_rcx_reg_no_rbp and int_no_rcx_reg_with_rbp.
479 reg_class_dynamic int_no_rcx_reg(int_no_rcx_reg_no_rbp, int_no_rcx_reg_with_rbp, %{ PreserveFramePointer %});
480
481 // Class for all int registers (excluding RAX, RDX, and RSP)
482 reg_class int_no_rax_rdx_reg_with_rbp(RBP,
483 RDI,
484 RSI,
485 RCX,
486 RBX,
487 R8,
488 R9,
489 R10,
490 R11,
491 R13,
492 R14);
493
494 // Class for all int registers (excluding RAX, RDX, RSP, and RBP)
495 reg_class int_no_rax_rdx_reg_no_rbp(RDI,
496 RSI,
497 RCX,
498 RBX,
499 R8,
500 R9,
501 R10,
502 R11,
503 R13,
504 R14);
505
506 // Dynamic register class that selects between int_no_rax_rdx_reg_no_rbp and int_no_rax_rdx_reg_with_rbp.
507 reg_class_dynamic int_no_rax_rdx_reg(int_no_rax_rdx_reg_no_rbp, int_no_rax_rdx_reg_with_rbp, %{ PreserveFramePointer %});
508
509 // Singleton class for RAX int register
510 reg_class int_rax_reg(RAX);
511
512 // Singleton class for RBX int register
513 reg_class int_rbx_reg(RBX);
514
515 // Singleton class for RCX int register
516 reg_class int_rcx_reg(RCX);
517
518 // Singleton class for RCX int register
519 reg_class int_rdx_reg(RDX);
520
521 // Singleton class for RCX int register
522 reg_class int_rdi_reg(RDI);
523
524 // Singleton class for instruction pointer
525 // reg_class ip_reg(RIP);
526
527 %}
528
529 //----------SOURCE BLOCK-------------------------------------------------------
530 // This is a block of C++ code which provides values, functions, and
531 // definitions necessary in the rest of the architecture description
532 source %{
533 #define RELOC_IMM64 Assembler::imm_operand
534 #define RELOC_DISP32 Assembler::disp32_operand
535
536 #define __ _masm.
537
538 static int clear_avx_size() {
539 return (Compile::current()->max_vector_size() > 16) ? 3 : 0; // vzeroupper
540 }
541
542 // !!!!! Special hack to get all types of calls to specify the byte offset
543 // from the start of the call to the point where the return address
544 // will point.
545 int MachCallStaticJavaNode::ret_addr_offset()
546 {
547 int offset = 5; // 5 bytes from start of call to where return address points
548 offset += clear_avx_size();
549 return offset;
550 }
551
552 int MachCallDynamicJavaNode::ret_addr_offset()
553 {
554 int offset = 15; // 15 bytes from start of call to where return address points
555 offset += clear_avx_size();
556 return offset;
557 }
558
559 int MachCallRuntimeNode::ret_addr_offset() {
560 int offset = 13; // movq r10,#addr; callq (r10)
561 offset += clear_avx_size();
562 return offset;
563 }
564
565 // Indicate if the safepoint node needs the polling page as an input,
566 // it does if the polling page is more than disp32 away.
567 bool SafePointNode::needs_polling_address_input()
568 {
569 return Assembler::is_polling_page_far();
570 }
571
572 //
573 // Compute padding required for nodes which need alignment
574 //
575
576 // The address of the call instruction needs to be 4-byte aligned to
577 // ensure that it does not span a cache line so that it can be patched.
578 int CallStaticJavaDirectNode::compute_padding(int current_offset) const
579 {
580 current_offset += clear_avx_size(); // skip vzeroupper
581 current_offset += 1; // skip call opcode byte
582 return round_to(current_offset, alignment_required()) - current_offset;
583 }
584
585 // The address of the call instruction needs to be 4-byte aligned to
586 // ensure that it does not span a cache line so that it can be patched.
587 int CallDynamicJavaDirectNode::compute_padding(int current_offset) const
588 {
589 current_offset += clear_avx_size(); // skip vzeroupper
590 current_offset += 11; // skip movq instruction + call opcode byte
591 return round_to(current_offset, alignment_required()) - current_offset;
592 }
593
594 // EMIT_RM()
595 void emit_rm(CodeBuffer &cbuf, int f1, int f2, int f3) {
596 unsigned char c = (unsigned char) ((f1 << 6) | (f2 << 3) | f3);
597 cbuf.insts()->emit_int8(c);
598 }
599
600 // EMIT_CC()
601 void emit_cc(CodeBuffer &cbuf, int f1, int f2) {
602 unsigned char c = (unsigned char) (f1 | f2);
603 cbuf.insts()->emit_int8(c);
604 }
605
606 // EMIT_OPCODE()
831 }
832 #endif
833
834
835 //=============================================================================
836 #ifndef PRODUCT
837 void MachPrologNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
838 Compile* C = ra_->C;
839
840 int framesize = C->frame_size_in_bytes();
841 int bangsize = C->bang_size_in_bytes();
842 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
843 // Remove wordSize for return addr which is already pushed.
844 framesize -= wordSize;
845
846 if (C->need_stack_bang(bangsize)) {
847 framesize -= wordSize;
848 st->print("# stack bang (%d bytes)", bangsize);
849 st->print("\n\t");
850 st->print("pushq rbp\t# Save rbp");
851 if (PreserveFramePointer) {
852 st->print("\n\t");
853 st->print("movq rbp, rsp\t# Save the caller's SP into rbp");
854 }
855 if (framesize) {
856 st->print("\n\t");
857 st->print("subq rsp, #%d\t# Create frame",framesize);
858 }
859 } else {
860 st->print("subq rsp, #%d\t# Create frame",framesize);
861 st->print("\n\t");
862 framesize -= wordSize;
863 st->print("movq [rsp + #%d], rbp\t# Save rbp",framesize);
864 if (PreserveFramePointer) {
865 st->print("\n\t");
866 st->print("movq rbp, [rsp + #%d]\t# Save the caller's SP into rbp", (framesize + wordSize));
867 }
868 }
869
870 if (VerifyStackAtCalls) {
871 st->print("\n\t");
872 framesize -= wordSize;
873 st->print("movq [rsp + #%d], 0xbadb100d\t# Majik cookie for stack depth check",framesize);
874 #ifdef ASSERT
875 st->print("\n\t");
876 st->print("# stack alignment check");
877 #endif
878 }
879 st->cr();
880 }
881 #endif
882
883 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
884 Compile* C = ra_->C;
885 MacroAssembler _masm(&cbuf);
886
887 int framesize = C->frame_size_in_bytes();
1713 // Register for DIVI projection of divmodI
1714 RegMask Matcher::divI_proj_mask() {
1715 return INT_RAX_REG_mask();
1716 }
1717
1718 // Register for MODI projection of divmodI
1719 RegMask Matcher::modI_proj_mask() {
1720 return INT_RDX_REG_mask();
1721 }
1722
1723 // Register for DIVL projection of divmodL
1724 RegMask Matcher::divL_proj_mask() {
1725 return LONG_RAX_REG_mask();
1726 }
1727
1728 // Register for MODL projection of divmodL
1729 RegMask Matcher::modL_proj_mask() {
1730 return LONG_RDX_REG_mask();
1731 }
1732
1733 // Register for saving SP into on method handle invokes. Not used on x86_64.
1734 const RegMask Matcher::method_handle_invoke_SP_save_mask() {
1735 return NO_REG_mask();
1736 }
1737
1738 %}
1739
1740 //----------ENCODING BLOCK-----------------------------------------------------
1741 // This block specifies the encoding classes used by the compiler to
1742 // output byte streams. Encoding classes are parameterized macros
1743 // used by Machine Instruction Nodes in order to generate the bit
1744 // encoding of the instruction. Operands specify their base encoding
1745 // interface with the interface keyword. There are currently
1746 // supported four interfaces, REG_INTER, CONST_INTER, MEMORY_INTER, &
1747 // COND_INTER. REG_INTER causes an operand to generate a function
1748 // which returns its register number when queried. CONST_INTER causes
1749 // an operand to generate a function which returns the value of the
1750 // constant when queried. MEMORY_INTER causes an operand to generate
1751 // four functions which return the Base Register, the Index Register,
1752 // the Scale Value, and the Offset Value of the operand when queried.
1753 // COND_INTER causes an operand to generate six functions which return
1754 // the encoding code (ie - encoding bits for the instruction)
1755 // associated with each basic boolean condition for a conditional
3340 match(rax_RegP);
3341 match(rbx_RegP);
3342 match(rdi_RegP);
3343 match(rsi_RegP);
3344 match(rbp_RegP);
3345 match(r15_RegP);
3346 match(rRegP);
3347
3348 format %{ %}
3349 interface(REG_INTER);
3350 %}
3351
3352 operand rRegP()
3353 %{
3354 constraint(ALLOC_IN_RC(ptr_reg));
3355 match(RegP);
3356 match(rax_RegP);
3357 match(rbx_RegP);
3358 match(rdi_RegP);
3359 match(rsi_RegP);
3360 match(rbp_RegP); // See Q&A below about
3361 match(r15_RegP); // r15_RegP and rbp_RegP.
3362
3363 format %{ %}
3364 interface(REG_INTER);
3365 %}
3366
3367 operand rRegN() %{
3368 constraint(ALLOC_IN_RC(int_reg));
3369 match(RegN);
3370
3371 format %{ %}
3372 interface(REG_INTER);
3373 %}
3374
3375 // Question: Why is r15_RegP (the read-only TLS register) a match for rRegP?
3376 // Answer: Operand match rules govern the DFA as it processes instruction inputs.
3377 // It's fine for an instruction input that expects rRegP to match a r15_RegP.
3378 // The output of an instruction is controlled by the allocator, which respects
3379 // register class masks, not match rules. Unless an instruction mentions
3380 // r15_RegP or any_RegP explicitly as its output, r15 will not be considered
3381 // by the allocator as an input.
3382 // The same logic applies to rbp_RegP being a match for rRegP: If PreserveFramePointer==true,
3383 // the RBP is used as a proper frame pointer and is not included in ptr_reg. As a
3384 // result, RBP is not included in the output of the instruction either.
3385
3386 operand no_rax_RegP()
3387 %{
3388 constraint(ALLOC_IN_RC(ptr_no_rax_reg));
3389 match(RegP);
3390 match(rbx_RegP);
3391 match(rsi_RegP);
3392 match(rdi_RegP);
3393
3394 format %{ %}
3395 interface(REG_INTER);
3396 %}
3397
3398 // This operand is not allowed to use RBP even if
3399 // RBP is not used to hold the frame pointer.
3400 operand no_rbp_RegP()
3401 %{
3402 constraint(ALLOC_IN_RC(ptr_reg_no_rbp));
3403 match(RegP);
3404 match(rbx_RegP);
3405 match(rsi_RegP);
3406 match(rdi_RegP);
3407
3408 format %{ %}
3409 interface(REG_INTER);
3410 %}
3411
3412 operand no_rax_rbx_RegP()
3413 %{
3414 constraint(ALLOC_IN_RC(ptr_no_rax_rbx_reg));
3415 match(RegP);
3416 match(rsi_RegP);
3417 match(rdi_RegP);
3418
3419 format %{ %}
3420 interface(REG_INTER);
3421 %}
3422
3459 %{
3460 constraint(ALLOC_IN_RC(ptr_rsi_reg));
3461 match(RegP);
3462 match(rRegP);
3463
3464 format %{ %}
3465 interface(REG_INTER);
3466 %}
3467
3468 // Used in rep stosq
3469 operand rdi_RegP()
3470 %{
3471 constraint(ALLOC_IN_RC(ptr_rdi_reg));
3472 match(RegP);
3473 match(rRegP);
3474
3475 format %{ %}
3476 interface(REG_INTER);
3477 %}
3478
3479 operand r15_RegP()
3480 %{
3481 constraint(ALLOC_IN_RC(ptr_r15_reg));
3482 match(RegP);
3483 match(rRegP);
3484
3485 format %{ %}
3486 interface(REG_INTER);
3487 %}
3488
3489 operand rRegL()
3490 %{
3491 constraint(ALLOC_IN_RC(long_reg));
3492 match(RegL);
3493 match(rax_RegL);
3494 match(rdx_RegL);
3495
3496 format %{ %}
3497 interface(REG_INTER);
3498 %}
11525 match(SafePoint poll);
11526 effect(KILL cr, USE poll);
11527
11528 format %{ "testl rax, [$poll]\t"
11529 "# Safepoint: poll for GC" %}
11530 ins_cost(125);
11531 ins_encode %{
11532 __ relocate(relocInfo::poll_type);
11533 __ testl(rax, Address($poll$$Register, 0));
11534 %}
11535 ins_pipe(ialu_reg_mem);
11536 %}
11537
11538 // ============================================================================
11539 // Procedure Call/Return Instructions
11540 // Call Java Static Instruction
11541 // Note: If this code changes, the corresponding ret_addr_offset() and
11542 // compute_padding() functions will have to be adjusted.
11543 instruct CallStaticJavaDirect(method meth) %{
11544 match(CallStaticJava);
11545 effect(USE meth);
11546
11547 ins_cost(300);
11548 format %{ "call,static " %}
11549 opcode(0xE8); /* E8 cd */
11550 ins_encode(clear_avx, Java_Static_Call(meth), call_epilog);
11551 ins_pipe(pipe_slow);
11552 ins_alignment(4);
11553 %}
11554
11555 // Call Java Dynamic Instruction
11556 // Note: If this code changes, the corresponding ret_addr_offset() and
11557 // compute_padding() functions will have to be adjusted.
11558 instruct CallDynamicJavaDirect(method meth)
11559 %{
11560 match(CallDynamicJava);
11561 effect(USE meth);
11562
11563 ins_cost(300);
11564 format %{ "movq rax, #Universe::non_oop_word()\n\t"
11565 "call,dynamic " %}
11566 ins_encode(clear_avx, Java_Dynamic_Call(meth), call_epilog);
11567 ins_pipe(pipe_slow);
11568 ins_alignment(4);
11569 %}
11570
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