106 // allocation. Highest priority is first. A useful heuristic is to
107 // give registers a low priority when they are required by machine
108 // instructions, like EAX and EDX. Registers which are used as
109 // pairs must fall on an even boundary (witness the FPR#L's in this list).
110 // For the Intel integer registers, the equivalent Long pairs are
111 // EDX:EAX, EBX:ECX, and EDI:EBP.
112 alloc_class chunk0( ECX, EBX, EBP, EDI, EAX, EDX, ESI, ESP,
113 FPR0L, FPR0H, FPR1L, FPR1H, FPR2L, FPR2H,
114 FPR3L, FPR3H, FPR4L, FPR4H, FPR5L, FPR5H,
115 FPR6L, FPR6H, FPR7L, FPR7H );
116
117
118 //----------Architecture Description Register Classes--------------------------
119 // Several register classes are automatically defined based upon information in
120 // this architecture description.
121 // 1) reg_class inline_cache_reg ( /* as def'd in frame section */ )
122 // 2) reg_class compiler_method_oop_reg ( /* as def'd in frame section */ )
123 // 2) reg_class interpreter_method_oop_reg ( /* as def'd in frame section */ )
124 // 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ )
125 //
126 // Class for all registers
127 reg_class any_reg(EAX, EDX, EBP, EDI, ESI, ECX, EBX, ESP);
128 // Class for general registers
129 reg_class int_reg(EAX, EDX, EBP, EDI, ESI, ECX, EBX);
130 // Class for general registers which may be used for implicit null checks on win95
131 // Also safe for use by tailjump. We don't want to allocate in rbp,
132 reg_class int_reg_no_rbp(EAX, EDX, EDI, ESI, ECX, EBX);
133 // Class of "X" registers
134 reg_class int_x_reg(EBX, ECX, EDX, EAX);
135 // Class of registers that can appear in an address with no offset.
136 // EBP and ESP require an extra instruction byte for zero offset.
137 // Used in fast-unlock
138 reg_class p_reg(EDX, EDI, ESI, EBX);
139 // Class for general registers not including ECX
140 reg_class ncx_reg(EAX, EDX, EBP, EDI, ESI, EBX);
141 // Class for general registers not including EAX
142 reg_class nax_reg(EDX, EDI, ESI, ECX, EBX);
143 // Class for general registers not including EAX or EBX.
144 reg_class nabx_reg(EDX, EDI, ESI, ECX, EBP);
145 // Class of EAX (for multiply and divide operations)
146 reg_class eax_reg(EAX);
147 // Class of EBX (for atomic add)
148 reg_class ebx_reg(EBX);
149 // Class of ECX (for shift and JCXZ operations and cmpLTMask)
150 reg_class ecx_reg(ECX);
151 // Class of EDX (for multiply and divide operations)
152 reg_class edx_reg(EDX);
153 // Class of EDI (for synchronization)
154 reg_class edi_reg(EDI);
155 // Class of ESI (for synchronization)
156 reg_class esi_reg(ESI);
157 // Singleton class for interpreter's stack pointer
158 reg_class ebp_reg(EBP);
159 // Singleton class for stack pointer
160 reg_class sp_reg(ESP);
161 // Singleton class for instruction pointer
162 // reg_class ip_reg(EIP);
163 // Class of integer register pairs
164 reg_class long_reg( EAX,EDX, ECX,EBX, EBP,EDI );
165 // Class of integer register pairs that aligns with calling convention
166 reg_class eadx_reg( EAX,EDX );
167 reg_class ebcx_reg( ECX,EBX );
168 // Not AX or DX, used in divides
169 reg_class nadx_reg( EBX,ECX,ESI,EDI,EBP );
170
171 // Floating point registers. Notice FPR0 is not a choice.
172 // FPR0 is not ever allocated; we use clever encodings to fake
173 // a 2-address instructions out of Intels FP stack.
174 reg_class fp_flt_reg( FPR1L,FPR2L,FPR3L,FPR4L,FPR5L,FPR6L,FPR7L );
175
176 reg_class fp_dbl_reg( FPR1L,FPR1H, FPR2L,FPR2H, FPR3L,FPR3H,
177 FPR4L,FPR4H, FPR5L,FPR5H, FPR6L,FPR6H,
178 FPR7L,FPR7H );
179
180 reg_class fp_flt_reg0( FPR1L );
181 reg_class fp_dbl_reg0( FPR1L,FPR1H );
182 reg_class fp_dbl_reg1( FPR2L,FPR2H );
183 reg_class fp_dbl_notreg0( FPR2L,FPR2H, FPR3L,FPR3H, FPR4L,FPR4H,
184 FPR5L,FPR5H, FPR6L,FPR6H, FPR7L,FPR7H );
185
186 %}
187
188
189 //----------SOURCE BLOCK-------------------------------------------------------
223
224 // Static initialization during VM startup.
225 static jlong *float_signmask_pool = double_quadword(&fp_signmask_pool[1*2], CONST64(0x7FFFFFFF7FFFFFFF), CONST64(0x7FFFFFFF7FFFFFFF));
226 static jlong *double_signmask_pool = double_quadword(&fp_signmask_pool[2*2], CONST64(0x7FFFFFFFFFFFFFFF), CONST64(0x7FFFFFFFFFFFFFFF));
227 static jlong *float_signflip_pool = double_quadword(&fp_signmask_pool[3*2], CONST64(0x8000000080000000), CONST64(0x8000000080000000));
228 static jlong *double_signflip_pool = double_quadword(&fp_signmask_pool[4*2], CONST64(0x8000000000000000), CONST64(0x8000000000000000));
229
230 // Offset hacking within calls.
231 static int pre_call_resets_size() {
232 int size = 0;
233 Compile* C = Compile::current();
234 if (C->in_24_bit_fp_mode()) {
235 size += 6; // fldcw
236 }
237 if (C->max_vector_size() > 16) {
238 size += 3; // vzeroupper
239 }
240 return size;
241 }
242
243 static int preserve_SP_size() {
244 return 2; // op, rm(reg/reg)
245 }
246
247 // !!!!! Special hack to get all type of calls to specify the byte offset
248 // from the start of the call to the point where the return address
249 // will point.
250 int MachCallStaticJavaNode::ret_addr_offset() {
251 int offset = 5 + pre_call_resets_size(); // 5 bytes from start of call to where return address points
252 if (_method_handle_invoke)
253 offset += preserve_SP_size();
254 return offset;
255 }
256
257 int MachCallDynamicJavaNode::ret_addr_offset() {
258 return 10 + pre_call_resets_size(); // 10 bytes from start of call to where return address points
259 }
260
261 static int sizeof_FFree_Float_Stack_All = -1;
262
263 int MachCallRuntimeNode::ret_addr_offset() {
264 assert(sizeof_FFree_Float_Stack_All != -1, "must have been emitted already");
265 return sizeof_FFree_Float_Stack_All + 5 + pre_call_resets_size();
266 }
267
268 // Indicate if the safepoint node needs the polling page as an input.
269 // Since x86 does have absolute addressing, it doesn't.
270 bool SafePointNode::needs_polling_address_input() {
271 return false;
272 }
273
274 //
275 // Compute padding required for nodes which need alignment
276 //
277
278 // The address of the call instruction needs to be 4-byte aligned to
279 // ensure that it does not span a cache line so that it can be patched.
280 int CallStaticJavaDirectNode::compute_padding(int current_offset) const {
281 current_offset += pre_call_resets_size(); // skip fldcw, if any
282 current_offset += 1; // skip call opcode byte
283 return round_to(current_offset, alignment_required()) - current_offset;
284 }
285
286 // The address of the call instruction needs to be 4-byte aligned to
287 // ensure that it does not span a cache line so that it can be patched.
288 int CallStaticJavaHandleNode::compute_padding(int current_offset) const {
289 current_offset += pre_call_resets_size(); // skip fldcw, if any
290 current_offset += preserve_SP_size(); // skip mov rbp, rsp
291 current_offset += 1; // skip call opcode byte
292 return round_to(current_offset, alignment_required()) - current_offset;
293 }
294
295 // The address of the call instruction needs to be 4-byte aligned to
296 // ensure that it does not span a cache line so that it can be patched.
297 int CallDynamicJavaDirectNode::compute_padding(int current_offset) const {
298 current_offset += pre_call_resets_size(); // skip fldcw, if any
299 current_offset += 5; // skip MOV instruction
300 current_offset += 1; // skip call opcode byte
301 return round_to(current_offset, alignment_required()) - current_offset;
302 }
303
304 // EMIT_RM()
305 void emit_rm(CodeBuffer &cbuf, int f1, int f2, int f3) {
306 unsigned char c = (unsigned char)((f1 << 6) | (f2 << 3) | f3);
307 cbuf.insts()->emit_int8(c);
308 }
309
310 // EMIT_CC()
311 void emit_cc(CodeBuffer &cbuf, int f1, int f2) {
312 unsigned char c = (unsigned char)( f1 | f2 );
313 cbuf.insts()->emit_int8(c);
314 }
315
316 // EMIT_OPCODE()
506 }
507 #endif
508
509
510 //=============================================================================
511 #ifndef PRODUCT
512 void MachPrologNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
513 Compile* C = ra_->C;
514
515 int framesize = C->frame_size_in_bytes();
516 int bangsize = C->bang_size_in_bytes();
517 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
518 // Remove wordSize for return addr which is already pushed.
519 framesize -= wordSize;
520
521 if (C->need_stack_bang(bangsize)) {
522 framesize -= wordSize;
523 st->print("# stack bang (%d bytes)", bangsize);
524 st->print("\n\t");
525 st->print("PUSH EBP\t# Save EBP");
526 if (framesize) {
527 st->print("\n\t");
528 st->print("SUB ESP, #%d\t# Create frame",framesize);
529 }
530 } else {
531 st->print("SUB ESP, #%d\t# Create frame",framesize);
532 st->print("\n\t");
533 framesize -= wordSize;
534 st->print("MOV [ESP + #%d], EBP\t# Save EBP",framesize);
535 }
536
537 if (VerifyStackAtCalls) {
538 st->print("\n\t");
539 framesize -= wordSize;
540 st->print("MOV [ESP + #%d], 0xBADB100D\t# Majik cookie for stack depth check",framesize);
541 }
542
543 if( C->in_24_bit_fp_mode() ) {
544 st->print("\n\t");
545 st->print("FLDCW \t# load 24 bit fpu control word");
546 }
547 if (UseSSE >= 2 && VerifyFPU) {
548 st->print("\n\t");
549 st->print("# verify FPU stack (must be clean on entry)");
550 }
551
552 #ifdef ASSERT
553 if (VerifyStackAtCalls) {
554 st->print("\n\t");
1471 }
1472
1473 // Register for MODI projection of divmodI
1474 RegMask Matcher::modI_proj_mask() {
1475 return EDX_REG_mask();
1476 }
1477
1478 // Register for DIVL projection of divmodL
1479 RegMask Matcher::divL_proj_mask() {
1480 ShouldNotReachHere();
1481 return RegMask();
1482 }
1483
1484 // Register for MODL projection of divmodL
1485 RegMask Matcher::modL_proj_mask() {
1486 ShouldNotReachHere();
1487 return RegMask();
1488 }
1489
1490 const RegMask Matcher::method_handle_invoke_SP_save_mask() {
1491 return EBP_REG_mask();
1492 }
1493
1494 // Returns true if the high 32 bits of the value is known to be zero.
1495 bool is_operand_hi32_zero(Node* n) {
1496 int opc = n->Opcode();
1497 if (opc == Op_AndL) {
1498 Node* o2 = n->in(2);
1499 if (o2->is_Con() && (o2->get_long() & 0xFFFFFFFF00000000LL) == 0LL) {
1500 return true;
1501 }
1502 }
1503 if (opc == Op_ConL && (n->get_long() & 0xFFFFFFFF00000000LL) == 0LL) {
1504 return true;
1505 }
1506 return false;
1507 }
1508
1509 %}
1510
1511 //----------ENCODING BLOCK-----------------------------------------------------
3717 match(eRegP);
3718
3719 format %{ %}
3720 interface(REG_INTER);
3721 %}
3722
3723 operand eRegP() %{
3724 constraint(ALLOC_IN_RC(int_reg));
3725 match(RegP);
3726 match(eAXRegP);
3727 match(eBXRegP);
3728 match(eCXRegP);
3729 match(eDIRegP);
3730
3731 format %{ %}
3732 interface(REG_INTER);
3733 %}
3734
3735 // On windows95, EBP is not safe to use for implicit null tests.
3736 operand eRegP_no_EBP() %{
3737 constraint(ALLOC_IN_RC(int_reg_no_rbp));
3738 match(RegP);
3739 match(eAXRegP);
3740 match(eBXRegP);
3741 match(eCXRegP);
3742 match(eDIRegP);
3743
3744 op_cost(100);
3745 format %{ %}
3746 interface(REG_INTER);
3747 %}
3748
3749 operand naxRegP() %{
3750 constraint(ALLOC_IN_RC(nax_reg));
3751 match(RegP);
3752 match(eBXRegP);
3753 match(eDXRegP);
3754 match(eCXRegP);
3755 match(eSIRegP);
3756 match(eDIRegP);
3757
3806 match(reg);
3807 format %{ "ECX" %}
3808 interface(REG_INTER);
3809 %}
3810
3811 operand eSIRegP(eRegP reg) %{
3812 constraint(ALLOC_IN_RC(esi_reg));
3813 match(reg);
3814 format %{ "ESI" %}
3815 interface(REG_INTER);
3816 %}
3817
3818 // Used in rep stosw
3819 operand eDIRegP(eRegP reg) %{
3820 constraint(ALLOC_IN_RC(edi_reg));
3821 match(reg);
3822 format %{ "EDI" %}
3823 interface(REG_INTER);
3824 %}
3825
3826 operand eBPRegP() %{
3827 constraint(ALLOC_IN_RC(ebp_reg));
3828 match(RegP);
3829 format %{ "EBP" %}
3830 interface(REG_INTER);
3831 %}
3832
3833 operand eRegL() %{
3834 constraint(ALLOC_IN_RC(long_reg));
3835 match(RegL);
3836 match(eADXRegL);
3837
3838 format %{ %}
3839 interface(REG_INTER);
3840 %}
3841
3842 operand eADXRegL( eRegL reg ) %{
3843 constraint(ALLOC_IN_RC(eadx_reg));
3844 match(reg);
3845
3846 format %{ "EDX:EAX" %}
3847 interface(REG_INTER);
3848 %}
3849
3850 operand eBCXRegL( eRegL reg ) %{
3851 constraint(ALLOC_IN_RC(ebcx_reg));
3852 match(reg);
12691 %}
12692
12693
12694 instruct cmovFF_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regF dst, regF src) %{
12695 predicate( UseSSE>=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt );
12696 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
12697 ins_cost(200);
12698 expand %{
12699 fcmovF_regS(cmp,flags,dst,src);
12700 %}
12701 %}
12702
12703
12704 // ============================================================================
12705 // Procedure Call/Return Instructions
12706 // Call Java Static Instruction
12707 // Note: If this code changes, the corresponding ret_addr_offset() and
12708 // compute_padding() functions will have to be adjusted.
12709 instruct CallStaticJavaDirect(method meth) %{
12710 match(CallStaticJava);
12711 predicate(! ((CallStaticJavaNode*)n)->is_method_handle_invoke());
12712 effect(USE meth);
12713
12714 ins_cost(300);
12715 format %{ "CALL,static " %}
12716 opcode(0xE8); /* E8 cd */
12717 ins_encode( pre_call_resets,
12718 Java_Static_Call( meth ),
12719 call_epilog,
12720 post_call_FPU );
12721 ins_pipe( pipe_slow );
12722 ins_alignment(4);
12723 %}
12724
12725 // Call Java Static Instruction (method handle version)
12726 // Note: If this code changes, the corresponding ret_addr_offset() and
12727 // compute_padding() functions will have to be adjusted.
12728 instruct CallStaticJavaHandle(method meth, eBPRegP ebp_mh_SP_save) %{
12729 match(CallStaticJava);
12730 predicate(((CallStaticJavaNode*)n)->is_method_handle_invoke());
12731 effect(USE meth);
12732 // EBP is saved by all callees (for interpreter stack correction).
12733 // We use it here for a similar purpose, in {preserve,restore}_SP.
12734
12735 ins_cost(300);
12736 format %{ "CALL,static/MethodHandle " %}
12737 opcode(0xE8); /* E8 cd */
12738 ins_encode( pre_call_resets,
12739 preserve_SP,
12740 Java_Static_Call( meth ),
12741 restore_SP,
12742 call_epilog,
12743 post_call_FPU );
12744 ins_pipe( pipe_slow );
12745 ins_alignment(4);
12746 %}
12747
12748 // Call Java Dynamic Instruction
12749 // Note: If this code changes, the corresponding ret_addr_offset() and
12750 // compute_padding() functions will have to be adjusted.
12751 instruct CallDynamicJavaDirect(method meth) %{
12752 match(CallDynamicJava);
12753 effect(USE meth);
12754
12755 ins_cost(300);
12756 format %{ "MOV EAX,(oop)-1\n\t"
12757 "CALL,dynamic" %}
12758 opcode(0xE8); /* E8 cd */
12759 ins_encode( pre_call_resets,
12760 Java_Dynamic_Call( meth ),
12761 call_epilog,
|
106 // allocation. Highest priority is first. A useful heuristic is to
107 // give registers a low priority when they are required by machine
108 // instructions, like EAX and EDX. Registers which are used as
109 // pairs must fall on an even boundary (witness the FPR#L's in this list).
110 // For the Intel integer registers, the equivalent Long pairs are
111 // EDX:EAX, EBX:ECX, and EDI:EBP.
112 alloc_class chunk0( ECX, EBX, EBP, EDI, EAX, EDX, ESI, ESP,
113 FPR0L, FPR0H, FPR1L, FPR1H, FPR2L, FPR2H,
114 FPR3L, FPR3H, FPR4L, FPR4H, FPR5L, FPR5H,
115 FPR6L, FPR6H, FPR7L, FPR7H );
116
117
118 //----------Architecture Description Register Classes--------------------------
119 // Several register classes are automatically defined based upon information in
120 // this architecture description.
121 // 1) reg_class inline_cache_reg ( /* as def'd in frame section */ )
122 // 2) reg_class compiler_method_oop_reg ( /* as def'd in frame section */ )
123 // 2) reg_class interpreter_method_oop_reg ( /* as def'd in frame section */ )
124 // 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ )
125 //
126 // Class for no registers (empty set).
127 reg_class no_reg();
128
129 // Class for all registers
130 reg_class any_reg_with_ebp(EAX, EDX, EBP, EDI, ESI, ECX, EBX, ESP);
131 // Class for all registers (excluding EBP)
132 reg_class any_reg_no_ebp(EAX, EDX, EDI, ESI, ECX, EBX, ESP);
133 // Dynamic register class that selects at runtime between register classes
134 // any_reg and any_no_ebp_reg (depending on the value of the flag PreserveFramePointer).
135 // Equivalent to: return PreserveFramePointer ? any_no_ebp_reg : any_reg;
136 reg_class_dynamic any_reg(any_reg_no_ebp, any_reg_with_ebp, %{ PreserveFramePointer %});
137
138 // Class for general registers
139 reg_class int_reg_with_ebp(EAX, EDX, EBP, EDI, ESI, ECX, EBX);
140 // Class for general registers (excluding EBP).
141 // This register class can be used for implicit null checks on win95.
142 // It is also safe for use by tailjumps (we don't want to allocate in ebp).
143 // Used also if the PreserveFramePointer flag is true.
144 reg_class int_reg_no_ebp(EAX, EDX, EDI, ESI, ECX, EBX);
145 // Dynamic register class that selects between int_reg and int_reg_no_ebp.
146 reg_class_dynamic int_reg(int_reg_no_ebp, int_reg_with_ebp, %{ PreserveFramePointer %});
147
148 // Class of "X" registers
149 reg_class int_x_reg(EBX, ECX, EDX, EAX);
150
151 // Class of registers that can appear in an address with no offset.
152 // EBP and ESP require an extra instruction byte for zero offset.
153 // Used in fast-unlock
154 reg_class p_reg(EDX, EDI, ESI, EBX);
155
156 // Class for general registers excluding ECX
157 reg_class ncx_reg_with_ebp(EAX, EDX, EBP, EDI, ESI, EBX);
158 // Class for general registers excluding ECX (and EBP)
159 reg_class ncx_reg_no_ebp(EAX, EDX, EDI, ESI, EBX);
160 // Dynamic register class that selects between ncx_reg and ncx_reg_no_ebp.
161 reg_class_dynamic ncx_reg(ncx_reg_no_ebp, ncx_reg_with_ebp, %{ PreserveFramePointer %});
162
163 // Class for general registers excluding EAX
164 reg_class nax_reg(EDX, EDI, ESI, ECX, EBX);
165
166 // Class for general registers excluding EAX and EBX.
167 reg_class nabx_reg_with_ebp(EDX, EDI, ESI, ECX, EBP);
168 // Class for general registers excluding EAX and EBX (and EBP)
169 reg_class nabx_reg_no_ebp(EDX, EDI, ESI, ECX);
170 // Dynamic register class that selects between nabx_reg and nabx_reg_no_ebp.
171 reg_class_dynamic nabx_reg(nabx_reg_no_ebp, nabx_reg_with_ebp, %{ PreserveFramePointer %});
172
173 // Class of EAX (for multiply and divide operations)
174 reg_class eax_reg(EAX);
175
176 // Class of EBX (for atomic add)
177 reg_class ebx_reg(EBX);
178
179 // Class of ECX (for shift and JCXZ operations and cmpLTMask)
180 reg_class ecx_reg(ECX);
181
182 // Class of EDX (for multiply and divide operations)
183 reg_class edx_reg(EDX);
184
185 // Class of EDI (for synchronization)
186 reg_class edi_reg(EDI);
187
188 // Class of ESI (for synchronization)
189 reg_class esi_reg(ESI);
190
191 // Singleton class for stack pointer
192 reg_class sp_reg(ESP);
193
194 // Singleton class for instruction pointer
195 // reg_class ip_reg(EIP);
196
197 // Class of integer register pairs
198 reg_class long_reg_with_ebp( EAX,EDX, ECX,EBX, EBP,EDI );
199 // Class of integer register pairs (excluding EBP and EDI);
200 reg_class long_reg_no_ebp( EAX,EDX, ECX,EBX );
201 // Dynamic register class that selects between long_reg and long_reg_no_ebp.
202 reg_class_dynamic long_reg(long_reg_no_ebp, long_reg_with_ebp, %{ PreserveFramePointer %});
203
204 // Class of integer register pairs that aligns with calling convention
205 reg_class eadx_reg( EAX,EDX );
206 reg_class ebcx_reg( ECX,EBX );
207
208 // Not AX or DX, used in divides
209 reg_class nadx_reg_with_ebp(EBX, ECX, ESI, EDI, EBP);
210 // Not AX or DX (and neither EBP), used in divides
211 reg_class nadx_reg_no_ebp(EBX, ECX, ESI, EDI);
212 // Dynamic register class that selects between nadx_reg and nadx_reg_no_ebp.
213 reg_class_dynamic nadx_reg(nadx_reg_no_ebp, nadx_reg_with_ebp, %{ PreserveFramePointer %});
214
215 // Floating point registers. Notice FPR0 is not a choice.
216 // FPR0 is not ever allocated; we use clever encodings to fake
217 // a 2-address instructions out of Intels FP stack.
218 reg_class fp_flt_reg( FPR1L,FPR2L,FPR3L,FPR4L,FPR5L,FPR6L,FPR7L );
219
220 reg_class fp_dbl_reg( FPR1L,FPR1H, FPR2L,FPR2H, FPR3L,FPR3H,
221 FPR4L,FPR4H, FPR5L,FPR5H, FPR6L,FPR6H,
222 FPR7L,FPR7H );
223
224 reg_class fp_flt_reg0( FPR1L );
225 reg_class fp_dbl_reg0( FPR1L,FPR1H );
226 reg_class fp_dbl_reg1( FPR2L,FPR2H );
227 reg_class fp_dbl_notreg0( FPR2L,FPR2H, FPR3L,FPR3H, FPR4L,FPR4H,
228 FPR5L,FPR5H, FPR6L,FPR6H, FPR7L,FPR7H );
229
230 %}
231
232
233 //----------SOURCE BLOCK-------------------------------------------------------
267
268 // Static initialization during VM startup.
269 static jlong *float_signmask_pool = double_quadword(&fp_signmask_pool[1*2], CONST64(0x7FFFFFFF7FFFFFFF), CONST64(0x7FFFFFFF7FFFFFFF));
270 static jlong *double_signmask_pool = double_quadword(&fp_signmask_pool[2*2], CONST64(0x7FFFFFFFFFFFFFFF), CONST64(0x7FFFFFFFFFFFFFFF));
271 static jlong *float_signflip_pool = double_quadword(&fp_signmask_pool[3*2], CONST64(0x8000000080000000), CONST64(0x8000000080000000));
272 static jlong *double_signflip_pool = double_quadword(&fp_signmask_pool[4*2], CONST64(0x8000000000000000), CONST64(0x8000000000000000));
273
274 // Offset hacking within calls.
275 static int pre_call_resets_size() {
276 int size = 0;
277 Compile* C = Compile::current();
278 if (C->in_24_bit_fp_mode()) {
279 size += 6; // fldcw
280 }
281 if (C->max_vector_size() > 16) {
282 size += 3; // vzeroupper
283 }
284 return size;
285 }
286
287 // !!!!! Special hack to get all type of calls to specify the byte offset
288 // from the start of the call to the point where the return address
289 // will point.
290 int MachCallStaticJavaNode::ret_addr_offset() {
291 return 5 + pre_call_resets_size(); // 5 bytes from start of call to where return address points
292 }
293
294 int MachCallDynamicJavaNode::ret_addr_offset() {
295 return 10 + pre_call_resets_size(); // 10 bytes from start of call to where return address points
296 }
297
298 static int sizeof_FFree_Float_Stack_All = -1;
299
300 int MachCallRuntimeNode::ret_addr_offset() {
301 assert(sizeof_FFree_Float_Stack_All != -1, "must have been emitted already");
302 return sizeof_FFree_Float_Stack_All + 5 + pre_call_resets_size();
303 }
304
305 // Indicate if the safepoint node needs the polling page as an input.
306 // Since x86 does have absolute addressing, it doesn't.
307 bool SafePointNode::needs_polling_address_input() {
308 return false;
309 }
310
311 //
312 // Compute padding required for nodes which need alignment
313 //
314
315 // The address of the call instruction needs to be 4-byte aligned to
316 // ensure that it does not span a cache line so that it can be patched.
317 int CallStaticJavaDirectNode::compute_padding(int current_offset) const {
318 current_offset += pre_call_resets_size(); // skip fldcw, if any
319 current_offset += 1; // skip call opcode byte
320 return round_to(current_offset, alignment_required()) - current_offset;
321 }
322
323 // The address of the call instruction needs to be 4-byte aligned to
324 // ensure that it does not span a cache line so that it can be patched.
325 int CallDynamicJavaDirectNode::compute_padding(int current_offset) const {
326 current_offset += pre_call_resets_size(); // skip fldcw, if any
327 current_offset += 5; // skip MOV instruction
328 current_offset += 1; // skip call opcode byte
329 return round_to(current_offset, alignment_required()) - current_offset;
330 }
331
332 // EMIT_RM()
333 void emit_rm(CodeBuffer &cbuf, int f1, int f2, int f3) {
334 unsigned char c = (unsigned char)((f1 << 6) | (f2 << 3) | f3);
335 cbuf.insts()->emit_int8(c);
336 }
337
338 // EMIT_CC()
339 void emit_cc(CodeBuffer &cbuf, int f1, int f2) {
340 unsigned char c = (unsigned char)( f1 | f2 );
341 cbuf.insts()->emit_int8(c);
342 }
343
344 // EMIT_OPCODE()
534 }
535 #endif
536
537
538 //=============================================================================
539 #ifndef PRODUCT
540 void MachPrologNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
541 Compile* C = ra_->C;
542
543 int framesize = C->frame_size_in_bytes();
544 int bangsize = C->bang_size_in_bytes();
545 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
546 // Remove wordSize for return addr which is already pushed.
547 framesize -= wordSize;
548
549 if (C->need_stack_bang(bangsize)) {
550 framesize -= wordSize;
551 st->print("# stack bang (%d bytes)", bangsize);
552 st->print("\n\t");
553 st->print("PUSH EBP\t# Save EBP");
554 if (PreserveFramePointer) {
555 st->print("\n\t");
556 st->print("MOV EBP, ESP\t# Save the caller's SP into EBP");
557 }
558 if (framesize) {
559 st->print("\n\t");
560 st->print("SUB ESP, #%d\t# Create frame",framesize);
561 }
562 } else {
563 st->print("SUB ESP, #%d\t# Create frame",framesize);
564 st->print("\n\t");
565 framesize -= wordSize;
566 st->print("MOV [ESP + #%d], EBP\t# Save EBP",framesize);
567 if (PreserveFramePointer) {
568 st->print("\n\t");
569 st->print("MOV EBP, [ESP + #%d]\t# Save the caller's SP into EBP", (framesize + wordSize));
570 }
571 }
572
573 if (VerifyStackAtCalls) {
574 st->print("\n\t");
575 framesize -= wordSize;
576 st->print("MOV [ESP + #%d], 0xBADB100D\t# Majik cookie for stack depth check",framesize);
577 }
578
579 if( C->in_24_bit_fp_mode() ) {
580 st->print("\n\t");
581 st->print("FLDCW \t# load 24 bit fpu control word");
582 }
583 if (UseSSE >= 2 && VerifyFPU) {
584 st->print("\n\t");
585 st->print("# verify FPU stack (must be clean on entry)");
586 }
587
588 #ifdef ASSERT
589 if (VerifyStackAtCalls) {
590 st->print("\n\t");
1507 }
1508
1509 // Register for MODI projection of divmodI
1510 RegMask Matcher::modI_proj_mask() {
1511 return EDX_REG_mask();
1512 }
1513
1514 // Register for DIVL projection of divmodL
1515 RegMask Matcher::divL_proj_mask() {
1516 ShouldNotReachHere();
1517 return RegMask();
1518 }
1519
1520 // Register for MODL projection of divmodL
1521 RegMask Matcher::modL_proj_mask() {
1522 ShouldNotReachHere();
1523 return RegMask();
1524 }
1525
1526 const RegMask Matcher::method_handle_invoke_SP_save_mask() {
1527 return NO_REG_mask();
1528 }
1529
1530 // Returns true if the high 32 bits of the value is known to be zero.
1531 bool is_operand_hi32_zero(Node* n) {
1532 int opc = n->Opcode();
1533 if (opc == Op_AndL) {
1534 Node* o2 = n->in(2);
1535 if (o2->is_Con() && (o2->get_long() & 0xFFFFFFFF00000000LL) == 0LL) {
1536 return true;
1537 }
1538 }
1539 if (opc == Op_ConL && (n->get_long() & 0xFFFFFFFF00000000LL) == 0LL) {
1540 return true;
1541 }
1542 return false;
1543 }
1544
1545 %}
1546
1547 //----------ENCODING BLOCK-----------------------------------------------------
3753 match(eRegP);
3754
3755 format %{ %}
3756 interface(REG_INTER);
3757 %}
3758
3759 operand eRegP() %{
3760 constraint(ALLOC_IN_RC(int_reg));
3761 match(RegP);
3762 match(eAXRegP);
3763 match(eBXRegP);
3764 match(eCXRegP);
3765 match(eDIRegP);
3766
3767 format %{ %}
3768 interface(REG_INTER);
3769 %}
3770
3771 // On windows95, EBP is not safe to use for implicit null tests.
3772 operand eRegP_no_EBP() %{
3773 constraint(ALLOC_IN_RC(int_reg_no_ebp));
3774 match(RegP);
3775 match(eAXRegP);
3776 match(eBXRegP);
3777 match(eCXRegP);
3778 match(eDIRegP);
3779
3780 op_cost(100);
3781 format %{ %}
3782 interface(REG_INTER);
3783 %}
3784
3785 operand naxRegP() %{
3786 constraint(ALLOC_IN_RC(nax_reg));
3787 match(RegP);
3788 match(eBXRegP);
3789 match(eDXRegP);
3790 match(eCXRegP);
3791 match(eSIRegP);
3792 match(eDIRegP);
3793
3842 match(reg);
3843 format %{ "ECX" %}
3844 interface(REG_INTER);
3845 %}
3846
3847 operand eSIRegP(eRegP reg) %{
3848 constraint(ALLOC_IN_RC(esi_reg));
3849 match(reg);
3850 format %{ "ESI" %}
3851 interface(REG_INTER);
3852 %}
3853
3854 // Used in rep stosw
3855 operand eDIRegP(eRegP reg) %{
3856 constraint(ALLOC_IN_RC(edi_reg));
3857 match(reg);
3858 format %{ "EDI" %}
3859 interface(REG_INTER);
3860 %}
3861
3862 operand eRegL() %{
3863 constraint(ALLOC_IN_RC(long_reg));
3864 match(RegL);
3865 match(eADXRegL);
3866
3867 format %{ %}
3868 interface(REG_INTER);
3869 %}
3870
3871 operand eADXRegL( eRegL reg ) %{
3872 constraint(ALLOC_IN_RC(eadx_reg));
3873 match(reg);
3874
3875 format %{ "EDX:EAX" %}
3876 interface(REG_INTER);
3877 %}
3878
3879 operand eBCXRegL( eRegL reg ) %{
3880 constraint(ALLOC_IN_RC(ebcx_reg));
3881 match(reg);
12720 %}
12721
12722
12723 instruct cmovFF_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regF dst, regF src) %{
12724 predicate( UseSSE>=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt );
12725 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
12726 ins_cost(200);
12727 expand %{
12728 fcmovF_regS(cmp,flags,dst,src);
12729 %}
12730 %}
12731
12732
12733 // ============================================================================
12734 // Procedure Call/Return Instructions
12735 // Call Java Static Instruction
12736 // Note: If this code changes, the corresponding ret_addr_offset() and
12737 // compute_padding() functions will have to be adjusted.
12738 instruct CallStaticJavaDirect(method meth) %{
12739 match(CallStaticJava);
12740 effect(USE meth);
12741
12742 ins_cost(300);
12743 format %{ "CALL,static " %}
12744 opcode(0xE8); /* E8 cd */
12745 ins_encode( pre_call_resets,
12746 Java_Static_Call( meth ),
12747 call_epilog,
12748 post_call_FPU );
12749 ins_pipe( pipe_slow );
12750 ins_alignment(4);
12751 %}
12752
12753 // Call Java Dynamic Instruction
12754 // Note: If this code changes, the corresponding ret_addr_offset() and
12755 // compute_padding() functions will have to be adjusted.
12756 instruct CallDynamicJavaDirect(method meth) %{
12757 match(CallDynamicJava);
12758 effect(USE meth);
12759
12760 ins_cost(300);
12761 format %{ "MOV EAX,(oop)-1\n\t"
12762 "CALL,dynamic" %}
12763 opcode(0xE8); /* E8 cd */
12764 ins_encode( pre_call_resets,
12765 Java_Dynamic_Call( meth ),
12766 call_epilog,
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