src/cpu/x86/vm/assembler_x86.hpp
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src/cpu/x86/vm/assembler_x86.hpp

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rev 7386 : 8068945: Use RBP register as proper frame pointer in JIT compiled code on x86
Summary: Introduce the PreserveFramePointer flag to control if RBP is used as the frame pointer or as a general purpose register.
Reviewed-by: kvn, roland, dlong, enevill, shade


 124 REGISTER_DECLARATION(XMMRegister, j_farg4, xmm4);
 125 REGISTER_DECLARATION(XMMRegister, j_farg5, xmm5);
 126 REGISTER_DECLARATION(XMMRegister, j_farg6, xmm6);
 127 REGISTER_DECLARATION(XMMRegister, j_farg7, xmm7);
 128 
 129 REGISTER_DECLARATION(Register, rscratch1, r10);  // volatile
 130 REGISTER_DECLARATION(Register, rscratch2, r11);  // volatile
 131 
 132 REGISTER_DECLARATION(Register, r12_heapbase, r12); // callee-saved
 133 REGISTER_DECLARATION(Register, r15_thread, r15); // callee-saved
 134 
 135 #else
 136 // rscratch1 will apear in 32bit code that is dead but of course must compile
 137 // Using noreg ensures if the dead code is incorrectly live and executed it
 138 // will cause an assertion failure
 139 #define rscratch1 noreg
 140 #define rscratch2 noreg
 141 
 142 #endif // _LP64
 143 
 144 // JSR 292 fixed register usages:
 145 REGISTER_DECLARATION(Register, rbp_mh_SP_save, rbp);


 146 
 147 // Address is an abstraction used to represent a memory location
 148 // using any of the amd64 addressing modes with one object.
 149 //
 150 // Note: A register location is represented via a Register, not
 151 //       via an address for efficiency & simplicity reasons.
 152 
 153 class ArrayAddress;
 154 
 155 class Address VALUE_OBJ_CLASS_SPEC {
 156  public:
 157   enum ScaleFactor {
 158     no_scale = -1,
 159     times_1  =  0,
 160     times_2  =  1,
 161     times_4  =  2,
 162     times_8  =  3,
 163     times_ptr = LP64_ONLY(times_8) NOT_LP64(times_4)
 164   };
 165   static ScaleFactor times(int size) {




 124 REGISTER_DECLARATION(XMMRegister, j_farg4, xmm4);
 125 REGISTER_DECLARATION(XMMRegister, j_farg5, xmm5);
 126 REGISTER_DECLARATION(XMMRegister, j_farg6, xmm6);
 127 REGISTER_DECLARATION(XMMRegister, j_farg7, xmm7);
 128 
 129 REGISTER_DECLARATION(Register, rscratch1, r10);  // volatile
 130 REGISTER_DECLARATION(Register, rscratch2, r11);  // volatile
 131 
 132 REGISTER_DECLARATION(Register, r12_heapbase, r12); // callee-saved
 133 REGISTER_DECLARATION(Register, r15_thread, r15); // callee-saved
 134 
 135 #else
 136 // rscratch1 will apear in 32bit code that is dead but of course must compile
 137 // Using noreg ensures if the dead code is incorrectly live and executed it
 138 // will cause an assertion failure
 139 #define rscratch1 noreg
 140 #define rscratch2 noreg
 141 
 142 #endif // _LP64
 143 
 144 // JSR 292
 145 // On x86, the SP does not have to be saved when invoking method handle intrinsics
 146 // or compiled lambda forms. We indicate that by setting rbp_mh_SP_save to noreg.
 147 REGISTER_DECLARATION(Register, rbp_mh_SP_save, noreg);
 148 
 149 // Address is an abstraction used to represent a memory location
 150 // using any of the amd64 addressing modes with one object.
 151 //
 152 // Note: A register location is represented via a Register, not
 153 //       via an address for efficiency & simplicity reasons.
 154 
 155 class ArrayAddress;
 156 
 157 class Address VALUE_OBJ_CLASS_SPEC {
 158  public:
 159   enum ScaleFactor {
 160     no_scale = -1,
 161     times_1  =  0,
 162     times_2  =  1,
 163     times_4  =  2,
 164     times_8  =  3,
 165     times_ptr = LP64_ONLY(times_8) NOT_LP64(times_4)
 166   };
 167   static ScaleFactor times(int size) {


src/cpu/x86/vm/assembler_x86.hpp
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