1 /*
2 * Copyright (c) 1997, 2020, Oracle and/or its affiliates. All rights reserved.
3 * Copyright (c) 2015, 2020, Red Hat Inc. All rights reserved.
4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
5 *
6 * This code is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 only, as
8 * published by the Free Software Foundation.
9 *
10 * This code is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * version 2 for more details (a copy is included in the LICENSE file that
14 * accompanied this code).
15 *
16 * You should have received a copy of the GNU General Public License version
17 * 2 along with this work; if not, write to the Free Software Foundation,
18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 * or visit www.oracle.com if you need additional information or have any
22 * questions.
23 *
24 */
25
26 #include "precompiled.hpp"
27 #include "asm/macroAssembler.hpp"
28 #include "asm/macroAssembler.inline.hpp"
29 #include "memory/resourceArea.hpp"
30 #include "runtime/java.hpp"
31 #include "runtime/os.hpp"
32 #include "runtime/stubCodeGenerator.hpp"
33 #include "runtime/vm_version.hpp"
34 #include "utilities/macros.hpp"
35
36 #include OS_HEADER_INLINE(os)
37
38 #include <sys/auxv.h>
39 #include <asm/hwcap.h>
40
41 #ifndef HWCAP_AES
42 #define HWCAP_AES (1<<3)
43 #endif
44
45 #ifndef HWCAP_PMULL
46 #define HWCAP_PMULL (1<<4)
47 #endif
48
49 #ifndef HWCAP_SHA1
50 #define HWCAP_SHA1 (1<<5)
51 #endif
52
53 #ifndef HWCAP_SHA2
54 #define HWCAP_SHA2 (1<<6)
55 #endif
56
57 #ifndef HWCAP_CRC32
58 #define HWCAP_CRC32 (1<<7)
59 #endif
60
61 #ifndef HWCAP_ATOMICS
62 #define HWCAP_ATOMICS (1<<8)
63 #endif
64
65 int VM_Version::_cpu;
66 int VM_Version::_model;
67 int VM_Version::_model2;
68 int VM_Version::_variant;
69 int VM_Version::_revision;
70 int VM_Version::_stepping;
71 bool VM_Version::_dcpop;
72 VM_Version::PsrInfo VM_Version::_psr_info = { 0, };
73
74 static BufferBlob* stub_blob;
75 static const int stub_size = 550;
76
77 extern "C" {
78 typedef void (*getPsrInfo_stub_t)(void*);
79 }
80 static getPsrInfo_stub_t getPsrInfo_stub = NULL;
81
82
83 class VM_Version_StubGenerator: public StubCodeGenerator {
84 public:
85
86 VM_Version_StubGenerator(CodeBuffer *c) : StubCodeGenerator(c) {}
87
88 address generate_getPsrInfo() {
89 StubCodeMark mark(this, "VM_Version", "getPsrInfo_stub");
90 # define __ _masm->
91 address start = __ pc();
92
93 // void getPsrInfo(VM_Version::PsrInfo* psr_info);
94
95 address entry = __ pc();
96
97 __ enter();
98
99 __ get_dczid_el0(rscratch1);
100 __ strw(rscratch1, Address(c_rarg0, in_bytes(VM_Version::dczid_el0_offset())));
101
102 __ get_ctr_el0(rscratch1);
103 __ strw(rscratch1, Address(c_rarg0, in_bytes(VM_Version::ctr_el0_offset())));
104
105 __ leave();
106 __ ret(lr);
107
108 # undef __
109
110 return start;
111 }
112 };
113
114
115 void VM_Version::get_processor_features() {
116 _supports_cx8 = true;
117 _supports_atomic_getset4 = true;
118 _supports_atomic_getadd4 = true;
119 _supports_atomic_getset8 = true;
120 _supports_atomic_getadd8 = true;
121
122 getPsrInfo_stub(&_psr_info);
123
124 int dcache_line = VM_Version::dcache_line_size();
125
126 // Limit AllocatePrefetchDistance so that it does not exceed the
127 // constraint in AllocatePrefetchDistanceConstraintFunc.
128 if (FLAG_IS_DEFAULT(AllocatePrefetchDistance))
129 FLAG_SET_DEFAULT(AllocatePrefetchDistance, MIN2(512, 3*dcache_line));
130
131 if (FLAG_IS_DEFAULT(AllocatePrefetchStepSize))
132 FLAG_SET_DEFAULT(AllocatePrefetchStepSize, dcache_line);
133 if (FLAG_IS_DEFAULT(PrefetchScanIntervalInBytes))
134 FLAG_SET_DEFAULT(PrefetchScanIntervalInBytes, 3*dcache_line);
135 if (FLAG_IS_DEFAULT(PrefetchCopyIntervalInBytes))
136 FLAG_SET_DEFAULT(PrefetchCopyIntervalInBytes, 3*dcache_line);
137 if (FLAG_IS_DEFAULT(SoftwarePrefetchHintDistance))
138 FLAG_SET_DEFAULT(SoftwarePrefetchHintDistance, 3*dcache_line);
139
140 if (PrefetchCopyIntervalInBytes != -1 &&
141 ((PrefetchCopyIntervalInBytes & 7) || (PrefetchCopyIntervalInBytes >= 32768))) {
142 warning("PrefetchCopyIntervalInBytes must be -1, or a multiple of 8 and < 32768");
143 PrefetchCopyIntervalInBytes &= ~7;
144 if (PrefetchCopyIntervalInBytes >= 32768)
145 PrefetchCopyIntervalInBytes = 32760;
146 }
147
148 if (AllocatePrefetchDistance !=-1 && (AllocatePrefetchDistance & 7)) {
149 warning("AllocatePrefetchDistance must be multiple of 8");
150 AllocatePrefetchDistance &= ~7;
151 }
152
153 if (AllocatePrefetchStepSize & 7) {
154 warning("AllocatePrefetchStepSize must be multiple of 8");
155 AllocatePrefetchStepSize &= ~7;
156 }
157
158 if (SoftwarePrefetchHintDistance != -1 &&
159 (SoftwarePrefetchHintDistance & 7)) {
160 warning("SoftwarePrefetchHintDistance must be -1, or a multiple of 8");
161 SoftwarePrefetchHintDistance &= ~7;
162 }
163
164 unsigned long auxv = getauxval(AT_HWCAP);
165
166 char buf[512];
167
168 _features = auxv;
169
170 int cpu_lines = 0;
171 if (FILE *f = fopen("/proc/cpuinfo", "r")) {
172 // need a large buffer as the flags line may include lots of text
173 char buf[1024], *p;
174 while (fgets(buf, sizeof (buf), f) != NULL) {
175 if ((p = strchr(buf, ':')) != NULL) {
176 long v = strtol(p+1, NULL, 0);
177 if (strncmp(buf, "CPU implementer", sizeof "CPU implementer" - 1) == 0) {
178 _cpu = v;
179 cpu_lines++;
180 } else if (strncmp(buf, "CPU variant", sizeof "CPU variant" - 1) == 0) {
181 _variant = v;
182 } else if (strncmp(buf, "CPU part", sizeof "CPU part" - 1) == 0) {
183 if (_model != v) _model2 = _model;
184 _model = v;
185 } else if (strncmp(buf, "CPU revision", sizeof "CPU revision" - 1) == 0) {
186 _revision = v;
187 } else if (strncmp(buf, "flags", sizeof("flags") - 1) == 0) {
188 if (strstr(p+1, "dcpop")) {
189 _dcpop = true;
190 }
191 }
192 }
193 }
194 fclose(f);
195 }
196
197 if (os::supports_map_sync()) {
198 // if dcpop is available publish data cache line flush size via
199 // generic field, otherwise let if default to zero thereby
200 // disabling writeback
201 if (_dcpop) {
202 _data_cache_line_flush_size = dcache_line;
203 }
204 }
205
206 // Enable vendor specific features
207
208 // Ampere eMAG
209 if (_cpu == CPU_AMCC && (_model == 0) && (_variant == 0x3)) {
210 if (FLAG_IS_DEFAULT(AvoidUnalignedAccesses)) {
211 FLAG_SET_DEFAULT(AvoidUnalignedAccesses, true);
212 }
213 if (FLAG_IS_DEFAULT(UseSIMDForMemoryOps)) {
214 FLAG_SET_DEFAULT(UseSIMDForMemoryOps, true);
215 }
216 if (FLAG_IS_DEFAULT(UseSIMDForArrayEquals)) {
217 FLAG_SET_DEFAULT(UseSIMDForArrayEquals, !(_revision == 1 || _revision == 2));
218 }
219 }
220
221 // ThunderX
222 if (_cpu == CPU_CAVIUM && (_model == 0xA1)) {
223 guarantee(_variant != 0, "Pre-release hardware no longer supported.");
224 if (FLAG_IS_DEFAULT(AvoidUnalignedAccesses)) {
225 FLAG_SET_DEFAULT(AvoidUnalignedAccesses, true);
226 }
227 if (FLAG_IS_DEFAULT(UseSIMDForMemoryOps)) {
228 FLAG_SET_DEFAULT(UseSIMDForMemoryOps, (_variant > 0));
229 }
230 if (FLAG_IS_DEFAULT(UseSIMDForArrayEquals)) {
231 FLAG_SET_DEFAULT(UseSIMDForArrayEquals, false);
232 }
233 }
234
235 // ThunderX2
236 if ((_cpu == CPU_CAVIUM && (_model == 0xAF)) ||
237 (_cpu == CPU_BROADCOM && (_model == 0x516))) {
238 if (FLAG_IS_DEFAULT(AvoidUnalignedAccesses)) {
239 FLAG_SET_DEFAULT(AvoidUnalignedAccesses, true);
240 }
241 if (FLAG_IS_DEFAULT(UseSIMDForMemoryOps)) {
242 FLAG_SET_DEFAULT(UseSIMDForMemoryOps, true);
243 }
244 }
245
246 // HiSilicon TSV110
247 if (_cpu == CPU_HISILICON && _model == 0xd01) {
248 if (FLAG_IS_DEFAULT(AvoidUnalignedAccesses)) {
249 FLAG_SET_DEFAULT(AvoidUnalignedAccesses, true);
250 }
251 if (FLAG_IS_DEFAULT(UseSIMDForMemoryOps)) {
252 FLAG_SET_DEFAULT(UseSIMDForMemoryOps, true);
253 }
254 }
255
256 // Cortex A53
257 if (_cpu == CPU_ARM && (_model == 0xd03 || _model2 == 0xd03)) {
258 _features |= CPU_A53MAC;
259 if (FLAG_IS_DEFAULT(UseSIMDForArrayEquals)) {
260 FLAG_SET_DEFAULT(UseSIMDForArrayEquals, false);
261 }
262 }
263
264 // Cortex A73
265 if (_cpu == CPU_ARM && (_model == 0xd09 || _model2 == 0xd09)) {
266 if (FLAG_IS_DEFAULT(SoftwarePrefetchHintDistance)) {
267 FLAG_SET_DEFAULT(SoftwarePrefetchHintDistance, -1);
268 }
269 // A73 is faster with short-and-easy-for-speculative-execution-loop
270 if (FLAG_IS_DEFAULT(UseSimpleArrayEquals)) {
271 FLAG_SET_DEFAULT(UseSimpleArrayEquals, true);
272 }
273 }
274
275 if (_cpu == CPU_ARM && (_model == 0xd07 || _model2 == 0xd07)) _features |= CPU_STXR_PREFETCH;
276 // If an olde style /proc/cpuinfo (cpu_lines == 1) then if _model is an A57 (0xd07)
277 // we assume the worst and assume we could be on a big little system and have
278 // undisclosed A53 cores which we could be swapped to at any stage
279 if (_cpu == CPU_ARM && cpu_lines == 1 && _model == 0xd07) _features |= CPU_A53MAC;
280
281 sprintf(buf, "0x%02x:0x%x:0x%03x:%d", _cpu, _variant, _model, _revision);
282 if (_model2) sprintf(buf+strlen(buf), "(0x%03x)", _model2);
283 if (auxv & HWCAP_ASIMD) strcat(buf, ", simd");
284 if (auxv & HWCAP_CRC32) strcat(buf, ", crc");
285 if (auxv & HWCAP_AES) strcat(buf, ", aes");
286 if (auxv & HWCAP_SHA1) strcat(buf, ", sha1");
287 if (auxv & HWCAP_SHA2) strcat(buf, ", sha256");
288 if (auxv & HWCAP_ATOMICS) strcat(buf, ", lse");
289
290 _features_string = os::strdup(buf);
291
292 if (FLAG_IS_DEFAULT(UseCRC32)) {
293 UseCRC32 = (auxv & HWCAP_CRC32) != 0;
294 }
295
296 if (UseCRC32 && (auxv & HWCAP_CRC32) == 0) {
297 warning("UseCRC32 specified, but not supported on this CPU");
298 FLAG_SET_DEFAULT(UseCRC32, false);
299 }
300
301 if (FLAG_IS_DEFAULT(UseAdler32Intrinsics)) {
302 FLAG_SET_DEFAULT(UseAdler32Intrinsics, true);
303 }
304
305 if (UseVectorizedMismatchIntrinsic) {
306 warning("UseVectorizedMismatchIntrinsic specified, but not available on this CPU.");
307 FLAG_SET_DEFAULT(UseVectorizedMismatchIntrinsic, false);
308 }
309
310 if (auxv & HWCAP_ATOMICS) {
311 if (FLAG_IS_DEFAULT(UseLSE))
312 FLAG_SET_DEFAULT(UseLSE, true);
313 } else {
314 if (UseLSE) {
315 warning("UseLSE specified, but not supported on this CPU");
316 FLAG_SET_DEFAULT(UseLSE, false);
317 }
318 }
319
320 if (auxv & HWCAP_AES) {
321 UseAES = UseAES || FLAG_IS_DEFAULT(UseAES);
322 UseAESIntrinsics =
323 UseAESIntrinsics || (UseAES && FLAG_IS_DEFAULT(UseAESIntrinsics));
324 if (UseAESIntrinsics && !UseAES) {
325 warning("UseAESIntrinsics enabled, but UseAES not, enabling");
326 UseAES = true;
327 }
328 } else {
329 if (UseAES) {
330 warning("AES instructions are not available on this CPU");
331 FLAG_SET_DEFAULT(UseAES, false);
332 }
333 if (UseAESIntrinsics) {
334 warning("AES intrinsics are not available on this CPU");
335 FLAG_SET_DEFAULT(UseAESIntrinsics, false);
336 }
337 }
338
339 if (UseAESCTRIntrinsics) {
340 warning("AES/CTR intrinsics are not available on this CPU");
341 FLAG_SET_DEFAULT(UseAESCTRIntrinsics, false);
342 }
343
344 if (FLAG_IS_DEFAULT(UseCRC32Intrinsics)) {
345 UseCRC32Intrinsics = true;
346 }
347
348 if (auxv & HWCAP_CRC32) {
349 if (FLAG_IS_DEFAULT(UseCRC32CIntrinsics)) {
350 FLAG_SET_DEFAULT(UseCRC32CIntrinsics, true);
351 }
352 } else if (UseCRC32CIntrinsics) {
353 warning("CRC32C is not available on the CPU");
354 FLAG_SET_DEFAULT(UseCRC32CIntrinsics, false);
355 }
356
357 if (FLAG_IS_DEFAULT(UseFMA)) {
358 FLAG_SET_DEFAULT(UseFMA, true);
359 }
360
361 if (auxv & (HWCAP_SHA1 | HWCAP_SHA2)) {
362 if (FLAG_IS_DEFAULT(UseSHA)) {
363 FLAG_SET_DEFAULT(UseSHA, true);
364 }
365 } else if (UseSHA) {
366 warning("SHA instructions are not available on this CPU");
367 FLAG_SET_DEFAULT(UseSHA, false);
368 }
369
370 if (UseSHA && (auxv & HWCAP_SHA1)) {
371 if (FLAG_IS_DEFAULT(UseSHA1Intrinsics)) {
372 FLAG_SET_DEFAULT(UseSHA1Intrinsics, true);
373 }
374 } else if (UseSHA1Intrinsics) {
375 warning("Intrinsics for SHA-1 crypto hash functions not available on this CPU.");
376 FLAG_SET_DEFAULT(UseSHA1Intrinsics, false);
377 }
378
379 if (UseSHA && (auxv & HWCAP_SHA2)) {
380 if (FLAG_IS_DEFAULT(UseSHA256Intrinsics)) {
381 FLAG_SET_DEFAULT(UseSHA256Intrinsics, true);
382 }
383 } else if (UseSHA256Intrinsics) {
384 warning("Intrinsics for SHA-224 and SHA-256 crypto hash functions not available on this CPU.");
385 FLAG_SET_DEFAULT(UseSHA256Intrinsics, false);
386 }
387
388 if (UseSHA512Intrinsics) {
389 warning("Intrinsics for SHA-384 and SHA-512 crypto hash functions not available on this CPU.");
390 FLAG_SET_DEFAULT(UseSHA512Intrinsics, false);
391 }
392
393 if (!(UseSHA1Intrinsics || UseSHA256Intrinsics || UseSHA512Intrinsics)) {
394 FLAG_SET_DEFAULT(UseSHA, false);
395 }
396
397 if (auxv & HWCAP_PMULL) {
398 if (FLAG_IS_DEFAULT(UseGHASHIntrinsics)) {
399 FLAG_SET_DEFAULT(UseGHASHIntrinsics, true);
400 }
401 } else if (UseGHASHIntrinsics) {
402 warning("GHASH intrinsics are not available on this CPU");
403 FLAG_SET_DEFAULT(UseGHASHIntrinsics, false);
404 }
405
406 if (is_zva_enabled()) {
407 if (FLAG_IS_DEFAULT(UseBlockZeroing)) {
408 FLAG_SET_DEFAULT(UseBlockZeroing, true);
409 }
410 if (FLAG_IS_DEFAULT(BlockZeroingLowLimit)) {
411 FLAG_SET_DEFAULT(BlockZeroingLowLimit, 4 * VM_Version::zva_length());
412 }
413 } else if (UseBlockZeroing) {
414 warning("DC ZVA is not available on this CPU");
415 FLAG_SET_DEFAULT(UseBlockZeroing, false);
416 }
417
418 // This machine allows unaligned memory accesses
419 if (FLAG_IS_DEFAULT(UseUnalignedAccesses)) {
420 FLAG_SET_DEFAULT(UseUnalignedAccesses, true);
421 }
422
423 if (FLAG_IS_DEFAULT(UsePopCountInstruction)) {
424 FLAG_SET_DEFAULT(UsePopCountInstruction, true);
425 }
426
427 if (!UsePopCountInstruction) {
428 warning("UsePopCountInstruction is always enabled on this CPU");
429 UsePopCountInstruction = true;
430 }
431
432 #ifdef COMPILER2
433 if (FLAG_IS_DEFAULT(UseMultiplyToLenIntrinsic)) {
434 UseMultiplyToLenIntrinsic = true;
435 }
436
437 if (FLAG_IS_DEFAULT(UseSquareToLenIntrinsic)) {
438 UseSquareToLenIntrinsic = true;
439 }
440
441 if (FLAG_IS_DEFAULT(UseMulAddIntrinsic)) {
442 UseMulAddIntrinsic = true;
443 }
444
445 if (FLAG_IS_DEFAULT(UseMontgomeryMultiplyIntrinsic)) {
446 UseMontgomeryMultiplyIntrinsic = true;
447 }
448 if (FLAG_IS_DEFAULT(UseMontgomerySquareIntrinsic)) {
449 UseMontgomerySquareIntrinsic = true;
450 }
451
452 int min_vector_size = 8;
453
454 if (!FLAG_IS_DEFAULT(MaxVectorSize)) {
455 if (MaxVectorSize < min_vector_size) {
456 warning("MaxVectorSize must be at least %i on this platform", min_vector_size);
457 FLAG_SET_DEFAULT(MaxVectorSize, min_vector_size);
458 }
459 }
460
461 if (FLAG_IS_DEFAULT(OptoScheduling)) {
462 OptoScheduling = true;
463 }
464
465 if (FLAG_IS_DEFAULT(AlignVector)) {
466 AlignVector = AvoidUnalignedAccesses;
467 }
468 #endif
469 }
470
471 void VM_Version::initialize() {
472 ResourceMark rm;
473
474 stub_blob = BufferBlob::create("getPsrInfo_stub", stub_size);
475 if (stub_blob == NULL) {
476 vm_exit_during_initialization("Unable to allocate getPsrInfo_stub");
477 }
478
479 CodeBuffer c(stub_blob);
480 VM_Version_StubGenerator g(&c);
481 getPsrInfo_stub = CAST_TO_FN_PTR(getPsrInfo_stub_t,
482 g.generate_getPsrInfo());
483
484 get_processor_features();
485
486 UNSUPPORTED_OPTION(CriticalJNINatives);
487 }