1 /*
2 * Copyright (c) 1997, 2020, Oracle and/or its affiliates. All rights reserved.
3 * Copyright (c) 2014, 2020, Red Hat Inc. All rights reserved.
4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
5 *
6 * This code is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 only, as
8 * published by the Free Software Foundation.
9 *
10 * This code is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * version 2 for more details (a copy is included in the LICENSE file that
14 * accompanied this code).
15 *
16 * You should have received a copy of the GNU General Public License version
17 * 2 along with this work; if not, write to the Free Software Foundation,
18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 * or visit www.oracle.com if you need additional information or have any
22 * questions.
23 *
24 */
25
26 #ifndef CPU_AARCH64_ASSEMBLER_AARCH64_HPP
27 #define CPU_AARCH64_ASSEMBLER_AARCH64_HPP
28
29 #include "asm/register.hpp"
30
31 // definitions of various symbolic names for machine registers
32
33 // First intercalls between C and Java which use 8 general registers
34 // and 8 floating registers
35
36 // we also have to copy between x86 and ARM registers but that's a
37 // secondary complication -- not all code employing C call convention
38 // executes as x86 code though -- we generate some of it
39
40 class Argument {
41 public:
42 enum {
43 n_int_register_parameters_c = 8, // r0, r1, ... r7 (c_rarg0, c_rarg1, ...)
44 n_float_register_parameters_c = 8, // v0, v1, ... v7 (c_farg0, c_farg1, ... )
45
46 n_int_register_parameters_j = 8, // r1, ... r7, r0 (rj_rarg0, j_rarg1, ...
47 n_float_register_parameters_j = 8 // v0, v1, ... v7 (j_farg0, j_farg1, ...
48 };
49 };
50
51 REGISTER_DECLARATION(Register, c_rarg0, r0);
52 REGISTER_DECLARATION(Register, c_rarg1, r1);
53 REGISTER_DECLARATION(Register, c_rarg2, r2);
54 REGISTER_DECLARATION(Register, c_rarg3, r3);
55 REGISTER_DECLARATION(Register, c_rarg4, r4);
56 REGISTER_DECLARATION(Register, c_rarg5, r5);
57 REGISTER_DECLARATION(Register, c_rarg6, r6);
58 REGISTER_DECLARATION(Register, c_rarg7, r7);
59
60 REGISTER_DECLARATION(FloatRegister, c_farg0, v0);
61 REGISTER_DECLARATION(FloatRegister, c_farg1, v1);
62 REGISTER_DECLARATION(FloatRegister, c_farg2, v2);
63 REGISTER_DECLARATION(FloatRegister, c_farg3, v3);
64 REGISTER_DECLARATION(FloatRegister, c_farg4, v4);
65 REGISTER_DECLARATION(FloatRegister, c_farg5, v5);
66 REGISTER_DECLARATION(FloatRegister, c_farg6, v6);
67 REGISTER_DECLARATION(FloatRegister, c_farg7, v7);
68
69 // Symbolically name the register arguments used by the Java calling convention.
70 // We have control over the convention for java so we can do what we please.
71 // What pleases us is to offset the java calling convention so that when
72 // we call a suitable jni method the arguments are lined up and we don't
73 // have to do much shuffling. A suitable jni method is non-static and a
74 // small number of arguments
75 //
76 // |--------------------------------------------------------------------|
77 // | c_rarg0 c_rarg1 c_rarg2 c_rarg3 c_rarg4 c_rarg5 c_rarg6 c_rarg7 |
78 // |--------------------------------------------------------------------|
79 // | r0 r1 r2 r3 r4 r5 r6 r7 |
80 // |--------------------------------------------------------------------|
81 // | j_rarg7 j_rarg0 j_rarg1 j_rarg2 j_rarg3 j_rarg4 j_rarg5 j_rarg6 |
82 // |--------------------------------------------------------------------|
83
84
85 REGISTER_DECLARATION(Register, j_rarg0, c_rarg1);
86 REGISTER_DECLARATION(Register, j_rarg1, c_rarg2);
87 REGISTER_DECLARATION(Register, j_rarg2, c_rarg3);
88 REGISTER_DECLARATION(Register, j_rarg3, c_rarg4);
89 REGISTER_DECLARATION(Register, j_rarg4, c_rarg5);
90 REGISTER_DECLARATION(Register, j_rarg5, c_rarg6);
91 REGISTER_DECLARATION(Register, j_rarg6, c_rarg7);
92 REGISTER_DECLARATION(Register, j_rarg7, c_rarg0);
93
94 // Java floating args are passed as per C
95
96 REGISTER_DECLARATION(FloatRegister, j_farg0, v0);
97 REGISTER_DECLARATION(FloatRegister, j_farg1, v1);
98 REGISTER_DECLARATION(FloatRegister, j_farg2, v2);
99 REGISTER_DECLARATION(FloatRegister, j_farg3, v3);
100 REGISTER_DECLARATION(FloatRegister, j_farg4, v4);
101 REGISTER_DECLARATION(FloatRegister, j_farg5, v5);
102 REGISTER_DECLARATION(FloatRegister, j_farg6, v6);
103 REGISTER_DECLARATION(FloatRegister, j_farg7, v7);
104
105 // registers used to hold VM data either temporarily within a method
106 // or across method calls
107
108 // volatile (caller-save) registers
109
110 // r8 is used for indirect result location return
111 // we use it and r9 as scratch registers
112 REGISTER_DECLARATION(Register, rscratch1, r8);
113 REGISTER_DECLARATION(Register, rscratch2, r9);
114
115 // current method -- must be in a call-clobbered register
116 REGISTER_DECLARATION(Register, rmethod, r12);
117
118 // non-volatile (callee-save) registers are r16-29
119 // of which the following are dedicated global state
120
121 // link register
122 REGISTER_DECLARATION(Register, lr, r30);
123 // frame pointer
124 REGISTER_DECLARATION(Register, rfp, r29);
125 // current thread
126 REGISTER_DECLARATION(Register, rthread, r28);
127 // base of heap
128 REGISTER_DECLARATION(Register, rheapbase, r27);
129 // constant pool cache
130 REGISTER_DECLARATION(Register, rcpool, r26);
131 // monitors allocated on stack
132 REGISTER_DECLARATION(Register, rmonitors, r25);
133 // locals on stack
134 REGISTER_DECLARATION(Register, rlocals, r24);
135 // bytecode pointer
136 REGISTER_DECLARATION(Register, rbcp, r22);
137 // Dispatch table base
138 REGISTER_DECLARATION(Register, rdispatch, r21);
139 // Java stack pointer
140 REGISTER_DECLARATION(Register, esp, r20);
141
142 #define assert_cond(ARG1) assert(ARG1, #ARG1)
143
144 namespace asm_util {
145 uint32_t encode_logical_immediate(bool is32, uint64_t imm);
146 };
147
148 using namespace asm_util;
149
150
151 class Assembler;
152
153 class Instruction_aarch64 {
154 unsigned insn;
155 #ifdef ASSERT
156 unsigned bits;
157 #endif
158 Assembler *assem;
159
160 public:
161
162 Instruction_aarch64(class Assembler *as) {
163 #ifdef ASSERT
164 bits = 0;
165 #endif
166 insn = 0;
167 assem = as;
168 }
169
170 inline ~Instruction_aarch64();
171
172 unsigned &get_insn() { return insn; }
173 #ifdef ASSERT
174 unsigned &get_bits() { return bits; }
175 #endif
176
177 static inline int32_t extend(unsigned val, int hi = 31, int lo = 0) {
178 union {
179 unsigned u;
180 int n;
181 };
182
183 u = val << (31 - hi);
184 n = n >> (31 - hi + lo);
185 return n;
186 }
187
188 static inline uint32_t extract(uint32_t val, int msb, int lsb) {
189 int nbits = msb - lsb + 1;
190 assert_cond(msb >= lsb);
191 uint32_t mask = (1U << nbits) - 1;
192 uint32_t result = val >> lsb;
193 result &= mask;
194 return result;
195 }
196
197 static inline int32_t sextract(uint32_t val, int msb, int lsb) {
198 uint32_t uval = extract(val, msb, lsb);
199 return extend(uval, msb - lsb);
200 }
201
202 static void patch(address a, int msb, int lsb, unsigned long val) {
203 int nbits = msb - lsb + 1;
204 guarantee(val < (1U << nbits), "Field too big for insn");
205 assert_cond(msb >= lsb);
206 unsigned mask = (1U << nbits) - 1;
207 val <<= lsb;
208 mask <<= lsb;
209 unsigned target = *(unsigned *)a;
210 target &= ~mask;
211 target |= val;
212 *(unsigned *)a = target;
213 }
214
215 static void spatch(address a, int msb, int lsb, long val) {
216 int nbits = msb - lsb + 1;
217 long chk = val >> (nbits - 1);
218 guarantee (chk == -1 || chk == 0, "Field too big for insn");
219 unsigned uval = val;
220 unsigned mask = (1U << nbits) - 1;
221 uval &= mask;
222 uval <<= lsb;
223 mask <<= lsb;
224 unsigned target = *(unsigned *)a;
225 target &= ~mask;
226 target |= uval;
227 *(unsigned *)a = target;
228 }
229
230 void f(unsigned val, int msb, int lsb) {
231 int nbits = msb - lsb + 1;
232 guarantee(val < (1U << nbits), "Field too big for insn");
233 assert_cond(msb >= lsb);
234 unsigned mask = (1U << nbits) - 1;
235 val <<= lsb;
236 mask <<= lsb;
237 insn |= val;
238 assert_cond((bits & mask) == 0);
239 #ifdef ASSERT
240 bits |= mask;
241 #endif
242 }
243
244 void f(unsigned val, int bit) {
245 f(val, bit, bit);
246 }
247
248 void sf(long val, int msb, int lsb) {
249 int nbits = msb - lsb + 1;
250 long chk = val >> (nbits - 1);
251 guarantee (chk == -1 || chk == 0, "Field too big for insn");
252 unsigned uval = val;
253 unsigned mask = (1U << nbits) - 1;
254 uval &= mask;
255 f(uval, lsb + nbits - 1, lsb);
256 }
257
258 void rf(Register r, int lsb) {
259 f(r->encoding_nocheck(), lsb + 4, lsb);
260 }
261
262 // reg|ZR
263 void zrf(Register r, int lsb) {
264 f(r->encoding_nocheck() - (r == zr), lsb + 4, lsb);
265 }
266
267 // reg|SP
268 void srf(Register r, int lsb) {
269 f(r == sp ? 31 : r->encoding_nocheck(), lsb + 4, lsb);
270 }
271
272 void rf(FloatRegister r, int lsb) {
273 f(r->encoding_nocheck(), lsb + 4, lsb);
274 }
275
276 unsigned get(int msb = 31, int lsb = 0) {
277 int nbits = msb - lsb + 1;
278 unsigned mask = ((1U << nbits) - 1) << lsb;
279 assert_cond((bits & mask) == mask);
280 return (insn & mask) >> lsb;
281 }
282
283 void fixed(unsigned value, unsigned mask) {
284 assert_cond ((mask & bits) == 0);
285 #ifdef ASSERT
286 bits |= mask;
287 #endif
288 insn |= value;
289 }
290 };
291
292 #define starti Instruction_aarch64 do_not_use(this); set_current(&do_not_use)
293
294 class PrePost {
295 int _offset;
296 Register _r;
297 public:
298 PrePost(Register reg, int o) : _offset(o), _r(reg) { }
299 int offset() { return _offset; }
300 Register reg() { return _r; }
301 };
302
303 class Pre : public PrePost {
304 public:
305 Pre(Register reg, int o) : PrePost(reg, o) { }
306 };
307 class Post : public PrePost {
308 Register _idx;
309 bool _is_postreg;
310 public:
311 Post(Register reg, int o) : PrePost(reg, o) { _idx = NULL; _is_postreg = false; }
312 Post(Register reg, Register idx) : PrePost(reg, 0) { _idx = idx; _is_postreg = true; }
313 Register idx_reg() { return _idx; }
314 bool is_postreg() {return _is_postreg; }
315 };
316
317 namespace ext
318 {
319 enum operation { uxtb, uxth, uxtw, uxtx, sxtb, sxth, sxtw, sxtx };
320 };
321
322 // Addressing modes
323 class Address {
324 public:
325
326 enum mode { no_mode, base_plus_offset, pre, post, post_reg, pcrel,
327 base_plus_offset_reg, literal };
328
329 // Shift and extend for base reg + reg offset addressing
330 class extend {
331 int _option, _shift;
332 ext::operation _op;
333 public:
334 extend() { }
335 extend(int s, int o, ext::operation op) : _option(o), _shift(s), _op(op) { }
336 int option() const{ return _option; }
337 int shift() const { return _shift; }
338 ext::operation op() const { return _op; }
339 };
340 class uxtw : public extend {
341 public:
342 uxtw(int shift = -1): extend(shift, 0b010, ext::uxtw) { }
343 };
344 class lsl : public extend {
345 public:
346 lsl(int shift = -1): extend(shift, 0b011, ext::uxtx) { }
347 };
348 class sxtw : public extend {
349 public:
350 sxtw(int shift = -1): extend(shift, 0b110, ext::sxtw) { }
351 };
352 class sxtx : public extend {
353 public:
354 sxtx(int shift = -1): extend(shift, 0b111, ext::sxtx) { }
355 };
356
357 private:
358 Register _base;
359 Register _index;
360 long _offset;
361 enum mode _mode;
362 extend _ext;
363
364 RelocationHolder _rspec;
365
366 // Typically we use AddressLiterals we want to use their rval
367 // However in some situations we want the lval (effect address) of
368 // the item. We provide a special factory for making those lvals.
369 bool _is_lval;
370
371 // If the target is far we'll need to load the ea of this to a
372 // register to reach it. Otherwise if near we can do PC-relative
373 // addressing.
374 address _target;
375
376 public:
377 Address()
378 : _mode(no_mode) { }
379 Address(Register r)
380 : _base(r), _index(noreg), _offset(0), _mode(base_plus_offset), _target(0) { }
381 Address(Register r, int o)
382 : _base(r), _index(noreg), _offset(o), _mode(base_plus_offset), _target(0) { }
383 Address(Register r, long o)
384 : _base(r), _index(noreg), _offset(o), _mode(base_plus_offset), _target(0) { }
385 Address(Register r, unsigned long o)
386 : _base(r), _index(noreg), _offset(o), _mode(base_plus_offset), _target(0) { }
387 #ifdef ASSERT
388 Address(Register r, ByteSize disp)
389 : _base(r), _index(noreg), _offset(in_bytes(disp)), _mode(base_plus_offset), _target(0) { }
390 #endif
391 Address(Register r, Register r1, extend ext = lsl())
392 : _base(r), _index(r1), _offset(0), _mode(base_plus_offset_reg),
393 _ext(ext), _target(0) { }
394 Address(Pre p)
395 : _base(p.reg()), _offset(p.offset()), _mode(pre) { }
396 Address(Post p)
397 : _base(p.reg()), _index(p.idx_reg()), _offset(p.offset()),
398 _mode(p.is_postreg() ? post_reg : post), _target(0) { }
399 Address(address target, RelocationHolder const& rspec)
400 : _mode(literal),
401 _rspec(rspec),
402 _is_lval(false),
403 _target(target) { }
404 Address(address target, relocInfo::relocType rtype = relocInfo::external_word_type);
405 Address(Register base, RegisterOrConstant index, extend ext = lsl())
406 : _base (base),
407 _offset(0), _ext(ext), _target(0) {
408 if (index.is_register()) {
409 _mode = base_plus_offset_reg;
410 _index = index.as_register();
411 } else {
412 guarantee(ext.option() == ext::uxtx, "should be");
413 assert(index.is_constant(), "should be");
414 _mode = base_plus_offset;
415 _offset = index.as_constant() << ext.shift();
416 }
417 }
418
419 Register base() const {
420 guarantee((_mode == base_plus_offset | _mode == base_plus_offset_reg
421 | _mode == post | _mode == post_reg),
422 "wrong mode");
423 return _base;
424 }
425 long offset() const {
426 return _offset;
427 }
428 Register index() const {
429 return _index;
430 }
431 mode getMode() const {
432 return _mode;
433 }
434 bool uses(Register reg) const { return _base == reg || _index == reg; }
435 address target() const { return _target; }
436 const RelocationHolder& rspec() const { return _rspec; }
437
438 void encode(Instruction_aarch64 *i) const {
439 i->f(0b111, 29, 27);
440 i->srf(_base, 5);
441
442 switch(_mode) {
443 case base_plus_offset:
444 {
445 unsigned size = i->get(31, 30);
446 if (i->get(26, 26) && i->get(23, 23)) {
447 // SIMD Q Type - Size = 128 bits
448 assert(size == 0, "bad size");
449 size = 0b100;
450 }
451 unsigned mask = (1 << size) - 1;
452 if (_offset < 0 || _offset & mask)
453 {
454 i->f(0b00, 25, 24);
455 i->f(0, 21), i->f(0b00, 11, 10);
456 i->sf(_offset, 20, 12);
457 } else {
458 i->f(0b01, 25, 24);
459 i->f(_offset >> size, 21, 10);
460 }
461 }
462 break;
463
464 case base_plus_offset_reg:
465 {
466 i->f(0b00, 25, 24);
467 i->f(1, 21);
468 i->rf(_index, 16);
469 i->f(_ext.option(), 15, 13);
470 unsigned size = i->get(31, 30);
471 if (i->get(26, 26) && i->get(23, 23)) {
472 // SIMD Q Type - Size = 128 bits
473 assert(size == 0, "bad size");
474 size = 0b100;
475 }
476 if (size == 0) // It's a byte
477 i->f(_ext.shift() >= 0, 12);
478 else {
479 if (_ext.shift() > 0)
480 assert(_ext.shift() == (int)size, "bad shift");
481 i->f(_ext.shift() > 0, 12);
482 }
483 i->f(0b10, 11, 10);
484 }
485 break;
486
487 case pre:
488 i->f(0b00, 25, 24);
489 i->f(0, 21), i->f(0b11, 11, 10);
490 i->sf(_offset, 20, 12);
491 break;
492
493 case post:
494 i->f(0b00, 25, 24);
495 i->f(0, 21), i->f(0b01, 11, 10);
496 i->sf(_offset, 20, 12);
497 break;
498
499 default:
500 ShouldNotReachHere();
501 }
502 }
503
504 void encode_pair(Instruction_aarch64 *i) const {
505 switch(_mode) {
506 case base_plus_offset:
507 i->f(0b010, 25, 23);
508 break;
509 case pre:
510 i->f(0b011, 25, 23);
511 break;
512 case post:
513 i->f(0b001, 25, 23);
514 break;
515 default:
516 ShouldNotReachHere();
517 }
518
519 unsigned size; // Operand shift in 32-bit words
520
521 if (i->get(26, 26)) { // float
522 switch(i->get(31, 30)) {
523 case 0b10:
524 size = 2; break;
525 case 0b01:
526 size = 1; break;
527 case 0b00:
528 size = 0; break;
529 default:
530 ShouldNotReachHere();
531 size = 0; // unreachable
532 }
533 } else {
534 size = i->get(31, 31);
535 }
536
537 size = 4 << size;
538 guarantee(_offset % size == 0, "bad offset");
539 i->sf(_offset / size, 21, 15);
540 i->srf(_base, 5);
541 }
542
543 void encode_nontemporal_pair(Instruction_aarch64 *i) const {
544 // Only base + offset is allowed
545 i->f(0b000, 25, 23);
546 unsigned size = i->get(31, 31);
547 size = 4 << size;
548 guarantee(_offset % size == 0, "bad offset");
549 i->sf(_offset / size, 21, 15);
550 i->srf(_base, 5);
551 guarantee(_mode == Address::base_plus_offset,
552 "Bad addressing mode for non-temporal op");
553 }
554
555 void lea(MacroAssembler *, Register) const;
556
557 static bool offset_ok_for_immed(long offset, int shift) {
558 unsigned mask = (1 << shift) - 1;
559 if (offset < 0 || offset & mask) {
560 return (uabs(offset) < (1 << (20 - 12))); // Unscaled offset
561 } else {
562 return ((offset >> shift) < (1 << (21 - 10 + 1))); // Scaled, unsigned offset
563 }
564 }
565 };
566
567 // Convience classes
568 class RuntimeAddress: public Address {
569
570 public:
571
572 RuntimeAddress(address target) : Address(target, relocInfo::runtime_call_type) {}
573
574 };
575
576 class OopAddress: public Address {
577
578 public:
579
580 OopAddress(address target) : Address(target, relocInfo::oop_type){}
581
582 };
583
584 class ExternalAddress: public Address {
585 private:
586 static relocInfo::relocType reloc_for_target(address target) {
587 // Sometimes ExternalAddress is used for values which aren't
588 // exactly addresses, like the card table base.
589 // external_word_type can't be used for values in the first page
590 // so just skip the reloc in that case.
591 return external_word_Relocation::can_be_relocated(target) ? relocInfo::external_word_type : relocInfo::none;
592 }
593
594 public:
595
596 ExternalAddress(address target) : Address(target, reloc_for_target(target)) {}
597
598 };
599
600 class InternalAddress: public Address {
601
602 public:
603
604 InternalAddress(address target) : Address(target, relocInfo::internal_word_type) {}
605 };
606
607 const int FPUStateSizeInWords = FloatRegisterImpl::number_of_registers *
608 FloatRegisterImpl::save_slots_per_register;
609
610 typedef enum {
611 PLDL1KEEP = 0b00000, PLDL1STRM, PLDL2KEEP, PLDL2STRM, PLDL3KEEP, PLDL3STRM,
612 PSTL1KEEP = 0b10000, PSTL1STRM, PSTL2KEEP, PSTL2STRM, PSTL3KEEP, PSTL3STRM,
613 PLIL1KEEP = 0b01000, PLIL1STRM, PLIL2KEEP, PLIL2STRM, PLIL3KEEP, PLIL3STRM
614 } prfop;
615
616 class Assembler : public AbstractAssembler {
617
618 #ifndef PRODUCT
619 static const unsigned long asm_bp;
620
621 void emit_long(jint x) {
622 if ((unsigned long)pc() == asm_bp)
623 asm volatile ("nop");
624 AbstractAssembler::emit_int32(x);
625 }
626 #else
627 void emit_long(jint x) {
628 AbstractAssembler::emit_int32(x);
629 }
630 #endif
631
632 public:
633
634 enum { instruction_size = 4 };
635
636 //---< calculate length of instruction >---
637 // We just use the values set above.
638 // instruction must start at passed address
639 static unsigned int instr_len(unsigned char *instr) { return instruction_size; }
640
641 //---< longest instructions >---
642 static unsigned int instr_maxlen() { return instruction_size; }
643
644 Address adjust(Register base, int offset, bool preIncrement) {
645 if (preIncrement)
646 return Address(Pre(base, offset));
647 else
648 return Address(Post(base, offset));
649 }
650
651 Address pre(Register base, int offset) {
652 return adjust(base, offset, true);
653 }
654
655 Address post(Register base, int offset) {
656 return adjust(base, offset, false);
657 }
658
659 Address post(Register base, Register idx) {
660 return Address(Post(base, idx));
661 }
662
663 Instruction_aarch64* current;
664
665 void set_current(Instruction_aarch64* i) { current = i; }
666
667 void f(unsigned val, int msb, int lsb) {
668 current->f(val, msb, lsb);
669 }
670 void f(unsigned val, int msb) {
671 current->f(val, msb, msb);
672 }
673 void sf(long val, int msb, int lsb) {
674 current->sf(val, msb, lsb);
675 }
676 void rf(Register reg, int lsb) {
677 current->rf(reg, lsb);
678 }
679 void srf(Register reg, int lsb) {
680 current->srf(reg, lsb);
681 }
682 void zrf(Register reg, int lsb) {
683 current->zrf(reg, lsb);
684 }
685 void rf(FloatRegister reg, int lsb) {
686 current->rf(reg, lsb);
687 }
688 void fixed(unsigned value, unsigned mask) {
689 current->fixed(value, mask);
690 }
691
692 void emit() {
693 emit_long(current->get_insn());
694 assert_cond(current->get_bits() == 0xffffffff);
695 current = NULL;
696 }
697
698 typedef void (Assembler::* uncond_branch_insn)(address dest);
699 typedef void (Assembler::* compare_and_branch_insn)(Register Rt, address dest);
700 typedef void (Assembler::* test_and_branch_insn)(Register Rt, int bitpos, address dest);
701 typedef void (Assembler::* prefetch_insn)(address target, prfop);
702
703 void wrap_label(Label &L, uncond_branch_insn insn);
704 void wrap_label(Register r, Label &L, compare_and_branch_insn insn);
705 void wrap_label(Register r, int bitpos, Label &L, test_and_branch_insn insn);
706 void wrap_label(Label &L, prfop, prefetch_insn insn);
707
708 // PC-rel. addressing
709
710 void adr(Register Rd, address dest);
711 void _adrp(Register Rd, address dest);
712
713 void adr(Register Rd, const Address &dest);
714 void _adrp(Register Rd, const Address &dest);
715
716 void adr(Register Rd, Label &L) {
717 wrap_label(Rd, L, &Assembler::Assembler::adr);
718 }
719 void _adrp(Register Rd, Label &L) {
720 wrap_label(Rd, L, &Assembler::_adrp);
721 }
722
723 void adrp(Register Rd, const Address &dest, unsigned long &offset);
724
725 #undef INSN
726
727 void add_sub_immediate(Register Rd, Register Rn, unsigned uimm, int op,
728 int negated_op);
729
730 // Add/subtract (immediate)
731 #define INSN(NAME, decode, negated) \
732 void NAME(Register Rd, Register Rn, unsigned imm, unsigned shift) { \
733 starti; \
734 f(decode, 31, 29), f(0b10001, 28, 24), f(shift, 23, 22), f(imm, 21, 10); \
735 zrf(Rd, 0), srf(Rn, 5); \
736 } \
737 \
738 void NAME(Register Rd, Register Rn, unsigned imm) { \
739 starti; \
740 add_sub_immediate(Rd, Rn, imm, decode, negated); \
741 }
742
743 INSN(addsw, 0b001, 0b011);
744 INSN(subsw, 0b011, 0b001);
745 INSN(adds, 0b101, 0b111);
746 INSN(subs, 0b111, 0b101);
747
748 #undef INSN
749
750 #define INSN(NAME, decode, negated) \
751 void NAME(Register Rd, Register Rn, unsigned imm) { \
752 starti; \
753 add_sub_immediate(Rd, Rn, imm, decode, negated); \
754 }
755
756 INSN(addw, 0b000, 0b010);
757 INSN(subw, 0b010, 0b000);
758 INSN(add, 0b100, 0b110);
759 INSN(sub, 0b110, 0b100);
760
761 #undef INSN
762
763 // Logical (immediate)
764 #define INSN(NAME, decode, is32) \
765 void NAME(Register Rd, Register Rn, uint64_t imm) { \
766 starti; \
767 uint32_t val = encode_logical_immediate(is32, imm); \
768 f(decode, 31, 29), f(0b100100, 28, 23), f(val, 22, 10); \
769 srf(Rd, 0), zrf(Rn, 5); \
770 }
771
772 INSN(andw, 0b000, true);
773 INSN(orrw, 0b001, true);
774 INSN(eorw, 0b010, true);
775 INSN(andr, 0b100, false);
776 INSN(orr, 0b101, false);
777 INSN(eor, 0b110, false);
778
779 #undef INSN
780
781 #define INSN(NAME, decode, is32) \
782 void NAME(Register Rd, Register Rn, uint64_t imm) { \
783 starti; \
784 uint32_t val = encode_logical_immediate(is32, imm); \
785 f(decode, 31, 29), f(0b100100, 28, 23), f(val, 22, 10); \
786 zrf(Rd, 0), zrf(Rn, 5); \
787 }
788
789 INSN(ands, 0b111, false);
790 INSN(andsw, 0b011, true);
791
792 #undef INSN
793
794 // Move wide (immediate)
795 #define INSN(NAME, opcode) \
796 void NAME(Register Rd, unsigned imm, unsigned shift = 0) { \
797 assert_cond((shift/16)*16 == shift); \
798 starti; \
799 f(opcode, 31, 29), f(0b100101, 28, 23), f(shift/16, 22, 21), \
800 f(imm, 20, 5); \
801 rf(Rd, 0); \
802 }
803
804 INSN(movnw, 0b000);
805 INSN(movzw, 0b010);
806 INSN(movkw, 0b011);
807 INSN(movn, 0b100);
808 INSN(movz, 0b110);
809 INSN(movk, 0b111);
810
811 #undef INSN
812
813 // Bitfield
814 #define INSN(NAME, opcode, size) \
815 void NAME(Register Rd, Register Rn, unsigned immr, unsigned imms) { \
816 starti; \
817 guarantee(size == 1 || (immr < 32 && imms < 32), "incorrect immr/imms");\
818 f(opcode, 31, 22), f(immr, 21, 16), f(imms, 15, 10); \
819 zrf(Rn, 5), rf(Rd, 0); \
820 }
821
822 INSN(sbfmw, 0b0001001100, 0);
823 INSN(bfmw, 0b0011001100, 0);
824 INSN(ubfmw, 0b0101001100, 0);
825 INSN(sbfm, 0b1001001101, 1);
826 INSN(bfm, 0b1011001101, 1);
827 INSN(ubfm, 0b1101001101, 1);
828
829 #undef INSN
830
831 // Extract
832 #define INSN(NAME, opcode, size) \
833 void NAME(Register Rd, Register Rn, Register Rm, unsigned imms) { \
834 starti; \
835 guarantee(size == 1 || imms < 32, "incorrect imms"); \
836 f(opcode, 31, 21), f(imms, 15, 10); \
837 zrf(Rm, 16), zrf(Rn, 5), zrf(Rd, 0); \
838 }
839
840 INSN(extrw, 0b00010011100, 0);
841 INSN(extr, 0b10010011110, 1);
842
843 #undef INSN
844
845 // The maximum range of a branch is fixed for the AArch64
846 // architecture. In debug mode we shrink it in order to test
847 // trampolines, but not so small that branches in the interpreter
848 // are out of range.
849 static const unsigned long branch_range = NOT_DEBUG(128 * M) DEBUG_ONLY(2 * M);
850
851 static bool reachable_from_branch_at(address branch, address target) {
852 return uabs(target - branch) < branch_range;
853 }
854
855 // Unconditional branch (immediate)
856 #define INSN(NAME, opcode) \
857 void NAME(address dest) { \
858 starti; \
859 long offset = (dest - pc()) >> 2; \
860 DEBUG_ONLY(assert(reachable_from_branch_at(pc(), dest), "debug only")); \
861 f(opcode, 31), f(0b00101, 30, 26), sf(offset, 25, 0); \
862 } \
863 void NAME(Label &L) { \
864 wrap_label(L, &Assembler::NAME); \
865 } \
866 void NAME(const Address &dest);
867
868 INSN(b, 0);
869 INSN(bl, 1);
870
871 #undef INSN
872
873 // Compare & branch (immediate)
874 #define INSN(NAME, opcode) \
875 void NAME(Register Rt, address dest) { \
876 long offset = (dest - pc()) >> 2; \
877 starti; \
878 f(opcode, 31, 24), sf(offset, 23, 5), rf(Rt, 0); \
879 } \
880 void NAME(Register Rt, Label &L) { \
881 wrap_label(Rt, L, &Assembler::NAME); \
882 }
883
884 INSN(cbzw, 0b00110100);
885 INSN(cbnzw, 0b00110101);
886 INSN(cbz, 0b10110100);
887 INSN(cbnz, 0b10110101);
888
889 #undef INSN
890
891 // Test & branch (immediate)
892 #define INSN(NAME, opcode) \
893 void NAME(Register Rt, int bitpos, address dest) { \
894 long offset = (dest - pc()) >> 2; \
895 int b5 = bitpos >> 5; \
896 bitpos &= 0x1f; \
897 starti; \
898 f(b5, 31), f(opcode, 30, 24), f(bitpos, 23, 19), sf(offset, 18, 5); \
899 rf(Rt, 0); \
900 } \
901 void NAME(Register Rt, int bitpos, Label &L) { \
902 wrap_label(Rt, bitpos, L, &Assembler::NAME); \
903 }
904
905 INSN(tbz, 0b0110110);
906 INSN(tbnz, 0b0110111);
907
908 #undef INSN
909
910 // Conditional branch (immediate)
911 enum Condition
912 {EQ, NE, HS, CS=HS, LO, CC=LO, MI, PL, VS, VC, HI, LS, GE, LT, GT, LE, AL, NV};
913
914 void br(Condition cond, address dest) {
915 long offset = (dest - pc()) >> 2;
916 starti;
917 f(0b0101010, 31, 25), f(0, 24), sf(offset, 23, 5), f(0, 4), f(cond, 3, 0);
918 }
919
920 #define INSN(NAME, cond) \
921 void NAME(address dest) { \
922 br(cond, dest); \
923 }
924
925 INSN(beq, EQ);
926 INSN(bne, NE);
927 INSN(bhs, HS);
928 INSN(bcs, CS);
929 INSN(blo, LO);
930 INSN(bcc, CC);
931 INSN(bmi, MI);
932 INSN(bpl, PL);
933 INSN(bvs, VS);
934 INSN(bvc, VC);
935 INSN(bhi, HI);
936 INSN(bls, LS);
937 INSN(bge, GE);
938 INSN(blt, LT);
939 INSN(bgt, GT);
940 INSN(ble, LE);
941 INSN(bal, AL);
942 INSN(bnv, NV);
943
944 void br(Condition cc, Label &L);
945
946 #undef INSN
947
948 // Exception generation
949 void generate_exception(int opc, int op2, int LL, unsigned imm) {
950 starti;
951 f(0b11010100, 31, 24);
952 f(opc, 23, 21), f(imm, 20, 5), f(op2, 4, 2), f(LL, 1, 0);
953 }
954
955 #define INSN(NAME, opc, op2, LL) \
956 void NAME(unsigned imm) { \
957 generate_exception(opc, op2, LL, imm); \
958 }
959
960 INSN(svc, 0b000, 0, 0b01);
961 INSN(hvc, 0b000, 0, 0b10);
962 INSN(smc, 0b000, 0, 0b11);
963 INSN(brk, 0b001, 0, 0b00);
964 INSN(hlt, 0b010, 0, 0b00);
965 INSN(dcps1, 0b101, 0, 0b01);
966 INSN(dcps2, 0b101, 0, 0b10);
967 INSN(dcps3, 0b101, 0, 0b11);
968
969 #undef INSN
970
971 // System
972 void system(int op0, int op1, int CRn, int CRm, int op2,
973 Register rt = dummy_reg)
974 {
975 starti;
976 f(0b11010101000, 31, 21);
977 f(op0, 20, 19);
978 f(op1, 18, 16);
979 f(CRn, 15, 12);
980 f(CRm, 11, 8);
981 f(op2, 7, 5);
982 rf(rt, 0);
983 }
984
985 void hint(int imm) {
986 system(0b00, 0b011, 0b0010, 0b0000, imm);
987 }
988
989 void nop() {
990 hint(0);
991 }
992
993 void yield() {
994 hint(1);
995 }
996
997 void wfe() {
998 hint(2);
999 }
1000
1001 void wfi() {
1002 hint(3);
1003 }
1004
1005 void sev() {
1006 hint(4);
1007 }
1008
1009 void sevl() {
1010 hint(5);
1011 }
1012
1013 // we only provide mrs and msr for the special purpose system
1014 // registers where op1 (instr[20:19]) == 11 and, (currently) only
1015 // use it for FPSR n.b msr has L (instr[21]) == 0 mrs has L == 1
1016
1017 void msr(int op1, int CRn, int CRm, int op2, Register rt) {
1018 starti;
1019 f(0b1101010100011, 31, 19);
1020 f(op1, 18, 16);
1021 f(CRn, 15, 12);
1022 f(CRm, 11, 8);
1023 f(op2, 7, 5);
1024 // writing zr is ok
1025 zrf(rt, 0);
1026 }
1027
1028 void mrs(int op1, int CRn, int CRm, int op2, Register rt) {
1029 starti;
1030 f(0b1101010100111, 31, 19);
1031 f(op1, 18, 16);
1032 f(CRn, 15, 12);
1033 f(CRm, 11, 8);
1034 f(op2, 7, 5);
1035 // reading to zr is a mistake
1036 rf(rt, 0);
1037 }
1038
1039 enum barrier {OSHLD = 0b0001, OSHST, OSH, NSHLD=0b0101, NSHST, NSH,
1040 ISHLD = 0b1001, ISHST, ISH, LD=0b1101, ST, SY};
1041
1042 void dsb(barrier imm) {
1043 system(0b00, 0b011, 0b00011, imm, 0b100);
1044 }
1045
1046 void dmb(barrier imm) {
1047 system(0b00, 0b011, 0b00011, imm, 0b101);
1048 }
1049
1050 void isb() {
1051 system(0b00, 0b011, 0b00011, SY, 0b110);
1052 }
1053
1054 void sys(int op1, int CRn, int CRm, int op2,
1055 Register rt = (Register)0b11111) {
1056 system(0b01, op1, CRn, CRm, op2, rt);
1057 }
1058
1059 // Only implement operations accessible from EL0 or higher, i.e.,
1060 // op1 CRn CRm op2
1061 // IC IVAU 3 7 5 1
1062 // DC CVAC 3 7 10 1
1063 // DC CVAP 3 7 12 1
1064 // DC CVAU 3 7 11 1
1065 // DC CIVAC 3 7 14 1
1066 // DC ZVA 3 7 4 1
1067 // So only deal with the CRm field.
1068 enum icache_maintenance {IVAU = 0b0101};
1069 enum dcache_maintenance {CVAC = 0b1010, CVAP = 0b1100, CVAU = 0b1011, CIVAC = 0b1110, ZVA = 0b100};
1070
1071 void dc(dcache_maintenance cm, Register Rt) {
1072 sys(0b011, 0b0111, cm, 0b001, Rt);
1073 }
1074
1075 void ic(icache_maintenance cm, Register Rt) {
1076 sys(0b011, 0b0111, cm, 0b001, Rt);
1077 }
1078
1079 // A more convenient access to dmb for our purposes
1080 enum Membar_mask_bits {
1081 // We can use ISH for a barrier because the ARM ARM says "This
1082 // architecture assumes that all Processing Elements that use the
1083 // same operating system or hypervisor are in the same Inner
1084 // Shareable shareability domain."
1085 StoreStore = ISHST,
1086 LoadStore = ISHLD,
1087 LoadLoad = ISHLD,
1088 StoreLoad = ISH,
1089 AnyAny = ISH
1090 };
1091
1092 void membar(Membar_mask_bits order_constraint) {
1093 dmb(Assembler::barrier(order_constraint));
1094 }
1095
1096 // Unconditional branch (register)
1097 void branch_reg(Register R, int opc) {
1098 starti;
1099 f(0b1101011, 31, 25);
1100 f(opc, 24, 21);
1101 f(0b11111000000, 20, 10);
1102 rf(R, 5);
1103 f(0b00000, 4, 0);
1104 }
1105
1106 #define INSN(NAME, opc) \
1107 void NAME(Register R) { \
1108 branch_reg(R, opc); \
1109 }
1110
1111 INSN(br, 0b0000);
1112 INSN(blr, 0b0001);
1113 INSN(ret, 0b0010);
1114
1115 void ret(void *p); // This forces a compile-time error for ret(0)
1116
1117 #undef INSN
1118
1119 #define INSN(NAME, opc) \
1120 void NAME() { \
1121 branch_reg(dummy_reg, opc); \
1122 }
1123
1124 INSN(eret, 0b0100);
1125 INSN(drps, 0b0101);
1126
1127 #undef INSN
1128
1129 // Load/store exclusive
1130 enum operand_size { byte, halfword, word, xword };
1131
1132 void load_store_exclusive(Register Rs, Register Rt1, Register Rt2,
1133 Register Rn, enum operand_size sz, int op, bool ordered) {
1134 starti;
1135 f(sz, 31, 30), f(0b001000, 29, 24), f(op, 23, 21);
1136 rf(Rs, 16), f(ordered, 15), zrf(Rt2, 10), srf(Rn, 5), zrf(Rt1, 0);
1137 }
1138
1139 void load_exclusive(Register dst, Register addr,
1140 enum operand_size sz, bool ordered) {
1141 load_store_exclusive(dummy_reg, dst, dummy_reg, addr,
1142 sz, 0b010, ordered);
1143 }
1144
1145 void store_exclusive(Register status, Register new_val, Register addr,
1146 enum operand_size sz, bool ordered) {
1147 load_store_exclusive(status, new_val, dummy_reg, addr,
1148 sz, 0b000, ordered);
1149 }
1150
1151 #define INSN4(NAME, sz, op, o0) /* Four registers */ \
1152 void NAME(Register Rs, Register Rt1, Register Rt2, Register Rn) { \
1153 guarantee(Rs != Rn && Rs != Rt1 && Rs != Rt2, "unpredictable instruction"); \
1154 load_store_exclusive(Rs, Rt1, Rt2, Rn, sz, op, o0); \
1155 }
1156
1157 #define INSN3(NAME, sz, op, o0) /* Three registers */ \
1158 void NAME(Register Rs, Register Rt, Register Rn) { \
1159 guarantee(Rs != Rn && Rs != Rt, "unpredictable instruction"); \
1160 load_store_exclusive(Rs, Rt, dummy_reg, Rn, sz, op, o0); \
1161 }
1162
1163 #define INSN2(NAME, sz, op, o0) /* Two registers */ \
1164 void NAME(Register Rt, Register Rn) { \
1165 load_store_exclusive(dummy_reg, Rt, dummy_reg, \
1166 Rn, sz, op, o0); \
1167 }
1168
1169 #define INSN_FOO(NAME, sz, op, o0) /* Three registers, encoded differently */ \
1170 void NAME(Register Rt1, Register Rt2, Register Rn) { \
1171 guarantee(Rt1 != Rt2, "unpredictable instruction"); \
1172 load_store_exclusive(dummy_reg, Rt1, Rt2, Rn, sz, op, o0); \
1173 }
1174
1175 // bytes
1176 INSN3(stxrb, byte, 0b000, 0);
1177 INSN3(stlxrb, byte, 0b000, 1);
1178 INSN2(ldxrb, byte, 0b010, 0);
1179 INSN2(ldaxrb, byte, 0b010, 1);
1180 INSN2(stlrb, byte, 0b100, 1);
1181 INSN2(ldarb, byte, 0b110, 1);
1182
1183 // halfwords
1184 INSN3(stxrh, halfword, 0b000, 0);
1185 INSN3(stlxrh, halfword, 0b000, 1);
1186 INSN2(ldxrh, halfword, 0b010, 0);
1187 INSN2(ldaxrh, halfword, 0b010, 1);
1188 INSN2(stlrh, halfword, 0b100, 1);
1189 INSN2(ldarh, halfword, 0b110, 1);
1190
1191 // words
1192 INSN3(stxrw, word, 0b000, 0);
1193 INSN3(stlxrw, word, 0b000, 1);
1194 INSN4(stxpw, word, 0b001, 0);
1195 INSN4(stlxpw, word, 0b001, 1);
1196 INSN2(ldxrw, word, 0b010, 0);
1197 INSN2(ldaxrw, word, 0b010, 1);
1198 INSN_FOO(ldxpw, word, 0b011, 0);
1199 INSN_FOO(ldaxpw, word, 0b011, 1);
1200 INSN2(stlrw, word, 0b100, 1);
1201 INSN2(ldarw, word, 0b110, 1);
1202
1203 // xwords
1204 INSN3(stxr, xword, 0b000, 0);
1205 INSN3(stlxr, xword, 0b000, 1);
1206 INSN4(stxp, xword, 0b001, 0);
1207 INSN4(stlxp, xword, 0b001, 1);
1208 INSN2(ldxr, xword, 0b010, 0);
1209 INSN2(ldaxr, xword, 0b010, 1);
1210 INSN_FOO(ldxp, xword, 0b011, 0);
1211 INSN_FOO(ldaxp, xword, 0b011, 1);
1212 INSN2(stlr, xword, 0b100, 1);
1213 INSN2(ldar, xword, 0b110, 1);
1214
1215 #undef INSN2
1216 #undef INSN3
1217 #undef INSN4
1218 #undef INSN_FOO
1219
1220 // 8.1 Compare and swap extensions
1221 void lse_cas(Register Rs, Register Rt, Register Rn,
1222 enum operand_size sz, bool a, bool r, bool not_pair) {
1223 starti;
1224 if (! not_pair) { // Pair
1225 assert(sz == word || sz == xword, "invalid size");
1226 /* The size bit is in bit 30, not 31 */
1227 sz = (operand_size)(sz == word ? 0b00:0b01);
1228 }
1229 f(sz, 31, 30), f(0b001000, 29, 24), f(not_pair ? 1 : 0, 23), f(a, 22), f(1, 21);
1230 zrf(Rs, 16), f(r, 15), f(0b11111, 14, 10), srf(Rn, 5), zrf(Rt, 0);
1231 }
1232
1233 // CAS
1234 #define INSN(NAME, a, r) \
1235 void NAME(operand_size sz, Register Rs, Register Rt, Register Rn) { \
1236 assert(Rs != Rn && Rs != Rt, "unpredictable instruction"); \
1237 lse_cas(Rs, Rt, Rn, sz, a, r, true); \
1238 }
1239 INSN(cas, false, false)
1240 INSN(casa, true, false)
1241 INSN(casl, false, true)
1242 INSN(casal, true, true)
1243 #undef INSN
1244
1245 // CASP
1246 #define INSN(NAME, a, r) \
1247 void NAME(operand_size sz, Register Rs, Register Rs1, \
1248 Register Rt, Register Rt1, Register Rn) { \
1249 assert((Rs->encoding() & 1) == 0 && (Rt->encoding() & 1) == 0 && \
1250 Rs->successor() == Rs1 && Rt->successor() == Rt1 && \
1251 Rs != Rn && Rs1 != Rn && Rs != Rt, "invalid registers"); \
1252 lse_cas(Rs, Rt, Rn, sz, a, r, false); \
1253 }
1254 INSN(casp, false, false)
1255 INSN(caspa, true, false)
1256 INSN(caspl, false, true)
1257 INSN(caspal, true, true)
1258 #undef INSN
1259
1260 // 8.1 Atomic operations
1261 void lse_atomic(Register Rs, Register Rt, Register Rn,
1262 enum operand_size sz, int op1, int op2, bool a, bool r) {
1263 starti;
1264 f(sz, 31, 30), f(0b111000, 29, 24), f(a, 23), f(r, 22), f(1, 21);
1265 zrf(Rs, 16), f(op1, 15), f(op2, 14, 12), f(0, 11, 10), srf(Rn, 5), zrf(Rt, 0);
1266 }
1267
1268 #define INSN(NAME, NAME_A, NAME_L, NAME_AL, op1, op2) \
1269 void NAME(operand_size sz, Register Rs, Register Rt, Register Rn) { \
1270 lse_atomic(Rs, Rt, Rn, sz, op1, op2, false, false); \
1271 } \
1272 void NAME_A(operand_size sz, Register Rs, Register Rt, Register Rn) { \
1273 lse_atomic(Rs, Rt, Rn, sz, op1, op2, true, false); \
1274 } \
1275 void NAME_L(operand_size sz, Register Rs, Register Rt, Register Rn) { \
1276 lse_atomic(Rs, Rt, Rn, sz, op1, op2, false, true); \
1277 } \
1278 void NAME_AL(operand_size sz, Register Rs, Register Rt, Register Rn) {\
1279 lse_atomic(Rs, Rt, Rn, sz, op1, op2, true, true); \
1280 }
1281 INSN(ldadd, ldadda, ldaddl, ldaddal, 0, 0b000);
1282 INSN(ldbic, ldbica, ldbicl, ldbical, 0, 0b001);
1283 INSN(ldeor, ldeora, ldeorl, ldeoral, 0, 0b010);
1284 INSN(ldorr, ldorra, ldorrl, ldorral, 0, 0b011);
1285 INSN(ldsmax, ldsmaxa, ldsmaxl, ldsmaxal, 0, 0b100);
1286 INSN(ldsmin, ldsmina, ldsminl, ldsminal, 0, 0b101);
1287 INSN(ldumax, ldumaxa, ldumaxl, ldumaxal, 0, 0b110);
1288 INSN(ldumin, ldumina, lduminl, lduminal, 0, 0b111);
1289 INSN(swp, swpa, swpl, swpal, 1, 0b000);
1290 #undef INSN
1291
1292 // Load register (literal)
1293 #define INSN(NAME, opc, V) \
1294 void NAME(Register Rt, address dest) { \
1295 long offset = (dest - pc()) >> 2; \
1296 starti; \
1297 f(opc, 31, 30), f(0b011, 29, 27), f(V, 26), f(0b00, 25, 24), \
1298 sf(offset, 23, 5); \
1299 rf(Rt, 0); \
1300 } \
1301 void NAME(Register Rt, address dest, relocInfo::relocType rtype) { \
1302 InstructionMark im(this); \
1303 guarantee(rtype == relocInfo::internal_word_type, \
1304 "only internal_word_type relocs make sense here"); \
1305 code_section()->relocate(inst_mark(), InternalAddress(dest).rspec()); \
1306 NAME(Rt, dest); \
1307 } \
1308 void NAME(Register Rt, Label &L) { \
1309 wrap_label(Rt, L, &Assembler::NAME); \
1310 }
1311
1312 INSN(ldrw, 0b00, 0);
1313 INSN(ldr, 0b01, 0);
1314 INSN(ldrsw, 0b10, 0);
1315
1316 #undef INSN
1317
1318 #define INSN(NAME, opc, V) \
1319 void NAME(FloatRegister Rt, address dest) { \
1320 long offset = (dest - pc()) >> 2; \
1321 starti; \
1322 f(opc, 31, 30), f(0b011, 29, 27), f(V, 26), f(0b00, 25, 24), \
1323 sf(offset, 23, 5); \
1324 rf((Register)Rt, 0); \
1325 }
1326
1327 INSN(ldrs, 0b00, 1);
1328 INSN(ldrd, 0b01, 1);
1329 INSN(ldrq, 0b10, 1);
1330
1331 #undef INSN
1332
1333 #define INSN(NAME, size, opc) \
1334 void NAME(FloatRegister Rt, Register Rn) { \
1335 starti; \
1336 f(size, 31, 30), f(0b111100, 29, 24), f(opc, 23, 22), f(0, 21); \
1337 f(0, 20, 12), f(0b01, 11, 10); \
1338 rf(Rn, 5), rf((Register)Rt, 0); \
1339 }
1340
1341 INSN(ldrs, 0b10, 0b01);
1342 INSN(ldrd, 0b11, 0b01);
1343 INSN(ldrq, 0b00, 0b11);
1344
1345 #undef INSN
1346
1347
1348 #define INSN(NAME, opc, V) \
1349 void NAME(address dest, prfop op = PLDL1KEEP) { \
1350 long offset = (dest - pc()) >> 2; \
1351 starti; \
1352 f(opc, 31, 30), f(0b011, 29, 27), f(V, 26), f(0b00, 25, 24), \
1353 sf(offset, 23, 5); \
1354 f(op, 4, 0); \
1355 } \
1356 void NAME(Label &L, prfop op = PLDL1KEEP) { \
1357 wrap_label(L, op, &Assembler::NAME); \
1358 }
1359
1360 INSN(prfm, 0b11, 0);
1361
1362 #undef INSN
1363
1364 // Load/store
1365 void ld_st1(int opc, int p1, int V, int L,
1366 Register Rt1, Register Rt2, Address adr, bool no_allocate) {
1367 starti;
1368 f(opc, 31, 30), f(p1, 29, 27), f(V, 26), f(L, 22);
1369 zrf(Rt2, 10), zrf(Rt1, 0);
1370 if (no_allocate) {
1371 adr.encode_nontemporal_pair(current);
1372 } else {
1373 adr.encode_pair(current);
1374 }
1375 }
1376
1377 // Load/store register pair (offset)
1378 #define INSN(NAME, size, p1, V, L, no_allocate) \
1379 void NAME(Register Rt1, Register Rt2, Address adr) { \
1380 ld_st1(size, p1, V, L, Rt1, Rt2, adr, no_allocate); \
1381 }
1382
1383 INSN(stpw, 0b00, 0b101, 0, 0, false);
1384 INSN(ldpw, 0b00, 0b101, 0, 1, false);
1385 INSN(ldpsw, 0b01, 0b101, 0, 1, false);
1386 INSN(stp, 0b10, 0b101, 0, 0, false);
1387 INSN(ldp, 0b10, 0b101, 0, 1, false);
1388
1389 // Load/store no-allocate pair (offset)
1390 INSN(stnpw, 0b00, 0b101, 0, 0, true);
1391 INSN(ldnpw, 0b00, 0b101, 0, 1, true);
1392 INSN(stnp, 0b10, 0b101, 0, 0, true);
1393 INSN(ldnp, 0b10, 0b101, 0, 1, true);
1394
1395 #undef INSN
1396
1397 #define INSN(NAME, size, p1, V, L, no_allocate) \
1398 void NAME(FloatRegister Rt1, FloatRegister Rt2, Address adr) { \
1399 ld_st1(size, p1, V, L, (Register)Rt1, (Register)Rt2, adr, no_allocate); \
1400 }
1401
1402 INSN(stps, 0b00, 0b101, 1, 0, false);
1403 INSN(ldps, 0b00, 0b101, 1, 1, false);
1404 INSN(stpd, 0b01, 0b101, 1, 0, false);
1405 INSN(ldpd, 0b01, 0b101, 1, 1, false);
1406 INSN(stpq, 0b10, 0b101, 1, 0, false);
1407 INSN(ldpq, 0b10, 0b101, 1, 1, false);
1408
1409 #undef INSN
1410
1411 // Load/store register (all modes)
1412 void ld_st2(Register Rt, const Address &adr, int size, int op, int V = 0) {
1413 starti;
1414
1415 f(V, 26); // general reg?
1416 zrf(Rt, 0);
1417
1418 // Encoding for literal loads is done here (rather than pushed
1419 // down into Address::encode) because the encoding of this
1420 // instruction is too different from all of the other forms to
1421 // make it worth sharing.
1422 if (adr.getMode() == Address::literal) {
1423 assert(size == 0b10 || size == 0b11, "bad operand size in ldr");
1424 assert(op == 0b01, "literal form can only be used with loads");
1425 f(size & 0b01, 31, 30), f(0b011, 29, 27), f(0b00, 25, 24);
1426 long offset = (adr.target() - pc()) >> 2;
1427 sf(offset, 23, 5);
1428 code_section()->relocate(pc(), adr.rspec());
1429 return;
1430 }
1431
1432 f(size, 31, 30);
1433 f(op, 23, 22); // str
1434 adr.encode(current);
1435 }
1436
1437 #define INSN(NAME, size, op) \
1438 void NAME(Register Rt, const Address &adr) { \
1439 ld_st2(Rt, adr, size, op); \
1440 } \
1441
1442 INSN(str, 0b11, 0b00);
1443 INSN(strw, 0b10, 0b00);
1444 INSN(strb, 0b00, 0b00);
1445 INSN(strh, 0b01, 0b00);
1446
1447 INSN(ldr, 0b11, 0b01);
1448 INSN(ldrw, 0b10, 0b01);
1449 INSN(ldrb, 0b00, 0b01);
1450 INSN(ldrh, 0b01, 0b01);
1451
1452 INSN(ldrsb, 0b00, 0b10);
1453 INSN(ldrsbw, 0b00, 0b11);
1454 INSN(ldrsh, 0b01, 0b10);
1455 INSN(ldrshw, 0b01, 0b11);
1456 INSN(ldrsw, 0b10, 0b10);
1457
1458 #undef INSN
1459
1460 #define INSN(NAME, size, op) \
1461 void NAME(const Address &adr, prfop pfop = PLDL1KEEP) { \
1462 ld_st2((Register)pfop, adr, size, op); \
1463 }
1464
1465 INSN(prfm, 0b11, 0b10); // FIXME: PRFM should not be used with
1466 // writeback modes, but the assembler
1467 // doesn't enfore that.
1468
1469 #undef INSN
1470
1471 #define INSN(NAME, size, op) \
1472 void NAME(FloatRegister Rt, const Address &adr) { \
1473 ld_st2((Register)Rt, adr, size, op, 1); \
1474 }
1475
1476 INSN(strd, 0b11, 0b00);
1477 INSN(strs, 0b10, 0b00);
1478 INSN(ldrd, 0b11, 0b01);
1479 INSN(ldrs, 0b10, 0b01);
1480 INSN(strq, 0b00, 0b10);
1481 INSN(ldrq, 0x00, 0b11);
1482
1483 #undef INSN
1484
1485 /* SIMD extensions
1486 *
1487 * We just use FloatRegister in the following. They are exactly the same
1488 * as SIMD registers.
1489 */
1490 public:
1491
1492 enum SIMD_Arrangement {
1493 T8B, T16B, T4H, T8H, T2S, T4S, T1D, T2D, T1Q
1494 };
1495
1496 enum SIMD_RegVariant {
1497 B, H, S, D, Q
1498 };
1499
1500 enum shift_kind { LSL, LSR, ASR, ROR };
1501
1502 void op_shifted_reg(unsigned decode,
1503 enum shift_kind kind, unsigned shift,
1504 unsigned size, unsigned op) {
1505 f(size, 31);
1506 f(op, 30, 29);
1507 f(decode, 28, 24);
1508 f(shift, 15, 10);
1509 f(kind, 23, 22);
1510 }
1511
1512 // Logical (shifted register)
1513 #define INSN(NAME, size, op, N) \
1514 void NAME(Register Rd, Register Rn, Register Rm, \
1515 enum shift_kind kind = LSL, unsigned shift = 0) { \
1516 starti; \
1517 guarantee(size == 1 || shift < 32, "incorrect shift"); \
1518 f(N, 21); \
1519 zrf(Rm, 16), zrf(Rn, 5), zrf(Rd, 0); \
1520 op_shifted_reg(0b01010, kind, shift, size, op); \
1521 }
1522
1523 INSN(andr, 1, 0b00, 0);
1524 INSN(orr, 1, 0b01, 0);
1525 INSN(eor, 1, 0b10, 0);
1526 INSN(ands, 1, 0b11, 0);
1527 INSN(andw, 0, 0b00, 0);
1528 INSN(orrw, 0, 0b01, 0);
1529 INSN(eorw, 0, 0b10, 0);
1530 INSN(andsw, 0, 0b11, 0);
1531
1532 #undef INSN
1533
1534 #define INSN(NAME, size, op, N) \
1535 void NAME(Register Rd, Register Rn, Register Rm, \
1536 enum shift_kind kind = LSL, unsigned shift = 0) { \
1537 starti; \
1538 f(N, 21); \
1539 zrf(Rm, 16), zrf(Rn, 5), zrf(Rd, 0); \
1540 op_shifted_reg(0b01010, kind, shift, size, op); \
1541 } \
1542 \
1543 /* These instructions have no immediate form. Provide an overload so \
1544 that if anyone does try to use an immediate operand -- this has \
1545 happened! -- we'll get a compile-time error. */ \
1546 void NAME(Register Rd, Register Rn, unsigned imm, \
1547 enum shift_kind kind = LSL, unsigned shift = 0) { \
1548 assert(false, " can't be used with immediate operand"); \
1549 }
1550
1551 INSN(bic, 1, 0b00, 1);
1552 INSN(orn, 1, 0b01, 1);
1553 INSN(eon, 1, 0b10, 1);
1554 INSN(bics, 1, 0b11, 1);
1555 INSN(bicw, 0, 0b00, 1);
1556 INSN(ornw, 0, 0b01, 1);
1557 INSN(eonw, 0, 0b10, 1);
1558 INSN(bicsw, 0, 0b11, 1);
1559
1560 #undef INSN
1561
1562 // Aliases for short forms of orn
1563 void mvn(Register Rd, Register Rm,
1564 enum shift_kind kind = LSL, unsigned shift = 0) {
1565 orn(Rd, zr, Rm, kind, shift);
1566 }
1567
1568 void mvnw(Register Rd, Register Rm,
1569 enum shift_kind kind = LSL, unsigned shift = 0) {
1570 ornw(Rd, zr, Rm, kind, shift);
1571 }
1572
1573 // Add/subtract (shifted register)
1574 #define INSN(NAME, size, op) \
1575 void NAME(Register Rd, Register Rn, Register Rm, \
1576 enum shift_kind kind, unsigned shift = 0) { \
1577 starti; \
1578 f(0, 21); \
1579 assert_cond(kind != ROR); \
1580 guarantee(size == 1 || shift < 32, "incorrect shift");\
1581 zrf(Rd, 0), zrf(Rn, 5), zrf(Rm, 16); \
1582 op_shifted_reg(0b01011, kind, shift, size, op); \
1583 }
1584
1585 INSN(add, 1, 0b000);
1586 INSN(sub, 1, 0b10);
1587 INSN(addw, 0, 0b000);
1588 INSN(subw, 0, 0b10);
1589
1590 INSN(adds, 1, 0b001);
1591 INSN(subs, 1, 0b11);
1592 INSN(addsw, 0, 0b001);
1593 INSN(subsw, 0, 0b11);
1594
1595 #undef INSN
1596
1597 // Add/subtract (extended register)
1598 #define INSN(NAME, op) \
1599 void NAME(Register Rd, Register Rn, Register Rm, \
1600 ext::operation option, int amount = 0) { \
1601 starti; \
1602 zrf(Rm, 16), srf(Rn, 5), srf(Rd, 0); \
1603 add_sub_extended_reg(op, 0b01011, Rd, Rn, Rm, 0b00, option, amount); \
1604 }
1605
1606 void add_sub_extended_reg(unsigned op, unsigned decode,
1607 Register Rd, Register Rn, Register Rm,
1608 unsigned opt, ext::operation option, unsigned imm) {
1609 guarantee(imm <= 4, "shift amount must be <= 4");
1610 f(op, 31, 29), f(decode, 28, 24), f(opt, 23, 22), f(1, 21);
1611 f(option, 15, 13), f(imm, 12, 10);
1612 }
1613
1614 INSN(addw, 0b000);
1615 INSN(subw, 0b010);
1616 INSN(add, 0b100);
1617 INSN(sub, 0b110);
1618
1619 #undef INSN
1620
1621 #define INSN(NAME, op) \
1622 void NAME(Register Rd, Register Rn, Register Rm, \
1623 ext::operation option, int amount = 0) { \
1624 starti; \
1625 zrf(Rm, 16), srf(Rn, 5), zrf(Rd, 0); \
1626 add_sub_extended_reg(op, 0b01011, Rd, Rn, Rm, 0b00, option, amount); \
1627 }
1628
1629 INSN(addsw, 0b001);
1630 INSN(subsw, 0b011);
1631 INSN(adds, 0b101);
1632 INSN(subs, 0b111);
1633
1634 #undef INSN
1635
1636 // Aliases for short forms of add and sub
1637 #define INSN(NAME) \
1638 void NAME(Register Rd, Register Rn, Register Rm) { \
1639 if (Rd == sp || Rn == sp) \
1640 NAME(Rd, Rn, Rm, ext::uxtx); \
1641 else \
1642 NAME(Rd, Rn, Rm, LSL); \
1643 }
1644
1645 INSN(addw);
1646 INSN(subw);
1647 INSN(add);
1648 INSN(sub);
1649
1650 INSN(addsw);
1651 INSN(subsw);
1652 INSN(adds);
1653 INSN(subs);
1654
1655 #undef INSN
1656
1657 // Add/subtract (with carry)
1658 void add_sub_carry(unsigned op, Register Rd, Register Rn, Register Rm) {
1659 starti;
1660 f(op, 31, 29);
1661 f(0b11010000, 28, 21);
1662 f(0b000000, 15, 10);
1663 zrf(Rm, 16), zrf(Rn, 5), zrf(Rd, 0);
1664 }
1665
1666 #define INSN(NAME, op) \
1667 void NAME(Register Rd, Register Rn, Register Rm) { \
1668 add_sub_carry(op, Rd, Rn, Rm); \
1669 }
1670
1671 INSN(adcw, 0b000);
1672 INSN(adcsw, 0b001);
1673 INSN(sbcw, 0b010);
1674 INSN(sbcsw, 0b011);
1675 INSN(adc, 0b100);
1676 INSN(adcs, 0b101);
1677 INSN(sbc,0b110);
1678 INSN(sbcs, 0b111);
1679
1680 #undef INSN
1681
1682 // Conditional compare (both kinds)
1683 void conditional_compare(unsigned op, int o1, int o2, int o3,
1684 Register Rn, unsigned imm5, unsigned nzcv,
1685 unsigned cond) {
1686 starti;
1687 f(op, 31, 29);
1688 f(0b11010010, 28, 21);
1689 f(cond, 15, 12);
1690 f(o1, 11);
1691 f(o2, 10);
1692 f(o3, 4);
1693 f(nzcv, 3, 0);
1694 f(imm5, 20, 16), zrf(Rn, 5);
1695 }
1696
1697 #define INSN(NAME, op) \
1698 void NAME(Register Rn, Register Rm, int imm, Condition cond) { \
1699 int regNumber = (Rm == zr ? 31 : (uintptr_t)Rm); \
1700 conditional_compare(op, 0, 0, 0, Rn, regNumber, imm, cond); \
1701 } \
1702 \
1703 void NAME(Register Rn, int imm5, int imm, Condition cond) { \
1704 conditional_compare(op, 1, 0, 0, Rn, imm5, imm, cond); \
1705 }
1706
1707 INSN(ccmnw, 0b001);
1708 INSN(ccmpw, 0b011);
1709 INSN(ccmn, 0b101);
1710 INSN(ccmp, 0b111);
1711
1712 #undef INSN
1713
1714 // Conditional select
1715 void conditional_select(unsigned op, unsigned op2,
1716 Register Rd, Register Rn, Register Rm,
1717 unsigned cond) {
1718 starti;
1719 f(op, 31, 29);
1720 f(0b11010100, 28, 21);
1721 f(cond, 15, 12);
1722 f(op2, 11, 10);
1723 zrf(Rm, 16), zrf(Rn, 5), rf(Rd, 0);
1724 }
1725
1726 #define INSN(NAME, op, op2) \
1727 void NAME(Register Rd, Register Rn, Register Rm, Condition cond) { \
1728 conditional_select(op, op2, Rd, Rn, Rm, cond); \
1729 }
1730
1731 INSN(cselw, 0b000, 0b00);
1732 INSN(csincw, 0b000, 0b01);
1733 INSN(csinvw, 0b010, 0b00);
1734 INSN(csnegw, 0b010, 0b01);
1735 INSN(csel, 0b100, 0b00);
1736 INSN(csinc, 0b100, 0b01);
1737 INSN(csinv, 0b110, 0b00);
1738 INSN(csneg, 0b110, 0b01);
1739
1740 #undef INSN
1741
1742 // Data processing
1743 void data_processing(unsigned op29, unsigned opcode,
1744 Register Rd, Register Rn) {
1745 f(op29, 31, 29), f(0b11010110, 28, 21);
1746 f(opcode, 15, 10);
1747 rf(Rn, 5), rf(Rd, 0);
1748 }
1749
1750 // (1 source)
1751 #define INSN(NAME, op29, opcode2, opcode) \
1752 void NAME(Register Rd, Register Rn) { \
1753 starti; \
1754 f(opcode2, 20, 16); \
1755 data_processing(op29, opcode, Rd, Rn); \
1756 }
1757
1758 INSN(rbitw, 0b010, 0b00000, 0b00000);
1759 INSN(rev16w, 0b010, 0b00000, 0b00001);
1760 INSN(revw, 0b010, 0b00000, 0b00010);
1761 INSN(clzw, 0b010, 0b00000, 0b00100);
1762 INSN(clsw, 0b010, 0b00000, 0b00101);
1763
1764 INSN(rbit, 0b110, 0b00000, 0b00000);
1765 INSN(rev16, 0b110, 0b00000, 0b00001);
1766 INSN(rev32, 0b110, 0b00000, 0b00010);
1767 INSN(rev, 0b110, 0b00000, 0b00011);
1768 INSN(clz, 0b110, 0b00000, 0b00100);
1769 INSN(cls, 0b110, 0b00000, 0b00101);
1770
1771 #undef INSN
1772
1773 // (2 sources)
1774 #define INSN(NAME, op29, opcode) \
1775 void NAME(Register Rd, Register Rn, Register Rm) { \
1776 starti; \
1777 rf(Rm, 16); \
1778 data_processing(op29, opcode, Rd, Rn); \
1779 }
1780
1781 INSN(udivw, 0b000, 0b000010);
1782 INSN(sdivw, 0b000, 0b000011);
1783 INSN(lslvw, 0b000, 0b001000);
1784 INSN(lsrvw, 0b000, 0b001001);
1785 INSN(asrvw, 0b000, 0b001010);
1786 INSN(rorvw, 0b000, 0b001011);
1787
1788 INSN(udiv, 0b100, 0b000010);
1789 INSN(sdiv, 0b100, 0b000011);
1790 INSN(lslv, 0b100, 0b001000);
1791 INSN(lsrv, 0b100, 0b001001);
1792 INSN(asrv, 0b100, 0b001010);
1793 INSN(rorv, 0b100, 0b001011);
1794
1795 #undef INSN
1796
1797 // (3 sources)
1798 void data_processing(unsigned op54, unsigned op31, unsigned o0,
1799 Register Rd, Register Rn, Register Rm,
1800 Register Ra) {
1801 starti;
1802 f(op54, 31, 29), f(0b11011, 28, 24);
1803 f(op31, 23, 21), f(o0, 15);
1804 zrf(Rm, 16), zrf(Ra, 10), zrf(Rn, 5), zrf(Rd, 0);
1805 }
1806
1807 #define INSN(NAME, op54, op31, o0) \
1808 void NAME(Register Rd, Register Rn, Register Rm, Register Ra) { \
1809 data_processing(op54, op31, o0, Rd, Rn, Rm, Ra); \
1810 }
1811
1812 INSN(maddw, 0b000, 0b000, 0);
1813 INSN(msubw, 0b000, 0b000, 1);
1814 INSN(madd, 0b100, 0b000, 0);
1815 INSN(msub, 0b100, 0b000, 1);
1816 INSN(smaddl, 0b100, 0b001, 0);
1817 INSN(smsubl, 0b100, 0b001, 1);
1818 INSN(umaddl, 0b100, 0b101, 0);
1819 INSN(umsubl, 0b100, 0b101, 1);
1820
1821 #undef INSN
1822
1823 #define INSN(NAME, op54, op31, o0) \
1824 void NAME(Register Rd, Register Rn, Register Rm) { \
1825 data_processing(op54, op31, o0, Rd, Rn, Rm, (Register)31); \
1826 }
1827
1828 INSN(smulh, 0b100, 0b010, 0);
1829 INSN(umulh, 0b100, 0b110, 0);
1830
1831 #undef INSN
1832
1833 // Floating-point data-processing (1 source)
1834 void data_processing(unsigned op31, unsigned type, unsigned opcode,
1835 FloatRegister Vd, FloatRegister Vn) {
1836 starti;
1837 f(op31, 31, 29);
1838 f(0b11110, 28, 24);
1839 f(type, 23, 22), f(1, 21), f(opcode, 20, 15), f(0b10000, 14, 10);
1840 rf(Vn, 5), rf(Vd, 0);
1841 }
1842
1843 #define INSN(NAME, op31, type, opcode) \
1844 void NAME(FloatRegister Vd, FloatRegister Vn) { \
1845 data_processing(op31, type, opcode, Vd, Vn); \
1846 }
1847
1848 private:
1849 INSN(i_fmovs, 0b000, 0b00, 0b000000);
1850 public:
1851 INSN(fabss, 0b000, 0b00, 0b000001);
1852 INSN(fnegs, 0b000, 0b00, 0b000010);
1853 INSN(fsqrts, 0b000, 0b00, 0b000011);
1854 INSN(fcvts, 0b000, 0b00, 0b000101); // Single-precision to double-precision
1855
1856 private:
1857 INSN(i_fmovd, 0b000, 0b01, 0b000000);
1858 public:
1859 INSN(fabsd, 0b000, 0b01, 0b000001);
1860 INSN(fnegd, 0b000, 0b01, 0b000010);
1861 INSN(fsqrtd, 0b000, 0b01, 0b000011);
1862 INSN(fcvtd, 0b000, 0b01, 0b000100); // Double-precision to single-precision
1863
1864 void fmovd(FloatRegister Vd, FloatRegister Vn) {
1865 assert(Vd != Vn, "should be");
1866 i_fmovd(Vd, Vn);
1867 }
1868
1869 void fmovs(FloatRegister Vd, FloatRegister Vn) {
1870 assert(Vd != Vn, "should be");
1871 i_fmovs(Vd, Vn);
1872 }
1873
1874 private:
1875 void _fcvt_narrow_extend(FloatRegister Vd, SIMD_Arrangement Ta,
1876 FloatRegister Vn, SIMD_Arrangement Tb, bool do_extend) {
1877 assert((do_extend && (Tb >> 1) + 1 == (Ta >> 1))
1878 || (!do_extend && (Ta >> 1) + 1 == (Tb >> 1)), "Incompatible arrangement");
1879 starti;
1880 int op30 = (do_extend ? Tb : Ta) & 1;
1881 int op22 = ((do_extend ? Ta : Tb) >> 1) & 1;
1882 f(0, 31), f(op30, 30), f(0b0011100, 29, 23), f(op22, 22);
1883 f(0b100001011, 21, 13), f(do_extend ? 1 : 0, 12), f(0b10, 11, 10);
1884 rf(Vn, 5), rf(Vd, 0);
1885 }
1886
1887 public:
1888 void fcvtl(FloatRegister Vd, SIMD_Arrangement Ta, FloatRegister Vn, SIMD_Arrangement Tb) {
1889 assert(Tb == T4H || Tb == T8H|| Tb == T2S || Tb == T4S, "invalid arrangement");
1890 _fcvt_narrow_extend(Vd, Ta, Vn, Tb, true);
1891 }
1892
1893 void fcvtn(FloatRegister Vd, SIMD_Arrangement Ta, FloatRegister Vn, SIMD_Arrangement Tb) {
1894 assert(Ta == T4H || Ta == T8H|| Ta == T2S || Ta == T4S, "invalid arrangement");
1895 _fcvt_narrow_extend(Vd, Ta, Vn, Tb, false);
1896 }
1897
1898 #undef INSN
1899
1900 // Floating-point data-processing (2 source)
1901 void data_processing(unsigned op31, unsigned type, unsigned opcode,
1902 FloatRegister Vd, FloatRegister Vn, FloatRegister Vm) {
1903 starti;
1904 f(op31, 31, 29);
1905 f(0b11110, 28, 24);
1906 f(type, 23, 22), f(1, 21), f(opcode, 15, 12), f(0b10, 11, 10);
1907 rf(Vm, 16), rf(Vn, 5), rf(Vd, 0);
1908 }
1909
1910 #define INSN(NAME, op31, type, opcode) \
1911 void NAME(FloatRegister Vd, FloatRegister Vn, FloatRegister Vm) { \
1912 data_processing(op31, type, opcode, Vd, Vn, Vm); \
1913 }
1914
1915 INSN(fmuls, 0b000, 0b00, 0b0000);
1916 INSN(fdivs, 0b000, 0b00, 0b0001);
1917 INSN(fadds, 0b000, 0b00, 0b0010);
1918 INSN(fsubs, 0b000, 0b00, 0b0011);
1919 INSN(fmaxs, 0b000, 0b00, 0b0100);
1920 INSN(fmins, 0b000, 0b00, 0b0101);
1921 INSN(fnmuls, 0b000, 0b00, 0b1000);
1922
1923 INSN(fmuld, 0b000, 0b01, 0b0000);
1924 INSN(fdivd, 0b000, 0b01, 0b0001);
1925 INSN(faddd, 0b000, 0b01, 0b0010);
1926 INSN(fsubd, 0b000, 0b01, 0b0011);
1927 INSN(fmaxd, 0b000, 0b01, 0b0100);
1928 INSN(fmind, 0b000, 0b01, 0b0101);
1929 INSN(fnmuld, 0b000, 0b01, 0b1000);
1930
1931 #undef INSN
1932
1933 // Floating-point data-processing (3 source)
1934 void data_processing(unsigned op31, unsigned type, unsigned o1, unsigned o0,
1935 FloatRegister Vd, FloatRegister Vn, FloatRegister Vm,
1936 FloatRegister Va) {
1937 starti;
1938 f(op31, 31, 29);
1939 f(0b11111, 28, 24);
1940 f(type, 23, 22), f(o1, 21), f(o0, 15);
1941 rf(Vm, 16), rf(Va, 10), rf(Vn, 5), rf(Vd, 0);
1942 }
1943
1944 #define INSN(NAME, op31, type, o1, o0) \
1945 void NAME(FloatRegister Vd, FloatRegister Vn, FloatRegister Vm, \
1946 FloatRegister Va) { \
1947 data_processing(op31, type, o1, o0, Vd, Vn, Vm, Va); \
1948 }
1949
1950 INSN(fmadds, 0b000, 0b00, 0, 0);
1951 INSN(fmsubs, 0b000, 0b00, 0, 1);
1952 INSN(fnmadds, 0b000, 0b00, 1, 0);
1953 INSN(fnmsubs, 0b000, 0b00, 1, 1);
1954
1955 INSN(fmaddd, 0b000, 0b01, 0, 0);
1956 INSN(fmsubd, 0b000, 0b01, 0, 1);
1957 INSN(fnmaddd, 0b000, 0b01, 1, 0);
1958 INSN(fnmsub, 0b000, 0b01, 1, 1);
1959
1960 #undef INSN
1961
1962 // Floating-point conditional select
1963 void fp_conditional_select(unsigned op31, unsigned type,
1964 unsigned op1, unsigned op2,
1965 Condition cond, FloatRegister Vd,
1966 FloatRegister Vn, FloatRegister Vm) {
1967 starti;
1968 f(op31, 31, 29);
1969 f(0b11110, 28, 24);
1970 f(type, 23, 22);
1971 f(op1, 21, 21);
1972 f(op2, 11, 10);
1973 f(cond, 15, 12);
1974 rf(Vm, 16), rf(Vn, 5), rf(Vd, 0);
1975 }
1976
1977 #define INSN(NAME, op31, type, op1, op2) \
1978 void NAME(FloatRegister Vd, FloatRegister Vn, \
1979 FloatRegister Vm, Condition cond) { \
1980 fp_conditional_select(op31, type, op1, op2, cond, Vd, Vn, Vm); \
1981 }
1982
1983 INSN(fcsels, 0b000, 0b00, 0b1, 0b11);
1984 INSN(fcseld, 0b000, 0b01, 0b1, 0b11);
1985
1986 #undef INSN
1987
1988 // Floating-point<->integer conversions
1989 void float_int_convert(unsigned op31, unsigned type,
1990 unsigned rmode, unsigned opcode,
1991 Register Rd, Register Rn) {
1992 starti;
1993 f(op31, 31, 29);
1994 f(0b11110, 28, 24);
1995 f(type, 23, 22), f(1, 21), f(rmode, 20, 19);
1996 f(opcode, 18, 16), f(0b000000, 15, 10);
1997 zrf(Rn, 5), zrf(Rd, 0);
1998 }
1999
2000 #define INSN(NAME, op31, type, rmode, opcode) \
2001 void NAME(Register Rd, FloatRegister Vn) { \
2002 float_int_convert(op31, type, rmode, opcode, Rd, (Register)Vn); \
2003 }
2004
2005 INSN(fcvtzsw, 0b000, 0b00, 0b11, 0b000);
2006 INSN(fcvtzs, 0b100, 0b00, 0b11, 0b000);
2007 INSN(fcvtzdw, 0b000, 0b01, 0b11, 0b000);
2008 INSN(fcvtzd, 0b100, 0b01, 0b11, 0b000);
2009
2010 INSN(fmovs, 0b000, 0b00, 0b00, 0b110);
2011 INSN(fmovd, 0b100, 0b01, 0b00, 0b110);
2012
2013 // INSN(fmovhid, 0b100, 0b10, 0b01, 0b110);
2014
2015 #undef INSN
2016
2017 #define INSN(NAME, op31, type, rmode, opcode) \
2018 void NAME(FloatRegister Vd, Register Rn) { \
2019 float_int_convert(op31, type, rmode, opcode, (Register)Vd, Rn); \
2020 }
2021
2022 INSN(fmovs, 0b000, 0b00, 0b00, 0b111);
2023 INSN(fmovd, 0b100, 0b01, 0b00, 0b111);
2024
2025 INSN(scvtfws, 0b000, 0b00, 0b00, 0b010);
2026 INSN(scvtfs, 0b100, 0b00, 0b00, 0b010);
2027 INSN(scvtfwd, 0b000, 0b01, 0b00, 0b010);
2028 INSN(scvtfd, 0b100, 0b01, 0b00, 0b010);
2029
2030 // INSN(fmovhid, 0b100, 0b10, 0b01, 0b111);
2031
2032 #undef INSN
2033
2034 enum sign_kind { SIGNED, UNSIGNED };
2035
2036 private:
2037 void _xcvtf_scalar_integer(sign_kind sign, unsigned sz,
2038 FloatRegister Rd, FloatRegister Rn) {
2039 starti;
2040 f(0b01, 31, 30), f(sign == SIGNED ? 0 : 1, 29);
2041 f(0b111100, 27, 23), f((sz >> 1) & 1, 22), f(0b100001110110, 21, 10);
2042 rf(Rn, 5), rf(Rd, 0);
2043 }
2044
2045 public:
2046 #define INSN(NAME, sign, sz) \
2047 void NAME(FloatRegister Rd, FloatRegister Rn) { \
2048 _xcvtf_scalar_integer(sign, sz, Rd, Rn); \
2049 }
2050
2051 INSN(scvtfs, SIGNED, 0);
2052 INSN(scvtfd, SIGNED, 1);
2053
2054 #undef INSN
2055
2056 private:
2057 void _xcvtf_vector_integer(sign_kind sign, SIMD_Arrangement T,
2058 FloatRegister Rd, FloatRegister Rn) {
2059 assert(T == T2S || T == T4S || T == T2D, "invalid arrangement");
2060 starti;
2061 f(0, 31), f(T & 1, 30), f(sign == SIGNED ? 0 : 1, 29);
2062 f(0b011100, 28, 23), f((T >> 1) & 1, 22), f(0b100001110110, 21, 10);
2063 rf(Rn, 5), rf(Rd, 0);
2064 }
2065
2066 public:
2067 void scvtfv(SIMD_Arrangement T, FloatRegister Rd, FloatRegister Rn) {
2068 _xcvtf_vector_integer(SIGNED, T, Rd, Rn);
2069 }
2070
2071 // Floating-point compare
2072 void float_compare(unsigned op31, unsigned type,
2073 unsigned op, unsigned op2,
2074 FloatRegister Vn, FloatRegister Vm = (FloatRegister)0) {
2075 starti;
2076 f(op31, 31, 29);
2077 f(0b11110, 28, 24);
2078 f(type, 23, 22), f(1, 21);
2079 f(op, 15, 14), f(0b1000, 13, 10), f(op2, 4, 0);
2080 rf(Vn, 5), rf(Vm, 16);
2081 }
2082
2083
2084 #define INSN(NAME, op31, type, op, op2) \
2085 void NAME(FloatRegister Vn, FloatRegister Vm) { \
2086 float_compare(op31, type, op, op2, Vn, Vm); \
2087 }
2088
2089 #define INSN1(NAME, op31, type, op, op2) \
2090 void NAME(FloatRegister Vn, double d) { \
2091 assert_cond(d == 0.0); \
2092 float_compare(op31, type, op, op2, Vn); \
2093 }
2094
2095 INSN(fcmps, 0b000, 0b00, 0b00, 0b00000);
2096 INSN1(fcmps, 0b000, 0b00, 0b00, 0b01000);
2097 // INSN(fcmpes, 0b000, 0b00, 0b00, 0b10000);
2098 // INSN1(fcmpes, 0b000, 0b00, 0b00, 0b11000);
2099
2100 INSN(fcmpd, 0b000, 0b01, 0b00, 0b00000);
2101 INSN1(fcmpd, 0b000, 0b01, 0b00, 0b01000);
2102 // INSN(fcmped, 0b000, 0b01, 0b00, 0b10000);
2103 // INSN1(fcmped, 0b000, 0b01, 0b00, 0b11000);
2104
2105 #undef INSN
2106 #undef INSN1
2107
2108 // Floating-point Move (immediate)
2109 private:
2110 unsigned pack(double value);
2111
2112 void fmov_imm(FloatRegister Vn, double value, unsigned size) {
2113 starti;
2114 f(0b00011110, 31, 24), f(size, 23, 22), f(1, 21);
2115 f(pack(value), 20, 13), f(0b10000000, 12, 5);
2116 rf(Vn, 0);
2117 }
2118
2119 public:
2120
2121 void fmovs(FloatRegister Vn, double value) {
2122 if (value)
2123 fmov_imm(Vn, value, 0b00);
2124 else
2125 fmovs(Vn, zr);
2126 }
2127 void fmovd(FloatRegister Vn, double value) {
2128 if (value)
2129 fmov_imm(Vn, value, 0b01);
2130 else
2131 fmovd(Vn, zr);
2132 }
2133
2134 // Floating-point rounding
2135 // type: half-precision = 11
2136 // single = 00
2137 // double = 01
2138 // rmode: A = Away = 100
2139 // I = current = 111
2140 // M = MinusInf = 010
2141 // N = eveN = 000
2142 // P = PlusInf = 001
2143 // X = eXact = 110
2144 // Z = Zero = 011
2145 void float_round(unsigned type, unsigned rmode, FloatRegister Rd, FloatRegister Rn) {
2146 starti;
2147 f(0b00011110, 31, 24);
2148 f(type, 23, 22);
2149 f(0b1001, 21, 18);
2150 f(rmode, 17, 15);
2151 f(0b10000, 14, 10);
2152 rf(Rn, 5), rf(Rd, 0);
2153 }
2154 #define INSN(NAME, type, rmode) \
2155 void NAME(FloatRegister Vd, FloatRegister Vn) { \
2156 float_round(type, rmode, Vd, Vn); \
2157 }
2158
2159 public:
2160 INSN(frintah, 0b11, 0b100);
2161 INSN(frintih, 0b11, 0b111);
2162 INSN(frintmh, 0b11, 0b010);
2163 INSN(frintnh, 0b11, 0b000);
2164 INSN(frintph, 0b11, 0b001);
2165 INSN(frintxh, 0b11, 0b110);
2166 INSN(frintzh, 0b11, 0b011);
2167
2168 INSN(frintas, 0b00, 0b100);
2169 INSN(frintis, 0b00, 0b111);
2170 INSN(frintms, 0b00, 0b010);
2171 INSN(frintns, 0b00, 0b000);
2172 INSN(frintps, 0b00, 0b001);
2173 INSN(frintxs, 0b00, 0b110);
2174 INSN(frintzs, 0b00, 0b011);
2175
2176 INSN(frintad, 0b01, 0b100);
2177 INSN(frintid, 0b01, 0b111);
2178 INSN(frintmd, 0b01, 0b010);
2179 INSN(frintnd, 0b01, 0b000);
2180 INSN(frintpd, 0b01, 0b001);
2181 INSN(frintxd, 0b01, 0b110);
2182 INSN(frintzd, 0b01, 0b011);
2183 #undef INSN
2184
2185 private:
2186 static short SIMD_Size_in_bytes[];
2187
2188 public:
2189 #define INSN(NAME, op) \
2190 void NAME(FloatRegister Rt, SIMD_RegVariant T, const Address &adr) { \
2191 ld_st2((Register)Rt, adr, (int)T & 3, op + ((T==Q) ? 0b10:0b00), 1); \
2192 } \
2193
2194 INSN(ldr, 1);
2195 INSN(str, 0);
2196
2197 #undef INSN
2198
2199 private:
2200
2201 void ld_st(FloatRegister Vt, SIMD_Arrangement T, Register Xn, int op1, int op2) {
2202 starti;
2203 f(0,31), f((int)T & 1, 30);
2204 f(op1, 29, 21), f(0, 20, 16), f(op2, 15, 12);
2205 f((int)T >> 1, 11, 10), srf(Xn, 5), rf(Vt, 0);
2206 }
2207 void ld_st(FloatRegister Vt, SIMD_Arrangement T, Register Xn,
2208 int imm, int op1, int op2, int regs) {
2209
2210 bool replicate = op2 >> 2 == 3;
2211 // post-index value (imm) is formed differently for replicate/non-replicate ld* instructions
2212 int expectedImmediate = replicate ? regs * (1 << (T >> 1)) : SIMD_Size_in_bytes[T] * regs;
2213 guarantee(T < T1Q , "incorrect arrangement");
2214 guarantee(imm == expectedImmediate, "bad offset");
2215 starti;
2216 f(0,31), f((int)T & 1, 30);
2217 f(op1 | 0b100, 29, 21), f(0b11111, 20, 16), f(op2, 15, 12);
2218 f((int)T >> 1, 11, 10), srf(Xn, 5), rf(Vt, 0);
2219 }
2220 void ld_st(FloatRegister Vt, SIMD_Arrangement T, Register Xn,
2221 Register Xm, int op1, int op2) {
2222 starti;
2223 f(0,31), f((int)T & 1, 30);
2224 f(op1 | 0b100, 29, 21), rf(Xm, 16), f(op2, 15, 12);
2225 f((int)T >> 1, 11, 10), srf(Xn, 5), rf(Vt, 0);
2226 }
2227
2228 void ld_st(FloatRegister Vt, SIMD_Arrangement T, Address a, int op1, int op2, int regs) {
2229 switch (a.getMode()) {
2230 case Address::base_plus_offset:
2231 guarantee(a.offset() == 0, "no offset allowed here");
2232 ld_st(Vt, T, a.base(), op1, op2);
2233 break;
2234 case Address::post:
2235 ld_st(Vt, T, a.base(), a.offset(), op1, op2, regs);
2236 break;
2237 case Address::post_reg:
2238 ld_st(Vt, T, a.base(), a.index(), op1, op2);
2239 break;
2240 default:
2241 ShouldNotReachHere();
2242 }
2243 }
2244
2245 public:
2246
2247 #define INSN1(NAME, op1, op2) \
2248 void NAME(FloatRegister Vt, SIMD_Arrangement T, const Address &a) { \
2249 ld_st(Vt, T, a, op1, op2, 1); \
2250 }
2251
2252 #define INSN2(NAME, op1, op2) \
2253 void NAME(FloatRegister Vt, FloatRegister Vt2, SIMD_Arrangement T, const Address &a) { \
2254 assert(Vt->successor() == Vt2, "Registers must be ordered"); \
2255 ld_st(Vt, T, a, op1, op2, 2); \
2256 }
2257
2258 #define INSN3(NAME, op1, op2) \
2259 void NAME(FloatRegister Vt, FloatRegister Vt2, FloatRegister Vt3, \
2260 SIMD_Arrangement T, const Address &a) { \
2261 assert(Vt->successor() == Vt2 && Vt2->successor() == Vt3, \
2262 "Registers must be ordered"); \
2263 ld_st(Vt, T, a, op1, op2, 3); \
2264 }
2265
2266 #define INSN4(NAME, op1, op2) \
2267 void NAME(FloatRegister Vt, FloatRegister Vt2, FloatRegister Vt3, \
2268 FloatRegister Vt4, SIMD_Arrangement T, const Address &a) { \
2269 assert(Vt->successor() == Vt2 && Vt2->successor() == Vt3 && \
2270 Vt3->successor() == Vt4, "Registers must be ordered"); \
2271 ld_st(Vt, T, a, op1, op2, 4); \
2272 }
2273
2274 INSN1(ld1, 0b001100010, 0b0111);
2275 INSN2(ld1, 0b001100010, 0b1010);
2276 INSN3(ld1, 0b001100010, 0b0110);
2277 INSN4(ld1, 0b001100010, 0b0010);
2278
2279 INSN2(ld2, 0b001100010, 0b1000);
2280 INSN3(ld3, 0b001100010, 0b0100);
2281 INSN4(ld4, 0b001100010, 0b0000);
2282
2283 INSN1(st1, 0b001100000, 0b0111);
2284 INSN2(st1, 0b001100000, 0b1010);
2285 INSN3(st1, 0b001100000, 0b0110);
2286 INSN4(st1, 0b001100000, 0b0010);
2287
2288 INSN2(st2, 0b001100000, 0b1000);
2289 INSN3(st3, 0b001100000, 0b0100);
2290 INSN4(st4, 0b001100000, 0b0000);
2291
2292 INSN1(ld1r, 0b001101010, 0b1100);
2293 INSN2(ld2r, 0b001101011, 0b1100);
2294 INSN3(ld3r, 0b001101010, 0b1110);
2295 INSN4(ld4r, 0b001101011, 0b1110);
2296
2297 #undef INSN1
2298 #undef INSN2
2299 #undef INSN3
2300 #undef INSN4
2301
2302 #define INSN(NAME, opc) \
2303 void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn, FloatRegister Vm) { \
2304 starti; \
2305 assert(T == T8B || T == T16B, "must be T8B or T16B"); \
2306 f(0, 31), f((int)T & 1, 30), f(opc, 29, 21); \
2307 rf(Vm, 16), f(0b000111, 15, 10), rf(Vn, 5), rf(Vd, 0); \
2308 }
2309
2310 INSN(eor, 0b101110001);
2311 INSN(orr, 0b001110101);
2312 INSN(andr, 0b001110001);
2313 INSN(bic, 0b001110011);
2314 INSN(bif, 0b101110111);
2315 INSN(bit, 0b101110101);
2316 INSN(bsl, 0b101110011);
2317 INSN(orn, 0b001110111);
2318
2319 #undef INSN
2320
2321 #define INSN(NAME, opc, opc2, acceptT2D) \
2322 void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn, FloatRegister Vm) { \
2323 guarantee(T != T1Q && T != T1D, "incorrect arrangement"); \
2324 if (!acceptT2D) guarantee(T != T2D, "incorrect arrangement"); \
2325 starti; \
2326 f(0, 31), f((int)T & 1, 30), f(opc, 29), f(0b01110, 28, 24); \
2327 f((int)T >> 1, 23, 22), f(1, 21), rf(Vm, 16), f(opc2, 15, 10); \
2328 rf(Vn, 5), rf(Vd, 0); \
2329 }
2330
2331 INSN(addv, 0, 0b100001, true); // accepted arrangements: T8B, T16B, T4H, T8H, T2S, T4S, T2D
2332 INSN(subv, 1, 0b100001, true); // accepted arrangements: T8B, T16B, T4H, T8H, T2S, T4S, T2D
2333 INSN(mulv, 0, 0b100111, false); // accepted arrangements: T8B, T16B, T4H, T8H, T2S, T4S
2334 INSN(mlav, 0, 0b100101, false); // accepted arrangements: T8B, T16B, T4H, T8H, T2S, T4S
2335 INSN(mlsv, 1, 0b100101, false); // accepted arrangements: T8B, T16B, T4H, T8H, T2S, T4S
2336 INSN(sshl, 0, 0b010001, true); // accepted arrangements: T8B, T16B, T4H, T8H, T2S, T4S, T2D
2337 INSN(ushl, 1, 0b010001, true); // accepted arrangements: T8B, T16B, T4H, T8H, T2S, T4S, T2D
2338 INSN(addpv, 0, 0b101111, true); // accepted arrangements: T8B, T16B, T4H, T8H, T2S, T4S, T2D
2339 INSN(smullv, 0, 0b110000, false); // accepted arrangements: T8B, T16B, T4H, T8H, T2S, T4S
2340 INSN(umullv, 1, 0b110000, false); // accepted arrangements: T8B, T16B, T4H, T8H, T2S, T4S
2341 INSN(umlalv, 1, 0b100000, false); // accepted arrangements: T8B, T16B, T4H, T8H, T2S, T4S
2342 INSN(maxv, 0, 0b011001, false); // accepted arrangements: T8B, T16B, T4H, T8H, T2S, T4S
2343 INSN(minv, 0, 0b011011, false); // accepted arrangements: T8B, T16B, T4H, T8H, T2S, T4S
2344 INSN(cmeq, 1, 0b100011, true); // accepted arrangements: T8B, T16B, T4H, T8H, T2S, T4S, T2D
2345 INSN(cmgt, 0, 0b001101, true); // accepted arrangements: T8B, T16B, T4H, T8H, T2S, T4S, T2D
2346 INSN(cmge, 0, 0b001111, true); // accepted arrangements: T8B, T16B, T4H, T8H, T2S, T4S, T2D
2347
2348 #undef INSN
2349
2350 #define INSN(NAME, opc, opc2, accepted) \
2351 void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn) { \
2352 guarantee(T != T1Q && T != T1D, "incorrect arrangement"); \
2353 if (accepted < 3) guarantee(T != T2D, "incorrect arrangement"); \
2354 if (accepted < 2) guarantee(T != T2S, "incorrect arrangement"); \
2355 if (accepted < 1) guarantee(T == T8B || T == T16B, "incorrect arrangement"); \
2356 starti; \
2357 f(0, 31), f((int)T & 1, 30), f(opc, 29), f(0b01110, 28, 24); \
2358 f((int)T >> 1, 23, 22), f(opc2, 21, 10); \
2359 rf(Vn, 5), rf(Vd, 0); \
2360 }
2361
2362 INSN(absr, 0, 0b100000101110, 3); // accepted arrangements: T8B, T16B, T4H, T8H, T2S, T4S, T2D
2363 INSN(negr, 1, 0b100000101110, 3); // accepted arrangements: T8B, T16B, T4H, T8H, T2S, T4S, T2D
2364 INSN(notr, 1, 0b100000010110, 0); // accepted arrangements: T8B, T16B
2365 INSN(addv, 0, 0b110001101110, 1); // accepted arrangements: T8B, T16B, T4H, T8H, T4S
2366 INSN(smaxv, 0, 0b110000101010, 1); // accepted arrangements: T8B, T16B, T4H, T8H, T4S
2367 INSN(sminv, 0, 0b110001101010, 1); // accepted arrangements: T8B, T16B, T4H, T8H, T4S
2368 INSN(cls, 0, 0b100000010010, 2); // accepted arrangements: T8B, T16B, T4H, T8H, T2S, T4S
2369 INSN(clz, 1, 0b100000010010, 2); // accepted arrangements: T8B, T16B, T4H, T8H, T2S, T4S
2370 INSN(cnt, 0, 0b100000010110, 0); // accepted arrangements: T8B, T16B
2371 INSN(uaddlp, 1, 0b100000001010, 2); // accepted arrangements: T8B, T16B, T4H, T8H, T2S, T4S
2372 INSN(uaddlv, 1, 0b110000001110, 1); // accepted arrangements: T8B, T16B, T4H, T8H, T4S
2373
2374 #undef INSN
2375
2376 #define INSN(NAME, opc) \
2377 void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn) { \
2378 starti; \
2379 assert(T == T4S, "arrangement must be T4S"); \
2380 f(0, 31), f((int)T & 1, 30), f(0b101110, 29, 24), f(opc, 23), \
2381 f(T == T4S ? 0 : 1, 22), f(0b110000111110, 21, 10); rf(Vn, 5), rf(Vd, 0); \
2382 }
2383
2384 INSN(fmaxv, 0);
2385 INSN(fminv, 1);
2386
2387 #undef INSN
2388
2389 #define INSN(NAME, op0, cmode0) \
2390 void NAME(FloatRegister Vd, SIMD_Arrangement T, unsigned imm8, unsigned lsl = 0) { \
2391 unsigned cmode = cmode0; \
2392 unsigned op = op0; \
2393 starti; \
2394 assert(lsl == 0 || \
2395 ((T == T4H || T == T8H) && lsl == 8) || \
2396 ((T == T2S || T == T4S) && ((lsl >> 3) < 4) && ((lsl & 7) == 0)), "invalid shift");\
2397 cmode |= lsl >> 2; \
2398 if (T == T4H || T == T8H) cmode |= 0b1000; \
2399 if (!(T == T4H || T == T8H || T == T2S || T == T4S)) { \
2400 assert(op == 0 && cmode0 == 0, "must be MOVI"); \
2401 cmode = 0b1110; \
2402 if (T == T1D || T == T2D) op = 1; \
2403 } \
2404 f(0, 31), f((int)T & 1, 30), f(op, 29), f(0b0111100000, 28, 19); \
2405 f(imm8 >> 5, 18, 16), f(cmode, 15, 12), f(0x01, 11, 10), f(imm8 & 0b11111, 9, 5); \
2406 rf(Vd, 0); \
2407 }
2408
2409 INSN(movi, 0, 0);
2410 INSN(orri, 0, 1);
2411 INSN(mvni, 1, 0);
2412 INSN(bici, 1, 1);
2413
2414 #undef INSN
2415
2416 #define INSN(NAME, op1, op2, op3) \
2417 void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn, FloatRegister Vm) { \
2418 starti; \
2419 assert(T == T2S || T == T4S || T == T2D, "invalid arrangement"); \
2420 f(0, 31), f((int)T & 1, 30), f(op1, 29), f(0b01110, 28, 24), f(op2, 23); \
2421 f(T==T2D ? 1:0, 22); f(1, 21), rf(Vm, 16), f(op3, 15, 10), rf(Vn, 5), rf(Vd, 0); \
2422 }
2423
2424 INSN(fadd, 0, 0, 0b110101);
2425 INSN(fdiv, 1, 0, 0b111111);
2426 INSN(fmul, 1, 0, 0b110111);
2427 INSN(fsub, 0, 1, 0b110101);
2428 INSN(fmla, 0, 0, 0b110011);
2429 INSN(fmls, 0, 1, 0b110011);
2430 INSN(fmax, 0, 0, 0b111101);
2431 INSN(fmin, 0, 1, 0b111101);
2432 INSN(fcmeq, 0, 0, 0b111001);
2433 INSN(fcmgt, 1, 1, 0b111001);
2434 INSN(fcmge, 1, 0, 0b111001);
2435
2436 #undef INSN
2437
2438 #define INSN(NAME, opc) \
2439 void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn, FloatRegister Vm) { \
2440 starti; \
2441 assert(T == T4S, "arrangement must be T4S"); \
2442 f(0b01011110000, 31, 21), rf(Vm, 16), f(opc, 15, 10), rf(Vn, 5), rf(Vd, 0); \
2443 }
2444
2445 INSN(sha1c, 0b000000);
2446 INSN(sha1m, 0b001000);
2447 INSN(sha1p, 0b000100);
2448 INSN(sha1su0, 0b001100);
2449 INSN(sha256h2, 0b010100);
2450 INSN(sha256h, 0b010000);
2451 INSN(sha256su1, 0b011000);
2452
2453 #undef INSN
2454
2455 #define INSN(NAME, opc) \
2456 void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn) { \
2457 starti; \
2458 assert(T == T4S, "arrangement must be T4S"); \
2459 f(0b0101111000101000, 31, 16), f(opc, 15, 10), rf(Vn, 5), rf(Vd, 0); \
2460 }
2461
2462 INSN(sha1h, 0b000010);
2463 INSN(sha1su1, 0b000110);
2464 INSN(sha256su0, 0b001010);
2465
2466 #undef INSN
2467
2468 #define INSN(NAME, opc) \
2469 void NAME(FloatRegister Vd, FloatRegister Vn) { \
2470 starti; \
2471 f(opc, 31, 10), rf(Vn, 5), rf(Vd, 0); \
2472 }
2473
2474 INSN(aese, 0b0100111000101000010010);
2475 INSN(aesd, 0b0100111000101000010110);
2476 INSN(aesmc, 0b0100111000101000011010);
2477 INSN(aesimc, 0b0100111000101000011110);
2478
2479 #undef INSN
2480
2481 #define INSN(NAME, op1, op2) \
2482 void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn, FloatRegister Vm, int index = 0) { \
2483 starti; \
2484 assert(T == T2S || T == T4S || T == T2D, "invalid arrangement"); \
2485 assert(index >= 0 && ((T == T2D && index <= 1) || (T != T2D && index <= 3)), "invalid index"); \
2486 f(0, 31), f((int)T & 1, 30), f(op1, 29); f(0b011111, 28, 23); \
2487 f(T == T2D ? 1 : 0, 22), f(T == T2D ? 0 : index & 1, 21), rf(Vm, 16); \
2488 f(op2, 15, 12), f(T == T2D ? index : (index >> 1), 11), f(0, 10); \
2489 rf(Vn, 5), rf(Vd, 0); \
2490 }
2491
2492 // FMLA/FMLS - Vector - Scalar
2493 INSN(fmlavs, 0, 0b0001);
2494 INSN(fmlsvs, 0, 0b0101);
2495 // FMULX - Vector - Scalar
2496 INSN(fmulxvs, 1, 0b1001);
2497
2498 #undef INSN
2499
2500 // Floating-point Reciprocal Estimate
2501 void frecpe(FloatRegister Vd, FloatRegister Vn, SIMD_RegVariant type) {
2502 assert(type == D || type == S, "Wrong type for frecpe");
2503 starti;
2504 f(0b010111101, 31, 23);
2505 f(type == D ? 1 : 0, 22);
2506 f(0b100001110110, 21, 10);
2507 rf(Vn, 5), rf(Vd, 0);
2508 }
2509
2510 // (long) {a, b} -> (a + b)
2511 void addpd(FloatRegister Vd, FloatRegister Vn) {
2512 starti;
2513 f(0b0101111011110001101110, 31, 10);
2514 rf(Vn, 5), rf(Vd, 0);
2515 }
2516
2517 // (Floating-point) {a, b} -> (a + b)
2518 void faddp(FloatRegister Vd, FloatRegister Vn, SIMD_RegVariant type) {
2519 assert(type == D || type == S, "Wrong type for faddp");
2520 starti;
2521 f(0b011111100, 31, 23);
2522 f(type == D ? 1 : 0, 22);
2523 f(0b110000110110, 21, 10);
2524 rf(Vn, 5), rf(Vd, 0);
2525 }
2526
2527 void ins(FloatRegister Vd, SIMD_RegVariant T, FloatRegister Vn, int didx, int sidx) {
2528 starti;
2529 assert(T != Q, "invalid register variant");
2530 f(0b01101110000, 31, 21), f(((didx<<1)|1)<<(int)T, 20, 16), f(0, 15);
2531 f(sidx<<(int)T, 14, 11), f(1, 10), rf(Vn, 5), rf(Vd, 0);
2532 }
2533
2534 void umov(Register Rd, FloatRegister Vn, SIMD_RegVariant T, int idx) {
2535 starti;
2536 f(0, 31), f(T==D ? 1:0, 30), f(0b001110000, 29, 21);
2537 f(((idx<<1)|1)<<(int)T, 20, 16), f(0b001111, 15, 10);
2538 rf(Vn, 5), rf(Rd, 0);
2539 }
2540
2541 void smov(Register Rd, FloatRegister Vn, SIMD_RegVariant T, int idx) {
2542 starti;
2543 f(0, 31), f(T==D ? 1:0, 30), f(0b001110000, 29, 21);
2544 f(((idx<<1)|1)<<(int)T, 20, 16), f(0b001011, 15, 10);
2545 rf(Vn, 5), rf(Rd, 0);
2546 }
2547
2548
2549 #define INSN(NAME, opc, opc2, isSHR) \
2550 void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn, int shift){ \
2551 starti; \
2552 /* The encodings for the immh:immb fields (bits 22:16) in *SHR are \
2553 * 0001 xxx 8B/16B, shift = 16 - UInt(immh:immb) \
2554 * 001x xxx 4H/8H, shift = 32 - UInt(immh:immb) \
2555 * 01xx xxx 2S/4S, shift = 64 - UInt(immh:immb) \
2556 * 1xxx xxx 1D/2D, shift = 128 - UInt(immh:immb) \
2557 * (1D is RESERVED) \
2558 * for SHL shift is calculated as: \
2559 * 0001 xxx 8B/16B, shift = UInt(immh:immb) - 8 \
2560 * 001x xxx 4H/8H, shift = UInt(immh:immb) - 16 \
2561 * 01xx xxx 2S/4S, shift = UInt(immh:immb) - 32 \
2562 * 1xxx xxx 1D/2D, shift = UInt(immh:immb) - 64 \
2563 * (1D is RESERVED) \
2564 */ \
2565 assert((1 << ((T>>1)+3)) > shift, "Invalid Shift value"); \
2566 int cVal = (1 << (((T >> 1) + 3) + (isSHR ? 1 : 0))); \
2567 int encodedShift = isSHR ? cVal - shift : cVal + shift; \
2568 f(0, 31), f(T & 1, 30), f(opc, 29), f(0b011110, 28, 23), \
2569 f(encodedShift, 22, 16); f(opc2, 15, 10), rf(Vn, 5), rf(Vd, 0); \
2570 }
2571
2572 INSN(shl, 0, 0b010101, /* isSHR = */ false);
2573 INSN(sshr, 0, 0b000001, /* isSHR = */ true);
2574 INSN(ushr, 1, 0b000001, /* isSHR = */ true);
2575
2576 #undef INSN
2577
2578 private:
2579 void _xshll(sign_kind sign, FloatRegister Vd, SIMD_Arrangement Ta, FloatRegister Vn, SIMD_Arrangement Tb, int shift) {
2580 starti;
2581 /* The encodings for the immh:immb fields (bits 22:16) are
2582 * 0001 xxx 8H, 8B/16B shift = xxx
2583 * 001x xxx 4S, 4H/8H shift = xxxx
2584 * 01xx xxx 2D, 2S/4S shift = xxxxx
2585 * 1xxx xxx RESERVED
2586 */
2587 assert((Tb >> 1) + 1 == (Ta >> 1), "Incompatible arrangement");
2588 assert((1 << ((Tb>>1)+3)) > shift, "Invalid shift value");
2589 f(0, 31), f(Tb & 1, 30), f(sign == SIGNED ? 0 : 1, 29), f(0b011110, 28, 23);
2590 f((1 << ((Tb>>1)+3))|shift, 22, 16);
2591 f(0b101001, 15, 10), rf(Vn, 5), rf(Vd, 0);
2592 }
2593
2594 public:
2595 void ushll(FloatRegister Vd, SIMD_Arrangement Ta, FloatRegister Vn, SIMD_Arrangement Tb, int shift) {
2596 assert(Tb == T8B || Tb == T4H || Tb == T2S, "invalid arrangement");
2597 _xshll(UNSIGNED, Vd, Ta, Vn, Tb, shift);
2598 }
2599
2600 void ushll2(FloatRegister Vd, SIMD_Arrangement Ta, FloatRegister Vn, SIMD_Arrangement Tb, int shift) {
2601 assert(Tb == T16B || Tb == T8H || Tb == T4S, "invalid arrangement");
2602 _xshll(UNSIGNED, Vd, Ta, Vn, Tb, shift);
2603 }
2604
2605 void uxtl(FloatRegister Vd, SIMD_Arrangement Ta, FloatRegister Vn, SIMD_Arrangement Tb) {
2606 ushll(Vd, Ta, Vn, Tb, 0);
2607 }
2608
2609 void sshll(FloatRegister Vd, SIMD_Arrangement Ta, FloatRegister Vn, SIMD_Arrangement Tb, int shift) {
2610 assert(Tb == T8B || Tb == T4H || Tb == T2S, "invalid arrangement");
2611 _xshll(SIGNED, Vd, Ta, Vn, Tb, shift);
2612 }
2613
2614 void sshll2(FloatRegister Vd, SIMD_Arrangement Ta, FloatRegister Vn, SIMD_Arrangement Tb, int shift) {
2615 assert(Tb == T16B || Tb == T8H || Tb == T4S, "invalid arrangement");
2616 _xshll(SIGNED, Vd, Ta, Vn, Tb, shift);
2617 }
2618
2619 void sxtl(FloatRegister Vd, SIMD_Arrangement Ta, FloatRegister Vn, SIMD_Arrangement Tb) {
2620 sshll(Vd, Ta, Vn, Tb, 0);
2621 }
2622
2623 // Move from general purpose register
2624 // mov Vd.T[index], Rn
2625 void mov(FloatRegister Vd, SIMD_Arrangement T, int index, Register Xn) {
2626 starti;
2627 f(0b01001110000, 31, 21), f(((1 << (T >> 1)) | (index << ((T >> 1) + 1))), 20, 16);
2628 f(0b000111, 15, 10), zrf(Xn, 5), rf(Vd, 0);
2629 }
2630
2631 // Move to general purpose register
2632 // mov Rd, Vn.T[index]
2633 void mov(Register Xd, FloatRegister Vn, SIMD_Arrangement T, int index) {
2634 guarantee(T >= T2S && T < T1Q, "only D and S arrangements are supported");
2635 starti;
2636 f(0, 31), f((T >= T1D) ? 1:0, 30), f(0b001110000, 29, 21);
2637 f(((1 << (T >> 1)) | (index << ((T >> 1) + 1))), 20, 16);
2638 f(0b001111, 15, 10), rf(Vn, 5), rf(Xd, 0);
2639 }
2640
2641 private:
2642 void _pmull(FloatRegister Vd, SIMD_Arrangement Ta, FloatRegister Vn, FloatRegister Vm, SIMD_Arrangement Tb) {
2643 starti;
2644 assert((Ta == T1Q && (Tb == T1D || Tb == T2D)) ||
2645 (Ta == T8H && (Tb == T8B || Tb == T16B)), "Invalid Size specifier");
2646 int size = (Ta == T1Q) ? 0b11 : 0b00;
2647 f(0, 31), f(Tb & 1, 30), f(0b001110, 29, 24), f(size, 23, 22);
2648 f(1, 21), rf(Vm, 16), f(0b111000, 15, 10), rf(Vn, 5), rf(Vd, 0);
2649 }
2650
2651 public:
2652 void pmull(FloatRegister Vd, SIMD_Arrangement Ta, FloatRegister Vn, FloatRegister Vm, SIMD_Arrangement Tb) {
2653 assert(Tb == T1D || Tb == T8B, "pmull assumes T1D or T8B as the second size specifier");
2654 _pmull(Vd, Ta, Vn, Vm, Tb);
2655 }
2656
2657 void pmull2(FloatRegister Vd, SIMD_Arrangement Ta, FloatRegister Vn, FloatRegister Vm, SIMD_Arrangement Tb) {
2658 assert(Tb == T2D || Tb == T16B, "pmull2 assumes T2D or T16B as the second size specifier");
2659 _pmull(Vd, Ta, Vn, Vm, Tb);
2660 }
2661
2662 void uqxtn(FloatRegister Vd, SIMD_Arrangement Tb, FloatRegister Vn, SIMD_Arrangement Ta) {
2663 starti;
2664 int size_b = (int)Tb >> 1;
2665 int size_a = (int)Ta >> 1;
2666 assert(size_b < 3 && size_b == size_a - 1, "Invalid size specifier");
2667 f(0, 31), f(Tb & 1, 30), f(0b101110, 29, 24), f(size_b, 23, 22);
2668 f(0b100001010010, 21, 10), rf(Vn, 5), rf(Vd, 0);
2669 }
2670
2671 void xtn(FloatRegister Vd, SIMD_Arrangement Tb, FloatRegister Vn, SIMD_Arrangement Ta) {
2672 starti;
2673 int size_b = (int)Tb >> 1;
2674 int size_a = (int)Ta >> 1;
2675 assert(size_b < 3 && size_b == size_a - 1, "Invalid size specifier");
2676 f(0, 31), f(Tb & 1, 30), f(0b001110, 29, 24), f(size_b, 23, 22);
2677 f(0b100001001010, 21, 10), rf(Vn, 5), rf(Vd, 0);
2678 }
2679
2680 void dup(FloatRegister Vd, SIMD_Arrangement T, Register Xs)
2681 {
2682 starti;
2683 assert(T != T1D, "reserved encoding");
2684 f(0,31), f((int)T & 1, 30), f(0b001110000, 29, 21);
2685 f((1 << (T >> 1)), 20, 16), f(0b000011, 15, 10), zrf(Xs, 5), rf(Vd, 0);
2686 }
2687
2688 void dup(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn, int index = 0)
2689 {
2690 starti;
2691 assert(T != T1D, "reserved encoding");
2692 f(0, 31), f((int)T & 1, 30), f(0b001110000, 29, 21);
2693 f(((1 << (T >> 1)) | (index << ((T >> 1) + 1))), 20, 16);
2694 f(0b000001, 15, 10), rf(Vn, 5), rf(Vd, 0);
2695 }
2696
2697 // AdvSIMD ZIP/UZP/TRN
2698 #define INSN(NAME, opcode) \
2699 void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn, FloatRegister Vm) { \
2700 guarantee(T != T1D && T != T1Q, "invalid arrangement"); \
2701 starti; \
2702 f(0, 31), f(0b001110, 29, 24), f(0, 21), f(0, 15); \
2703 f(opcode, 14, 12), f(0b10, 11, 10); \
2704 rf(Vm, 16), rf(Vn, 5), rf(Vd, 0); \
2705 f(T & 1, 30), f(T >> 1, 23, 22); \
2706 }
2707
2708 INSN(uzp1, 0b001);
2709 INSN(trn1, 0b010);
2710 INSN(zip1, 0b011);
2711 INSN(uzp2, 0b101);
2712 INSN(trn2, 0b110);
2713 INSN(zip2, 0b111);
2714
2715 #undef INSN
2716
2717 // CRC32 instructions
2718 #define INSN(NAME, c, sf, sz) \
2719 void NAME(Register Rd, Register Rn, Register Rm) { \
2720 starti; \
2721 f(sf, 31), f(0b0011010110, 30, 21), f(0b010, 15, 13), f(c, 12); \
2722 f(sz, 11, 10), rf(Rm, 16), rf(Rn, 5), rf(Rd, 0); \
2723 }
2724
2725 INSN(crc32b, 0, 0, 0b00);
2726 INSN(crc32h, 0, 0, 0b01);
2727 INSN(crc32w, 0, 0, 0b10);
2728 INSN(crc32x, 0, 1, 0b11);
2729 INSN(crc32cb, 1, 0, 0b00);
2730 INSN(crc32ch, 1, 0, 0b01);
2731 INSN(crc32cw, 1, 0, 0b10);
2732 INSN(crc32cx, 1, 1, 0b11);
2733
2734 #undef INSN
2735
2736 // Table vector lookup
2737 #define INSN(NAME, op) \
2738 void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn, unsigned registers, FloatRegister Vm) { \
2739 starti; \
2740 assert(T == T8B || T == T16B, "invalid arrangement"); \
2741 assert(0 < registers && registers <= 4, "invalid number of registers"); \
2742 f(0, 31), f((int)T & 1, 30), f(0b001110000, 29, 21), rf(Vm, 16), f(0, 15); \
2743 f(registers - 1, 14, 13), f(op, 12),f(0b00, 11, 10), rf(Vn, 5), rf(Vd, 0); \
2744 }
2745
2746 INSN(tbl, 0);
2747 INSN(tbx, 1);
2748
2749 #undef INSN
2750
2751 // AdvSIMD two-reg misc
2752 // In this instruction group, the 2 bits in the size field ([23:22]) may be
2753 // fixed or determined by the "SIMD_Arrangement T", or both. The additional
2754 // parameter "tmask" is a 2-bit mask used to indicate which bits in the size
2755 // field are determined by the SIMD_Arrangement. The bit of "tmask" should be
2756 // set to 1 if corresponding bit marked as "x" in the ArmARM.
2757 #define INSN(NAME, U, size, tmask, opcode) \
2758 void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn) { \
2759 starti; \
2760 assert((ASSERTION), MSG); \
2761 f(0, 31), f((int)T & 1, 30), f(U, 29), f(0b01110, 28, 24); \
2762 f(size | ((int)(T >> 1) & tmask), 23, 22), f(0b10000, 21, 17); \
2763 f(opcode, 16, 12), f(0b10, 11, 10), rf(Vn, 5), rf(Vd, 0); \
2764 }
2765
2766 #define MSG "invalid arrangement"
2767
2768 #define ASSERTION (T == T2S || T == T4S || T == T2D)
2769 INSN(fsqrt, 1, 0b10, 0b01, 0b11111);
2770 INSN(fabs, 0, 0b10, 0b01, 0b01111);
2771 INSN(fneg, 1, 0b10, 0b01, 0b01111);
2772 INSN(frintn, 0, 0b00, 0b01, 0b11000);
2773 INSN(frintm, 0, 0b00, 0b01, 0b11001);
2774 INSN(frintp, 0, 0b10, 0b01, 0b11000);
2775 #undef ASSERTION
2776
2777 #define ASSERTION (T == T8B || T == T16B || T == T4H || T == T8H || T == T2S || T == T4S)
2778 INSN(rev64, 0, 0b00, 0b11, 0b00000);
2779 #undef ASSERTION
2780
2781 #define ASSERTION (T == T8B || T == T16B || T == T4H || T == T8H)
2782 INSN(rev32, 1, 0b00, 0b11, 0b00000);
2783 #undef ASSERTION
2784
2785 #define ASSERTION (T == T8B || T == T16B)
2786 INSN(rev16, 0, 0b00, 0b11, 0b00001);
2787 INSN(rbit, 1, 0b01, 0b00, 0b00101);
2788 #undef ASSERTION
2789
2790 #undef MSG
2791
2792 #undef INSN
2793
2794 void ext(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn, FloatRegister Vm, int index)
2795 {
2796 starti;
2797 assert(T == T8B || T == T16B, "invalid arrangement");
2798 assert((T == T8B && index <= 0b0111) || (T == T16B && index <= 0b1111), "Invalid index value");
2799 f(0, 31), f((int)T & 1, 30), f(0b101110000, 29, 21);
2800 rf(Vm, 16), f(0, 15), f(index, 14, 11);
2801 f(0, 10), rf(Vn, 5), rf(Vd, 0);
2802 }
2803
2804 Assembler(CodeBuffer* code) : AbstractAssembler(code) {
2805 }
2806
2807 virtual RegisterOrConstant delayed_value_impl(intptr_t* delayed_value_addr,
2808 Register tmp,
2809 int offset) {
2810 ShouldNotCallThis();
2811 return RegisterOrConstant();
2812 }
2813
2814 // Stack overflow checking
2815 virtual void bang_stack_with_offset(int offset);
2816
2817 static bool operand_valid_for_logical_immediate(bool is32, uint64_t imm);
2818 static bool operand_valid_for_add_sub_immediate(long imm);
2819 static bool operand_valid_for_float_immediate(double imm);
2820
2821 void emit_data64(jlong data, relocInfo::relocType rtype, int format = 0);
2822 void emit_data64(jlong data, RelocationHolder const& rspec, int format = 0);
2823 };
2824
2825 inline Assembler::Membar_mask_bits operator|(Assembler::Membar_mask_bits a,
2826 Assembler::Membar_mask_bits b) {
2827 return Assembler::Membar_mask_bits(unsigned(a)|unsigned(b));
2828 }
2829
2830 Instruction_aarch64::~Instruction_aarch64() {
2831 assem->emit();
2832 }
2833
2834 #undef starti
2835
2836 // Invert a condition
2837 inline const Assembler::Condition operator~(const Assembler::Condition cond) {
2838 return Assembler::Condition(int(cond) ^ 1);
2839 }
2840
2841 class BiasedLockingCounters;
2842
2843 extern "C" void das(uint64_t start, int len);
2844
2845 #endif // CPU_AARCH64_ASSEMBLER_AARCH64_HPP