1 /*
2 * Copyright (c) 1997, 2020, Oracle and/or its affiliates. All rights reserved.
3 * Copyright (c) 2014, 2020 Red Hat Inc. All rights reserved.
4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
5 *
6 * This code is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 only, as
8 * published by the Free Software Foundation.
9 *
10 * This code is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * version 2 for more details (a copy is included in the LICENSE file that
14 * accompanied this code).
15 *
16 * You should have received a copy of the GNU General Public License version
17 * 2 along with this work; if not, write to the Free Software Foundation,
18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 * or visit www.oracle.com if you need additional information or have any
22 * questions.
23 */
24
25 #include <stdio.h>
26 #include <sys/types.h>
27
28 #include "precompiled.hpp"
29 #include "asm/assembler.hpp"
30 #include "asm/assembler.inline.hpp"
31 #include "interpreter/interpreter.hpp"
32
33 #ifndef PRODUCT
34 const unsigned long Assembler::asm_bp = 0x00007fffee09ac88;
35 #endif
36
37 #include "compiler/disassembler.hpp"
38 #include "memory/resourceArea.hpp"
39 #include "runtime/interfaceSupport.inline.hpp"
40 #include "runtime/sharedRuntime.hpp"
41 #include "immediate_aarch64.hpp"
42
43 extern "C" void entry(CodeBuffer *cb);
44
45 #define __ _masm.
46 #ifdef PRODUCT
47 #define BLOCK_COMMENT(str) /* nothing */
48 #else
49 #define BLOCK_COMMENT(str) block_comment(str)
50 #endif
51
52 #define BIND(label) bind(label); __ BLOCK_COMMENT(#label ":")
53
54 static float unpack(unsigned value);
55
56 short Assembler::SIMD_Size_in_bytes[] = {
57 // T8B, T16B, T4H, T8H, T2S, T4S, T1D, T2D, T1Q
58 8, 16, 8, 16, 8, 16, 8, 16, 16
59 };
60
61 #ifdef ASSERT
62 static void asm_check(const unsigned int *insns, const unsigned int *insns1, size_t len) {
63 bool ok = true;
64 for (unsigned int i = 0; i < len; i++) {
65 if (insns[i] != insns1[i]) {
66 ok = false;
67 printf("Ours:\n");
68 Disassembler::decode((address)&insns1[i], (address)&insns1[i+1]);
69 printf("Theirs:\n");
70 Disassembler::decode((address)&insns[i], (address)&insns[i+1]);
71 printf("\n");
72 }
73 }
74 assert(ok, "Assembler smoke test failed");
75 }
76
77 void entry(CodeBuffer *cb) {
78
79 // {
80 // for (int i = 0; i < 256; i+=16)
81 // {
82 // printf("\"%20.20g\", ", unpack(i));
83 // printf("\"%20.20g\", ", unpack(i+1));
84 // }
85 // printf("\n");
86 // }
87
88 Assembler _masm(cb);
89 address entry = __ pc();
90
91 // Smoke test for assembler
92
93 // BEGIN Generated code -- do not edit
94 // Generated by aarch64-asmtest.py
95 Label back, forth;
96 __ bind(back);
97
98 // ArithOp
99 __ add(r26, r23, r13, Assembler::LSL, 32); // add x26, x23, x13, LSL #32
100 __ sub(r12, r24, r9, Assembler::LSR, 37); // sub x12, x24, x9, LSR #37
101 __ adds(r28, r15, r8, Assembler::ASR, 39); // adds x28, x15, x8, ASR #39
102 __ subs(r7, r28, r30, Assembler::ASR, 57); // subs x7, x28, x30, ASR #57
103 __ addw(r9, r22, r27, Assembler::ASR, 15); // add w9, w22, w27, ASR #15
104 __ subw(r3, r13, r18, Assembler::ASR, 30); // sub w3, w13, w18, ASR #30
105 __ addsw(r14, r26, r8, Assembler::ASR, 17); // adds w14, w26, w8, ASR #17
106 __ subsw(r0, r22, r12, Assembler::ASR, 21); // subs w0, w22, w12, ASR #21
107 __ andr(r0, r15, r26, Assembler::LSL, 20); // and x0, x15, x26, LSL #20
108 __ orr(r26, r5, r17, Assembler::LSL, 61); // orr x26, x5, x17, LSL #61
109 __ eor(r24, r13, r2, Assembler::LSL, 32); // eor x24, x13, x2, LSL #32
110 __ ands(r28, r3, r17, Assembler::ASR, 35); // ands x28, x3, x17, ASR #35
111 __ andw(r25, r16, r29, Assembler::LSR, 18); // and w25, w16, w29, LSR #18
112 __ orrw(r13, r18, r11, Assembler::LSR, 9); // orr w13, w18, w11, LSR #9
113 __ eorw(r5, r5, r18, Assembler::LSR, 15); // eor w5, w5, w18, LSR #15
114 __ andsw(r2, r23, r27, Assembler::ASR, 26); // ands w2, w23, w27, ASR #26
115 __ bic(r27, r28, r16, Assembler::LSR, 45); // bic x27, x28, x16, LSR #45
116 __ orn(r8, r25, r26, Assembler::ASR, 37); // orn x8, x25, x26, ASR #37
117 __ eon(r29, r17, r13, Assembler::LSR, 63); // eon x29, x17, x13, LSR #63
118 __ bics(r28, r24, r2, Assembler::LSR, 31); // bics x28, x24, x2, LSR #31
119 __ bicw(r19, r26, r7, Assembler::ASR, 3); // bic w19, w26, w7, ASR #3
120 __ ornw(r6, r24, r10, Assembler::ASR, 3); // orn w6, w24, w10, ASR #3
121 __ eonw(r4, r21, r1, Assembler::LSR, 29); // eon w4, w21, w1, LSR #29
122 __ bicsw(r16, r21, r0, Assembler::LSR, 19); // bics w16, w21, w0, LSR #19
123
124 // AddSubImmOp
125 __ addw(r17, r12, 379u); // add w17, w12, #379
126 __ addsw(r30, r1, 22u); // adds w30, w1, #22
127 __ subw(r29, r5, 126u); // sub w29, w5, #126
128 __ subsw(r6, r24, 960u); // subs w6, w24, #960
129 __ add(r0, r13, 104u); // add x0, x13, #104
130 __ adds(r8, r6, 663u); // adds x8, x6, #663
131 __ sub(r10, r5, 516u); // sub x10, x5, #516
132 __ subs(r1, r3, 1012u); // subs x1, x3, #1012
133
134 // LogicalImmOp
135 __ andw(r6, r11, 4294049777ul); // and w6, w11, #0xfff1fff1
136 __ orrw(r28, r5, 4294966791ul); // orr w28, w5, #0xfffffe07
137 __ eorw(r1, r20, 134217216ul); // eor w1, w20, #0x7fffe00
138 __ andsw(r7, r18, 1048576ul); // ands w7, w18, #0x100000
139 __ andr(r14, r12, 9223372036854775808ul); // and x14, x12, #0x8000000000000000
140 __ orr(r9, r11, 562675075514368ul); // orr x9, x11, #0x1ffc000000000
141 __ eor(r17, r0, 18014398509481728ul); // eor x17, x0, #0x3fffffffffff00
142 __ ands(r1, r8, 18446744073705357315ul); // ands x1, x8, #0xffffffffffc00003
143
144 // AbsOp
145 __ b(__ pc()); // b .
146 __ b(back); // b back
147 __ b(forth); // b forth
148 __ bl(__ pc()); // bl .
149 __ bl(back); // bl back
150 __ bl(forth); // bl forth
151
152 // RegAndAbsOp
153 __ cbzw(r10, __ pc()); // cbz w10, .
154 __ cbzw(r10, back); // cbz w10, back
155 __ cbzw(r10, forth); // cbz w10, forth
156 __ cbnzw(r8, __ pc()); // cbnz w8, .
157 __ cbnzw(r8, back); // cbnz w8, back
158 __ cbnzw(r8, forth); // cbnz w8, forth
159 __ cbz(r11, __ pc()); // cbz x11, .
160 __ cbz(r11, back); // cbz x11, back
161 __ cbz(r11, forth); // cbz x11, forth
162 __ cbnz(r29, __ pc()); // cbnz x29, .
163 __ cbnz(r29, back); // cbnz x29, back
164 __ cbnz(r29, forth); // cbnz x29, forth
165 __ adr(r19, __ pc()); // adr x19, .
166 __ adr(r19, back); // adr x19, back
167 __ adr(r19, forth); // adr x19, forth
168 __ _adrp(r19, __ pc()); // adrp x19, .
169
170 // RegImmAbsOp
171 __ tbz(r22, 6, __ pc()); // tbz x22, #6, .
172 __ tbz(r22, 6, back); // tbz x22, #6, back
173 __ tbz(r22, 6, forth); // tbz x22, #6, forth
174 __ tbnz(r12, 11, __ pc()); // tbnz x12, #11, .
175 __ tbnz(r12, 11, back); // tbnz x12, #11, back
176 __ tbnz(r12, 11, forth); // tbnz x12, #11, forth
177
178 // MoveWideImmOp
179 __ movnw(r0, 6301, 0); // movn w0, #6301, lsl 0
180 __ movzw(r7, 20886, 0); // movz w7, #20886, lsl 0
181 __ movkw(r27, 18617, 0); // movk w27, #18617, lsl 0
182 __ movn(r12, 22998, 16); // movn x12, #22998, lsl 16
183 __ movz(r20, 1532, 16); // movz x20, #1532, lsl 16
184 __ movk(r8, 5167, 32); // movk x8, #5167, lsl 32
185
186 // BitfieldOp
187 __ sbfm(r15, r17, 24, 28); // sbfm x15, x17, #24, #28
188 __ bfmw(r15, r9, 14, 25); // bfm w15, w9, #14, #25
189 __ ubfmw(r27, r25, 6, 31); // ubfm w27, w25, #6, #31
190 __ sbfm(r19, r2, 23, 31); // sbfm x19, x2, #23, #31
191 __ bfm(r12, r21, 10, 6); // bfm x12, x21, #10, #6
192 __ ubfm(r22, r0, 26, 16); // ubfm x22, x0, #26, #16
193
194 // ExtractOp
195 __ extrw(r3, r3, r20, 27); // extr w3, w3, w20, #27
196 __ extr(r8, r30, r3, 54); // extr x8, x30, x3, #54
197
198 // CondBranchOp
199 __ br(Assembler::EQ, __ pc()); // b.EQ .
200 __ br(Assembler::EQ, back); // b.EQ back
201 __ br(Assembler::EQ, forth); // b.EQ forth
202 __ br(Assembler::NE, __ pc()); // b.NE .
203 __ br(Assembler::NE, back); // b.NE back
204 __ br(Assembler::NE, forth); // b.NE forth
205 __ br(Assembler::HS, __ pc()); // b.HS .
206 __ br(Assembler::HS, back); // b.HS back
207 __ br(Assembler::HS, forth); // b.HS forth
208 __ br(Assembler::CS, __ pc()); // b.CS .
209 __ br(Assembler::CS, back); // b.CS back
210 __ br(Assembler::CS, forth); // b.CS forth
211 __ br(Assembler::LO, __ pc()); // b.LO .
212 __ br(Assembler::LO, back); // b.LO back
213 __ br(Assembler::LO, forth); // b.LO forth
214 __ br(Assembler::CC, __ pc()); // b.CC .
215 __ br(Assembler::CC, back); // b.CC back
216 __ br(Assembler::CC, forth); // b.CC forth
217 __ br(Assembler::MI, __ pc()); // b.MI .
218 __ br(Assembler::MI, back); // b.MI back
219 __ br(Assembler::MI, forth); // b.MI forth
220 __ br(Assembler::PL, __ pc()); // b.PL .
221 __ br(Assembler::PL, back); // b.PL back
222 __ br(Assembler::PL, forth); // b.PL forth
223 __ br(Assembler::VS, __ pc()); // b.VS .
224 __ br(Assembler::VS, back); // b.VS back
225 __ br(Assembler::VS, forth); // b.VS forth
226 __ br(Assembler::VC, __ pc()); // b.VC .
227 __ br(Assembler::VC, back); // b.VC back
228 __ br(Assembler::VC, forth); // b.VC forth
229 __ br(Assembler::HI, __ pc()); // b.HI .
230 __ br(Assembler::HI, back); // b.HI back
231 __ br(Assembler::HI, forth); // b.HI forth
232 __ br(Assembler::LS, __ pc()); // b.LS .
233 __ br(Assembler::LS, back); // b.LS back
234 __ br(Assembler::LS, forth); // b.LS forth
235 __ br(Assembler::GE, __ pc()); // b.GE .
236 __ br(Assembler::GE, back); // b.GE back
237 __ br(Assembler::GE, forth); // b.GE forth
238 __ br(Assembler::LT, __ pc()); // b.LT .
239 __ br(Assembler::LT, back); // b.LT back
240 __ br(Assembler::LT, forth); // b.LT forth
241 __ br(Assembler::GT, __ pc()); // b.GT .
242 __ br(Assembler::GT, back); // b.GT back
243 __ br(Assembler::GT, forth); // b.GT forth
244 __ br(Assembler::LE, __ pc()); // b.LE .
245 __ br(Assembler::LE, back); // b.LE back
246 __ br(Assembler::LE, forth); // b.LE forth
247 __ br(Assembler::AL, __ pc()); // b.AL .
248 __ br(Assembler::AL, back); // b.AL back
249 __ br(Assembler::AL, forth); // b.AL forth
250 __ br(Assembler::NV, __ pc()); // b.NV .
251 __ br(Assembler::NV, back); // b.NV back
252 __ br(Assembler::NV, forth); // b.NV forth
253
254 // ImmOp
255 __ svc(12999); // svc #12999
256 __ hvc(2665); // hvc #2665
257 __ smc(9002); // smc #9002
258 __ brk(14843); // brk #14843
259 __ hlt(25964); // hlt #25964
260
261 // Op
262 __ nop(); // nop
263 __ eret(); // eret
264 __ drps(); // drps
265 __ isb(); // isb
266
267 // SystemOp
268 __ dsb(Assembler::ST); // dsb ST
269 __ dmb(Assembler::OSHST); // dmb OSHST
270
271 // OneRegOp
272 __ br(r16); // br x16
273 __ blr(r20); // blr x20
274
275 // LoadStoreExclusiveOp
276 __ stxr(r10, r27, r8); // stxr w10, x27, [x8]
277 __ stlxr(r0, r1, r21); // stlxr w0, x1, [x21]
278 __ ldxr(r17, r29); // ldxr x17, [x29]
279 __ ldaxr(r29, r28); // ldaxr x29, [x28]
280 __ stlr(r1, r23); // stlr x1, [x23]
281 __ ldar(r21, r20); // ldar x21, [x20]
282
283 // LoadStoreExclusiveOp
284 __ stxrw(r22, r27, r19); // stxr w22, w27, [x19]
285 __ stlxrw(r11, r16, r6); // stlxr w11, w16, [x6]
286 __ ldxrw(r18, r0); // ldxr w18, [x0]
287 __ ldaxrw(r4, r10); // ldaxr w4, [x10]
288 __ stlrw(r24, r22); // stlr w24, [x22]
289 __ ldarw(r10, r19); // ldar w10, [x19]
290
291 // LoadStoreExclusiveOp
292 __ stxrh(r1, r5, r30); // stxrh w1, w5, [x30]
293 __ stlxrh(r8, r12, r17); // stlxrh w8, w12, [x17]
294 __ ldxrh(r9, r14); // ldxrh w9, [x14]
295 __ ldaxrh(r7, r1); // ldaxrh w7, [x1]
296 __ stlrh(r5, r16); // stlrh w5, [x16]
297 __ ldarh(r2, r12); // ldarh w2, [x12]
298
299 // LoadStoreExclusiveOp
300 __ stxrb(r10, r12, r3); // stxrb w10, w12, [x3]
301 __ stlxrb(r28, r14, r26); // stlxrb w28, w14, [x26]
302 __ ldxrb(r30, r10); // ldxrb w30, [x10]
303 __ ldaxrb(r14, r21); // ldaxrb w14, [x21]
304 __ stlrb(r13, r9); // stlrb w13, [x9]
305 __ ldarb(r22, r27); // ldarb w22, [x27]
306
307 // LoadStoreExclusiveOp
308 __ ldxp(r28, r19, r11); // ldxp x28, x19, [x11]
309 __ ldaxp(r30, r19, r2); // ldaxp x30, x19, [x2]
310 __ stxp(r2, r23, r1, r0); // stxp w2, x23, x1, [x0]
311 __ stlxp(r12, r16, r13, r15); // stlxp w12, x16, x13, [x15]
312
313 // LoadStoreExclusiveOp
314 __ ldxpw(r18, r21, r13); // ldxp w18, w21, [x13]
315 __ ldaxpw(r11, r30, r8); // ldaxp w11, w30, [x8]
316 __ stxpw(r24, r13, r11, r1); // stxp w24, w13, w11, [x1]
317 __ stlxpw(r26, r21, r27, r13); // stlxp w26, w21, w27, [x13]
318
319 // base_plus_unscaled_offset
320 // LoadStoreOp
321 __ str(r11, Address(r20, -103)); // str x11, [x20, -103]
322 __ strw(r28, Address(r16, 62)); // str w28, [x16, 62]
323 __ strb(r27, Address(r9, -9)); // strb w27, [x9, -9]
324 __ strh(r2, Address(r25, -50)); // strh w2, [x25, -50]
325 __ ldr(r4, Address(r2, -241)); // ldr x4, [x2, -241]
326 __ ldrw(r30, Address(r20, -31)); // ldr w30, [x20, -31]
327 __ ldrb(r18, Address(r23, -23)); // ldrb w18, [x23, -23]
328 __ ldrh(r29, Address(r26, -1)); // ldrh w29, [x26, -1]
329 __ ldrsb(r1, Address(r9, 6)); // ldrsb x1, [x9, 6]
330 __ ldrsh(r11, Address(r12, 19)); // ldrsh x11, [x12, 19]
331 __ ldrshw(r11, Address(r1, -50)); // ldrsh w11, [x1, -50]
332 __ ldrsw(r19, Address(r24, 41)); // ldrsw x19, [x24, 41]
333 __ ldrd(v24, Address(r24, 95)); // ldr d24, [x24, 95]
334 __ ldrs(v15, Address(r5, -43)); // ldr s15, [x5, -43]
335 __ strd(v21, Address(r27, 1)); // str d21, [x27, 1]
336 __ strs(v23, Address(r13, -107)); // str s23, [x13, -107]
337
338 // pre
339 // LoadStoreOp
340 __ str(r2, Address(__ pre(r22, 8))); // str x2, [x22, 8]!
341 __ strw(r6, Address(__ pre(r11, -127))); // str w6, [x11, -127]!
342 __ strb(r3, Address(__ pre(r20, -32))); // strb w3, [x20, -32]!
343 __ strh(r19, Address(__ pre(r10, 29))); // strh w19, [x10, 29]!
344 __ ldr(r7, Address(__ pre(r5, -33))); // ldr x7, [x5, -33]!
345 __ ldrw(r17, Address(__ pre(r23, -120))); // ldr w17, [x23, -120]!
346 __ ldrb(r12, Address(__ pre(r22, -2))); // ldrb w12, [x22, -2]!
347 __ ldrh(r17, Address(__ pre(r12, -45))); // ldrh w17, [x12, -45]!
348 __ ldrsb(r4, Address(__ pre(r21, -13))); // ldrsb x4, [x21, -13]!
349 __ ldrsh(r23, Address(__ pre(r14, -45))); // ldrsh x23, [x14, -45]!
350 __ ldrshw(r8, Address(__ pre(r19, 3))); // ldrsh w8, [x19, 3]!
351 __ ldrsw(r7, Address(__ pre(r30, -121))); // ldrsw x7, [x30, -121]!
352 __ ldrd(v7, Address(__ pre(r8, -27))); // ldr d7, [x8, -27]!
353 __ ldrs(v19, Address(__ pre(r28, -73))); // ldr s19, [x28, -73]!
354 __ strd(v18, Address(__ pre(r12, -144))); // str d18, [x12, -144]!
355 __ strs(v1, Address(__ pre(r4, -38))); // str s1, [x4, -38]!
356
357 // post
358 // LoadStoreOp
359 __ str(r2, Address(__ post(r9, -247))); // str x2, [x9], -247
360 __ strw(r21, Address(__ post(r26, -127))); // str w21, [x26], -127
361 __ strb(r27, Address(__ post(r22, -27))); // strb w27, [x22], -27
362 __ strh(r25, Address(__ post(r13, -52))); // strh w25, [x13], -52
363 __ ldr(r5, Address(__ post(r12, -31))); // ldr x5, [x12], -31
364 __ ldrw(r10, Address(__ post(r1, -11))); // ldr w10, [x1], -11
365 __ ldrb(r21, Address(__ post(r14, 13))); // ldrb w21, [x14], 13
366 __ ldrh(r30, Address(__ post(r6, -64))); // ldrh w30, [x6], -64
367 __ ldrsb(r10, Address(__ post(r12, -28))); // ldrsb x10, [x12], -28
368 __ ldrsh(r9, Address(__ post(r0, -14))); // ldrsh x9, [x0], -14
369 __ ldrshw(r1, Address(__ post(r26, -60))); // ldrsh w1, [x26], -60
370 __ ldrsw(r13, Address(__ post(r25, -113))); // ldrsw x13, [x25], -113
371 __ ldrd(v28, Address(__ post(r2, -241))); // ldr d28, [x2], -241
372 __ ldrs(v16, Address(__ post(r9, -24))); // ldr s16, [x9], -24
373 __ strd(v20, Address(__ post(r8, -218))); // str d20, [x8], -218
374 __ strs(v21, Address(__ post(r22, -4))); // str s21, [x22], -4
375
376 // base_plus_reg
377 // LoadStoreOp
378 __ str(r5, Address(r20, r6, Address::sxtw(0))); // str x5, [x20, w6, sxtw #0]
379 __ strw(r2, Address(r25, r17, Address::sxtx(2))); // str w2, [x25, x17, sxtx #2]
380 __ strb(r10, Address(r23, r24, Address::sxtx(0))); // strb w10, [x23, x24, sxtx #0]
381 __ strh(r6, Address(r18, r19, Address::lsl(0))); // strh w6, [x18, x19, lsl #0]
382 __ ldr(r21, Address(r20, r20, Address::lsl(3))); // ldr x21, [x20, x20, lsl #3]
383 __ ldrw(r22, Address(r25, r24, Address::lsl(0))); // ldr w22, [x25, x24, lsl #0]
384 __ ldrb(r19, Address(r20, r8, Address::uxtw(0))); // ldrb w19, [x20, w8, uxtw #0]
385 __ ldrh(r6, Address(r0, r1, Address::lsl(1))); // ldrh w6, [x0, x1, lsl #1]
386 __ ldrsb(r16, Address(r13, r11, Address::lsl(0))); // ldrsb x16, [x13, x11, lsl #0]
387 __ ldrsh(r26, Address(r22, r21, Address::uxtw(0))); // ldrsh x26, [x22, w21, uxtw #0]
388 __ ldrshw(r5, Address(r15, r22, Address::uxtw(1))); // ldrsh w5, [x15, w22, uxtw #1]
389 __ ldrsw(r18, Address(r24, r21, Address::lsl(0))); // ldrsw x18, [x24, x21, lsl #0]
390 __ ldrd(v7, Address(r7, r24, Address::lsl(0))); // ldr d7, [x7, x24, lsl #0]
391 __ ldrs(v30, Address(r11, r22, Address::sxtx(2))); // ldr s30, [x11, x22, sxtx #2]
392 __ strd(v22, Address(r23, r17, Address::lsl(0))); // str d22, [x23, x17, lsl #0]
393 __ strs(v30, Address(r1, r21, Address::sxtw(0))); // str s30, [x1, w21, sxtw #0]
394
395 // base_plus_scaled_offset
396 // LoadStoreOp
397 __ str(r10, Address(r30, 12992)); // str x10, [x30, 12992]
398 __ strw(r19, Address(r28, 6408)); // str w19, [x28, 6408]
399 __ strb(r29, Address(r10, 1580)); // strb w29, [x10, 1580]
400 __ strh(r5, Address(r14, 3172)); // strh w5, [x14, 3172]
401 __ ldr(r8, Address(r5, 13152)); // ldr x8, [x5, 13152]
402 __ ldrw(r24, Address(r13, 8152)); // ldr w24, [x13, 8152]
403 __ ldrb(r12, Address(r26, 1905)); // ldrb w12, [x26, 1905]
404 __ ldrh(r15, Address(r19, 3442)); // ldrh w15, [x19, 3442]
405 __ ldrsb(r13, Address(r22, 1615)); // ldrsb x13, [x22, 1615]
406 __ ldrsh(r7, Address(r15, 3950)); // ldrsh x7, [x15, 3950]
407 __ ldrshw(r24, Address(r27, 3584)); // ldrsh w24, [x27, 3584]
408 __ ldrsw(r0, Address(r19, 6660)); // ldrsw x0, [x19, 6660]
409 __ ldrd(v1, Address(r14, 13848)); // ldr d1, [x14, 13848]
410 __ ldrs(v18, Address(r28, 7228)); // ldr s18, [x28, 7228]
411 __ strd(v25, Address(r12, 13448)); // str d25, [x12, 13448]
412 __ strs(v25, Address(r1, 6496)); // str s25, [x1, 6496]
413
414 // pcrel
415 // LoadStoreOp
416 __ ldr(r17, forth); // ldr x17, forth
417 __ ldrw(r7, back); // ldr w7, back
418
419 // LoadStoreOp
420 __ prfm(Address(r14, -127)); // prfm PLDL1KEEP, [x14, -127]
421
422 // LoadStoreOp
423 __ prfm(back); // prfm PLDL1KEEP, back
424
425 // LoadStoreOp
426 __ prfm(Address(r0, r22, Address::lsl(0))); // prfm PLDL1KEEP, [x0, x22, lsl #0]
427
428 // LoadStoreOp
429 __ prfm(Address(r23, 15192)); // prfm PLDL1KEEP, [x23, 15192]
430
431 // AddSubCarryOp
432 __ adcw(r17, r24, r12); // adc w17, w24, w12
433 __ adcsw(r0, r24, r5); // adcs w0, w24, w5
434 __ sbcw(r12, r11, r3); // sbc w12, w11, w3
435 __ sbcsw(r10, r5, r19); // sbcs w10, w5, w19
436 __ adc(r20, r0, r14); // adc x20, x0, x14
437 __ adcs(r17, r27, r15); // adcs x17, x27, x15
438 __ sbc(r2, r1, r26); // sbc x2, x1, x26
439 __ sbcs(r24, r26, r8); // sbcs x24, x26, x8
440
441 // AddSubExtendedOp
442 __ addw(r20, r2, r25, ext::sxtx, 2); // add w20, w2, w25, sxtx #2
443 __ addsw(r14, r1, r28, ext::uxtw, 3); // adds w14, w1, w28, uxtw #3
444 __ sub(r1, r11, r4, ext::uxth, 3); // sub x1, x11, x4, uxth #3
445 __ subsw(r5, r28, r19, ext::sxtx, 1); // subs w5, w28, w19, sxtx #1
446 __ add(r19, r29, r14, ext::sxth, 4); // add x19, x29, x14, sxth #4
447 __ adds(r1, r7, r8, ext::uxth, 1); // adds x1, x7, x8, uxth #1
448 __ sub(r7, r27, r14, ext::uxth, 4); // sub x7, x27, x14, uxth #4
449 __ subs(r17, r0, r28, ext::uxtx, 1); // subs x17, x0, x28, uxtx #1
450
451 // ConditionalCompareOp
452 __ ccmnw(r24, r30, 8u, Assembler::LT); // ccmn w24, w30, #8, LT
453 __ ccmpw(r1, r24, 12u, Assembler::VC); // ccmp w1, w24, #12, VC
454 __ ccmn(r20, r11, 14u, Assembler::MI); // ccmn x20, x11, #14, MI
455 __ ccmp(r10, r7, 8u, Assembler::VS); // ccmp x10, x7, #8, VS
456
457 // ConditionalCompareImmedOp
458 __ ccmnw(r2, 30, 10, Assembler::MI); // ccmn w2, #30, #10, MI
459 __ ccmpw(r13, 7, 7, Assembler::MI); // ccmp w13, #7, #7, MI
460 __ ccmn(r12, 18, 6, Assembler::HI); // ccmn x12, #18, #6, HI
461 __ ccmp(r25, 11, 14, Assembler::LE); // ccmp x25, #11, #14, LE
462
463 // ConditionalSelectOp
464 __ cselw(r0, r18, r14, Assembler::CS); // csel w0, w18, w14, CS
465 __ csincw(r1, r9, r24, Assembler::LE); // csinc w1, w9, w24, LE
466 __ csinvw(r3, r27, r1, Assembler::LS); // csinv w3, w27, w1, LS
467 __ csnegw(r0, r13, r26, Assembler::MI); // csneg w0, w13, w26, MI
468 __ csel(r28, r22, r18, Assembler::HS); // csel x28, x22, x18, HS
469 __ csinc(r10, r12, r18, Assembler::LE); // csinc x10, x12, x18, LE
470 __ csinv(r8, r15, r28, Assembler::CC); // csinv x8, x15, x28, CC
471 __ csneg(r19, r23, r19, Assembler::GE); // csneg x19, x23, x19, GE
472
473 // TwoRegOp
474 __ rbitw(r6, r29); // rbit w6, w29
475 __ rev16w(r5, r18); // rev16 w5, w18
476 __ revw(r9, r19); // rev w9, w19
477 __ clzw(r9, r13); // clz w9, w13
478 __ clsw(r21, r8); // cls w21, w8
479 __ rbit(r22, r10); // rbit x22, x10
480 __ rev16(r4, r19); // rev16 x4, x19
481 __ rev32(r5, r13); // rev32 x5, x13
482 __ rev(r12, r2); // rev x12, x2
483 __ clz(r22, r21); // clz x22, x21
484 __ cls(r24, r16); // cls x24, x16
485
486 // ThreeRegOp
487 __ udivw(r17, r5, r6); // udiv w17, w5, w6
488 __ sdivw(r7, r16, r25); // sdiv w7, w16, w25
489 __ lslvw(r11, r27, r22); // lslv w11, w27, w22
490 __ lsrvw(r22, r10, r3); // lsrv w22, w10, w3
491 __ asrvw(r29, r26, r12); // asrv w29, w26, w12
492 __ rorvw(r26, r27, r10); // rorv w26, w27, w10
493 __ udiv(r15, r10, r21); // udiv x15, x10, x21
494 __ sdiv(r28, r30, r23); // sdiv x28, x30, x23
495 __ lslv(r9, r27, r30); // lslv x9, x27, x30
496 __ lsrv(r10, r29, r15); // lsrv x10, x29, x15
497 __ asrv(r29, r30, r25); // asrv x29, x30, x25
498 __ rorv(r21, r4, r0); // rorv x21, x4, x0
499 __ umulh(r18, r21, r29); // umulh x18, x21, x29
500 __ smulh(r16, r21, r20); // smulh x16, x21, x20
501
502 // FourRegMulOp
503 __ maddw(r6, r19, r30, r3); // madd w6, w19, w30, w3
504 __ msubw(r21, r19, r11, r24); // msub w21, w19, w11, w24
505 __ madd(r0, r27, r25, r14); // madd x0, x27, x25, x14
506 __ msub(r3, r14, r18, r7); // msub x3, x14, x18, x7
507 __ smaddl(r15, r24, r28, r17); // smaddl x15, w24, w28, x17
508 __ smsubl(r25, r2, r26, r28); // smsubl x25, w2, w26, x28
509 __ umaddl(r5, r25, r26, r27); // umaddl x5, w25, w26, x27
510 __ umsubl(r16, r18, r6, r21); // umsubl x16, w18, w6, x21
511
512 // ThreeRegFloatOp
513 __ fmuls(v12, v0, v4); // fmul s12, s0, s4
514 __ fdivs(v12, v27, v17); // fdiv s12, s27, s17
515 __ fadds(v28, v28, v2); // fadd s28, s28, s2
516 __ fsubs(v18, v10, v15); // fsub s18, s10, s15
517 __ fmuls(v14, v14, v3); // fmul s14, s14, s3
518 __ fmuld(v25, v15, v19); // fmul d25, d15, d19
519 __ fdivd(v14, v5, v16); // fdiv d14, d5, d16
520 __ faddd(v4, v26, v25); // fadd d4, d26, d25
521 __ fsubd(v4, v2, v2); // fsub d4, d2, d2
522 __ fmuld(v12, v29, v17); // fmul d12, d29, d17
523
524 // FourRegFloatOp
525 __ fmadds(v8, v7, v3, v4); // fmadd s8, s7, s3, s4
526 __ fmsubs(v25, v4, v26, v25); // fmsub s25, s4, s26, s25
527 __ fnmadds(v4, v17, v0, v26); // fnmadd s4, s17, s0, s26
528 __ fnmadds(v17, v23, v15, v21); // fnmadd s17, s23, s15, s21
529 __ fmaddd(v28, v17, v27, v10); // fmadd d28, d17, d27, d10
530 __ fmsubd(v3, v0, v7, v25); // fmsub d3, d0, d7, d25
531 __ fnmaddd(v9, v6, v15, v29); // fnmadd d9, d6, d15, d29
532 __ fnmaddd(v15, v10, v2, v17); // fnmadd d15, d10, d2, d17
533
534 // TwoRegFloatOp
535 __ fmovs(v7, v11); // fmov s7, s11
536 __ fabss(v11, v23); // fabs s11, s23
537 __ fnegs(v7, v29); // fneg s7, s29
538 __ fsqrts(v23, v14); // fsqrt s23, s14
539 __ fcvts(v27, v11); // fcvt d27, s11
540 __ fmovd(v11, v4); // fmov d11, d4
541 __ fabsd(v24, v12); // fabs d24, d12
542 __ fnegd(v15, v14); // fneg d15, d14
543 __ fsqrtd(v20, v11); // fsqrt d20, d11
544 __ fcvtd(v28, v13); // fcvt s28, d13
545
546 // FloatConvertOp
547 __ fcvtzsw(r11, v12); // fcvtzs w11, s12
548 __ fcvtzs(r23, v30); // fcvtzs x23, s30
549 __ fcvtzdw(r26, v14); // fcvtzs w26, d14
550 __ fcvtzd(r9, v13); // fcvtzs x9, d13
551 __ scvtfws(v10, r7); // scvtf s10, w7
552 __ scvtfs(v5, r29); // scvtf s5, x29
553 __ scvtfwd(v15, r3); // scvtf d15, w3
554 __ scvtfd(v11, r12); // scvtf d11, x12
555 __ fmovs(r15, v30); // fmov w15, s30
556 __ fmovd(r30, v17); // fmov x30, d17
557 __ fmovs(v19, r20); // fmov s19, w20
558 __ fmovd(v15, r15); // fmov d15, x15
559
560 // TwoRegFloatOp
561 __ fcmps(v9, v21); // fcmp s9, s21
562 __ fcmpd(v2, v9); // fcmp d2, d9
563 __ fcmps(v27, 0.0); // fcmp s27, #0.0
564 __ fcmpd(v7, 0.0); // fcmp d7, #0.0
565
566 // LoadStorePairOp
567 __ stpw(r30, r17, Address(r1, 128)); // stp w30, w17, [x1, #128]
568 __ ldpw(r6, r10, Address(r3, -224)); // ldp w6, w10, [x3, #-224]
569 __ ldpsw(r11, r7, Address(r1, 48)); // ldpsw x11, x7, [x1, #48]
570 __ stp(r0, r3, Address(r18, -112)); // stp x0, x3, [x18, #-112]
571 __ ldp(r6, r22, Address(r6, 112)); // ldp x6, x22, [x6, #112]
572
573 // LoadStorePairOp
574 __ stpw(r27, r26, Address(__ pre(r2, -256))); // stp w27, w26, [x2, #-256]!
575 __ ldpw(r7, r28, Address(__ pre(r11, -192))); // ldp w7, w28, [x11, #-192]!
576 __ ldpsw(r13, r11, Address(__ pre(r23, 64))); // ldpsw x13, x11, [x23, #64]!
577 __ stp(r8, r18, Address(__ pre(r21, -16))); // stp x8, x18, [x21, #-16]!
578 __ ldp(r20, r19, Address(__ pre(r18, 64))); // ldp x20, x19, [x18, #64]!
579
580 // LoadStorePairOp
581 __ stpw(r29, r22, Address(__ post(r8, -224))); // stp w29, w22, [x8], #-224
582 __ ldpw(r19, r20, Address(__ post(r11, 16))); // ldp w19, w20, [x11], #16
583 __ ldpsw(r20, r6, Address(__ post(r15, -32))); // ldpsw x20, x6, [x15], #-32
584 __ stp(r3, r28, Address(__ post(r3, -208))); // stp x3, x28, [x3], #-208
585 __ ldp(r14, r14, Address(__ post(r10, 96))); // ldp x14, x14, [x10], #96
586
587 // LoadStorePairOp
588 __ stnpw(r11, r17, Address(r10, -96)); // stnp w11, w17, [x10, #-96]
589 __ ldnpw(r7, r7, Address(r14, 64)); // ldnp w7, w7, [x14, #64]
590 __ stnp(r0, r22, Address(r0, 112)); // stnp x0, x22, [x0, #112]
591 __ ldnp(r23, r13, Address(r13, -96)); // ldnp x23, x13, [x13, #-96]
592
593 // LdStNEONOp
594 __ ld1(v2, __ T8B, Address(r7)); // ld1 {v2.8B}, [x7]
595 __ ld1(v14, v15, __ T16B, Address(__ post(r9, 32))); // ld1 {v14.16B, v15.16B}, [x9], 32
596 __ ld1(v16, v17, v18, __ T1D, Address(__ post(r21, r12))); // ld1 {v16.1D, v17.1D, v18.1D}, [x21], x12
597 __ ld1(v17, v18, v19, v20, __ T8H, Address(__ post(r22, 64))); // ld1 {v17.8H, v18.8H, v19.8H, v20.8H}, [x22], 64
598 __ ld1r(v13, __ T8B, Address(r6)); // ld1r {v13.8B}, [x6]
599 __ ld1r(v10, __ T4S, Address(__ post(r20, 4))); // ld1r {v10.4S}, [x20], 4
600 __ ld1r(v4, __ T1D, Address(__ post(r21, r5))); // ld1r {v4.1D}, [x21], x5
601 __ ld2(v6, v7, __ T2D, Address(r23)); // ld2 {v6.2D, v7.2D}, [x23]
602 __ ld2(v15, v16, __ T4H, Address(__ post(r26, 16))); // ld2 {v15.4H, v16.4H}, [x26], 16
603 __ ld2r(v23, v24, __ T16B, Address(r11)); // ld2r {v23.16B, v24.16B}, [x11]
604 __ ld2r(v8, v9, __ T2S, Address(__ post(r23, 8))); // ld2r {v8.2S, v9.2S}, [x23], 8
605 __ ld2r(v19, v20, __ T2D, Address(__ post(r25, r6))); // ld2r {v19.2D, v20.2D}, [x25], x6
606 __ ld3(v29, v30, v31, __ T4S, Address(__ post(r17, r1))); // ld3 {v29.4S, v30.4S, v31.4S}, [x17], x1
607 __ ld3(v24, v25, v26, __ T2S, Address(r23)); // ld3 {v24.2S, v25.2S, v26.2S}, [x23]
608 __ ld3r(v10, v11, v12, __ T8H, Address(r5)); // ld3r {v10.8H, v11.8H, v12.8H}, [x5]
609 __ ld3r(v18, v19, v20, __ T4S, Address(__ post(r10, 12))); // ld3r {v18.4S, v19.4S, v20.4S}, [x10], 12
610 __ ld3r(v12, v13, v14, __ T1D, Address(__ post(r15, r16))); // ld3r {v12.1D, v13.1D, v14.1D}, [x15], x16
611 __ ld4(v25, v26, v27, v28, __ T8H, Address(__ post(r18, 64))); // ld4 {v25.8H, v26.8H, v27.8H, v28.8H}, [x18], 64
612 __ ld4(v1, v2, v3, v4, __ T8B, Address(__ post(r30, r8))); // ld4 {v1.8B, v2.8B, v3.8B, v4.8B}, [x30], x8
613 __ ld4r(v16, v17, v18, v19, __ T8B, Address(r18)); // ld4r {v16.8B, v17.8B, v18.8B, v19.8B}, [x18]
614 __ ld4r(v25, v26, v27, v28, __ T4H, Address(__ post(r12, 8))); // ld4r {v25.4H, v26.4H, v27.4H, v28.4H}, [x12], 8
615 __ ld4r(v26, v27, v28, v29, __ T2S, Address(__ post(r19, r8))); // ld4r {v26.2S, v27.2S, v28.2S, v29.2S}, [x19], x8
616
617 // NEONReduceInstruction
618 __ addv(v21, __ T8B, v22); // addv b21, v22.8B
619 __ addv(v4, __ T16B, v5); // addv b4, v5.16B
620 __ addv(v18, __ T4H, v19); // addv h18, v19.4H
621 __ addv(v24, __ T8H, v25); // addv h24, v25.8H
622 __ addv(v12, __ T4S, v13); // addv s12, v13.4S
623 __ smaxv(v18, __ T8B, v19); // smaxv b18, v19.8B
624 __ smaxv(v7, __ T16B, v8); // smaxv b7, v8.16B
625 __ smaxv(v9, __ T4H, v10); // smaxv h9, v10.4H
626 __ smaxv(v25, __ T8H, v26); // smaxv h25, v26.8H
627 __ smaxv(v15, __ T4S, v16); // smaxv s15, v16.4S
628 __ fmaxv(v13, __ T4S, v14); // fmaxv s13, v14.4S
629 __ sminv(v3, __ T8B, v4); // sminv b3, v4.8B
630 __ sminv(v11, __ T16B, v12); // sminv b11, v12.16B
631 __ sminv(v16, __ T4H, v17); // sminv h16, v17.4H
632 __ sminv(v7, __ T8H, v8); // sminv h7, v8.8H
633 __ sminv(v25, __ T4S, v26); // sminv s25, v26.4S
634 __ fminv(v11, __ T4S, v12); // fminv s11, v12.4S
635
636 // TwoRegNEONOp
637 __ absr(v7, __ T8B, v8); // abs v7.8B, v8.8B
638 __ absr(v9, __ T16B, v10); // abs v9.16B, v10.16B
639 __ absr(v25, __ T4H, v26); // abs v25.4H, v26.4H
640 __ absr(v28, __ T8H, v29); // abs v28.8H, v29.8H
641 __ absr(v29, __ T2S, v30); // abs v29.2S, v30.2S
642 __ absr(v0, __ T4S, v1); // abs v0.4S, v1.4S
643 __ absr(v23, __ T2D, v24); // abs v23.2D, v24.2D
644 __ fabs(v16, __ T2S, v17); // fabs v16.2S, v17.2S
645 __ fabs(v3, __ T4S, v4); // fabs v3.4S, v4.4S
646 __ fabs(v7, __ T2D, v8); // fabs v7.2D, v8.2D
647 __ fneg(v8, __ T2S, v9); // fneg v8.2S, v9.2S
648 __ fneg(v12, __ T4S, v13); // fneg v12.4S, v13.4S
649 __ fneg(v14, __ T2D, v15); // fneg v14.2D, v15.2D
650 __ fsqrt(v29, __ T2S, v30); // fsqrt v29.2S, v30.2S
651 __ fsqrt(v1, __ T4S, v2); // fsqrt v1.4S, v2.4S
652 __ fsqrt(v21, __ T2D, v22); // fsqrt v21.2D, v22.2D
653 __ notr(v26, __ T8B, v27); // not v26.8B, v27.8B
654 __ notr(v11, __ T16B, v12); // not v11.16B, v12.16B
655
656 // ThreeRegNEONOp
657 __ andr(v7, __ T8B, v8, v9); // and v7.8B, v8.8B, v9.8B
658 __ andr(v6, __ T16B, v7, v8); // and v6.16B, v7.16B, v8.16B
659 __ orr(v9, __ T8B, v10, v11); // orr v9.8B, v10.8B, v11.8B
660 __ orr(v4, __ T16B, v5, v6); // orr v4.16B, v5.16B, v6.16B
661 __ eor(v17, __ T8B, v18, v19); // eor v17.8B, v18.8B, v19.8B
662 __ eor(v7, __ T16B, v8, v9); // eor v7.16B, v8.16B, v9.16B
663 __ addv(v0, __ T8B, v1, v2); // add v0.8B, v1.8B, v2.8B
664 __ addv(v7, __ T16B, v8, v9); // add v7.16B, v8.16B, v9.16B
665 __ addv(v25, __ T4H, v26, v27); // add v25.4H, v26.4H, v27.4H
666 __ addv(v12, __ T8H, v13, v14); // add v12.8H, v13.8H, v14.8H
667 __ addv(v27, __ T2S, v28, v29); // add v27.2S, v28.2S, v29.2S
668 __ addv(v29, __ T4S, v30, v31); // add v29.4S, v30.4S, v31.4S
669 __ addv(v7, __ T2D, v8, v9); // add v7.2D, v8.2D, v9.2D
670 __ fadd(v17, __ T2S, v18, v19); // fadd v17.2S, v18.2S, v19.2S
671 __ fadd(v27, __ T4S, v28, v29); // fadd v27.4S, v28.4S, v29.4S
672 __ fadd(v18, __ T2D, v19, v20); // fadd v18.2D, v19.2D, v20.2D
673 __ subv(v5, __ T8B, v6, v7); // sub v5.8B, v6.8B, v7.8B
674 __ subv(v7, __ T16B, v8, v9); // sub v7.16B, v8.16B, v9.16B
675 __ subv(v30, __ T4H, v31, v0); // sub v30.4H, v31.4H, v0.4H
676 __ subv(v9, __ T8H, v10, v11); // sub v9.8H, v10.8H, v11.8H
677 __ subv(v26, __ T2S, v27, v28); // sub v26.2S, v27.2S, v28.2S
678 __ subv(v24, __ T4S, v25, v26); // sub v24.4S, v25.4S, v26.4S
679 __ subv(v23, __ T2D, v24, v25); // sub v23.2D, v24.2D, v25.2D
680 __ fsub(v22, __ T2S, v23, v24); // fsub v22.2S, v23.2S, v24.2S
681 __ fsub(v24, __ T4S, v25, v26); // fsub v24.4S, v25.4S, v26.4S
682 __ fsub(v26, __ T2D, v27, v28); // fsub v26.2D, v27.2D, v28.2D
683 __ mulv(v1, __ T8B, v2, v3); // mul v1.8B, v2.8B, v3.8B
684 __ mulv(v5, __ T16B, v6, v7); // mul v5.16B, v6.16B, v7.16B
685 __ mulv(v15, __ T4H, v16, v17); // mul v15.4H, v16.4H, v17.4H
686 __ mulv(v6, __ T8H, v7, v8); // mul v6.8H, v7.8H, v8.8H
687 __ mulv(v16, __ T2S, v17, v18); // mul v16.2S, v17.2S, v18.2S
688 __ mulv(v15, __ T4S, v16, v17); // mul v15.4S, v16.4S, v17.4S
689 __ fmul(v3, __ T2S, v4, v5); // fmul v3.2S, v4.2S, v5.2S
690 __ fmul(v2, __ T4S, v3, v4); // fmul v2.4S, v3.4S, v4.4S
691 __ fmul(v0, __ T2D, v1, v2); // fmul v0.2D, v1.2D, v2.2D
692 __ mlav(v25, __ T4H, v26, v27); // mla v25.4H, v26.4H, v27.4H
693 __ mlav(v2, __ T8H, v3, v4); // mla v2.8H, v3.8H, v4.8H
694 __ mlav(v29, __ T2S, v30, v31); // mla v29.2S, v30.2S, v31.2S
695 __ mlav(v30, __ T4S, v31, v0); // mla v30.4S, v31.4S, v0.4S
696 __ fmla(v23, __ T2S, v24, v25); // fmla v23.2S, v24.2S, v25.2S
697 __ fmla(v13, __ T4S, v14, v15); // fmla v13.4S, v14.4S, v15.4S
698 __ fmla(v8, __ T2D, v9, v10); // fmla v8.2D, v9.2D, v10.2D
699 __ mlsv(v12, __ T4H, v13, v14); // mls v12.4H, v13.4H, v14.4H
700 __ mlsv(v10, __ T8H, v11, v12); // mls v10.8H, v11.8H, v12.8H
701 __ mlsv(v12, __ T2S, v13, v14); // mls v12.2S, v13.2S, v14.2S
702 __ mlsv(v22, __ T4S, v23, v24); // mls v22.4S, v23.4S, v24.4S
703 __ fmls(v27, __ T2S, v28, v29); // fmls v27.2S, v28.2S, v29.2S
704 __ fmls(v4, __ T4S, v5, v6); // fmls v4.4S, v5.4S, v6.4S
705 __ fmls(v7, __ T2D, v8, v9); // fmls v7.2D, v8.2D, v9.2D
706 __ fdiv(v6, __ T2S, v7, v8); // fdiv v6.2S, v7.2S, v8.2S
707 __ fdiv(v1, __ T4S, v2, v3); // fdiv v1.4S, v2.4S, v3.4S
708 __ fdiv(v26, __ T2D, v27, v28); // fdiv v26.2D, v27.2D, v28.2D
709 __ maxv(v15, __ T8B, v16, v17); // smax v15.8B, v16.8B, v17.8B
710 __ maxv(v2, __ T16B, v3, v4); // smax v2.16B, v3.16B, v4.16B
711 __ maxv(v13, __ T4H, v14, v15); // smax v13.4H, v14.4H, v15.4H
712 __ maxv(v13, __ T8H, v14, v15); // smax v13.8H, v14.8H, v15.8H
713 __ maxv(v24, __ T2S, v25, v26); // smax v24.2S, v25.2S, v26.2S
714 __ maxv(v23, __ T4S, v24, v25); // smax v23.4S, v24.4S, v25.4S
715 __ fmax(v4, __ T2S, v5, v6); // fmax v4.2S, v5.2S, v6.2S
716 __ fmax(v19, __ T4S, v20, v21); // fmax v19.4S, v20.4S, v21.4S
717 __ fmax(v15, __ T2D, v16, v17); // fmax v15.2D, v16.2D, v17.2D
718 __ minv(v0, __ T8B, v1, v2); // smin v0.8B, v1.8B, v2.8B
719 __ minv(v4, __ T16B, v5, v6); // smin v4.16B, v5.16B, v6.16B
720 __ minv(v20, __ T4H, v21, v22); // smin v20.4H, v21.4H, v22.4H
721 __ minv(v11, __ T8H, v12, v13); // smin v11.8H, v12.8H, v13.8H
722 __ minv(v29, __ T2S, v30, v31); // smin v29.2S, v30.2S, v31.2S
723 __ minv(v15, __ T4S, v16, v17); // smin v15.4S, v16.4S, v17.4S
724 __ fmin(v21, __ T2S, v22, v23); // fmin v21.2S, v22.2S, v23.2S
725 __ fmin(v4, __ T4S, v5, v6); // fmin v4.4S, v5.4S, v6.4S
726 __ fmin(v14, __ T2D, v15, v16); // fmin v14.2D, v15.2D, v16.2D
727 __ cmeq(v22, __ T8B, v23, v24); // cmeq v22.8B, v23.8B, v24.8B
728 __ cmeq(v25, __ T16B, v26, v27); // cmeq v25.16B, v26.16B, v27.16B
729 __ cmeq(v6, __ T4H, v7, v8); // cmeq v6.4H, v7.4H, v8.4H
730 __ cmeq(v12, __ T8H, v13, v14); // cmeq v12.8H, v13.8H, v14.8H
731 __ cmeq(v14, __ T2S, v15, v16); // cmeq v14.2S, v15.2S, v16.2S
732 __ cmeq(v13, __ T4S, v14, v15); // cmeq v13.4S, v14.4S, v15.4S
733 __ cmeq(v14, __ T2D, v15, v16); // cmeq v14.2D, v15.2D, v16.2D
734 __ fcmeq(v9, __ T2S, v10, v11); // fcmeq v9.2S, v10.2S, v11.2S
735 __ fcmeq(v25, __ T4S, v26, v27); // fcmeq v25.4S, v26.4S, v27.4S
736 __ fcmeq(v28, __ T2D, v29, v30); // fcmeq v28.2D, v29.2D, v30.2D
737 __ cmgt(v10, __ T8B, v11, v12); // cmgt v10.8B, v11.8B, v12.8B
738 __ cmgt(v19, __ T16B, v20, v21); // cmgt v19.16B, v20.16B, v21.16B
739 __ cmgt(v11, __ T4H, v12, v13); // cmgt v11.4H, v12.4H, v13.4H
740 __ cmgt(v17, __ T8H, v18, v19); // cmgt v17.8H, v18.8H, v19.8H
741 __ cmgt(v21, __ T2S, v22, v23); // cmgt v21.2S, v22.2S, v23.2S
742 __ cmgt(v15, __ T4S, v16, v17); // cmgt v15.4S, v16.4S, v17.4S
743 __ cmgt(v20, __ T2D, v21, v22); // cmgt v20.2D, v21.2D, v22.2D
744 __ fcmgt(v23, __ T2S, v24, v25); // fcmgt v23.2S, v24.2S, v25.2S
745 __ fcmgt(v26, __ T4S, v27, v28); // fcmgt v26.4S, v27.4S, v28.4S
746 __ fcmgt(v5, __ T2D, v6, v7); // fcmgt v5.2D, v6.2D, v7.2D
747 __ cmge(v6, __ T8B, v7, v8); // cmge v6.8B, v7.8B, v8.8B
748 __ cmge(v15, __ T16B, v16, v17); // cmge v15.16B, v16.16B, v17.16B
749 __ cmge(v15, __ T4H, v16, v17); // cmge v15.4H, v16.4H, v17.4H
750 __ cmge(v25, __ T8H, v26, v27); // cmge v25.8H, v26.8H, v27.8H
751 __ cmge(v16, __ T2S, v17, v18); // cmge v16.2S, v17.2S, v18.2S
752 __ cmge(v27, __ T4S, v28, v29); // cmge v27.4S, v28.4S, v29.4S
753 __ cmge(v24, __ T2D, v25, v26); // cmge v24.2D, v25.2D, v26.2D
754 __ fcmge(v15, __ T2S, v16, v17); // fcmge v15.2S, v16.2S, v17.2S
755 __ fcmge(v25, __ T4S, v26, v27); // fcmge v25.4S, v26.4S, v27.4S
756 __ fcmge(v14, __ T2D, v15, v16); // fcmge v14.2D, v15.2D, v16.2D
757
758 // SpecialCases
759 __ ccmn(zr, zr, 3u, Assembler::LE); // ccmn xzr, xzr, #3, LE
760 __ ccmnw(zr, zr, 5u, Assembler::EQ); // ccmn wzr, wzr, #5, EQ
761 __ ccmp(zr, 1, 4u, Assembler::NE); // ccmp xzr, 1, #4, NE
762 __ ccmpw(zr, 2, 2, Assembler::GT); // ccmp wzr, 2, #2, GT
763 __ extr(zr, zr, zr, 0); // extr xzr, xzr, xzr, 0
764 __ stlxp(r0, zr, zr, sp); // stlxp w0, xzr, xzr, [sp]
765 __ stlxpw(r2, zr, zr, r3); // stlxp w2, wzr, wzr, [x3]
766 __ stxp(r4, zr, zr, r5); // stxp w4, xzr, xzr, [x5]
767 __ stxpw(r6, zr, zr, sp); // stxp w6, wzr, wzr, [sp]
768 __ dup(v0, __ T16B, zr); // dup v0.16b, wzr
769 __ mov(v1, __ T1D, 0, zr); // mov v1.d[0], xzr
770 __ mov(v1, __ T2S, 1, zr); // mov v1.s[1], wzr
771 __ mov(v1, __ T4H, 2, zr); // mov v1.h[2], wzr
772 __ mov(v1, __ T8B, 3, zr); // mov v1.b[3], wzr
773 __ ld1(v31, v0, __ T2D, Address(__ post(r1, r0))); // ld1 {v31.2d, v0.2d}, [x1], x0
774
775 // FloatImmediateOp
776 __ fmovd(v0, 2.0); // fmov d0, #2.0
777 __ fmovd(v0, 2.125); // fmov d0, #2.125
778 __ fmovd(v0, 4.0); // fmov d0, #4.0
779 __ fmovd(v0, 4.25); // fmov d0, #4.25
780 __ fmovd(v0, 8.0); // fmov d0, #8.0
781 __ fmovd(v0, 8.5); // fmov d0, #8.5
782 __ fmovd(v0, 16.0); // fmov d0, #16.0
783 __ fmovd(v0, 17.0); // fmov d0, #17.0
784 __ fmovd(v0, 0.125); // fmov d0, #0.125
785 __ fmovd(v0, 0.1328125); // fmov d0, #0.1328125
786 __ fmovd(v0, 0.25); // fmov d0, #0.25
787 __ fmovd(v0, 0.265625); // fmov d0, #0.265625
788 __ fmovd(v0, 0.5); // fmov d0, #0.5
789 __ fmovd(v0, 0.53125); // fmov d0, #0.53125
790 __ fmovd(v0, 1.0); // fmov d0, #1.0
791 __ fmovd(v0, 1.0625); // fmov d0, #1.0625
792 __ fmovd(v0, -2.0); // fmov d0, #-2.0
793 __ fmovd(v0, -2.125); // fmov d0, #-2.125
794 __ fmovd(v0, -4.0); // fmov d0, #-4.0
795 __ fmovd(v0, -4.25); // fmov d0, #-4.25
796 __ fmovd(v0, -8.0); // fmov d0, #-8.0
797 __ fmovd(v0, -8.5); // fmov d0, #-8.5
798 __ fmovd(v0, -16.0); // fmov d0, #-16.0
799 __ fmovd(v0, -17.0); // fmov d0, #-17.0
800 __ fmovd(v0, -0.125); // fmov d0, #-0.125
801 __ fmovd(v0, -0.1328125); // fmov d0, #-0.1328125
802 __ fmovd(v0, -0.25); // fmov d0, #-0.25
803 __ fmovd(v0, -0.265625); // fmov d0, #-0.265625
804 __ fmovd(v0, -0.5); // fmov d0, #-0.5
805 __ fmovd(v0, -0.53125); // fmov d0, #-0.53125
806 __ fmovd(v0, -1.0); // fmov d0, #-1.0
807 __ fmovd(v0, -1.0625); // fmov d0, #-1.0625
808
809 // LSEOp
810 __ swp(Assembler::xword, r10, r13, r14); // swp x10, x13, [x14]
811 __ ldadd(Assembler::xword, r20, r1, r23); // ldadd x20, x1, [x23]
812 __ ldbic(Assembler::xword, r30, r14, r2); // ldclr x30, x14, [x2]
813 __ ldeor(Assembler::xword, r6, r3, r8); // ldeor x6, x3, [x8]
814 __ ldorr(Assembler::xword, r25, r0, r27); // ldset x25, x0, [x27]
815 __ ldsmin(Assembler::xword, r30, r5, r5); // ldsmin x30, x5, [x5]
816 __ ldsmax(Assembler::xword, r30, r11, r25); // ldsmax x30, x11, [x25]
817 __ ldumin(Assembler::xword, r0, zr, r0); // ldumin x0, xzr, [x0]
818 __ ldumax(Assembler::xword, r19, r29, r26); // ldumax x19, x29, [x26]
819
820 // LSEOp
821 __ swpa(Assembler::xword, r9, r26, r12); // swpa x9, x26, [x12]
822 __ ldadda(Assembler::xword, r15, r11, r11); // ldadda x15, x11, [x11]
823 __ ldbica(Assembler::xword, r18, r25, r22); // ldclra x18, x25, [x22]
824 __ ldeora(Assembler::xword, r24, r0, r17); // ldeora x24, x0, [x17]
825 __ ldorra(Assembler::xword, r11, r6, r29); // ldseta x11, x6, [x29]
826 __ ldsmina(Assembler::xword, r6, r5, r5); // ldsmina x6, x5, [x5]
827 __ ldsmaxa(Assembler::xword, r21, r19, r16); // ldsmaxa x21, x19, [x16]
828 __ ldumina(Assembler::xword, r18, r30, r27); // ldumina x18, x30, [x27]
829 __ ldumaxa(Assembler::xword, r28, r1, r28); // ldumaxa x28, x1, [x28]
830
831 // LSEOp
832 __ swpal(Assembler::xword, r1, r20, r29); // swpal x1, x20, [x29]
833 __ ldaddal(Assembler::xword, r16, r13, r10); // ldaddal x16, x13, [x10]
834 __ ldbical(Assembler::xword, r29, r29, r19); // ldclral x29, x29, [x19]
835 __ ldeoral(Assembler::xword, r22, r10, r4); // ldeoral x22, x10, [x4]
836 __ ldorral(Assembler::xword, zr, r21, r8); // ldsetal xzr, x21, [x8]
837 __ ldsminal(Assembler::xword, zr, r19, r10); // ldsminal xzr, x19, [x10]
838 __ ldsmaxal(Assembler::xword, r28, r2, r25); // ldsmaxal x28, x2, [x25]
839 __ lduminal(Assembler::xword, r5, r3, r8); // lduminal x5, x3, [x8]
840 __ ldumaxal(Assembler::xword, r22, r19, r13); // ldumaxal x22, x19, [x13]
841
842 // LSEOp
843 __ swpl(Assembler::xword, r5, r29, r24); // swpl x5, x29, [x24]
844 __ ldaddl(Assembler::xword, r21, r26, r24); // ldaddl x21, x26, [x24]
845 __ ldbicl(Assembler::xword, r3, r24, r26); // ldclrl x3, x24, [x26]
846 __ ldeorl(Assembler::xword, r23, r15, r21); // ldeorl x23, x15, [x21]
847 __ ldorrl(Assembler::xword, r3, r24, r8); // ldsetl x3, x24, [x8]
848 __ ldsminl(Assembler::xword, r25, r20, r16); // ldsminl x25, x20, [x16]
849 __ ldsmaxl(Assembler::xword, r17, r2, r1); // ldsmaxl x17, x2, [x1]
850 __ lduminl(Assembler::xword, r0, r24, r4); // lduminl x0, x24, [x4]
851 __ ldumaxl(Assembler::xword, r3, r12, sp); // ldumaxl x3, x12, [sp]
852
853 // LSEOp
854 __ swp(Assembler::word, r28, r10, r26); // swp w28, w10, [x26]
855 __ ldadd(Assembler::word, r2, r12, r18); // ldadd w2, w12, [x18]
856 __ ldbic(Assembler::word, zr, r1, r13); // ldclr wzr, w1, [x13]
857 __ ldeor(Assembler::word, r29, r0, r19); // ldeor w29, w0, [x19]
858 __ ldorr(Assembler::word, r12, r17, r22); // ldset w12, w17, [x22]
859 __ ldsmin(Assembler::word, r13, r28, r30); // ldsmin w13, w28, [x30]
860 __ ldsmax(Assembler::word, zr, r1, r26); // ldsmax wzr, w1, [x26]
861 __ ldumin(Assembler::word, r28, r4, r30); // ldumin w28, w4, [x30]
862 __ ldumax(Assembler::word, r4, r6, r30); // ldumax w4, w6, [x30]
863
864 // LSEOp
865 __ swpa(Assembler::word, r26, r18, r9); // swpa w26, w18, [x9]
866 __ ldadda(Assembler::word, r8, r12, r0); // ldadda w8, w12, [x0]
867 __ ldbica(Assembler::word, r20, r1, r24); // ldclra w20, w1, [x24]
868 __ ldeora(Assembler::word, r2, r0, r9); // ldeora w2, w0, [x9]
869 __ ldorra(Assembler::word, r24, r26, r16); // ldseta w24, w26, [x16]
870 __ ldsmina(Assembler::word, r30, r3, r10); // ldsmina w30, w3, [x10]
871 __ ldsmaxa(Assembler::word, r23, r10, r4); // ldsmaxa w23, w10, [x4]
872 __ ldumina(Assembler::word, r18, r2, r11); // ldumina w18, w2, [x11]
873 __ ldumaxa(Assembler::word, r8, r10, r15); // ldumaxa w8, w10, [x15]
874
875 // LSEOp
876 __ swpal(Assembler::word, r17, r2, r10); // swpal w17, w2, [x10]
877 __ ldaddal(Assembler::word, r12, r12, r15); // ldaddal w12, w12, [x15]
878 __ ldbical(Assembler::word, r13, r2, r7); // ldclral w13, w2, [x7]
879 __ ldeoral(Assembler::word, r20, r26, r16); // ldeoral w20, w26, [x16]
880 __ ldorral(Assembler::word, r4, r2, r4); // ldsetal w4, w2, [x4]
881 __ ldsminal(Assembler::word, r12, r18, r21); // ldsminal w12, w18, [x21]
882 __ ldsmaxal(Assembler::word, r16, r18, r11); // ldsmaxal w16, w18, [x11]
883 __ lduminal(Assembler::word, r21, r23, r12); // lduminal w21, w23, [x12]
884 __ ldumaxal(Assembler::word, r26, r23, r28); // ldumaxal w26, w23, [x28]
885
886 // LSEOp
887 __ swpl(Assembler::word, r14, r11, r24); // swpl w14, w11, [x24]
888 __ ldaddl(Assembler::word, r1, r12, sp); // ldaddl w1, w12, [sp]
889 __ ldbicl(Assembler::word, r10, r16, r7); // ldclrl w10, w16, [x7]
890 __ ldeorl(Assembler::word, r2, r3, r13); // ldeorl w2, w3, [x13]
891 __ ldorrl(Assembler::word, r19, r17, r16); // ldsetl w19, w17, [x16]
892 __ ldsminl(Assembler::word, r3, r1, r11); // ldsminl w3, w1, [x11]
893 __ ldsmaxl(Assembler::word, r30, r5, r8); // ldsmaxl w30, w5, [x8]
894 __ lduminl(Assembler::word, r15, r29, r30); // lduminl w15, w29, [x30]
895 __ ldumaxl(Assembler::word, r0, r20, r7); // ldumaxl w0, w20, [x7]
896
897 __ bind(forth);
898
899 /*
900
901 aarch64ops.o: file format elf64-littleaarch64
902
903
904 Disassembly of section .text:
905
906 0000000000000000 <back>:
907 0: 8b0d82fa add x26, x23, x13, lsl #32
908 4: cb49970c sub x12, x24, x9, lsr #37
909 8: ab889dfc adds x28, x15, x8, asr #39
910 c: eb9ee787 subs x7, x28, x30, asr #57
911 10: 0b9b3ec9 add w9, w22, w27, asr #15
912 14: 4b9279a3 sub w3, w13, w18, asr #30
913 18: 2b88474e adds w14, w26, w8, asr #17
914 1c: 6b8c56c0 subs w0, w22, w12, asr #21
915 20: 8a1a51e0 and x0, x15, x26, lsl #20
916 24: aa11f4ba orr x26, x5, x17, lsl #61
917 28: ca0281b8 eor x24, x13, x2, lsl #32
918 2c: ea918c7c ands x28, x3, x17, asr #35
919 30: 0a5d4a19 and w25, w16, w29, lsr #18
920 34: 2a4b264d orr w13, w18, w11, lsr #9
921 38: 4a523ca5 eor w5, w5, w18, lsr #15
922 3c: 6a9b6ae2 ands w2, w23, w27, asr #26
923 40: 8a70b79b bic x27, x28, x16, lsr #45
924 44: aaba9728 orn x8, x25, x26, asr #37
925 48: ca6dfe3d eon x29, x17, x13, lsr #63
926 4c: ea627f1c bics x28, x24, x2, lsr #31
927 50: 0aa70f53 bic w19, w26, w7, asr #3
928 54: 2aaa0f06 orn w6, w24, w10, asr #3
929 58: 4a6176a4 eon w4, w21, w1, lsr #29
930 5c: 6a604eb0 bics w16, w21, w0, lsr #19
931 60: 1105ed91 add w17, w12, #0x17b
932 64: 3100583e adds w30, w1, #0x16
933 68: 5101f8bd sub w29, w5, #0x7e
934 6c: 710f0306 subs w6, w24, #0x3c0
935 70: 9101a1a0 add x0, x13, #0x68
936 74: b10a5cc8 adds x8, x6, #0x297
937 78: d10810aa sub x10, x5, #0x204
938 7c: f10fd061 subs x1, x3, #0x3f4
939 80: 120cb166 and w6, w11, #0xfff1fff1
940 84: 321764bc orr w28, w5, #0xfffffe07
941 88: 52174681 eor w1, w20, #0x7fffe00
942 8c: 720c0247 ands w7, w18, #0x100000
943 90: 9241018e and x14, x12, #0x8000000000000000
944 94: b25a2969 orr x9, x11, #0x1ffc000000000
945 98: d278b411 eor x17, x0, #0x3fffffffffff00
946 9c: f26aad01 ands x1, x8, #0xffffffffffc00003
947 a0: 14000000 b a0 <back+0xa0>
948 a4: 17ffffd7 b 0 <back>
949 a8: 14000275 b a7c <forth>
950 ac: 94000000 bl ac <back+0xac>
951 b0: 97ffffd4 bl 0 <back>
952 b4: 94000272 bl a7c <forth>
953 b8: 3400000a cbz w10, b8 <back+0xb8>
954 bc: 34fffa2a cbz w10, 0 <back>
955 c0: 34004dea cbz w10, a7c <forth>
956 c4: 35000008 cbnz w8, c4 <back+0xc4>
957 c8: 35fff9c8 cbnz w8, 0 <back>
958 cc: 35004d88 cbnz w8, a7c <forth>
959 d0: b400000b cbz x11, d0 <back+0xd0>
960 d4: b4fff96b cbz x11, 0 <back>
961 d8: b4004d2b cbz x11, a7c <forth>
962 dc: b500001d cbnz x29, dc <back+0xdc>
963 e0: b5fff91d cbnz x29, 0 <back>
964 e4: b5004cdd cbnz x29, a7c <forth>
965 e8: 10000013 adr x19, e8 <back+0xe8>
966 ec: 10fff8b3 adr x19, 0 <back>
967 f0: 10004c73 adr x19, a7c <forth>
968 f4: 90000013 adrp x19, 0 <back>
969 f8: 36300016 tbz w22, #6, f8 <back+0xf8>
970 fc: 3637f836 tbz w22, #6, 0 <back>
971 100: 36304bf6 tbz w22, #6, a7c <forth>
972 104: 3758000c tbnz w12, #11, 104 <back+0x104>
973 108: 375ff7cc tbnz w12, #11, 0 <back>
974 10c: 37584b8c tbnz w12, #11, a7c <forth>
975 110: 128313a0 mov w0, #0xffffe762 // #-6302
976 114: 528a32c7 mov w7, #0x5196 // #20886
977 118: 7289173b movk w27, #0x48b9
978 11c: 92ab3acc mov x12, #0xffffffffa629ffff // #-1507196929
979 120: d2a0bf94 mov x20, #0x5fc0000 // #100401152
980 124: f2c285e8 movk x8, #0x142f, lsl #32
981 128: 9358722f sbfx x15, x17, #24, #5
982 12c: 330e652f bfxil w15, w9, #14, #12
983 130: 53067f3b lsr w27, w25, #6
984 134: 93577c53 sbfx x19, x2, #23, #9
985 138: b34a1aac bfi x12, x21, #54, #7
986 13c: d35a4016 ubfiz x22, x0, #38, #17
987 140: 13946c63 extr w3, w3, w20, #27
988 144: 93c3dbc8 extr x8, x30, x3, #54
989 148: 54000000 b.eq 148 <back+0x148> // b.none
990 14c: 54fff5a0 b.eq 0 <back> // b.none
991 150: 54004960 b.eq a7c <forth> // b.none
992 154: 54000001 b.ne 154 <back+0x154> // b.any
993 158: 54fff541 b.ne 0 <back> // b.any
994 15c: 54004901 b.ne a7c <forth> // b.any
995 160: 54000002 b.cs 160 <back+0x160> // b.hs, b.nlast
996 164: 54fff4e2 b.cs 0 <back> // b.hs, b.nlast
997 168: 540048a2 b.cs a7c <forth> // b.hs, b.nlast
998 16c: 54000002 b.cs 16c <back+0x16c> // b.hs, b.nlast
999 170: 54fff482 b.cs 0 <back> // b.hs, b.nlast
1000 174: 54004842 b.cs a7c <forth> // b.hs, b.nlast
1001 178: 54000003 b.cc 178 <back+0x178> // b.lo, b.ul, b.last
1002 17c: 54fff423 b.cc 0 <back> // b.lo, b.ul, b.last
1003 180: 540047e3 b.cc a7c <forth> // b.lo, b.ul, b.last
1004 184: 54000003 b.cc 184 <back+0x184> // b.lo, b.ul, b.last
1005 188: 54fff3c3 b.cc 0 <back> // b.lo, b.ul, b.last
1006 18c: 54004783 b.cc a7c <forth> // b.lo, b.ul, b.last
1007 190: 54000004 b.mi 190 <back+0x190> // b.first
1008 194: 54fff364 b.mi 0 <back> // b.first
1009 198: 54004724 b.mi a7c <forth> // b.first
1010 19c: 54000005 b.pl 19c <back+0x19c> // b.nfrst
1011 1a0: 54fff305 b.pl 0 <back> // b.nfrst
1012 1a4: 540046c5 b.pl a7c <forth> // b.nfrst
1013 1a8: 54000006 b.vs 1a8 <back+0x1a8>
1014 1ac: 54fff2a6 b.vs 0 <back>
1015 1b0: 54004666 b.vs a7c <forth>
1016 1b4: 54000007 b.vc 1b4 <back+0x1b4>
1017 1b8: 54fff247 b.vc 0 <back>
1018 1bc: 54004607 b.vc a7c <forth>
1019 1c0: 54000008 b.hi 1c0 <back+0x1c0> // b.pmore
1020 1c4: 54fff1e8 b.hi 0 <back> // b.pmore
1021 1c8: 540045a8 b.hi a7c <forth> // b.pmore
1022 1cc: 54000009 b.ls 1cc <back+0x1cc> // b.plast
1023 1d0: 54fff189 b.ls 0 <back> // b.plast
1024 1d4: 54004549 b.ls a7c <forth> // b.plast
1025 1d8: 5400000a b.ge 1d8 <back+0x1d8> // b.tcont
1026 1dc: 54fff12a b.ge 0 <back> // b.tcont
1027 1e0: 540044ea b.ge a7c <forth> // b.tcont
1028 1e4: 5400000b b.lt 1e4 <back+0x1e4> // b.tstop
1029 1e8: 54fff0cb b.lt 0 <back> // b.tstop
1030 1ec: 5400448b b.lt a7c <forth> // b.tstop
1031 1f0: 5400000c b.gt 1f0 <back+0x1f0>
1032 1f4: 54fff06c b.gt 0 <back>
1033 1f8: 5400442c b.gt a7c <forth>
1034 1fc: 5400000d b.le 1fc <back+0x1fc>
1035 200: 54fff00d b.le 0 <back>
1036 204: 540043cd b.le a7c <forth>
1037 208: 5400000e b.al 208 <back+0x208>
1038 20c: 54ffefae b.al 0 <back>
1039 210: 5400436e b.al a7c <forth>
1040 214: 5400000f b.nv 214 <back+0x214>
1041 218: 54ffef4f b.nv 0 <back>
1042 21c: 5400430f b.nv a7c <forth>
1043 220: d40658e1 svc #0x32c7
1044 224: d4014d22 hvc #0xa69
1045 228: d4046543 smc #0x232a
1046 22c: d4273f60 brk #0x39fb
1047 230: d44cad80 hlt #0x656c
1048 234: d503201f nop
1049 238: d69f03e0 eret
1050 23c: d6bf03e0 drps
1051 240: d5033fdf isb
1052 244: d5033e9f dsb st
1053 248: d50332bf dmb oshst
1054 24c: d61f0200 br x16
1055 250: d63f0280 blr x20
1056 254: c80a7d1b stxr w10, x27, [x8]
1057 258: c800fea1 stlxr w0, x1, [x21]
1058 25c: c85f7fb1 ldxr x17, [x29]
1059 260: c85fff9d ldaxr x29, [x28]
1060 264: c89ffee1 stlr x1, [x23]
1061 268: c8dffe95 ldar x21, [x20]
1062 26c: 88167e7b stxr w22, w27, [x19]
1063 270: 880bfcd0 stlxr w11, w16, [x6]
1064 274: 885f7c12 ldxr w18, [x0]
1065 278: 885ffd44 ldaxr w4, [x10]
1066 27c: 889ffed8 stlr w24, [x22]
1067 280: 88dffe6a ldar w10, [x19]
1068 284: 48017fc5 stxrh w1, w5, [x30]
1069 288: 4808fe2c stlxrh w8, w12, [x17]
1070 28c: 485f7dc9 ldxrh w9, [x14]
1071 290: 485ffc27 ldaxrh w7, [x1]
1072 294: 489ffe05 stlrh w5, [x16]
1073 298: 48dffd82 ldarh w2, [x12]
1074 29c: 080a7c6c stxrb w10, w12, [x3]
1075 2a0: 081cff4e stlxrb w28, w14, [x26]
1076 2a4: 085f7d5e ldxrb w30, [x10]
1077 2a8: 085ffeae ldaxrb w14, [x21]
1078 2ac: 089ffd2d stlrb w13, [x9]
1079 2b0: 08dfff76 ldarb w22, [x27]
1080 2b4: c87f4d7c ldxp x28, x19, [x11]
1081 2b8: c87fcc5e ldaxp x30, x19, [x2]
1082 2bc: c8220417 stxp w2, x23, x1, [x0]
1083 2c0: c82cb5f0 stlxp w12, x16, x13, [x15]
1084 2c4: 887f55b2 ldxp w18, w21, [x13]
1085 2c8: 887ff90b ldaxp w11, w30, [x8]
1086 2cc: 88382c2d stxp w24, w13, w11, [x1]
1087 2d0: 883aedb5 stlxp w26, w21, w27, [x13]
1088 2d4: f819928b stur x11, [x20, #-103]
1089 2d8: b803e21c stur w28, [x16, #62]
1090 2dc: 381f713b sturb w27, [x9, #-9]
1091 2e0: 781ce322 sturh w2, [x25, #-50]
1092 2e4: f850f044 ldur x4, [x2, #-241]
1093 2e8: b85e129e ldur w30, [x20, #-31]
1094 2ec: 385e92f2 ldurb w18, [x23, #-23]
1095 2f0: 785ff35d ldurh w29, [x26, #-1]
1096 2f4: 39801921 ldrsb x1, [x9, #6]
1097 2f8: 7881318b ldursh x11, [x12, #19]
1098 2fc: 78dce02b ldursh w11, [x1, #-50]
1099 300: b8829313 ldursw x19, [x24, #41]
1100 304: fc45f318 ldur d24, [x24, #95]
1101 308: bc5d50af ldur s15, [x5, #-43]
1102 30c: fc001375 stur d21, [x27, #1]
1103 310: bc1951b7 stur s23, [x13, #-107]
1104 314: f8008ec2 str x2, [x22, #8]!
1105 318: b8181d66 str w6, [x11, #-127]!
1106 31c: 381e0e83 strb w3, [x20, #-32]!
1107 320: 7801dd53 strh w19, [x10, #29]!
1108 324: f85dfca7 ldr x7, [x5, #-33]!
1109 328: b8588ef1 ldr w17, [x23, #-120]!
1110 32c: 385feecc ldrb w12, [x22, #-2]!
1111 330: 785d3d91 ldrh w17, [x12, #-45]!
1112 334: 389f3ea4 ldrsb x4, [x21, #-13]!
1113 338: 789d3dd7 ldrsh x23, [x14, #-45]!
1114 33c: 78c03e68 ldrsh w8, [x19, #3]!
1115 340: b8987fc7 ldrsw x7, [x30, #-121]!
1116 344: fc5e5d07 ldr d7, [x8, #-27]!
1117 348: bc5b7f93 ldr s19, [x28, #-73]!
1118 34c: fc170d92 str d18, [x12, #-144]!
1119 350: bc1dac81 str s1, [x4, #-38]!
1120 354: f8109522 str x2, [x9], #-247
1121 358: b8181755 str w21, [x26], #-127
1122 35c: 381e56db strb w27, [x22], #-27
1123 360: 781cc5b9 strh w25, [x13], #-52
1124 364: f85e1585 ldr x5, [x12], #-31
1125 368: b85f542a ldr w10, [x1], #-11
1126 36c: 3840d5d5 ldrb w21, [x14], #13
1127 370: 785c04de ldrh w30, [x6], #-64
1128 374: 389e458a ldrsb x10, [x12], #-28
1129 378: 789f2409 ldrsh x9, [x0], #-14
1130 37c: 78dc4741 ldrsh w1, [x26], #-60
1131 380: b898f72d ldrsw x13, [x25], #-113
1132 384: fc50f45c ldr d28, [x2], #-241
1133 388: bc5e8530 ldr s16, [x9], #-24
1134 38c: fc126514 str d20, [x8], #-218
1135 390: bc1fc6d5 str s21, [x22], #-4
1136 394: f826ca85 str x5, [x20, w6, sxtw]
1137 398: b831fb22 str w2, [x25, x17, sxtx #2]
1138 39c: 3838faea strb w10, [x23, x24, sxtx #0]
1139 3a0: 78336a46 strh w6, [x18, x19]
1140 3a4: f8747a95 ldr x21, [x20, x20, lsl #3]
1141 3a8: b8786b36 ldr w22, [x25, x24]
1142 3ac: 38685a93 ldrb w19, [x20, w8, uxtw #0]
1143 3b0: 78617806 ldrh w6, [x0, x1, lsl #1]
1144 3b4: 38ab79b0 ldrsb x16, [x13, x11, lsl #0]
1145 3b8: 78b54ada ldrsh x26, [x22, w21, uxtw]
1146 3bc: 78f659e5 ldrsh w5, [x15, w22, uxtw #1]
1147 3c0: b8b56b12 ldrsw x18, [x24, x21]
1148 3c4: fc7868e7 ldr d7, [x7, x24]
1149 3c8: bc76f97e ldr s30, [x11, x22, sxtx #2]
1150 3cc: fc316af6 str d22, [x23, x17]
1151 3d0: bc35c83e str s30, [x1, w21, sxtw]
1152 3d4: f91963ca str x10, [x30, #12992]
1153 3d8: b9190b93 str w19, [x28, #6408]
1154 3dc: 3918b15d strb w29, [x10, #1580]
1155 3e0: 7918c9c5 strh w5, [x14, #3172]
1156 3e4: f959b0a8 ldr x8, [x5, #13152]
1157 3e8: b95fd9b8 ldr w24, [x13, #8152]
1158 3ec: 395dc74c ldrb w12, [x26, #1905]
1159 3f0: 795ae66f ldrh w15, [x19, #3442]
1160 3f4: 39993ecd ldrsb x13, [x22, #1615]
1161 3f8: 799edde7 ldrsh x7, [x15, #3950]
1162 3fc: 79dc0378 ldrsh w24, [x27, #3584]
1163 400: b99a0660 ldrsw x0, [x19, #6660]
1164 404: fd5b0dc1 ldr d1, [x14, #13848]
1165 408: bd5c3f92 ldr s18, [x28, #7228]
1166 40c: fd1a4599 str d25, [x12, #13448]
1167 410: bd196039 str s25, [x1, #6496]
1168 414: 58003351 ldr x17, a7c <forth>
1169 418: 18ffdf47 ldr w7, 0 <back>
1170 41c: f89811c0 prfum pldl1keep, [x14, #-127]
1171 420: d8ffdf00 prfm pldl1keep, 0 <back>
1172 424: f8b66800 prfm pldl1keep, [x0, x22]
1173 428: f99daee0 prfm pldl1keep, [x23, #15192]
1174 42c: 1a0c0311 adc w17, w24, w12
1175 430: 3a050300 adcs w0, w24, w5
1176 434: 5a03016c sbc w12, w11, w3
1177 438: 7a1300aa sbcs w10, w5, w19
1178 43c: 9a0e0014 adc x20, x0, x14
1179 440: ba0f0371 adcs x17, x27, x15
1180 444: da1a0022 sbc x2, x1, x26
1181 448: fa080358 sbcs x24, x26, x8
1182 44c: 0b39e854 add w20, w2, w25, sxtx #2
1183 450: 2b3c4c2e adds w14, w1, w28, uxtw #3
1184 454: cb242d61 sub x1, x11, w4, uxth #3
1185 458: 6b33e785 subs w5, w28, w19, sxtx #1
1186 45c: 8b2eb3b3 add x19, x29, w14, sxth #4
1187 460: ab2824e1 adds x1, x7, w8, uxth #1
1188 464: cb2e3367 sub x7, x27, w14, uxth #4
1189 468: eb3c6411 subs x17, x0, x28, uxtx #1
1190 46c: 3a5eb308 ccmn w24, w30, #0x8, lt // lt = tstop
1191 470: 7a58702c ccmp w1, w24, #0xc, vc
1192 474: ba4b428e ccmn x20, x11, #0xe, mi // mi = first
1193 478: fa476148 ccmp x10, x7, #0x8, vs
1194 47c: 3a5e484a ccmn w2, #0x1e, #0xa, mi // mi = first
1195 480: 7a4749a7 ccmp w13, #0x7, #0x7, mi // mi = first
1196 484: ba528986 ccmn x12, #0x12, #0x6, hi // hi = pmore
1197 488: fa4bdb2e ccmp x25, #0xb, #0xe, le
1198 48c: 1a8e2240 csel w0, w18, w14, cs // cs = hs, nlast
1199 490: 1a98d521 csinc w1, w9, w24, le
1200 494: 5a819363 csinv w3, w27, w1, ls // ls = plast
1201 498: 5a9a45a0 csneg w0, w13, w26, mi // mi = first
1202 49c: 9a9222dc csel x28, x22, x18, cs // cs = hs, nlast
1203 4a0: 9a92d58a csinc x10, x12, x18, le
1204 4a4: da9c31e8 csinv x8, x15, x28, cc // cc = lo, ul, last
1205 4a8: da93a6f3 csneg x19, x23, x19, ge // ge = tcont
1206 4ac: 5ac003a6 rbit w6, w29
1207 4b0: 5ac00645 rev16 w5, w18
1208 4b4: 5ac00a69 rev w9, w19
1209 4b8: 5ac011a9 clz w9, w13
1210 4bc: 5ac01515 cls w21, w8
1211 4c0: dac00156 rbit x22, x10
1212 4c4: dac00664 rev16 x4, x19
1213 4c8: dac009a5 rev32 x5, x13
1214 4cc: dac00c4c rev x12, x2
1215 4d0: dac012b6 clz x22, x21
1216 4d4: dac01618 cls x24, x16
1217 4d8: 1ac608b1 udiv w17, w5, w6
1218 4dc: 1ad90e07 sdiv w7, w16, w25
1219 4e0: 1ad6236b lsl w11, w27, w22
1220 4e4: 1ac32556 lsr w22, w10, w3
1221 4e8: 1acc2b5d asr w29, w26, w12
1222 4ec: 1aca2f7a ror w26, w27, w10
1223 4f0: 9ad5094f udiv x15, x10, x21
1224 4f4: 9ad70fdc sdiv x28, x30, x23
1225 4f8: 9ade2369 lsl x9, x27, x30
1226 4fc: 9acf27aa lsr x10, x29, x15
1227 500: 9ad92bdd asr x29, x30, x25
1228 504: 9ac02c95 ror x21, x4, x0
1229 508: 9bdd7eb2 umulh x18, x21, x29
1230 50c: 9b547eb0 smulh x16, x21, x20
1231 510: 1b1e0e66 madd w6, w19, w30, w3
1232 514: 1b0be275 msub w21, w19, w11, w24
1233 518: 9b193b60 madd x0, x27, x25, x14
1234 51c: 9b129dc3 msub x3, x14, x18, x7
1235 520: 9b3c470f smaddl x15, w24, w28, x17
1236 524: 9b3af059 smsubl x25, w2, w26, x28
1237 528: 9bba6f25 umaddl x5, w25, w26, x27
1238 52c: 9ba6d650 umsubl x16, w18, w6, x21
1239 530: 1e24080c fmul s12, s0, s4
1240 534: 1e311b6c fdiv s12, s27, s17
1241 538: 1e222b9c fadd s28, s28, s2
1242 53c: 1e2f3952 fsub s18, s10, s15
1243 540: 1e2309ce fmul s14, s14, s3
1244 544: 1e7309f9 fmul d25, d15, d19
1245 548: 1e7018ae fdiv d14, d5, d16
1246 54c: 1e792b44 fadd d4, d26, d25
1247 550: 1e623844 fsub d4, d2, d2
1248 554: 1e710bac fmul d12, d29, d17
1249 558: 1f0310e8 fmadd s8, s7, s3, s4
1250 55c: 1f1ae499 fmsub s25, s4, s26, s25
1251 560: 1f206a24 fnmadd s4, s17, s0, s26
1252 564: 1f2f56f1 fnmadd s17, s23, s15, s21
1253 568: 1f5b2a3c fmadd d28, d17, d27, d10
1254 56c: 1f47e403 fmsub d3, d0, d7, d25
1255 570: 1f6f74c9 fnmadd d9, d6, d15, d29
1256 574: 1f62454f fnmadd d15, d10, d2, d17
1257 578: 1e204167 fmov s7, s11
1258 57c: 1e20c2eb fabs s11, s23
1259 580: 1e2143a7 fneg s7, s29
1260 584: 1e21c1d7 fsqrt s23, s14
1261 588: 1e22c17b fcvt d27, s11
1262 58c: 1e60408b fmov d11, d4
1263 590: 1e60c198 fabs d24, d12
1264 594: 1e6141cf fneg d15, d14
1265 598: 1e61c174 fsqrt d20, d11
1266 59c: 1e6241bc fcvt s28, d13
1267 5a0: 1e38018b fcvtzs w11, s12
1268 5a4: 9e3803d7 fcvtzs x23, s30
1269 5a8: 1e7801da fcvtzs w26, d14
1270 5ac: 9e7801a9 fcvtzs x9, d13
1271 5b0: 1e2200ea scvtf s10, w7
1272 5b4: 9e2203a5 scvtf s5, x29
1273 5b8: 1e62006f scvtf d15, w3
1274 5bc: 9e62018b scvtf d11, x12
1275 5c0: 1e2603cf fmov w15, s30
1276 5c4: 9e66023e fmov x30, d17
1277 5c8: 1e270293 fmov s19, w20
1278 5cc: 9e6701ef fmov d15, x15
1279 5d0: 1e352120 fcmp s9, s21
1280 5d4: 1e692040 fcmp d2, d9
1281 5d8: 1e202368 fcmp s27, #0.0
1282 5dc: 1e6020e8 fcmp d7, #0.0
1283 5e0: 2910443e stp w30, w17, [x1, #128]
1284 5e4: 29642866 ldp w6, w10, [x3, #-224]
1285 5e8: 69461c2b ldpsw x11, x7, [x1, #48]
1286 5ec: a9390e40 stp x0, x3, [x18, #-112]
1287 5f0: a94758c6 ldp x6, x22, [x6, #112]
1288 5f4: 29a0685b stp w27, w26, [x2, #-256]!
1289 5f8: 29e87167 ldp w7, w28, [x11, #-192]!
1290 5fc: 69c82eed ldpsw x13, x11, [x23, #64]!
1291 600: a9bf4aa8 stp x8, x18, [x21, #-16]!
1292 604: a9c44e54 ldp x20, x19, [x18, #64]!
1293 608: 28a4591d stp w29, w22, [x8], #-224
1294 60c: 28c25173 ldp w19, w20, [x11], #16
1295 610: 68fc19f4 ldpsw x20, x6, [x15], #-32
1296 614: a8b37063 stp x3, x28, [x3], #-208
1297 618: a8c6394e ldp x14, x14, [x10], #96
1298 61c: 2834454b stnp w11, w17, [x10, #-96]
1299 620: 28481dc7 ldnp w7, w7, [x14, #64]
1300 624: a8075800 stnp x0, x22, [x0, #112]
1301 628: a87a35b7 ldnp x23, x13, [x13, #-96]
1302 62c: 0c4070e2 ld1 {v2.8b}, [x7]
1303 630: 4cdfa12e ld1 {v14.16b, v15.16b}, [x9], #32
1304 634: 0ccc6eb0 ld1 {v16.1d-v18.1d}, [x21], x12
1305 638: 4cdf26d1 ld1 {v17.8h-v20.8h}, [x22], #64
1306 63c: 0d40c0cd ld1r {v13.8b}, [x6]
1307 640: 4ddfca8a ld1r {v10.4s}, [x20], #4
1308 644: 0dc5cea4 ld1r {v4.1d}, [x21], x5
1309 648: 4c408ee6 ld2 {v6.2d, v7.2d}, [x23]
1310 64c: 0cdf874f ld2 {v15.4h, v16.4h}, [x26], #16
1311 650: 4d60c177 ld2r {v23.16b, v24.16b}, [x11]
1312 654: 0dffcae8 ld2r {v8.2s, v9.2s}, [x23], #8
1313 658: 4de6cf33 ld2r {v19.2d, v20.2d}, [x25], x6
1314 65c: 4cc14a3d ld3 {v29.4s-v31.4s}, [x17], x1
1315 660: 0c404af8 ld3 {v24.2s-v26.2s}, [x23]
1316 664: 4d40e4aa ld3r {v10.8h-v12.8h}, [x5]
1317 668: 4ddfe952 ld3r {v18.4s-v20.4s}, [x10], #12
1318 66c: 0dd0edec ld3r {v12.1d-v14.1d}, [x15], x16
1319 670: 4cdf0659 ld4 {v25.8h-v28.8h}, [x18], #64
1320 674: 0cc803c1 ld4 {v1.8b-v4.8b}, [x30], x8
1321 678: 0d60e250 ld4r {v16.8b-v19.8b}, [x18]
1322 67c: 0dffe599 ld4r {v25.4h-v28.4h}, [x12], #8
1323 680: 0de8ea7a ld4r {v26.2s-v29.2s}, [x19], x8
1324 684: 0e31bad5 addv b21, v22.8b
1325 688: 4e31b8a4 addv b4, v5.16b
1326 68c: 0e71ba72 addv h18, v19.4h
1327 690: 4e71bb38 addv h24, v25.8h
1328 694: 4eb1b9ac addv s12, v13.4s
1329 698: 0e30aa72 smaxv b18, v19.8b
1330 69c: 4e30a907 smaxv b7, v8.16b
1331 6a0: 0e70a949 smaxv h9, v10.4h
1332 6a4: 4e70ab59 smaxv h25, v26.8h
1333 6a8: 4eb0aa0f smaxv s15, v16.4s
1334 6ac: 6e30f9cd fmaxv s13, v14.4s
1335 6b0: 0e31a883 sminv b3, v4.8b
1336 6b4: 4e31a98b sminv b11, v12.16b
1337 6b8: 0e71aa30 sminv h16, v17.4h
1338 6bc: 4e71a907 sminv h7, v8.8h
1339 6c0: 4eb1ab59 sminv s25, v26.4s
1340 6c4: 6eb0f98b fminv s11, v12.4s
1341 6c8: 0e20b907 abs v7.8b, v8.8b
1342 6cc: 4e20b949 abs v9.16b, v10.16b
1343 6d0: 0e60bb59 abs v25.4h, v26.4h
1344 6d4: 4e60bbbc abs v28.8h, v29.8h
1345 6d8: 0ea0bbdd abs v29.2s, v30.2s
1346 6dc: 4ea0b820 abs v0.4s, v1.4s
1347 6e0: 4ee0bb17 abs v23.2d, v24.2d
1348 6e4: 0ea0fa30 fabs v16.2s, v17.2s
1349 6e8: 4ea0f883 fabs v3.4s, v4.4s
1350 6ec: 4ee0f907 fabs v7.2d, v8.2d
1351 6f0: 2ea0f928 fneg v8.2s, v9.2s
1352 6f4: 6ea0f9ac fneg v12.4s, v13.4s
1353 6f8: 6ee0f9ee fneg v14.2d, v15.2d
1354 6fc: 2ea1fbdd fsqrt v29.2s, v30.2s
1355 700: 6ea1f841 fsqrt v1.4s, v2.4s
1356 704: 6ee1fad5 fsqrt v21.2d, v22.2d
1357 708: 2e205b7a mvn v26.8b, v27.8b
1358 70c: 6e20598b mvn v11.16b, v12.16b
1359 710: 0e291d07 and v7.8b, v8.8b, v9.8b
1360 714: 4e281ce6 and v6.16b, v7.16b, v8.16b
1361 718: 0eab1d49 orr v9.8b, v10.8b, v11.8b
1362 71c: 4ea61ca4 orr v4.16b, v5.16b, v6.16b
1363 720: 2e331e51 eor v17.8b, v18.8b, v19.8b
1364 724: 6e291d07 eor v7.16b, v8.16b, v9.16b
1365 728: 0e228420 add v0.8b, v1.8b, v2.8b
1366 72c: 4e298507 add v7.16b, v8.16b, v9.16b
1367 730: 0e7b8759 add v25.4h, v26.4h, v27.4h
1368 734: 4e6e85ac add v12.8h, v13.8h, v14.8h
1369 738: 0ebd879b add v27.2s, v28.2s, v29.2s
1370 73c: 4ebf87dd add v29.4s, v30.4s, v31.4s
1371 740: 4ee98507 add v7.2d, v8.2d, v9.2d
1372 744: 0e33d651 fadd v17.2s, v18.2s, v19.2s
1373 748: 4e3dd79b fadd v27.4s, v28.4s, v29.4s
1374 74c: 4e74d672 fadd v18.2d, v19.2d, v20.2d
1375 750: 2e2784c5 sub v5.8b, v6.8b, v7.8b
1376 754: 6e298507 sub v7.16b, v8.16b, v9.16b
1377 758: 2e6087fe sub v30.4h, v31.4h, v0.4h
1378 75c: 6e6b8549 sub v9.8h, v10.8h, v11.8h
1379 760: 2ebc877a sub v26.2s, v27.2s, v28.2s
1380 764: 6eba8738 sub v24.4s, v25.4s, v26.4s
1381 768: 6ef98717 sub v23.2d, v24.2d, v25.2d
1382 76c: 0eb8d6f6 fsub v22.2s, v23.2s, v24.2s
1383 770: 4ebad738 fsub v24.4s, v25.4s, v26.4s
1384 774: 4efcd77a fsub v26.2d, v27.2d, v28.2d
1385 778: 0e239c41 mul v1.8b, v2.8b, v3.8b
1386 77c: 4e279cc5 mul v5.16b, v6.16b, v7.16b
1387 780: 0e719e0f mul v15.4h, v16.4h, v17.4h
1388 784: 4e689ce6 mul v6.8h, v7.8h, v8.8h
1389 788: 0eb29e30 mul v16.2s, v17.2s, v18.2s
1390 78c: 4eb19e0f mul v15.4s, v16.4s, v17.4s
1391 790: 2e25dc83 fmul v3.2s, v4.2s, v5.2s
1392 794: 6e24dc62 fmul v2.4s, v3.4s, v4.4s
1393 798: 6e62dc20 fmul v0.2d, v1.2d, v2.2d
1394 79c: 0e7b9759 mla v25.4h, v26.4h, v27.4h
1395 7a0: 4e649462 mla v2.8h, v3.8h, v4.8h
1396 7a4: 0ebf97dd mla v29.2s, v30.2s, v31.2s
1397 7a8: 4ea097fe mla v30.4s, v31.4s, v0.4s
1398 7ac: 0e39cf17 fmla v23.2s, v24.2s, v25.2s
1399 7b0: 4e2fcdcd fmla v13.4s, v14.4s, v15.4s
1400 7b4: 4e6acd28 fmla v8.2d, v9.2d, v10.2d
1401 7b8: 2e6e95ac mls v12.4h, v13.4h, v14.4h
1402 7bc: 6e6c956a mls v10.8h, v11.8h, v12.8h
1403 7c0: 2eae95ac mls v12.2s, v13.2s, v14.2s
1404 7c4: 6eb896f6 mls v22.4s, v23.4s, v24.4s
1405 7c8: 0ebdcf9b fmls v27.2s, v28.2s, v29.2s
1406 7cc: 4ea6cca4 fmls v4.4s, v5.4s, v6.4s
1407 7d0: 4ee9cd07 fmls v7.2d, v8.2d, v9.2d
1408 7d4: 2e28fce6 fdiv v6.2s, v7.2s, v8.2s
1409 7d8: 6e23fc41 fdiv v1.4s, v2.4s, v3.4s
1410 7dc: 6e7cff7a fdiv v26.2d, v27.2d, v28.2d
1411 7e0: 0e31660f smax v15.8b, v16.8b, v17.8b
1412 7e4: 4e246462 smax v2.16b, v3.16b, v4.16b
1413 7e8: 0e6f65cd smax v13.4h, v14.4h, v15.4h
1414 7ec: 4e6f65cd smax v13.8h, v14.8h, v15.8h
1415 7f0: 0eba6738 smax v24.2s, v25.2s, v26.2s
1416 7f4: 4eb96717 smax v23.4s, v24.4s, v25.4s
1417 7f8: 0e26f4a4 fmax v4.2s, v5.2s, v6.2s
1418 7fc: 4e35f693 fmax v19.4s, v20.4s, v21.4s
1419 800: 4e71f60f fmax v15.2d, v16.2d, v17.2d
1420 804: 0e226c20 smin v0.8b, v1.8b, v2.8b
1421 808: 4e266ca4 smin v4.16b, v5.16b, v6.16b
1422 80c: 0e766eb4 smin v20.4h, v21.4h, v22.4h
1423 810: 4e6d6d8b smin v11.8h, v12.8h, v13.8h
1424 814: 0ebf6fdd smin v29.2s, v30.2s, v31.2s
1425 818: 4eb16e0f smin v15.4s, v16.4s, v17.4s
1426 81c: 0eb7f6d5 fmin v21.2s, v22.2s, v23.2s
1427 820: 4ea6f4a4 fmin v4.4s, v5.4s, v6.4s
1428 824: 4ef0f5ee fmin v14.2d, v15.2d, v16.2d
1429 828: 2e388ef6 cmeq v22.8b, v23.8b, v24.8b
1430 82c: 6e3b8f59 cmeq v25.16b, v26.16b, v27.16b
1431 830: 2e688ce6 cmeq v6.4h, v7.4h, v8.4h
1432 834: 6e6e8dac cmeq v12.8h, v13.8h, v14.8h
1433 838: 2eb08dee cmeq v14.2s, v15.2s, v16.2s
1434 83c: 6eaf8dcd cmeq v13.4s, v14.4s, v15.4s
1435 840: 6ef08dee cmeq v14.2d, v15.2d, v16.2d
1436 844: 0e2be549 fcmeq v9.2s, v10.2s, v11.2s
1437 848: 4e3be759 fcmeq v25.4s, v26.4s, v27.4s
1438 84c: 4e7ee7bc fcmeq v28.2d, v29.2d, v30.2d
1439 850: 0e2c356a cmgt v10.8b, v11.8b, v12.8b
1440 854: 4e353693 cmgt v19.16b, v20.16b, v21.16b
1441 858: 0e6d358b cmgt v11.4h, v12.4h, v13.4h
1442 85c: 4e733651 cmgt v17.8h, v18.8h, v19.8h
1443 860: 0eb736d5 cmgt v21.2s, v22.2s, v23.2s
1444 864: 4eb1360f cmgt v15.4s, v16.4s, v17.4s
1445 868: 4ef636b4 cmgt v20.2d, v21.2d, v22.2d
1446 86c: 2eb9e717 fcmgt v23.2s, v24.2s, v25.2s
1447 870: 6ebce77a fcmgt v26.4s, v27.4s, v28.4s
1448 874: 6ee7e4c5 fcmgt v5.2d, v6.2d, v7.2d
1449 878: 0e283ce6 cmge v6.8b, v7.8b, v8.8b
1450 87c: 4e313e0f cmge v15.16b, v16.16b, v17.16b
1451 880: 0e713e0f cmge v15.4h, v16.4h, v17.4h
1452 884: 4e7b3f59 cmge v25.8h, v26.8h, v27.8h
1453 888: 0eb23e30 cmge v16.2s, v17.2s, v18.2s
1454 88c: 4ebd3f9b cmge v27.4s, v28.4s, v29.4s
1455 890: 4efa3f38 cmge v24.2d, v25.2d, v26.2d
1456 894: 2e31e60f fcmge v15.2s, v16.2s, v17.2s
1457 898: 6e3be759 fcmge v25.4s, v26.4s, v27.4s
1458 89c: 6e70e5ee fcmge v14.2d, v15.2d, v16.2d
1459 8a0: ba5fd3e3 ccmn xzr, xzr, #0x3, le
1460 8a4: 3a5f03e5 ccmn wzr, wzr, #0x5, eq // eq = none
1461 8a8: fa411be4 ccmp xzr, #0x1, #0x4, ne // ne = any
1462 8ac: 7a42cbe2 ccmp wzr, #0x2, #0x2, gt
1463 8b0: 93df03ff ror xzr, xzr, #0
1464 8b4: c820ffff stlxp w0, xzr, xzr, [sp]
1465 8b8: 8822fc7f stlxp w2, wzr, wzr, [x3]
1466 8bc: c8247cbf stxp w4, xzr, xzr, [x5]
1467 8c0: 88267fff stxp w6, wzr, wzr, [sp]
1468 8c4: 4e010fe0 dup v0.16b, wzr
1469 8c8: 4e081fe1 mov v1.d[0], xzr
1470 8cc: 4e0c1fe1 mov v1.s[1], wzr
1471 8d0: 4e0a1fe1 mov v1.h[2], wzr
1472 8d4: 4e071fe1 mov v1.b[3], wzr
1473 8d8: 4cc0ac3f ld1 {v31.2d, v0.2d}, [x1], x0
1474 8dc: 1e601000 fmov d0, #2.000000000000000000e+00
1475 8e0: 1e603000 fmov d0, #2.125000000000000000e+00
1476 8e4: 1e621000 fmov d0, #4.000000000000000000e+00
1477 8e8: 1e623000 fmov d0, #4.250000000000000000e+00
1478 8ec: 1e641000 fmov d0, #8.000000000000000000e+00
1479 8f0: 1e643000 fmov d0, #8.500000000000000000e+00
1480 8f4: 1e661000 fmov d0, #1.600000000000000000e+01
1481 8f8: 1e663000 fmov d0, #1.700000000000000000e+01
1482 8fc: 1e681000 fmov d0, #1.250000000000000000e-01
1483 900: 1e683000 fmov d0, #1.328125000000000000e-01
1484 904: 1e6a1000 fmov d0, #2.500000000000000000e-01
1485 908: 1e6a3000 fmov d0, #2.656250000000000000e-01
1486 90c: 1e6c1000 fmov d0, #5.000000000000000000e-01
1487 910: 1e6c3000 fmov d0, #5.312500000000000000e-01
1488 914: 1e6e1000 fmov d0, #1.000000000000000000e+00
1489 918: 1e6e3000 fmov d0, #1.062500000000000000e+00
1490 91c: 1e701000 fmov d0, #-2.000000000000000000e+00
1491 920: 1e703000 fmov d0, #-2.125000000000000000e+00
1492 924: 1e721000 fmov d0, #-4.000000000000000000e+00
1493 928: 1e723000 fmov d0, #-4.250000000000000000e+00
1494 92c: 1e741000 fmov d0, #-8.000000000000000000e+00
1495 930: 1e743000 fmov d0, #-8.500000000000000000e+00
1496 934: 1e761000 fmov d0, #-1.600000000000000000e+01
1497 938: 1e763000 fmov d0, #-1.700000000000000000e+01
1498 93c: 1e781000 fmov d0, #-1.250000000000000000e-01
1499 940: 1e783000 fmov d0, #-1.328125000000000000e-01
1500 944: 1e7a1000 fmov d0, #-2.500000000000000000e-01
1501 948: 1e7a3000 fmov d0, #-2.656250000000000000e-01
1502 94c: 1e7c1000 fmov d0, #-5.000000000000000000e-01
1503 950: 1e7c3000 fmov d0, #-5.312500000000000000e-01
1504 954: 1e7e1000 fmov d0, #-1.000000000000000000e+00
1505 958: 1e7e3000 fmov d0, #-1.062500000000000000e+00
1506 95c: f82a81cd swp x10, x13, [x14]
1507 960: f83402e1 ldadd x20, x1, [x23]
1508 964: f83e104e ldclr x30, x14, [x2]
1509 968: f8262103 ldeor x6, x3, [x8]
1510 96c: f8393360 ldset x25, x0, [x27]
1511 970: f83e50a5 ldsmin x30, x5, [x5]
1512 974: f83e432b ldsmax x30, x11, [x25]
1513 978: f820701f stumin x0, [x0]
1514 97c: f833635d ldumax x19, x29, [x26]
1515 980: f8a9819a swpa x9, x26, [x12]
1516 984: f8af016b ldadda x15, x11, [x11]
1517 988: f8b212d9 ldclra x18, x25, [x22]
1518 98c: f8b82220 ldeora x24, x0, [x17]
1519 990: f8ab33a6 ldseta x11, x6, [x29]
1520 994: f8a650a5 ldsmina x6, x5, [x5]
1521 998: f8b54213 ldsmaxa x21, x19, [x16]
1522 99c: f8b2737e ldumina x18, x30, [x27]
1523 9a0: f8bc6381 ldumaxa x28, x1, [x28]
1524 9a4: f8e183b4 swpal x1, x20, [x29]
1525 9a8: f8f0014d ldaddal x16, x13, [x10]
1526 9ac: f8fd127d ldclral x29, x29, [x19]
1527 9b0: f8f6208a ldeoral x22, x10, [x4]
1528 9b4: f8ff3115 ldsetal xzr, x21, [x8]
1529 9b8: f8ff5153 ldsminal xzr, x19, [x10]
1530 9bc: f8fc4322 ldsmaxal x28, x2, [x25]
1531 9c0: f8e57103 lduminal x5, x3, [x8]
1532 9c4: f8f661b3 ldumaxal x22, x19, [x13]
1533 9c8: f865831d swpl x5, x29, [x24]
1534 9cc: f875031a ldaddl x21, x26, [x24]
1535 9d0: f8631358 ldclrl x3, x24, [x26]
1536 9d4: f87722af ldeorl x23, x15, [x21]
1537 9d8: f8633118 ldsetl x3, x24, [x8]
1538 9dc: f8795214 ldsminl x25, x20, [x16]
1539 9e0: f8714022 ldsmaxl x17, x2, [x1]
1540 9e4: f8607098 lduminl x0, x24, [x4]
1541 9e8: f86363ec ldumaxl x3, x12, [sp]
1542 9ec: b83c834a swp w28, w10, [x26]
1543 9f0: b822024c ldadd w2, w12, [x18]
1544 9f4: b83f11a1 ldclr wzr, w1, [x13]
1545 9f8: b83d2260 ldeor w29, w0, [x19]
1546 9fc: b82c32d1 ldset w12, w17, [x22]
1547 a00: b82d53dc ldsmin w13, w28, [x30]
1548 a04: b83f4341 ldsmax wzr, w1, [x26]
1549 a08: b83c73c4 ldumin w28, w4, [x30]
1550 a0c: b82463c6 ldumax w4, w6, [x30]
1551 a10: b8ba8132 swpa w26, w18, [x9]
1552 a14: b8a8000c ldadda w8, w12, [x0]
1553 a18: b8b41301 ldclra w20, w1, [x24]
1554 a1c: b8a22120 ldeora w2, w0, [x9]
1555 a20: b8b8321a ldseta w24, w26, [x16]
1556 a24: b8be5143 ldsmina w30, w3, [x10]
1557 a28: b8b7408a ldsmaxa w23, w10, [x4]
1558 a2c: b8b27162 ldumina w18, w2, [x11]
1559 a30: b8a861ea ldumaxa w8, w10, [x15]
1560 a34: b8f18142 swpal w17, w2, [x10]
1561 a38: b8ec01ec ldaddal w12, w12, [x15]
1562 a3c: b8ed10e2 ldclral w13, w2, [x7]
1563 a40: b8f4221a ldeoral w20, w26, [x16]
1564 a44: b8e43082 ldsetal w4, w2, [x4]
1565 a48: b8ec52b2 ldsminal w12, w18, [x21]
1566 a4c: b8f04172 ldsmaxal w16, w18, [x11]
1567 a50: b8f57197 lduminal w21, w23, [x12]
1568 a54: b8fa6397 ldumaxal w26, w23, [x28]
1569 a58: b86e830b swpl w14, w11, [x24]
1570 a5c: b86103ec ldaddl w1, w12, [sp]
1571 a60: b86a10f0 ldclrl w10, w16, [x7]
1572 a64: b86221a3 ldeorl w2, w3, [x13]
1573 a68: b8733211 ldsetl w19, w17, [x16]
1574 a6c: b8635161 ldsminl w3, w1, [x11]
1575 a70: b87e4105 ldsmaxl w30, w5, [x8]
1576 a74: b86f73dd lduminl w15, w29, [x30]
1577 a78: b86060f4 ldumaxl w0, w20, [x7]
1578
1579 */
1580
1581 static const unsigned int insns[] =
1582 {
1583 0x8b0d82fa, 0xcb49970c, 0xab889dfc, 0xeb9ee787,
1584 0x0b9b3ec9, 0x4b9279a3, 0x2b88474e, 0x6b8c56c0,
1585 0x8a1a51e0, 0xaa11f4ba, 0xca0281b8, 0xea918c7c,
1586 0x0a5d4a19, 0x2a4b264d, 0x4a523ca5, 0x6a9b6ae2,
1587 0x8a70b79b, 0xaaba9728, 0xca6dfe3d, 0xea627f1c,
1588 0x0aa70f53, 0x2aaa0f06, 0x4a6176a4, 0x6a604eb0,
1589 0x1105ed91, 0x3100583e, 0x5101f8bd, 0x710f0306,
1590 0x9101a1a0, 0xb10a5cc8, 0xd10810aa, 0xf10fd061,
1591 0x120cb166, 0x321764bc, 0x52174681, 0x720c0247,
1592 0x9241018e, 0xb25a2969, 0xd278b411, 0xf26aad01,
1593 0x14000000, 0x17ffffd7, 0x14000275, 0x94000000,
1594 0x97ffffd4, 0x94000272, 0x3400000a, 0x34fffa2a,
1595 0x34004dea, 0x35000008, 0x35fff9c8, 0x35004d88,
1596 0xb400000b, 0xb4fff96b, 0xb4004d2b, 0xb500001d,
1597 0xb5fff91d, 0xb5004cdd, 0x10000013, 0x10fff8b3,
1598 0x10004c73, 0x90000013, 0x36300016, 0x3637f836,
1599 0x36304bf6, 0x3758000c, 0x375ff7cc, 0x37584b8c,
1600 0x128313a0, 0x528a32c7, 0x7289173b, 0x92ab3acc,
1601 0xd2a0bf94, 0xf2c285e8, 0x9358722f, 0x330e652f,
1602 0x53067f3b, 0x93577c53, 0xb34a1aac, 0xd35a4016,
1603 0x13946c63, 0x93c3dbc8, 0x54000000, 0x54fff5a0,
1604 0x54004960, 0x54000001, 0x54fff541, 0x54004901,
1605 0x54000002, 0x54fff4e2, 0x540048a2, 0x54000002,
1606 0x54fff482, 0x54004842, 0x54000003, 0x54fff423,
1607 0x540047e3, 0x54000003, 0x54fff3c3, 0x54004783,
1608 0x54000004, 0x54fff364, 0x54004724, 0x54000005,
1609 0x54fff305, 0x540046c5, 0x54000006, 0x54fff2a6,
1610 0x54004666, 0x54000007, 0x54fff247, 0x54004607,
1611 0x54000008, 0x54fff1e8, 0x540045a8, 0x54000009,
1612 0x54fff189, 0x54004549, 0x5400000a, 0x54fff12a,
1613 0x540044ea, 0x5400000b, 0x54fff0cb, 0x5400448b,
1614 0x5400000c, 0x54fff06c, 0x5400442c, 0x5400000d,
1615 0x54fff00d, 0x540043cd, 0x5400000e, 0x54ffefae,
1616 0x5400436e, 0x5400000f, 0x54ffef4f, 0x5400430f,
1617 0xd40658e1, 0xd4014d22, 0xd4046543, 0xd4273f60,
1618 0xd44cad80, 0xd503201f, 0xd69f03e0, 0xd6bf03e0,
1619 0xd5033fdf, 0xd5033e9f, 0xd50332bf, 0xd61f0200,
1620 0xd63f0280, 0xc80a7d1b, 0xc800fea1, 0xc85f7fb1,
1621 0xc85fff9d, 0xc89ffee1, 0xc8dffe95, 0x88167e7b,
1622 0x880bfcd0, 0x885f7c12, 0x885ffd44, 0x889ffed8,
1623 0x88dffe6a, 0x48017fc5, 0x4808fe2c, 0x485f7dc9,
1624 0x485ffc27, 0x489ffe05, 0x48dffd82, 0x080a7c6c,
1625 0x081cff4e, 0x085f7d5e, 0x085ffeae, 0x089ffd2d,
1626 0x08dfff76, 0xc87f4d7c, 0xc87fcc5e, 0xc8220417,
1627 0xc82cb5f0, 0x887f55b2, 0x887ff90b, 0x88382c2d,
1628 0x883aedb5, 0xf819928b, 0xb803e21c, 0x381f713b,
1629 0x781ce322, 0xf850f044, 0xb85e129e, 0x385e92f2,
1630 0x785ff35d, 0x39801921, 0x7881318b, 0x78dce02b,
1631 0xb8829313, 0xfc45f318, 0xbc5d50af, 0xfc001375,
1632 0xbc1951b7, 0xf8008ec2, 0xb8181d66, 0x381e0e83,
1633 0x7801dd53, 0xf85dfca7, 0xb8588ef1, 0x385feecc,
1634 0x785d3d91, 0x389f3ea4, 0x789d3dd7, 0x78c03e68,
1635 0xb8987fc7, 0xfc5e5d07, 0xbc5b7f93, 0xfc170d92,
1636 0xbc1dac81, 0xf8109522, 0xb8181755, 0x381e56db,
1637 0x781cc5b9, 0xf85e1585, 0xb85f542a, 0x3840d5d5,
1638 0x785c04de, 0x389e458a, 0x789f2409, 0x78dc4741,
1639 0xb898f72d, 0xfc50f45c, 0xbc5e8530, 0xfc126514,
1640 0xbc1fc6d5, 0xf826ca85, 0xb831fb22, 0x3838faea,
1641 0x78336a46, 0xf8747a95, 0xb8786b36, 0x38685a93,
1642 0x78617806, 0x38ab79b0, 0x78b54ada, 0x78f659e5,
1643 0xb8b56b12, 0xfc7868e7, 0xbc76f97e, 0xfc316af6,
1644 0xbc35c83e, 0xf91963ca, 0xb9190b93, 0x3918b15d,
1645 0x7918c9c5, 0xf959b0a8, 0xb95fd9b8, 0x395dc74c,
1646 0x795ae66f, 0x39993ecd, 0x799edde7, 0x79dc0378,
1647 0xb99a0660, 0xfd5b0dc1, 0xbd5c3f92, 0xfd1a4599,
1648 0xbd196039, 0x58003351, 0x18ffdf47, 0xf89811c0,
1649 0xd8ffdf00, 0xf8b66800, 0xf99daee0, 0x1a0c0311,
1650 0x3a050300, 0x5a03016c, 0x7a1300aa, 0x9a0e0014,
1651 0xba0f0371, 0xda1a0022, 0xfa080358, 0x0b39e854,
1652 0x2b3c4c2e, 0xcb242d61, 0x6b33e785, 0x8b2eb3b3,
1653 0xab2824e1, 0xcb2e3367, 0xeb3c6411, 0x3a5eb308,
1654 0x7a58702c, 0xba4b428e, 0xfa476148, 0x3a5e484a,
1655 0x7a4749a7, 0xba528986, 0xfa4bdb2e, 0x1a8e2240,
1656 0x1a98d521, 0x5a819363, 0x5a9a45a0, 0x9a9222dc,
1657 0x9a92d58a, 0xda9c31e8, 0xda93a6f3, 0x5ac003a6,
1658 0x5ac00645, 0x5ac00a69, 0x5ac011a9, 0x5ac01515,
1659 0xdac00156, 0xdac00664, 0xdac009a5, 0xdac00c4c,
1660 0xdac012b6, 0xdac01618, 0x1ac608b1, 0x1ad90e07,
1661 0x1ad6236b, 0x1ac32556, 0x1acc2b5d, 0x1aca2f7a,
1662 0x9ad5094f, 0x9ad70fdc, 0x9ade2369, 0x9acf27aa,
1663 0x9ad92bdd, 0x9ac02c95, 0x9bdd7eb2, 0x9b547eb0,
1664 0x1b1e0e66, 0x1b0be275, 0x9b193b60, 0x9b129dc3,
1665 0x9b3c470f, 0x9b3af059, 0x9bba6f25, 0x9ba6d650,
1666 0x1e24080c, 0x1e311b6c, 0x1e222b9c, 0x1e2f3952,
1667 0x1e2309ce, 0x1e7309f9, 0x1e7018ae, 0x1e792b44,
1668 0x1e623844, 0x1e710bac, 0x1f0310e8, 0x1f1ae499,
1669 0x1f206a24, 0x1f2f56f1, 0x1f5b2a3c, 0x1f47e403,
1670 0x1f6f74c9, 0x1f62454f, 0x1e204167, 0x1e20c2eb,
1671 0x1e2143a7, 0x1e21c1d7, 0x1e22c17b, 0x1e60408b,
1672 0x1e60c198, 0x1e6141cf, 0x1e61c174, 0x1e6241bc,
1673 0x1e38018b, 0x9e3803d7, 0x1e7801da, 0x9e7801a9,
1674 0x1e2200ea, 0x9e2203a5, 0x1e62006f, 0x9e62018b,
1675 0x1e2603cf, 0x9e66023e, 0x1e270293, 0x9e6701ef,
1676 0x1e352120, 0x1e692040, 0x1e202368, 0x1e6020e8,
1677 0x2910443e, 0x29642866, 0x69461c2b, 0xa9390e40,
1678 0xa94758c6, 0x29a0685b, 0x29e87167, 0x69c82eed,
1679 0xa9bf4aa8, 0xa9c44e54, 0x28a4591d, 0x28c25173,
1680 0x68fc19f4, 0xa8b37063, 0xa8c6394e, 0x2834454b,
1681 0x28481dc7, 0xa8075800, 0xa87a35b7, 0x0c4070e2,
1682 0x4cdfa12e, 0x0ccc6eb0, 0x4cdf26d1, 0x0d40c0cd,
1683 0x4ddfca8a, 0x0dc5cea4, 0x4c408ee6, 0x0cdf874f,
1684 0x4d60c177, 0x0dffcae8, 0x4de6cf33, 0x4cc14a3d,
1685 0x0c404af8, 0x4d40e4aa, 0x4ddfe952, 0x0dd0edec,
1686 0x4cdf0659, 0x0cc803c1, 0x0d60e250, 0x0dffe599,
1687 0x0de8ea7a, 0x0e31bad5, 0x4e31b8a4, 0x0e71ba72,
1688 0x4e71bb38, 0x4eb1b9ac, 0x0e30aa72, 0x4e30a907,
1689 0x0e70a949, 0x4e70ab59, 0x4eb0aa0f, 0x6e30f9cd,
1690 0x0e31a883, 0x4e31a98b, 0x0e71aa30, 0x4e71a907,
1691 0x4eb1ab59, 0x6eb0f98b, 0x0e20b907, 0x4e20b949,
1692 0x0e60bb59, 0x4e60bbbc, 0x0ea0bbdd, 0x4ea0b820,
1693 0x4ee0bb17, 0x0ea0fa30, 0x4ea0f883, 0x4ee0f907,
1694 0x2ea0f928, 0x6ea0f9ac, 0x6ee0f9ee, 0x2ea1fbdd,
1695 0x6ea1f841, 0x6ee1fad5, 0x2e205b7a, 0x6e20598b,
1696 0x0e291d07, 0x4e281ce6, 0x0eab1d49, 0x4ea61ca4,
1697 0x2e331e51, 0x6e291d07, 0x0e228420, 0x4e298507,
1698 0x0e7b8759, 0x4e6e85ac, 0x0ebd879b, 0x4ebf87dd,
1699 0x4ee98507, 0x0e33d651, 0x4e3dd79b, 0x4e74d672,
1700 0x2e2784c5, 0x6e298507, 0x2e6087fe, 0x6e6b8549,
1701 0x2ebc877a, 0x6eba8738, 0x6ef98717, 0x0eb8d6f6,
1702 0x4ebad738, 0x4efcd77a, 0x0e239c41, 0x4e279cc5,
1703 0x0e719e0f, 0x4e689ce6, 0x0eb29e30, 0x4eb19e0f,
1704 0x2e25dc83, 0x6e24dc62, 0x6e62dc20, 0x0e7b9759,
1705 0x4e649462, 0x0ebf97dd, 0x4ea097fe, 0x0e39cf17,
1706 0x4e2fcdcd, 0x4e6acd28, 0x2e6e95ac, 0x6e6c956a,
1707 0x2eae95ac, 0x6eb896f6, 0x0ebdcf9b, 0x4ea6cca4,
1708 0x4ee9cd07, 0x2e28fce6, 0x6e23fc41, 0x6e7cff7a,
1709 0x0e31660f, 0x4e246462, 0x0e6f65cd, 0x4e6f65cd,
1710 0x0eba6738, 0x4eb96717, 0x0e26f4a4, 0x4e35f693,
1711 0x4e71f60f, 0x0e226c20, 0x4e266ca4, 0x0e766eb4,
1712 0x4e6d6d8b, 0x0ebf6fdd, 0x4eb16e0f, 0x0eb7f6d5,
1713 0x4ea6f4a4, 0x4ef0f5ee, 0x2e388ef6, 0x6e3b8f59,
1714 0x2e688ce6, 0x6e6e8dac, 0x2eb08dee, 0x6eaf8dcd,
1715 0x6ef08dee, 0x0e2be549, 0x4e3be759, 0x4e7ee7bc,
1716 0x0e2c356a, 0x4e353693, 0x0e6d358b, 0x4e733651,
1717 0x0eb736d5, 0x4eb1360f, 0x4ef636b4, 0x2eb9e717,
1718 0x6ebce77a, 0x6ee7e4c5, 0x0e283ce6, 0x4e313e0f,
1719 0x0e713e0f, 0x4e7b3f59, 0x0eb23e30, 0x4ebd3f9b,
1720 0x4efa3f38, 0x2e31e60f, 0x6e3be759, 0x6e70e5ee,
1721 0xba5fd3e3, 0x3a5f03e5, 0xfa411be4, 0x7a42cbe2,
1722 0x93df03ff, 0xc820ffff, 0x8822fc7f, 0xc8247cbf,
1723 0x88267fff, 0x4e010fe0, 0x4e081fe1, 0x4e0c1fe1,
1724 0x4e0a1fe1, 0x4e071fe1, 0x4cc0ac3f, 0x1e601000,
1725 0x1e603000, 0x1e621000, 0x1e623000, 0x1e641000,
1726 0x1e643000, 0x1e661000, 0x1e663000, 0x1e681000,
1727 0x1e683000, 0x1e6a1000, 0x1e6a3000, 0x1e6c1000,
1728 0x1e6c3000, 0x1e6e1000, 0x1e6e3000, 0x1e701000,
1729 0x1e703000, 0x1e721000, 0x1e723000, 0x1e741000,
1730 0x1e743000, 0x1e761000, 0x1e763000, 0x1e781000,
1731 0x1e783000, 0x1e7a1000, 0x1e7a3000, 0x1e7c1000,
1732 0x1e7c3000, 0x1e7e1000, 0x1e7e3000, 0xf82a81cd,
1733 0xf83402e1, 0xf83e104e, 0xf8262103, 0xf8393360,
1734 0xf83e50a5, 0xf83e432b, 0xf820701f, 0xf833635d,
1735 0xf8a9819a, 0xf8af016b, 0xf8b212d9, 0xf8b82220,
1736 0xf8ab33a6, 0xf8a650a5, 0xf8b54213, 0xf8b2737e,
1737 0xf8bc6381, 0xf8e183b4, 0xf8f0014d, 0xf8fd127d,
1738 0xf8f6208a, 0xf8ff3115, 0xf8ff5153, 0xf8fc4322,
1739 0xf8e57103, 0xf8f661b3, 0xf865831d, 0xf875031a,
1740 0xf8631358, 0xf87722af, 0xf8633118, 0xf8795214,
1741 0xf8714022, 0xf8607098, 0xf86363ec, 0xb83c834a,
1742 0xb822024c, 0xb83f11a1, 0xb83d2260, 0xb82c32d1,
1743 0xb82d53dc, 0xb83f4341, 0xb83c73c4, 0xb82463c6,
1744 0xb8ba8132, 0xb8a8000c, 0xb8b41301, 0xb8a22120,
1745 0xb8b8321a, 0xb8be5143, 0xb8b7408a, 0xb8b27162,
1746 0xb8a861ea, 0xb8f18142, 0xb8ec01ec, 0xb8ed10e2,
1747 0xb8f4221a, 0xb8e43082, 0xb8ec52b2, 0xb8f04172,
1748 0xb8f57197, 0xb8fa6397, 0xb86e830b, 0xb86103ec,
1749 0xb86a10f0, 0xb86221a3, 0xb8733211, 0xb8635161,
1750 0xb87e4105, 0xb86f73dd, 0xb86060f4,
1751 };
1752 // END Generated code -- do not edit
1753
1754 asm_check((unsigned int *)entry, insns, sizeof insns / sizeof insns[0]);
1755
1756 {
1757 address PC = __ pc();
1758 __ ld1(v0, __ T16B, Address(r16)); // No offset
1759 __ ld1(v0, __ T8H, __ post(r16, 16)); // Post-index
1760 __ ld2(v0, v1, __ T8H, __ post(r24, 16 * 2)); // Post-index
1761 __ ld1(v0, __ T16B, __ post(r16, r17)); // Register post-index
1762 static const unsigned int vector_insns[] = {
1763 0x4c407200, // ld1 {v0.16b}, [x16]
1764 0x4cdf7600, // ld1 {v0.8h}, [x16], #16
1765 0x4cdf8700, // ld2 {v0.8h, v1.8h}, [x24], #32
1766 0x4cd17200, // ld1 {v0.16b}, [x16], x17
1767 };
1768 asm_check((unsigned int *)PC, vector_insns,
1769 sizeof vector_insns / sizeof vector_insns[0]);
1770 }
1771 }
1772 #endif // ASSERT
1773
1774 #undef __
1775
1776 void Assembler::emit_data64(jlong data,
1777 relocInfo::relocType rtype,
1778 int format) {
1779 if (rtype == relocInfo::none) {
1780 emit_int64(data);
1781 } else {
1782 emit_data64(data, Relocation::spec_simple(rtype), format);
1783 }
1784 }
1785
1786 void Assembler::emit_data64(jlong data,
1787 RelocationHolder const& rspec,
1788 int format) {
1789
1790 assert(inst_mark() != NULL, "must be inside InstructionMark");
1791 // Do not use AbstractAssembler::relocate, which is not intended for
1792 // embedded words. Instead, relocate to the enclosing instruction.
1793 code_section()->relocate(inst_mark(), rspec, format);
1794 emit_int64(data);
1795 }
1796
1797 extern "C" {
1798 void das(uint64_t start, int len) {
1799 ResourceMark rm;
1800 len <<= 2;
1801 if (len < 0)
1802 Disassembler::decode((address)start + len, (address)start);
1803 else
1804 Disassembler::decode((address)start, (address)start + len);
1805 }
1806
1807 JNIEXPORT void das1(unsigned long insn) {
1808 das(insn, 1);
1809 }
1810 }
1811
1812 #define gas_assert(ARG1) assert(ARG1, #ARG1)
1813
1814 #define __ as->
1815
1816 void Address::lea(MacroAssembler *as, Register r) const {
1817 Relocation* reloc = _rspec.reloc();
1818 relocInfo::relocType rtype = (relocInfo::relocType) reloc->type();
1819
1820 switch(_mode) {
1821 case base_plus_offset: {
1822 if (_offset == 0 && _base == r) // it's a nop
1823 break;
1824 if (_offset > 0)
1825 __ add(r, _base, _offset);
1826 else
1827 __ sub(r, _base, -_offset);
1828 break;
1829 }
1830 case base_plus_offset_reg: {
1831 __ add(r, _base, _index, _ext.op(), MAX(_ext.shift(), 0));
1832 break;
1833 }
1834 case literal: {
1835 if (rtype == relocInfo::none)
1836 __ mov(r, target());
1837 else
1838 __ movptr(r, (uint64_t)target());
1839 break;
1840 }
1841 default:
1842 ShouldNotReachHere();
1843 }
1844 }
1845
1846 void Assembler::adrp(Register reg1, const Address &dest, unsigned long &byte_offset) {
1847 ShouldNotReachHere();
1848 }
1849
1850 #undef __
1851
1852 #define starti Instruction_aarch64 do_not_use(this); set_current(&do_not_use)
1853
1854 void Assembler::adr(Register Rd, address adr) {
1855 long offset = adr - pc();
1856 int offset_lo = offset & 3;
1857 offset >>= 2;
1858 starti;
1859 f(0, 31), f(offset_lo, 30, 29), f(0b10000, 28, 24), sf(offset, 23, 5);
1860 rf(Rd, 0);
1861 }
1862
1863 void Assembler::_adrp(Register Rd, address adr) {
1864 uint64_t pc_page = (uint64_t)pc() >> 12;
1865 uint64_t adr_page = (uint64_t)adr >> 12;
1866 long offset = adr_page - pc_page;
1867 int offset_lo = offset & 3;
1868 offset >>= 2;
1869 starti;
1870 f(1, 31), f(offset_lo, 30, 29), f(0b10000, 28, 24), sf(offset, 23, 5);
1871 rf(Rd, 0);
1872 }
1873
1874 #undef starti
1875
1876 Address::Address(address target, relocInfo::relocType rtype) : _mode(literal){
1877 _is_lval = false;
1878 _target = target;
1879 switch (rtype) {
1880 case relocInfo::oop_type:
1881 case relocInfo::metadata_type:
1882 // Oops are a special case. Normally they would be their own section
1883 // but in cases like icBuffer they are literals in the code stream that
1884 // we don't have a section for. We use none so that we get a literal address
1885 // which is always patchable.
1886 break;
1887 case relocInfo::external_word_type:
1888 _rspec = external_word_Relocation::spec(target);
1889 break;
1890 case relocInfo::internal_word_type:
1891 _rspec = internal_word_Relocation::spec(target);
1892 break;
1893 case relocInfo::opt_virtual_call_type:
1894 _rspec = opt_virtual_call_Relocation::spec();
1895 break;
1896 case relocInfo::static_call_type:
1897 _rspec = static_call_Relocation::spec();
1898 break;
1899 case relocInfo::runtime_call_type:
1900 _rspec = runtime_call_Relocation::spec();
1901 break;
1902 case relocInfo::poll_type:
1903 case relocInfo::poll_return_type:
1904 _rspec = Relocation::spec_simple(rtype);
1905 break;
1906 case relocInfo::none:
1907 _rspec = RelocationHolder::none;
1908 break;
1909 default:
1910 ShouldNotReachHere();
1911 break;
1912 }
1913 }
1914
1915 void Assembler::b(const Address &dest) {
1916 code_section()->relocate(pc(), dest.rspec());
1917 b(dest.target());
1918 }
1919
1920 void Assembler::bl(const Address &dest) {
1921 code_section()->relocate(pc(), dest.rspec());
1922 bl(dest.target());
1923 }
1924
1925 void Assembler::adr(Register r, const Address &dest) {
1926 code_section()->relocate(pc(), dest.rspec());
1927 adr(r, dest.target());
1928 }
1929
1930 void Assembler::br(Condition cc, Label &L) {
1931 if (L.is_bound()) {
1932 br(cc, target(L));
1933 } else {
1934 L.add_patch_at(code(), locator());
1935 br(cc, pc());
1936 }
1937 }
1938
1939 void Assembler::wrap_label(Label &L,
1940 Assembler::uncond_branch_insn insn) {
1941 if (L.is_bound()) {
1942 (this->*insn)(target(L));
1943 } else {
1944 L.add_patch_at(code(), locator());
1945 (this->*insn)(pc());
1946 }
1947 }
1948
1949 void Assembler::wrap_label(Register r, Label &L,
1950 compare_and_branch_insn insn) {
1951 if (L.is_bound()) {
1952 (this->*insn)(r, target(L));
1953 } else {
1954 L.add_patch_at(code(), locator());
1955 (this->*insn)(r, pc());
1956 }
1957 }
1958
1959 void Assembler::wrap_label(Register r, int bitpos, Label &L,
1960 test_and_branch_insn insn) {
1961 if (L.is_bound()) {
1962 (this->*insn)(r, bitpos, target(L));
1963 } else {
1964 L.add_patch_at(code(), locator());
1965 (this->*insn)(r, bitpos, pc());
1966 }
1967 }
1968
1969 void Assembler::wrap_label(Label &L, prfop op, prefetch_insn insn) {
1970 if (L.is_bound()) {
1971 (this->*insn)(target(L), op);
1972 } else {
1973 L.add_patch_at(code(), locator());
1974 (this->*insn)(pc(), op);
1975 }
1976 }
1977
1978 // An "all-purpose" add/subtract immediate, per ARM documentation:
1979 // A "programmer-friendly" assembler may accept a negative immediate
1980 // between -(2^24 -1) and -1 inclusive, causing it to convert a
1981 // requested ADD operation to a SUB, or vice versa, and then encode
1982 // the absolute value of the immediate as for uimm24.
1983 void Assembler::add_sub_immediate(Register Rd, Register Rn, unsigned uimm, int op,
1984 int negated_op) {
1985 bool sets_flags = op & 1; // this op sets flags
1986 union {
1987 unsigned u;
1988 int imm;
1989 };
1990 u = uimm;
1991 bool shift = false;
1992 bool neg = imm < 0;
1993 if (neg) {
1994 imm = -imm;
1995 op = negated_op;
1996 }
1997 assert(Rd != sp || imm % 16 == 0, "misaligned stack");
1998 if (imm >= (1 << 11)
1999 && ((imm >> 12) << 12 == imm)) {
2000 imm >>= 12;
2001 shift = true;
2002 }
2003 f(op, 31, 29), f(0b10001, 28, 24), f(shift, 23, 22), f(imm, 21, 10);
2004
2005 // add/subtract immediate ops with the S bit set treat r31 as zr;
2006 // with S unset they use sp.
2007 if (sets_flags)
2008 zrf(Rd, 0);
2009 else
2010 srf(Rd, 0);
2011
2012 srf(Rn, 5);
2013 }
2014
2015 bool Assembler::operand_valid_for_add_sub_immediate(long imm) {
2016 bool shift = false;
2017 unsigned long uimm = uabs(imm);
2018 if (uimm < (1 << 12))
2019 return true;
2020 if (uimm < (1 << 24)
2021 && ((uimm >> 12) << 12 == uimm)) {
2022 return true;
2023 }
2024 return false;
2025 }
2026
2027 bool Assembler::operand_valid_for_logical_immediate(bool is32, uint64_t imm) {
2028 return encode_logical_immediate(is32, imm) != 0xffffffff;
2029 }
2030
2031 static uint64_t doubleTo64Bits(jdouble d) {
2032 union {
2033 jdouble double_value;
2034 uint64_t double_bits;
2035 };
2036
2037 double_value = d;
2038 return double_bits;
2039 }
2040
2041 bool Assembler::operand_valid_for_float_immediate(double imm) {
2042 // If imm is all zero bits we can use ZR as the source of a
2043 // floating-point value.
2044 if (doubleTo64Bits(imm) == 0)
2045 return true;
2046
2047 // Otherwise try to encode imm then convert the encoded value back
2048 // and make sure it's the exact same bit pattern.
2049 unsigned result = encoding_for_fp_immediate(imm);
2050 return doubleTo64Bits(imm) == fp_immediate_for_encoding(result, true);
2051 }
2052
2053 int AbstractAssembler::code_fill_byte() {
2054 return 0;
2055 }
2056
2057 // n.b. this is implemented in subclass MacroAssembler
2058 void Assembler::bang_stack_with_offset(int offset) { Unimplemented(); }
2059
2060
2061 // and now the routines called by the assembler which encapsulate the
2062 // above encode and decode functions
2063
2064 uint32_t
2065 asm_util::encode_logical_immediate(bool is32, uint64_t imm)
2066 {
2067 if (is32) {
2068 /* Allow all zeros or all ones in top 32-bits, so that
2069 constant expressions like ~1 are permitted. */
2070 if (imm >> 32 != 0 && imm >> 32 != 0xffffffff)
2071 return 0xffffffff;
2072 /* Replicate the 32 lower bits to the 32 upper bits. */
2073 imm &= 0xffffffff;
2074 imm |= imm << 32;
2075 }
2076
2077 return encoding_for_logical_immediate(imm);
2078 }
2079
2080 unsigned Assembler::pack(double value) {
2081 float val = (float)value;
2082 unsigned result = encoding_for_fp_immediate(val);
2083 guarantee(unpack(result) == value,
2084 "Invalid floating-point immediate operand");
2085 return result;
2086 }
2087
2088 // Packed operands for Floating-point Move (immediate)
2089
2090 static float unpack(unsigned value) {
2091 union {
2092 unsigned ival;
2093 float val;
2094 };
2095 ival = fp_immediate_for_encoding(value, 0);
2096 return val;
2097 }