1 // Copyright (c) 2020, Oracle and/or its affiliates. All rights reserved.
2 // Copyright (c) 2020, Arm Limited. All rights reserved.
3 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 //
5 // This code is free software; you can redistribute it and/or modify it
6 // under the terms of the GNU General Public License version 2 only, as
7 // published by the Free Software Foundation.
8 //
9 // This code is distributed in the hope that it will be useful, but WITHOUT
10 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 // version 2 for more details (a copy is included in the LICENSE file that
13 // accompanied this code).
14 //
15 // You should have received a copy of the GNU General Public License version
16 // 2 along with this work; if not, write to the Free Software Foundation,
17 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 //
19 // Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 // or visit www.oracle.com if you need additional information or have any
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22 //
23 //
24
25 // This file is automatically generated by running "m4 aarch64_neon_ad.m4". Do not edit ----
26
27 // AArch64 NEON Architecture Description File
28
29 // ====================VECTOR INSTRUCTIONS==================================
30
31 // ------------------------------ Load/store/reinterpret -----------------------
32
33 // Load vector (16 bits)
34 instruct loadV2(vecD dst, memory mem)
35 %{
36 predicate(n->as_LoadVector()->memory_size() == 2);
37 match(Set dst (LoadVector mem));
38 ins_cost(4 * INSN_COST);
39 format %{ "ldrh $dst,$mem\t# vector (16 bits)" %}
40 ins_encode( aarch64_enc_ldrvH(dst, mem) );
41 ins_pipe(vload_reg_mem64);
42 %}
43
44 // Store Vector (16 bits)
45 instruct storeV2(vecD src, memory mem)
46 %{
47 predicate(n->as_StoreVector()->memory_size() == 2);
48 match(Set mem (StoreVector mem src));
49 ins_cost(4 * INSN_COST);
50 format %{ "strh $mem,$src\t# vector (16 bits)" %}
51 ins_encode( aarch64_enc_strvH(src, mem) );
52 ins_pipe(vstore_reg_mem64);
53 %}
54
55 instruct reinterpretD(vecD dst)
56 %{
57 predicate(n->bottom_type()->is_vect()->length_in_bytes() == 8 &&
58 n->in(1)->bottom_type()->is_vect()->length_in_bytes() == 8);
59 match(Set dst (VectorReinterpret dst));
60 ins_cost(0);
61 format %{ " # reinterpret $dst" %}
62 ins_encode %{
63 // empty
64 %}
65 ins_pipe(pipe_class_empty);
66 %}
67
68 instruct reinterpretX(vecX dst)
69 %{
70 predicate(n->bottom_type()->is_vect()->length_in_bytes() == 16 &&
71 n->in(1)->bottom_type()->is_vect()->length_in_bytes() == 16);
72 match(Set dst (VectorReinterpret dst));
73 ins_cost(0);
74 format %{ " # reinterpret $dst" %}
75 ins_encode %{
76 // empty
77 %}
78 ins_pipe(pipe_class_empty);
79 %}
80
81 instruct reinterpretD2X(vecX dst, vecD src)
82 %{
83 predicate(n->bottom_type()->is_vect()->length_in_bytes() == 16 &&
84 n->in(1)->bottom_type()->is_vect()->length_in_bytes() == 8);
85 match(Set dst (VectorReinterpret src));
86 ins_cost(INSN_COST);
87 format %{ " # reinterpret $dst,$src" %}
88 ins_encode %{
89 // If register is the same, then move is not needed.
90 if (as_FloatRegister($dst$$reg) != as_FloatRegister($src$$reg)) {
91 __ orr(as_FloatRegister($dst$$reg), __ T8B,
92 as_FloatRegister($src$$reg),
93 as_FloatRegister($src$$reg));
94 }
95 %}
96 ins_pipe(vlogical64);
97 %}
98
99 instruct reinterpretX2D(vecD dst, vecX src)
100 %{
101 predicate(n->bottom_type()->is_vect()->length_in_bytes() == 8 &&
102 n->in(1)->bottom_type()->is_vect()->length_in_bytes() == 16);
103 match(Set dst (VectorReinterpret src));
104 ins_cost(INSN_COST);
105 format %{ " # reinterpret $dst,$src" %}
106 ins_encode %{
107 // If register is the same, then move is not needed.
108 if (as_FloatRegister($dst$$reg) != as_FloatRegister($src$$reg)) {
109 __ orr(as_FloatRegister($dst$$reg), __ T8B,
110 as_FloatRegister($src$$reg),
111 as_FloatRegister($src$$reg));
112 }
113 %}
114 ins_pipe(vlogical64);
115 %}
116
117 // ------------------------------ Vector cast -------------------------------
118
119 instruct vcvt4Bto4S(vecD dst, vecD src)
120 %{
121 predicate(n->as_Vector()->length() == 4 && n->bottom_type()->is_vect()->element_basic_type() == T_SHORT);
122 match(Set dst (VectorCastB2X src));
123 format %{ "sxtl $dst, T8H, $src, T8B\t# convert 4B to 4S vector" %}
124 ins_encode %{
125 __ sxtl(as_FloatRegister($dst$$reg), __ T8H, as_FloatRegister($src$$reg), __ T8B);
126 %}
127 ins_pipe(pipe_class_default);
128 %}
129
130 instruct vcvt8Bto8S(vecX dst, vecD src)
131 %{
132 predicate(n->as_Vector()->length() == 8 && n->bottom_type()->is_vect()->element_basic_type() == T_SHORT);
133 match(Set dst (VectorCastB2X src));
134 format %{ "sxtl $dst, T8H, $src, T8B\t# convert 8B to 8S vector" %}
135 ins_encode %{
136 __ sxtl(as_FloatRegister($dst$$reg), __ T8H, as_FloatRegister($src$$reg), __ T8B);
137 %}
138 ins_pipe(pipe_class_default);
139 %}
140
141 instruct vcvt4Sto4B(vecD dst, vecD src)
142 %{
143 predicate(n->as_Vector()->length() == 4 && n->bottom_type()->is_vect()->element_basic_type() == T_BYTE);
144 match(Set dst (VectorCastS2X src));
145 format %{ "xtn $dst, T8B, $src, T8H\t# convert 4S to 4B vector" %}
146 ins_encode %{
147 __ xtn(as_FloatRegister($dst$$reg), __ T8B, as_FloatRegister($src$$reg), __ T8H);
148 %}
149 ins_pipe(pipe_class_default);
150 %}
151
152 instruct vcvt8Sto8B(vecD dst, vecX src)
153 %{
154 predicate(n->as_Vector()->length() == 8 && n->bottom_type()->is_vect()->element_basic_type() == T_BYTE);
155 match(Set dst (VectorCastS2X src));
156 format %{ "xtn $dst, T8B, $src, T8H\t# convert 8S to 8B vector" %}
157 ins_encode %{
158 __ xtn(as_FloatRegister($dst$$reg), __ T8B, as_FloatRegister($src$$reg), __ T8H);
159 %}
160 ins_pipe(pipe_class_default);
161 %}
162
163 instruct vcvt4Sto4I(vecX dst, vecD src)
164 %{
165 predicate(n->as_Vector()->length() == 4 && n->bottom_type()->is_vect()->element_basic_type() == T_INT);
166 match(Set dst (VectorCastS2X src));
167 format %{ "sxtl $dst, T4S, $src, T4H\t# convert 4S to 4I vector" %}
168 ins_encode %{
169 __ sxtl(as_FloatRegister($dst$$reg), __ T4S, as_FloatRegister($src$$reg), __ T4H);
170 %}
171 ins_pipe(pipe_class_default);
172 %}
173
174 instruct vcvt4Ito4S(vecD dst, vecX src)
175 %{
176 predicate(n->as_Vector()->length() == 4 && n->bottom_type()->is_vect()->element_basic_type() == T_SHORT);
177 match(Set dst (VectorCastI2X src));
178 format %{ "xtn $dst, T4H, $src, T4S\t# convert 4I to 4S vector" %}
179 ins_encode %{
180 __ xtn(as_FloatRegister($dst$$reg), __ T4H, as_FloatRegister($src$$reg), __ T4S);
181 %}
182 ins_pipe(pipe_class_default);
183 %}
184
185 instruct vcvt2Ito2L(vecX dst, vecD src)
186 %{
187 predicate(n->as_Vector()->length() == 2 && n->bottom_type()->is_vect()->element_basic_type() == T_LONG);
188 match(Set dst (VectorCastI2X src));
189 format %{ "sxtl $dst, T2D, $src, T2S\t# convert 2I to 2L vector" %}
190 ins_encode %{
191 __ sxtl(as_FloatRegister($dst$$reg), __ T2D, as_FloatRegister($src$$reg), __ T2S);
192 %}
193 ins_pipe(pipe_class_default);
194 %}
195
196 instruct vcvt2Lto2I(vecD dst, vecX src)
197 %{
198 predicate(n->as_Vector()->length() == 2 && n->bottom_type()->is_vect()->element_basic_type() == T_INT);
199 match(Set dst (VectorCastL2X src));
200 format %{ "xtn $dst, T2S, $src, T2D\t# convert 2L to 2I vector" %}
201 ins_encode %{
202 __ xtn(as_FloatRegister($dst$$reg), __ T2S, as_FloatRegister($src$$reg), __ T2D);
203 %}
204 ins_pipe(pipe_class_default);
205 %}
206
207 instruct vcvt4Bto4I(vecX dst, vecD src)
208 %{
209 predicate(n->as_Vector()->length() == 4 && n->bottom_type()->is_vect()->element_basic_type() == T_INT);
210 match(Set dst (VectorCastB2X src));
211 format %{ "sxtl $dst, T8H, $src, T8B\n\t"
212 "sxtl $dst, T4S, $dst, T4H\t# convert 4B to 4I vector"
213 %}
214 ins_encode %{
215 __ sxtl(as_FloatRegister($dst$$reg), __ T8H, as_FloatRegister($src$$reg), __ T8B);
216 __ sxtl(as_FloatRegister($dst$$reg), __ T4S, as_FloatRegister($dst$$reg), __ T4H);
217 %}
218 ins_pipe(pipe_slow);
219 %}
220
221 instruct vcvt4Ito4B(vecD dst, vecX src)
222 %{
223 predicate(n->as_Vector()->length() == 4 && n->bottom_type()->is_vect()->element_basic_type() == T_BYTE);
224 match(Set dst (VectorCastI2X src));
225 format %{ "xtn $dst, T4H, $src, T4S\n\t"
226 "xtn $dst, T8B, $dst, T8H\t# convert 4I to 4B vector"
227 %}
228 ins_encode %{
229 __ xtn(as_FloatRegister($dst$$reg), __ T4H, as_FloatRegister($src$$reg), __ T4S);
230 __ xtn(as_FloatRegister($dst$$reg), __ T8B, as_FloatRegister($dst$$reg), __ T8H);
231 %}
232 ins_pipe(pipe_slow);
233 %}
234
235 instruct vcvt4Bto4F(vecX dst, vecD src)
236 %{
237 predicate(n->as_Vector()->length() == 4 && n->bottom_type()->is_vect()->element_basic_type() == T_FLOAT);
238 match(Set dst (VectorCastB2X src));
239 format %{ "sxtl $dst, T8H, $src, T8B\n\t"
240 "sxtl $dst, T4S, $dst, T4H\n\t"
241 "scvtfv T4S, $dst, $dst\t# convert 4B to 4F vector"
242 %}
243 ins_encode %{
244 __ sxtl(as_FloatRegister($dst$$reg), __ T8H, as_FloatRegister($src$$reg), __ T8B);
245 __ sxtl(as_FloatRegister($dst$$reg), __ T4S, as_FloatRegister($dst$$reg), __ T4H);
246 __ scvtfv(__ T4S, as_FloatRegister($dst$$reg), as_FloatRegister($dst$$reg));
247 %}
248 ins_pipe(pipe_slow);
249 %}
250
251 instruct vcvt4Sto4F(vecX dst, vecD src)
252 %{
253 predicate(n->as_Vector()->length() == 4 && n->bottom_type()->is_vect()->element_basic_type() == T_FLOAT);
254 match(Set dst (VectorCastS2X src));
255 format %{ "sxtl $dst, T4S, $src, T4H\n\t"
256 "scvtfv T4S, $dst, $dst\t# convert 4S to 4F vector"
257 %}
258 ins_encode %{
259 __ sxtl(as_FloatRegister($dst$$reg), __ T4S, as_FloatRegister($src$$reg), __ T4H);
260 __ scvtfv(__ T4S, as_FloatRegister($dst$$reg), as_FloatRegister($dst$$reg));
261 %}
262 ins_pipe(pipe_slow);
263 %}
264
265 instruct vcvt2Ito2D(vecX dst, vecD src)
266 %{
267 predicate(n->as_Vector()->length() == 2 && n->bottom_type()->is_vect()->element_basic_type() == T_DOUBLE);
268 match(Set dst (VectorCastI2X src));
269 format %{ "sxtl $dst, T2D, $src, T2S\n\t"
270 "scvtfv T2D, $dst, $dst\t# convert 2I to 2D vector"
271 %}
272 ins_encode %{
273 __ sxtl(as_FloatRegister($dst$$reg), __ T2D, as_FloatRegister($src$$reg), __ T2S);
274 __ scvtfv(__ T2D, as_FloatRegister($dst$$reg), as_FloatRegister($dst$$reg));
275 %}
276 ins_pipe(pipe_slow);
277 %}
278
279 instruct vcvt2Ito2F(vecD dst, vecD src)
280 %{
281 predicate(n->as_Vector()->length() == 2 && n->bottom_type()->is_vect()->element_basic_type() == T_FLOAT);
282 match(Set dst (VectorCastI2X src));
283 format %{ "scvtfv T2S, $dst, $src\t# convert 2I to 2F vector" %}
284 ins_encode %{
285 __ scvtfv(__ T2S, as_FloatRegister($dst$$reg), as_FloatRegister($src$$reg));
286 %}
287 ins_pipe(pipe_class_default);
288 %}
289
290 instruct vcvt4Ito4F(vecX dst, vecX src)
291 %{
292 predicate(n->as_Vector()->length() == 4 && n->bottom_type()->is_vect()->element_basic_type() == T_FLOAT);
293 match(Set dst (VectorCastI2X src));
294 format %{ "scvtfv T4S, $dst, $src\t# convert 4I to 4F vector" %}
295 ins_encode %{
296 __ scvtfv(__ T4S, as_FloatRegister($dst$$reg), as_FloatRegister($src$$reg));
297 %}
298 ins_pipe(pipe_class_default);
299 %}
300
301 instruct vcvt2Lto2D(vecX dst, vecX src)
302 %{
303 predicate(n->as_Vector()->length() == 2 && n->bottom_type()->is_vect()->element_basic_type() == T_DOUBLE);
304 match(Set dst (VectorCastL2X src));
305 format %{ "scvtfv T2D, $dst, $src\t# convert 2L to 2D vector" %}
306 ins_encode %{
307 __ scvtfv(__ T2D, as_FloatRegister($dst$$reg), as_FloatRegister($src$$reg));
308 %}
309 ins_pipe(pipe_class_default);
310 %}
311
312 instruct vcvt2Fto2D(vecX dst, vecD src)
313 %{
314 predicate(n->as_Vector()->length() == 2 && n->bottom_type()->is_vect()->element_basic_type() == T_DOUBLE);
315 match(Set dst (VectorCastF2X src));
316 format %{ "fcvtl $dst, T2D, $src, T2S\t# convert 2F to 2D vector" %}
317 ins_encode %{
318 __ fcvtl(as_FloatRegister($dst$$reg), __ T2D, as_FloatRegister($src$$reg), __ T2S);
319 %}
320 ins_pipe(pipe_class_default);
321 %}
322
323 instruct vcvt2Dto2F(vecD dst, vecX src)
324 %{
325 predicate(n->as_Vector()->length() == 2 && n->bottom_type()->is_vect()->element_basic_type() == T_FLOAT);
326 match(Set dst (VectorCastD2X src));
327 format %{ "fcvtn $dst, T2S, $src, T2D\t# convert 2D to 2F vector" %}
328 ins_encode %{
329 __ fcvtn(as_FloatRegister($dst$$reg), __ T2S, as_FloatRegister($src$$reg), __ T2D);
330 %}
331 ins_pipe(pipe_class_default);
332 %}
333
334 instruct vcvt2Lto2F(vecD dst, vecX src)
335 %{
336 predicate(n->as_Vector()->length() == 2 && n->bottom_type()->is_vect()->element_basic_type() == T_FLOAT);
337 match(Set dst (VectorCastL2X src));
338 format %{ "scvtfv T2D, $dst, $src\n\t"
339 "fcvtn $dst, T2S, $dst, T2D\t# convert 2L to 2F vector"
340 %}
341 ins_encode %{
342 __ scvtfv(__ T2D, as_FloatRegister($dst$$reg), as_FloatRegister($src$$reg));
343 __ fcvtn(as_FloatRegister($dst$$reg), __ T2S, as_FloatRegister($dst$$reg), __ T2D);
344 %}
345 ins_pipe(pipe_slow);
346 %}
347
348 // ------------------------------ Reduction -------------------------------
349
350 instruct reduce_add8B(iRegINoSp dst, iRegIorL2I isrc, vecD vsrc, vecD tmp)
351 %{
352 predicate(n->in(2)->bottom_type()->is_vect()->element_basic_type() == T_BYTE);
353 match(Set dst (AddReductionVI isrc vsrc));
354 ins_cost(INSN_COST);
355 effect(TEMP_DEF dst, TEMP tmp);
356 format %{ "addv $tmp, T8B, $vsrc\n\t"
357 "smov $dst, $tmp, B, 0\n\t"
358 "addw $dst, $dst, $isrc\n\t"
359 "sxtb $dst, $dst\t# add reduction8B"
360 %}
361 ins_encode %{
362 __ addv(as_FloatRegister($tmp$$reg), __ T8B, as_FloatRegister($vsrc$$reg));
363 __ smov($dst$$Register, as_FloatRegister($tmp$$reg), __ B, 0);
364 __ addw($dst$$Register, $dst$$Register, $isrc$$Register);
365 __ sxtb($dst$$Register, $dst$$Register);
366 %}
367 ins_pipe(pipe_slow);
368 %}
369
370 instruct reduce_add16B(iRegINoSp dst, iRegIorL2I isrc, vecX vsrc, vecX tmp)
371 %{
372 predicate(n->in(2)->bottom_type()->is_vect()->element_basic_type() == T_BYTE);
373 match(Set dst (AddReductionVI isrc vsrc));
374 ins_cost(INSN_COST);
375 effect(TEMP_DEF dst, TEMP tmp);
376 format %{ "addv $tmp, T16B, $vsrc\n\t"
377 "smov $dst, $tmp, B, 0\n\t"
378 "addw $dst, $dst, $isrc\n\t"
379 "sxtb $dst, $dst\t# add reduction16B"
380 %}
381 ins_encode %{
382 __ addv(as_FloatRegister($tmp$$reg), __ T16B, as_FloatRegister($vsrc$$reg));
383 __ smov($dst$$Register, as_FloatRegister($tmp$$reg), __ B, 0);
384 __ addw($dst$$Register, $dst$$Register, $isrc$$Register);
385 __ sxtb($dst$$Register, $dst$$Register);
386 %}
387 ins_pipe(pipe_slow);
388 %}
389
390 instruct reduce_add4S(iRegINoSp dst, iRegIorL2I isrc, vecD vsrc, vecD tmp)
391 %{
392 predicate(n->in(2)->bottom_type()->is_vect()->element_basic_type() == T_SHORT);
393 match(Set dst (AddReductionVI isrc vsrc));
394 ins_cost(INSN_COST);
395 effect(TEMP_DEF dst, TEMP tmp);
396 format %{ "addv $tmp, T4H, $vsrc\n\t"
397 "smov $dst, $tmp, H, 0\n\t"
398 "addw $dst, $dst, $isrc\n\t"
399 "sxth $dst, $dst\t# add reduction4S"
400 %}
401 ins_encode %{
402 __ addv(as_FloatRegister($tmp$$reg), __ T4H, as_FloatRegister($vsrc$$reg));
403 __ smov($dst$$Register, as_FloatRegister($tmp$$reg), __ H, 0);
404 __ addw($dst$$Register, $dst$$Register, $isrc$$Register);
405 __ sxth($dst$$Register, $dst$$Register);
406 %}
407 ins_pipe(pipe_slow);
408 %}
409
410 instruct reduce_add8S(iRegINoSp dst, iRegIorL2I isrc, vecX vsrc, vecX tmp)
411 %{
412 predicate(n->in(2)->bottom_type()->is_vect()->element_basic_type() == T_SHORT);
413 match(Set dst (AddReductionVI isrc vsrc));
414 ins_cost(INSN_COST);
415 effect(TEMP_DEF dst, TEMP tmp);
416 format %{ "addv $tmp, T8H, $vsrc\n\t"
417 "smov $dst, $tmp, H, 0\n\t"
418 "addw $dst, $dst, $isrc\n\t"
419 "sxth $dst, $dst\t# add reduction8S"
420 %}
421 ins_encode %{
422 __ addv(as_FloatRegister($tmp$$reg), __ T8H, as_FloatRegister($vsrc$$reg));
423 __ smov($dst$$Register, as_FloatRegister($tmp$$reg), __ H, 0);
424 __ addw($dst$$Register, $dst$$Register, $isrc$$Register);
425 __ sxth($dst$$Register, $dst$$Register);
426 %}
427 ins_pipe(pipe_slow);
428 %}
429
430 instruct reduce_add2L(iRegLNoSp dst, iRegL isrc, vecX vsrc, vecX tmp)
431 %{
432 match(Set dst (AddReductionVL isrc vsrc));
433 ins_cost(INSN_COST);
434 effect(TEMP_DEF dst, TEMP tmp);
435 format %{ "addpd $tmp, $vsrc\n\t"
436 "umov $dst, $tmp, D, 0\n\t"
437 "add $dst, $isrc, $dst\t# add reduction2L"
438 %}
439 ins_encode %{
440 __ addpd(as_FloatRegister($tmp$$reg), as_FloatRegister($vsrc$$reg));
441 __ umov($dst$$Register, as_FloatRegister($tmp$$reg), __ D, 0);
442 __ add($dst$$Register, $isrc$$Register, $dst$$Register);
443 %}
444 ins_pipe(pipe_slow);
445 %}
446
447 instruct reduce_mul8B(iRegINoSp dst, iRegIorL2I isrc, vecD vsrc, vecD vtmp1, vecD vtmp2, iRegINoSp itmp)
448 %{
449 predicate(n->in(2)->bottom_type()->is_vect()->element_basic_type() == T_BYTE);
450 match(Set dst (MulReductionVI isrc vsrc));
451 ins_cost(INSN_COST);
452 effect(TEMP_DEF dst, TEMP vtmp1, TEMP vtmp2, TEMP itmp);
453 format %{ "ins $vtmp1, S, $vsrc, 0, 1\n\t"
454 "mulv $vtmp1, T8B, $vtmp1, $vsrc\n\t"
455 "ins $vtmp2, H, $vtmp1, 0, 1\n\t"
456 "mulv $vtmp2, T8B, $vtmp2, $vtmp1\n\t"
457 "umov $itmp, $vtmp2, B, 0\n\t"
458 "mulw $dst, $itmp, $isrc\n\t"
459 "sxtb $dst, $dst\n\t"
460 "umov $itmp, $vtmp2, B, 1\n\t"
461 "mulw $dst, $itmp, $dst\n\t"
462 "sxtb $dst, $dst\t# mul reduction8B"
463 %}
464 ins_encode %{
465 __ ins(as_FloatRegister($vtmp1$$reg), __ S,
466 as_FloatRegister($vsrc$$reg), 0, 1);
467 __ mulv(as_FloatRegister($vtmp1$$reg), __ T8B,
468 as_FloatRegister($vtmp1$$reg), as_FloatRegister($vsrc$$reg));
469 __ ins(as_FloatRegister($vtmp2$$reg), __ H,
470 as_FloatRegister($vtmp1$$reg), 0, 1);
471 __ mulv(as_FloatRegister($vtmp2$$reg), __ T8B,
472 as_FloatRegister($vtmp2$$reg), as_FloatRegister($vtmp1$$reg));
473 __ umov($itmp$$Register, as_FloatRegister($vtmp2$$reg), __ B, 0);
474 __ mulw($dst$$Register, $itmp$$Register, $isrc$$Register);
475 __ sxtb($dst$$Register, $dst$$Register);
476 __ umov($itmp$$Register, as_FloatRegister($vtmp2$$reg), __ B, 1);
477 __ mulw($dst$$Register, $itmp$$Register, $dst$$Register);
478 __ sxtb($dst$$Register, $dst$$Register);
479 %}
480 ins_pipe(pipe_slow);
481 %}
482
483 instruct reduce_mul16B(iRegINoSp dst, iRegIorL2I isrc, vecX vsrc, vecX vtmp1, vecX vtmp2, iRegINoSp itmp)
484 %{
485 predicate(n->in(2)->bottom_type()->is_vect()->element_basic_type() == T_BYTE);
486 match(Set dst (MulReductionVI isrc vsrc));
487 ins_cost(INSN_COST);
488 effect(TEMP_DEF dst, TEMP vtmp1, TEMP vtmp2, TEMP itmp);
489 format %{ "ins $vtmp1, D, $vsrc, 0, 1\n\t"
490 "mulv $vtmp1, T8B, $vtmp1, $vsrc\n\t"
491 "ins $vtmp2, S, $vtmp1, 0, 1\n\t"
492 "mulv $vtmp1, T8B, $vtmp2, $vtmp1\n\t"
493 "ins $vtmp2, H, $vtmp1, 0, 1\n\t"
494 "mulv $vtmp2, T8B, $vtmp2, $vtmp1\n\t"
495 "umov $itmp, $vtmp2, B, 0\n\t"
496 "mulw $dst, $itmp, $isrc\n\t"
497 "sxtb $dst, $dst\n\t"
498 "umov $itmp, $vtmp2, B, 1\n\t"
499 "mulw $dst, $itmp, $dst\n\t"
500 "sxtb $dst, $dst\t# mul reduction16B"
501 %}
502 ins_encode %{
503 __ ins(as_FloatRegister($vtmp1$$reg), __ D,
504 as_FloatRegister($vsrc$$reg), 0, 1);
505 __ mulv(as_FloatRegister($vtmp1$$reg), __ T8B,
506 as_FloatRegister($vtmp1$$reg), as_FloatRegister($vsrc$$reg));
507 __ ins(as_FloatRegister($vtmp2$$reg), __ S,
508 as_FloatRegister($vtmp1$$reg), 0, 1);
509 __ mulv(as_FloatRegister($vtmp1$$reg), __ T8B,
510 as_FloatRegister($vtmp2$$reg), as_FloatRegister($vtmp1$$reg));
511 __ ins(as_FloatRegister($vtmp2$$reg), __ H,
512 as_FloatRegister($vtmp1$$reg), 0, 1);
513 __ mulv(as_FloatRegister($vtmp2$$reg), __ T8B,
514 as_FloatRegister($vtmp2$$reg), as_FloatRegister($vtmp1$$reg));
515 __ umov($itmp$$Register, as_FloatRegister($vtmp2$$reg), __ B, 0);
516 __ mulw($dst$$Register, $itmp$$Register, $isrc$$Register);
517 __ sxtb($dst$$Register, $dst$$Register);
518 __ umov($itmp$$Register, as_FloatRegister($vtmp2$$reg), __ B, 1);
519 __ mulw($dst$$Register, $itmp$$Register, $dst$$Register);
520 __ sxtb($dst$$Register, $dst$$Register);
521 %}
522 ins_pipe(pipe_slow);
523 %}
524
525 instruct reduce_mul4S(iRegINoSp dst, iRegIorL2I isrc, vecD vsrc, vecD vtmp, iRegINoSp itmp)
526 %{
527 predicate(n->in(2)->bottom_type()->is_vect()->element_basic_type() == T_SHORT);
528 match(Set dst (MulReductionVI isrc vsrc));
529 ins_cost(INSN_COST);
530 effect(TEMP_DEF dst, TEMP vtmp, TEMP itmp);
531 format %{ "ins $vtmp, S, $vsrc, 0, 1\n\t"
532 "mulv $vtmp, T4H, $vtmp, $vsrc\n\t"
533 "umov $itmp, $vtmp, H, 0\n\t"
534 "mulw $dst, $itmp, $isrc\n\t"
535 "sxth $dst, $dst\n\t"
536 "umov $itmp, $vtmp, H, 1\n\t"
537 "mulw $dst, $itmp, $dst\n\t"
538 "sxth $dst, $dst\t# mul reduction4S"
539 %}
540 ins_encode %{
541 __ ins(as_FloatRegister($vtmp$$reg), __ S,
542 as_FloatRegister($vsrc$$reg), 0, 1);
543 __ mulv(as_FloatRegister($vtmp$$reg), __ T4H,
544 as_FloatRegister($vtmp$$reg), as_FloatRegister($vsrc$$reg));
545 __ umov($itmp$$Register, as_FloatRegister($vtmp$$reg), __ H, 0);
546 __ mulw($dst$$Register, $itmp$$Register, $isrc$$Register);
547 __ sxth($dst$$Register, $dst$$Register);
548 __ umov($itmp$$Register, as_FloatRegister($vtmp$$reg), __ H, 1);
549 __ mulw($dst$$Register, $itmp$$Register, $dst$$Register);
550 __ sxth($dst$$Register, $dst$$Register);
551 %}
552 ins_pipe(pipe_slow);
553 %}
554
555 instruct reduce_mul8S(iRegINoSp dst, iRegIorL2I isrc, vecX vsrc, vecX vtmp1, vecX vtmp2, iRegINoSp itmp)
556 %{
557 predicate(n->in(2)->bottom_type()->is_vect()->element_basic_type() == T_SHORT);
558 match(Set dst (MulReductionVI isrc vsrc));
559 ins_cost(INSN_COST);
560 effect(TEMP_DEF dst, TEMP vtmp1, TEMP vtmp2, TEMP itmp);
561 format %{ "ins $vtmp1, D, $vsrc, 0, 1\n\t"
562 "mulv $vtmp1, T4H, $vtmp1, $vsrc\n\t"
563 "ins $vtmp2, S, $vtmp1, 0, 1\n\t"
564 "mulv $vtmp2, T4H, $vtmp2, $vtmp1\n\t"
565 "umov $itmp, $vtmp2, H, 0\n\t"
566 "mulw $dst, $itmp, $isrc\n\t"
567 "sxth $dst, $dst\n\t"
568 "umov $itmp, $vtmp2, H, 1\n\t"
569 "mulw $dst, $itmp, $dst\n\t"
570 "sxth $dst, $dst\t# mul reduction8S"
571 %}
572 ins_encode %{
573 __ ins(as_FloatRegister($vtmp1$$reg), __ D,
574 as_FloatRegister($vsrc$$reg), 0, 1);
575 __ mulv(as_FloatRegister($vtmp1$$reg), __ T4H,
576 as_FloatRegister($vtmp1$$reg), as_FloatRegister($vsrc$$reg));
577 __ ins(as_FloatRegister($vtmp2$$reg), __ S,
578 as_FloatRegister($vtmp1$$reg), 0, 1);
579 __ mulv(as_FloatRegister($vtmp2$$reg), __ T4H,
580 as_FloatRegister($vtmp2$$reg), as_FloatRegister($vtmp1$$reg));
581 __ umov($itmp$$Register, as_FloatRegister($vtmp2$$reg), __ H, 0);
582 __ mulw($dst$$Register, $itmp$$Register, $isrc$$Register);
583 __ sxth($dst$$Register, $dst$$Register);
584 __ umov($itmp$$Register, as_FloatRegister($vtmp2$$reg), __ H, 1);
585 __ mulw($dst$$Register, $itmp$$Register, $dst$$Register);
586 __ sxth($dst$$Register, $dst$$Register);
587 %}
588 ins_pipe(pipe_slow);
589 %}
590
591 instruct reduce_mul2L(iRegLNoSp dst, iRegL isrc, vecX vsrc, iRegLNoSp tmp)
592 %{
593 match(Set dst (MulReductionVL isrc vsrc));
594 ins_cost(INSN_COST);
595 effect(TEMP_DEF dst, TEMP tmp);
596 format %{ "umov $tmp, $vsrc, D, 0\n\t"
597 "mul $dst, $isrc, $tmp\n\t"
598 "umov $tmp, $vsrc, D, 1\n\t"
599 "mul $dst, $dst, $tmp\t# mul reduction2L"
600 %}
601 ins_encode %{
602 __ umov($tmp$$Register, as_FloatRegister($vsrc$$reg), __ D, 0);
603 __ mul($dst$$Register, $isrc$$Register, $tmp$$Register);
604 __ umov($tmp$$Register, as_FloatRegister($vsrc$$reg), __ D, 1);
605 __ mul($dst$$Register, $dst$$Register, $tmp$$Register);
606 %}
607 ins_pipe(pipe_slow);
608 %}
609
610 instruct reduce_max8B(iRegINoSp dst, iRegIorL2I isrc, vecD vsrc, vecD tmp, rFlagsReg cr)
611 %{
612 predicate(n->in(2)->bottom_type()->is_vect()->element_basic_type() == T_BYTE);
613 match(Set dst (MaxReductionV isrc vsrc));
614 ins_cost(INSN_COST);
615 effect(TEMP_DEF dst, TEMP tmp, KILL cr);
616 format %{ "smaxv $tmp, T8B, $vsrc\n\t"
617 "smov $dst, $tmp, B, 0\n\t"
618 "cmpw $dst, $isrc\n\t"
619 "cselw $dst, $dst, $isrc GT\t# max reduction8B"
620 %}
621 ins_encode %{
622 __ smaxv(as_FloatRegister($tmp$$reg), __ T8B, as_FloatRegister($vsrc$$reg));
623 __ smov(as_Register($dst$$reg), as_FloatRegister($tmp$$reg), __ B, 0);
624 __ cmpw(as_Register($dst$$reg), as_Register($isrc$$reg));
625 __ cselw(as_Register($dst$$reg), as_Register($dst$$reg), as_Register($isrc$$reg), Assembler::GT);
626 %}
627 ins_pipe(pipe_slow);
628 %}
629
630 instruct reduce_max16B(iRegINoSp dst, iRegIorL2I isrc, vecX vsrc, vecX tmp, rFlagsReg cr)
631 %{
632 predicate(n->in(2)->bottom_type()->is_vect()->element_basic_type() == T_BYTE);
633 match(Set dst (MaxReductionV isrc vsrc));
634 ins_cost(INSN_COST);
635 effect(TEMP_DEF dst, TEMP tmp, KILL cr);
636 format %{ "smaxv $tmp, T16B, $vsrc\n\t"
637 "smov $dst, $tmp, B, 0\n\t"
638 "cmpw $dst, $isrc\n\t"
639 "cselw $dst, $dst, $isrc GT\t# max reduction16B"
640 %}
641 ins_encode %{
642 __ smaxv(as_FloatRegister($tmp$$reg), __ T16B, as_FloatRegister($vsrc$$reg));
643 __ smov(as_Register($dst$$reg), as_FloatRegister($tmp$$reg), __ B, 0);
644 __ cmpw(as_Register($dst$$reg), as_Register($isrc$$reg));
645 __ cselw(as_Register($dst$$reg), as_Register($dst$$reg), as_Register($isrc$$reg), Assembler::GT);
646 %}
647 ins_pipe(pipe_slow);
648 %}
649
650 instruct reduce_max4S(iRegINoSp dst, iRegIorL2I isrc, vecD vsrc, vecD tmp, rFlagsReg cr)
651 %{
652 predicate(n->in(2)->bottom_type()->is_vect()->element_basic_type() == T_SHORT);
653 match(Set dst (MaxReductionV isrc vsrc));
654 ins_cost(INSN_COST);
655 effect(TEMP_DEF dst, TEMP tmp, KILL cr);
656 format %{ "smaxv $tmp, T4H, $vsrc\n\t"
657 "smov $dst, $tmp, H, 0\n\t"
658 "cmpw $dst, $isrc\n\t"
659 "cselw $dst, $dst, $isrc GT\t# max reduction4S"
660 %}
661 ins_encode %{
662 __ smaxv(as_FloatRegister($tmp$$reg), __ T4H, as_FloatRegister($vsrc$$reg));
663 __ smov(as_Register($dst$$reg), as_FloatRegister($tmp$$reg), __ H, 0);
664 __ cmpw(as_Register($dst$$reg), as_Register($isrc$$reg));
665 __ cselw(as_Register($dst$$reg), as_Register($dst$$reg), as_Register($isrc$$reg), Assembler::GT);
666 %}
667 ins_pipe(pipe_slow);
668 %}
669
670 instruct reduce_max8S(iRegINoSp dst, iRegIorL2I isrc, vecX vsrc, vecX tmp, rFlagsReg cr)
671 %{
672 predicate(n->in(2)->bottom_type()->is_vect()->element_basic_type() == T_SHORT);
673 match(Set dst (MaxReductionV isrc vsrc));
674 ins_cost(INSN_COST);
675 effect(TEMP_DEF dst, TEMP tmp, KILL cr);
676 format %{ "smaxv $tmp, T8H, $vsrc\n\t"
677 "smov $dst, $tmp, H, 0\n\t"
678 "cmpw $dst, $isrc\n\t"
679 "cselw $dst, $dst, $isrc GT\t# max reduction8S"
680 %}
681 ins_encode %{
682 __ smaxv(as_FloatRegister($tmp$$reg), __ T8H, as_FloatRegister($vsrc$$reg));
683 __ smov(as_Register($dst$$reg), as_FloatRegister($tmp$$reg), __ H, 0);
684 __ cmpw(as_Register($dst$$reg), as_Register($isrc$$reg));
685 __ cselw(as_Register($dst$$reg), as_Register($dst$$reg), as_Register($isrc$$reg), Assembler::GT);
686 %}
687 ins_pipe(pipe_slow);
688 %}
689
690 instruct reduce_max4I(iRegINoSp dst, iRegIorL2I isrc, vecX vsrc, vecX tmp, rFlagsReg cr)
691 %{
692 predicate(n->in(2)->bottom_type()->is_vect()->element_basic_type() == T_INT);
693 match(Set dst (MaxReductionV isrc vsrc));
694 ins_cost(INSN_COST);
695 effect(TEMP_DEF dst, TEMP tmp, KILL cr);
696 format %{ "smaxv $tmp, T4S, $vsrc\n\t"
697 "umov $dst, $tmp, S, 0\n\t"
698 "cmpw $dst, $isrc\n\t"
699 "cselw $dst, $dst, $isrc GT\t# max reduction4I"
700 %}
701 ins_encode %{
702 __ smaxv(as_FloatRegister($tmp$$reg), __ T4S, as_FloatRegister($vsrc$$reg));
703 __ umov(as_Register($dst$$reg), as_FloatRegister($tmp$$reg), __ S, 0);
704 __ cmpw(as_Register($dst$$reg), as_Register($isrc$$reg));
705 __ cselw(as_Register($dst$$reg), as_Register($dst$$reg), as_Register($isrc$$reg), Assembler::GT);
706 %}
707 ins_pipe(pipe_slow);
708 %}
709
710 instruct reduce_min8B(iRegINoSp dst, iRegIorL2I isrc, vecD vsrc, vecD tmp, rFlagsReg cr)
711 %{
712 predicate(n->in(2)->bottom_type()->is_vect()->element_basic_type() == T_BYTE);
713 match(Set dst (MinReductionV isrc vsrc));
714 ins_cost(INSN_COST);
715 effect(TEMP_DEF dst, TEMP tmp, KILL cr);
716 format %{ "sminv $tmp, T8B, $vsrc\n\t"
717 "smov $dst, $tmp, B, 0\n\t"
718 "cmpw $dst, $isrc\n\t"
719 "cselw $dst, $dst, $isrc LT\t# min reduction8B"
720 %}
721 ins_encode %{
722 __ sminv(as_FloatRegister($tmp$$reg), __ T8B, as_FloatRegister($vsrc$$reg));
723 __ smov(as_Register($dst$$reg), as_FloatRegister($tmp$$reg), __ B, 0);
724 __ cmpw(as_Register($dst$$reg), as_Register($isrc$$reg));
725 __ cselw(as_Register($dst$$reg), as_Register($dst$$reg), as_Register($isrc$$reg), Assembler::LT);
726 %}
727 ins_pipe(pipe_slow);
728 %}
729
730 instruct reduce_min16B(iRegINoSp dst, iRegIorL2I isrc, vecX vsrc, vecX tmp, rFlagsReg cr)
731 %{
732 predicate(n->in(2)->bottom_type()->is_vect()->element_basic_type() == T_BYTE);
733 match(Set dst (MinReductionV isrc vsrc));
734 ins_cost(INSN_COST);
735 effect(TEMP_DEF dst, TEMP tmp, KILL cr);
736 format %{ "sminv $tmp, T16B, $vsrc\n\t"
737 "smov $dst, $tmp, B, 0\n\t"
738 "cmpw $dst, $isrc\n\t"
739 "cselw $dst, $dst, $isrc LT\t# min reduction16B"
740 %}
741 ins_encode %{
742 __ sminv(as_FloatRegister($tmp$$reg), __ T16B, as_FloatRegister($vsrc$$reg));
743 __ smov(as_Register($dst$$reg), as_FloatRegister($tmp$$reg), __ B, 0);
744 __ cmpw(as_Register($dst$$reg), as_Register($isrc$$reg));
745 __ cselw(as_Register($dst$$reg), as_Register($dst$$reg), as_Register($isrc$$reg), Assembler::LT);
746 %}
747 ins_pipe(pipe_slow);
748 %}
749
750 instruct reduce_min4S(iRegINoSp dst, iRegIorL2I isrc, vecD vsrc, vecD tmp, rFlagsReg cr)
751 %{
752 predicate(n->in(2)->bottom_type()->is_vect()->element_basic_type() == T_SHORT);
753 match(Set dst (MinReductionV isrc vsrc));
754 ins_cost(INSN_COST);
755 effect(TEMP_DEF dst, TEMP tmp, KILL cr);
756 format %{ "sminv $tmp, T4H, $vsrc\n\t"
757 "smov $dst, $tmp, H, 0\n\t"
758 "cmpw $dst, $isrc\n\t"
759 "cselw $dst, $dst, $isrc LT\t# min reduction4S"
760 %}
761 ins_encode %{
762 __ sminv(as_FloatRegister($tmp$$reg), __ T4H, as_FloatRegister($vsrc$$reg));
763 __ smov(as_Register($dst$$reg), as_FloatRegister($tmp$$reg), __ H, 0);
764 __ cmpw(as_Register($dst$$reg), as_Register($isrc$$reg));
765 __ cselw(as_Register($dst$$reg), as_Register($dst$$reg), as_Register($isrc$$reg), Assembler::LT);
766 %}
767 ins_pipe(pipe_slow);
768 %}
769
770 instruct reduce_min8S(iRegINoSp dst, iRegIorL2I isrc, vecX vsrc, vecX tmp, rFlagsReg cr)
771 %{
772 predicate(n->in(2)->bottom_type()->is_vect()->element_basic_type() == T_SHORT);
773 match(Set dst (MinReductionV isrc vsrc));
774 ins_cost(INSN_COST);
775 effect(TEMP_DEF dst, TEMP tmp, KILL cr);
776 format %{ "sminv $tmp, T8H, $vsrc\n\t"
777 "smov $dst, $tmp, H, 0\n\t"
778 "cmpw $dst, $isrc\n\t"
779 "cselw $dst, $dst, $isrc LT\t# min reduction8S"
780 %}
781 ins_encode %{
782 __ sminv(as_FloatRegister($tmp$$reg), __ T8H, as_FloatRegister($vsrc$$reg));
783 __ smov(as_Register($dst$$reg), as_FloatRegister($tmp$$reg), __ H, 0);
784 __ cmpw(as_Register($dst$$reg), as_Register($isrc$$reg));
785 __ cselw(as_Register($dst$$reg), as_Register($dst$$reg), as_Register($isrc$$reg), Assembler::LT);
786 %}
787 ins_pipe(pipe_slow);
788 %}
789
790 instruct reduce_min4I(iRegINoSp dst, iRegIorL2I isrc, vecX vsrc, vecX tmp, rFlagsReg cr)
791 %{
792 predicate(n->in(2)->bottom_type()->is_vect()->element_basic_type() == T_INT);
793 match(Set dst (MinReductionV isrc vsrc));
794 ins_cost(INSN_COST);
795 effect(TEMP_DEF dst, TEMP tmp, KILL cr);
796 format %{ "sminv $tmp, T4S, $vsrc\n\t"
797 "umov $dst, $tmp, S, 0\n\t"
798 "cmpw $dst, $isrc\n\t"
799 "cselw $dst, $dst, $isrc LT\t# min reduction4I"
800 %}
801 ins_encode %{
802 __ sminv(as_FloatRegister($tmp$$reg), __ T4S, as_FloatRegister($vsrc$$reg));
803 __ umov(as_Register($dst$$reg), as_FloatRegister($tmp$$reg), __ S, 0);
804 __ cmpw(as_Register($dst$$reg), as_Register($isrc$$reg));
805 __ cselw(as_Register($dst$$reg), as_Register($dst$$reg), as_Register($isrc$$reg), Assembler::LT);
806 %}
807 ins_pipe(pipe_slow);
808 %}
809
810 instruct reduce_max2I(iRegINoSp dst, iRegIorL2I isrc, vecD vsrc, vecX tmp, rFlagsReg cr)
811 %{
812 predicate(n->in(2)->bottom_type()->is_vect()->element_basic_type() == T_INT);
813 match(Set dst (MaxReductionV isrc vsrc));
814 ins_cost(INSN_COST);
815 effect(TEMP_DEF dst, TEMP tmp, KILL cr);
816 format %{ "dup $tmp, T2D, $vsrc\n\t"
817 "smaxv $tmp, T4S, $tmp\n\t"
818 "umov $dst, $tmp, S, 0\n\t"
819 "cmpw $dst, $isrc\n\t"
820 "cselw $dst, $dst, $isrc GT\t# max reduction2I"
821 %}
822 ins_encode %{
823 __ dup(as_FloatRegister($tmp$$reg), __ T2D, as_FloatRegister($vsrc$$reg));
824 __ smaxv(as_FloatRegister($tmp$$reg), __ T4S, as_FloatRegister($tmp$$reg));
825 __ umov(as_Register($dst$$reg), as_FloatRegister($tmp$$reg), __ S, 0);
826 __ cmpw(as_Register($dst$$reg), as_Register($isrc$$reg));
827 __ cselw(as_Register($dst$$reg), as_Register($dst$$reg), as_Register($isrc$$reg), Assembler::GT);
828 %}
829 ins_pipe(pipe_slow);
830 %}
831
832 instruct reduce_min2I(iRegINoSp dst, iRegIorL2I isrc, vecD vsrc, vecX tmp, rFlagsReg cr)
833 %{
834 predicate(n->in(2)->bottom_type()->is_vect()->element_basic_type() == T_INT);
835 match(Set dst (MinReductionV isrc vsrc));
836 ins_cost(INSN_COST);
837 effect(TEMP_DEF dst, TEMP tmp, KILL cr);
838 format %{ "dup $tmp, T2D, $vsrc\n\t"
839 "sminv $tmp, T4S, $tmp\n\t"
840 "umov $dst, $tmp, S, 0\n\t"
841 "cmpw $dst, $isrc\n\t"
842 "cselw $dst, $dst, $isrc LT\t# min reduction2I"
843 %}
844 ins_encode %{
845 __ dup(as_FloatRegister($tmp$$reg), __ T2D, as_FloatRegister($vsrc$$reg));
846 __ sminv(as_FloatRegister($tmp$$reg), __ T4S, as_FloatRegister($tmp$$reg));
847 __ umov(as_Register($dst$$reg), as_FloatRegister($tmp$$reg), __ S, 0);
848 __ cmpw(as_Register($dst$$reg), as_Register($isrc$$reg));
849 __ cselw(as_Register($dst$$reg), as_Register($dst$$reg), as_Register($isrc$$reg), Assembler::LT);
850 %}
851 ins_pipe(pipe_slow);
852 %}
853
854 instruct reduce_max2L(iRegLNoSp dst, iRegL isrc, vecX vsrc, iRegLNoSp tmp, rFlagsReg cr)
855 %{
856 predicate(n->in(2)->bottom_type()->is_vect()->element_basic_type() == T_LONG);
857 match(Set dst (MaxReductionV isrc vsrc));
858 ins_cost(INSN_COST);
859 effect(TEMP_DEF dst, TEMP tmp, KILL cr);
860 format %{ "umov $tmp, $vsrc, D, 0\n\t"
861 "cmp $isrc,$tmp\n\t"
862 "csel $dst, $isrc, $tmp GT\n\t"
863 "umov $tmp, $vsrc, D, 1\n\t"
864 "cmp $dst, $tmp\n\t"
865 "csel $dst, $dst, $tmp GT\t# max reduction2L"
866 %}
867 ins_encode %{
868 __ umov(as_Register($tmp$$reg), as_FloatRegister($vsrc$$reg), __ D, 0);
869 __ cmp(as_Register($isrc$$reg), as_Register($tmp$$reg));
870 __ csel(as_Register($dst$$reg), as_Register($isrc$$reg), as_Register($tmp$$reg), Assembler::GT);
871 __ umov(as_Register($tmp$$reg), as_FloatRegister($vsrc$$reg), __ D, 1);
872 __ cmp(as_Register($dst$$reg), as_Register($tmp$$reg));
873 __ csel(as_Register($dst$$reg), as_Register($dst$$reg), as_Register($tmp$$reg), Assembler::GT);
874 %}
875 ins_pipe(pipe_slow);
876 %}
877
878 instruct reduce_min2L(iRegLNoSp dst, iRegL isrc, vecX vsrc, iRegLNoSp tmp, rFlagsReg cr)
879 %{
880 predicate(n->in(2)->bottom_type()->is_vect()->element_basic_type() == T_LONG);
881 match(Set dst (MinReductionV isrc vsrc));
882 ins_cost(INSN_COST);
883 effect(TEMP_DEF dst, TEMP tmp, KILL cr);
884 format %{ "umov $tmp, $vsrc, D, 0\n\t"
885 "cmp $isrc,$tmp\n\t"
886 "csel $dst, $isrc, $tmp LT\n\t"
887 "umov $tmp, $vsrc, D, 1\n\t"
888 "cmp $dst, $tmp\n\t"
889 "csel $dst, $dst, $tmp LT\t# min reduction2L"
890 %}
891 ins_encode %{
892 __ umov(as_Register($tmp$$reg), as_FloatRegister($vsrc$$reg), __ D, 0);
893 __ cmp(as_Register($isrc$$reg), as_Register($tmp$$reg));
894 __ csel(as_Register($dst$$reg), as_Register($isrc$$reg), as_Register($tmp$$reg), Assembler::LT);
895 __ umov(as_Register($tmp$$reg), as_FloatRegister($vsrc$$reg), __ D, 1);
896 __ cmp(as_Register($dst$$reg), as_Register($tmp$$reg));
897 __ csel(as_Register($dst$$reg), as_Register($dst$$reg), as_Register($tmp$$reg), Assembler::LT);
898 %}
899 ins_pipe(pipe_slow);
900 %}
901
902 instruct reduce_and8B(iRegINoSp dst, iRegIorL2I isrc, vecD vsrc, iRegINoSp tmp)
903 %{
904 predicate(n->in(2)->bottom_type()->is_vect()->element_basic_type() == T_BYTE);
905 match(Set dst (AndReductionV isrc vsrc));
906 ins_cost(INSN_COST);
907 effect(TEMP_DEF dst, TEMP tmp);
908 format %{ "umov $tmp, $vsrc, S, 0\n\t"
909 "umov $dst, $vsrc, S, 1\n\t"
910 "andw $dst, $dst, $tmp\n\t"
911 "andw $dst, $dst, $dst, LSR #16\n\t"
912 "andw $dst, $dst, $dst, LSR #8\n\t"
913 "andw $dst, $isrc, $dst\n\t"
914 "sxtb $dst, $dst\t# and reduction8B"
915 %}
916 ins_encode %{
917 __ umov($tmp$$Register, as_FloatRegister($vsrc$$reg), __ S, 0);
918 __ umov($dst$$Register, as_FloatRegister($vsrc$$reg), __ S, 1);
919 __ andw($dst$$Register, $dst$$Register, $tmp$$Register);
920 __ andw($dst$$Register, $dst$$Register, $dst$$Register, Assembler::LSR, 16);
921 __ andw($dst$$Register, $dst$$Register, $dst$$Register, Assembler::LSR, 8);
922 __ andw($dst$$Register, $isrc$$Register, $dst$$Register);
923 __ sxtb($dst$$Register, $dst$$Register);
924 %}
925 ins_pipe(pipe_slow);
926 %}
927
928 instruct reduce_orr8B(iRegINoSp dst, iRegIorL2I isrc, vecD vsrc, iRegINoSp tmp)
929 %{
930 predicate(n->in(2)->bottom_type()->is_vect()->element_basic_type() == T_BYTE);
931 match(Set dst (OrReductionV isrc vsrc));
932 ins_cost(INSN_COST);
933 effect(TEMP_DEF dst, TEMP tmp);
934 format %{ "umov $tmp, $vsrc, S, 0\n\t"
935 "umov $dst, $vsrc, S, 1\n\t"
936 "orrw $dst, $dst, $tmp\n\t"
937 "orrw $dst, $dst, $dst, LSR #16\n\t"
938 "orrw $dst, $dst, $dst, LSR #8\n\t"
939 "orrw $dst, $isrc, $dst\n\t"
940 "sxtb $dst, $dst\t# orr reduction8B"
941 %}
942 ins_encode %{
943 __ umov($tmp$$Register, as_FloatRegister($vsrc$$reg), __ S, 0);
944 __ umov($dst$$Register, as_FloatRegister($vsrc$$reg), __ S, 1);
945 __ orrw($dst$$Register, $dst$$Register, $tmp$$Register);
946 __ orrw($dst$$Register, $dst$$Register, $dst$$Register, Assembler::LSR, 16);
947 __ orrw($dst$$Register, $dst$$Register, $dst$$Register, Assembler::LSR, 8);
948 __ orrw($dst$$Register, $isrc$$Register, $dst$$Register);
949 __ sxtb($dst$$Register, $dst$$Register);
950 %}
951 ins_pipe(pipe_slow);
952 %}
953
954 instruct reduce_eor8B(iRegINoSp dst, iRegIorL2I isrc, vecD vsrc, iRegINoSp tmp)
955 %{
956 predicate(n->in(2)->bottom_type()->is_vect()->element_basic_type() == T_BYTE);
957 match(Set dst (XorReductionV isrc vsrc));
958 ins_cost(INSN_COST);
959 effect(TEMP_DEF dst, TEMP tmp);
960 format %{ "umov $tmp, $vsrc, S, 0\n\t"
961 "umov $dst, $vsrc, S, 1\n\t"
962 "eorw $dst, $dst, $tmp\n\t"
963 "eorw $dst, $dst, $dst, LSR #16\n\t"
964 "eorw $dst, $dst, $dst, LSR #8\n\t"
965 "eorw $dst, $isrc, $dst\n\t"
966 "sxtb $dst, $dst\t# eor reduction8B"
967 %}
968 ins_encode %{
969 __ umov($tmp$$Register, as_FloatRegister($vsrc$$reg), __ S, 0);
970 __ umov($dst$$Register, as_FloatRegister($vsrc$$reg), __ S, 1);
971 __ eorw($dst$$Register, $dst$$Register, $tmp$$Register);
972 __ eorw($dst$$Register, $dst$$Register, $dst$$Register, Assembler::LSR, 16);
973 __ eorw($dst$$Register, $dst$$Register, $dst$$Register, Assembler::LSR, 8);
974 __ eorw($dst$$Register, $isrc$$Register, $dst$$Register);
975 __ sxtb($dst$$Register, $dst$$Register);
976 %}
977 ins_pipe(pipe_slow);
978 %}
979
980 instruct reduce_and16B(iRegINoSp dst, iRegIorL2I isrc, vecX vsrc, iRegINoSp tmp)
981 %{
982 predicate(n->in(2)->bottom_type()->is_vect()->element_basic_type() == T_BYTE);
983 match(Set dst (AndReductionV isrc vsrc));
984 ins_cost(INSN_COST);
985 effect(TEMP_DEF dst, TEMP tmp);
986 format %{ "umov $tmp, $vsrc, D, 0\n\t"
987 "umov $dst, $vsrc, D, 1\n\t"
988 "andr $dst, $dst, $tmp\n\t"
989 "andr $dst, $dst, $dst, LSR #32\n\t"
990 "andw $dst, $dst, $dst, LSR #16\n\t"
991 "andw $dst, $dst, $dst, LSR #8\n\t"
992 "andw $dst, $isrc, $dst\n\t"
993 "sxtb $dst, $dst\t# and reduction16B"
994 %}
995 ins_encode %{
996 __ umov($tmp$$Register, as_FloatRegister($vsrc$$reg), __ D, 0);
997 __ umov($dst$$Register, as_FloatRegister($vsrc$$reg), __ D, 1);
998 __ andr($dst$$Register, $dst$$Register, $tmp$$Register);
999 __ andr($dst$$Register, $dst$$Register, $dst$$Register, Assembler::LSR, 32);
1000 __ andw($dst$$Register, $dst$$Register, $dst$$Register, Assembler::LSR, 16);
1001 __ andw($dst$$Register, $dst$$Register, $dst$$Register, Assembler::LSR, 8);
1002 __ andw($dst$$Register, $isrc$$Register, $dst$$Register);
1003 __ sxtb($dst$$Register, $dst$$Register);
1004 %}
1005 ins_pipe(pipe_slow);
1006 %}
1007
1008 instruct reduce_orr16B(iRegINoSp dst, iRegIorL2I isrc, vecX vsrc, iRegINoSp tmp)
1009 %{
1010 predicate(n->in(2)->bottom_type()->is_vect()->element_basic_type() == T_BYTE);
1011 match(Set dst (OrReductionV isrc vsrc));
1012 ins_cost(INSN_COST);
1013 effect(TEMP_DEF dst, TEMP tmp);
1014 format %{ "umov $tmp, $vsrc, D, 0\n\t"
1015 "umov $dst, $vsrc, D, 1\n\t"
1016 "orr $dst, $dst, $tmp\n\t"
1017 "orr $dst, $dst, $dst, LSR #32\n\t"
1018 "orrw $dst, $dst, $dst, LSR #16\n\t"
1019 "orrw $dst, $dst, $dst, LSR #8\n\t"
1020 "orrw $dst, $isrc, $dst\n\t"
1021 "sxtb $dst, $dst\t# orr reduction16B"
1022 %}
1023 ins_encode %{
1024 __ umov($tmp$$Register, as_FloatRegister($vsrc$$reg), __ D, 0);
1025 __ umov($dst$$Register, as_FloatRegister($vsrc$$reg), __ D, 1);
1026 __ orr ($dst$$Register, $dst$$Register, $tmp$$Register);
1027 __ orr ($dst$$Register, $dst$$Register, $dst$$Register, Assembler::LSR, 32);
1028 __ orrw($dst$$Register, $dst$$Register, $dst$$Register, Assembler::LSR, 16);
1029 __ orrw($dst$$Register, $dst$$Register, $dst$$Register, Assembler::LSR, 8);
1030 __ orrw($dst$$Register, $isrc$$Register, $dst$$Register);
1031 __ sxtb($dst$$Register, $dst$$Register);
1032 %}
1033 ins_pipe(pipe_slow);
1034 %}
1035
1036 instruct reduce_eor16B(iRegINoSp dst, iRegIorL2I isrc, vecX vsrc, iRegINoSp tmp)
1037 %{
1038 predicate(n->in(2)->bottom_type()->is_vect()->element_basic_type() == T_BYTE);
1039 match(Set dst (XorReductionV isrc vsrc));
1040 ins_cost(INSN_COST);
1041 effect(TEMP_DEF dst, TEMP tmp);
1042 format %{ "umov $tmp, $vsrc, D, 0\n\t"
1043 "umov $dst, $vsrc, D, 1\n\t"
1044 "eor $dst, $dst, $tmp\n\t"
1045 "eor $dst, $dst, $dst, LSR #32\n\t"
1046 "eorw $dst, $dst, $dst, LSR #16\n\t"
1047 "eorw $dst, $dst, $dst, LSR #8\n\t"
1048 "eorw $dst, $isrc, $dst\n\t"
1049 "sxtb $dst, $dst\t# eor reduction16B"
1050 %}
1051 ins_encode %{
1052 __ umov($tmp$$Register, as_FloatRegister($vsrc$$reg), __ D, 0);
1053 __ umov($dst$$Register, as_FloatRegister($vsrc$$reg), __ D, 1);
1054 __ eor ($dst$$Register, $dst$$Register, $tmp$$Register);
1055 __ eor ($dst$$Register, $dst$$Register, $dst$$Register, Assembler::LSR, 32);
1056 __ eorw($dst$$Register, $dst$$Register, $dst$$Register, Assembler::LSR, 16);
1057 __ eorw($dst$$Register, $dst$$Register, $dst$$Register, Assembler::LSR, 8);
1058 __ eorw($dst$$Register, $isrc$$Register, $dst$$Register);
1059 __ sxtb($dst$$Register, $dst$$Register);
1060 %}
1061 ins_pipe(pipe_slow);
1062 %}
1063
1064 instruct reduce_and4S(iRegINoSp dst, iRegIorL2I isrc, vecD vsrc, iRegINoSp tmp)
1065 %{
1066 predicate(n->in(2)->bottom_type()->is_vect()->element_basic_type() == T_SHORT);
1067 match(Set dst (AndReductionV isrc vsrc));
1068 ins_cost(INSN_COST);
1069 effect(TEMP_DEF dst, TEMP tmp);
1070 format %{ "umov $tmp, $vsrc, S, 0\n\t"
1071 "umov $dst, $vsrc, S, 1\n\t"
1072 "andw $dst, $dst, $tmp\n\t"
1073 "andw $dst, $dst, $dst, LSR #16\n\t"
1074 "andw $dst, $isrc, $dst\n\t"
1075 "sxth $dst, $dst\t# and reduction4S"
1076 %}
1077 ins_encode %{
1078 __ umov($tmp$$Register, as_FloatRegister($vsrc$$reg), __ S, 0);
1079 __ umov($dst$$Register, as_FloatRegister($vsrc$$reg), __ S, 1);
1080 __ andw($dst$$Register, $dst$$Register, $tmp$$Register);
1081 __ andw($dst$$Register, $dst$$Register, $dst$$Register, Assembler::LSR, 16);
1082 __ andw($dst$$Register, $isrc$$Register, $dst$$Register);
1083 __ sxth($dst$$Register, $dst$$Register);
1084 %}
1085 ins_pipe(pipe_slow);
1086 %}
1087
1088 instruct reduce_orr4S(iRegINoSp dst, iRegIorL2I isrc, vecD vsrc, iRegINoSp tmp)
1089 %{
1090 predicate(n->in(2)->bottom_type()->is_vect()->element_basic_type() == T_SHORT);
1091 match(Set dst (OrReductionV isrc vsrc));
1092 ins_cost(INSN_COST);
1093 effect(TEMP_DEF dst, TEMP tmp);
1094 format %{ "umov $tmp, $vsrc, S, 0\n\t"
1095 "umov $dst, $vsrc, S, 1\n\t"
1096 "orrw $dst, $dst, $tmp\n\t"
1097 "orrw $dst, $dst, $dst, LSR #16\n\t"
1098 "orrw $dst, $isrc, $dst\n\t"
1099 "sxth $dst, $dst\t# orr reduction4S"
1100 %}
1101 ins_encode %{
1102 __ umov($tmp$$Register, as_FloatRegister($vsrc$$reg), __ S, 0);
1103 __ umov($dst$$Register, as_FloatRegister($vsrc$$reg), __ S, 1);
1104 __ orrw($dst$$Register, $dst$$Register, $tmp$$Register);
1105 __ orrw($dst$$Register, $dst$$Register, $dst$$Register, Assembler::LSR, 16);
1106 __ orrw($dst$$Register, $isrc$$Register, $dst$$Register);
1107 __ sxth($dst$$Register, $dst$$Register);
1108 %}
1109 ins_pipe(pipe_slow);
1110 %}
1111
1112 instruct reduce_eor4S(iRegINoSp dst, iRegIorL2I isrc, vecD vsrc, iRegINoSp tmp)
1113 %{
1114 predicate(n->in(2)->bottom_type()->is_vect()->element_basic_type() == T_SHORT);
1115 match(Set dst (XorReductionV isrc vsrc));
1116 ins_cost(INSN_COST);
1117 effect(TEMP_DEF dst, TEMP tmp);
1118 format %{ "umov $tmp, $vsrc, S, 0\n\t"
1119 "umov $dst, $vsrc, S, 1\n\t"
1120 "eorw $dst, $dst, $tmp\n\t"
1121 "eorw $dst, $dst, $dst, LSR #16\n\t"
1122 "eorw $dst, $isrc, $dst\n\t"
1123 "sxth $dst, $dst\t# eor reduction4S"
1124 %}
1125 ins_encode %{
1126 __ umov($tmp$$Register, as_FloatRegister($vsrc$$reg), __ S, 0);
1127 __ umov($dst$$Register, as_FloatRegister($vsrc$$reg), __ S, 1);
1128 __ eorw($dst$$Register, $dst$$Register, $tmp$$Register);
1129 __ eorw($dst$$Register, $dst$$Register, $dst$$Register, Assembler::LSR, 16);
1130 __ eorw($dst$$Register, $isrc$$Register, $dst$$Register);
1131 __ sxth($dst$$Register, $dst$$Register);
1132 %}
1133 ins_pipe(pipe_slow);
1134 %}
1135
1136 instruct reduce_and8S(iRegINoSp dst, iRegIorL2I isrc, vecX vsrc, iRegINoSp tmp)
1137 %{
1138 predicate(n->in(2)->bottom_type()->is_vect()->element_basic_type() == T_SHORT);
1139 match(Set dst (AndReductionV isrc vsrc));
1140 ins_cost(INSN_COST);
1141 effect(TEMP_DEF dst, TEMP tmp);
1142 format %{ "umov $tmp, $vsrc, D, 0\n\t"
1143 "umov $dst, $vsrc, D, 1\n\t"
1144 "andr $dst, $dst, $tmp\n\t"
1145 "andr $dst, $dst, $dst, LSR #32\n\t"
1146 "andw $dst, $dst, $dst, LSR #16\n\t"
1147 "andw $dst, $isrc, $dst\n\t"
1148 "sxth $dst, $dst\t# and reduction8S"
1149 %}
1150 ins_encode %{
1151 __ umov($tmp$$Register, as_FloatRegister($vsrc$$reg), __ D, 0);
1152 __ umov($dst$$Register, as_FloatRegister($vsrc$$reg), __ D, 1);
1153 __ andr($dst$$Register, $dst$$Register, $tmp$$Register);
1154 __ andr($dst$$Register, $dst$$Register, $dst$$Register, Assembler::LSR, 32);
1155 __ andw($dst$$Register, $dst$$Register, $dst$$Register, Assembler::LSR, 16);
1156 __ andw($dst$$Register, $isrc$$Register, $dst$$Register);
1157 __ sxth($dst$$Register, $dst$$Register);
1158 %}
1159 ins_pipe(pipe_slow);
1160 %}
1161
1162 instruct reduce_orr8S(iRegINoSp dst, iRegIorL2I isrc, vecX vsrc, iRegINoSp tmp)
1163 %{
1164 predicate(n->in(2)->bottom_type()->is_vect()->element_basic_type() == T_SHORT);
1165 match(Set dst (OrReductionV isrc vsrc));
1166 ins_cost(INSN_COST);
1167 effect(TEMP_DEF dst, TEMP tmp);
1168 format %{ "umov $tmp, $vsrc, D, 0\n\t"
1169 "umov $dst, $vsrc, D, 1\n\t"
1170 "orr $dst, $dst, $tmp\n\t"
1171 "orr $dst, $dst, $dst, LSR #32\n\t"
1172 "orrw $dst, $dst, $dst, LSR #16\n\t"
1173 "orrw $dst, $isrc, $dst\n\t"
1174 "sxth $dst, $dst\t# orr reduction8S"
1175 %}
1176 ins_encode %{
1177 __ umov($tmp$$Register, as_FloatRegister($vsrc$$reg), __ D, 0);
1178 __ umov($dst$$Register, as_FloatRegister($vsrc$$reg), __ D, 1);
1179 __ orr ($dst$$Register, $dst$$Register, $tmp$$Register);
1180 __ orr ($dst$$Register, $dst$$Register, $dst$$Register, Assembler::LSR, 32);
1181 __ orrw($dst$$Register, $dst$$Register, $dst$$Register, Assembler::LSR, 16);
1182 __ orrw($dst$$Register, $isrc$$Register, $dst$$Register);
1183 __ sxth($dst$$Register, $dst$$Register);
1184 %}
1185 ins_pipe(pipe_slow);
1186 %}
1187
1188 instruct reduce_eor8S(iRegINoSp dst, iRegIorL2I isrc, vecX vsrc, iRegINoSp tmp)
1189 %{
1190 predicate(n->in(2)->bottom_type()->is_vect()->element_basic_type() == T_SHORT);
1191 match(Set dst (XorReductionV isrc vsrc));
1192 ins_cost(INSN_COST);
1193 effect(TEMP_DEF dst, TEMP tmp);
1194 format %{ "umov $tmp, $vsrc, D, 0\n\t"
1195 "umov $dst, $vsrc, D, 1\n\t"
1196 "eor $dst, $dst, $tmp\n\t"
1197 "eor $dst, $dst, $dst, LSR #32\n\t"
1198 "eorw $dst, $dst, $dst, LSR #16\n\t"
1199 "eorw $dst, $isrc, $dst\n\t"
1200 "sxth $dst, $dst\t# eor reduction8S"
1201 %}
1202 ins_encode %{
1203 __ umov($tmp$$Register, as_FloatRegister($vsrc$$reg), __ D, 0);
1204 __ umov($dst$$Register, as_FloatRegister($vsrc$$reg), __ D, 1);
1205 __ eor ($dst$$Register, $dst$$Register, $tmp$$Register);
1206 __ eor ($dst$$Register, $dst$$Register, $dst$$Register, Assembler::LSR, 32);
1207 __ eorw($dst$$Register, $dst$$Register, $dst$$Register, Assembler::LSR, 16);
1208 __ eorw($dst$$Register, $isrc$$Register, $dst$$Register);
1209 __ sxth($dst$$Register, $dst$$Register);
1210 %}
1211 ins_pipe(pipe_slow);
1212 %}
1213
1214 instruct reduce_and2I(iRegINoSp dst, iRegIorL2I isrc, vecD vsrc, iRegINoSp tmp)
1215 %{
1216 predicate(n->in(2)->bottom_type()->is_vect()->element_basic_type() == T_INT);
1217 match(Set dst (AndReductionV isrc vsrc));
1218 ins_cost(INSN_COST);
1219 effect(TEMP_DEF dst, TEMP tmp);
1220 format %{ "umov $tmp, $vsrc, S, 0\n\t"
1221 "andw $dst, $tmp, $isrc\n\t"
1222 "umov $tmp, $vsrc, S, 1\n\t"
1223 "andw $dst, $tmp, $dst\t# and reduction2I"
1224 %}
1225 ins_encode %{
1226 __ umov($tmp$$Register, as_FloatRegister($vsrc$$reg), __ S, 0);
1227 __ andw($dst$$Register, $tmp$$Register, $isrc$$Register);
1228 __ umov($tmp$$Register, as_FloatRegister($vsrc$$reg), __ S, 1);
1229 __ andw($dst$$Register, $tmp$$Register, $dst$$Register);
1230 %}
1231 ins_pipe(pipe_slow);
1232 %}
1233
1234 instruct reduce_orr2I(iRegINoSp dst, iRegIorL2I isrc, vecD vsrc, iRegINoSp tmp)
1235 %{
1236 predicate(n->in(2)->bottom_type()->is_vect()->element_basic_type() == T_INT);
1237 match(Set dst (OrReductionV isrc vsrc));
1238 ins_cost(INSN_COST);
1239 effect(TEMP_DEF dst, TEMP tmp);
1240 format %{ "umov $tmp, $vsrc, S, 0\n\t"
1241 "orrw $dst, $tmp, $isrc\n\t"
1242 "umov $tmp, $vsrc, S, 1\n\t"
1243 "orrw $dst, $tmp, $dst\t# orr reduction2I"
1244 %}
1245 ins_encode %{
1246 __ umov($tmp$$Register, as_FloatRegister($vsrc$$reg), __ S, 0);
1247 __ orrw($dst$$Register, $tmp$$Register, $isrc$$Register);
1248 __ umov($tmp$$Register, as_FloatRegister($vsrc$$reg), __ S, 1);
1249 __ orrw($dst$$Register, $tmp$$Register, $dst$$Register);
1250 %}
1251 ins_pipe(pipe_slow);
1252 %}
1253
1254 instruct reduce_eor2I(iRegINoSp dst, iRegIorL2I isrc, vecD vsrc, iRegINoSp tmp)
1255 %{
1256 predicate(n->in(2)->bottom_type()->is_vect()->element_basic_type() == T_INT);
1257 match(Set dst (XorReductionV isrc vsrc));
1258 ins_cost(INSN_COST);
1259 effect(TEMP_DEF dst, TEMP tmp);
1260 format %{ "umov $tmp, $vsrc, S, 0\n\t"
1261 "eorw $dst, $tmp, $isrc\n\t"
1262 "umov $tmp, $vsrc, S, 1\n\t"
1263 "eorw $dst, $tmp, $dst\t# eor reduction2I"
1264 %}
1265 ins_encode %{
1266 __ umov($tmp$$Register, as_FloatRegister($vsrc$$reg), __ S, 0);
1267 __ eorw($dst$$Register, $tmp$$Register, $isrc$$Register);
1268 __ umov($tmp$$Register, as_FloatRegister($vsrc$$reg), __ S, 1);
1269 __ eorw($dst$$Register, $tmp$$Register, $dst$$Register);
1270 %}
1271 ins_pipe(pipe_slow);
1272 %}
1273
1274 instruct reduce_and4I(iRegINoSp dst, iRegIorL2I isrc, vecX vsrc, iRegINoSp tmp)
1275 %{
1276 predicate(n->in(2)->bottom_type()->is_vect()->element_basic_type() == T_INT);
1277 match(Set dst (AndReductionV isrc vsrc));
1278 ins_cost(INSN_COST);
1279 effect(TEMP_DEF dst, TEMP tmp);
1280 format %{ "umov $tmp, $vsrc, D, 0\n\t"
1281 "umov $dst, $vsrc, D, 1\n\t"
1282 "andr $dst, $dst, $tmp\n\t"
1283 "andr $dst, $dst, $dst, LSR #32\n\t"
1284 "andw $dst, $isrc, $dst\t# and reduction4I"
1285 %}
1286 ins_encode %{
1287 __ umov($tmp$$Register, as_FloatRegister($vsrc$$reg), __ D, 0);
1288 __ umov($dst$$Register, as_FloatRegister($vsrc$$reg), __ D, 1);
1289 __ andr($dst$$Register, $dst$$Register, $tmp$$Register);
1290 __ andr($dst$$Register, $dst$$Register, $dst$$Register, Assembler::LSR, 32);
1291 __ andw($dst$$Register, $isrc$$Register, $dst$$Register);
1292 %}
1293 ins_pipe(pipe_slow);
1294 %}
1295
1296 instruct reduce_orr4I(iRegINoSp dst, iRegIorL2I isrc, vecX vsrc, iRegINoSp tmp)
1297 %{
1298 predicate(n->in(2)->bottom_type()->is_vect()->element_basic_type() == T_INT);
1299 match(Set dst (OrReductionV isrc vsrc));
1300 ins_cost(INSN_COST);
1301 effect(TEMP_DEF dst, TEMP tmp);
1302 format %{ "umov $tmp, $vsrc, D, 0\n\t"
1303 "umov $dst, $vsrc, D, 1\n\t"
1304 "orr $dst, $dst, $tmp\n\t"
1305 "orr $dst, $dst, $dst, LSR #32\n\t"
1306 "orrw $dst, $isrc, $dst\t# orr reduction4I"
1307 %}
1308 ins_encode %{
1309 __ umov($tmp$$Register, as_FloatRegister($vsrc$$reg), __ D, 0);
1310 __ umov($dst$$Register, as_FloatRegister($vsrc$$reg), __ D, 1);
1311 __ orr ($dst$$Register, $dst$$Register, $tmp$$Register);
1312 __ orr ($dst$$Register, $dst$$Register, $dst$$Register, Assembler::LSR, 32);
1313 __ orrw($dst$$Register, $isrc$$Register, $dst$$Register);
1314 %}
1315 ins_pipe(pipe_slow);
1316 %}
1317
1318 instruct reduce_eor4I(iRegINoSp dst, iRegIorL2I isrc, vecX vsrc, iRegINoSp tmp)
1319 %{
1320 predicate(n->in(2)->bottom_type()->is_vect()->element_basic_type() == T_INT);
1321 match(Set dst (XorReductionV isrc vsrc));
1322 ins_cost(INSN_COST);
1323 effect(TEMP_DEF dst, TEMP tmp);
1324 format %{ "umov $tmp, $vsrc, D, 0\n\t"
1325 "umov $dst, $vsrc, D, 1\n\t"
1326 "eor $dst, $dst, $tmp\n\t"
1327 "eor $dst, $dst, $dst, LSR #32\n\t"
1328 "eorw $dst, $isrc, $dst\t# eor reduction4I"
1329 %}
1330 ins_encode %{
1331 __ umov($tmp$$Register, as_FloatRegister($vsrc$$reg), __ D, 0);
1332 __ umov($dst$$Register, as_FloatRegister($vsrc$$reg), __ D, 1);
1333 __ eor ($dst$$Register, $dst$$Register, $tmp$$Register);
1334 __ eor ($dst$$Register, $dst$$Register, $dst$$Register, Assembler::LSR, 32);
1335 __ eorw($dst$$Register, $isrc$$Register, $dst$$Register);
1336 %}
1337 ins_pipe(pipe_slow);
1338 %}
1339
1340 instruct reduce_and2L(iRegLNoSp dst, iRegL isrc, vecX vsrc, iRegLNoSp tmp)
1341 %{
1342 predicate(n->in(2)->bottom_type()->is_vect()->element_basic_type() == T_LONG);
1343 match(Set dst (AndReductionV isrc vsrc));
1344 ins_cost(INSN_COST);
1345 effect(TEMP_DEF dst, TEMP tmp);
1346 format %{ "umov $tmp, $vsrc, D, 0\n\t"
1347 "andr $dst, $isrc, $tmp\n\t"
1348 "umov $tmp, $vsrc, D, 1\n\t"
1349 "andr $dst, $dst, $tmp\t# and reduction2L"
1350 %}
1351 ins_encode %{
1352 __ umov($tmp$$Register, as_FloatRegister($vsrc$$reg), __ D, 0);
1353 __ andr($dst$$Register, $isrc$$Register, $tmp$$Register);
1354 __ umov($tmp$$Register, as_FloatRegister($vsrc$$reg), __ D, 1);
1355 __ andr($dst$$Register, $dst$$Register, $tmp$$Register);
1356 %}
1357 ins_pipe(pipe_slow);
1358 %}
1359
1360 instruct reduce_orr2L(iRegLNoSp dst, iRegL isrc, vecX vsrc, iRegLNoSp tmp)
1361 %{
1362 predicate(n->in(2)->bottom_type()->is_vect()->element_basic_type() == T_LONG);
1363 match(Set dst (OrReductionV isrc vsrc));
1364 ins_cost(INSN_COST);
1365 effect(TEMP_DEF dst, TEMP tmp);
1366 format %{ "umov $tmp, $vsrc, D, 0\n\t"
1367 "orr $dst, $isrc, $tmp\n\t"
1368 "umov $tmp, $vsrc, D, 1\n\t"
1369 "orr $dst, $dst, $tmp\t# orr reduction2L"
1370 %}
1371 ins_encode %{
1372 __ umov($tmp$$Register, as_FloatRegister($vsrc$$reg), __ D, 0);
1373 __ orr ($dst$$Register, $isrc$$Register, $tmp$$Register);
1374 __ umov($tmp$$Register, as_FloatRegister($vsrc$$reg), __ D, 1);
1375 __ orr ($dst$$Register, $dst$$Register, $tmp$$Register);
1376 %}
1377 ins_pipe(pipe_slow);
1378 %}
1379
1380 instruct reduce_eor2L(iRegLNoSp dst, iRegL isrc, vecX vsrc, iRegLNoSp tmp)
1381 %{
1382 predicate(n->in(2)->bottom_type()->is_vect()->element_basic_type() == T_LONG);
1383 match(Set dst (XorReductionV isrc vsrc));
1384 ins_cost(INSN_COST);
1385 effect(TEMP_DEF dst, TEMP tmp);
1386 format %{ "umov $tmp, $vsrc, D, 0\n\t"
1387 "eor $dst, $isrc, $tmp\n\t"
1388 "umov $tmp, $vsrc, D, 1\n\t"
1389 "eor $dst, $dst, $tmp\t# eor reduction2L"
1390 %}
1391 ins_encode %{
1392 __ umov($tmp$$Register, as_FloatRegister($vsrc$$reg), __ D, 0);
1393 __ eor ($dst$$Register, $isrc$$Register, $tmp$$Register);
1394 __ umov($tmp$$Register, as_FloatRegister($vsrc$$reg), __ D, 1);
1395 __ eor ($dst$$Register, $dst$$Register, $tmp$$Register);
1396 %}
1397 ins_pipe(pipe_slow);
1398 %}
1399
1400 // ------------------------------ Vector insert ---------------------------------
1401
1402 instruct insert8B(vecD dst, vecD src, iRegIorL2I val, immI idx)
1403 %{
1404 predicate(n->bottom_type()->is_vect()->element_basic_type() == T_BYTE);
1405 match(Set dst (VectorInsert (Binary src val) idx));
1406 ins_cost(INSN_COST);
1407 format %{ "orr $dst, T8B, $src, $src\n\t"
1408 "mov $dst, T8B, $idx, $val\t# insert into vector(8B)" %}
1409 ins_encode %{
1410 if (as_FloatRegister($dst$$reg) != as_FloatRegister($src$$reg)) {
1411 __ orr(as_FloatRegister($dst$$reg), __ T8B,
1412 as_FloatRegister($src$$reg), as_FloatRegister($src$$reg));
1413 }
1414 __ mov(as_FloatRegister($dst$$reg), __ T8B, $idx$$constant, $val$$Register);
1415 %}
1416 ins_pipe(pipe_slow);
1417 %}
1418
1419 instruct insert16B(vecX dst, vecX src, iRegIorL2I val, immI idx)
1420 %{
1421 predicate(n->bottom_type()->is_vect()->element_basic_type() == T_BYTE);
1422 match(Set dst (VectorInsert (Binary src val) idx));
1423 ins_cost(INSN_COST);
1424 format %{ "orr $dst, T16B, $src, $src\n\t"
1425 "mov $dst, T16B, $idx, $val\t# insert into vector(16B)" %}
1426 ins_encode %{
1427 if (as_FloatRegister($dst$$reg) != as_FloatRegister($src$$reg)) {
1428 __ orr(as_FloatRegister($dst$$reg), __ T16B,
1429 as_FloatRegister($src$$reg), as_FloatRegister($src$$reg));
1430 }
1431 __ mov(as_FloatRegister($dst$$reg), __ T16B, $idx$$constant, $val$$Register);
1432 %}
1433 ins_pipe(pipe_slow);
1434 %}
1435
1436 instruct insert4S(vecD dst, vecD src, iRegIorL2I val, immI idx)
1437 %{
1438 predicate(n->bottom_type()->is_vect()->element_basic_type() == T_SHORT);
1439 match(Set dst (VectorInsert (Binary src val) idx));
1440 ins_cost(INSN_COST);
1441 format %{ "orr $dst, T8B, $src, $src\n\t"
1442 "mov $dst, T4H, $idx, $val\t# insert into vector(4S)" %}
1443 ins_encode %{
1444 if (as_FloatRegister($dst$$reg) != as_FloatRegister($src$$reg)) {
1445 __ orr(as_FloatRegister($dst$$reg), __ T8B,
1446 as_FloatRegister($src$$reg), as_FloatRegister($src$$reg));
1447 }
1448 __ mov(as_FloatRegister($dst$$reg), __ T4H, $idx$$constant, $val$$Register);
1449 %}
1450 ins_pipe(pipe_slow);
1451 %}
1452
1453 instruct insert8S(vecX dst, vecX src, iRegIorL2I val, immI idx)
1454 %{
1455 predicate(n->bottom_type()->is_vect()->element_basic_type() == T_SHORT);
1456 match(Set dst (VectorInsert (Binary src val) idx));
1457 ins_cost(INSN_COST);
1458 format %{ "orr $dst, T16B, $src, $src\n\t"
1459 "mov $dst, T8H, $idx, $val\t# insert into vector(8S)" %}
1460 ins_encode %{
1461 if (as_FloatRegister($dst$$reg) != as_FloatRegister($src$$reg)) {
1462 __ orr(as_FloatRegister($dst$$reg), __ T16B,
1463 as_FloatRegister($src$$reg), as_FloatRegister($src$$reg));
1464 }
1465 __ mov(as_FloatRegister($dst$$reg), __ T8H, $idx$$constant, $val$$Register);
1466 %}
1467 ins_pipe(pipe_slow);
1468 %}
1469
1470 instruct insert2I(vecD dst, vecD src, iRegIorL2I val, immI idx)
1471 %{
1472 predicate(n->bottom_type()->is_vect()->element_basic_type() == T_INT);
1473 match(Set dst (VectorInsert (Binary src val) idx));
1474 ins_cost(INSN_COST);
1475 format %{ "orr $dst, T8B, $src, $src\n\t"
1476 "mov $dst, T2S, $idx, $val\t# insert into vector(2I)" %}
1477 ins_encode %{
1478 if (as_FloatRegister($dst$$reg) != as_FloatRegister($src$$reg)) {
1479 __ orr(as_FloatRegister($dst$$reg), __ T8B,
1480 as_FloatRegister($src$$reg), as_FloatRegister($src$$reg));
1481 }
1482 __ mov(as_FloatRegister($dst$$reg), __ T2S, $idx$$constant, $val$$Register);
1483 %}
1484 ins_pipe(pipe_slow);
1485 %}
1486
1487 instruct insert4I(vecX dst, vecX src, iRegIorL2I val, immI idx)
1488 %{
1489 predicate(n->bottom_type()->is_vect()->element_basic_type() == T_INT);
1490 match(Set dst (VectorInsert (Binary src val) idx));
1491 ins_cost(INSN_COST);
1492 format %{ "orr $dst, T16B, $src, $src\n\t"
1493 "mov $dst, T4S, $idx, $val\t# insert into vector(4I)" %}
1494 ins_encode %{
1495 if (as_FloatRegister($dst$$reg) != as_FloatRegister($src$$reg)) {
1496 __ orr(as_FloatRegister($dst$$reg), __ T16B,
1497 as_FloatRegister($src$$reg), as_FloatRegister($src$$reg));
1498 }
1499 __ mov(as_FloatRegister($dst$$reg), __ T4S, $idx$$constant, $val$$Register);
1500 %}
1501 ins_pipe(pipe_slow);
1502 %}
1503
1504 instruct insert2L(vecX dst, vecX src, iRegL val, immI idx)
1505 %{
1506 predicate(n->bottom_type()->is_vect()->element_basic_type() == T_LONG);
1507 match(Set dst (VectorInsert (Binary src val) idx));
1508 ins_cost(INSN_COST);
1509 format %{ "orr $dst, T16B, $src, $src\n\t"
1510 "mov $dst, T2D, $idx, $val\t# insert into vector(2L)" %}
1511 ins_encode %{
1512 if (as_FloatRegister($dst$$reg) != as_FloatRegister($src$$reg)) {
1513 __ orr(as_FloatRegister($dst$$reg), __ T16B,
1514 as_FloatRegister($src$$reg), as_FloatRegister($src$$reg));
1515 }
1516 __ mov(as_FloatRegister($dst$$reg), __ T2D, $idx$$constant, $val$$Register);
1517 %}
1518 ins_pipe(pipe_slow);
1519 %}
1520
1521 instruct insert2F(vecD dst, vecD src, vRegF val, immI idx)
1522 %{
1523 predicate(n->bottom_type()->is_vect()->element_basic_type() == T_FLOAT);
1524 match(Set dst (VectorInsert (Binary src val) idx));
1525 ins_cost(INSN_COST);
1526 effect(TEMP_DEF dst);
1527 format %{ "orr $dst, T8B, $src, $src\n\t"
1528 "ins $dst, S, $val, $idx, 0\t# insert into vector(2F)" %}
1529 ins_encode %{
1530 __ orr(as_FloatRegister($dst$$reg), __ T8B,
1531 as_FloatRegister($src$$reg), as_FloatRegister($src$$reg));
1532 __ ins(as_FloatRegister($dst$$reg), __ S,
1533 as_FloatRegister($val$$reg), $idx$$constant, 0);
1534 %}
1535 ins_pipe(pipe_slow);
1536 %}
1537
1538 instruct insert4F(vecX dst, vecX src, vRegF val, immI idx)
1539 %{
1540 predicate(n->bottom_type()->is_vect()->element_basic_type() == T_FLOAT);
1541 match(Set dst (VectorInsert (Binary src val) idx));
1542 ins_cost(INSN_COST);
1543 effect(TEMP_DEF dst);
1544 format %{ "orr $dst, T16B, $src, $src\n\t"
1545 "ins $dst, S, $val, $idx, 0\t# insert into vector(4F)" %}
1546 ins_encode %{
1547 __ orr(as_FloatRegister($dst$$reg), __ T16B,
1548 as_FloatRegister($src$$reg), as_FloatRegister($src$$reg));
1549 __ ins(as_FloatRegister($dst$$reg), __ S,
1550 as_FloatRegister($val$$reg), $idx$$constant, 0);
1551 %}
1552 ins_pipe(pipe_slow);
1553 %}
1554
1555 instruct insert2D(vecX dst, vecX src, vRegD val, immI idx)
1556 %{
1557 predicate(n->bottom_type()->is_vect()->element_basic_type() == T_DOUBLE);
1558 match(Set dst (VectorInsert (Binary src val) idx));
1559 ins_cost(INSN_COST);
1560 effect(TEMP_DEF dst);
1561 format %{ "orr $dst, T16B, $src, $src\n\t"
1562 "ins $dst, D, $val, $idx, 0\t# insert into vector(2D)" %}
1563 ins_encode %{
1564 __ orr(as_FloatRegister($dst$$reg), __ T16B,
1565 as_FloatRegister($src$$reg), as_FloatRegister($src$$reg));
1566 __ ins(as_FloatRegister($dst$$reg), __ D,
1567 as_FloatRegister($val$$reg), $idx$$constant, 0);
1568 %}
1569 ins_pipe(pipe_slow);
1570 %}
1571
1572 // ------------------------------ Vector extract ---------------------------------
1573
1574 instruct extract8B(iRegINoSp dst, vecD src, immI idx)
1575 %{
1576 predicate(n->in(1)->bottom_type()->is_vect()->length() == 8);
1577 match(Set dst (ExtractB src idx));
1578 ins_cost(INSN_COST);
1579 format %{ "smov $dst, $src, B, $idx\t# extract from vector(8B)" %}
1580 ins_encode %{
1581 __ smov($dst$$Register, as_FloatRegister($src$$reg), __ B, $idx$$constant);
1582 %}
1583 ins_pipe(pipe_class_default);
1584 %}
1585
1586 instruct extract16B(iRegINoSp dst, vecX src, immI idx)
1587 %{
1588 predicate(n->in(1)->bottom_type()->is_vect()->length() == 16);
1589 match(Set dst (ExtractB src idx));
1590 ins_cost(INSN_COST);
1591 format %{ "smov $dst, $src, B, $idx\t# extract from vector(16B)" %}
1592 ins_encode %{
1593 __ smov($dst$$Register, as_FloatRegister($src$$reg), __ B, $idx$$constant);
1594 %}
1595 ins_pipe(pipe_class_default);
1596 %}
1597
1598 instruct extract4S(iRegINoSp dst, vecD src, immI idx)
1599 %{
1600 predicate(n->in(1)->bottom_type()->is_vect()->length() == 4);
1601 match(Set dst (ExtractS src idx));
1602 ins_cost(INSN_COST);
1603 format %{ "smov $dst, $src, H, $idx\t# extract from vector(4S)" %}
1604 ins_encode %{
1605 __ smov($dst$$Register, as_FloatRegister($src$$reg), __ H, $idx$$constant);
1606 %}
1607 ins_pipe(pipe_class_default);
1608 %}
1609
1610 instruct extract8S(iRegINoSp dst, vecX src, immI idx)
1611 %{
1612 predicate(n->in(1)->bottom_type()->is_vect()->length() == 8);
1613 match(Set dst (ExtractS src idx));
1614 ins_cost(INSN_COST);
1615 format %{ "smov $dst, $src, H, $idx\t# extract from vector(8S)" %}
1616 ins_encode %{
1617 __ smov($dst$$Register, as_FloatRegister($src$$reg), __ H, $idx$$constant);
1618 %}
1619 ins_pipe(pipe_class_default);
1620 %}
1621
1622 instruct extract2I(iRegINoSp dst, vecD src, immI idx)
1623 %{
1624 predicate(n->in(1)->bottom_type()->is_vect()->length() == 2);
1625 match(Set dst (ExtractI src idx));
1626 ins_cost(INSN_COST);
1627 format %{ "umov $dst, $src, S, $idx\t# extract from vector(2I)" %}
1628 ins_encode %{
1629 __ umov($dst$$Register, as_FloatRegister($src$$reg), __ S, $idx$$constant);
1630 %}
1631 ins_pipe(pipe_class_default);
1632 %}
1633
1634 instruct extract4I(iRegINoSp dst, vecX src, immI idx)
1635 %{
1636 predicate(n->in(1)->bottom_type()->is_vect()->length() == 4);
1637 match(Set dst (ExtractI src idx));
1638 ins_cost(INSN_COST);
1639 format %{ "umov $dst, $src, S, $idx\t# extract from vector(4I)" %}
1640 ins_encode %{
1641 __ umov($dst$$Register, as_FloatRegister($src$$reg), __ S, $idx$$constant);
1642 %}
1643 ins_pipe(pipe_class_default);
1644 %}
1645
1646 instruct extract2L(iRegLNoSp dst, vecX src, immI idx)
1647 %{
1648 predicate(n->in(1)->bottom_type()->is_vect()->length() == 2);
1649 match(Set dst (ExtractL src idx));
1650 ins_cost(INSN_COST);
1651 format %{ "umov $dst, $src, D, $idx\t# extract from vector(2L)" %}
1652 ins_encode %{
1653 __ umov($dst$$Register, as_FloatRegister($src$$reg), __ D, $idx$$constant);
1654 %}
1655 ins_pipe(pipe_class_default);
1656 %}
1657
1658 instruct extract2F(vRegF dst, vecD src, immI idx)
1659 %{
1660 predicate(n->in(1)->bottom_type()->is_vect()->length() == 2);
1661 match(Set dst (ExtractF src idx));
1662 ins_cost(INSN_COST);
1663 format %{ "ins $dst, S, $src, 0, $idx\t# extract from vector(2F)" %}
1664 ins_encode %{
1665 __ ins(as_FloatRegister($dst$$reg), __ S,
1666 as_FloatRegister($src$$reg), 0, $idx$$constant);
1667 %}
1668 ins_pipe(pipe_class_default);
1669 %}
1670
1671 instruct extract4F(vRegF dst, vecX src, immI idx)
1672 %{
1673 predicate(n->in(1)->bottom_type()->is_vect()->length() == 4);
1674 match(Set dst (ExtractF src idx));
1675 ins_cost(INSN_COST);
1676 format %{ "ins $dst, S, $src, 0, $idx\t# extract from vector(4F)" %}
1677 ins_encode %{
1678 __ ins(as_FloatRegister($dst$$reg), __ S,
1679 as_FloatRegister($src$$reg), 0, $idx$$constant);
1680 %}
1681 ins_pipe(pipe_class_default);
1682 %}
1683
1684 instruct extract2D(vRegD dst, vecX src, immI idx)
1685 %{
1686 predicate(n->in(1)->bottom_type()->is_vect()->length() == 2);
1687 match(Set dst (ExtractD src idx));
1688 ins_cost(INSN_COST);
1689 format %{ "ins $dst, D, $src, 0, $idx\t# extract from vector(2D)" %}
1690 ins_encode %{
1691 __ ins(as_FloatRegister($dst$$reg), __ D,
1692 as_FloatRegister($src$$reg), 0, $idx$$constant);
1693 %}
1694 ins_pipe(pipe_class_default);
1695 %}
1696
1697 // ------------------------------ Vector comparison ---------------------------------
1698
1699 instruct vcmeq8B(vecD dst, vecD src1, vecD src2, immI cond)
1700 %{
1701 predicate(n->as_Vector()->length() == 8 &&
1702 n->as_VectorMaskCmp()->get_predicate() == BoolTest::eq &&
1703 n->in(1)->in(1)->bottom_type()->is_vect()->element_basic_type() == T_BYTE);
1704 match(Set dst (VectorMaskCmp (Binary src1 src2) cond));
1705 format %{ "cmeq $dst, $src1, $src2\t# vector cmp (8B)" %}
1706 ins_cost(INSN_COST);
1707 ins_encode %{
1708 __ cmeq(as_FloatRegister($dst$$reg), __ T8B,
1709 as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg));
1710 %}
1711 ins_pipe(vdop64);
1712 %}
1713
1714 instruct vcmeq16B(vecX dst, vecX src1, vecX src2, immI cond)
1715 %{
1716 predicate(n->as_Vector()->length() == 16 &&
1717 n->as_VectorMaskCmp()->get_predicate() == BoolTest::eq &&
1718 n->in(1)->in(1)->bottom_type()->is_vect()->element_basic_type() == T_BYTE);
1719 match(Set dst (VectorMaskCmp (Binary src1 src2) cond));
1720 format %{ "cmeq $dst, $src1, $src2\t# vector cmp (16B)" %}
1721 ins_cost(INSN_COST);
1722 ins_encode %{
1723 __ cmeq(as_FloatRegister($dst$$reg), __ T16B,
1724 as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg));
1725 %}
1726 ins_pipe(vdop128);
1727 %}
1728
1729 instruct vcmeq4S(vecD dst, vecD src1, vecD src2, immI cond)
1730 %{
1731 predicate(n->as_Vector()->length() == 4 &&
1732 n->as_VectorMaskCmp()->get_predicate() == BoolTest::eq &&
1733 n->in(1)->in(1)->bottom_type()->is_vect()->element_basic_type() == T_SHORT);
1734 match(Set dst (VectorMaskCmp (Binary src1 src2) cond));
1735 format %{ "cmeq $dst, $src1, $src2\t# vector cmp (4S)" %}
1736 ins_cost(INSN_COST);
1737 ins_encode %{
1738 __ cmeq(as_FloatRegister($dst$$reg), __ T4H,
1739 as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg));
1740 %}
1741 ins_pipe(vdop64);
1742 %}
1743
1744 instruct vcmeq8S(vecX dst, vecX src1, vecX src2, immI cond)
1745 %{
1746 predicate(n->as_Vector()->length() == 8 &&
1747 n->as_VectorMaskCmp()->get_predicate() == BoolTest::eq &&
1748 n->in(1)->in(1)->bottom_type()->is_vect()->element_basic_type() == T_SHORT);
1749 match(Set dst (VectorMaskCmp (Binary src1 src2) cond));
1750 format %{ "cmeq $dst, $src1, $src2\t# vector cmp (8S)" %}
1751 ins_cost(INSN_COST);
1752 ins_encode %{
1753 __ cmeq(as_FloatRegister($dst$$reg), __ T8H,
1754 as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg));
1755 %}
1756 ins_pipe(vdop128);
1757 %}
1758
1759 instruct vcmeq2I(vecD dst, vecD src1, vecD src2, immI cond)
1760 %{
1761 predicate(n->as_Vector()->length() == 2 &&
1762 n->as_VectorMaskCmp()->get_predicate() == BoolTest::eq &&
1763 n->in(1)->in(1)->bottom_type()->is_vect()->element_basic_type() == T_INT);
1764 match(Set dst (VectorMaskCmp (Binary src1 src2) cond));
1765 format %{ "cmeq $dst, $src1, $src2\t# vector cmp (2I)" %}
1766 ins_cost(INSN_COST);
1767 ins_encode %{
1768 __ cmeq(as_FloatRegister($dst$$reg), __ T2S,
1769 as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg));
1770 %}
1771 ins_pipe(vdop64);
1772 %}
1773
1774 instruct vcmeq4I(vecX dst, vecX src1, vecX src2, immI cond)
1775 %{
1776 predicate(n->as_Vector()->length() == 4 &&
1777 n->as_VectorMaskCmp()->get_predicate() == BoolTest::eq &&
1778 n->in(1)->in(1)->bottom_type()->is_vect()->element_basic_type() == T_INT);
1779 match(Set dst (VectorMaskCmp (Binary src1 src2) cond));
1780 format %{ "cmeq $dst, $src1, $src2\t# vector cmp (4I)" %}
1781 ins_cost(INSN_COST);
1782 ins_encode %{
1783 __ cmeq(as_FloatRegister($dst$$reg), __ T4S,
1784 as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg));
1785 %}
1786 ins_pipe(vdop128);
1787 %}
1788
1789 instruct vcmeq2L(vecX dst, vecX src1, vecX src2, immI cond)
1790 %{
1791 predicate(n->as_Vector()->length() == 2 &&
1792 n->as_VectorMaskCmp()->get_predicate() == BoolTest::eq &&
1793 n->in(1)->in(1)->bottom_type()->is_vect()->element_basic_type() == T_LONG);
1794 match(Set dst (VectorMaskCmp (Binary src1 src2) cond));
1795 format %{ "cmeq $dst, $src1, $src2\t# vector cmp (2L)" %}
1796 ins_cost(INSN_COST);
1797 ins_encode %{
1798 __ cmeq(as_FloatRegister($dst$$reg), __ T2D,
1799 as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg));
1800 %}
1801 ins_pipe(vdop128);
1802 %}
1803
1804 instruct vcmeq2F(vecD dst, vecD src1, vecD src2, immI cond)
1805 %{
1806 predicate(n->as_Vector()->length() == 2 &&
1807 n->as_VectorMaskCmp()->get_predicate() == BoolTest::eq &&
1808 n->in(1)->in(1)->bottom_type()->is_vect()->element_basic_type() == T_FLOAT);
1809 match(Set dst (VectorMaskCmp (Binary src1 src2) cond));
1810 format %{ "fcmeq $dst, $src1, $src2\t# vector cmp (2F)" %}
1811 ins_cost(INSN_COST);
1812 ins_encode %{
1813 __ fcmeq(as_FloatRegister($dst$$reg), __ T2S,
1814 as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg));
1815 %}
1816 ins_pipe(vdop64);
1817 %}
1818
1819 instruct vcmeq4F(vecX dst, vecX src1, vecX src2, immI cond)
1820 %{
1821 predicate(n->as_Vector()->length() == 4 &&
1822 n->as_VectorMaskCmp()->get_predicate() == BoolTest::eq &&
1823 n->in(1)->in(1)->bottom_type()->is_vect()->element_basic_type() == T_FLOAT);
1824 match(Set dst (VectorMaskCmp (Binary src1 src2) cond));
1825 format %{ "fcmeq $dst, $src1, $src2\t# vector cmp (4F)" %}
1826 ins_cost(INSN_COST);
1827 ins_encode %{
1828 __ fcmeq(as_FloatRegister($dst$$reg), __ T4S,
1829 as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg));
1830 %}
1831 ins_pipe(vdop128);
1832 %}
1833
1834 instruct vcmeq2D(vecX dst, vecX src1, vecX src2, immI cond)
1835 %{
1836 predicate(n->as_Vector()->length() == 2 &&
1837 n->as_VectorMaskCmp()->get_predicate() == BoolTest::eq &&
1838 n->in(1)->in(1)->bottom_type()->is_vect()->element_basic_type() == T_DOUBLE);
1839 match(Set dst (VectorMaskCmp (Binary src1 src2) cond));
1840 format %{ "fcmeq $dst, $src1, $src2\t# vector cmp (2D)" %}
1841 ins_cost(INSN_COST);
1842 ins_encode %{
1843 __ fcmeq(as_FloatRegister($dst$$reg), __ T2D,
1844 as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg));
1845 %}
1846 ins_pipe(vdop128);
1847 %}
1848
1849 instruct vcmgt8B(vecD dst, vecD src1, vecD src2, immI cond)
1850 %{
1851 predicate(n->as_Vector()->length() == 8 &&
1852 n->as_VectorMaskCmp()->get_predicate() == BoolTest::gt &&
1853 n->in(1)->in(1)->bottom_type()->is_vect()->element_basic_type() == T_BYTE);
1854 match(Set dst (VectorMaskCmp (Binary src1 src2) cond));
1855 format %{ "cmgt $dst, $src1, $src2\t# vector cmp (8B)" %}
1856 ins_cost(INSN_COST);
1857 ins_encode %{
1858 __ cmgt(as_FloatRegister($dst$$reg), __ T8B,
1859 as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg));
1860 %}
1861 ins_pipe(vdop64);
1862 %}
1863
1864 instruct vcmgt16B(vecX dst, vecX src1, vecX src2, immI cond)
1865 %{
1866 predicate(n->as_Vector()->length() == 16 &&
1867 n->as_VectorMaskCmp()->get_predicate() == BoolTest::gt &&
1868 n->in(1)->in(1)->bottom_type()->is_vect()->element_basic_type() == T_BYTE);
1869 match(Set dst (VectorMaskCmp (Binary src1 src2) cond));
1870 format %{ "cmgt $dst, $src1, $src2\t# vector cmp (16B)" %}
1871 ins_cost(INSN_COST);
1872 ins_encode %{
1873 __ cmgt(as_FloatRegister($dst$$reg), __ T16B,
1874 as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg));
1875 %}
1876 ins_pipe(vdop128);
1877 %}
1878
1879 instruct vcmgt4S(vecD dst, vecD src1, vecD src2, immI cond)
1880 %{
1881 predicate(n->as_Vector()->length() == 4 &&
1882 n->as_VectorMaskCmp()->get_predicate() == BoolTest::gt &&
1883 n->in(1)->in(1)->bottom_type()->is_vect()->element_basic_type() == T_SHORT);
1884 match(Set dst (VectorMaskCmp (Binary src1 src2) cond));
1885 format %{ "cmgt $dst, $src1, $src2\t# vector cmp (4S)" %}
1886 ins_cost(INSN_COST);
1887 ins_encode %{
1888 __ cmgt(as_FloatRegister($dst$$reg), __ T4H,
1889 as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg));
1890 %}
1891 ins_pipe(vdop64);
1892 %}
1893
1894 instruct vcmgt8S(vecX dst, vecX src1, vecX src2, immI cond)
1895 %{
1896 predicate(n->as_Vector()->length() == 8 &&
1897 n->as_VectorMaskCmp()->get_predicate() == BoolTest::gt &&
1898 n->in(1)->in(1)->bottom_type()->is_vect()->element_basic_type() == T_SHORT);
1899 match(Set dst (VectorMaskCmp (Binary src1 src2) cond));
1900 format %{ "cmgt $dst, $src1, $src2\t# vector cmp (8S)" %}
1901 ins_cost(INSN_COST);
1902 ins_encode %{
1903 __ cmgt(as_FloatRegister($dst$$reg), __ T8H,
1904 as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg));
1905 %}
1906 ins_pipe(vdop128);
1907 %}
1908
1909 instruct vcmgt2I(vecD dst, vecD src1, vecD src2, immI cond)
1910 %{
1911 predicate(n->as_Vector()->length() == 2 &&
1912 n->as_VectorMaskCmp()->get_predicate() == BoolTest::gt &&
1913 n->in(1)->in(1)->bottom_type()->is_vect()->element_basic_type() == T_INT);
1914 match(Set dst (VectorMaskCmp (Binary src1 src2) cond));
1915 format %{ "cmgt $dst, $src1, $src2\t# vector cmp (2I)" %}
1916 ins_cost(INSN_COST);
1917 ins_encode %{
1918 __ cmgt(as_FloatRegister($dst$$reg), __ T2S,
1919 as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg));
1920 %}
1921 ins_pipe(vdop64);
1922 %}
1923
1924 instruct vcmgt4I(vecX dst, vecX src1, vecX src2, immI cond)
1925 %{
1926 predicate(n->as_Vector()->length() == 4 &&
1927 n->as_VectorMaskCmp()->get_predicate() == BoolTest::gt &&
1928 n->in(1)->in(1)->bottom_type()->is_vect()->element_basic_type() == T_INT);
1929 match(Set dst (VectorMaskCmp (Binary src1 src2) cond));
1930 format %{ "cmgt $dst, $src1, $src2\t# vector cmp (4I)" %}
1931 ins_cost(INSN_COST);
1932 ins_encode %{
1933 __ cmgt(as_FloatRegister($dst$$reg), __ T4S,
1934 as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg));
1935 %}
1936 ins_pipe(vdop128);
1937 %}
1938
1939 instruct vcmgt2L(vecX dst, vecX src1, vecX src2, immI cond)
1940 %{
1941 predicate(n->as_Vector()->length() == 2 &&
1942 n->as_VectorMaskCmp()->get_predicate() == BoolTest::gt &&
1943 n->in(1)->in(1)->bottom_type()->is_vect()->element_basic_type() == T_LONG);
1944 match(Set dst (VectorMaskCmp (Binary src1 src2) cond));
1945 format %{ "cmgt $dst, $src1, $src2\t# vector cmp (2L)" %}
1946 ins_cost(INSN_COST);
1947 ins_encode %{
1948 __ cmgt(as_FloatRegister($dst$$reg), __ T2D,
1949 as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg));
1950 %}
1951 ins_pipe(vdop128);
1952 %}
1953
1954 instruct vcmgt2F(vecD dst, vecD src1, vecD src2, immI cond)
1955 %{
1956 predicate(n->as_Vector()->length() == 2 &&
1957 n->as_VectorMaskCmp()->get_predicate() == BoolTest::gt &&
1958 n->in(1)->in(1)->bottom_type()->is_vect()->element_basic_type() == T_FLOAT);
1959 match(Set dst (VectorMaskCmp (Binary src1 src2) cond));
1960 format %{ "fcmgt $dst, $src1, $src2\t# vector cmp (2F)" %}
1961 ins_cost(INSN_COST);
1962 ins_encode %{
1963 __ fcmgt(as_FloatRegister($dst$$reg), __ T2S,
1964 as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg));
1965 %}
1966 ins_pipe(vdop64);
1967 %}
1968
1969 instruct vcmgt4F(vecX dst, vecX src1, vecX src2, immI cond)
1970 %{
1971 predicate(n->as_Vector()->length() == 4 &&
1972 n->as_VectorMaskCmp()->get_predicate() == BoolTest::gt &&
1973 n->in(1)->in(1)->bottom_type()->is_vect()->element_basic_type() == T_FLOAT);
1974 match(Set dst (VectorMaskCmp (Binary src1 src2) cond));
1975 format %{ "fcmgt $dst, $src1, $src2\t# vector cmp (4F)" %}
1976 ins_cost(INSN_COST);
1977 ins_encode %{
1978 __ fcmgt(as_FloatRegister($dst$$reg), __ T4S,
1979 as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg));
1980 %}
1981 ins_pipe(vdop128);
1982 %}
1983
1984 instruct vcmgt2D(vecX dst, vecX src1, vecX src2, immI cond)
1985 %{
1986 predicate(n->as_Vector()->length() == 2 &&
1987 n->as_VectorMaskCmp()->get_predicate() == BoolTest::gt &&
1988 n->in(1)->in(1)->bottom_type()->is_vect()->element_basic_type() == T_DOUBLE);
1989 match(Set dst (VectorMaskCmp (Binary src1 src2) cond));
1990 format %{ "fcmgt $dst, $src1, $src2\t# vector cmp (2D)" %}
1991 ins_cost(INSN_COST);
1992 ins_encode %{
1993 __ fcmgt(as_FloatRegister($dst$$reg), __ T2D,
1994 as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg));
1995 %}
1996 ins_pipe(vdop128);
1997 %}
1998
1999 instruct vcmge8B(vecD dst, vecD src1, vecD src2, immI cond)
2000 %{
2001 predicate(n->as_Vector()->length() == 8 &&
2002 n->as_VectorMaskCmp()->get_predicate() == BoolTest::ge &&
2003 n->in(1)->in(1)->bottom_type()->is_vect()->element_basic_type() == T_BYTE);
2004 match(Set dst (VectorMaskCmp (Binary src1 src2) cond));
2005 format %{ "cmge $dst, $src1, $src2\t# vector cmp (8B)" %}
2006 ins_cost(INSN_COST);
2007 ins_encode %{
2008 __ cmge(as_FloatRegister($dst$$reg), __ T8B,
2009 as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg));
2010 %}
2011 ins_pipe(vdop64);
2012 %}
2013
2014 instruct vcmge16B(vecX dst, vecX src1, vecX src2, immI cond)
2015 %{
2016 predicate(n->as_Vector()->length() == 16 &&
2017 n->as_VectorMaskCmp()->get_predicate() == BoolTest::ge &&
2018 n->in(1)->in(1)->bottom_type()->is_vect()->element_basic_type() == T_BYTE);
2019 match(Set dst (VectorMaskCmp (Binary src1 src2) cond));
2020 format %{ "cmge $dst, $src1, $src2\t# vector cmp (16B)" %}
2021 ins_cost(INSN_COST);
2022 ins_encode %{
2023 __ cmge(as_FloatRegister($dst$$reg), __ T16B,
2024 as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg));
2025 %}
2026 ins_pipe(vdop128);
2027 %}
2028
2029 instruct vcmge4S(vecD dst, vecD src1, vecD src2, immI cond)
2030 %{
2031 predicate(n->as_Vector()->length() == 4 &&
2032 n->as_VectorMaskCmp()->get_predicate() == BoolTest::ge &&
2033 n->in(1)->in(1)->bottom_type()->is_vect()->element_basic_type() == T_SHORT);
2034 match(Set dst (VectorMaskCmp (Binary src1 src2) cond));
2035 format %{ "cmge $dst, $src1, $src2\t# vector cmp (4S)" %}
2036 ins_cost(INSN_COST);
2037 ins_encode %{
2038 __ cmge(as_FloatRegister($dst$$reg), __ T4H,
2039 as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg));
2040 %}
2041 ins_pipe(vdop64);
2042 %}
2043
2044 instruct vcmge8S(vecX dst, vecX src1, vecX src2, immI cond)
2045 %{
2046 predicate(n->as_Vector()->length() == 8 &&
2047 n->as_VectorMaskCmp()->get_predicate() == BoolTest::ge &&
2048 n->in(1)->in(1)->bottom_type()->is_vect()->element_basic_type() == T_SHORT);
2049 match(Set dst (VectorMaskCmp (Binary src1 src2) cond));
2050 format %{ "cmge $dst, $src1, $src2\t# vector cmp (8S)" %}
2051 ins_cost(INSN_COST);
2052 ins_encode %{
2053 __ cmge(as_FloatRegister($dst$$reg), __ T8H,
2054 as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg));
2055 %}
2056 ins_pipe(vdop128);
2057 %}
2058
2059 instruct vcmge2I(vecD dst, vecD src1, vecD src2, immI cond)
2060 %{
2061 predicate(n->as_Vector()->length() == 2 &&
2062 n->as_VectorMaskCmp()->get_predicate() == BoolTest::ge &&
2063 n->in(1)->in(1)->bottom_type()->is_vect()->element_basic_type() == T_INT);
2064 match(Set dst (VectorMaskCmp (Binary src1 src2) cond));
2065 format %{ "cmge $dst, $src1, $src2\t# vector cmp (2I)" %}
2066 ins_cost(INSN_COST);
2067 ins_encode %{
2068 __ cmge(as_FloatRegister($dst$$reg), __ T2S,
2069 as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg));
2070 %}
2071 ins_pipe(vdop64);
2072 %}
2073
2074 instruct vcmge4I(vecX dst, vecX src1, vecX src2, immI cond)
2075 %{
2076 predicate(n->as_Vector()->length() == 4 &&
2077 n->as_VectorMaskCmp()->get_predicate() == BoolTest::ge &&
2078 n->in(1)->in(1)->bottom_type()->is_vect()->element_basic_type() == T_INT);
2079 match(Set dst (VectorMaskCmp (Binary src1 src2) cond));
2080 format %{ "cmge $dst, $src1, $src2\t# vector cmp (4I)" %}
2081 ins_cost(INSN_COST);
2082 ins_encode %{
2083 __ cmge(as_FloatRegister($dst$$reg), __ T4S,
2084 as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg));
2085 %}
2086 ins_pipe(vdop128);
2087 %}
2088
2089 instruct vcmge2L(vecX dst, vecX src1, vecX src2, immI cond)
2090 %{
2091 predicate(n->as_Vector()->length() == 2 &&
2092 n->as_VectorMaskCmp()->get_predicate() == BoolTest::ge &&
2093 n->in(1)->in(1)->bottom_type()->is_vect()->element_basic_type() == T_LONG);
2094 match(Set dst (VectorMaskCmp (Binary src1 src2) cond));
2095 format %{ "cmge $dst, $src1, $src2\t# vector cmp (2L)" %}
2096 ins_cost(INSN_COST);
2097 ins_encode %{
2098 __ cmge(as_FloatRegister($dst$$reg), __ T2D,
2099 as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg));
2100 %}
2101 ins_pipe(vdop128);
2102 %}
2103
2104 instruct vcmge2F(vecD dst, vecD src1, vecD src2, immI cond)
2105 %{
2106 predicate(n->as_Vector()->length() == 2 &&
2107 n->as_VectorMaskCmp()->get_predicate() == BoolTest::ge &&
2108 n->in(1)->in(1)->bottom_type()->is_vect()->element_basic_type() == T_FLOAT);
2109 match(Set dst (VectorMaskCmp (Binary src1 src2) cond));
2110 format %{ "fcmge $dst, $src1, $src2\t# vector cmp (2F)" %}
2111 ins_cost(INSN_COST);
2112 ins_encode %{
2113 __ fcmge(as_FloatRegister($dst$$reg), __ T2S,
2114 as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg));
2115 %}
2116 ins_pipe(vdop64);
2117 %}
2118
2119 instruct vcmge4F(vecX dst, vecX src1, vecX src2, immI cond)
2120 %{
2121 predicate(n->as_Vector()->length() == 4 &&
2122 n->as_VectorMaskCmp()->get_predicate() == BoolTest::ge &&
2123 n->in(1)->in(1)->bottom_type()->is_vect()->element_basic_type() == T_FLOAT);
2124 match(Set dst (VectorMaskCmp (Binary src1 src2) cond));
2125 format %{ "fcmge $dst, $src1, $src2\t# vector cmp (4F)" %}
2126 ins_cost(INSN_COST);
2127 ins_encode %{
2128 __ fcmge(as_FloatRegister($dst$$reg), __ T4S,
2129 as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg));
2130 %}
2131 ins_pipe(vdop128);
2132 %}
2133
2134 instruct vcmge2D(vecX dst, vecX src1, vecX src2, immI cond)
2135 %{
2136 predicate(n->as_Vector()->length() == 2 &&
2137 n->as_VectorMaskCmp()->get_predicate() == BoolTest::ge &&
2138 n->in(1)->in(1)->bottom_type()->is_vect()->element_basic_type() == T_DOUBLE);
2139 match(Set dst (VectorMaskCmp (Binary src1 src2) cond));
2140 format %{ "fcmge $dst, $src1, $src2\t# vector cmp (2D)" %}
2141 ins_cost(INSN_COST);
2142 ins_encode %{
2143 __ fcmge(as_FloatRegister($dst$$reg), __ T2D,
2144 as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg));
2145 %}
2146 ins_pipe(vdop128);
2147 %}
2148
2149 instruct vcmne8B(vecD dst, vecD src1, vecD src2, immI cond)
2150 %{
2151 predicate(n->as_Vector()->length() == 8 &&
2152 n->as_VectorMaskCmp()->get_predicate() == BoolTest::ne &&
2153 n->in(1)->in(1)->bottom_type()->is_vect()->element_basic_type() == T_BYTE);
2154 match(Set dst (VectorMaskCmp (Binary src1 src2) cond));
2155 format %{ "cmeq $dst, $src1, $src2\n\t# vector cmp (8B)"
2156 "not $dst, $dst\t" %}
2157 ins_cost(INSN_COST);
2158 ins_encode %{
2159 __ cmeq(as_FloatRegister($dst$$reg), __ T8B,
2160 as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg));
2161 __ notr(as_FloatRegister($dst$$reg), __ T8B, as_FloatRegister($dst$$reg));
2162 %}
2163 ins_pipe(pipe_slow);
2164 %}
2165
2166 instruct vcmne16B(vecX dst, vecX src1, vecX src2, immI cond)
2167 %{
2168 predicate(n->as_Vector()->length() == 16 &&
2169 n->as_VectorMaskCmp()->get_predicate() == BoolTest::ne &&
2170 n->in(1)->in(1)->bottom_type()->is_vect()->element_basic_type() == T_BYTE);
2171 match(Set dst (VectorMaskCmp (Binary src1 src2) cond));
2172 format %{ "cmeq $dst, $src1, $src2\n\t# vector cmp (16B)"
2173 "not $dst, $dst\t" %}
2174 ins_cost(INSN_COST);
2175 ins_encode %{
2176 __ cmeq(as_FloatRegister($dst$$reg), __ T16B,
2177 as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg));
2178 __ notr(as_FloatRegister($dst$$reg), __ T16B, as_FloatRegister($dst$$reg));
2179 %}
2180 ins_pipe(pipe_slow);
2181 %}
2182
2183 instruct vcmne4S(vecD dst, vecD src1, vecD src2, immI cond)
2184 %{
2185 predicate(n->as_Vector()->length() == 4 &&
2186 n->as_VectorMaskCmp()->get_predicate() == BoolTest::ne &&
2187 n->in(1)->in(1)->bottom_type()->is_vect()->element_basic_type() == T_SHORT);
2188 match(Set dst (VectorMaskCmp (Binary src1 src2) cond));
2189 format %{ "cmeq $dst, $src1, $src2\n\t# vector cmp (4S)"
2190 "not $dst, $dst\t" %}
2191 ins_cost(INSN_COST);
2192 ins_encode %{
2193 __ cmeq(as_FloatRegister($dst$$reg), __ T4H,
2194 as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg));
2195 __ notr(as_FloatRegister($dst$$reg), __ T8B, as_FloatRegister($dst$$reg));
2196 %}
2197 ins_pipe(pipe_slow);
2198 %}
2199
2200 instruct vcmne8S(vecX dst, vecX src1, vecX src2, immI cond)
2201 %{
2202 predicate(n->as_Vector()->length() == 8 &&
2203 n->as_VectorMaskCmp()->get_predicate() == BoolTest::ne &&
2204 n->in(1)->in(1)->bottom_type()->is_vect()->element_basic_type() == T_SHORT);
2205 match(Set dst (VectorMaskCmp (Binary src1 src2) cond));
2206 format %{ "cmeq $dst, $src1, $src2\n\t# vector cmp (8S)"
2207 "not $dst, $dst\t" %}
2208 ins_cost(INSN_COST);
2209 ins_encode %{
2210 __ cmeq(as_FloatRegister($dst$$reg), __ T8H,
2211 as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg));
2212 __ notr(as_FloatRegister($dst$$reg), __ T16B, as_FloatRegister($dst$$reg));
2213 %}
2214 ins_pipe(pipe_slow);
2215 %}
2216
2217 instruct vcmne2I(vecD dst, vecD src1, vecD src2, immI cond)
2218 %{
2219 predicate(n->as_Vector()->length() == 2 &&
2220 n->as_VectorMaskCmp()->get_predicate() == BoolTest::ne &&
2221 n->in(1)->in(1)->bottom_type()->is_vect()->element_basic_type() == T_INT);
2222 match(Set dst (VectorMaskCmp (Binary src1 src2) cond));
2223 format %{ "cmeq $dst, $src1, $src2\n\t# vector cmp (2I)"
2224 "not $dst, $dst\t" %}
2225 ins_cost(INSN_COST);
2226 ins_encode %{
2227 __ cmeq(as_FloatRegister($dst$$reg), __ T2S,
2228 as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg));
2229 __ notr(as_FloatRegister($dst$$reg), __ T8B, as_FloatRegister($dst$$reg));
2230 %}
2231 ins_pipe(pipe_slow);
2232 %}
2233
2234 instruct vcmne4I(vecX dst, vecX src1, vecX src2, immI cond)
2235 %{
2236 predicate(n->as_Vector()->length() == 4 &&
2237 n->as_VectorMaskCmp()->get_predicate() == BoolTest::ne &&
2238 n->in(1)->in(1)->bottom_type()->is_vect()->element_basic_type() == T_INT);
2239 match(Set dst (VectorMaskCmp (Binary src1 src2) cond));
2240 format %{ "cmeq $dst, $src1, $src2\n\t# vector cmp (4I)"
2241 "not $dst, $dst\t" %}
2242 ins_cost(INSN_COST);
2243 ins_encode %{
2244 __ cmeq(as_FloatRegister($dst$$reg), __ T4S,
2245 as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg));
2246 __ notr(as_FloatRegister($dst$$reg), __ T16B, as_FloatRegister($dst$$reg));
2247 %}
2248 ins_pipe(pipe_slow);
2249 %}
2250
2251 instruct vcmne2L(vecX dst, vecX src1, vecX src2, immI cond)
2252 %{
2253 predicate(n->as_Vector()->length() == 2 &&
2254 n->as_VectorMaskCmp()->get_predicate() == BoolTest::ne &&
2255 n->in(1)->in(1)->bottom_type()->is_vect()->element_basic_type() == T_LONG);
2256 match(Set dst (VectorMaskCmp (Binary src1 src2) cond));
2257 format %{ "cmeq $dst, $src1, $src2\n\t# vector cmp (2L)"
2258 "not $dst, $dst\t" %}
2259 ins_cost(INSN_COST);
2260 ins_encode %{
2261 __ cmeq(as_FloatRegister($dst$$reg), __ T2D,
2262 as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg));
2263 __ notr(as_FloatRegister($dst$$reg), __ T16B, as_FloatRegister($dst$$reg));
2264 %}
2265 ins_pipe(pipe_slow);
2266 %}
2267
2268 instruct vcmne2F(vecD dst, vecD src1, vecD src2, immI cond)
2269 %{
2270 predicate(n->as_Vector()->length() == 2 &&
2271 n->as_VectorMaskCmp()->get_predicate() == BoolTest::ne &&
2272 n->in(1)->in(1)->bottom_type()->is_vect()->element_basic_type() == T_FLOAT);
2273 match(Set dst (VectorMaskCmp (Binary src1 src2) cond));
2274 format %{ "fcmeq $dst, $src1, $src2\n\t# vector cmp (2F)"
2275 "not $dst, $dst\t" %}
2276 ins_cost(INSN_COST);
2277 ins_encode %{
2278 __ fcmeq(as_FloatRegister($dst$$reg), __ T2S,
2279 as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg));
2280 __ notr(as_FloatRegister($dst$$reg), __ T8B, as_FloatRegister($dst$$reg));
2281 %}
2282 ins_pipe(pipe_slow);
2283 %}
2284
2285 instruct vcmne4F(vecX dst, vecX src1, vecX src2, immI cond)
2286 %{
2287 predicate(n->as_Vector()->length() == 4 &&
2288 n->as_VectorMaskCmp()->get_predicate() == BoolTest::ne &&
2289 n->in(1)->in(1)->bottom_type()->is_vect()->element_basic_type() == T_FLOAT);
2290 match(Set dst (VectorMaskCmp (Binary src1 src2) cond));
2291 format %{ "fcmeq $dst, $src1, $src2\n\t# vector cmp (4F)"
2292 "not $dst, $dst\t" %}
2293 ins_cost(INSN_COST);
2294 ins_encode %{
2295 __ fcmeq(as_FloatRegister($dst$$reg), __ T4S,
2296 as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg));
2297 __ notr(as_FloatRegister($dst$$reg), __ T16B, as_FloatRegister($dst$$reg));
2298 %}
2299 ins_pipe(pipe_slow);
2300 %}
2301
2302 instruct vcmne2D(vecX dst, vecX src1, vecX src2, immI cond)
2303 %{
2304 predicate(n->as_Vector()->length() == 2 &&
2305 n->as_VectorMaskCmp()->get_predicate() == BoolTest::ne &&
2306 n->in(1)->in(1)->bottom_type()->is_vect()->element_basic_type() == T_DOUBLE);
2307 match(Set dst (VectorMaskCmp (Binary src1 src2) cond));
2308 format %{ "fcmeq $dst, $src1, $src2\n\t# vector cmp (2D)"
2309 "not $dst, $dst\t" %}
2310 ins_cost(INSN_COST);
2311 ins_encode %{
2312 __ fcmeq(as_FloatRegister($dst$$reg), __ T2D,
2313 as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg));
2314 __ notr(as_FloatRegister($dst$$reg), __ T16B, as_FloatRegister($dst$$reg));
2315 %}
2316 ins_pipe(pipe_slow);
2317 %}
2318
2319 instruct vcmlt8B(vecD dst, vecD src1, vecD src2, immI cond)
2320 %{
2321 predicate(n->as_Vector()->length() == 8 &&
2322 n->as_VectorMaskCmp()->get_predicate() == BoolTest::lt &&
2323 n->in(1)->in(1)->bottom_type()->is_vect()->element_basic_type() == T_BYTE);
2324 match(Set dst (VectorMaskCmp (Binary src1 src2) cond));
2325 format %{ "cmgt $dst, $src2, $src1\t# vector cmp (8B)" %}
2326 ins_cost(INSN_COST);
2327 ins_encode %{
2328 __ cmgt(as_FloatRegister($dst$$reg), __ T8B,
2329 as_FloatRegister($src2$$reg), as_FloatRegister($src1$$reg));
2330 %}
2331 ins_pipe(vdop64);
2332 %}
2333
2334 instruct vcmlt16B(vecX dst, vecX src1, vecX src2, immI cond)
2335 %{
2336 predicate(n->as_Vector()->length() == 16 &&
2337 n->as_VectorMaskCmp()->get_predicate() == BoolTest::lt &&
2338 n->in(1)->in(1)->bottom_type()->is_vect()->element_basic_type() == T_BYTE);
2339 match(Set dst (VectorMaskCmp (Binary src1 src2) cond));
2340 format %{ "cmgt $dst, $src2, $src1\t# vector cmp (16B)" %}
2341 ins_cost(INSN_COST);
2342 ins_encode %{
2343 __ cmgt(as_FloatRegister($dst$$reg), __ T16B,
2344 as_FloatRegister($src2$$reg), as_FloatRegister($src1$$reg));
2345 %}
2346 ins_pipe(vdop128);
2347 %}
2348
2349 instruct vcmlt4S(vecD dst, vecD src1, vecD src2, immI cond)
2350 %{
2351 predicate(n->as_Vector()->length() == 4 &&
2352 n->as_VectorMaskCmp()->get_predicate() == BoolTest::lt &&
2353 n->in(1)->in(1)->bottom_type()->is_vect()->element_basic_type() == T_SHORT);
2354 match(Set dst (VectorMaskCmp (Binary src1 src2) cond));
2355 format %{ "cmgt $dst, $src2, $src1\t# vector cmp (4S)" %}
2356 ins_cost(INSN_COST);
2357 ins_encode %{
2358 __ cmgt(as_FloatRegister($dst$$reg), __ T4H,
2359 as_FloatRegister($src2$$reg), as_FloatRegister($src1$$reg));
2360 %}
2361 ins_pipe(vdop64);
2362 %}
2363
2364 instruct vcmlt8S(vecX dst, vecX src1, vecX src2, immI cond)
2365 %{
2366 predicate(n->as_Vector()->length() == 8 &&
2367 n->as_VectorMaskCmp()->get_predicate() == BoolTest::lt &&
2368 n->in(1)->in(1)->bottom_type()->is_vect()->element_basic_type() == T_SHORT);
2369 match(Set dst (VectorMaskCmp (Binary src1 src2) cond));
2370 format %{ "cmgt $dst, $src2, $src1\t# vector cmp (8S)" %}
2371 ins_cost(INSN_COST);
2372 ins_encode %{
2373 __ cmgt(as_FloatRegister($dst$$reg), __ T8H,
2374 as_FloatRegister($src2$$reg), as_FloatRegister($src1$$reg));
2375 %}
2376 ins_pipe(vdop128);
2377 %}
2378
2379 instruct vcmlt2I(vecD dst, vecD src1, vecD src2, immI cond)
2380 %{
2381 predicate(n->as_Vector()->length() == 2 &&
2382 n->as_VectorMaskCmp()->get_predicate() == BoolTest::lt &&
2383 n->in(1)->in(1)->bottom_type()->is_vect()->element_basic_type() == T_INT);
2384 match(Set dst (VectorMaskCmp (Binary src1 src2) cond));
2385 format %{ "cmgt $dst, $src2, $src1\t# vector cmp (2I)" %}
2386 ins_cost(INSN_COST);
2387 ins_encode %{
2388 __ cmgt(as_FloatRegister($dst$$reg), __ T2S,
2389 as_FloatRegister($src2$$reg), as_FloatRegister($src1$$reg));
2390 %}
2391 ins_pipe(vdop64);
2392 %}
2393
2394 instruct vcmlt4I(vecX dst, vecX src1, vecX src2, immI cond)
2395 %{
2396 predicate(n->as_Vector()->length() == 4 &&
2397 n->as_VectorMaskCmp()->get_predicate() == BoolTest::lt &&
2398 n->in(1)->in(1)->bottom_type()->is_vect()->element_basic_type() == T_INT);
2399 match(Set dst (VectorMaskCmp (Binary src1 src2) cond));
2400 format %{ "cmgt $dst, $src2, $src1\t# vector cmp (4I)" %}
2401 ins_cost(INSN_COST);
2402 ins_encode %{
2403 __ cmgt(as_FloatRegister($dst$$reg), __ T4S,
2404 as_FloatRegister($src2$$reg), as_FloatRegister($src1$$reg));
2405 %}
2406 ins_pipe(vdop128);
2407 %}
2408
2409 instruct vcmlt2L(vecX dst, vecX src1, vecX src2, immI cond)
2410 %{
2411 predicate(n->as_Vector()->length() == 2 &&
2412 n->as_VectorMaskCmp()->get_predicate() == BoolTest::lt &&
2413 n->in(1)->in(1)->bottom_type()->is_vect()->element_basic_type() == T_LONG);
2414 match(Set dst (VectorMaskCmp (Binary src1 src2) cond));
2415 format %{ "cmgt $dst, $src2, $src1\t# vector cmp (2L)" %}
2416 ins_cost(INSN_COST);
2417 ins_encode %{
2418 __ cmgt(as_FloatRegister($dst$$reg), __ T2D,
2419 as_FloatRegister($src2$$reg), as_FloatRegister($src1$$reg));
2420 %}
2421 ins_pipe(vdop128);
2422 %}
2423
2424 instruct vcmlt2F(vecD dst, vecD src1, vecD src2, immI cond)
2425 %{
2426 predicate(n->as_Vector()->length() == 2 &&
2427 n->as_VectorMaskCmp()->get_predicate() == BoolTest::lt &&
2428 n->in(1)->in(1)->bottom_type()->is_vect()->element_basic_type() == T_FLOAT);
2429 match(Set dst (VectorMaskCmp (Binary src1 src2) cond));
2430 format %{ "fcmgt $dst, $src2, $src1\t# vector cmp (2F)" %}
2431 ins_cost(INSN_COST);
2432 ins_encode %{
2433 __ fcmgt(as_FloatRegister($dst$$reg), __ T2S,
2434 as_FloatRegister($src2$$reg), as_FloatRegister($src1$$reg));
2435 %}
2436 ins_pipe(vdop64);
2437 %}
2438
2439 instruct vcmlt4F(vecX dst, vecX src1, vecX src2, immI cond)
2440 %{
2441 predicate(n->as_Vector()->length() == 4 &&
2442 n->as_VectorMaskCmp()->get_predicate() == BoolTest::lt &&
2443 n->in(1)->in(1)->bottom_type()->is_vect()->element_basic_type() == T_FLOAT);
2444 match(Set dst (VectorMaskCmp (Binary src1 src2) cond));
2445 format %{ "fcmgt $dst, $src2, $src1\t# vector cmp (4F)" %}
2446 ins_cost(INSN_COST);
2447 ins_encode %{
2448 __ fcmgt(as_FloatRegister($dst$$reg), __ T4S,
2449 as_FloatRegister($src2$$reg), as_FloatRegister($src1$$reg));
2450 %}
2451 ins_pipe(vdop128);
2452 %}
2453
2454 instruct vcmlt2D(vecX dst, vecX src1, vecX src2, immI cond)
2455 %{
2456 predicate(n->as_Vector()->length() == 2 &&
2457 n->as_VectorMaskCmp()->get_predicate() == BoolTest::lt &&
2458 n->in(1)->in(1)->bottom_type()->is_vect()->element_basic_type() == T_DOUBLE);
2459 match(Set dst (VectorMaskCmp (Binary src1 src2) cond));
2460 format %{ "fcmgt $dst, $src2, $src1\t# vector cmp (2D)" %}
2461 ins_cost(INSN_COST);
2462 ins_encode %{
2463 __ fcmgt(as_FloatRegister($dst$$reg), __ T2D,
2464 as_FloatRegister($src2$$reg), as_FloatRegister($src1$$reg));
2465 %}
2466 ins_pipe(vdop128);
2467 %}
2468
2469 instruct vcmle8B(vecD dst, vecD src1, vecD src2, immI cond)
2470 %{
2471 predicate(n->as_Vector()->length() == 8 &&
2472 n->as_VectorMaskCmp()->get_predicate() == BoolTest::le &&
2473 n->in(1)->in(1)->bottom_type()->is_vect()->element_basic_type() == T_BYTE);
2474 match(Set dst (VectorMaskCmp (Binary src1 src2) cond));
2475 format %{ "cmge $dst, $src2, $src1\t# vector cmp (8B)" %}
2476 ins_cost(INSN_COST);
2477 ins_encode %{
2478 __ cmge(as_FloatRegister($dst$$reg), __ T8B,
2479 as_FloatRegister($src2$$reg), as_FloatRegister($src1$$reg));
2480 %}
2481 ins_pipe(vdop64);
2482 %}
2483
2484 instruct vcmle16B(vecX dst, vecX src1, vecX src2, immI cond)
2485 %{
2486 predicate(n->as_Vector()->length() == 16 &&
2487 n->as_VectorMaskCmp()->get_predicate() == BoolTest::le &&
2488 n->in(1)->in(1)->bottom_type()->is_vect()->element_basic_type() == T_BYTE);
2489 match(Set dst (VectorMaskCmp (Binary src1 src2) cond));
2490 format %{ "cmge $dst, $src2, $src1\t# vector cmp (16B)" %}
2491 ins_cost(INSN_COST);
2492 ins_encode %{
2493 __ cmge(as_FloatRegister($dst$$reg), __ T16B,
2494 as_FloatRegister($src2$$reg), as_FloatRegister($src1$$reg));
2495 %}
2496 ins_pipe(vdop128);
2497 %}
2498
2499 instruct vcmle4S(vecD dst, vecD src1, vecD src2, immI cond)
2500 %{
2501 predicate(n->as_Vector()->length() == 4 &&
2502 n->as_VectorMaskCmp()->get_predicate() == BoolTest::le &&
2503 n->in(1)->in(1)->bottom_type()->is_vect()->element_basic_type() == T_SHORT);
2504 match(Set dst (VectorMaskCmp (Binary src1 src2) cond));
2505 format %{ "cmge $dst, $src2, $src1\t# vector cmp (4S)" %}
2506 ins_cost(INSN_COST);
2507 ins_encode %{
2508 __ cmge(as_FloatRegister($dst$$reg), __ T4H,
2509 as_FloatRegister($src2$$reg), as_FloatRegister($src1$$reg));
2510 %}
2511 ins_pipe(vdop64);
2512 %}
2513
2514 instruct vcmle8S(vecX dst, vecX src1, vecX src2, immI cond)
2515 %{
2516 predicate(n->as_Vector()->length() == 8 &&
2517 n->as_VectorMaskCmp()->get_predicate() == BoolTest::le &&
2518 n->in(1)->in(1)->bottom_type()->is_vect()->element_basic_type() == T_SHORT);
2519 match(Set dst (VectorMaskCmp (Binary src1 src2) cond));
2520 format %{ "cmge $dst, $src2, $src1\t# vector cmp (8S)" %}
2521 ins_cost(INSN_COST);
2522 ins_encode %{
2523 __ cmge(as_FloatRegister($dst$$reg), __ T8H,
2524 as_FloatRegister($src2$$reg), as_FloatRegister($src1$$reg));
2525 %}
2526 ins_pipe(vdop128);
2527 %}
2528
2529 instruct vcmle2I(vecD dst, vecD src1, vecD src2, immI cond)
2530 %{
2531 predicate(n->as_Vector()->length() == 2 &&
2532 n->as_VectorMaskCmp()->get_predicate() == BoolTest::le &&
2533 n->in(1)->in(1)->bottom_type()->is_vect()->element_basic_type() == T_INT);
2534 match(Set dst (VectorMaskCmp (Binary src1 src2) cond));
2535 format %{ "cmge $dst, $src2, $src1\t# vector cmp (2I)" %}
2536 ins_cost(INSN_COST);
2537 ins_encode %{
2538 __ cmge(as_FloatRegister($dst$$reg), __ T2S,
2539 as_FloatRegister($src2$$reg), as_FloatRegister($src1$$reg));
2540 %}
2541 ins_pipe(vdop64);
2542 %}
2543
2544 instruct vcmle4I(vecX dst, vecX src1, vecX src2, immI cond)
2545 %{
2546 predicate(n->as_Vector()->length() == 4 &&
2547 n->as_VectorMaskCmp()->get_predicate() == BoolTest::le &&
2548 n->in(1)->in(1)->bottom_type()->is_vect()->element_basic_type() == T_INT);
2549 match(Set dst (VectorMaskCmp (Binary src1 src2) cond));
2550 format %{ "cmge $dst, $src2, $src1\t# vector cmp (4I)" %}
2551 ins_cost(INSN_COST);
2552 ins_encode %{
2553 __ cmge(as_FloatRegister($dst$$reg), __ T4S,
2554 as_FloatRegister($src2$$reg), as_FloatRegister($src1$$reg));
2555 %}
2556 ins_pipe(vdop128);
2557 %}
2558
2559 instruct vcmle2L(vecX dst, vecX src1, vecX src2, immI cond)
2560 %{
2561 predicate(n->as_Vector()->length() == 2 &&
2562 n->as_VectorMaskCmp()->get_predicate() == BoolTest::le &&
2563 n->in(1)->in(1)->bottom_type()->is_vect()->element_basic_type() == T_LONG);
2564 match(Set dst (VectorMaskCmp (Binary src1 src2) cond));
2565 format %{ "cmge $dst, $src2, $src1\t# vector cmp (2L)" %}
2566 ins_cost(INSN_COST);
2567 ins_encode %{
2568 __ cmge(as_FloatRegister($dst$$reg), __ T2D,
2569 as_FloatRegister($src2$$reg), as_FloatRegister($src1$$reg));
2570 %}
2571 ins_pipe(vdop128);
2572 %}
2573
2574 instruct vcmle2F(vecD dst, vecD src1, vecD src2, immI cond)
2575 %{
2576 predicate(n->as_Vector()->length() == 2 &&
2577 n->as_VectorMaskCmp()->get_predicate() == BoolTest::le &&
2578 n->in(1)->in(1)->bottom_type()->is_vect()->element_basic_type() == T_FLOAT);
2579 match(Set dst (VectorMaskCmp (Binary src1 src2) cond));
2580 format %{ "fcmge $dst, $src2, $src1\t# vector cmp (2F)" %}
2581 ins_cost(INSN_COST);
2582 ins_encode %{
2583 __ fcmge(as_FloatRegister($dst$$reg), __ T2S,
2584 as_FloatRegister($src2$$reg), as_FloatRegister($src1$$reg));
2585 %}
2586 ins_pipe(vdop64);
2587 %}
2588
2589 instruct vcmle4F(vecX dst, vecX src1, vecX src2, immI cond)
2590 %{
2591 predicate(n->as_Vector()->length() == 4 &&
2592 n->as_VectorMaskCmp()->get_predicate() == BoolTest::le &&
2593 n->in(1)->in(1)->bottom_type()->is_vect()->element_basic_type() == T_FLOAT);
2594 match(Set dst (VectorMaskCmp (Binary src1 src2) cond));
2595 format %{ "fcmge $dst, $src2, $src1\t# vector cmp (4F)" %}
2596 ins_cost(INSN_COST);
2597 ins_encode %{
2598 __ fcmge(as_FloatRegister($dst$$reg), __ T4S,
2599 as_FloatRegister($src2$$reg), as_FloatRegister($src1$$reg));
2600 %}
2601 ins_pipe(vdop128);
2602 %}
2603
2604 instruct vcmle2D(vecX dst, vecX src1, vecX src2, immI cond)
2605 %{
2606 predicate(n->as_Vector()->length() == 2 &&
2607 n->as_VectorMaskCmp()->get_predicate() == BoolTest::le &&
2608 n->in(1)->in(1)->bottom_type()->is_vect()->element_basic_type() == T_DOUBLE);
2609 match(Set dst (VectorMaskCmp (Binary src1 src2) cond));
2610 format %{ "fcmge $dst, $src2, $src1\t# vector cmp (2D)" %}
2611 ins_cost(INSN_COST);
2612 ins_encode %{
2613 __ fcmge(as_FloatRegister($dst$$reg), __ T2D,
2614 as_FloatRegister($src2$$reg), as_FloatRegister($src1$$reg));
2615 %}
2616 ins_pipe(vdop128);
2617 %}
2618
2619 // ------------------------------ Vector mul -----------------------------------
2620
2621 instruct vmul2L(vecX dst, vecX src1, vecX src2, iRegLNoSp tmp1, iRegLNoSp tmp2)
2622 %{
2623 predicate(n->as_Vector()->length() == 2);
2624 match(Set dst (MulVL src1 src2));
2625 ins_cost(INSN_COST);
2626 effect(TEMP tmp1, TEMP tmp2);
2627 format %{ "umov $tmp1, $src1, D, 0\n\t"
2628 "umov $tmp2, $src2, D, 0\n\t"
2629 "mul $tmp2, $tmp2, $tmp1\n\t"
2630 "mov $dst, T2D, 0, $tmp2\t# insert into vector(2L)\n\t"
2631 "umov $tmp1, $src1, D, 1\n\t"
2632 "umov $tmp2, $src2, D, 1\n\t"
2633 "mul $tmp2, $tmp2, $tmp1\n\t"
2634 "mov $dst, T2D, 1, $tmp2\t# insert into vector(2L)\n\t"
2635 %}
2636 ins_encode %{
2637 __ umov($tmp1$$Register, as_FloatRegister($src1$$reg), __ D, 0);
2638 __ umov($tmp2$$Register, as_FloatRegister($src2$$reg), __ D, 0);
2639 __ mul(as_Register($tmp2$$reg), as_Register($tmp2$$reg), as_Register($tmp1$$reg));
2640 __ mov(as_FloatRegister($dst$$reg), __ T2D, 0, $tmp2$$Register);
2641 __ umov($tmp1$$Register, as_FloatRegister($src1$$reg), __ D, 1);
2642 __ umov($tmp2$$Register, as_FloatRegister($src2$$reg), __ D, 1);
2643 __ mul(as_Register($tmp2$$reg), as_Register($tmp2$$reg), as_Register($tmp1$$reg));
2644 __ mov(as_FloatRegister($dst$$reg), __ T2D, 1, $tmp2$$Register);
2645 %}
2646 ins_pipe(pipe_slow);
2647 %}
2648
2649 // --------------------------------- Vector not --------------------------------
2650
2651 instruct vnot2I(vecD dst, vecD src, immI_M1 m1)
2652 %{
2653 predicate(n->as_Vector()->length_in_bytes() == 8);
2654 match(Set dst (XorV src (ReplicateB m1)));
2655 match(Set dst (XorV src (ReplicateS m1)));
2656 match(Set dst (XorV src (ReplicateI m1)));
2657 ins_cost(INSN_COST);
2658 format %{ "not $dst, $src\t# vector (8B)" %}
2659 ins_encode %{
2660 __ notr(as_FloatRegister($dst$$reg), __ T8B,
2661 as_FloatRegister($src$$reg));
2662 %}
2663 ins_pipe(pipe_class_default);
2664 %}
2665
2666 instruct vnot4I(vecX dst, vecX src, immI_M1 m1)
2667 %{
2668 predicate(n->as_Vector()->length_in_bytes() == 16);
2669 match(Set dst (XorV src (ReplicateB m1)));
2670 match(Set dst (XorV src (ReplicateS m1)));
2671 match(Set dst (XorV src (ReplicateI m1)));
2672 ins_cost(INSN_COST);
2673 format %{ "not $dst, $src\t# vector (16B)" %}
2674 ins_encode %{
2675 __ notr(as_FloatRegister($dst$$reg), __ T16B,
2676 as_FloatRegister($src$$reg));
2677 %}
2678 ins_pipe(pipe_class_default);
2679 %}
2680
2681 instruct vnot2L(vecX dst, vecX src, immL_M1 m1)
2682 %{
2683 predicate(n->as_Vector()->length_in_bytes() == 16);
2684 match(Set dst (XorV src (ReplicateL m1)));
2685 ins_cost(INSN_COST);
2686 format %{ "not $dst, $src\t# vector (16B)" %}
2687 ins_encode %{
2688 __ notr(as_FloatRegister($dst$$reg), __ T16B,
2689 as_FloatRegister($src$$reg));
2690 %}
2691 ins_pipe(pipe_class_default);
2692 %}
2693
2694 // ------------------------------ Vector max/min -------------------------------
2695
2696 instruct vmax8B(vecD dst, vecD src1, vecD src2)
2697 %{
2698 predicate((n->as_Vector()->length() == 4 || n->as_Vector()->length() == 8) &&
2699 n->bottom_type()->is_vect()->element_basic_type() == T_BYTE);
2700 match(Set dst (MaxV src1 src2));
2701 ins_cost(INSN_COST);
2702 format %{ "maxv $dst, $src1, $src2\t# vector (8B)" %}
2703 ins_encode %{
2704 __ maxv(as_FloatRegister($dst$$reg), __ T8B,
2705 as_FloatRegister($src1$$reg),
2706 as_FloatRegister($src2$$reg));
2707 %}
2708 ins_pipe(vdop64);
2709 %}
2710
2711 instruct vmax16B(vecX dst, vecX src1, vecX src2)
2712 %{
2713 predicate(n->as_Vector()->length() == 16 && n->bottom_type()->is_vect()->element_basic_type() == T_BYTE);
2714 match(Set dst (MaxV src1 src2));
2715 ins_cost(INSN_COST);
2716 format %{ "maxv $dst, $src1, $src2\t# vector (16B)" %}
2717 ins_encode %{
2718 __ maxv(as_FloatRegister($dst$$reg), __ T16B,
2719 as_FloatRegister($src1$$reg),
2720 as_FloatRegister($src2$$reg));
2721 %}
2722 ins_pipe(vdop128);
2723 %}
2724
2725 instruct vmax4S(vecD dst, vecD src1, vecD src2)
2726 %{
2727 predicate(n->as_Vector()->length() == 4 && n->bottom_type()->is_vect()->element_basic_type() == T_SHORT);
2728 match(Set dst (MaxV src1 src2));
2729 ins_cost(INSN_COST);
2730 format %{ "maxv $dst, $src1, $src2\t# vector (4S)" %}
2731 ins_encode %{
2732 __ maxv(as_FloatRegister($dst$$reg), __ T4H,
2733 as_FloatRegister($src1$$reg),
2734 as_FloatRegister($src2$$reg));
2735 %}
2736 ins_pipe(vdop64);
2737 %}
2738
2739 instruct vmax8S(vecX dst, vecX src1, vecX src2)
2740 %{
2741 predicate(n->as_Vector()->length() == 8 && n->bottom_type()->is_vect()->element_basic_type() == T_SHORT);
2742 match(Set dst (MaxV src1 src2));
2743 ins_cost(INSN_COST);
2744 format %{ "maxv $dst, $src1, $src2\t# vector (8S)" %}
2745 ins_encode %{
2746 __ maxv(as_FloatRegister($dst$$reg), __ T8H,
2747 as_FloatRegister($src1$$reg),
2748 as_FloatRegister($src2$$reg));
2749 %}
2750 ins_pipe(vdop128);
2751 %}
2752
2753 instruct vmax2I(vecD dst, vecD src1, vecD src2)
2754 %{
2755 predicate(n->as_Vector()->length() == 2 && n->bottom_type()->is_vect()->element_basic_type() == T_INT);
2756 match(Set dst (MaxV src1 src2));
2757 ins_cost(INSN_COST);
2758 format %{ "maxv $dst, $src1, $src2\t# vector (2I)" %}
2759 ins_encode %{
2760 __ maxv(as_FloatRegister($dst$$reg), __ T2S,
2761 as_FloatRegister($src1$$reg),
2762 as_FloatRegister($src2$$reg));
2763 %}
2764 ins_pipe(vdop64);
2765 %}
2766
2767 instruct vmax4I(vecX dst, vecX src1, vecX src2)
2768 %{
2769 predicate(n->as_Vector()->length() == 4 && n->bottom_type()->is_vect()->element_basic_type() == T_INT);
2770 match(Set dst (MaxV src1 src2));
2771 ins_cost(INSN_COST);
2772 format %{ "maxv $dst, $src1, $src2\t# vector (4I)" %}
2773 ins_encode %{
2774 __ maxv(as_FloatRegister($dst$$reg), __ T4S,
2775 as_FloatRegister($src1$$reg),
2776 as_FloatRegister($src2$$reg));
2777 %}
2778 ins_pipe(vdop128);
2779 %}
2780
2781 instruct vmin8B(vecD dst, vecD src1, vecD src2)
2782 %{
2783 predicate((n->as_Vector()->length() == 4 || n->as_Vector()->length() == 8) &&
2784 n->bottom_type()->is_vect()->element_basic_type() == T_BYTE);
2785 match(Set dst (MinV src1 src2));
2786 ins_cost(INSN_COST);
2787 format %{ "minv $dst, $src1, $src2\t# vector (8B)" %}
2788 ins_encode %{
2789 __ minv(as_FloatRegister($dst$$reg), __ T8B,
2790 as_FloatRegister($src1$$reg),
2791 as_FloatRegister($src2$$reg));
2792 %}
2793 ins_pipe(vdop64);
2794 %}
2795
2796 instruct vmin16B(vecX dst, vecX src1, vecX src2)
2797 %{
2798 predicate(n->as_Vector()->length() == 16 && n->bottom_type()->is_vect()->element_basic_type() == T_BYTE);
2799 match(Set dst (MinV src1 src2));
2800 ins_cost(INSN_COST);
2801 format %{ "minv $dst, $src1, $src2\t# vector (16B)" %}
2802 ins_encode %{
2803 __ minv(as_FloatRegister($dst$$reg), __ T16B,
2804 as_FloatRegister($src1$$reg),
2805 as_FloatRegister($src2$$reg));
2806 %}
2807 ins_pipe(vdop128);
2808 %}
2809
2810 instruct vmin4S(vecD dst, vecD src1, vecD src2)
2811 %{
2812 predicate(n->as_Vector()->length() == 4 && n->bottom_type()->is_vect()->element_basic_type() == T_SHORT);
2813 match(Set dst (MinV src1 src2));
2814 ins_cost(INSN_COST);
2815 format %{ "minv $dst, $src1, $src2\t# vector (4S)" %}
2816 ins_encode %{
2817 __ minv(as_FloatRegister($dst$$reg), __ T4H,
2818 as_FloatRegister($src1$$reg),
2819 as_FloatRegister($src2$$reg));
2820 %}
2821 ins_pipe(vdop64);
2822 %}
2823
2824 instruct vmin8S(vecX dst, vecX src1, vecX src2)
2825 %{
2826 predicate(n->as_Vector()->length() == 8 && n->bottom_type()->is_vect()->element_basic_type() == T_SHORT);
2827 match(Set dst (MinV src1 src2));
2828 ins_cost(INSN_COST);
2829 format %{ "minv $dst, $src1, $src2\t# vector (8S)" %}
2830 ins_encode %{
2831 __ minv(as_FloatRegister($dst$$reg), __ T8H,
2832 as_FloatRegister($src1$$reg),
2833 as_FloatRegister($src2$$reg));
2834 %}
2835 ins_pipe(vdop128);
2836 %}
2837
2838 instruct vmin2I(vecD dst, vecD src1, vecD src2)
2839 %{
2840 predicate(n->as_Vector()->length() == 2 && n->bottom_type()->is_vect()->element_basic_type() == T_INT);
2841 match(Set dst (MinV src1 src2));
2842 ins_cost(INSN_COST);
2843 format %{ "minv $dst, $src1, $src2\t# vector (2I)" %}
2844 ins_encode %{
2845 __ minv(as_FloatRegister($dst$$reg), __ T2S,
2846 as_FloatRegister($src1$$reg),
2847 as_FloatRegister($src2$$reg));
2848 %}
2849 ins_pipe(vdop64);
2850 %}
2851
2852 instruct vmin4I(vecX dst, vecX src1, vecX src2)
2853 %{
2854 predicate(n->as_Vector()->length() == 4 && n->bottom_type()->is_vect()->element_basic_type() == T_INT);
2855 match(Set dst (MinV src1 src2));
2856 ins_cost(INSN_COST);
2857 format %{ "minv $dst, $src1, $src2\t# vector (4I)" %}
2858 ins_encode %{
2859 __ minv(as_FloatRegister($dst$$reg), __ T4S,
2860 as_FloatRegister($src1$$reg),
2861 as_FloatRegister($src2$$reg));
2862 %}
2863 ins_pipe(vdop128);
2864 %}
2865
2866
2867 instruct vmax2L(vecX dst, vecX src1, vecX src2)
2868 %{
2869 predicate(n->as_Vector()->length() == 2 && n->bottom_type()->is_vect()->element_basic_type() == T_LONG);
2870 match(Set dst (MaxV src1 src2));
2871 ins_cost(INSN_COST);
2872 effect(TEMP dst);
2873 format %{ "cmgt $dst, $src1, $src2\t# vector (2L)\n\t"
2874 "bsl $dst, $src1, $src2\t# vector (16B)" %}
2875 ins_encode %{
2876 __ cmgt(as_FloatRegister($dst$$reg), __ T2D,
2877 as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg));
2878 __ bsl(as_FloatRegister($dst$$reg), __ T16B,
2879 as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg));
2880 %}
2881 ins_pipe(vdop128);
2882 %}
2883
2884 instruct vmin2L(vecX dst, vecX src1, vecX src2)
2885 %{
2886 predicate(n->as_Vector()->length() == 2 && n->bottom_type()->is_vect()->element_basic_type() == T_LONG);
2887 match(Set dst (MinV src1 src2));
2888 ins_cost(INSN_COST);
2889 effect(TEMP dst);
2890 format %{ "cmgt $dst, $src1, $src2\t# vector (2L)\n\t"
2891 "bsl $dst, $src2, $src1\t# vector (16B)" %}
2892 ins_encode %{
2893 __ cmgt(as_FloatRegister($dst$$reg), __ T2D,
2894 as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg));
2895 __ bsl(as_FloatRegister($dst$$reg), __ T16B,
2896 as_FloatRegister($src2$$reg), as_FloatRegister($src1$$reg));
2897 %}
2898 ins_pipe(vdop128);
2899 %}
2900
2901 // --------------------------------- blend (bsl) ----------------------------
2902
2903 instruct vbsl8B(vecD dst, vecD src1, vecD src2)
2904 %{
2905 predicate(n->as_Vector()->length_in_bytes() == 8);
2906 match(Set dst (VectorBlend (Binary src1 src2) dst));
2907 ins_cost(INSN_COST);
2908 format %{ "bsl $dst, $src2, $src1\t# vector (8B)" %}
2909 ins_encode %{
2910 __ bsl(as_FloatRegister($dst$$reg), __ T8B,
2911 as_FloatRegister($src2$$reg), as_FloatRegister($src1$$reg));
2912 %}
2913 ins_pipe(vlogical64);
2914 %}
2915
2916 instruct vbsl16B(vecX dst, vecX src1, vecX src2)
2917 %{
2918 predicate(n->as_Vector()->length_in_bytes() == 16);
2919 match(Set dst (VectorBlend (Binary src1 src2) dst));
2920 ins_cost(INSN_COST);
2921 format %{ "bsl $dst, $src2, $src1\t# vector (16B)" %}
2922 ins_encode %{
2923 __ bsl(as_FloatRegister($dst$$reg), __ T16B,
2924 as_FloatRegister($src2$$reg), as_FloatRegister($src1$$reg));
2925 %}
2926 ins_pipe(vlogical128);
2927 %}
2928
2929 // --------------------------------- Load/store Mask ----------------------------
2930
2931 instruct loadmask8B(vecD dst, vecD src )
2932 %{
2933 predicate(n->as_Vector()->length() == 8 && n->bottom_type()->is_vect()->element_basic_type() == T_BYTE);
2934 match(Set dst (VectorLoadMask src ));
2935 ins_cost(INSN_COST);
2936 format %{ "negr $dst, $src\t# load mask (8B to 8B)" %}
2937 ins_encode %{
2938 __ negr(as_FloatRegister($dst$$reg), __ T8B, as_FloatRegister($src$$reg));
2939 %}
2940 ins_pipe(pipe_class_default);
2941 %}
2942
2943 instruct loadmask16B(vecX dst, vecX src )
2944 %{
2945 predicate(n->as_Vector()->length() == 16 && n->bottom_type()->is_vect()->element_basic_type() == T_BYTE);
2946 match(Set dst (VectorLoadMask src ));
2947 ins_cost(INSN_COST);
2948 format %{ "negr $dst, $src\t# load mask (16B to 16B)" %}
2949 ins_encode %{
2950 __ negr(as_FloatRegister($dst$$reg), __ T16B, as_FloatRegister($src$$reg));
2951 %}
2952 ins_pipe(pipe_class_default);
2953 %}
2954
2955 instruct storemask8B(vecD dst, vecD src , immI_1 size)
2956 %{
2957 predicate(n->as_Vector()->length() == 8);
2958 match(Set dst (VectorStoreMask src size));
2959 ins_cost(INSN_COST);
2960 format %{ "negr $dst, $src\t# store mask (8B to 8B)" %}
2961 ins_encode %{
2962 __ negr(as_FloatRegister($dst$$reg), __ T8B, as_FloatRegister($src$$reg));
2963 %}
2964 ins_pipe(pipe_class_default);
2965 %}
2966
2967 instruct storemask16B(vecX dst, vecX src , immI_1 size)
2968 %{
2969 predicate(n->as_Vector()->length() == 16);
2970 match(Set dst (VectorStoreMask src size));
2971 ins_cost(INSN_COST);
2972 format %{ "negr $dst, $src\t# store mask (16B to 16B)" %}
2973 ins_encode %{
2974 __ negr(as_FloatRegister($dst$$reg), __ T16B, as_FloatRegister($src$$reg));
2975 %}
2976 ins_pipe(pipe_class_default);
2977 %}
2978
2979 instruct loadmask4S(vecD dst, vecD src )
2980 %{
2981 predicate(n->as_Vector()->length() == 4 && n->bottom_type()->is_vect()->element_basic_type() == T_SHORT);
2982 match(Set dst (VectorLoadMask src ));
2983 ins_cost(INSN_COST);
2984 format %{ "uxtl $dst, $src\n\t"
2985 "negr $dst, $dst\t# load mask (4B to 4H)" %}
2986 ins_encode %{
2987 __ uxtl(as_FloatRegister($dst$$reg), __ T8H, as_FloatRegister($src$$reg), __ T8B);
2988 __ negr(as_FloatRegister($dst$$reg), __ T8H, as_FloatRegister($dst$$reg));
2989 %}
2990 ins_pipe(pipe_slow);
2991 %}
2992
2993 instruct loadmask8S(vecX dst, vecD src )
2994 %{
2995 predicate(n->as_Vector()->length() == 8 && n->bottom_type()->is_vect()->element_basic_type() == T_SHORT);
2996 match(Set dst (VectorLoadMask src ));
2997 ins_cost(INSN_COST);
2998 format %{ "uxtl $dst, $src\n\t"
2999 "negr $dst, $dst\t# load mask (8B to 8H)" %}
3000 ins_encode %{
3001 __ uxtl(as_FloatRegister($dst$$reg), __ T8H, as_FloatRegister($src$$reg), __ T8B);
3002 __ negr(as_FloatRegister($dst$$reg), __ T8H, as_FloatRegister($dst$$reg));
3003 %}
3004 ins_pipe(pipe_slow);
3005 %}
3006
3007 instruct storemask4S(vecD dst, vecD src , immI_2 size)
3008 %{
3009 predicate(n->as_Vector()->length() == 4);
3010 match(Set dst (VectorStoreMask src size));
3011 ins_cost(INSN_COST);
3012 format %{ "xtn $dst, $src\n\t"
3013 "negr $dst, $dst\t# store mask (4H to 4B)" %}
3014 ins_encode %{
3015 __ xtn(as_FloatRegister($dst$$reg), __ T8B, as_FloatRegister($src$$reg), __ T8H);
3016 __ negr(as_FloatRegister($dst$$reg), __ T8B, as_FloatRegister($dst$$reg));
3017 %}
3018 ins_pipe(pipe_slow);
3019 %}
3020
3021 instruct storemask8S(vecD dst, vecX src , immI_2 size)
3022 %{
3023 predicate(n->as_Vector()->length() == 8);
3024 match(Set dst (VectorStoreMask src size));
3025 ins_cost(INSN_COST);
3026 format %{ "xtn $dst, $src\n\t"
3027 "negr $dst, $dst\t# store mask (8H to 8B)" %}
3028 ins_encode %{
3029 __ xtn(as_FloatRegister($dst$$reg), __ T8B, as_FloatRegister($src$$reg), __ T8H);
3030 __ negr(as_FloatRegister($dst$$reg), __ T8B, as_FloatRegister($dst$$reg));
3031 %}
3032 ins_pipe(pipe_slow);
3033 %}
3034
3035 instruct loadmask2I(vecD dst, vecD src )
3036 %{
3037 predicate(n->as_Vector()->length() == 2 &&
3038 (n->bottom_type()->is_vect()->element_basic_type() == T_INT ||
3039 n->bottom_type()->is_vect()->element_basic_type() == T_FLOAT));
3040 match(Set dst (VectorLoadMask src ));
3041 ins_cost(INSN_COST);
3042 format %{ "uxtl $dst, $src\t# 2B to 2H\n\t"
3043 "uxtl $dst, $dst\t# 2H to 2S\n\t"
3044 "negr $dst, $dst\t# load mask (2B to 2S)" %}
3045 ins_encode %{
3046 __ uxtl(as_FloatRegister($dst$$reg), __ T8H, as_FloatRegister($src$$reg), __ T8B);
3047 __ uxtl(as_FloatRegister($dst$$reg), __ T4S, as_FloatRegister($dst$$reg), __ T4H);
3048 __ negr(as_FloatRegister($dst$$reg), __ T4S, as_FloatRegister($dst$$reg));
3049 %}
3050 ins_pipe(pipe_slow);
3051 %}
3052
3053 instruct loadmask4I(vecX dst, vecD src )
3054 %{
3055 predicate(n->as_Vector()->length() == 4 &&
3056 (n->bottom_type()->is_vect()->element_basic_type() == T_INT ||
3057 n->bottom_type()->is_vect()->element_basic_type() == T_FLOAT));
3058 match(Set dst (VectorLoadMask src ));
3059 ins_cost(INSN_COST);
3060 format %{ "uxtl $dst, $src\t# 4B to 4H\n\t"
3061 "uxtl $dst, $dst\t# 4H to 4S\n\t"
3062 "negr $dst, $dst\t# load mask (4B to 4S)" %}
3063 ins_encode %{
3064 __ uxtl(as_FloatRegister($dst$$reg), __ T8H, as_FloatRegister($src$$reg), __ T8B);
3065 __ uxtl(as_FloatRegister($dst$$reg), __ T4S, as_FloatRegister($dst$$reg), __ T4H);
3066 __ negr(as_FloatRegister($dst$$reg), __ T4S, as_FloatRegister($dst$$reg));
3067 %}
3068 ins_pipe(pipe_slow);
3069 %}
3070
3071 instruct storemask2I(vecD dst, vecD src , immI_4 size)
3072 %{
3073 predicate(n->as_Vector()->length() == 2);
3074 match(Set dst (VectorStoreMask src size));
3075 ins_cost(INSN_COST);
3076 format %{ "xtn $dst, $src\t# 2S to 2H\n\t"
3077 "xtn $dst, $dst\t# 2H to 2B\n\t"
3078 "negr $dst, $dst\t# store mask (2S to 2B)" %}
3079 ins_encode %{
3080 __ xtn(as_FloatRegister($dst$$reg), __ T4H, as_FloatRegister($src$$reg), __ T4S);
3081 __ xtn(as_FloatRegister($dst$$reg), __ T8B, as_FloatRegister($dst$$reg), __ T8H);
3082 __ negr(as_FloatRegister($dst$$reg), __ T8B, as_FloatRegister($dst$$reg));
3083 %}
3084 ins_pipe(pipe_slow);
3085 %}
3086
3087 instruct storemask4I(vecD dst, vecX src , immI_4 size)
3088 %{
3089 predicate(n->as_Vector()->length() == 4);
3090 match(Set dst (VectorStoreMask src size));
3091 ins_cost(INSN_COST);
3092 format %{ "xtn $dst, $src\t# 4S to 4H\n\t"
3093 "xtn $dst, $dst\t# 4H to 4B\n\t"
3094 "negr $dst, $dst\t# store mask (4S to 4B)" %}
3095 ins_encode %{
3096 __ xtn(as_FloatRegister($dst$$reg), __ T4H, as_FloatRegister($src$$reg), __ T4S);
3097 __ xtn(as_FloatRegister($dst$$reg), __ T8B, as_FloatRegister($dst$$reg), __ T8H);
3098 __ negr(as_FloatRegister($dst$$reg), __ T8B, as_FloatRegister($dst$$reg));
3099 %}
3100 ins_pipe(pipe_slow);
3101 %}
3102
3103 instruct loadmask2L(vecX dst, vecD src)
3104 %{
3105 predicate(n->as_Vector()->length() == 2 &&
3106 (n->bottom_type()->is_vect()->element_basic_type() == T_LONG ||
3107 n->bottom_type()->is_vect()->element_basic_type() == T_DOUBLE));
3108 match(Set dst (VectorLoadMask src));
3109 ins_cost(INSN_COST);
3110 format %{ "uxtl $dst, $src\t# 2B to 2S\n\t"
3111 "uxtl $dst, $dst\t# 2S to 2I\n\t"
3112 "uxtl $dst, $dst\t# 2I to 2L\n\t"
3113 "neg $dst, $dst\t# load mask (2B to 2L)" %}
3114 ins_encode %{
3115 __ uxtl(as_FloatRegister($dst$$reg), __ T8H, as_FloatRegister($src$$reg), __ T8B);
3116 __ uxtl(as_FloatRegister($dst$$reg), __ T4S, as_FloatRegister($dst$$reg), __ T4H);
3117 __ uxtl(as_FloatRegister($dst$$reg), __ T2D, as_FloatRegister($dst$$reg), __ T2S);
3118 __ negr(as_FloatRegister($dst$$reg), __ T2D, as_FloatRegister($dst$$reg));
3119 %}
3120 ins_pipe(pipe_slow);
3121 %}
3122
3123 instruct storemask2L(vecD dst, vecX src, immI_8 size)
3124 %{
3125 predicate(n->as_Vector()->length() == 2);
3126 match(Set dst (VectorStoreMask src size));
3127 ins_cost(INSN_COST);
3128 format %{ "xtn $dst, $src\t# 2L to 2I\n\t"
3129 "xtn $dst, $dst\t# 2I to 2S\n\t"
3130 "xtn $dst, $dst\t# 2S to 2B\n\t"
3131 "neg $dst, $dst\t# store mask (2L to 2B)" %}
3132 ins_encode %{
3133 __ xtn(as_FloatRegister($dst$$reg), __ T2S, as_FloatRegister($src$$reg), __ T2D);
3134 __ xtn(as_FloatRegister($dst$$reg), __ T4H, as_FloatRegister($dst$$reg), __ T4S);
3135 __ xtn(as_FloatRegister($dst$$reg), __ T8B, as_FloatRegister($dst$$reg), __ T8H);
3136 __ negr(as_FloatRegister($dst$$reg), __ T8B, as_FloatRegister($dst$$reg));
3137 %}
3138 ins_pipe(pipe_slow);
3139 %}
3140
3141 //-------------------------------- LOAD_IOTA_INDICES----------------------------------
3142
3143 instruct loadcon8B(vecD dst, immI0 src)
3144 %{
3145 predicate((n->as_Vector()->length() == 2 || n->as_Vector()->length() == 4 ||
3146 n->as_Vector()->length() == 8) &&
3147 n->bottom_type()->is_vect()->element_basic_type() == T_BYTE);
3148 match(Set dst (VectorLoadConst src));
3149 ins_cost(INSN_COST);
3150 format %{ "ldr $dst, CONSTANT_MEMORY\t# load iota indices" %}
3151 ins_encode %{
3152 __ lea(rscratch1, ExternalAddress(StubRoutines::aarch64::vector_iota_indices()));
3153 __ ldrd(as_FloatRegister($dst$$reg), rscratch1);
3154 %}
3155 ins_pipe(pipe_class_memory);
3156 %}
3157
3158 instruct loadcon16B(vecX dst, immI0 src)
3159 %{
3160 predicate(n->as_Vector()->length() == 16 && n->bottom_type()->is_vect()->element_basic_type() == T_BYTE);
3161 match(Set dst (VectorLoadConst src));
3162 ins_cost(INSN_COST);
3163 format %{ "ldr $dst, CONSTANT_MEMORY\t# load iota indices" %}
3164 ins_encode %{
3165 __ lea(rscratch1, ExternalAddress(StubRoutines::aarch64::vector_iota_indices()));
3166 __ ldrq(as_FloatRegister($dst$$reg), rscratch1);
3167 %}
3168 ins_pipe(pipe_class_memory);
3169 %}
3170
3171 //-------------------------------- LOAD_SHUFFLE ----------------------------------
3172
3173 instruct loadshuffle8B(vecD dst, vecD src)
3174 %{
3175 predicate(n->as_Vector()->length() == 8 &&
3176 n->bottom_type()->is_vect()->element_basic_type() == T_BYTE);
3177 match(Set dst (VectorLoadShuffle src));
3178 ins_cost(INSN_COST);
3179 format %{ "mov $dst, $src\t# get 8B shuffle" %}
3180 ins_encode %{
3181 __ orr(as_FloatRegister($dst$$reg), __ T8B,
3182 as_FloatRegister($src$$reg), as_FloatRegister($src$$reg));
3183 %}
3184 ins_pipe(pipe_class_default);
3185 %}
3186
3187 instruct loadshuffle16B(vecX dst, vecX src)
3188 %{
3189 predicate(n->as_Vector()->length() == 16 &&
3190 n->bottom_type()->is_vect()->element_basic_type() == T_BYTE);
3191 match(Set dst (VectorLoadShuffle src));
3192 ins_cost(INSN_COST);
3193 format %{ "mov $dst, $src\t# get 16B shuffle" %}
3194 ins_encode %{
3195 __ orr(as_FloatRegister($dst$$reg), __ T16B,
3196 as_FloatRegister($src$$reg), as_FloatRegister($src$$reg));
3197 %}
3198 ins_pipe(pipe_class_default);
3199 %}
3200
3201 instruct loadshuffle4S(vecD dst, vecD src)
3202 %{
3203 predicate(n->as_Vector()->length() == 4 &&
3204 n->bottom_type()->is_vect()->element_basic_type() == T_SHORT);
3205 match(Set dst (VectorLoadShuffle src));
3206 ins_cost(INSN_COST);
3207 format %{ "uxtl $dst, $src\t# 4B to 4H" %}
3208 ins_encode %{
3209 __ uxtl(as_FloatRegister($dst$$reg), __ T8H, as_FloatRegister($src$$reg), __ T8B);
3210 %}
3211 ins_pipe(pipe_class_default);
3212 %}
3213
3214 instruct loadshuffle8S(vecX dst, vecD src)
3215 %{
3216 predicate(n->as_Vector()->length() == 8 &&
3217 n->bottom_type()->is_vect()->element_basic_type() == T_SHORT);
3218 match(Set dst (VectorLoadShuffle src));
3219 ins_cost(INSN_COST);
3220 format %{ "uxtl $dst, $src\t# 8B to 8H" %}
3221 ins_encode %{
3222 __ uxtl(as_FloatRegister($dst$$reg), __ T8H, as_FloatRegister($src$$reg), __ T8B);
3223 %}
3224 ins_pipe(pipe_class_default);
3225 %}
3226
3227 instruct loadshuffle4I(vecX dst, vecD src)
3228 %{
3229 predicate(n->as_Vector()->length() == 4 &&
3230 (n->bottom_type()->is_vect()->element_basic_type() == T_INT ||
3231 n->bottom_type()->is_vect()->element_basic_type() == T_FLOAT));
3232 match(Set dst (VectorLoadShuffle src));
3233 ins_cost(INSN_COST);
3234 format %{ "uxtl $dst, $src\t# 4B to 4H \n\t"
3235 "uxtl $dst, $dst\t# 4H to 4S" %}
3236 ins_encode %{
3237 __ uxtl(as_FloatRegister($dst$$reg), __ T8H, as_FloatRegister($src$$reg), __ T8B);
3238 __ uxtl(as_FloatRegister($dst$$reg), __ T4S, as_FloatRegister($dst$$reg), __ T4H);
3239 %}
3240 ins_pipe(pipe_slow);
3241 %}
3242
3243 //-------------------------------- Rearrange -------------------------------------
3244 // Here is an example that rearranges a NEON vector with 4 ints:
3245 // Rearrange V1 int[a0, a1, a2, a3] to V2 int[a2, a3, a0, a1]
3246 // 1. Get the indices of V1 and store them as Vi byte[0, 1, 2, 3].
3247 // 2. Convert Vi byte[0, 1, 2, 3] to the indices of V2 and also store them as Vi byte[2, 3, 0, 1].
3248 // 3. Unsigned extend Long Vi from byte[2, 3, 0, 1] to int[2, 3, 0, 1].
3249 // 4. Multiply Vi int[2, 3, 0, 1] with constant int[0x04040404, 0x04040404, 0x04040404, 0x04040404]
3250 // and get tbl base Vm int[0x08080808, 0x0c0c0c0c, 0x00000000, 0x04040404].
3251 // 5. Add Vm with constant int[0x03020100, 0x03020100, 0x03020100, 0x03020100]
3252 // and get tbl index Vm int[0x0b0a0908, 0x0f0e0d0c, 0x03020100, 0x07060504]
3253 // 6. Use Vm as index register, and use V1 as table register.
3254 // Then get V2 as the result by tbl NEON instructions.
3255 // Notes:
3256 // Step 1 matches VectorLoadConst.
3257 // Step 3 matches VectorLoadShuffle.
3258 // Step 4, 5, 6 match VectorRearrange.
3259 // For VectorRearrange short/int, the reason why such complex calculation is
3260 // required is because NEON tbl supports bytes table only, so for short/int, we
3261 // need to lookup 2/4 bytes as a group. For VectorRearrange long, we use bsl
3262 // to implement rearrange.
3263
3264 instruct rearrange8B(vecD dst, vecD src, vecD shuffle)
3265 %{
3266 predicate(n->as_Vector()->length() == 8 &&
3267 n->bottom_type()->is_vect()->element_basic_type() == T_BYTE);
3268 match(Set dst (VectorRearrange src shuffle));
3269 ins_cost(INSN_COST);
3270 effect(TEMP_DEF dst);
3271 format %{ "tbl $dst, {$dst}, $shuffle\t# rearrange 8B" %}
3272 ins_encode %{
3273 __ tbl(as_FloatRegister($dst$$reg), __ T8B,
3274 as_FloatRegister($src$$reg), 1, as_FloatRegister($shuffle$$reg));
3275 %}
3276 ins_pipe(pipe_slow);
3277 %}
3278
3279 instruct rearrange16B(vecX dst, vecX src, vecX shuffle)
3280 %{
3281 predicate(n->as_Vector()->length() == 16 &&
3282 n->bottom_type()->is_vect()->element_basic_type() == T_BYTE);
3283 match(Set dst (VectorRearrange src shuffle));
3284 ins_cost(INSN_COST);
3285 effect(TEMP_DEF dst);
3286 format %{ "tbl $dst, {$dst}, $shuffle\t# rearrange 16B" %}
3287 ins_encode %{
3288 __ tbl(as_FloatRegister($dst$$reg), __ T16B,
3289 as_FloatRegister($src$$reg), 1, as_FloatRegister($shuffle$$reg));
3290 %}
3291 ins_pipe(pipe_slow);
3292 %}
3293
3294 instruct rearrange4S(vecD dst, vecD src, vecD shuffle, vecD tmp0, vecD tmp1)
3295 %{
3296 predicate(n->as_Vector()->length() == 4 &&
3297 n->bottom_type()->is_vect()->element_basic_type() == T_SHORT);
3298 match(Set dst (VectorRearrange src shuffle));
3299 ins_cost(INSN_COST);
3300 effect(TEMP_DEF dst, TEMP tmp0, TEMP tmp1);
3301 format %{ "mov $tmp0, CONSTANT\t# constant 0x0202020202020202\n\t"
3302 "mov $tmp1, CONSTANT\t# constant 0x0100010001000100\n\t"
3303 "mulv $dst, T4H, $shuffle, $tmp0\n\t"
3304 "addv $dst, T8B, $dst, $tmp1\n\t"
3305 "tbl $dst, {$src}, $dst\t# rearrange 4S" %}
3306 ins_encode %{
3307 __ mov(as_FloatRegister($tmp0$$reg), __ T8B, 0x02);
3308 __ mov(as_FloatRegister($tmp1$$reg), __ T4H, 0x0100);
3309 __ mulv(as_FloatRegister($dst$$reg), __ T4H,
3310 as_FloatRegister($shuffle$$reg), as_FloatRegister($tmp0$$reg));
3311 __ addv(as_FloatRegister($dst$$reg), __ T8B,
3312 as_FloatRegister($dst$$reg), as_FloatRegister($tmp1$$reg));
3313 __ tbl(as_FloatRegister($dst$$reg), __ T8B,
3314 as_FloatRegister($src$$reg), 1, as_FloatRegister($dst$$reg));
3315 %}
3316 ins_pipe(pipe_slow);
3317 %}
3318
3319 instruct rearrange8S(vecX dst, vecX src, vecX shuffle, vecX tmp0, vecX tmp1)
3320 %{
3321 predicate(n->as_Vector()->length() == 8 &&
3322 n->bottom_type()->is_vect()->element_basic_type() == T_SHORT);
3323 match(Set dst (VectorRearrange src shuffle));
3324 ins_cost(INSN_COST);
3325 effect(TEMP_DEF dst, TEMP tmp0, TEMP tmp1);
3326 format %{ "mov $tmp0, CONSTANT\t# constant 0x0202020202020202\n\t"
3327 "mov $tmp1, CONSTANT\t# constant 0x0100010001000100\n\t"
3328 "mulv $dst, T8H, $shuffle, $tmp0\n\t"
3329 "addv $dst, T16B, $dst, $tmp1\n\t"
3330 "tbl $dst, {$src}, $dst\t# rearrange 8S" %}
3331 ins_encode %{
3332 __ mov(as_FloatRegister($tmp0$$reg), __ T16B, 0x02);
3333 __ mov(as_FloatRegister($tmp1$$reg), __ T8H, 0x0100);
3334 __ mulv(as_FloatRegister($dst$$reg), __ T8H,
3335 as_FloatRegister($shuffle$$reg), as_FloatRegister($tmp0$$reg));
3336 __ addv(as_FloatRegister($dst$$reg), __ T16B,
3337 as_FloatRegister($dst$$reg), as_FloatRegister($tmp1$$reg));
3338 __ tbl(as_FloatRegister($dst$$reg), __ T16B,
3339 as_FloatRegister($src$$reg), 1, as_FloatRegister($dst$$reg));
3340 %}
3341 ins_pipe(pipe_slow);
3342 %}
3343
3344 instruct rearrange4I(vecX dst, vecX src, vecX shuffle, vecX tmp0, vecX tmp1)
3345 %{
3346 predicate(n->as_Vector()->length() == 4 &&
3347 (n->bottom_type()->is_vect()->element_basic_type() == T_INT ||
3348 n->bottom_type()->is_vect()->element_basic_type() == T_FLOAT));
3349 match(Set dst (VectorRearrange src shuffle));
3350 ins_cost(INSN_COST);
3351 effect(TEMP_DEF dst, TEMP tmp0, TEMP tmp1);
3352 format %{ "mov $tmp0, CONSTANT\t# constant 0x0404040404040404\n\t"
3353 "mov $tmp1, CONSTANT\t# constant 0x0302010003020100\n\t"
3354 "mulv $dst, T8H, $shuffle, $tmp0\n\t"
3355 "addv $dst, T16B, $dst, $tmp1\n\t"
3356 "tbl $dst, {$src}, $dst\t# rearrange 4I" %}
3357 ins_encode %{
3358 __ mov(as_FloatRegister($tmp0$$reg), __ T16B, 0x04);
3359 __ mov(as_FloatRegister($tmp1$$reg), __ T4S, 0x03020100);
3360 __ mulv(as_FloatRegister($dst$$reg), __ T4S,
3361 as_FloatRegister($shuffle$$reg), as_FloatRegister($tmp0$$reg));
3362 __ addv(as_FloatRegister($dst$$reg), __ T16B,
3363 as_FloatRegister($dst$$reg), as_FloatRegister($tmp1$$reg));
3364 __ tbl(as_FloatRegister($dst$$reg), __ T16B,
3365 as_FloatRegister($src$$reg), 1, as_FloatRegister($dst$$reg));
3366 %}
3367 ins_pipe(pipe_slow);
3368 %}
3369
3370 //-------------------------------- Anytrue/alltrue -----------------------------
3371
3372 instruct anytrue_in_mask8B(iRegINoSp dst, vecD src1, vecD src2, vecD tmp, rFlagsReg cr)
3373 %{
3374 predicate(static_cast<const VectorTestNode*>(n)->get_predicate() == BoolTest::ne);
3375 match(Set dst (VectorTest src1 src2 ));
3376 ins_cost(INSN_COST);
3377 effect(TEMP tmp, KILL cr);
3378 format %{ "addv $tmp, T8B, $src1\t# src1 and src2 are the same\n\t"
3379 "umov $dst, $tmp, B, 0\n\t"
3380 "cmp $dst, 0\n\t"
3381 "cset $dst" %}
3382 ins_encode %{
3383 __ addv(as_FloatRegister($tmp$$reg), __ T8B, as_FloatRegister($src1$$reg));
3384 __ umov($dst$$Register, as_FloatRegister($tmp$$reg), __ B, 0);
3385 __ cmpw($dst$$Register, zr);
3386 __ csetw($dst$$Register, Assembler::NE);
3387 %}
3388 ins_pipe(pipe_slow);
3389 %}
3390
3391 instruct anytrue_in_mask16B(iRegINoSp dst, vecX src1, vecX src2, vecX tmp, rFlagsReg cr)
3392 %{
3393 predicate(static_cast<const VectorTestNode*>(n)->get_predicate() == BoolTest::ne);
3394 match(Set dst (VectorTest src1 src2 ));
3395 ins_cost(INSN_COST);
3396 effect(TEMP tmp, KILL cr);
3397 format %{ "addv $tmp, T16B, $src1\t# src1 and src2 are the same\n\t"
3398 "umov $dst, $tmp, B, 0\n\t"
3399 "cmp $dst, 0\n\t"
3400 "cset $dst" %}
3401 ins_encode %{
3402 __ addv(as_FloatRegister($tmp$$reg), __ T16B, as_FloatRegister($src1$$reg));
3403 __ umov($dst$$Register, as_FloatRegister($tmp$$reg), __ B, 0);
3404 __ cmpw($dst$$Register, zr);
3405 __ csetw($dst$$Register, Assembler::NE);
3406 %}
3407 ins_pipe(pipe_slow);
3408 %}
3409
3410 instruct alltrue_in_mask8B(iRegINoSp dst, vecD src1, vecD src2, vecD tmp, rFlagsReg cr)
3411 %{
3412 predicate(static_cast<const VectorTestNode*>(n)->get_predicate() == BoolTest::overflow);
3413 match(Set dst (VectorTest src1 src2 ));
3414 ins_cost(INSN_COST);
3415 effect(TEMP tmp, KILL cr);
3416 format %{ "andr $tmp, T8B, $src1, $src2\t# src2 is maskAllTrue\n\t"
3417 "notr $tmp, T8B, $tmp\n\t"
3418 "addv $tmp, T8B, $tmp\n\t"
3419 "umov $dst, $tmp, B, 0\n\t"
3420 "cmp $dst, 0\n\t"
3421 "cset $dst" %}
3422 ins_encode %{
3423 __ andr(as_FloatRegister($tmp$$reg), __ T8B,
3424 as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg));
3425 __ notr(as_FloatRegister($tmp$$reg), __ T8B, as_FloatRegister($tmp$$reg));
3426 __ addv(as_FloatRegister($tmp$$reg), __ T8B, as_FloatRegister($tmp$$reg));
3427 __ umov($dst$$Register, as_FloatRegister($tmp$$reg), __ B, 0);
3428 __ cmpw($dst$$Register, zr);
3429 __ csetw($dst$$Register, Assembler::EQ);
3430 %}
3431 ins_pipe(pipe_slow);
3432 %}
3433
3434 instruct alltrue_in_mask16B(iRegINoSp dst, vecX src1, vecX src2, vecX tmp, rFlagsReg cr)
3435 %{
3436 predicate(static_cast<const VectorTestNode*>(n)->get_predicate() == BoolTest::overflow);
3437 match(Set dst (VectorTest src1 src2 ));
3438 ins_cost(INSN_COST);
3439 effect(TEMP tmp, KILL cr);
3440 format %{ "andr $tmp, T16B, $src1, $src2\t# src2 is maskAllTrue\n\t"
3441 "notr $tmp, T16B, $tmp\n\t"
3442 "addv $tmp, T16B, $tmp\n\t"
3443 "umov $dst, $tmp, B, 0\n\t"
3444 "cmp $dst, 0\n\t"
3445 "cset $dst" %}
3446 ins_encode %{
3447 __ andr(as_FloatRegister($tmp$$reg), __ T16B,
3448 as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg));
3449 __ notr(as_FloatRegister($tmp$$reg), __ T16B, as_FloatRegister($tmp$$reg));
3450 __ addv(as_FloatRegister($tmp$$reg), __ T16B, as_FloatRegister($tmp$$reg));
3451 __ umov($dst$$Register, as_FloatRegister($tmp$$reg), __ B, 0);
3452 __ cmpw($dst$$Register, zr);
3453 __ csetw($dst$$Register, Assembler::EQ);
3454 %}
3455 ins_pipe(pipe_slow);
3456 %}