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src/hotspot/share/opto/matcher.cpp

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*** 421,431 **** rms[TypeFunc::ReturnAdr] = ret_adr; rms[TypeFunc::FramePtr ] = fp; return rms; } ! #define NOF_STACK_MASKS (3*6+5) // Create the initial stack mask used by values spilling to the stack. // Disallow any debug info in outgoing argument areas by setting the // initial mask accordingly. void Matcher::init_first_stack_mask() { --- 421,431 ---- rms[TypeFunc::ReturnAdr] = ret_adr; rms[TypeFunc::FramePtr ] = fp; return rms; } ! #define NOF_STACK_MASKS (3*11) // Create the initial stack mask used by values spilling to the stack. // Disallow any debug info in outgoing argument areas by setting the // initial mask accordingly. void Matcher::init_first_stack_mask() {
*** 463,472 **** --- 463,484 ---- idealreg2spillmask [Op_VecD] = &rms[19]; idealreg2spillmask [Op_VecX] = &rms[20]; idealreg2spillmask [Op_VecY] = &rms[21]; idealreg2spillmask [Op_VecZ] = &rms[22]; + idealreg2debugmask [Op_VecS] = &rms[23]; + idealreg2debugmask [Op_VecD] = &rms[24]; + idealreg2debugmask [Op_VecX] = &rms[25]; + idealreg2debugmask [Op_VecY] = &rms[26]; + idealreg2debugmask [Op_VecZ] = &rms[27]; + + idealreg2mhdebugmask[Op_VecS] = &rms[28]; + idealreg2mhdebugmask[Op_VecD] = &rms[29]; + idealreg2mhdebugmask[Op_VecX] = &rms[30]; + idealreg2mhdebugmask[Op_VecY] = &rms[31]; + idealreg2mhdebugmask[Op_VecZ] = &rms[32]; + OptoReg::Name i; // At first, start with the empty mask C->FIRST_STACK_mask().Clear();
*** 509,525 **** --- 521,543 ---- idealreg2spillmask[Op_RegD]->OR(aligned_stack_mask); if (Matcher::vector_size_supported(T_BYTE,4)) { *idealreg2spillmask[Op_VecS] = *idealreg2regmask[Op_VecS]; idealreg2spillmask[Op_VecS]->OR(C->FIRST_STACK_mask()); + } else { + *idealreg2spillmask[Op_VecS] = RegMask::Empty; } + if (Matcher::vector_size_supported(T_FLOAT,2)) { // For VecD we need dual alignment and 8 bytes (2 slots) for spills. // RA guarantees such alignment since it is needed for Double and Long values. *idealreg2spillmask[Op_VecD] = *idealreg2regmask[Op_VecD]; idealreg2spillmask[Op_VecD]->OR(aligned_stack_mask); + } else { + *idealreg2spillmask[Op_VecD] = RegMask::Empty; } + if (Matcher::vector_size_supported(T_FLOAT,4)) { // For VecX we need quadro alignment and 16 bytes (4 slots) for spills. // // RA can use input arguments stack slots for spills but until RA // we don't know frame size and offset of input arg stack slots.
*** 533,543 **** --- 551,564 ---- } aligned_stack_mask.clear_to_sets(RegMask::SlotsPerVecX); assert(aligned_stack_mask.is_AllStack(), "should be infinite stack"); *idealreg2spillmask[Op_VecX] = *idealreg2regmask[Op_VecX]; idealreg2spillmask[Op_VecX]->OR(aligned_stack_mask); + } else { + *idealreg2spillmask[Op_VecX] = RegMask::Empty; } + if (Matcher::vector_size_supported(T_FLOAT,8)) { // For VecY we need octo alignment and 32 bytes (8 slots) for spills. OptoReg::Name in = OptoReg::add(_in_arg_limit, -1); for (int k = 1; (in >= init_in) && (k < RegMask::SlotsPerVecY); k++) { aligned_stack_mask.Remove(in);
*** 545,555 **** --- 566,579 ---- } aligned_stack_mask.clear_to_sets(RegMask::SlotsPerVecY); assert(aligned_stack_mask.is_AllStack(), "should be infinite stack"); *idealreg2spillmask[Op_VecY] = *idealreg2regmask[Op_VecY]; idealreg2spillmask[Op_VecY]->OR(aligned_stack_mask); + } else { + *idealreg2spillmask[Op_VecY] = RegMask::Empty; } + if (Matcher::vector_size_supported(T_FLOAT,16)) { // For VecZ we need enough alignment and 64 bytes (16 slots) for spills. OptoReg::Name in = OptoReg::add(_in_arg_limit, -1); for (int k = 1; (in >= init_in) && (k < RegMask::SlotsPerVecZ); k++) { aligned_stack_mask.Remove(in);
*** 557,567 **** --- 581,594 ---- } aligned_stack_mask.clear_to_sets(RegMask::SlotsPerVecZ); assert(aligned_stack_mask.is_AllStack(), "should be infinite stack"); *idealreg2spillmask[Op_VecZ] = *idealreg2regmask[Op_VecZ]; idealreg2spillmask[Op_VecZ]->OR(aligned_stack_mask); + } else { + *idealreg2spillmask[Op_VecZ] = RegMask::Empty; } + if (UseFPUForSpilling) { // This mask logic assumes that the spill operations are // symmetric and that the registers involved are the same size. // On sparc for instance we may have to use 64 bit moves will // kill 2 registers when used with F0-F31.
*** 591,607 **** --- 618,646 ---- *idealreg2debugmask [Op_RegL]= *idealreg2spillmask[Op_RegL]; *idealreg2debugmask [Op_RegF]= *idealreg2spillmask[Op_RegF]; *idealreg2debugmask [Op_RegD]= *idealreg2spillmask[Op_RegD]; *idealreg2debugmask [Op_RegP]= *idealreg2spillmask[Op_RegP]; + *idealreg2debugmask [Op_VecS]= *idealreg2spillmask[Op_VecS]; + *idealreg2debugmask [Op_VecD]= *idealreg2spillmask[Op_VecD]; + *idealreg2debugmask [Op_VecX]= *idealreg2spillmask[Op_VecX]; + *idealreg2debugmask [Op_VecY]= *idealreg2spillmask[Op_VecY]; + *idealreg2debugmask [Op_VecZ]= *idealreg2spillmask[Op_VecZ]; + *idealreg2mhdebugmask[Op_RegN]= *idealreg2spillmask[Op_RegN]; *idealreg2mhdebugmask[Op_RegI]= *idealreg2spillmask[Op_RegI]; *idealreg2mhdebugmask[Op_RegL]= *idealreg2spillmask[Op_RegL]; *idealreg2mhdebugmask[Op_RegF]= *idealreg2spillmask[Op_RegF]; *idealreg2mhdebugmask[Op_RegD]= *idealreg2spillmask[Op_RegD]; *idealreg2mhdebugmask[Op_RegP]= *idealreg2spillmask[Op_RegP]; + *idealreg2mhdebugmask[Op_VecS]= *idealreg2spillmask[Op_VecS]; + *idealreg2mhdebugmask[Op_VecD]= *idealreg2spillmask[Op_VecD]; + *idealreg2mhdebugmask[Op_VecX]= *idealreg2spillmask[Op_VecX]; + *idealreg2mhdebugmask[Op_VecY]= *idealreg2spillmask[Op_VecY]; + *idealreg2mhdebugmask[Op_VecZ]= *idealreg2spillmask[Op_VecZ]; + // Prevent stub compilations from attempting to reference // callee-saved registers from debug info bool exclude_soe = !Compile::current()->is_method_compilation(); for( i=OptoReg::Name(0); i<OptoReg::Name(_last_Mach_Reg); i = OptoReg::add(i,1) ) {
*** 613,629 **** --- 652,678 ---- idealreg2debugmask [Op_RegI]->Remove(i); // Exclude save-on-call idealreg2debugmask [Op_RegL]->Remove(i); // registers from debug idealreg2debugmask [Op_RegF]->Remove(i); // masks idealreg2debugmask [Op_RegD]->Remove(i); idealreg2debugmask [Op_RegP]->Remove(i); + idealreg2debugmask [Op_VecS]->Remove(i); + idealreg2debugmask [Op_VecD]->Remove(i); + idealreg2debugmask [Op_VecX]->Remove(i); + idealreg2debugmask [Op_VecY]->Remove(i); + idealreg2debugmask [Op_VecZ]->Remove(i); idealreg2mhdebugmask[Op_RegN]->Remove(i); idealreg2mhdebugmask[Op_RegI]->Remove(i); idealreg2mhdebugmask[Op_RegL]->Remove(i); idealreg2mhdebugmask[Op_RegF]->Remove(i); idealreg2mhdebugmask[Op_RegD]->Remove(i); idealreg2mhdebugmask[Op_RegP]->Remove(i); + idealreg2mhdebugmask[Op_VecS]->Remove(i); + idealreg2mhdebugmask[Op_VecD]->Remove(i); + idealreg2mhdebugmask[Op_VecX]->Remove(i); + idealreg2mhdebugmask[Op_VecY]->Remove(i); + idealreg2mhdebugmask[Op_VecZ]->Remove(i); } } // Subtract the register we use to save the SP for MethodHandle // invokes to from the debug mask.
*** 632,641 **** --- 681,695 ---- idealreg2mhdebugmask[Op_RegI]->SUBTRACT(save_mask); idealreg2mhdebugmask[Op_RegL]->SUBTRACT(save_mask); idealreg2mhdebugmask[Op_RegF]->SUBTRACT(save_mask); idealreg2mhdebugmask[Op_RegD]->SUBTRACT(save_mask); idealreg2mhdebugmask[Op_RegP]->SUBTRACT(save_mask); + idealreg2mhdebugmask[Op_VecS]->SUBTRACT(save_mask); + idealreg2mhdebugmask[Op_VecD]->SUBTRACT(save_mask); + idealreg2mhdebugmask[Op_VecX]->SUBTRACT(save_mask); + idealreg2mhdebugmask[Op_VecY]->SUBTRACT(save_mask); + idealreg2mhdebugmask[Op_VecZ]->SUBTRACT(save_mask); } //---------------------------is_save_on_entry---------------------------------- bool Matcher::is_save_on_entry( int reg ) { return
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