1 /* 2 * Copyright (c) 1997, 2014, Oracle and/or its affiliates. All rights reserved. 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 4 * 5 * This code is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License version 2 only, as 7 * published by the Free Software Foundation. 8 * 9 * This code is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 12 * version 2 for more details (a copy is included in the LICENSE file that 13 * accompanied this code). 14 * 15 * You should have received a copy of the GNU General Public License version 16 * 2 along with this work; if not, write to the Free Software Foundation, 17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 18 * 19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA 20 * or visit www.oracle.com if you need additional information or have any 21 * questions. 22 * 23 */ 24 25 #ifndef CPU_X86_VM_VM_VERSION_X86_HPP 26 #define CPU_X86_VM_VM_VERSION_X86_HPP 27 28 #include "runtime/globals_extension.hpp" 29 #include "runtime/vm_version.hpp" 30 31 class VM_Version : public Abstract_VM_Version { 32 public: 33 // cpuid result register layouts. These are all unions of a uint32_t 34 // (in case anyone wants access to the register as a whole) and a bitfield. 35 36 union StdCpuid1Eax { 37 uint32_t value; 38 struct { 39 uint32_t stepping : 4, 40 model : 4, 41 family : 4, 42 proc_type : 2, 43 : 2, 44 ext_model : 4, 45 ext_family : 8, 46 : 4; 47 } bits; 48 }; 49 50 union StdCpuid1Ebx { // example, unused 51 uint32_t value; 52 struct { 53 uint32_t brand_id : 8, 54 clflush_size : 8, 55 threads_per_cpu : 8, 56 apic_id : 8; 57 } bits; 58 }; 59 60 union StdCpuid1Ecx { 61 uint32_t value; 62 struct { 63 uint32_t sse3 : 1, 64 clmul : 1, 65 : 1, 66 monitor : 1, 67 : 1, 68 vmx : 1, 69 : 1, 70 est : 1, 71 : 1, 72 ssse3 : 1, 73 cid : 1, 74 : 2, 75 cmpxchg16: 1, 76 : 4, 77 dca : 1, 78 sse4_1 : 1, 79 sse4_2 : 1, 80 : 2, 81 popcnt : 1, 82 : 1, 83 aes : 1, 84 : 1, 85 osxsave : 1, 86 avx : 1, 87 : 3; 88 } bits; 89 }; 90 91 union StdCpuid1Edx { 92 uint32_t value; 93 struct { 94 uint32_t : 4, 95 tsc : 1, 96 : 3, 97 cmpxchg8 : 1, 98 : 6, 99 cmov : 1, 100 : 3, 101 clflush : 1, 102 : 3, 103 mmx : 1, 104 fxsr : 1, 105 sse : 1, 106 sse2 : 1, 107 : 1, 108 ht : 1, 109 : 3; 110 } bits; 111 }; 112 113 union DcpCpuid4Eax { 114 uint32_t value; 115 struct { 116 uint32_t cache_type : 5, 117 : 21, 118 cores_per_cpu : 6; 119 } bits; 120 }; 121 122 union DcpCpuid4Ebx { 123 uint32_t value; 124 struct { 125 uint32_t L1_line_size : 12, 126 partitions : 10, 127 associativity : 10; 128 } bits; 129 }; 130 131 union TplCpuidBEbx { 132 uint32_t value; 133 struct { 134 uint32_t logical_cpus : 16, 135 : 16; 136 } bits; 137 }; 138 139 union ExtCpuid1Ecx { 140 uint32_t value; 141 struct { 142 uint32_t LahfSahf : 1, 143 CmpLegacy : 1, 144 : 3, 145 lzcnt_intel : 1, 146 lzcnt : 1, 147 sse4a : 1, 148 misalignsse : 1, 149 prefetchw : 1, 150 : 22; 151 } bits; 152 }; 153 154 union ExtCpuid1Edx { 155 uint32_t value; 156 struct { 157 uint32_t : 22, 158 mmx_amd : 1, 159 mmx : 1, 160 fxsr : 1, 161 : 4, 162 long_mode : 1, 163 tdnow2 : 1, 164 tdnow : 1; 165 } bits; 166 }; 167 168 union ExtCpuid5Ex { 169 uint32_t value; 170 struct { 171 uint32_t L1_line_size : 8, 172 L1_tag_lines : 8, 173 L1_assoc : 8, 174 L1_size : 8; 175 } bits; 176 }; 177 178 union ExtCpuid7Edx { 179 uint32_t value; 180 struct { 181 uint32_t : 8, 182 tsc_invariance : 1, 183 : 23; 184 } bits; 185 }; 186 187 union ExtCpuid8Ecx { 188 uint32_t value; 189 struct { 190 uint32_t cores_per_cpu : 8, 191 : 24; 192 } bits; 193 }; 194 195 union SefCpuid7Eax { 196 uint32_t value; 197 }; 198 199 union SefCpuid7Ebx { 200 uint32_t value; 201 struct { 202 uint32_t fsgsbase : 1, 203 : 2, 204 bmi1 : 1, 205 : 1, 206 avx2 : 1, 207 : 2, 208 bmi2 : 1, 209 erms : 1, 210 : 1, 211 rtm : 1, 212 : 4, 213 avx512f : 1, 214 avx512dq : 1, 215 : 1, 216 adx : 1, 217 : 6, 218 avx512pf : 1, 219 avx512er : 1, 220 avx512cd : 1, 221 : 1, 222 avx512bw : 1, 223 avx512vl : 1; 224 } bits; 225 }; 226 227 union XemXcr0Eax { 228 uint32_t value; 229 struct { 230 uint32_t x87 : 1, 231 sse : 1, 232 ymm : 1, 233 bndregs : 1, 234 bndcsr : 1, 235 opmask : 1, 236 zmm512 : 1, 237 zmm32 : 1, 238 : 24; 239 } bits; 240 }; 241 242 protected: 243 static int _cpu; 244 static int _model; 245 static int _stepping; 246 static uint64_t _cpuFeatures; // features returned by the "cpuid" instruction 247 // 0 if this instruction is not available 248 static const char* _features_str; 249 250 static address _cpuinfo_segv_addr; // address of instruction which causes SEGV 251 static address _cpuinfo_cont_addr; // address of instruction after the one which causes SEGV 252 253 enum { 254 CPU_CX8 = (1 << 0), // next bits are from cpuid 1 (EDX) 255 CPU_CMOV = (1 << 1), 256 CPU_FXSR = (1 << 2), 257 CPU_HT = (1 << 3), 258 CPU_MMX = (1 << 4), 259 CPU_3DNOW_PREFETCH = (1 << 5), // Processor supports 3dnow prefetch and prefetchw instructions 260 // may not necessarily support other 3dnow instructions 261 CPU_SSE = (1 << 6), 262 CPU_SSE2 = (1 << 7), 263 CPU_SSE3 = (1 << 8), // SSE3 comes from cpuid 1 (ECX) 264 CPU_SSSE3 = (1 << 9), 265 CPU_SSE4A = (1 << 10), 266 CPU_SSE4_1 = (1 << 11), 267 CPU_SSE4_2 = (1 << 12), 268 CPU_POPCNT = (1 << 13), 269 CPU_LZCNT = (1 << 14), 270 CPU_TSC = (1 << 15), 271 CPU_TSCINV = (1 << 16), 272 CPU_AVX = (1 << 17), 273 CPU_AVX2 = (1 << 18), 274 CPU_AES = (1 << 19), 275 CPU_ERMS = (1 << 20), // enhanced 'rep movsb/stosb' instructions 276 CPU_CLMUL = (1 << 21), // carryless multiply for CRC 277 CPU_BMI1 = (1 << 22), 278 CPU_BMI2 = (1 << 23), 279 CPU_RTM = (1 << 24), // Restricted Transactional Memory instructions 280 CPU_ADX = (1 << 25), 281 CPU_AVX512F = (1 << 26), // AVX 512bit foundation instructions 282 CPU_AVX512DQ = (1 << 27), 283 CPU_AVX512PF = (1 << 28), 284 CPU_AVX512ER = (1 << 29), 285 CPU_AVX512CD = (1 << 30), 286 CPU_AVX512BW = (1 << 31) 287 } cpuFeatureFlags; 288 289 #define CPU_AVX512VL UCONST64(0x100000000) // EVEX instructions with smaller vector length : enums are limited to 32bit 290 291 enum { 292 // AMD 293 CPU_FAMILY_AMD_11H = 0x11, 294 // Intel 295 CPU_FAMILY_INTEL_CORE = 6, 296 CPU_MODEL_NEHALEM = 0x1e, 297 CPU_MODEL_NEHALEM_EP = 0x1a, 298 CPU_MODEL_NEHALEM_EX = 0x2e, 299 CPU_MODEL_WESTMERE = 0x25, 300 CPU_MODEL_WESTMERE_EP = 0x2c, 301 CPU_MODEL_WESTMERE_EX = 0x2f, 302 CPU_MODEL_SANDYBRIDGE = 0x2a, 303 CPU_MODEL_SANDYBRIDGE_EP = 0x2d, 304 CPU_MODEL_IVYBRIDGE_EP = 0x3a, 305 CPU_MODEL_HASWELL_E3 = 0x3c, 306 CPU_MODEL_HASWELL_E7 = 0x3f, 307 CPU_MODEL_BROADWELL = 0x3d, 308 CPU_MODEL_SKYLAKE = CPU_MODEL_HASWELL_E3 309 } cpuExtendedFamily; 310 311 // cpuid information block. All info derived from executing cpuid with 312 // various function numbers is stored here. Intel and AMD info is 313 // merged in this block: accessor methods disentangle it. 314 // 315 // The info block is laid out in subblocks of 4 dwords corresponding to 316 // eax, ebx, ecx and edx, whether or not they contain anything useful. 317 struct CpuidInfo { 318 // cpuid function 0 319 uint32_t std_max_function; 320 uint32_t std_vendor_name_0; 321 uint32_t std_vendor_name_1; 322 uint32_t std_vendor_name_2; 323 324 // cpuid function 1 325 StdCpuid1Eax std_cpuid1_eax; 326 StdCpuid1Ebx std_cpuid1_ebx; 327 StdCpuid1Ecx std_cpuid1_ecx; 328 StdCpuid1Edx std_cpuid1_edx; 329 330 // cpuid function 4 (deterministic cache parameters) 331 DcpCpuid4Eax dcp_cpuid4_eax; 332 DcpCpuid4Ebx dcp_cpuid4_ebx; 333 uint32_t dcp_cpuid4_ecx; // unused currently 334 uint32_t dcp_cpuid4_edx; // unused currently 335 336 // cpuid function 7 (structured extended features) 337 SefCpuid7Eax sef_cpuid7_eax; 338 SefCpuid7Ebx sef_cpuid7_ebx; 339 uint32_t sef_cpuid7_ecx; // unused currently 340 uint32_t sef_cpuid7_edx; // unused currently 341 342 // cpuid function 0xB (processor topology) 343 // ecx = 0 344 uint32_t tpl_cpuidB0_eax; 345 TplCpuidBEbx tpl_cpuidB0_ebx; 346 uint32_t tpl_cpuidB0_ecx; // unused currently 347 uint32_t tpl_cpuidB0_edx; // unused currently 348 349 // ecx = 1 350 uint32_t tpl_cpuidB1_eax; 351 TplCpuidBEbx tpl_cpuidB1_ebx; 352 uint32_t tpl_cpuidB1_ecx; // unused currently 353 uint32_t tpl_cpuidB1_edx; // unused currently 354 355 // ecx = 2 356 uint32_t tpl_cpuidB2_eax; 357 TplCpuidBEbx tpl_cpuidB2_ebx; 358 uint32_t tpl_cpuidB2_ecx; // unused currently 359 uint32_t tpl_cpuidB2_edx; // unused currently 360 361 // cpuid function 0x80000000 // example, unused 362 uint32_t ext_max_function; 363 uint32_t ext_vendor_name_0; 364 uint32_t ext_vendor_name_1; 365 uint32_t ext_vendor_name_2; 366 367 // cpuid function 0x80000001 368 uint32_t ext_cpuid1_eax; // reserved 369 uint32_t ext_cpuid1_ebx; // reserved 370 ExtCpuid1Ecx ext_cpuid1_ecx; 371 ExtCpuid1Edx ext_cpuid1_edx; 372 373 // cpuid functions 0x80000002 thru 0x80000004: example, unused 374 uint32_t proc_name_0, proc_name_1, proc_name_2, proc_name_3; 375 uint32_t proc_name_4, proc_name_5, proc_name_6, proc_name_7; 376 uint32_t proc_name_8, proc_name_9, proc_name_10,proc_name_11; 377 378 // cpuid function 0x80000005 // AMD L1, Intel reserved 379 uint32_t ext_cpuid5_eax; // unused currently 380 uint32_t ext_cpuid5_ebx; // reserved 381 ExtCpuid5Ex ext_cpuid5_ecx; // L1 data cache info (AMD) 382 ExtCpuid5Ex ext_cpuid5_edx; // L1 instruction cache info (AMD) 383 384 // cpuid function 0x80000007 385 uint32_t ext_cpuid7_eax; // reserved 386 uint32_t ext_cpuid7_ebx; // reserved 387 uint32_t ext_cpuid7_ecx; // reserved 388 ExtCpuid7Edx ext_cpuid7_edx; // tscinv 389 390 // cpuid function 0x80000008 391 uint32_t ext_cpuid8_eax; // unused currently 392 uint32_t ext_cpuid8_ebx; // reserved 393 ExtCpuid8Ecx ext_cpuid8_ecx; 394 uint32_t ext_cpuid8_edx; // reserved 395 396 // extended control register XCR0 (the XFEATURE_ENABLED_MASK register) 397 XemXcr0Eax xem_xcr0_eax; 398 uint32_t xem_xcr0_edx; // reserved 399 400 // Space to save ymm registers after signal handle 401 int ymm_save[8*4]; // Save ymm0, ymm7, ymm8, ymm15 402 403 // Space to save zmm registers after signal handle 404 int zmm_save[16*4]; // Save zmm0, zmm7, zmm8, zmm31 405 }; 406 407 // The actual cpuid info block 408 static CpuidInfo _cpuid_info; 409 410 // Extractors and predicates 411 static uint32_t extended_cpu_family() { 412 uint32_t result = _cpuid_info.std_cpuid1_eax.bits.family; 413 result += _cpuid_info.std_cpuid1_eax.bits.ext_family; 414 return result; 415 } 416 417 static uint32_t extended_cpu_model() { 418 uint32_t result = _cpuid_info.std_cpuid1_eax.bits.model; 419 result |= _cpuid_info.std_cpuid1_eax.bits.ext_model << 4; 420 return result; 421 } 422 423 static uint32_t cpu_stepping() { 424 uint32_t result = _cpuid_info.std_cpuid1_eax.bits.stepping; 425 return result; 426 } 427 428 static uint logical_processor_count() { 429 uint result = threads_per_core(); 430 return result; 431 } 432 433 static uint64_t feature_flags() { 434 uint64_t result = 0; 435 if (_cpuid_info.std_cpuid1_edx.bits.cmpxchg8 != 0) 436 result |= CPU_CX8; 437 if (_cpuid_info.std_cpuid1_edx.bits.cmov != 0) 438 result |= CPU_CMOV; 439 if (_cpuid_info.std_cpuid1_edx.bits.fxsr != 0 || (is_amd() && 440 _cpuid_info.ext_cpuid1_edx.bits.fxsr != 0)) 441 result |= CPU_FXSR; 442 // HT flag is set for multi-core processors also. 443 if (threads_per_core() > 1) 444 result |= CPU_HT; 445 if (_cpuid_info.std_cpuid1_edx.bits.mmx != 0 || (is_amd() && 446 _cpuid_info.ext_cpuid1_edx.bits.mmx != 0)) 447 result |= CPU_MMX; 448 if (_cpuid_info.std_cpuid1_edx.bits.sse != 0) 449 result |= CPU_SSE; 450 if (_cpuid_info.std_cpuid1_edx.bits.sse2 != 0) 451 result |= CPU_SSE2; 452 if (_cpuid_info.std_cpuid1_ecx.bits.sse3 != 0) 453 result |= CPU_SSE3; 454 if (_cpuid_info.std_cpuid1_ecx.bits.ssse3 != 0) 455 result |= CPU_SSSE3; 456 if (_cpuid_info.std_cpuid1_ecx.bits.sse4_1 != 0) 457 result |= CPU_SSE4_1; 458 if (_cpuid_info.std_cpuid1_ecx.bits.sse4_2 != 0) 459 result |= CPU_SSE4_2; 460 if (_cpuid_info.std_cpuid1_ecx.bits.popcnt != 0) 461 result |= CPU_POPCNT; 462 if (_cpuid_info.std_cpuid1_ecx.bits.avx != 0 && 463 _cpuid_info.std_cpuid1_ecx.bits.osxsave != 0 && 464 _cpuid_info.xem_xcr0_eax.bits.sse != 0 && 465 _cpuid_info.xem_xcr0_eax.bits.ymm != 0) { 466 result |= CPU_AVX; 467 if (_cpuid_info.sef_cpuid7_ebx.bits.avx2 != 0) 468 result |= CPU_AVX2; 469 if (_cpuid_info.sef_cpuid7_ebx.bits.avx512f != 0 && 470 _cpuid_info.xem_xcr0_eax.bits.opmask != 0 && 471 _cpuid_info.xem_xcr0_eax.bits.zmm512 != 0 && 472 _cpuid_info.xem_xcr0_eax.bits.zmm32 != 0) { 473 result |= CPU_AVX512F; 474 if (_cpuid_info.sef_cpuid7_ebx.bits.avx512cd != 0) 475 result |= CPU_AVX512CD; 476 if (_cpuid_info.sef_cpuid7_ebx.bits.avx512dq != 0) 477 result |= CPU_AVX512DQ; 478 if (_cpuid_info.sef_cpuid7_ebx.bits.avx512pf != 0) 479 result |= CPU_AVX512PF; 480 if (_cpuid_info.sef_cpuid7_ebx.bits.avx512er != 0) 481 result |= CPU_AVX512ER; 482 if (_cpuid_info.sef_cpuid7_ebx.bits.avx512bw != 0) 483 result |= CPU_AVX512BW; 484 if (_cpuid_info.sef_cpuid7_ebx.bits.avx512vl != 0) 485 result |= CPU_AVX512VL; 486 } 487 } 488 if(_cpuid_info.sef_cpuid7_ebx.bits.bmi1 != 0) 489 result |= CPU_BMI1; 490 if (_cpuid_info.std_cpuid1_edx.bits.tsc != 0) 491 result |= CPU_TSC; 492 if (_cpuid_info.ext_cpuid7_edx.bits.tsc_invariance != 0) 493 result |= CPU_TSCINV; 494 if (_cpuid_info.std_cpuid1_ecx.bits.aes != 0) 495 result |= CPU_AES; 496 if (_cpuid_info.sef_cpuid7_ebx.bits.erms != 0) 497 result |= CPU_ERMS; 498 if (_cpuid_info.std_cpuid1_ecx.bits.clmul != 0) 499 result |= CPU_CLMUL; 500 if (_cpuid_info.sef_cpuid7_ebx.bits.rtm != 0) 501 result |= CPU_RTM; 502 503 // AMD features. 504 if (is_amd()) { 505 if ((_cpuid_info.ext_cpuid1_edx.bits.tdnow != 0) || 506 (_cpuid_info.ext_cpuid1_ecx.bits.prefetchw != 0)) 507 result |= CPU_3DNOW_PREFETCH; 508 if (_cpuid_info.ext_cpuid1_ecx.bits.lzcnt != 0) 509 result |= CPU_LZCNT; 510 if (_cpuid_info.ext_cpuid1_ecx.bits.sse4a != 0) 511 result |= CPU_SSE4A; 512 } 513 // Intel features. 514 if(is_intel()) { 515 if(_cpuid_info.sef_cpuid7_ebx.bits.adx != 0) 516 result |= CPU_ADX; 517 if(_cpuid_info.sef_cpuid7_ebx.bits.bmi2 != 0) 518 result |= CPU_BMI2; 519 if(_cpuid_info.ext_cpuid1_ecx.bits.lzcnt_intel != 0) 520 result |= CPU_LZCNT; 521 // for Intel, ecx.bits.misalignsse bit (bit 8) indicates support for prefetchw 522 if (_cpuid_info.ext_cpuid1_ecx.bits.misalignsse != 0) { 523 result |= CPU_3DNOW_PREFETCH; 524 } 525 } 526 527 return result; 528 } 529 530 static bool os_supports_avx_vectors() { 531 bool retVal = false; 532 if (supports_evex()) { 533 // Verify that OS save/restore all bits of EVEX registers 534 // during signal processing. 535 int nreg = 2 LP64_ONLY(+2); 536 retVal = true; 537 for (int i = 0; i < 16 * nreg; i++) { // 64 bytes per zmm register 538 if (_cpuid_info.zmm_save[i] != ymm_test_value()) { 539 retVal = false; 540 break; 541 } 542 } 543 } else if (supports_avx()) { 544 // Verify that OS save/restore all bits of AVX registers 545 // during signal processing. 546 int nreg = 2 LP64_ONLY(+2); 547 retVal = true; 548 for (int i = 0; i < 8 * nreg; i++) { // 32 bytes per ymm register 549 if (_cpuid_info.ymm_save[i] != ymm_test_value()) { 550 retVal = false; 551 break; 552 } 553 } 554 } 555 return retVal; 556 } 557 558 static void get_processor_features(); 559 560 public: 561 // Offsets for cpuid asm stub 562 static ByteSize std_cpuid0_offset() { return byte_offset_of(CpuidInfo, std_max_function); } 563 static ByteSize std_cpuid1_offset() { return byte_offset_of(CpuidInfo, std_cpuid1_eax); } 564 static ByteSize dcp_cpuid4_offset() { return byte_offset_of(CpuidInfo, dcp_cpuid4_eax); } 565 static ByteSize sef_cpuid7_offset() { return byte_offset_of(CpuidInfo, sef_cpuid7_eax); } 566 static ByteSize ext_cpuid1_offset() { return byte_offset_of(CpuidInfo, ext_cpuid1_eax); } 567 static ByteSize ext_cpuid5_offset() { return byte_offset_of(CpuidInfo, ext_cpuid5_eax); } 568 static ByteSize ext_cpuid7_offset() { return byte_offset_of(CpuidInfo, ext_cpuid7_eax); } 569 static ByteSize ext_cpuid8_offset() { return byte_offset_of(CpuidInfo, ext_cpuid8_eax); } 570 static ByteSize tpl_cpuidB0_offset() { return byte_offset_of(CpuidInfo, tpl_cpuidB0_eax); } 571 static ByteSize tpl_cpuidB1_offset() { return byte_offset_of(CpuidInfo, tpl_cpuidB1_eax); } 572 static ByteSize tpl_cpuidB2_offset() { return byte_offset_of(CpuidInfo, tpl_cpuidB2_eax); } 573 static ByteSize xem_xcr0_offset() { return byte_offset_of(CpuidInfo, xem_xcr0_eax); } 574 static ByteSize ymm_save_offset() { return byte_offset_of(CpuidInfo, ymm_save); } 575 static ByteSize zmm_save_offset() { return byte_offset_of(CpuidInfo, zmm_save); } 576 577 // The value used to check ymm register after signal handle 578 static int ymm_test_value() { return 0xCAFEBABE; } 579 580 static void get_cpu_info_wrapper(); 581 static void set_cpuinfo_segv_addr(address pc) { _cpuinfo_segv_addr = pc; } 582 static bool is_cpuinfo_segv_addr(address pc) { return _cpuinfo_segv_addr == pc; } 583 static void set_cpuinfo_cont_addr(address pc) { _cpuinfo_cont_addr = pc; } 584 static address cpuinfo_cont_addr() { return _cpuinfo_cont_addr; } 585 586 static void clean_cpuFeatures() { _cpuFeatures = 0; } 587 static void set_avx_cpuFeatures() { _cpuFeatures = (CPU_SSE | CPU_SSE2 | CPU_AVX); } 588 static void set_evex_cpuFeatures() { _cpuFeatures = (CPU_AVX512F | CPU_SSE | CPU_SSE2 ); } 589 590 591 // Initialization 592 static void initialize(); 593 594 // Override Abstract_VM_Version implementation 595 static bool use_biased_locking(); 596 597 // Asserts 598 static void assert_is_initialized() { 599 assert(_cpuid_info.std_cpuid1_eax.bits.family != 0, "VM_Version not initialized"); 600 } 601 602 // 603 // Processor family: 604 // 3 - 386 605 // 4 - 486 606 // 5 - Pentium 607 // 6 - PentiumPro, Pentium II, Celeron, Xeon, Pentium III, Athlon, 608 // Pentium M, Core Solo, Core Duo, Core2 Duo 609 // family 6 model: 9, 13, 14, 15 610 // 0x0f - Pentium 4, Opteron 611 // 612 // Note: The cpu family should be used to select between 613 // instruction sequences which are valid on all Intel 614 // processors. Use the feature test functions below to 615 // determine whether a particular instruction is supported. 616 // 617 static int cpu_family() { return _cpu;} 618 static bool is_P6() { return cpu_family() >= 6; } 619 static bool is_amd() { assert_is_initialized(); return _cpuid_info.std_vendor_name_0 == 0x68747541; } // 'htuA' 620 static bool is_intel() { assert_is_initialized(); return _cpuid_info.std_vendor_name_0 == 0x756e6547; } // 'uneG' 621 622 static bool supports_processor_topology() { 623 return (_cpuid_info.std_max_function >= 0xB) && 624 // eax[4:0] | ebx[0:15] == 0 indicates invalid topology level. 625 // Some cpus have max cpuid >= 0xB but do not support processor topology. 626 (((_cpuid_info.tpl_cpuidB0_eax & 0x1f) | _cpuid_info.tpl_cpuidB0_ebx.bits.logical_cpus) != 0); 627 } 628 629 static uint cores_per_cpu() { 630 uint result = 1; 631 if (is_intel()) { 632 bool supports_topology = supports_processor_topology(); 633 if (supports_topology) { 634 result = _cpuid_info.tpl_cpuidB1_ebx.bits.logical_cpus / 635 _cpuid_info.tpl_cpuidB0_ebx.bits.logical_cpus; 636 } 637 if (!supports_topology || result == 0) { 638 result = (_cpuid_info.dcp_cpuid4_eax.bits.cores_per_cpu + 1); 639 } 640 } else if (is_amd()) { 641 result = (_cpuid_info.ext_cpuid8_ecx.bits.cores_per_cpu + 1); 642 } 643 return result; 644 } 645 646 static uint threads_per_core() { 647 uint result = 1; 648 if (is_intel() && supports_processor_topology()) { 649 result = _cpuid_info.tpl_cpuidB0_ebx.bits.logical_cpus; 650 } else if (_cpuid_info.std_cpuid1_edx.bits.ht != 0) { 651 result = _cpuid_info.std_cpuid1_ebx.bits.threads_per_cpu / 652 cores_per_cpu(); 653 } 654 return result; 655 } 656 657 static intx L1_line_size() { 658 intx result = 0; 659 if (is_intel()) { 660 result = (_cpuid_info.dcp_cpuid4_ebx.bits.L1_line_size + 1); 661 } else if (is_amd()) { 662 result = _cpuid_info.ext_cpuid5_ecx.bits.L1_line_size; 663 } 664 if (result < 32) // not defined ? 665 result = 32; // 32 bytes by default on x86 and other x64 666 return result; 667 } 668 669 static intx prefetch_data_size() { 670 return L1_line_size(); 671 } 672 673 // 674 // Feature identification 675 // 676 static bool supports_cpuid() { return _cpuFeatures != 0; } 677 static bool supports_cmpxchg8() { return (_cpuFeatures & CPU_CX8) != 0; } 678 static bool supports_cmov() { return (_cpuFeatures & CPU_CMOV) != 0; } 679 static bool supports_fxsr() { return (_cpuFeatures & CPU_FXSR) != 0; } 680 static bool supports_ht() { return (_cpuFeatures & CPU_HT) != 0; } 681 static bool supports_mmx() { return (_cpuFeatures & CPU_MMX) != 0; } 682 static bool supports_sse() { return (_cpuFeatures & CPU_SSE) != 0; } 683 static bool supports_sse2() { return (_cpuFeatures & CPU_SSE2) != 0; } 684 static bool supports_sse3() { return (_cpuFeatures & CPU_SSE3) != 0; } 685 static bool supports_ssse3() { return (_cpuFeatures & CPU_SSSE3)!= 0; } 686 static bool supports_sse4_1() { return (_cpuFeatures & CPU_SSE4_1) != 0; } 687 static bool supports_sse4_2() { return (_cpuFeatures & CPU_SSE4_2) != 0; } 688 static bool supports_popcnt() { return (_cpuFeatures & CPU_POPCNT) != 0; } 689 static bool supports_avx() { return (_cpuFeatures & CPU_AVX) != 0; } 690 static bool supports_avx2() { return (_cpuFeatures & CPU_AVX2) != 0; } 691 static bool supports_tsc() { return (_cpuFeatures & CPU_TSC) != 0; } 692 static bool supports_aes() { return (_cpuFeatures & CPU_AES) != 0; } 693 static bool supports_erms() { return (_cpuFeatures & CPU_ERMS) != 0; } 694 static bool supports_clmul() { return (_cpuFeatures & CPU_CLMUL) != 0; } 695 static bool supports_rtm() { return (_cpuFeatures & CPU_RTM) != 0; } 696 static bool supports_bmi1() { return (_cpuFeatures & CPU_BMI1) != 0; } 697 static bool supports_bmi2() { return (_cpuFeatures & CPU_BMI2) != 0; } 698 static bool supports_adx() { return (_cpuFeatures & CPU_ADX) != 0; } 699 static bool supports_evex() { return (_cpuFeatures & CPU_AVX512F) != 0; } 700 static bool supports_avx512dq() { return (_cpuFeatures & CPU_AVX512DQ) != 0; } 701 static bool supports_avx512pf() { return (_cpuFeatures & CPU_AVX512PF) != 0; } 702 static bool supports_avx512er() { return (_cpuFeatures & CPU_AVX512ER) != 0; } 703 static bool supports_avx512cd() { return (_cpuFeatures & CPU_AVX512CD) != 0; } 704 static bool supports_avx512bw() { return (_cpuFeatures & CPU_AVX512BW) != 0; } 705 static bool supports_avx512vl() { return (_cpuFeatures & CPU_AVX512VL) != 0; } 706 static bool supports_avx512vlbw() { return (supports_avx512bw() && supports_avx512vl()); } 707 static bool supports_avx512novl() { return (supports_evex() && !supports_avx512vl()); } 708 // Intel features 709 static bool is_intel_family_core() { return is_intel() && 710 extended_cpu_family() == CPU_FAMILY_INTEL_CORE; } 711 712 static bool is_intel_tsc_synched_at_init() { 713 if (is_intel_family_core()) { 714 uint32_t ext_model = extended_cpu_model(); 715 if (ext_model == CPU_MODEL_NEHALEM_EP || 716 ext_model == CPU_MODEL_WESTMERE_EP || 717 ext_model == CPU_MODEL_SANDYBRIDGE_EP || 718 ext_model == CPU_MODEL_IVYBRIDGE_EP) { 719 // <= 2-socket invariant tsc support. EX versions are usually used 720 // in > 2-socket systems and likely don't synchronize tscs at 721 // initialization. 722 // Code that uses tsc values must be prepared for them to arbitrarily 723 // jump forward or backward. 724 return true; 725 } 726 } 727 return false; 728 } 729 730 // AMD features 731 static bool supports_3dnow_prefetch() { return (_cpuFeatures & CPU_3DNOW_PREFETCH) != 0; } 732 static bool supports_mmx_ext() { return is_amd() && _cpuid_info.ext_cpuid1_edx.bits.mmx_amd != 0; } 733 static bool supports_lzcnt() { return (_cpuFeatures & CPU_LZCNT) != 0; } 734 static bool supports_sse4a() { return (_cpuFeatures & CPU_SSE4A) != 0; } 735 736 static bool is_amd_Barcelona() { return is_amd() && 737 extended_cpu_family() == CPU_FAMILY_AMD_11H; } 738 739 // Intel and AMD newer cores support fast timestamps well 740 static bool supports_tscinv_bit() { 741 return (_cpuFeatures & CPU_TSCINV) != 0; 742 } 743 static bool supports_tscinv() { 744 return supports_tscinv_bit() && 745 ( (is_amd() && !is_amd_Barcelona()) || 746 is_intel_tsc_synched_at_init() ); 747 } 748 749 // Intel Core and newer cpus have fast IDIV instruction (excluding Atom). 750 static bool has_fast_idiv() { return is_intel() && cpu_family() == 6 && 751 supports_sse3() && _model != 0x1C; } 752 753 static bool supports_compare_and_exchange() { return true; } 754 755 static const char* cpu_features() { return _features_str; } 756 757 static intx allocate_prefetch_distance() { 758 // This method should be called before allocate_prefetch_style(). 759 // 760 // Hardware prefetching (distance/size in bytes): 761 // Pentium 3 - 64 / 32 762 // Pentium 4 - 256 / 128 763 // Athlon - 64 / 32 ???? 764 // Opteron - 128 / 64 only when 2 sequential cache lines accessed 765 // Core - 128 / 64 766 // 767 // Software prefetching (distance in bytes / instruction with best score): 768 // Pentium 3 - 128 / prefetchnta 769 // Pentium 4 - 512 / prefetchnta 770 // Athlon - 128 / prefetchnta 771 // Opteron - 256 / prefetchnta 772 // Core - 256 / prefetchnta 773 // It will be used only when AllocatePrefetchStyle > 0 774 775 intx count = AllocatePrefetchDistance; 776 if (count < 0) { // default ? 777 if (is_amd()) { // AMD 778 if (supports_sse2()) 779 count = 256; // Opteron 780 else 781 count = 128; // Athlon 782 } else { // Intel 783 if (supports_sse2()) 784 if (cpu_family() == 6) { 785 count = 256; // Pentium M, Core, Core2 786 } else { 787 count = 512; // Pentium 4 788 } 789 else 790 count = 128; // Pentium 3 (and all other old CPUs) 791 } 792 } 793 return count; 794 } 795 static intx allocate_prefetch_style() { 796 assert(AllocatePrefetchStyle >= 0, "AllocatePrefetchStyle should be positive"); 797 // Return 0 if AllocatePrefetchDistance was not defined. 798 return AllocatePrefetchDistance > 0 ? AllocatePrefetchStyle : 0; 799 } 800 801 // Prefetch interval for gc copy/scan == 9 dcache lines. Derived from 802 // 50-warehouse specjbb runs on a 2-way 1.8ghz opteron using a 4gb heap. 803 // Tested intervals from 128 to 2048 in increments of 64 == one cache line. 804 // 256 bytes (4 dcache lines) was the nearest runner-up to 576. 805 806 // gc copy/scan is disabled if prefetchw isn't supported, because 807 // Prefetch::write emits an inlined prefetchw on Linux. 808 // Do not use the 3dnow prefetchw instruction. It isn't supported on em64t. 809 // The used prefetcht0 instruction works for both amd64 and em64t. 810 static intx prefetch_copy_interval_in_bytes() { 811 intx interval = PrefetchCopyIntervalInBytes; 812 return interval >= 0 ? interval : 576; 813 } 814 static intx prefetch_scan_interval_in_bytes() { 815 intx interval = PrefetchScanIntervalInBytes; 816 return interval >= 0 ? interval : 576; 817 } 818 static intx prefetch_fields_ahead() { 819 intx count = PrefetchFieldsAhead; 820 return count >= 0 ? count : 1; 821 } 822 static uint32_t get_xsave_header_lower_segment() { 823 return _cpuid_info.xem_xcr0_eax.value; 824 } 825 static uint32_t get_xsave_header_upper_segment() { 826 return _cpuid_info.xem_xcr0_edx; 827 } 828 }; 829 830 #endif // CPU_X86_VM_VM_VERSION_X86_HPP