src/cpu/x86/vm/nativeInst_x86.cpp

@@ -39,11 +39,10 @@
 
 void NativeInstruction::wrote(int offset) {
   ICache::invalidate_word(addr_at(offset));
 }
 
-
 void NativeCall::verify() {
   // Make sure code pattern is actually a call imm32 instruction.
   int inst = ubyte_at(0);
   if (inst != instruction_code) {
     tty->print_cr("Addr: " INTPTR_FORMAT " Code: 0x%x", instruction_address(),

@@ -472,10 +471,11 @@
 // entry point is in same cache line as unverified entry point, and the instruction being
 // patched is >= 5 byte (size of patch).
 //
 // In C2 the 5+ byte sized instruction is enforced by code in MachPrologNode::emit.
 // In C1 the restriction is enforced by CodeEmitter::method_entry
+// In JVMCI, the restriction is enforced by HotSpotFrameContext.enter(...)
 //
 void NativeJump::patch_verified_entry(address entry, address verified_entry, address dest) {
   // complete jump instruction (to be inserted) is in code_buffer;
   unsigned char code_buffer[5];
   code_buffer[0] = instruction_code;