rev 58404 : 8241042: x86_64: Improve Assembler generation
Reviewed-by: vlivanov

   1 /*
   2  * Copyright (c) 1997, 2019, Oracle and/or its affiliates. All rights reserved.
   3  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
   4  *
   5  * This code is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License version 2 only, as
   7  * published by the Free Software Foundation.
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   9  * This code is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  12  * version 2 for more details (a copy is included in the LICENSE file that
  13  * accompanied this code).
  14  *
  15  * You should have received a copy of the GNU General Public License version
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  17  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
  18  *
  19  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
  20  * or visit www.oracle.com if you need additional information or have any
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  24 
  25 #ifndef CPU_X86_ASSEMBLER_X86_HPP
  26 #define CPU_X86_ASSEMBLER_X86_HPP
  27 
  28 #include "asm/register.hpp"
  29 #include "runtime/vm_version.hpp"
  30 #include "utilities/powerOfTwo.hpp"
  31 
  32 class BiasedLockingCounters;
  33 
  34 // Contains all the definitions needed for x86 assembly code generation.
  35 
  36 // Calling convention
  37 class Argument {
  38  public:
  39   enum {
  40 #ifdef _LP64
  41 #ifdef _WIN64
  42     n_int_register_parameters_c   = 4, // rcx, rdx, r8, r9 (c_rarg0, c_rarg1, ...)
  43     n_float_register_parameters_c = 4,  // xmm0 - xmm3 (c_farg0, c_farg1, ... )
  44 #else
  45     n_int_register_parameters_c   = 6, // rdi, rsi, rdx, rcx, r8, r9 (c_rarg0, c_rarg1, ...)
  46     n_float_register_parameters_c = 8,  // xmm0 - xmm7 (c_farg0, c_farg1, ... )
  47 #endif // _WIN64
  48     n_int_register_parameters_j   = 6, // j_rarg0, j_rarg1, ...
  49     n_float_register_parameters_j = 8  // j_farg0, j_farg1, ...
  50 #else
  51     n_register_parameters = 0   // 0 registers used to pass arguments
  52 #endif // _LP64
  53   };
  54 };
  55 
  56 
  57 #ifdef _LP64
  58 // Symbolically name the register arguments used by the c calling convention.
  59 // Windows is different from linux/solaris. So much for standards...
  60 
  61 #ifdef _WIN64
  62 
  63 REGISTER_DECLARATION(Register, c_rarg0, rcx);
  64 REGISTER_DECLARATION(Register, c_rarg1, rdx);
  65 REGISTER_DECLARATION(Register, c_rarg2, r8);
  66 REGISTER_DECLARATION(Register, c_rarg3, r9);
  67 
  68 REGISTER_DECLARATION(XMMRegister, c_farg0, xmm0);
  69 REGISTER_DECLARATION(XMMRegister, c_farg1, xmm1);
  70 REGISTER_DECLARATION(XMMRegister, c_farg2, xmm2);
  71 REGISTER_DECLARATION(XMMRegister, c_farg3, xmm3);
  72 
  73 #else
  74 
  75 REGISTER_DECLARATION(Register, c_rarg0, rdi);
  76 REGISTER_DECLARATION(Register, c_rarg1, rsi);
  77 REGISTER_DECLARATION(Register, c_rarg2, rdx);
  78 REGISTER_DECLARATION(Register, c_rarg3, rcx);
  79 REGISTER_DECLARATION(Register, c_rarg4, r8);
  80 REGISTER_DECLARATION(Register, c_rarg5, r9);
  81 
  82 REGISTER_DECLARATION(XMMRegister, c_farg0, xmm0);
  83 REGISTER_DECLARATION(XMMRegister, c_farg1, xmm1);
  84 REGISTER_DECLARATION(XMMRegister, c_farg2, xmm2);
  85 REGISTER_DECLARATION(XMMRegister, c_farg3, xmm3);
  86 REGISTER_DECLARATION(XMMRegister, c_farg4, xmm4);
  87 REGISTER_DECLARATION(XMMRegister, c_farg5, xmm5);
  88 REGISTER_DECLARATION(XMMRegister, c_farg6, xmm6);
  89 REGISTER_DECLARATION(XMMRegister, c_farg7, xmm7);
  90 
  91 #endif // _WIN64
  92 
  93 // Symbolically name the register arguments used by the Java calling convention.
  94 // We have control over the convention for java so we can do what we please.
  95 // What pleases us is to offset the java calling convention so that when
  96 // we call a suitable jni method the arguments are lined up and we don't
  97 // have to do little shuffling. A suitable jni method is non-static and a
  98 // small number of arguments (two fewer args on windows)
  99 //
 100 //        |-------------------------------------------------------|
 101 //        | c_rarg0   c_rarg1  c_rarg2 c_rarg3 c_rarg4 c_rarg5    |
 102 //        |-------------------------------------------------------|
 103 //        | rcx       rdx      r8      r9      rdi*    rsi*       | windows (* not a c_rarg)
 104 //        | rdi       rsi      rdx     rcx     r8      r9         | solaris/linux
 105 //        |-------------------------------------------------------|
 106 //        | j_rarg5   j_rarg0  j_rarg1 j_rarg2 j_rarg3 j_rarg4    |
 107 //        |-------------------------------------------------------|
 108 
 109 REGISTER_DECLARATION(Register, j_rarg0, c_rarg1);
 110 REGISTER_DECLARATION(Register, j_rarg1, c_rarg2);
 111 REGISTER_DECLARATION(Register, j_rarg2, c_rarg3);
 112 // Windows runs out of register args here
 113 #ifdef _WIN64
 114 REGISTER_DECLARATION(Register, j_rarg3, rdi);
 115 REGISTER_DECLARATION(Register, j_rarg4, rsi);
 116 #else
 117 REGISTER_DECLARATION(Register, j_rarg3, c_rarg4);
 118 REGISTER_DECLARATION(Register, j_rarg4, c_rarg5);
 119 #endif /* _WIN64 */
 120 REGISTER_DECLARATION(Register, j_rarg5, c_rarg0);
 121 
 122 REGISTER_DECLARATION(XMMRegister, j_farg0, xmm0);
 123 REGISTER_DECLARATION(XMMRegister, j_farg1, xmm1);
 124 REGISTER_DECLARATION(XMMRegister, j_farg2, xmm2);
 125 REGISTER_DECLARATION(XMMRegister, j_farg3, xmm3);
 126 REGISTER_DECLARATION(XMMRegister, j_farg4, xmm4);
 127 REGISTER_DECLARATION(XMMRegister, j_farg5, xmm5);
 128 REGISTER_DECLARATION(XMMRegister, j_farg6, xmm6);
 129 REGISTER_DECLARATION(XMMRegister, j_farg7, xmm7);
 130 
 131 REGISTER_DECLARATION(Register, rscratch1, r10);  // volatile
 132 REGISTER_DECLARATION(Register, rscratch2, r11);  // volatile
 133 
 134 REGISTER_DECLARATION(Register, r12_heapbase, r12); // callee-saved
 135 REGISTER_DECLARATION(Register, r15_thread, r15); // callee-saved
 136 
 137 #else
 138 // rscratch1 will apear in 32bit code that is dead but of course must compile
 139 // Using noreg ensures if the dead code is incorrectly live and executed it
 140 // will cause an assertion failure
 141 #define rscratch1 noreg
 142 #define rscratch2 noreg
 143 
 144 #endif // _LP64
 145 
 146 // JSR 292
 147 // On x86, the SP does not have to be saved when invoking method handle intrinsics
 148 // or compiled lambda forms. We indicate that by setting rbp_mh_SP_save to noreg.
 149 REGISTER_DECLARATION(Register, rbp_mh_SP_save, noreg);
 150 
 151 // Address is an abstraction used to represent a memory location
 152 // using any of the amd64 addressing modes with one object.
 153 //
 154 // Note: A register location is represented via a Register, not
 155 //       via an address for efficiency & simplicity reasons.
 156 
 157 class ArrayAddress;
 158 
 159 class Address {
 160  public:
 161   enum ScaleFactor {
 162     no_scale = -1,
 163     times_1  =  0,
 164     times_2  =  1,
 165     times_4  =  2,
 166     times_8  =  3,
 167     times_ptr = LP64_ONLY(times_8) NOT_LP64(times_4)
 168   };
 169   static ScaleFactor times(int size) {
 170     assert(size >= 1 && size <= 8 && is_power_of_2(size), "bad scale size");
 171     if (size == 8)  return times_8;
 172     if (size == 4)  return times_4;
 173     if (size == 2)  return times_2;
 174     return times_1;
 175   }
 176   static int scale_size(ScaleFactor scale) {
 177     assert(scale != no_scale, "");
 178     assert(((1 << (int)times_1) == 1 &&
 179             (1 << (int)times_2) == 2 &&
 180             (1 << (int)times_4) == 4 &&
 181             (1 << (int)times_8) == 8), "");
 182     return (1 << (int)scale);
 183   }
 184 
 185  private:
 186   Register         _base;
 187   Register         _index;
 188   XMMRegister      _xmmindex;
 189   ScaleFactor      _scale;
 190   int              _disp;
 191   bool             _isxmmindex;
 192   RelocationHolder _rspec;
 193 
 194   // Easily misused constructors make them private
 195   // %%% can we make these go away?
 196   NOT_LP64(Address(address loc, RelocationHolder spec);)
 197   Address(int disp, address loc, relocInfo::relocType rtype);
 198   Address(int disp, address loc, RelocationHolder spec);
 199 
 200  public:
 201 
 202  int disp() { return _disp; }
 203   // creation
 204   Address()
 205     : _base(noreg),
 206       _index(noreg),
 207       _xmmindex(xnoreg),
 208       _scale(no_scale),
 209       _disp(0),
 210       _isxmmindex(false){
 211   }
 212 
 213   // No default displacement otherwise Register can be implicitly
 214   // converted to 0(Register) which is quite a different animal.
 215 
 216   Address(Register base, int disp)
 217     : _base(base),
 218       _index(noreg),
 219       _xmmindex(xnoreg),
 220       _scale(no_scale),
 221       _disp(disp),
 222       _isxmmindex(false){
 223   }
 224 
 225   Address(Register base, Register index, ScaleFactor scale, int disp = 0)
 226     : _base (base),
 227       _index(index),
 228       _xmmindex(xnoreg),
 229       _scale(scale),
 230       _disp (disp),
 231       _isxmmindex(false) {
 232     assert(!index->is_valid() == (scale == Address::no_scale),
 233            "inconsistent address");
 234   }
 235 
 236   Address(Register base, RegisterOrConstant index, ScaleFactor scale = times_1, int disp = 0)
 237     : _base (base),
 238       _index(index.register_or_noreg()),
 239       _xmmindex(xnoreg),
 240       _scale(scale),
 241       _disp (disp + (index.constant_or_zero() * scale_size(scale))),
 242       _isxmmindex(false){
 243     if (!index.is_register())  scale = Address::no_scale;
 244     assert(!_index->is_valid() == (scale == Address::no_scale),
 245            "inconsistent address");
 246   }
 247 
 248   Address(Register base, XMMRegister index, ScaleFactor scale, int disp = 0)
 249     : _base (base),
 250       _index(noreg),
 251       _xmmindex(index),
 252       _scale(scale),
 253       _disp(disp),
 254       _isxmmindex(true) {
 255       assert(!index->is_valid() == (scale == Address::no_scale),
 256              "inconsistent address");
 257   }
 258 
 259   Address plus_disp(int disp) const {
 260     Address a = (*this);
 261     a._disp += disp;
 262     return a;
 263   }
 264   Address plus_disp(RegisterOrConstant disp, ScaleFactor scale = times_1) const {
 265     Address a = (*this);
 266     a._disp += disp.constant_or_zero() * scale_size(scale);
 267     if (disp.is_register()) {
 268       assert(!a.index()->is_valid(), "competing indexes");
 269       a._index = disp.as_register();
 270       a._scale = scale;
 271     }
 272     return a;
 273   }
 274   bool is_same_address(Address a) const {
 275     // disregard _rspec
 276     return _base == a._base && _disp == a._disp && _index == a._index && _scale == a._scale;
 277   }
 278 
 279   // The following two overloads are used in connection with the
 280   // ByteSize type (see sizes.hpp).  They simplify the use of
 281   // ByteSize'd arguments in assembly code. Note that their equivalent
 282   // for the optimized build are the member functions with int disp
 283   // argument since ByteSize is mapped to an int type in that case.
 284   //
 285   // Note: DO NOT introduce similar overloaded functions for WordSize
 286   // arguments as in the optimized mode, both ByteSize and WordSize
 287   // are mapped to the same type and thus the compiler cannot make a
 288   // distinction anymore (=> compiler errors).
 289 
 290 #ifdef ASSERT
 291   Address(Register base, ByteSize disp)
 292     : _base(base),
 293       _index(noreg),
 294       _xmmindex(xnoreg),
 295       _scale(no_scale),
 296       _disp(in_bytes(disp)),
 297       _isxmmindex(false){
 298   }
 299 
 300   Address(Register base, Register index, ScaleFactor scale, ByteSize disp)
 301     : _base(base),
 302       _index(index),
 303       _xmmindex(xnoreg),
 304       _scale(scale),
 305       _disp(in_bytes(disp)),
 306       _isxmmindex(false){
 307     assert(!index->is_valid() == (scale == Address::no_scale),
 308            "inconsistent address");
 309   }
 310   Address(Register base, RegisterOrConstant index, ScaleFactor scale, ByteSize disp)
 311     : _base (base),
 312       _index(index.register_or_noreg()),
 313       _xmmindex(xnoreg),
 314       _scale(scale),
 315       _disp (in_bytes(disp) + (index.constant_or_zero() * scale_size(scale))),
 316       _isxmmindex(false) {
 317     if (!index.is_register())  scale = Address::no_scale;
 318     assert(!_index->is_valid() == (scale == Address::no_scale),
 319            "inconsistent address");
 320   }
 321 
 322 #endif // ASSERT
 323 
 324   // accessors
 325   bool        uses(Register reg) const { return _base == reg || _index == reg; }
 326   Register    base()             const { return _base;  }
 327   Register    index()            const { return _index; }
 328   XMMRegister xmmindex()         const { return _xmmindex; }
 329   ScaleFactor scale()            const { return _scale; }
 330   int         disp()             const { return _disp;  }
 331   bool        isxmmindex()       const { return _isxmmindex; }
 332 
 333   // Convert the raw encoding form into the form expected by the constructor for
 334   // Address.  An index of 4 (rsp) corresponds to having no index, so convert
 335   // that to noreg for the Address constructor.
 336   static Address make_raw(int base, int index, int scale, int disp, relocInfo::relocType disp_reloc);
 337 
 338   static Address make_array(ArrayAddress);
 339 
 340  private:
 341   bool base_needs_rex() const {
 342     return _base->is_valid() && _base->encoding() >= 8;
 343   }
 344 
 345   bool index_needs_rex() const {
 346     return _index->is_valid() &&_index->encoding() >= 8;
 347   }
 348 
 349   bool xmmindex_needs_rex() const {
 350     return _xmmindex->is_valid() && _xmmindex->encoding() >= 8;
 351   }
 352 
 353   relocInfo::relocType reloc() const { return _rspec.type(); }
 354 
 355   friend class Assembler;
 356   friend class MacroAssembler;
 357   friend class LIR_Assembler; // base/index/scale/disp
 358 };
 359 
 360 //
 361 // AddressLiteral has been split out from Address because operands of this type
 362 // need to be treated specially on 32bit vs. 64bit platforms. By splitting it out
 363 // the few instructions that need to deal with address literals are unique and the
 364 // MacroAssembler does not have to implement every instruction in the Assembler
 365 // in order to search for address literals that may need special handling depending
 366 // on the instruction and the platform. As small step on the way to merging i486/amd64
 367 // directories.
 368 //
 369 class AddressLiteral {
 370   friend class ArrayAddress;
 371   RelocationHolder _rspec;
 372   // Typically we use AddressLiterals we want to use their rval
 373   // However in some situations we want the lval (effect address) of the item.
 374   // We provide a special factory for making those lvals.
 375   bool _is_lval;
 376 
 377   // If the target is far we'll need to load the ea of this to
 378   // a register to reach it. Otherwise if near we can do rip
 379   // relative addressing.
 380 
 381   address          _target;
 382 
 383  protected:
 384   // creation
 385   AddressLiteral()
 386     : _is_lval(false),
 387       _target(NULL)
 388   {}
 389 
 390   public:
 391 
 392 
 393   AddressLiteral(address target, relocInfo::relocType rtype);
 394 
 395   AddressLiteral(address target, RelocationHolder const& rspec)
 396     : _rspec(rspec),
 397       _is_lval(false),
 398       _target(target)
 399   {}
 400 
 401   AddressLiteral addr() {
 402     AddressLiteral ret = *this;
 403     ret._is_lval = true;
 404     return ret;
 405   }
 406 
 407 
 408  private:
 409 
 410   address target() { return _target; }
 411   bool is_lval() { return _is_lval; }
 412 
 413   relocInfo::relocType reloc() const { return _rspec.type(); }
 414   const RelocationHolder& rspec() const { return _rspec; }
 415 
 416   friend class Assembler;
 417   friend class MacroAssembler;
 418   friend class Address;
 419   friend class LIR_Assembler;
 420 };
 421 
 422 // Convience classes
 423 class RuntimeAddress: public AddressLiteral {
 424 
 425   public:
 426 
 427   RuntimeAddress(address target) : AddressLiteral(target, relocInfo::runtime_call_type) {}
 428 
 429 };
 430 
 431 class ExternalAddress: public AddressLiteral {
 432  private:
 433   static relocInfo::relocType reloc_for_target(address target) {
 434     // Sometimes ExternalAddress is used for values which aren't
 435     // exactly addresses, like the card table base.
 436     // external_word_type can't be used for values in the first page
 437     // so just skip the reloc in that case.
 438     return external_word_Relocation::can_be_relocated(target) ? relocInfo::external_word_type : relocInfo::none;
 439   }
 440 
 441  public:
 442 
 443   ExternalAddress(address target) : AddressLiteral(target, reloc_for_target(target)) {}
 444 
 445 };
 446 
 447 class InternalAddress: public AddressLiteral {
 448 
 449   public:
 450 
 451   InternalAddress(address target) : AddressLiteral(target, relocInfo::internal_word_type) {}
 452 
 453 };
 454 
 455 // x86 can do array addressing as a single operation since disp can be an absolute
 456 // address amd64 can't. We create a class that expresses the concept but does extra
 457 // magic on amd64 to get the final result
 458 
 459 class ArrayAddress {
 460   private:
 461 
 462   AddressLiteral _base;
 463   Address        _index;
 464 
 465   public:
 466 
 467   ArrayAddress() {};
 468   ArrayAddress(AddressLiteral base, Address index): _base(base), _index(index) {};
 469   AddressLiteral base() { return _base; }
 470   Address index() { return _index; }
 471 
 472 };
 473 
 474 class InstructionAttr;
 475 
 476 // 64-bit refect the fxsave size which is 512 bytes and the new xsave area on EVEX which is another 2176 bytes
 477 // See fxsave and xsave(EVEX enabled) documentation for layout
 478 const int FPUStateSizeInWords = NOT_LP64(27) LP64_ONLY(2688 / wordSize);
 479 
 480 // The Intel x86/Amd64 Assembler: Pure assembler doing NO optimizations on the instruction
 481 // level (e.g. mov rax, 0 is not translated into xor rax, rax!); i.e., what you write
 482 // is what you get. The Assembler is generating code into a CodeBuffer.
 483 
 484 class Assembler : public AbstractAssembler  {
 485   friend class AbstractAssembler; // for the non-virtual hack
 486   friend class LIR_Assembler; // as_Address()
 487   friend class StubGenerator;
 488 
 489  public:
 490   enum Condition {                     // The x86 condition codes used for conditional jumps/moves.
 491     zero          = 0x4,
 492     notZero       = 0x5,
 493     equal         = 0x4,
 494     notEqual      = 0x5,
 495     less          = 0xc,
 496     lessEqual     = 0xe,
 497     greater       = 0xf,
 498     greaterEqual  = 0xd,
 499     below         = 0x2,
 500     belowEqual    = 0x6,
 501     above         = 0x7,
 502     aboveEqual    = 0x3,
 503     overflow      = 0x0,
 504     noOverflow    = 0x1,
 505     carrySet      = 0x2,
 506     carryClear    = 0x3,
 507     negative      = 0x8,
 508     positive      = 0x9,
 509     parity        = 0xa,
 510     noParity      = 0xb
 511   };
 512 
 513   enum Prefix {
 514     // segment overrides
 515     CS_segment = 0x2e,
 516     SS_segment = 0x36,
 517     DS_segment = 0x3e,
 518     ES_segment = 0x26,
 519     FS_segment = 0x64,
 520     GS_segment = 0x65,
 521 
 522     REX        = 0x40,
 523 
 524     REX_B      = 0x41,
 525     REX_X      = 0x42,
 526     REX_XB     = 0x43,
 527     REX_R      = 0x44,
 528     REX_RB     = 0x45,
 529     REX_RX     = 0x46,
 530     REX_RXB    = 0x47,
 531 
 532     REX_W      = 0x48,
 533 
 534     REX_WB     = 0x49,
 535     REX_WX     = 0x4A,
 536     REX_WXB    = 0x4B,
 537     REX_WR     = 0x4C,
 538     REX_WRB    = 0x4D,
 539     REX_WRX    = 0x4E,
 540     REX_WRXB   = 0x4F,
 541 
 542     VEX_3bytes = 0xC4,
 543     VEX_2bytes = 0xC5,
 544     EVEX_4bytes = 0x62,
 545     Prefix_EMPTY = 0x0
 546   };
 547 
 548   enum VexPrefix {
 549     VEX_B = 0x20,
 550     VEX_X = 0x40,
 551     VEX_R = 0x80,
 552     VEX_W = 0x80
 553   };
 554 
 555   enum ExexPrefix {
 556     EVEX_F  = 0x04,
 557     EVEX_V  = 0x08,
 558     EVEX_Rb = 0x10,
 559     EVEX_X  = 0x40,
 560     EVEX_Z  = 0x80
 561   };
 562 
 563   enum VexSimdPrefix {
 564     VEX_SIMD_NONE = 0x0,
 565     VEX_SIMD_66   = 0x1,
 566     VEX_SIMD_F3   = 0x2,
 567     VEX_SIMD_F2   = 0x3
 568   };
 569 
 570   enum VexOpcode {
 571     VEX_OPCODE_NONE  = 0x0,
 572     VEX_OPCODE_0F    = 0x1,
 573     VEX_OPCODE_0F_38 = 0x2,
 574     VEX_OPCODE_0F_3A = 0x3,
 575     VEX_OPCODE_MASK  = 0x1F
 576   };
 577 
 578   enum AvxVectorLen {
 579     AVX_128bit = 0x0,
 580     AVX_256bit = 0x1,
 581     AVX_512bit = 0x2,
 582     AVX_NoVec  = 0x4
 583   };
 584 
 585   enum EvexTupleType {
 586     EVEX_FV   = 0,
 587     EVEX_HV   = 4,
 588     EVEX_FVM  = 6,
 589     EVEX_T1S  = 7,
 590     EVEX_T1F  = 11,
 591     EVEX_T2   = 13,
 592     EVEX_T4   = 15,
 593     EVEX_T8   = 17,
 594     EVEX_HVM  = 18,
 595     EVEX_QVM  = 19,
 596     EVEX_OVM  = 20,
 597     EVEX_M128 = 21,
 598     EVEX_DUP  = 22,
 599     EVEX_ETUP = 23
 600   };
 601 
 602   enum EvexInputSizeInBits {
 603     EVEX_8bit  = 0,
 604     EVEX_16bit = 1,
 605     EVEX_32bit = 2,
 606     EVEX_64bit = 3,
 607     EVEX_NObit = 4
 608   };
 609 
 610   enum WhichOperand {
 611     // input to locate_operand, and format code for relocations
 612     imm_operand  = 0,            // embedded 32-bit|64-bit immediate operand
 613     disp32_operand = 1,          // embedded 32-bit displacement or address
 614     call32_operand = 2,          // embedded 32-bit self-relative displacement
 615 #ifndef _LP64
 616     _WhichOperand_limit = 3
 617 #else
 618      narrow_oop_operand = 3,     // embedded 32-bit immediate narrow oop
 619     _WhichOperand_limit = 4
 620 #endif
 621   };
 622 
 623   enum ComparisonPredicate {
 624     eq = 0,
 625     lt = 1,
 626     le = 2,
 627     _false = 3,
 628     neq = 4,
 629     nlt = 5,
 630     nle = 6,
 631     _true = 7
 632   };
 633 
 634   //---<  calculate length of instruction  >---
 635   // As instruction size can't be found out easily on x86/x64,
 636   // we just use '4' for len and maxlen.
 637   // instruction must start at passed address
 638   static unsigned int instr_len(unsigned char *instr) { return 4; }
 639 
 640   //---<  longest instructions  >---
 641   // Max instruction length is not specified in architecture documentation.
 642   // We could use a "safe enough" estimate (15), but just default to
 643   // instruction length guess from above.
 644   static unsigned int instr_maxlen() { return 4; }
 645 
 646   // NOTE: The general philopsophy of the declarations here is that 64bit versions
 647   // of instructions are freely declared without the need for wrapping them an ifdef.
 648   // (Some dangerous instructions are ifdef's out of inappropriate jvm's.)
 649   // In the .cpp file the implementations are wrapped so that they are dropped out
 650   // of the resulting jvm. This is done mostly to keep the footprint of MINIMAL
 651   // to the size it was prior to merging up the 32bit and 64bit assemblers.
 652   //
 653   // This does mean you'll get a linker/runtime error if you use a 64bit only instruction
 654   // in a 32bit vm. This is somewhat unfortunate but keeps the ifdef noise down.
 655 
 656 private:
 657 
 658   bool _legacy_mode_bw;
 659   bool _legacy_mode_dq;
 660   bool _legacy_mode_vl;
 661   bool _legacy_mode_vlbw;
 662   NOT_LP64(bool _is_managed;)
 663 
 664   class InstructionAttr *_attributes;
 665 
 666   // 64bit prefixes
 667   int prefix_and_encode(int reg_enc, bool byteinst = false);
 668   int prefixq_and_encode(int reg_enc);
 669 
 670   int prefix_and_encode(int dst_enc, int src_enc) {
 671     return prefix_and_encode(dst_enc, false, src_enc, false);
 672   }
 673   int prefix_and_encode(int dst_enc, bool dst_is_byte, int src_enc, bool src_is_byte);
 674   int prefixq_and_encode(int dst_enc, int src_enc);
 675 
 676 
 677   void prefix(Register reg);
 678   void prefix(Register dst, Register src, Prefix p);
 679   void prefix(Register dst, Address adr, Prefix p);
 680   void prefix(Address adr);
 681   void prefixq(Address adr);
 682 
 683 
 684   void prefix(Address adr, Register reg,  bool byteinst = false);
 685   void prefix(Address adr, XMMRegister reg);
 686   void prefixq(Address adr, Register reg);
 687   void prefixq(Address adr, XMMRegister reg);
 688 
 689   // Some prefix variant have a total mapping - they always exactly one prefix
 690   // byte per input), so beside a prefix-emitting method we provide a method
 691   // to get the prefix byte to emit. This byte can then be folded into a byte
 692   // stream. This can generate faster, more compact code.
 693   int8_t get_prefixq(Address adr);
 694   int8_t get_prefixq(Address adr, Register reg);
 695 
 696   void rex_prefix(Address adr, XMMRegister xreg,
 697                   VexSimdPrefix pre, VexOpcode opc, bool rex_w);
 698   int  rex_prefix_and_encode(int dst_enc, int src_enc,
 699                              VexSimdPrefix pre, VexOpcode opc, bool rex_w);
 700 
 701   void vex_prefix(bool vex_r, bool vex_b, bool vex_x, int nds_enc, VexSimdPrefix pre, VexOpcode opc);
 702 
 703   void evex_prefix(bool vex_r, bool vex_b, bool vex_x, bool evex_r, bool evex_v,
 704                    int nds_enc, VexSimdPrefix pre, VexOpcode opc);
 705 
 706   void vex_prefix(Address adr, int nds_enc, int xreg_enc,
 707                   VexSimdPrefix pre, VexOpcode opc,
 708                   InstructionAttr *attributes);
 709 
 710   int  vex_prefix_and_encode(int dst_enc, int nds_enc, int src_enc,
 711                              VexSimdPrefix pre, VexOpcode opc,
 712                              InstructionAttr *attributes);
 713 
 714   void simd_prefix(XMMRegister xreg, XMMRegister nds, Address adr, VexSimdPrefix pre,
 715                    VexOpcode opc, InstructionAttr *attributes);
 716 
 717   int simd_prefix_and_encode(XMMRegister dst, XMMRegister nds, XMMRegister src, VexSimdPrefix pre,
 718                              VexOpcode opc, InstructionAttr *attributes);
 719 
 720   // Helper functions for groups of instructions
 721   void emit_arith_b(int op1, int op2, Register dst, int imm8);
 722 
 723   void emit_arith(int op1, int op2, Register dst, int32_t imm32);
 724   // Force generation of a 4 byte immediate value even if it fits into 8bit
 725   void emit_arith_imm32(int op1, int op2, Register dst, int32_t imm32);
 726   void emit_arith(int op1, int op2, Register dst, Register src);
 727 
 728   bool emit_compressed_disp_byte(int &disp);
 729 
 730   void emit_operand(Register reg,
 731                     Register base, Register index, Address::ScaleFactor scale,
 732                     int disp,
 733                     RelocationHolder const& rspec,
 734                     int rip_relative_correction = 0);
 735 
 736   void emit_operand(XMMRegister reg, Register base, XMMRegister index,
 737                     Address::ScaleFactor scale,
 738                     int disp, RelocationHolder const& rspec);
 739 
 740   void emit_operand(Register reg, Address adr, int rip_relative_correction = 0);
 741 
 742   // operands that only take the original 32bit registers
 743   void emit_operand32(Register reg, Address adr);
 744 
 745   void emit_operand(XMMRegister reg,
 746                     Register base, Register index, Address::ScaleFactor scale,
 747                     int disp,
 748                     RelocationHolder const& rspec);
 749 
 750   void emit_operand(XMMRegister reg, Address adr);
 751 
 752   void emit_operand(MMXRegister reg, Address adr);
 753 
 754   // workaround gcc (3.2.1-7) bug
 755   void emit_operand(Address adr, MMXRegister reg);
 756 
 757 
 758   // Immediate-to-memory forms
 759   void emit_arith_operand(int op1, Register rm, Address adr, int32_t imm32);
 760 
 761   void emit_farith(int b1, int b2, int i);
 762 
 763 
 764  protected:
 765   #ifdef ASSERT
 766   void check_relocation(RelocationHolder const& rspec, int format);
 767   #endif
 768 
 769   void emit_data(jint data, relocInfo::relocType    rtype, int format);
 770   void emit_data(jint data, RelocationHolder const& rspec, int format);
 771   void emit_data64(jlong data, relocInfo::relocType rtype, int format = 0);
 772   void emit_data64(jlong data, RelocationHolder const& rspec, int format = 0);
 773 
 774   bool reachable(AddressLiteral adr) NOT_LP64({ return true;});
 775 
 776   // These are all easily abused and hence protected
 777 
 778   // 32BIT ONLY SECTION
 779 #ifndef _LP64
 780   // Make these disappear in 64bit mode since they would never be correct
 781   void cmp_literal32(Register src1, int32_t imm32, RelocationHolder const& rspec);   // 32BIT ONLY
 782   void cmp_literal32(Address src1, int32_t imm32, RelocationHolder const& rspec);    // 32BIT ONLY
 783 
 784   void mov_literal32(Register dst, int32_t imm32, RelocationHolder const& rspec);    // 32BIT ONLY
 785   void mov_literal32(Address dst, int32_t imm32, RelocationHolder const& rspec);     // 32BIT ONLY
 786 
 787   void push_literal32(int32_t imm32, RelocationHolder const& rspec);                 // 32BIT ONLY
 788 #else
 789   // 64BIT ONLY SECTION
 790   void mov_literal64(Register dst, intptr_t imm64, RelocationHolder const& rspec);   // 64BIT ONLY
 791 
 792   void cmp_narrow_oop(Register src1, int32_t imm32, RelocationHolder const& rspec);
 793   void cmp_narrow_oop(Address src1, int32_t imm32, RelocationHolder const& rspec);
 794 
 795   void mov_narrow_oop(Register dst, int32_t imm32, RelocationHolder const& rspec);
 796   void mov_narrow_oop(Address dst, int32_t imm32, RelocationHolder const& rspec);
 797 #endif // _LP64
 798 
 799   // These are unique in that we are ensured by the caller that the 32bit
 800   // relative in these instructions will always be able to reach the potentially
 801   // 64bit address described by entry. Since they can take a 64bit address they
 802   // don't have the 32 suffix like the other instructions in this class.
 803 
 804   void call_literal(address entry, RelocationHolder const& rspec);
 805   void jmp_literal(address entry, RelocationHolder const& rspec);
 806 
 807   // Avoid using directly section
 808   // Instructions in this section are actually usable by anyone without danger
 809   // of failure but have performance issues that are addressed my enhanced
 810   // instructions which will do the proper thing base on the particular cpu.
 811   // We protect them because we don't trust you...
 812 
 813   // Don't use next inc() and dec() methods directly. INC & DEC instructions
 814   // could cause a partial flag stall since they don't set CF flag.
 815   // Use MacroAssembler::decrement() & MacroAssembler::increment() methods
 816   // which call inc() & dec() or add() & sub() in accordance with
 817   // the product flag UseIncDec value.
 818 
 819   void decl(Register dst);
 820   void decl(Address dst);
 821   void decq(Register dst);
 822   void decq(Address dst);
 823 
 824   void incl(Register dst);
 825   void incl(Address dst);
 826   void incq(Register dst);
 827   void incq(Address dst);
 828 
 829   // New cpus require use of movsd and movss to avoid partial register stall
 830   // when loading from memory. But for old Opteron use movlpd instead of movsd.
 831   // The selection is done in MacroAssembler::movdbl() and movflt().
 832 
 833   // Move Scalar Single-Precision Floating-Point Values
 834   void movss(XMMRegister dst, Address src);
 835   void movss(XMMRegister dst, XMMRegister src);
 836   void movss(Address dst, XMMRegister src);
 837 
 838   // Move Scalar Double-Precision Floating-Point Values
 839   void movsd(XMMRegister dst, Address src);
 840   void movsd(XMMRegister dst, XMMRegister src);
 841   void movsd(Address dst, XMMRegister src);
 842   void movlpd(XMMRegister dst, Address src);
 843 
 844   // New cpus require use of movaps and movapd to avoid partial register stall
 845   // when moving between registers.
 846   void movaps(XMMRegister dst, XMMRegister src);
 847   void movapd(XMMRegister dst, XMMRegister src);
 848 
 849   // End avoid using directly
 850 
 851 
 852   // Instruction prefixes
 853   void prefix(Prefix p);
 854 
 855   public:
 856 
 857   // Creation
 858   Assembler(CodeBuffer* code) : AbstractAssembler(code) {
 859     init_attributes();
 860   }
 861 
 862   // Decoding
 863   static address locate_operand(address inst, WhichOperand which);
 864   static address locate_next_instruction(address inst);
 865 
 866   // Utilities
 867   static bool is_polling_page_far() NOT_LP64({ return false;});
 868   static bool query_compressed_disp_byte(int disp, bool is_evex_inst, int vector_len,
 869                                          int cur_tuple_type, int in_size_in_bits, int cur_encoding);
 870 
 871   // Generic instructions
 872   // Does 32bit or 64bit as needed for the platform. In some sense these
 873   // belong in macro assembler but there is no need for both varieties to exist
 874 
 875   void init_attributes(void) {
 876     _legacy_mode_bw = (VM_Version::supports_avx512bw() == false);
 877     _legacy_mode_dq = (VM_Version::supports_avx512dq() == false);
 878     _legacy_mode_vl = (VM_Version::supports_avx512vl() == false);
 879     _legacy_mode_vlbw = (VM_Version::supports_avx512vlbw() == false);
 880     NOT_LP64(_is_managed = false;)
 881     _attributes = NULL;
 882   }
 883 
 884   void set_attributes(InstructionAttr *attributes) { _attributes = attributes; }
 885   void clear_attributes(void) { _attributes = NULL; }
 886 
 887   void set_managed(void) { NOT_LP64(_is_managed = true;) }
 888   void clear_managed(void) { NOT_LP64(_is_managed = false;) }
 889   bool is_managed(void) {
 890     NOT_LP64(return _is_managed;)
 891     LP64_ONLY(return false;) }
 892 
 893   void lea(Register dst, Address src);
 894 
 895   void mov(Register dst, Register src);
 896 
 897 #ifdef _LP64
 898   // support caching the result of some routines
 899 
 900   // must be called before pusha(), popa(), vzeroupper() - checked with asserts
 901   static void precompute_instructions();
 902 
 903   void pusha_uncached();
 904   void popa_uncached();
 905 #endif
 906   void vzeroupper_uncached();
 907 
 908   void pusha();
 909   void popa();
 910 
 911   void pushf();
 912   void popf();
 913 
 914   void push(int32_t imm32);
 915 
 916   void push(Register src);
 917 
 918   void pop(Register dst);
 919 
 920   // These are dummies to prevent surprise implicit conversions to Register
 921   void push(void* v);
 922   void pop(void* v);
 923 
 924   // These do register sized moves/scans
 925   void rep_mov();
 926   void rep_stos();
 927   void rep_stosb();
 928   void repne_scan();
 929 #ifdef _LP64
 930   void repne_scanl();
 931 #endif
 932 
 933   // Vanilla instructions in lexical order
 934 
 935   void adcl(Address dst, int32_t imm32);
 936   void adcl(Address dst, Register src);
 937   void adcl(Register dst, int32_t imm32);
 938   void adcl(Register dst, Address src);
 939   void adcl(Register dst, Register src);
 940 
 941   void adcq(Register dst, int32_t imm32);
 942   void adcq(Register dst, Address src);
 943   void adcq(Register dst, Register src);
 944 
 945   void addb(Address dst, int imm8);
 946   void addw(Address dst, int imm16);
 947 
 948   void addl(Address dst, int32_t imm32);
 949   void addl(Address dst, Register src);
 950   void addl(Register dst, int32_t imm32);
 951   void addl(Register dst, Address src);
 952   void addl(Register dst, Register src);
 953 
 954   void addq(Address dst, int32_t imm32);
 955   void addq(Address dst, Register src);
 956   void addq(Register dst, int32_t imm32);
 957   void addq(Register dst, Address src);
 958   void addq(Register dst, Register src);
 959 
 960 #ifdef _LP64
 961  //Add Unsigned Integers with Carry Flag
 962   void adcxq(Register dst, Register src);
 963 
 964  //Add Unsigned Integers with Overflow Flag
 965   void adoxq(Register dst, Register src);
 966 #endif
 967 
 968   void addr_nop_4();
 969   void addr_nop_5();
 970   void addr_nop_7();
 971   void addr_nop_8();
 972 
 973   // Add Scalar Double-Precision Floating-Point Values
 974   void addsd(XMMRegister dst, Address src);
 975   void addsd(XMMRegister dst, XMMRegister src);
 976 
 977   // Add Scalar Single-Precision Floating-Point Values
 978   void addss(XMMRegister dst, Address src);
 979   void addss(XMMRegister dst, XMMRegister src);
 980 
 981   // AES instructions
 982   void aesdec(XMMRegister dst, Address src);
 983   void aesdec(XMMRegister dst, XMMRegister src);
 984   void aesdeclast(XMMRegister dst, Address src);
 985   void aesdeclast(XMMRegister dst, XMMRegister src);
 986   void aesenc(XMMRegister dst, Address src);
 987   void aesenc(XMMRegister dst, XMMRegister src);
 988   void aesenclast(XMMRegister dst, Address src);
 989   void aesenclast(XMMRegister dst, XMMRegister src);
 990   // Vector AES instructions
 991   void vaesenc(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
 992   void vaesenclast(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
 993   void vaesdec(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
 994   void vaesdeclast(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
 995 
 996   void andl(Address  dst, int32_t imm32);
 997   void andl(Register dst, int32_t imm32);
 998   void andl(Register dst, Address src);
 999   void andl(Register dst, Register src);
1000 
1001   void andq(Address  dst, int32_t imm32);
1002   void andq(Register dst, int32_t imm32);
1003   void andq(Register dst, Address src);
1004   void andq(Register dst, Register src);
1005 
1006   // BMI instructions
1007   void andnl(Register dst, Register src1, Register src2);
1008   void andnl(Register dst, Register src1, Address src2);
1009   void andnq(Register dst, Register src1, Register src2);
1010   void andnq(Register dst, Register src1, Address src2);
1011 
1012   void blsil(Register dst, Register src);
1013   void blsil(Register dst, Address src);
1014   void blsiq(Register dst, Register src);
1015   void blsiq(Register dst, Address src);
1016 
1017   void blsmskl(Register dst, Register src);
1018   void blsmskl(Register dst, Address src);
1019   void blsmskq(Register dst, Register src);
1020   void blsmskq(Register dst, Address src);
1021 
1022   void blsrl(Register dst, Register src);
1023   void blsrl(Register dst, Address src);
1024   void blsrq(Register dst, Register src);
1025   void blsrq(Register dst, Address src);
1026 
1027   void bsfl(Register dst, Register src);
1028   void bsrl(Register dst, Register src);
1029 
1030 #ifdef _LP64
1031   void bsfq(Register dst, Register src);
1032   void bsrq(Register dst, Register src);
1033 #endif
1034 
1035   void bswapl(Register reg);
1036 
1037   void bswapq(Register reg);
1038 
1039   void call(Label& L, relocInfo::relocType rtype);
1040   void call(Register reg);  // push pc; pc <- reg
1041   void call(Address adr);   // push pc; pc <- adr
1042 
1043   void cdql();
1044 
1045   void cdqq();
1046 
1047   void cld();
1048 
1049   void clflush(Address adr);
1050   void clflushopt(Address adr);
1051   void clwb(Address adr);
1052 
1053   void cmovl(Condition cc, Register dst, Register src);
1054   void cmovl(Condition cc, Register dst, Address src);
1055 
1056   void cmovq(Condition cc, Register dst, Register src);
1057   void cmovq(Condition cc, Register dst, Address src);
1058 
1059 
1060   void cmpb(Address dst, int imm8);
1061 
1062   void cmpl(Address dst, int32_t imm32);
1063 
1064   void cmpl(Register dst, int32_t imm32);
1065   void cmpl(Register dst, Register src);
1066   void cmpl(Register dst, Address src);
1067 
1068   void cmpq(Address dst, int32_t imm32);
1069   void cmpq(Address dst, Register src);
1070 
1071   void cmpq(Register dst, int32_t imm32);
1072   void cmpq(Register dst, Register src);
1073   void cmpq(Register dst, Address src);
1074 
1075   // these are dummies used to catch attempting to convert NULL to Register
1076   void cmpl(Register dst, void* junk); // dummy
1077   void cmpq(Register dst, void* junk); // dummy
1078 
1079   void cmpw(Address dst, int imm16);
1080 
1081   void cmpxchg8 (Address adr);
1082 
1083   void cmpxchgb(Register reg, Address adr);
1084   void cmpxchgl(Register reg, Address adr);
1085 
1086   void cmpxchgq(Register reg, Address adr);
1087 
1088   // Ordered Compare Scalar Double-Precision Floating-Point Values and set EFLAGS
1089   void comisd(XMMRegister dst, Address src);
1090   void comisd(XMMRegister dst, XMMRegister src);
1091 
1092   // Ordered Compare Scalar Single-Precision Floating-Point Values and set EFLAGS
1093   void comiss(XMMRegister dst, Address src);
1094   void comiss(XMMRegister dst, XMMRegister src);
1095 
1096   // Identify processor type and features
1097   void cpuid();
1098 
1099   // CRC32C
1100   void crc32(Register crc, Register v, int8_t sizeInBytes);
1101   void crc32(Register crc, Address adr, int8_t sizeInBytes);
1102 
1103   // Convert Scalar Double-Precision Floating-Point Value to Scalar Single-Precision Floating-Point Value
1104   void cvtsd2ss(XMMRegister dst, XMMRegister src);
1105   void cvtsd2ss(XMMRegister dst, Address src);
1106 
1107   // Convert Doubleword Integer to Scalar Double-Precision Floating-Point Value
1108   void cvtsi2sdl(XMMRegister dst, Register src);
1109   void cvtsi2sdl(XMMRegister dst, Address src);
1110   void cvtsi2sdq(XMMRegister dst, Register src);
1111   void cvtsi2sdq(XMMRegister dst, Address src);
1112 
1113   // Convert Doubleword Integer to Scalar Single-Precision Floating-Point Value
1114   void cvtsi2ssl(XMMRegister dst, Register src);
1115   void cvtsi2ssl(XMMRegister dst, Address src);
1116   void cvtsi2ssq(XMMRegister dst, Register src);
1117   void cvtsi2ssq(XMMRegister dst, Address src);
1118 
1119   // Convert Packed Signed Doubleword Integers to Packed Double-Precision Floating-Point Value
1120   void cvtdq2pd(XMMRegister dst, XMMRegister src);
1121 
1122   // Convert Packed Signed Doubleword Integers to Packed Single-Precision Floating-Point Value
1123   void cvtdq2ps(XMMRegister dst, XMMRegister src);
1124 
1125   // Convert Scalar Single-Precision Floating-Point Value to Scalar Double-Precision Floating-Point Value
1126   void cvtss2sd(XMMRegister dst, XMMRegister src);
1127   void cvtss2sd(XMMRegister dst, Address src);
1128 
1129   // Convert with Truncation Scalar Double-Precision Floating-Point Value to Doubleword Integer
1130   void cvttsd2sil(Register dst, Address src);
1131   void cvttsd2sil(Register dst, XMMRegister src);
1132   void cvttsd2siq(Register dst, Address src);
1133   void cvttsd2siq(Register dst, XMMRegister src);
1134 
1135   // Convert with Truncation Scalar Single-Precision Floating-Point Value to Doubleword Integer
1136   void cvttss2sil(Register dst, XMMRegister src);
1137   void cvttss2siq(Register dst, XMMRegister src);
1138 
1139   void cvttpd2dq(XMMRegister dst, XMMRegister src);
1140 
1141   //Abs of packed Integer values
1142   void pabsb(XMMRegister dst, XMMRegister src);
1143   void pabsw(XMMRegister dst, XMMRegister src);
1144   void pabsd(XMMRegister dst, XMMRegister src);
1145   void vpabsb(XMMRegister dst, XMMRegister src, int vector_len);
1146   void vpabsw(XMMRegister dst, XMMRegister src, int vector_len);
1147   void vpabsd(XMMRegister dst, XMMRegister src, int vector_len);
1148   void evpabsq(XMMRegister dst, XMMRegister src, int vector_len);
1149 
1150   // Divide Scalar Double-Precision Floating-Point Values
1151   void divsd(XMMRegister dst, Address src);
1152   void divsd(XMMRegister dst, XMMRegister src);
1153 
1154   // Divide Scalar Single-Precision Floating-Point Values
1155   void divss(XMMRegister dst, Address src);
1156   void divss(XMMRegister dst, XMMRegister src);
1157 
1158   void emms();
1159 
1160 #ifndef _LP64
1161   void fabs();
1162 
1163   void fadd(int i);
1164 
1165   void fadd_d(Address src);
1166   void fadd_s(Address src);
1167 
1168   // "Alternate" versions of x87 instructions place result down in FPU
1169   // stack instead of on TOS
1170 
1171   void fadda(int i); // "alternate" fadd
1172   void faddp(int i = 1);
1173 
1174   void fchs();
1175 
1176   void fcom(int i);
1177 
1178   void fcomp(int i = 1);
1179   void fcomp_d(Address src);
1180   void fcomp_s(Address src);
1181 
1182   void fcompp();
1183 
1184   void fcos();
1185 
1186   void fdecstp();
1187 
1188   void fdiv(int i);
1189   void fdiv_d(Address src);
1190   void fdivr_s(Address src);
1191   void fdiva(int i);  // "alternate" fdiv
1192   void fdivp(int i = 1);
1193 
1194   void fdivr(int i);
1195   void fdivr_d(Address src);
1196   void fdiv_s(Address src);
1197 
1198   void fdivra(int i); // "alternate" reversed fdiv
1199 
1200   void fdivrp(int i = 1);
1201 
1202   void ffree(int i = 0);
1203 
1204   void fild_d(Address adr);
1205   void fild_s(Address adr);
1206 
1207   void fincstp();
1208 
1209   void finit();
1210 
1211   void fist_s (Address adr);
1212   void fistp_d(Address adr);
1213   void fistp_s(Address adr);
1214 
1215   void fld1();
1216 
1217   void fld_d(Address adr);
1218   void fld_s(Address adr);
1219   void fld_s(int index);
1220   void fld_x(Address adr);  // extended-precision (80-bit) format
1221 
1222   void fldcw(Address src);
1223 
1224   void fldenv(Address src);
1225 
1226   void fldlg2();
1227 
1228   void fldln2();
1229 
1230   void fldz();
1231 
1232   void flog();
1233   void flog10();
1234 
1235   void fmul(int i);
1236 
1237   void fmul_d(Address src);
1238   void fmul_s(Address src);
1239 
1240   void fmula(int i);  // "alternate" fmul
1241 
1242   void fmulp(int i = 1);
1243 
1244   void fnsave(Address dst);
1245 
1246   void fnstcw(Address src);
1247 
1248   void fnstsw_ax();
1249 
1250   void fprem();
1251   void fprem1();
1252 
1253   void frstor(Address src);
1254 
1255   void fsin();
1256 
1257   void fsqrt();
1258 
1259   void fst_d(Address adr);
1260   void fst_s(Address adr);
1261 
1262   void fstp_d(Address adr);
1263   void fstp_d(int index);
1264   void fstp_s(Address adr);
1265   void fstp_x(Address adr); // extended-precision (80-bit) format
1266 
1267   void fsub(int i);
1268   void fsub_d(Address src);
1269   void fsub_s(Address src);
1270 
1271   void fsuba(int i);  // "alternate" fsub
1272 
1273   void fsubp(int i = 1);
1274 
1275   void fsubr(int i);
1276   void fsubr_d(Address src);
1277   void fsubr_s(Address src);
1278 
1279   void fsubra(int i); // "alternate" reversed fsub
1280 
1281   void fsubrp(int i = 1);
1282 
1283   void ftan();
1284 
1285   void ftst();
1286 
1287   void fucomi(int i = 1);
1288   void fucomip(int i = 1);
1289 
1290   void fwait();
1291 
1292   void fxch(int i = 1);
1293 
1294   void fyl2x();
1295   void frndint();
1296   void f2xm1();
1297   void fldl2e();
1298 #endif // !_LP64
1299 
1300   void fxrstor(Address src);
1301   void xrstor(Address src);
1302 
1303   void fxsave(Address dst);
1304   void xsave(Address dst);
1305 
1306   void hlt();
1307 
1308   void idivl(Register src);
1309   void divl(Register src); // Unsigned division
1310 
1311 #ifdef _LP64
1312   void idivq(Register src);
1313 #endif
1314 
1315   void imull(Register src);
1316   void imull(Register dst, Register src);
1317   void imull(Register dst, Register src, int value);
1318   void imull(Register dst, Address src);
1319 
1320 #ifdef _LP64
1321   void imulq(Register dst, Register src);
1322   void imulq(Register dst, Register src, int value);
1323   void imulq(Register dst, Address src);
1324 #endif
1325 
1326   // jcc is the generic conditional branch generator to run-
1327   // time routines, jcc is used for branches to labels. jcc
1328   // takes a branch opcode (cc) and a label (L) and generates
1329   // either a backward branch or a forward branch and links it
1330   // to the label fixup chain. Usage:
1331   //
1332   // Label L;      // unbound label
1333   // jcc(cc, L);   // forward branch to unbound label
1334   // bind(L);      // bind label to the current pc
1335   // jcc(cc, L);   // backward branch to bound label
1336   // bind(L);      // illegal: a label may be bound only once
1337   //
1338   // Note: The same Label can be used for forward and backward branches
1339   // but it may be bound only once.
1340 
1341   void jcc(Condition cc, Label& L, bool maybe_short = true);
1342 
1343   // Conditional jump to a 8-bit offset to L.
1344   // WARNING: be very careful using this for forward jumps.  If the label is
1345   // not bound within an 8-bit offset of this instruction, a run-time error
1346   // will occur.
1347 
1348   // Use macro to record file and line number.
1349   #define jccb(cc, L) jccb_0(cc, L, __FILE__, __LINE__)
1350 
1351   void jccb_0(Condition cc, Label& L, const char* file, int line);
1352 
1353   void jmp(Address entry);    // pc <- entry
1354 
1355   // Label operations & relative jumps (PPUM Appendix D)
1356   void jmp(Label& L, bool maybe_short = true);   // unconditional jump to L
1357 
1358   void jmp(Register entry); // pc <- entry
1359 
1360   // Unconditional 8-bit offset jump to L.
1361   // WARNING: be very careful using this for forward jumps.  If the label is
1362   // not bound within an 8-bit offset of this instruction, a run-time error
1363   // will occur.
1364 
1365   // Use macro to record file and line number.
1366   #define jmpb(L) jmpb_0(L, __FILE__, __LINE__)
1367 
1368   void jmpb_0(Label& L, const char* file, int line);
1369 
1370   void ldmxcsr( Address src );
1371 
1372   void leal(Register dst, Address src);
1373 
1374   void leaq(Register dst, Address src);
1375 
1376   void lfence();
1377 
1378   void lock();
1379 
1380   void lzcntl(Register dst, Register src);
1381 
1382 #ifdef _LP64
1383   void lzcntq(Register dst, Register src);
1384 #endif
1385 
1386   enum Membar_mask_bits {
1387     StoreStore = 1 << 3,
1388     LoadStore  = 1 << 2,
1389     StoreLoad  = 1 << 1,
1390     LoadLoad   = 1 << 0
1391   };
1392 
1393   // Serializes memory and blows flags
1394   void membar(Membar_mask_bits order_constraint) {
1395     // We only have to handle StoreLoad
1396     if (order_constraint & StoreLoad) {
1397       // All usable chips support "locked" instructions which suffice
1398       // as barriers, and are much faster than the alternative of
1399       // using cpuid instruction. We use here a locked add [esp-C],0.
1400       // This is conveniently otherwise a no-op except for blowing
1401       // flags, and introducing a false dependency on target memory
1402       // location. We can't do anything with flags, but we can avoid
1403       // memory dependencies in the current method by locked-adding
1404       // somewhere else on the stack. Doing [esp+C] will collide with
1405       // something on stack in current method, hence we go for [esp-C].
1406       // It is convenient since it is almost always in data cache, for
1407       // any small C.  We need to step back from SP to avoid data
1408       // dependencies with other things on below SP (callee-saves, for
1409       // example). Without a clear way to figure out the minimal safe
1410       // distance from SP, it makes sense to step back the complete
1411       // cache line, as this will also avoid possible second-order effects
1412       // with locked ops against the cache line. Our choice of offset
1413       // is bounded by x86 operand encoding, which should stay within
1414       // [-128; +127] to have the 8-byte displacement encoding.
1415       //
1416       // Any change to this code may need to revisit other places in
1417       // the code where this idiom is used, in particular the
1418       // orderAccess code.
1419 
1420       int offset = -VM_Version::L1_line_size();
1421       if (offset < -128) {
1422         offset = -128;
1423       }
1424 
1425       lock();
1426       addl(Address(rsp, offset), 0);// Assert the lock# signal here
1427     }
1428   }
1429 
1430   void mfence();
1431   void sfence();
1432 
1433   // Moves
1434 
1435   void mov64(Register dst, int64_t imm64);
1436 
1437   void movb(Address dst, Register src);
1438   void movb(Address dst, int imm8);
1439   void movb(Register dst, Address src);
1440 
1441   void movddup(XMMRegister dst, XMMRegister src);
1442 
1443   void kmovbl(KRegister dst, Register src);
1444   void kmovbl(Register dst, KRegister src);
1445   void kmovwl(KRegister dst, Register src);
1446   void kmovwl(KRegister dst, Address src);
1447   void kmovwl(Register dst, KRegister src);
1448   void kmovdl(KRegister dst, Register src);
1449   void kmovdl(Register dst, KRegister src);
1450   void kmovql(KRegister dst, KRegister src);
1451   void kmovql(Address dst, KRegister src);
1452   void kmovql(KRegister dst, Address src);
1453   void kmovql(KRegister dst, Register src);
1454   void kmovql(Register dst, KRegister src);
1455 
1456   void knotwl(KRegister dst, KRegister src);
1457 
1458   void kortestbl(KRegister dst, KRegister src);
1459   void kortestwl(KRegister dst, KRegister src);
1460   void kortestdl(KRegister dst, KRegister src);
1461   void kortestql(KRegister dst, KRegister src);
1462 
1463   void ktestq(KRegister src1, KRegister src2);
1464   void ktestd(KRegister src1, KRegister src2);
1465 
1466   void ktestql(KRegister dst, KRegister src);
1467 
1468   void movdl(XMMRegister dst, Register src);
1469   void movdl(Register dst, XMMRegister src);
1470   void movdl(XMMRegister dst, Address src);
1471   void movdl(Address dst, XMMRegister src);
1472 
1473   // Move Double Quadword
1474   void movdq(XMMRegister dst, Register src);
1475   void movdq(Register dst, XMMRegister src);
1476 
1477   // Move Aligned Double Quadword
1478   void movdqa(XMMRegister dst, XMMRegister src);
1479   void movdqa(XMMRegister dst, Address src);
1480 
1481   // Move Unaligned Double Quadword
1482   void movdqu(Address     dst, XMMRegister src);
1483   void movdqu(XMMRegister dst, Address src);
1484   void movdqu(XMMRegister dst, XMMRegister src);
1485 
1486   // Move Unaligned 256bit Vector
1487   void vmovdqu(Address dst, XMMRegister src);
1488   void vmovdqu(XMMRegister dst, Address src);
1489   void vmovdqu(XMMRegister dst, XMMRegister src);
1490 
1491    // Move Unaligned 512bit Vector
1492   void evmovdqub(Address dst, XMMRegister src, int vector_len);
1493   void evmovdqub(XMMRegister dst, Address src, int vector_len);
1494   void evmovdqub(XMMRegister dst, XMMRegister src, int vector_len);
1495   void evmovdqub(XMMRegister dst, KRegister mask, Address src, int vector_len);
1496   void evmovdquw(Address dst, XMMRegister src, int vector_len);
1497   void evmovdquw(Address dst, KRegister mask, XMMRegister src, int vector_len);
1498   void evmovdquw(XMMRegister dst, Address src, int vector_len);
1499   void evmovdquw(XMMRegister dst, KRegister mask, Address src, int vector_len);
1500   void evmovdqul(Address dst, XMMRegister src, int vector_len);
1501   void evmovdqul(XMMRegister dst, Address src, int vector_len);
1502   void evmovdqul(XMMRegister dst, XMMRegister src, int vector_len);
1503   void evmovdquq(Address dst, XMMRegister src, int vector_len);
1504   void evmovdquq(XMMRegister dst, Address src, int vector_len);
1505   void evmovdquq(XMMRegister dst, XMMRegister src, int vector_len);
1506 
1507   // Move lower 64bit to high 64bit in 128bit register
1508   void movlhps(XMMRegister dst, XMMRegister src);
1509 
1510   void movl(Register dst, int32_t imm32);
1511   void movl(Address dst, int32_t imm32);
1512   void movl(Register dst, Register src);
1513   void movl(Register dst, Address src);
1514   void movl(Address dst, Register src);
1515 
1516   // These dummies prevent using movl from converting a zero (like NULL) into Register
1517   // by giving the compiler two choices it can't resolve
1518 
1519   void movl(Address  dst, void* junk);
1520   void movl(Register dst, void* junk);
1521 
1522 #ifdef _LP64
1523   void movq(Register dst, Register src);
1524   void movq(Register dst, Address src);
1525   void movq(Address  dst, Register src);
1526 #endif
1527 
1528   void movq(Address     dst, MMXRegister src );
1529   void movq(MMXRegister dst, Address src );
1530 
1531 #ifdef _LP64
1532   // These dummies prevent using movq from converting a zero (like NULL) into Register
1533   // by giving the compiler two choices it can't resolve
1534 
1535   void movq(Address  dst, void* dummy);
1536   void movq(Register dst, void* dummy);
1537 #endif
1538 
1539   // Move Quadword
1540   void movq(Address     dst, XMMRegister src);
1541   void movq(XMMRegister dst, Address src);
1542 
1543   void movsbl(Register dst, Address src);
1544   void movsbl(Register dst, Register src);
1545 
1546 #ifdef _LP64
1547   void movsbq(Register dst, Address src);
1548   void movsbq(Register dst, Register src);
1549 
1550   // Move signed 32bit immediate to 64bit extending sign
1551   void movslq(Address  dst, int32_t imm64);
1552   void movslq(Register dst, int32_t imm64);
1553 
1554   void movslq(Register dst, Address src);
1555   void movslq(Register dst, Register src);
1556   void movslq(Register dst, void* src); // Dummy declaration to cause NULL to be ambiguous
1557 #endif
1558 
1559   void movswl(Register dst, Address src);
1560   void movswl(Register dst, Register src);
1561 
1562 #ifdef _LP64
1563   void movswq(Register dst, Address src);
1564   void movswq(Register dst, Register src);
1565 #endif
1566 
1567   void movw(Address dst, int imm16);
1568   void movw(Register dst, Address src);
1569   void movw(Address dst, Register src);
1570 
1571   void movzbl(Register dst, Address src);
1572   void movzbl(Register dst, Register src);
1573 
1574 #ifdef _LP64
1575   void movzbq(Register dst, Address src);
1576   void movzbq(Register dst, Register src);
1577 #endif
1578 
1579   void movzwl(Register dst, Address src);
1580   void movzwl(Register dst, Register src);
1581 
1582 #ifdef _LP64
1583   void movzwq(Register dst, Address src);
1584   void movzwq(Register dst, Register src);
1585 #endif
1586 
1587   // Unsigned multiply with RAX destination register
1588   void mull(Address src);
1589   void mull(Register src);
1590 
1591 #ifdef _LP64
1592   void mulq(Address src);
1593   void mulq(Register src);
1594   void mulxq(Register dst1, Register dst2, Register src);
1595 #endif
1596 
1597   // Multiply Scalar Double-Precision Floating-Point Values
1598   void mulsd(XMMRegister dst, Address src);
1599   void mulsd(XMMRegister dst, XMMRegister src);
1600 
1601   // Multiply Scalar Single-Precision Floating-Point Values
1602   void mulss(XMMRegister dst, Address src);
1603   void mulss(XMMRegister dst, XMMRegister src);
1604 
1605   void negl(Register dst);
1606 
1607 #ifdef _LP64
1608   void negq(Register dst);
1609 #endif
1610 
1611   void nop(int i = 1);
1612 
1613   void notl(Register dst);
1614 
1615 #ifdef _LP64
1616   void notq(Register dst);
1617 
1618   void btsq(Address dst, int imm8);
1619   void btrq(Address dst, int imm8);
1620 #endif
1621 
1622   void orl(Address dst, int32_t imm32);
1623   void orl(Register dst, int32_t imm32);
1624   void orl(Register dst, Address src);
1625   void orl(Register dst, Register src);
1626   void orl(Address dst, Register src);
1627 
1628   void orb(Address dst, int imm8);
1629 
1630   void orq(Address dst, int32_t imm32);
1631   void orq(Register dst, int32_t imm32);
1632   void orq(Register dst, Address src);
1633   void orq(Register dst, Register src);
1634 
1635   // Pack with unsigned saturation
1636   void packuswb(XMMRegister dst, XMMRegister src);
1637   void packuswb(XMMRegister dst, Address src);
1638   void vpackuswb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1639 
1640   // Pemutation of 64bit words
1641   void vpermq(XMMRegister dst, XMMRegister src, int imm8, int vector_len);
1642   void vpermq(XMMRegister dst, XMMRegister src, int imm8);
1643   void vpermq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1644   void vperm2i128(XMMRegister dst,  XMMRegister nds, XMMRegister src, int imm8);
1645   void vperm2f128(XMMRegister dst, XMMRegister nds, XMMRegister src, int imm8);
1646   void evpermi2q(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1647 
1648   void pause();
1649 
1650   // Undefined Instruction
1651   void ud2();
1652 
1653   // SSE4.2 string instructions
1654   void pcmpestri(XMMRegister xmm1, XMMRegister xmm2, int imm8);
1655   void pcmpestri(XMMRegister xmm1, Address src, int imm8);
1656 
1657   void pcmpeqb(XMMRegister dst, XMMRegister src);
1658   void vpcmpeqb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1659   void evpcmpeqb(KRegister kdst, XMMRegister nds, XMMRegister src, int vector_len);
1660   void evpcmpeqb(KRegister kdst, XMMRegister nds, Address src, int vector_len);
1661   void evpcmpeqb(KRegister kdst, KRegister mask, XMMRegister nds, Address src, int vector_len);
1662 
1663   void evpcmpgtb(KRegister kdst, XMMRegister nds, Address src, int vector_len);
1664   void evpcmpgtb(KRegister kdst, KRegister mask, XMMRegister nds, Address src, int vector_len);
1665 
1666   void evpcmpuw(KRegister kdst, XMMRegister nds, XMMRegister src, ComparisonPredicate vcc, int vector_len);
1667   void evpcmpuw(KRegister kdst, KRegister mask, XMMRegister nds, XMMRegister src, ComparisonPredicate of, int vector_len);
1668   void evpcmpuw(KRegister kdst, XMMRegister nds, Address src, ComparisonPredicate vcc, int vector_len);
1669 
1670   void pcmpeqw(XMMRegister dst, XMMRegister src);
1671   void vpcmpeqw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1672   void evpcmpeqw(KRegister kdst, XMMRegister nds, XMMRegister src, int vector_len);
1673   void evpcmpeqw(KRegister kdst, XMMRegister nds, Address src, int vector_len);
1674 
1675   void pcmpeqd(XMMRegister dst, XMMRegister src);
1676   void vpcmpeqd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1677   void evpcmpeqd(KRegister kdst, XMMRegister nds, XMMRegister src, int vector_len);
1678   void evpcmpeqd(KRegister kdst, XMMRegister nds, Address src, int vector_len);
1679 
1680   void pcmpeqq(XMMRegister dst, XMMRegister src);
1681   void vpcmpeqq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1682   void evpcmpeqq(KRegister kdst, XMMRegister nds, XMMRegister src, int vector_len);
1683   void evpcmpeqq(KRegister kdst, XMMRegister nds, Address src, int vector_len);
1684 
1685   void pmovmskb(Register dst, XMMRegister src);
1686   void vpmovmskb(Register dst, XMMRegister src);
1687 
1688   // SSE 4.1 extract
1689   void pextrd(Register dst, XMMRegister src, int imm8);
1690   void pextrq(Register dst, XMMRegister src, int imm8);
1691   void pextrd(Address dst, XMMRegister src, int imm8);
1692   void pextrq(Address dst, XMMRegister src, int imm8);
1693   void pextrb(Address dst, XMMRegister src, int imm8);
1694   // SSE 2 extract
1695   void pextrw(Register dst, XMMRegister src, int imm8);
1696   void pextrw(Address dst, XMMRegister src, int imm8);
1697 
1698   // SSE 4.1 insert
1699   void pinsrd(XMMRegister dst, Register src, int imm8);
1700   void pinsrq(XMMRegister dst, Register src, int imm8);
1701   void pinsrd(XMMRegister dst, Address src, int imm8);
1702   void pinsrq(XMMRegister dst, Address src, int imm8);
1703   void pinsrb(XMMRegister dst, Address src, int imm8);
1704   // SSE 2 insert
1705   void pinsrw(XMMRegister dst, Register src, int imm8);
1706   void pinsrw(XMMRegister dst, Address src, int imm8);
1707 
1708   // SSE4.1 packed move
1709   void pmovzxbw(XMMRegister dst, XMMRegister src);
1710   void pmovzxbw(XMMRegister dst, Address src);
1711 
1712   void vpmovzxbw( XMMRegister dst, Address src, int vector_len);
1713   void vpmovzxbw(XMMRegister dst, XMMRegister src, int vector_len);
1714   void evpmovzxbw(XMMRegister dst, KRegister mask, Address src, int vector_len);
1715 
1716   void evpmovwb(Address dst, XMMRegister src, int vector_len);
1717   void evpmovwb(Address dst, KRegister mask, XMMRegister src, int vector_len);
1718 
1719   void vpmovzxwd(XMMRegister dst, XMMRegister src, int vector_len);
1720 
1721   void evpmovdb(Address dst, XMMRegister src, int vector_len);
1722 
1723   // Sign extend moves
1724   void pmovsxbw(XMMRegister dst, XMMRegister src);
1725   void vpmovsxbw(XMMRegister dst, XMMRegister src, int vector_len);
1726 
1727   // Multiply add
1728   void pmaddwd(XMMRegister dst, XMMRegister src);
1729   void vpmaddwd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1730   // Multiply add accumulate
1731   void evpdpwssd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1732 
1733 #ifndef _LP64 // no 32bit push/pop on amd64
1734   void popl(Address dst);
1735 #endif
1736 
1737 #ifdef _LP64
1738   void popq(Address dst);
1739 #endif
1740 
1741   void popcntl(Register dst, Address src);
1742   void popcntl(Register dst, Register src);
1743 
1744   void vpopcntd(XMMRegister dst, XMMRegister src, int vector_len);
1745 
1746 #ifdef _LP64
1747   void popcntq(Register dst, Address src);
1748   void popcntq(Register dst, Register src);
1749 #endif
1750 
1751   // Prefetches (SSE, SSE2, 3DNOW only)
1752 
1753   void prefetchnta(Address src);
1754   void prefetchr(Address src);
1755   void prefetcht0(Address src);
1756   void prefetcht1(Address src);
1757   void prefetcht2(Address src);
1758   void prefetchw(Address src);
1759 
1760   // Shuffle Bytes
1761   void pshufb(XMMRegister dst, XMMRegister src);
1762   void pshufb(XMMRegister dst, Address src);
1763   void vpshufb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1764 
1765   // Shuffle Packed Doublewords
1766   void pshufd(XMMRegister dst, XMMRegister src, int mode);
1767   void pshufd(XMMRegister dst, Address src,     int mode);
1768   void vpshufd(XMMRegister dst, XMMRegister src, int mode, int vector_len);
1769 
1770   // Shuffle Packed Low Words
1771   void pshuflw(XMMRegister dst, XMMRegister src, int mode);
1772   void pshuflw(XMMRegister dst, Address src,     int mode);
1773 
1774   // Shuffle packed values at 128 bit granularity
1775   void evshufi64x2(XMMRegister dst, XMMRegister nds, XMMRegister src, int imm8, int vector_len);
1776 
1777   // Shift Right by bytes Logical DoubleQuadword Immediate
1778   void psrldq(XMMRegister dst, int shift);
1779   // Shift Left by bytes Logical DoubleQuadword Immediate
1780   void pslldq(XMMRegister dst, int shift);
1781 
1782   // Logical Compare 128bit
1783   void ptest(XMMRegister dst, XMMRegister src);
1784   void ptest(XMMRegister dst, Address src);
1785   // Logical Compare 256bit
1786   void vptest(XMMRegister dst, XMMRegister src);
1787   void vptest(XMMRegister dst, Address src);
1788 
1789   // Interleave Low Bytes
1790   void punpcklbw(XMMRegister dst, XMMRegister src);
1791   void punpcklbw(XMMRegister dst, Address src);
1792 
1793   // Interleave Low Doublewords
1794   void punpckldq(XMMRegister dst, XMMRegister src);
1795   void punpckldq(XMMRegister dst, Address src);
1796 
1797   // Interleave Low Quadwords
1798   void punpcklqdq(XMMRegister dst, XMMRegister src);
1799 
1800 #ifndef _LP64 // no 32bit push/pop on amd64
1801   void pushl(Address src);
1802 #endif
1803 
1804   void pushq(Address src);
1805 
1806   void rcll(Register dst, int imm8);
1807 
1808   void rclq(Register dst, int imm8);
1809 
1810   void rcrq(Register dst, int imm8);
1811 
1812   void rcpps(XMMRegister dst, XMMRegister src);
1813 
1814   void rcpss(XMMRegister dst, XMMRegister src);
1815 
1816   void rdtsc();
1817 
1818   void ret(int imm16);
1819 
1820 #ifdef _LP64
1821   void rorq(Register dst, int imm8);
1822   void rorxq(Register dst, Register src, int imm8);
1823   void rorxd(Register dst, Register src, int imm8);
1824 #endif
1825 
1826   void sahf();
1827 
1828   void sarl(Register dst, int imm8);
1829   void sarl(Register dst);
1830 
1831   void sarq(Register dst, int imm8);
1832   void sarq(Register dst);
1833 
1834   void sbbl(Address dst, int32_t imm32);
1835   void sbbl(Register dst, int32_t imm32);
1836   void sbbl(Register dst, Address src);
1837   void sbbl(Register dst, Register src);
1838 
1839   void sbbq(Address dst, int32_t imm32);
1840   void sbbq(Register dst, int32_t imm32);
1841   void sbbq(Register dst, Address src);
1842   void sbbq(Register dst, Register src);
1843 
1844   void setb(Condition cc, Register dst);
1845 
1846   void palignr(XMMRegister dst, XMMRegister src, int imm8);
1847   void vpalignr(XMMRegister dst, XMMRegister src1, XMMRegister src2, int imm8, int vector_len);
1848   void evalignq(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8);
1849 
1850   void pblendw(XMMRegister dst, XMMRegister src, int imm8);
1851 
1852   void sha1rnds4(XMMRegister dst, XMMRegister src, int imm8);
1853   void sha1nexte(XMMRegister dst, XMMRegister src);
1854   void sha1msg1(XMMRegister dst, XMMRegister src);
1855   void sha1msg2(XMMRegister dst, XMMRegister src);
1856   // xmm0 is implicit additional source to the following instruction.
1857   void sha256rnds2(XMMRegister dst, XMMRegister src);
1858   void sha256msg1(XMMRegister dst, XMMRegister src);
1859   void sha256msg2(XMMRegister dst, XMMRegister src);
1860 
1861   void shldl(Register dst, Register src);
1862   void shldl(Register dst, Register src, int8_t imm8);
1863   void shrdl(Register dst, Register src);
1864   void shrdl(Register dst, Register src, int8_t imm8);
1865 
1866   void shll(Register dst, int imm8);
1867   void shll(Register dst);
1868 
1869   void shlq(Register dst, int imm8);
1870   void shlq(Register dst);
1871 
1872   void shrl(Register dst, int imm8);
1873   void shrl(Register dst);
1874 
1875   void shrq(Register dst, int imm8);
1876   void shrq(Register dst);
1877 
1878   void smovl(); // QQQ generic?
1879 
1880   // Compute Square Root of Scalar Double-Precision Floating-Point Value
1881   void sqrtsd(XMMRegister dst, Address src);
1882   void sqrtsd(XMMRegister dst, XMMRegister src);
1883 
1884   void roundsd(XMMRegister dst, Address src, int32_t rmode);
1885   void roundsd(XMMRegister dst, XMMRegister src, int32_t rmode);
1886 
1887   // Compute Square Root of Scalar Single-Precision Floating-Point Value
1888   void sqrtss(XMMRegister dst, Address src);
1889   void sqrtss(XMMRegister dst, XMMRegister src);
1890 
1891   void std();
1892 
1893   void stmxcsr( Address dst );
1894 
1895   void subl(Address dst, int32_t imm32);
1896   void subl(Address dst, Register src);
1897   void subl(Register dst, int32_t imm32);
1898   void subl(Register dst, Address src);
1899   void subl(Register dst, Register src);
1900 
1901   void subq(Address dst, int32_t imm32);
1902   void subq(Address dst, Register src);
1903   void subq(Register dst, int32_t imm32);
1904   void subq(Register dst, Address src);
1905   void subq(Register dst, Register src);
1906 
1907   // Force generation of a 4 byte immediate value even if it fits into 8bit
1908   void subl_imm32(Register dst, int32_t imm32);
1909   void subq_imm32(Register dst, int32_t imm32);
1910 
1911   // Subtract Scalar Double-Precision Floating-Point Values
1912   void subsd(XMMRegister dst, Address src);
1913   void subsd(XMMRegister dst, XMMRegister src);
1914 
1915   // Subtract Scalar Single-Precision Floating-Point Values
1916   void subss(XMMRegister dst, Address src);
1917   void subss(XMMRegister dst, XMMRegister src);
1918 
1919   void testb(Register dst, int imm8);
1920   void testb(Address dst, int imm8);
1921 
1922   void testl(Register dst, int32_t imm32);
1923   void testl(Register dst, Register src);
1924   void testl(Register dst, Address src);
1925 
1926   void testq(Register dst, int32_t imm32);
1927   void testq(Register dst, Register src);
1928   void testq(Register dst, Address src);
1929 
1930   // BMI - count trailing zeros
1931   void tzcntl(Register dst, Register src);
1932   void tzcntq(Register dst, Register src);
1933 
1934   // Unordered Compare Scalar Double-Precision Floating-Point Values and set EFLAGS
1935   void ucomisd(XMMRegister dst, Address src);
1936   void ucomisd(XMMRegister dst, XMMRegister src);
1937 
1938   // Unordered Compare Scalar Single-Precision Floating-Point Values and set EFLAGS
1939   void ucomiss(XMMRegister dst, Address src);
1940   void ucomiss(XMMRegister dst, XMMRegister src);
1941 
1942   void xabort(int8_t imm8);
1943 
1944   void xaddb(Address dst, Register src);
1945   void xaddw(Address dst, Register src);
1946   void xaddl(Address dst, Register src);
1947   void xaddq(Address dst, Register src);
1948 
1949   void xbegin(Label& abort, relocInfo::relocType rtype = relocInfo::none);
1950 
1951   void xchgb(Register reg, Address adr);
1952   void xchgw(Register reg, Address adr);
1953   void xchgl(Register reg, Address adr);
1954   void xchgl(Register dst, Register src);
1955 
1956   void xchgq(Register reg, Address adr);
1957   void xchgq(Register dst, Register src);
1958 
1959   void xend();
1960 
1961   // Get Value of Extended Control Register
1962   void xgetbv();
1963 
1964   void xorl(Register dst, int32_t imm32);
1965   void xorl(Register dst, Address src);
1966   void xorl(Register dst, Register src);
1967 
1968   void xorb(Register dst, Address src);
1969 
1970   void xorq(Register dst, Address src);
1971   void xorq(Register dst, Register src);
1972 
1973   void set_byte_if_not_zero(Register dst); // sets reg to 1 if not zero, otherwise 0
1974 
1975   // AVX 3-operands scalar instructions (encoded with VEX prefix)
1976 
1977   void vaddsd(XMMRegister dst, XMMRegister nds, Address src);
1978   void vaddsd(XMMRegister dst, XMMRegister nds, XMMRegister src);
1979   void vaddss(XMMRegister dst, XMMRegister nds, Address src);
1980   void vaddss(XMMRegister dst, XMMRegister nds, XMMRegister src);
1981   void vdivsd(XMMRegister dst, XMMRegister nds, Address src);
1982   void vdivsd(XMMRegister dst, XMMRegister nds, XMMRegister src);
1983   void vdivss(XMMRegister dst, XMMRegister nds, Address src);
1984   void vdivss(XMMRegister dst, XMMRegister nds, XMMRegister src);
1985   void vfmadd231sd(XMMRegister dst, XMMRegister nds, XMMRegister src);
1986   void vfmadd231ss(XMMRegister dst, XMMRegister nds, XMMRegister src);
1987   void vmulsd(XMMRegister dst, XMMRegister nds, Address src);
1988   void vmulsd(XMMRegister dst, XMMRegister nds, XMMRegister src);
1989   void vmulss(XMMRegister dst, XMMRegister nds, Address src);
1990   void vmulss(XMMRegister dst, XMMRegister nds, XMMRegister src);
1991   void vsubsd(XMMRegister dst, XMMRegister nds, Address src);
1992   void vsubsd(XMMRegister dst, XMMRegister nds, XMMRegister src);
1993   void vsubss(XMMRegister dst, XMMRegister nds, Address src);
1994   void vsubss(XMMRegister dst, XMMRegister nds, XMMRegister src);
1995 
1996   void vmaxss(XMMRegister dst, XMMRegister nds, XMMRegister src);
1997   void vmaxsd(XMMRegister dst, XMMRegister nds, XMMRegister src);
1998   void vminss(XMMRegister dst, XMMRegister nds, XMMRegister src);
1999   void vminsd(XMMRegister dst, XMMRegister nds, XMMRegister src);
2000 
2001   void shlxl(Register dst, Register src1, Register src2);
2002   void shlxq(Register dst, Register src1, Register src2);
2003 
2004   //====================VECTOR ARITHMETIC=====================================
2005 
2006   // Add Packed Floating-Point Values
2007   void addpd(XMMRegister dst, XMMRegister src);
2008   void addpd(XMMRegister dst, Address src);
2009   void addps(XMMRegister dst, XMMRegister src);
2010   void vaddpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2011   void vaddps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2012   void vaddpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2013   void vaddps(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2014 
2015   // Subtract Packed Floating-Point Values
2016   void subpd(XMMRegister dst, XMMRegister src);
2017   void subps(XMMRegister dst, XMMRegister src);
2018   void vsubpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2019   void vsubps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2020   void vsubpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2021   void vsubps(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2022 
2023   // Multiply Packed Floating-Point Values
2024   void mulpd(XMMRegister dst, XMMRegister src);
2025   void mulpd(XMMRegister dst, Address src);
2026   void mulps(XMMRegister dst, XMMRegister src);
2027   void vmulpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2028   void vmulps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2029   void vmulpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2030   void vmulps(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2031 
2032   void vfmadd231pd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2033   void vfmadd231ps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2034   void vfmadd231pd(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2035   void vfmadd231ps(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2036 
2037   // Divide Packed Floating-Point Values
2038   void divpd(XMMRegister dst, XMMRegister src);
2039   void divps(XMMRegister dst, XMMRegister src);
2040   void vdivpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2041   void vdivps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2042   void vdivpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2043   void vdivps(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2044 
2045   // Sqrt Packed Floating-Point Values
2046   void vsqrtpd(XMMRegister dst, XMMRegister src, int vector_len);
2047   void vsqrtpd(XMMRegister dst, Address src, int vector_len);
2048   void vsqrtps(XMMRegister dst, XMMRegister src, int vector_len);
2049   void vsqrtps(XMMRegister dst, Address src, int vector_len);
2050 
2051   // Round Packed Double precision value.
2052   void vroundpd(XMMRegister dst, XMMRegister src, int32_t rmode, int vector_len);
2053   void vroundpd(XMMRegister dst, Address src, int32_t rmode, int vector_len);
2054   void vrndscalepd(XMMRegister dst,  XMMRegister src,  int32_t rmode, int vector_len);
2055   void vrndscalepd(XMMRegister dst, Address src, int32_t rmode, int vector_len);
2056 
2057   // Bitwise Logical AND of Packed Floating-Point Values
2058   void andpd(XMMRegister dst, XMMRegister src);
2059   void andps(XMMRegister dst, XMMRegister src);
2060   void vandpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2061   void vandps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2062   void vandpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2063   void vandps(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2064 
2065   void unpckhpd(XMMRegister dst, XMMRegister src);
2066   void unpcklpd(XMMRegister dst, XMMRegister src);
2067 
2068   // Bitwise Logical XOR of Packed Floating-Point Values
2069   void xorpd(XMMRegister dst, XMMRegister src);
2070   void xorps(XMMRegister dst, XMMRegister src);
2071   void vxorpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2072   void vxorps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2073   void vxorpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2074   void vxorps(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2075 
2076   // Add horizontal packed integers
2077   void vphaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2078   void vphaddd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2079   void phaddw(XMMRegister dst, XMMRegister src);
2080   void phaddd(XMMRegister dst, XMMRegister src);
2081 
2082   // Add packed integers
2083   void paddb(XMMRegister dst, XMMRegister src);
2084   void paddw(XMMRegister dst, XMMRegister src);
2085   void paddd(XMMRegister dst, XMMRegister src);
2086   void paddd(XMMRegister dst, Address src);
2087   void paddq(XMMRegister dst, XMMRegister src);
2088   void vpaddb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2089   void vpaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2090   void vpaddd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2091   void vpaddq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2092   void vpaddb(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2093   void vpaddw(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2094   void vpaddd(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2095   void vpaddq(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2096 
2097   // Sub packed integers
2098   void psubb(XMMRegister dst, XMMRegister src);
2099   void psubw(XMMRegister dst, XMMRegister src);
2100   void psubd(XMMRegister dst, XMMRegister src);
2101   void psubq(XMMRegister dst, XMMRegister src);
2102   void vpsubb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2103   void vpsubw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2104   void vpsubd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2105   void vpsubq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2106   void vpsubb(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2107   void vpsubw(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2108   void vpsubd(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2109   void vpsubq(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2110 
2111   // Multiply packed integers (only shorts and ints)
2112   void pmullw(XMMRegister dst, XMMRegister src);
2113   void pmulld(XMMRegister dst, XMMRegister src);
2114   void vpmullw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2115   void vpmulld(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2116   void vpmullq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2117   void vpmullw(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2118   void vpmulld(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2119   void vpmullq(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2120 
2121   // Shift left packed integers
2122   void psllw(XMMRegister dst, int shift);
2123   void pslld(XMMRegister dst, int shift);
2124   void psllq(XMMRegister dst, int shift);
2125   void psllw(XMMRegister dst, XMMRegister shift);
2126   void pslld(XMMRegister dst, XMMRegister shift);
2127   void psllq(XMMRegister dst, XMMRegister shift);
2128   void vpsllw(XMMRegister dst, XMMRegister src, int shift, int vector_len);
2129   void vpslld(XMMRegister dst, XMMRegister src, int shift, int vector_len);
2130   void vpsllq(XMMRegister dst, XMMRegister src, int shift, int vector_len);
2131   void vpsllw(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len);
2132   void vpslld(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len);
2133   void vpsllq(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len);
2134   void vpslldq(XMMRegister dst, XMMRegister src, int shift, int vector_len);
2135 
2136   // Logical shift right packed integers
2137   void psrlw(XMMRegister dst, int shift);
2138   void psrld(XMMRegister dst, int shift);
2139   void psrlq(XMMRegister dst, int shift);
2140   void psrlw(XMMRegister dst, XMMRegister shift);
2141   void psrld(XMMRegister dst, XMMRegister shift);
2142   void psrlq(XMMRegister dst, XMMRegister shift);
2143   void vpsrlw(XMMRegister dst, XMMRegister src, int shift, int vector_len);
2144   void vpsrld(XMMRegister dst, XMMRegister src, int shift, int vector_len);
2145   void vpsrlq(XMMRegister dst, XMMRegister src, int shift, int vector_len);
2146   void vpsrlw(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len);
2147   void vpsrld(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len);
2148   void vpsrlq(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len);
2149   void vpsrldq(XMMRegister dst, XMMRegister src, int shift, int vector_len);
2150   void evpsrlvw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2151   void evpsllvw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2152 
2153   // Arithmetic shift right packed integers (only shorts and ints, no instructions for longs)
2154   void psraw(XMMRegister dst, int shift);
2155   void psrad(XMMRegister dst, int shift);
2156   void psraw(XMMRegister dst, XMMRegister shift);
2157   void psrad(XMMRegister dst, XMMRegister shift);
2158   void vpsraw(XMMRegister dst, XMMRegister src, int shift, int vector_len);
2159   void vpsrad(XMMRegister dst, XMMRegister src, int shift, int vector_len);
2160   void vpsraw(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len);
2161   void vpsrad(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len);
2162   void evpsraq(XMMRegister dst, XMMRegister src, int shift, int vector_len);
2163   void evpsraq(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len);
2164 
2165   void vpshldvd(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len);
2166   void vpshrdvd(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len);
2167 
2168   // And packed integers
2169   void pand(XMMRegister dst, XMMRegister src);
2170   void vpand(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2171   void vpand(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2172   void vpandq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2173 
2174   // Andn packed integers
2175   void pandn(XMMRegister dst, XMMRegister src);
2176   void vpandn(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2177 
2178   // Or packed integers
2179   void por(XMMRegister dst, XMMRegister src);
2180   void vpor(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2181   void vpor(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2182   void vporq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2183 
2184   // Xor packed integers
2185   void pxor(XMMRegister dst, XMMRegister src);
2186   void vpxor(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2187   void vpxor(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2188   void evpxorq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2189   void evpxorq(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2190 
2191 
2192   // vinserti forms
2193   void vinserti128(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8);
2194   void vinserti128(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8);
2195   void vinserti32x4(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8);
2196   void vinserti32x4(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8);
2197   void vinserti64x4(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8);
2198 
2199   // vinsertf forms
2200   void vinsertf128(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8);
2201   void vinsertf128(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8);
2202   void vinsertf32x4(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8);
2203   void vinsertf32x4(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8);
2204   void vinsertf64x4(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8);
2205   void vinsertf64x4(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8);
2206 
2207   // vextracti forms
2208   void vextracti128(XMMRegister dst, XMMRegister src, uint8_t imm8);
2209   void vextracti128(Address dst, XMMRegister src, uint8_t imm8);
2210   void vextracti32x4(XMMRegister dst, XMMRegister src, uint8_t imm8);
2211   void vextracti32x4(Address dst, XMMRegister src, uint8_t imm8);
2212   void vextracti64x2(XMMRegister dst, XMMRegister src, uint8_t imm8);
2213   void vextracti64x4(XMMRegister dst, XMMRegister src, uint8_t imm8);
2214   void vextracti64x4(Address dst, XMMRegister src, uint8_t imm8);
2215 
2216   // vextractf forms
2217   void vextractf128(XMMRegister dst, XMMRegister src, uint8_t imm8);
2218   void vextractf128(Address dst, XMMRegister src, uint8_t imm8);
2219   void vextractf32x4(XMMRegister dst, XMMRegister src, uint8_t imm8);
2220   void vextractf32x4(Address dst, XMMRegister src, uint8_t imm8);
2221   void vextractf64x2(XMMRegister dst, XMMRegister src, uint8_t imm8);
2222   void vextractf64x4(XMMRegister dst, XMMRegister src, uint8_t imm8);
2223   void vextractf64x4(Address dst, XMMRegister src, uint8_t imm8);
2224 
2225   // xmm/mem sourced byte/word/dword/qword replicate
2226   void vpbroadcastb(XMMRegister dst, XMMRegister src, int vector_len);
2227   void vpbroadcastb(XMMRegister dst, Address src, int vector_len);
2228   void vpbroadcastw(XMMRegister dst, XMMRegister src, int vector_len);
2229   void vpbroadcastw(XMMRegister dst, Address src, int vector_len);
2230   void vpbroadcastd(XMMRegister dst, XMMRegister src, int vector_len);
2231   void vpbroadcastd(XMMRegister dst, Address src, int vector_len);
2232   void vpbroadcastq(XMMRegister dst, XMMRegister src, int vector_len);
2233   void vpbroadcastq(XMMRegister dst, Address src, int vector_len);
2234 
2235   void evbroadcasti64x2(XMMRegister dst, XMMRegister src, int vector_len);
2236   void evbroadcasti64x2(XMMRegister dst, Address src, int vector_len);
2237 
2238   // scalar single/double precision replicate
2239   void vbroadcastss(XMMRegister dst, XMMRegister src, int vector_len);
2240   void vbroadcastss(XMMRegister dst, Address src, int vector_len);
2241   void vbroadcastsd(XMMRegister dst, XMMRegister src, int vector_len);
2242   void vbroadcastsd(XMMRegister dst, Address src, int vector_len);
2243 
2244   // gpr sourced byte/word/dword/qword replicate
2245   void evpbroadcastb(XMMRegister dst, Register src, int vector_len);
2246   void evpbroadcastw(XMMRegister dst, Register src, int vector_len);
2247   void evpbroadcastd(XMMRegister dst, Register src, int vector_len);
2248   void evpbroadcastq(XMMRegister dst, Register src, int vector_len);
2249 
2250   void evpgatherdd(XMMRegister dst, KRegister k1, Address src, int vector_len);
2251 
2252   // Carry-Less Multiplication Quadword
2253   void pclmulqdq(XMMRegister dst, XMMRegister src, int mask);
2254   void vpclmulqdq(XMMRegister dst, XMMRegister nds, XMMRegister src, int mask);
2255   void evpclmulqdq(XMMRegister dst, XMMRegister nds, XMMRegister src, int mask, int vector_len);
2256   // AVX instruction which is used to clear upper 128 bits of YMM registers and
2257   // to avoid transaction penalty between AVX and SSE states. There is no
2258   // penalty if legacy SSE instructions are encoded using VEX prefix because
2259   // they always clear upper 128 bits. It should be used before calling
2260   // runtime code and native libraries.
2261   void vzeroupper();
2262 
2263   // AVX support for vectorized conditional move (float/double). The following two instructions used only coupled.
2264   void cmppd(XMMRegister dst, XMMRegister nds, XMMRegister src, int cop, int vector_len);
2265   void blendvpd(XMMRegister dst, XMMRegister nds, XMMRegister src1, XMMRegister src2, int vector_len);
2266   void cmpps(XMMRegister dst, XMMRegister nds, XMMRegister src, int cop, int vector_len);
2267   void blendvps(XMMRegister dst, XMMRegister nds, XMMRegister src1, XMMRegister src2, int vector_len);
2268   void vpblendd(XMMRegister dst, XMMRegister nds, XMMRegister src, int imm8, int vector_len);
2269 
2270  protected:
2271   // Next instructions require address alignment 16 bytes SSE mode.
2272   // They should be called only from corresponding MacroAssembler instructions.
2273   void andpd(XMMRegister dst, Address src);
2274   void andps(XMMRegister dst, Address src);
2275   void xorpd(XMMRegister dst, Address src);
2276   void xorps(XMMRegister dst, Address src);
2277 
2278 };
2279 
2280 // The Intel x86/Amd64 Assembler attributes: All fields enclosed here are to guide encoding level decisions.
2281 // Specific set functions are for specialized use, else defaults or whatever was supplied to object construction
2282 // are applied.
2283 class InstructionAttr {
2284 public:
2285   InstructionAttr(
2286     int vector_len,     // The length of vector to be applied in encoding - for both AVX and EVEX
2287     bool rex_vex_w,     // Width of data: if 32-bits or less, false, else if 64-bit or specially defined, true
2288     bool legacy_mode,   // Details if either this instruction is conditionally encoded to AVX or earlier if true else possibly EVEX
2289     bool no_reg_mask,   // when true, k0 is used when EVEX encoding is chosen, else embedded_opmask_register_specifier is used
2290     bool uses_vl)       // This instruction may have legacy constraints based on vector length for EVEX
2291     :

2292       _rex_vex_w(rex_vex_w),
2293       _legacy_mode(legacy_mode || UseAVX < 3),

2294       _no_reg_mask(no_reg_mask),
2295       _uses_vl(uses_vl),
2296       _rex_vex_w_reverted(false),

2297       _is_evex_instruction(false),

2298       _is_clear_context(true),
2299       _is_extended_context(false),
2300       _avx_vector_len(vector_len),
2301       _tuple_type(Assembler::EVEX_ETUP),
2302       _input_size_in_bits(Assembler::EVEX_NObit),
2303       _evex_encoding(0),
2304       _embedded_opmask_register_specifier(0), // hard code k0
2305       _current_assembler(NULL) { }


2306 
2307   ~InstructionAttr() {
2308     if (_current_assembler != NULL) {
2309       _current_assembler->clear_attributes();
2310     }
2311     _current_assembler = NULL;
2312   }
2313 
2314 private:

2315   bool _rex_vex_w;

2316   bool _legacy_mode;
2317   bool _no_reg_mask;
2318   bool _uses_vl;
2319   bool _rex_vex_w_reverted;

2320   bool _is_evex_instruction;

2321   bool _is_clear_context;
2322   bool _is_extended_context;
2323   int  _avx_vector_len;
2324   int  _tuple_type;
2325   int  _input_size_in_bits;
2326   int  _evex_encoding;
2327   int _embedded_opmask_register_specifier;
2328 
2329   Assembler *_current_assembler;
2330 
2331 public:
2332   // query functions for field accessors

2333   bool is_rex_vex_w(void) const { return _rex_vex_w; }

2334   bool is_legacy_mode(void) const { return _legacy_mode; }
2335   bool is_no_reg_mask(void) const { return _no_reg_mask; }
2336   bool uses_vl(void) const { return _uses_vl; }
2337   bool is_rex_vex_w_reverted(void) { return _rex_vex_w_reverted; }
2338   bool is_evex_instruction(void) const { return _is_evex_instruction; }
2339   bool is_clear_context(void) const { return _is_clear_context; }
2340   bool is_extended_context(void) const { return _is_extended_context; }
2341   int  get_vector_len(void) const { return _avx_vector_len; }
2342   int  get_tuple_type(void) const { return _tuple_type; }
2343   int  get_input_size(void) const { return _input_size_in_bits; }

2344   int  get_evex_encoding(void) const { return _evex_encoding; }


2345   int  get_embedded_opmask_register_specifier(void) const { return _embedded_opmask_register_specifier; }
2346 
2347   // Set the vector len manually
2348   void set_vector_len(int vector_len) { _avx_vector_len = vector_len; }
2349 
2350   // Set revert rex_vex_w for avx encoding
2351   void set_rex_vex_w_reverted(void) { _rex_vex_w_reverted = true; }
2352 
2353   // Set rex_vex_w based on state
2354   void set_rex_vex_w(bool state) { _rex_vex_w = state; }
2355 
2356   // Set the instruction to be encoded in AVX mode
2357   void set_is_legacy_mode(void) { _legacy_mode = true; }
2358 
2359   // Set the current instuction to be encoded as an EVEX instuction
2360   void set_is_evex_instruction(void) { _is_evex_instruction = true; }
2361 
2362   // Internal encoding data used in compressed immediate offset programming
2363   void set_evex_encoding(int value) { _evex_encoding = value; }
2364 
2365   // Set the Evex.Z field to be used to clear all non directed XMM/YMM/ZMM components
2366   void reset_is_clear_context(void) { _is_clear_context = false; }
2367 
2368   // Map back to current asembler so that we can manage object level assocation
2369   void set_current_assembler(Assembler *current_assembler) { _current_assembler = current_assembler; }
2370 
2371   // Address modifiers used for compressed displacement calculation
2372   void set_address_attributes(int tuple_type, int input_size_in_bits) {
2373     if (VM_Version::supports_evex()) {
2374       _tuple_type = tuple_type;
2375       _input_size_in_bits = input_size_in_bits;
2376     }
2377   }
2378 
2379   // Set embedded opmask register specifier.
2380   void set_embedded_opmask_register_specifier(KRegister mask) {
2381     _embedded_opmask_register_specifier = (*mask).encoding() & 0x7;
2382   }
2383 
2384 };
2385 
2386 #endif // CPU_X86_ASSEMBLER_X86_HPP
--- EOF ---