rev 58404 : 8241042: x86_64: Improve Assembler generation
Reviewed-by: vlivanov

   1 /*
   2  * Copyright (c) 1997, 2019, Oracle and/or its affiliates. All rights reserved.
   3  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
   4  *
   5  * This code is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License version 2 only, as
   7  * published by the Free Software Foundation.
   8  *
   9  * This code is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  12  * version 2 for more details (a copy is included in the LICENSE file that
  13  * accompanied this code).
  14  *
  15  * You should have received a copy of the GNU General Public License version
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  17  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
  18  *
  19  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
  20  * or visit www.oracle.com if you need additional information or have any
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  24 
  25 #ifndef CPU_X86_ASSEMBLER_X86_HPP
  26 #define CPU_X86_ASSEMBLER_X86_HPP
  27 
  28 #include "asm/register.hpp"
  29 #include "runtime/vm_version.hpp"
  30 #include "utilities/powerOfTwo.hpp"
  31 
  32 class BiasedLockingCounters;
  33 
  34 // Contains all the definitions needed for x86 assembly code generation.
  35 
  36 // Calling convention
  37 class Argument {
  38  public:
  39   enum {
  40 #ifdef _LP64
  41 #ifdef _WIN64
  42     n_int_register_parameters_c   = 4, // rcx, rdx, r8, r9 (c_rarg0, c_rarg1, ...)
  43     n_float_register_parameters_c = 4,  // xmm0 - xmm3 (c_farg0, c_farg1, ... )
  44 #else
  45     n_int_register_parameters_c   = 6, // rdi, rsi, rdx, rcx, r8, r9 (c_rarg0, c_rarg1, ...)
  46     n_float_register_parameters_c = 8,  // xmm0 - xmm7 (c_farg0, c_farg1, ... )
  47 #endif // _WIN64
  48     n_int_register_parameters_j   = 6, // j_rarg0, j_rarg1, ...
  49     n_float_register_parameters_j = 8  // j_farg0, j_farg1, ...
  50 #else
  51     n_register_parameters = 0   // 0 registers used to pass arguments
  52 #endif // _LP64
  53   };
  54 };
  55 
  56 
  57 #ifdef _LP64
  58 // Symbolically name the register arguments used by the c calling convention.
  59 // Windows is different from linux/solaris. So much for standards...
  60 
  61 #ifdef _WIN64
  62 
  63 REGISTER_DECLARATION(Register, c_rarg0, rcx);
  64 REGISTER_DECLARATION(Register, c_rarg1, rdx);
  65 REGISTER_DECLARATION(Register, c_rarg2, r8);
  66 REGISTER_DECLARATION(Register, c_rarg3, r9);
  67 
  68 REGISTER_DECLARATION(XMMRegister, c_farg0, xmm0);
  69 REGISTER_DECLARATION(XMMRegister, c_farg1, xmm1);
  70 REGISTER_DECLARATION(XMMRegister, c_farg2, xmm2);
  71 REGISTER_DECLARATION(XMMRegister, c_farg3, xmm3);
  72 
  73 #else
  74 
  75 REGISTER_DECLARATION(Register, c_rarg0, rdi);
  76 REGISTER_DECLARATION(Register, c_rarg1, rsi);
  77 REGISTER_DECLARATION(Register, c_rarg2, rdx);
  78 REGISTER_DECLARATION(Register, c_rarg3, rcx);
  79 REGISTER_DECLARATION(Register, c_rarg4, r8);
  80 REGISTER_DECLARATION(Register, c_rarg5, r9);
  81 
  82 REGISTER_DECLARATION(XMMRegister, c_farg0, xmm0);
  83 REGISTER_DECLARATION(XMMRegister, c_farg1, xmm1);
  84 REGISTER_DECLARATION(XMMRegister, c_farg2, xmm2);
  85 REGISTER_DECLARATION(XMMRegister, c_farg3, xmm3);
  86 REGISTER_DECLARATION(XMMRegister, c_farg4, xmm4);
  87 REGISTER_DECLARATION(XMMRegister, c_farg5, xmm5);
  88 REGISTER_DECLARATION(XMMRegister, c_farg6, xmm6);
  89 REGISTER_DECLARATION(XMMRegister, c_farg7, xmm7);
  90 
  91 #endif // _WIN64
  92 
  93 // Symbolically name the register arguments used by the Java calling convention.
  94 // We have control over the convention for java so we can do what we please.
  95 // What pleases us is to offset the java calling convention so that when
  96 // we call a suitable jni method the arguments are lined up and we don't
  97 // have to do little shuffling. A suitable jni method is non-static and a
  98 // small number of arguments (two fewer args on windows)
  99 //
 100 //        |-------------------------------------------------------|
 101 //        | c_rarg0   c_rarg1  c_rarg2 c_rarg3 c_rarg4 c_rarg5    |
 102 //        |-------------------------------------------------------|
 103 //        | rcx       rdx      r8      r9      rdi*    rsi*       | windows (* not a c_rarg)
 104 //        | rdi       rsi      rdx     rcx     r8      r9         | solaris/linux
 105 //        |-------------------------------------------------------|
 106 //        | j_rarg5   j_rarg0  j_rarg1 j_rarg2 j_rarg3 j_rarg4    |
 107 //        |-------------------------------------------------------|
 108 
 109 REGISTER_DECLARATION(Register, j_rarg0, c_rarg1);
 110 REGISTER_DECLARATION(Register, j_rarg1, c_rarg2);
 111 REGISTER_DECLARATION(Register, j_rarg2, c_rarg3);
 112 // Windows runs out of register args here
 113 #ifdef _WIN64
 114 REGISTER_DECLARATION(Register, j_rarg3, rdi);
 115 REGISTER_DECLARATION(Register, j_rarg4, rsi);
 116 #else
 117 REGISTER_DECLARATION(Register, j_rarg3, c_rarg4);
 118 REGISTER_DECLARATION(Register, j_rarg4, c_rarg5);
 119 #endif /* _WIN64 */
 120 REGISTER_DECLARATION(Register, j_rarg5, c_rarg0);
 121 
 122 REGISTER_DECLARATION(XMMRegister, j_farg0, xmm0);
 123 REGISTER_DECLARATION(XMMRegister, j_farg1, xmm1);
 124 REGISTER_DECLARATION(XMMRegister, j_farg2, xmm2);
 125 REGISTER_DECLARATION(XMMRegister, j_farg3, xmm3);
 126 REGISTER_DECLARATION(XMMRegister, j_farg4, xmm4);
 127 REGISTER_DECLARATION(XMMRegister, j_farg5, xmm5);
 128 REGISTER_DECLARATION(XMMRegister, j_farg6, xmm6);
 129 REGISTER_DECLARATION(XMMRegister, j_farg7, xmm7);
 130 
 131 REGISTER_DECLARATION(Register, rscratch1, r10);  // volatile
 132 REGISTER_DECLARATION(Register, rscratch2, r11);  // volatile
 133 
 134 REGISTER_DECLARATION(Register, r12_heapbase, r12); // callee-saved
 135 REGISTER_DECLARATION(Register, r15_thread, r15); // callee-saved
 136 
 137 #else
 138 // rscratch1 will apear in 32bit code that is dead but of course must compile
 139 // Using noreg ensures if the dead code is incorrectly live and executed it
 140 // will cause an assertion failure
 141 #define rscratch1 noreg
 142 #define rscratch2 noreg
 143 
 144 #endif // _LP64
 145 
 146 // JSR 292
 147 // On x86, the SP does not have to be saved when invoking method handle intrinsics
 148 // or compiled lambda forms. We indicate that by setting rbp_mh_SP_save to noreg.
 149 REGISTER_DECLARATION(Register, rbp_mh_SP_save, noreg);
 150 
 151 // Address is an abstraction used to represent a memory location
 152 // using any of the amd64 addressing modes with one object.
 153 //
 154 // Note: A register location is represented via a Register, not
 155 //       via an address for efficiency & simplicity reasons.
 156 
 157 class ArrayAddress;
 158 
 159 class Address {
 160  public:
 161   enum ScaleFactor {
 162     no_scale = -1,
 163     times_1  =  0,
 164     times_2  =  1,
 165     times_4  =  2,
 166     times_8  =  3,
 167     times_ptr = LP64_ONLY(times_8) NOT_LP64(times_4)
 168   };
 169   static ScaleFactor times(int size) {
 170     assert(size >= 1 && size <= 8 && is_power_of_2(size), "bad scale size");
 171     if (size == 8)  return times_8;
 172     if (size == 4)  return times_4;
 173     if (size == 2)  return times_2;
 174     return times_1;
 175   }
 176   static int scale_size(ScaleFactor scale) {
 177     assert(scale != no_scale, "");
 178     assert(((1 << (int)times_1) == 1 &&
 179             (1 << (int)times_2) == 2 &&
 180             (1 << (int)times_4) == 4 &&
 181             (1 << (int)times_8) == 8), "");
 182     return (1 << (int)scale);
 183   }
 184 
 185  private:
 186   Register         _base;
 187   Register         _index;
 188   XMMRegister      _xmmindex;
 189   ScaleFactor      _scale;
 190   int              _disp;
 191   bool             _isxmmindex;
 192   RelocationHolder _rspec;
 193 
 194   // Easily misused constructors make them private
 195   // %%% can we make these go away?
 196   NOT_LP64(Address(address loc, RelocationHolder spec);)
 197   Address(int disp, address loc, relocInfo::relocType rtype);
 198   Address(int disp, address loc, RelocationHolder spec);
 199 
 200  public:
 201 
 202  int disp() { return _disp; }
 203   // creation
 204   Address()
 205     : _base(noreg),
 206       _index(noreg),
 207       _xmmindex(xnoreg),
 208       _scale(no_scale),
 209       _disp(0),
 210       _isxmmindex(false){
 211   }
 212 
 213   // No default displacement otherwise Register can be implicitly
 214   // converted to 0(Register) which is quite a different animal.
 215 
 216   Address(Register base, int disp)
 217     : _base(base),
 218       _index(noreg),
 219       _xmmindex(xnoreg),
 220       _scale(no_scale),
 221       _disp(disp),
 222       _isxmmindex(false){
 223   }
 224 
 225   Address(Register base, Register index, ScaleFactor scale, int disp = 0)
 226     : _base (base),
 227       _index(index),
 228       _xmmindex(xnoreg),
 229       _scale(scale),
 230       _disp (disp),
 231       _isxmmindex(false) {
 232     assert(!index->is_valid() == (scale == Address::no_scale),
 233            "inconsistent address");
 234   }
 235 
 236   Address(Register base, RegisterOrConstant index, ScaleFactor scale = times_1, int disp = 0)
 237     : _base (base),
 238       _index(index.register_or_noreg()),
 239       _xmmindex(xnoreg),
 240       _scale(scale),
 241       _disp (disp + (index.constant_or_zero() * scale_size(scale))),
 242       _isxmmindex(false){
 243     if (!index.is_register())  scale = Address::no_scale;
 244     assert(!_index->is_valid() == (scale == Address::no_scale),
 245            "inconsistent address");
 246   }
 247 
 248   Address(Register base, XMMRegister index, ScaleFactor scale, int disp = 0)
 249     : _base (base),
 250       _index(noreg),
 251       _xmmindex(index),
 252       _scale(scale),
 253       _disp(disp),
 254       _isxmmindex(true) {
 255       assert(!index->is_valid() == (scale == Address::no_scale),
 256              "inconsistent address");
 257   }
 258 
 259   Address plus_disp(int disp) const {
 260     Address a = (*this);
 261     a._disp += disp;
 262     return a;
 263   }
 264   Address plus_disp(RegisterOrConstant disp, ScaleFactor scale = times_1) const {
 265     Address a = (*this);
 266     a._disp += disp.constant_or_zero() * scale_size(scale);
 267     if (disp.is_register()) {
 268       assert(!a.index()->is_valid(), "competing indexes");
 269       a._index = disp.as_register();
 270       a._scale = scale;
 271     }
 272     return a;
 273   }
 274   bool is_same_address(Address a) const {
 275     // disregard _rspec
 276     return _base == a._base && _disp == a._disp && _index == a._index && _scale == a._scale;
 277   }
 278 
 279   // The following two overloads are used in connection with the
 280   // ByteSize type (see sizes.hpp).  They simplify the use of
 281   // ByteSize'd arguments in assembly code. Note that their equivalent
 282   // for the optimized build are the member functions with int disp
 283   // argument since ByteSize is mapped to an int type in that case.
 284   //
 285   // Note: DO NOT introduce similar overloaded functions for WordSize
 286   // arguments as in the optimized mode, both ByteSize and WordSize
 287   // are mapped to the same type and thus the compiler cannot make a
 288   // distinction anymore (=> compiler errors).
 289 
 290 #ifdef ASSERT
 291   Address(Register base, ByteSize disp)
 292     : _base(base),
 293       _index(noreg),
 294       _xmmindex(xnoreg),
 295       _scale(no_scale),
 296       _disp(in_bytes(disp)),
 297       _isxmmindex(false){
 298   }
 299 
 300   Address(Register base, Register index, ScaleFactor scale, ByteSize disp)
 301     : _base(base),
 302       _index(index),
 303       _xmmindex(xnoreg),
 304       _scale(scale),
 305       _disp(in_bytes(disp)),
 306       _isxmmindex(false){
 307     assert(!index->is_valid() == (scale == Address::no_scale),
 308            "inconsistent address");
 309   }
 310   Address(Register base, RegisterOrConstant index, ScaleFactor scale, ByteSize disp)
 311     : _base (base),
 312       _index(index.register_or_noreg()),
 313       _xmmindex(xnoreg),
 314       _scale(scale),
 315       _disp (in_bytes(disp) + (index.constant_or_zero() * scale_size(scale))),
 316       _isxmmindex(false) {
 317     if (!index.is_register())  scale = Address::no_scale;
 318     assert(!_index->is_valid() == (scale == Address::no_scale),
 319            "inconsistent address");
 320   }
 321 
 322 #endif // ASSERT
 323 
 324   // accessors
 325   bool        uses(Register reg) const { return _base == reg || _index == reg; }
 326   Register    base()             const { return _base;  }
 327   Register    index()            const { return _index; }
 328   XMMRegister xmmindex()         const { return _xmmindex; }
 329   ScaleFactor scale()            const { return _scale; }
 330   int         disp()             const { return _disp;  }
 331   bool        isxmmindex()       const { return _isxmmindex; }
 332 
 333   // Convert the raw encoding form into the form expected by the constructor for
 334   // Address.  An index of 4 (rsp) corresponds to having no index, so convert
 335   // that to noreg for the Address constructor.
 336   static Address make_raw(int base, int index, int scale, int disp, relocInfo::relocType disp_reloc);
 337 
 338   static Address make_array(ArrayAddress);
 339 
 340  private:
 341   bool base_needs_rex() const {
 342     return _base != noreg && _base->encoding() >= 8;
 343   }
 344 
 345   bool index_needs_rex() const {
 346     return _index != noreg &&_index->encoding() >= 8;
 347   }
 348 
 349   bool xmmindex_needs_rex() const {
 350     return _xmmindex != xnoreg && _xmmindex->encoding() >= 8;
 351   }
 352 
 353   relocInfo::relocType reloc() const { return _rspec.type(); }
 354 
 355   friend class Assembler;
 356   friend class MacroAssembler;
 357   friend class LIR_Assembler; // base/index/scale/disp
 358 };
 359 
 360 //
 361 // AddressLiteral has been split out from Address because operands of this type
 362 // need to be treated specially on 32bit vs. 64bit platforms. By splitting it out
 363 // the few instructions that need to deal with address literals are unique and the
 364 // MacroAssembler does not have to implement every instruction in the Assembler
 365 // in order to search for address literals that may need special handling depending
 366 // on the instruction and the platform. As small step on the way to merging i486/amd64
 367 // directories.
 368 //
 369 class AddressLiteral {
 370   friend class ArrayAddress;
 371   RelocationHolder _rspec;
 372   // Typically we use AddressLiterals we want to use their rval
 373   // However in some situations we want the lval (effect address) of the item.
 374   // We provide a special factory for making those lvals.
 375   bool _is_lval;
 376 
 377   // If the target is far we'll need to load the ea of this to
 378   // a register to reach it. Otherwise if near we can do rip
 379   // relative addressing.
 380 
 381   address          _target;
 382 
 383  protected:
 384   // creation
 385   AddressLiteral()
 386     : _is_lval(false),
 387       _target(NULL)
 388   {}
 389 
 390   public:
 391 
 392 
 393   AddressLiteral(address target, relocInfo::relocType rtype);
 394 
 395   AddressLiteral(address target, RelocationHolder const& rspec)
 396     : _rspec(rspec),
 397       _is_lval(false),
 398       _target(target)
 399   {}
 400 
 401   AddressLiteral addr() {
 402     AddressLiteral ret = *this;
 403     ret._is_lval = true;
 404     return ret;
 405   }
 406 
 407 
 408  private:
 409 
 410   address target() { return _target; }
 411   bool is_lval() { return _is_lval; }
 412 
 413   relocInfo::relocType reloc() const { return _rspec.type(); }
 414   const RelocationHolder& rspec() const { return _rspec; }
 415 
 416   friend class Assembler;
 417   friend class MacroAssembler;
 418   friend class Address;
 419   friend class LIR_Assembler;
 420 };
 421 
 422 // Convience classes
 423 class RuntimeAddress: public AddressLiteral {
 424 
 425   public:
 426 
 427   RuntimeAddress(address target) : AddressLiteral(target, relocInfo::runtime_call_type) {}
 428 
 429 };
 430 
 431 class ExternalAddress: public AddressLiteral {
 432  private:
 433   static relocInfo::relocType reloc_for_target(address target) {
 434     // Sometimes ExternalAddress is used for values which aren't
 435     // exactly addresses, like the card table base.
 436     // external_word_type can't be used for values in the first page
 437     // so just skip the reloc in that case.
 438     return external_word_Relocation::can_be_relocated(target) ? relocInfo::external_word_type : relocInfo::none;
 439   }
 440 
 441  public:
 442 
 443   ExternalAddress(address target) : AddressLiteral(target, reloc_for_target(target)) {}
 444 
 445 };
 446 
 447 class InternalAddress: public AddressLiteral {
 448 
 449   public:
 450 
 451   InternalAddress(address target) : AddressLiteral(target, relocInfo::internal_word_type) {}
 452 
 453 };
 454 
 455 // x86 can do array addressing as a single operation since disp can be an absolute
 456 // address amd64 can't. We create a class that expresses the concept but does extra
 457 // magic on amd64 to get the final result
 458 
 459 class ArrayAddress {
 460   private:
 461 
 462   AddressLiteral _base;
 463   Address        _index;
 464 
 465   public:
 466 
 467   ArrayAddress() {};
 468   ArrayAddress(AddressLiteral base, Address index): _base(base), _index(index) {};
 469   AddressLiteral base() { return _base; }
 470   Address index() { return _index; }
 471 
 472 };
 473 
 474 class InstructionAttr;
 475 
 476 // 64-bit refect the fxsave size which is 512 bytes and the new xsave area on EVEX which is another 2176 bytes
 477 // See fxsave and xsave(EVEX enabled) documentation for layout
 478 const int FPUStateSizeInWords = NOT_LP64(27) LP64_ONLY(2688 / wordSize);
 479 
 480 // The Intel x86/Amd64 Assembler: Pure assembler doing NO optimizations on the instruction
 481 // level (e.g. mov rax, 0 is not translated into xor rax, rax!); i.e., what you write
 482 // is what you get. The Assembler is generating code into a CodeBuffer.
 483 
 484 class Assembler : public AbstractAssembler  {
 485   friend class AbstractAssembler; // for the non-virtual hack
 486   friend class LIR_Assembler; // as_Address()
 487   friend class StubGenerator;
 488 
 489  public:
 490   enum Condition {                     // The x86 condition codes used for conditional jumps/moves.
 491     zero          = 0x4,
 492     notZero       = 0x5,
 493     equal         = 0x4,
 494     notEqual      = 0x5,
 495     less          = 0xc,
 496     lessEqual     = 0xe,
 497     greater       = 0xf,
 498     greaterEqual  = 0xd,
 499     below         = 0x2,
 500     belowEqual    = 0x6,
 501     above         = 0x7,
 502     aboveEqual    = 0x3,
 503     overflow      = 0x0,
 504     noOverflow    = 0x1,
 505     carrySet      = 0x2,
 506     carryClear    = 0x3,
 507     negative      = 0x8,
 508     positive      = 0x9,
 509     parity        = 0xa,
 510     noParity      = 0xb
 511   };
 512 
 513   enum Prefix {
 514     // segment overrides
 515     CS_segment = 0x2e,
 516     SS_segment = 0x36,
 517     DS_segment = 0x3e,
 518     ES_segment = 0x26,
 519     FS_segment = 0x64,
 520     GS_segment = 0x65,
 521 
 522     REX        = 0x40,
 523 
 524     REX_B      = 0x41,
 525     REX_X      = 0x42,
 526     REX_XB     = 0x43,
 527     REX_R      = 0x44,
 528     REX_RB     = 0x45,
 529     REX_RX     = 0x46,
 530     REX_RXB    = 0x47,
 531 
 532     REX_W      = 0x48,
 533 
 534     REX_WB     = 0x49,
 535     REX_WX     = 0x4A,
 536     REX_WXB    = 0x4B,
 537     REX_WR     = 0x4C,
 538     REX_WRB    = 0x4D,
 539     REX_WRX    = 0x4E,
 540     REX_WRXB   = 0x4F,
 541 
 542     VEX_3bytes = 0xC4,
 543     VEX_2bytes = 0xC5,
 544     EVEX_4bytes = 0x62,
 545     Prefix_EMPTY = 0x0
 546   };
 547 
 548   enum VexPrefix {
 549     VEX_B = 0x20,
 550     VEX_X = 0x40,
 551     VEX_R = 0x80,
 552     VEX_W = 0x80
 553   };
 554 
 555   enum ExexPrefix {
 556     EVEX_F  = 0x04,
 557     EVEX_V  = 0x08,
 558     EVEX_Rb = 0x10,
 559     EVEX_X  = 0x40,
 560     EVEX_Z  = 0x80
 561   };
 562 
 563   enum VexSimdPrefix {
 564     VEX_SIMD_NONE = 0x0,
 565     VEX_SIMD_66   = 0x1,
 566     VEX_SIMD_F3   = 0x2,
 567     VEX_SIMD_F2   = 0x3
 568   };
 569 
 570   enum VexOpcode {
 571     VEX_OPCODE_NONE  = 0x0,
 572     VEX_OPCODE_0F    = 0x1,
 573     VEX_OPCODE_0F_38 = 0x2,
 574     VEX_OPCODE_0F_3A = 0x3,
 575     VEX_OPCODE_MASK  = 0x1F
 576   };
 577 
 578   enum AvxVectorLen {
 579     AVX_128bit = 0x0,
 580     AVX_256bit = 0x1,
 581     AVX_512bit = 0x2,
 582     AVX_NoVec  = 0x4
 583   };
 584 
 585   enum EvexTupleType {
 586     EVEX_FV   = 0,
 587     EVEX_HV   = 4,
 588     EVEX_FVM  = 6,
 589     EVEX_T1S  = 7,
 590     EVEX_T1F  = 11,
 591     EVEX_T2   = 13,
 592     EVEX_T4   = 15,
 593     EVEX_T8   = 17,
 594     EVEX_HVM  = 18,
 595     EVEX_QVM  = 19,
 596     EVEX_OVM  = 20,
 597     EVEX_M128 = 21,
 598     EVEX_DUP  = 22,
 599     EVEX_ETUP = 23
 600   };
 601 
 602   enum EvexInputSizeInBits {
 603     EVEX_8bit  = 0,
 604     EVEX_16bit = 1,
 605     EVEX_32bit = 2,
 606     EVEX_64bit = 3,
 607     EVEX_NObit = 4
 608   };
 609 
 610   enum WhichOperand {
 611     // input to locate_operand, and format code for relocations
 612     imm_operand  = 0,            // embedded 32-bit|64-bit immediate operand
 613     disp32_operand = 1,          // embedded 32-bit displacement or address
 614     call32_operand = 2,          // embedded 32-bit self-relative displacement
 615 #ifndef _LP64
 616     _WhichOperand_limit = 3
 617 #else
 618      narrow_oop_operand = 3,     // embedded 32-bit immediate narrow oop
 619     _WhichOperand_limit = 4
 620 #endif
 621   };
 622 
 623   enum ComparisonPredicate {
 624     eq = 0,
 625     lt = 1,
 626     le = 2,
 627     _false = 3,
 628     neq = 4,
 629     nlt = 5,
 630     nle = 6,
 631     _true = 7
 632   };
 633 
 634   //---<  calculate length of instruction  >---
 635   // As instruction size can't be found out easily on x86/x64,
 636   // we just use '4' for len and maxlen.
 637   // instruction must start at passed address
 638   static unsigned int instr_len(unsigned char *instr) { return 4; }
 639 
 640   //---<  longest instructions  >---
 641   // Max instruction length is not specified in architecture documentation.
 642   // We could use a "safe enough" estimate (15), but just default to
 643   // instruction length guess from above.
 644   static unsigned int instr_maxlen() { return 4; }
 645 
 646   // NOTE: The general philopsophy of the declarations here is that 64bit versions
 647   // of instructions are freely declared without the need for wrapping them an ifdef.
 648   // (Some dangerous instructions are ifdef's out of inappropriate jvm's.)
 649   // In the .cpp file the implementations are wrapped so that they are dropped out
 650   // of the resulting jvm. This is done mostly to keep the footprint of MINIMAL
 651   // to the size it was prior to merging up the 32bit and 64bit assemblers.
 652   //
 653   // This does mean you'll get a linker/runtime error if you use a 64bit only instruction
 654   // in a 32bit vm. This is somewhat unfortunate but keeps the ifdef noise down.
 655 
 656 private:
 657 
 658   bool _legacy_mode_bw;
 659   bool _legacy_mode_dq;
 660   bool _legacy_mode_vl;
 661   bool _legacy_mode_vlbw;
 662   bool _is_managed;
 663 
 664   class InstructionAttr *_attributes;
 665 
 666   // 64bit prefixes
 667   int prefix_and_encode(int reg_enc, bool byteinst = false);
 668   int prefixq_and_encode(int reg_enc);
 669 
 670   int prefix_and_encode(int dst_enc, int src_enc) {
 671     return prefix_and_encode(dst_enc, false, src_enc, false);
 672   }
 673   int prefix_and_encode(int dst_enc, bool dst_is_byte, int src_enc, bool src_is_byte);
 674   int prefixq_and_encode(int dst_enc, int src_enc);
 675 

 676   void prefix(Register reg);
 677   void prefix(Register dst, Register src, Prefix p);
 678   void prefix(Register dst, Address adr, Prefix p);
 679   void prefix(Address adr);
 680   void prefixq(Address adr);
 681 

 682   void prefix(Address adr, Register reg,  bool byteinst = false);
 683   void prefix(Address adr, XMMRegister reg);
 684   void prefixq(Address adr, Register reg);
 685   void prefixq(Address adr, XMMRegister reg);
 686 
 687   void prefetch_prefix(Address src);





 688 
 689   void rex_prefix(Address adr, XMMRegister xreg,
 690                   VexSimdPrefix pre, VexOpcode opc, bool rex_w);
 691   int  rex_prefix_and_encode(int dst_enc, int src_enc,
 692                              VexSimdPrefix pre, VexOpcode opc, bool rex_w);
 693 
 694   void vex_prefix(bool vex_r, bool vex_b, bool vex_x, int nds_enc, VexSimdPrefix pre, VexOpcode opc);
 695 
 696   void evex_prefix(bool vex_r, bool vex_b, bool vex_x, bool evex_r, bool evex_v,
 697                    int nds_enc, VexSimdPrefix pre, VexOpcode opc);
 698 
 699   void vex_prefix(Address adr, int nds_enc, int xreg_enc,
 700                   VexSimdPrefix pre, VexOpcode opc,
 701                   InstructionAttr *attributes);
 702 
 703   int  vex_prefix_and_encode(int dst_enc, int nds_enc, int src_enc,
 704                              VexSimdPrefix pre, VexOpcode opc,
 705                              InstructionAttr *attributes);
 706 
 707   void simd_prefix(XMMRegister xreg, XMMRegister nds, Address adr, VexSimdPrefix pre,
 708                    VexOpcode opc, InstructionAttr *attributes);
 709 
 710   int simd_prefix_and_encode(XMMRegister dst, XMMRegister nds, XMMRegister src, VexSimdPrefix pre,
 711                              VexOpcode opc, InstructionAttr *attributes);
 712 
 713   // Helper functions for groups of instructions
 714   void emit_arith_b(int op1, int op2, Register dst, int imm8);
 715 
 716   void emit_arith(int op1, int op2, Register dst, int32_t imm32);
 717   // Force generation of a 4 byte immediate value even if it fits into 8bit
 718   void emit_arith_imm32(int op1, int op2, Register dst, int32_t imm32);
 719   void emit_arith(int op1, int op2, Register dst, Register src);
 720 
 721   bool emit_compressed_disp_byte(int &disp);
 722 
 723   void emit_operand(Register reg,
 724                     Register base, Register index, Address::ScaleFactor scale,
 725                     int disp,
 726                     RelocationHolder const& rspec,
 727                     int rip_relative_correction = 0);
 728 
 729   void emit_operand(XMMRegister reg, Register base, XMMRegister index,
 730                     Address::ScaleFactor scale,
 731                     int disp, RelocationHolder const& rspec);
 732 
 733   void emit_operand(Register reg, Address adr, int rip_relative_correction = 0);
 734 
 735   // operands that only take the original 32bit registers
 736   void emit_operand32(Register reg, Address adr);
 737 
 738   void emit_operand(XMMRegister reg,
 739                     Register base, Register index, Address::ScaleFactor scale,
 740                     int disp,
 741                     RelocationHolder const& rspec);
 742 
 743   void emit_operand(XMMRegister reg, Address adr);
 744 
 745   void emit_operand(MMXRegister reg, Address adr);
 746 
 747   // workaround gcc (3.2.1-7) bug
 748   void emit_operand(Address adr, MMXRegister reg);
 749 
 750 
 751   // Immediate-to-memory forms
 752   void emit_arith_operand(int op1, Register rm, Address adr, int32_t imm32);
 753 
 754   void emit_farith(int b1, int b2, int i);
 755 
 756 
 757  protected:
 758   #ifdef ASSERT
 759   void check_relocation(RelocationHolder const& rspec, int format);
 760   #endif
 761 
 762   void emit_data(jint data, relocInfo::relocType    rtype, int format);
 763   void emit_data(jint data, RelocationHolder const& rspec, int format);
 764   void emit_data64(jlong data, relocInfo::relocType rtype, int format = 0);
 765   void emit_data64(jlong data, RelocationHolder const& rspec, int format = 0);
 766 
 767   bool reachable(AddressLiteral adr) NOT_LP64({ return true;});
 768 
 769   // These are all easily abused and hence protected
 770 
 771   // 32BIT ONLY SECTION
 772 #ifndef _LP64
 773   // Make these disappear in 64bit mode since they would never be correct
 774   void cmp_literal32(Register src1, int32_t imm32, RelocationHolder const& rspec);   // 32BIT ONLY
 775   void cmp_literal32(Address src1, int32_t imm32, RelocationHolder const& rspec);    // 32BIT ONLY
 776 
 777   void mov_literal32(Register dst, int32_t imm32, RelocationHolder const& rspec);    // 32BIT ONLY
 778   void mov_literal32(Address dst, int32_t imm32, RelocationHolder const& rspec);     // 32BIT ONLY
 779 
 780   void push_literal32(int32_t imm32, RelocationHolder const& rspec);                 // 32BIT ONLY
 781 #else
 782   // 64BIT ONLY SECTION
 783   void mov_literal64(Register dst, intptr_t imm64, RelocationHolder const& rspec);   // 64BIT ONLY
 784 
 785   void cmp_narrow_oop(Register src1, int32_t imm32, RelocationHolder const& rspec);
 786   void cmp_narrow_oop(Address src1, int32_t imm32, RelocationHolder const& rspec);
 787 
 788   void mov_narrow_oop(Register dst, int32_t imm32, RelocationHolder const& rspec);
 789   void mov_narrow_oop(Address dst, int32_t imm32, RelocationHolder const& rspec);
 790 #endif // _LP64
 791 
 792   // These are unique in that we are ensured by the caller that the 32bit
 793   // relative in these instructions will always be able to reach the potentially
 794   // 64bit address described by entry. Since they can take a 64bit address they
 795   // don't have the 32 suffix like the other instructions in this class.
 796 
 797   void call_literal(address entry, RelocationHolder const& rspec);
 798   void jmp_literal(address entry, RelocationHolder const& rspec);
 799 
 800   // Avoid using directly section
 801   // Instructions in this section are actually usable by anyone without danger
 802   // of failure but have performance issues that are addressed my enhanced
 803   // instructions which will do the proper thing base on the particular cpu.
 804   // We protect them because we don't trust you...
 805 
 806   // Don't use next inc() and dec() methods directly. INC & DEC instructions
 807   // could cause a partial flag stall since they don't set CF flag.
 808   // Use MacroAssembler::decrement() & MacroAssembler::increment() methods
 809   // which call inc() & dec() or add() & sub() in accordance with
 810   // the product flag UseIncDec value.
 811 
 812   void decl(Register dst);
 813   void decl(Address dst);
 814   void decq(Register dst);
 815   void decq(Address dst);
 816 
 817   void incl(Register dst);
 818   void incl(Address dst);
 819   void incq(Register dst);
 820   void incq(Address dst);
 821 
 822   // New cpus require use of movsd and movss to avoid partial register stall
 823   // when loading from memory. But for old Opteron use movlpd instead of movsd.
 824   // The selection is done in MacroAssembler::movdbl() and movflt().
 825 
 826   // Move Scalar Single-Precision Floating-Point Values
 827   void movss(XMMRegister dst, Address src);
 828   void movss(XMMRegister dst, XMMRegister src);
 829   void movss(Address dst, XMMRegister src);
 830 
 831   // Move Scalar Double-Precision Floating-Point Values
 832   void movsd(XMMRegister dst, Address src);
 833   void movsd(XMMRegister dst, XMMRegister src);
 834   void movsd(Address dst, XMMRegister src);
 835   void movlpd(XMMRegister dst, Address src);
 836 
 837   // New cpus require use of movaps and movapd to avoid partial register stall
 838   // when moving between registers.
 839   void movaps(XMMRegister dst, XMMRegister src);
 840   void movapd(XMMRegister dst, XMMRegister src);
 841 
 842   // End avoid using directly
 843 
 844 
 845   // Instruction prefixes
 846   void prefix(Prefix p);
 847 
 848   public:
 849 
 850   // Creation
 851   Assembler(CodeBuffer* code) : AbstractAssembler(code) {
 852     init_attributes();
 853   }
 854 
 855   // Decoding
 856   static address locate_operand(address inst, WhichOperand which);
 857   static address locate_next_instruction(address inst);
 858 
 859   // Utilities
 860   static bool is_polling_page_far() NOT_LP64({ return false;});
 861   static bool query_compressed_disp_byte(int disp, bool is_evex_inst, int vector_len,
 862                                          int cur_tuple_type, int in_size_in_bits, int cur_encoding);
 863 
 864   // Generic instructions
 865   // Does 32bit or 64bit as needed for the platform. In some sense these
 866   // belong in macro assembler but there is no need for both varieties to exist
 867 
 868   void init_attributes(void) {
 869     _legacy_mode_bw = (VM_Version::supports_avx512bw() == false);
 870     _legacy_mode_dq = (VM_Version::supports_avx512dq() == false);
 871     _legacy_mode_vl = (VM_Version::supports_avx512vl() == false);
 872     _legacy_mode_vlbw = (VM_Version::supports_avx512vlbw() == false);
 873     _is_managed = false;
 874     _attributes = NULL;
 875   }
 876 
 877   void set_attributes(InstructionAttr *attributes) { _attributes = attributes; }
 878   void clear_attributes(void) { _attributes = NULL; }
 879 
 880   void set_managed(void) { _is_managed = true; }
 881   void clear_managed(void) { _is_managed = false; }
 882   bool is_managed(void) { return _is_managed; }


 883 
 884   void lea(Register dst, Address src);
 885 
 886   void mov(Register dst, Register src);
 887 
 888 #ifdef _LP64
 889   // support caching the result of some routines
 890 
 891   // must be called before pusha(), popa(), vzeroupper() - checked with asserts
 892   static void precompute_instructions();
 893 
 894   void pusha_uncached();
 895   void popa_uncached();
 896 #endif
 897   void vzeroupper_uncached();
 898 
 899   void pusha();
 900   void popa();
 901 
 902   void pushf();
 903   void popf();
 904 
 905   void push(int32_t imm32);
 906 
 907   void push(Register src);
 908 
 909   void pop(Register dst);
 910 
 911   // These are dummies to prevent surprise implicit conversions to Register
 912   void push(void* v);
 913   void pop(void* v);
 914 
 915   // These do register sized moves/scans
 916   void rep_mov();
 917   void rep_stos();
 918   void rep_stosb();
 919   void repne_scan();
 920 #ifdef _LP64
 921   void repne_scanl();
 922 #endif
 923 
 924   // Vanilla instructions in lexical order
 925 
 926   void adcl(Address dst, int32_t imm32);
 927   void adcl(Address dst, Register src);
 928   void adcl(Register dst, int32_t imm32);
 929   void adcl(Register dst, Address src);
 930   void adcl(Register dst, Register src);
 931 
 932   void adcq(Register dst, int32_t imm32);
 933   void adcq(Register dst, Address src);
 934   void adcq(Register dst, Register src);
 935 
 936   void addb(Address dst, int imm8);
 937   void addw(Address dst, int imm16);
 938 
 939   void addl(Address dst, int32_t imm32);
 940   void addl(Address dst, Register src);
 941   void addl(Register dst, int32_t imm32);
 942   void addl(Register dst, Address src);
 943   void addl(Register dst, Register src);
 944 
 945   void addq(Address dst, int32_t imm32);
 946   void addq(Address dst, Register src);
 947   void addq(Register dst, int32_t imm32);
 948   void addq(Register dst, Address src);
 949   void addq(Register dst, Register src);
 950 
 951 #ifdef _LP64
 952  //Add Unsigned Integers with Carry Flag
 953   void adcxq(Register dst, Register src);
 954 
 955  //Add Unsigned Integers with Overflow Flag
 956   void adoxq(Register dst, Register src);
 957 #endif
 958 
 959   void addr_nop_4();
 960   void addr_nop_5();
 961   void addr_nop_7();
 962   void addr_nop_8();
 963 
 964   // Add Scalar Double-Precision Floating-Point Values
 965   void addsd(XMMRegister dst, Address src);
 966   void addsd(XMMRegister dst, XMMRegister src);
 967 
 968   // Add Scalar Single-Precision Floating-Point Values
 969   void addss(XMMRegister dst, Address src);
 970   void addss(XMMRegister dst, XMMRegister src);
 971 
 972   // AES instructions
 973   void aesdec(XMMRegister dst, Address src);
 974   void aesdec(XMMRegister dst, XMMRegister src);
 975   void aesdeclast(XMMRegister dst, Address src);
 976   void aesdeclast(XMMRegister dst, XMMRegister src);
 977   void aesenc(XMMRegister dst, Address src);
 978   void aesenc(XMMRegister dst, XMMRegister src);
 979   void aesenclast(XMMRegister dst, Address src);
 980   void aesenclast(XMMRegister dst, XMMRegister src);
 981   // Vector AES instructions
 982   void vaesenc(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
 983   void vaesenclast(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
 984   void vaesdec(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
 985   void vaesdeclast(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
 986 
 987   void andl(Address  dst, int32_t imm32);
 988   void andl(Register dst, int32_t imm32);
 989   void andl(Register dst, Address src);
 990   void andl(Register dst, Register src);
 991 
 992   void andq(Address  dst, int32_t imm32);
 993   void andq(Register dst, int32_t imm32);
 994   void andq(Register dst, Address src);
 995   void andq(Register dst, Register src);
 996 
 997   // BMI instructions
 998   void andnl(Register dst, Register src1, Register src2);
 999   void andnl(Register dst, Register src1, Address src2);
1000   void andnq(Register dst, Register src1, Register src2);
1001   void andnq(Register dst, Register src1, Address src2);
1002 
1003   void blsil(Register dst, Register src);
1004   void blsil(Register dst, Address src);
1005   void blsiq(Register dst, Register src);
1006   void blsiq(Register dst, Address src);
1007 
1008   void blsmskl(Register dst, Register src);
1009   void blsmskl(Register dst, Address src);
1010   void blsmskq(Register dst, Register src);
1011   void blsmskq(Register dst, Address src);
1012 
1013   void blsrl(Register dst, Register src);
1014   void blsrl(Register dst, Address src);
1015   void blsrq(Register dst, Register src);
1016   void blsrq(Register dst, Address src);
1017 
1018   void bsfl(Register dst, Register src);
1019   void bsrl(Register dst, Register src);
1020 
1021 #ifdef _LP64
1022   void bsfq(Register dst, Register src);
1023   void bsrq(Register dst, Register src);
1024 #endif
1025 
1026   void bswapl(Register reg);
1027 
1028   void bswapq(Register reg);
1029 
1030   void call(Label& L, relocInfo::relocType rtype);
1031   void call(Register reg);  // push pc; pc <- reg
1032   void call(Address adr);   // push pc; pc <- adr
1033 
1034   void cdql();
1035 
1036   void cdqq();
1037 
1038   void cld();
1039 
1040   void clflush(Address adr);
1041   void clflushopt(Address adr);
1042   void clwb(Address adr);
1043 
1044   void cmovl(Condition cc, Register dst, Register src);
1045   void cmovl(Condition cc, Register dst, Address src);
1046 
1047   void cmovq(Condition cc, Register dst, Register src);
1048   void cmovq(Condition cc, Register dst, Address src);
1049 
1050 
1051   void cmpb(Address dst, int imm8);
1052 
1053   void cmpl(Address dst, int32_t imm32);
1054 
1055   void cmpl(Register dst, int32_t imm32);
1056   void cmpl(Register dst, Register src);
1057   void cmpl(Register dst, Address src);
1058 
1059   void cmpq(Address dst, int32_t imm32);
1060   void cmpq(Address dst, Register src);
1061 
1062   void cmpq(Register dst, int32_t imm32);
1063   void cmpq(Register dst, Register src);
1064   void cmpq(Register dst, Address src);
1065 
1066   // these are dummies used to catch attempting to convert NULL to Register
1067   void cmpl(Register dst, void* junk); // dummy
1068   void cmpq(Register dst, void* junk); // dummy
1069 
1070   void cmpw(Address dst, int imm16);
1071 
1072   void cmpxchg8 (Address adr);
1073 
1074   void cmpxchgb(Register reg, Address adr);
1075   void cmpxchgl(Register reg, Address adr);
1076 
1077   void cmpxchgq(Register reg, Address adr);
1078 
1079   // Ordered Compare Scalar Double-Precision Floating-Point Values and set EFLAGS
1080   void comisd(XMMRegister dst, Address src);
1081   void comisd(XMMRegister dst, XMMRegister src);
1082 
1083   // Ordered Compare Scalar Single-Precision Floating-Point Values and set EFLAGS
1084   void comiss(XMMRegister dst, Address src);
1085   void comiss(XMMRegister dst, XMMRegister src);
1086 
1087   // Identify processor type and features
1088   void cpuid();
1089 
1090   // CRC32C
1091   void crc32(Register crc, Register v, int8_t sizeInBytes);
1092   void crc32(Register crc, Address adr, int8_t sizeInBytes);
1093 
1094   // Convert Scalar Double-Precision Floating-Point Value to Scalar Single-Precision Floating-Point Value
1095   void cvtsd2ss(XMMRegister dst, XMMRegister src);
1096   void cvtsd2ss(XMMRegister dst, Address src);
1097 
1098   // Convert Doubleword Integer to Scalar Double-Precision Floating-Point Value
1099   void cvtsi2sdl(XMMRegister dst, Register src);
1100   void cvtsi2sdl(XMMRegister dst, Address src);
1101   void cvtsi2sdq(XMMRegister dst, Register src);
1102   void cvtsi2sdq(XMMRegister dst, Address src);
1103 
1104   // Convert Doubleword Integer to Scalar Single-Precision Floating-Point Value
1105   void cvtsi2ssl(XMMRegister dst, Register src);
1106   void cvtsi2ssl(XMMRegister dst, Address src);
1107   void cvtsi2ssq(XMMRegister dst, Register src);
1108   void cvtsi2ssq(XMMRegister dst, Address src);
1109 
1110   // Convert Packed Signed Doubleword Integers to Packed Double-Precision Floating-Point Value
1111   void cvtdq2pd(XMMRegister dst, XMMRegister src);
1112 
1113   // Convert Packed Signed Doubleword Integers to Packed Single-Precision Floating-Point Value
1114   void cvtdq2ps(XMMRegister dst, XMMRegister src);
1115 
1116   // Convert Scalar Single-Precision Floating-Point Value to Scalar Double-Precision Floating-Point Value
1117   void cvtss2sd(XMMRegister dst, XMMRegister src);
1118   void cvtss2sd(XMMRegister dst, Address src);
1119 
1120   // Convert with Truncation Scalar Double-Precision Floating-Point Value to Doubleword Integer
1121   void cvttsd2sil(Register dst, Address src);
1122   void cvttsd2sil(Register dst, XMMRegister src);
1123   void cvttsd2siq(Register dst, Address src);
1124   void cvttsd2siq(Register dst, XMMRegister src);
1125 
1126   // Convert with Truncation Scalar Single-Precision Floating-Point Value to Doubleword Integer
1127   void cvttss2sil(Register dst, XMMRegister src);
1128   void cvttss2siq(Register dst, XMMRegister src);
1129 
1130   void cvttpd2dq(XMMRegister dst, XMMRegister src);
1131 
1132   //Abs of packed Integer values
1133   void pabsb(XMMRegister dst, XMMRegister src);
1134   void pabsw(XMMRegister dst, XMMRegister src);
1135   void pabsd(XMMRegister dst, XMMRegister src);
1136   void vpabsb(XMMRegister dst, XMMRegister src, int vector_len);
1137   void vpabsw(XMMRegister dst, XMMRegister src, int vector_len);
1138   void vpabsd(XMMRegister dst, XMMRegister src, int vector_len);
1139   void evpabsq(XMMRegister dst, XMMRegister src, int vector_len);
1140 
1141   // Divide Scalar Double-Precision Floating-Point Values
1142   void divsd(XMMRegister dst, Address src);
1143   void divsd(XMMRegister dst, XMMRegister src);
1144 
1145   // Divide Scalar Single-Precision Floating-Point Values
1146   void divss(XMMRegister dst, Address src);
1147   void divss(XMMRegister dst, XMMRegister src);
1148 
1149   void emms();
1150 
1151 #ifndef _LP64
1152   void fabs();
1153 
1154   void fadd(int i);
1155 
1156   void fadd_d(Address src);
1157   void fadd_s(Address src);
1158 
1159   // "Alternate" versions of x87 instructions place result down in FPU
1160   // stack instead of on TOS
1161 
1162   void fadda(int i); // "alternate" fadd
1163   void faddp(int i = 1);
1164 
1165   void fchs();
1166 
1167   void fcom(int i);
1168 
1169   void fcomp(int i = 1);
1170   void fcomp_d(Address src);
1171   void fcomp_s(Address src);
1172 
1173   void fcompp();
1174 
1175   void fcos();
1176 
1177   void fdecstp();
1178 
1179   void fdiv(int i);
1180   void fdiv_d(Address src);
1181   void fdivr_s(Address src);
1182   void fdiva(int i);  // "alternate" fdiv
1183   void fdivp(int i = 1);
1184 
1185   void fdivr(int i);
1186   void fdivr_d(Address src);
1187   void fdiv_s(Address src);
1188 
1189   void fdivra(int i); // "alternate" reversed fdiv
1190 
1191   void fdivrp(int i = 1);
1192 
1193   void ffree(int i = 0);
1194 
1195   void fild_d(Address adr);
1196   void fild_s(Address adr);
1197 
1198   void fincstp();
1199 
1200   void finit();
1201 
1202   void fist_s (Address adr);
1203   void fistp_d(Address adr);
1204   void fistp_s(Address adr);
1205 
1206   void fld1();
1207 
1208   void fld_d(Address adr);
1209   void fld_s(Address adr);
1210   void fld_s(int index);
1211   void fld_x(Address adr);  // extended-precision (80-bit) format
1212 
1213   void fldcw(Address src);
1214 
1215   void fldenv(Address src);
1216 
1217   void fldlg2();
1218 
1219   void fldln2();
1220 
1221   void fldz();
1222 
1223   void flog();
1224   void flog10();
1225 
1226   void fmul(int i);
1227 
1228   void fmul_d(Address src);
1229   void fmul_s(Address src);
1230 
1231   void fmula(int i);  // "alternate" fmul
1232 
1233   void fmulp(int i = 1);
1234 
1235   void fnsave(Address dst);
1236 
1237   void fnstcw(Address src);
1238 
1239   void fnstsw_ax();
1240 
1241   void fprem();
1242   void fprem1();
1243 
1244   void frstor(Address src);
1245 
1246   void fsin();
1247 
1248   void fsqrt();
1249 
1250   void fst_d(Address adr);
1251   void fst_s(Address adr);
1252 
1253   void fstp_d(Address adr);
1254   void fstp_d(int index);
1255   void fstp_s(Address adr);
1256   void fstp_x(Address adr); // extended-precision (80-bit) format
1257 
1258   void fsub(int i);
1259   void fsub_d(Address src);
1260   void fsub_s(Address src);
1261 
1262   void fsuba(int i);  // "alternate" fsub
1263 
1264   void fsubp(int i = 1);
1265 
1266   void fsubr(int i);
1267   void fsubr_d(Address src);
1268   void fsubr_s(Address src);
1269 
1270   void fsubra(int i); // "alternate" reversed fsub
1271 
1272   void fsubrp(int i = 1);
1273 
1274   void ftan();
1275 
1276   void ftst();
1277 
1278   void fucomi(int i = 1);
1279   void fucomip(int i = 1);
1280 
1281   void fwait();
1282 
1283   void fxch(int i = 1);
1284 
1285   void fyl2x();
1286   void frndint();
1287   void f2xm1();
1288   void fldl2e();
1289 #endif // !_LP64
1290 
1291   void fxrstor(Address src);
1292   void xrstor(Address src);
1293 
1294   void fxsave(Address dst);
1295   void xsave(Address dst);
1296 
1297   void hlt();
1298 
1299   void idivl(Register src);
1300   void divl(Register src); // Unsigned division
1301 
1302 #ifdef _LP64
1303   void idivq(Register src);
1304 #endif
1305 
1306   void imull(Register src);
1307   void imull(Register dst, Register src);
1308   void imull(Register dst, Register src, int value);
1309   void imull(Register dst, Address src);
1310 
1311 #ifdef _LP64
1312   void imulq(Register dst, Register src);
1313   void imulq(Register dst, Register src, int value);
1314   void imulq(Register dst, Address src);
1315 #endif
1316 
1317   // jcc is the generic conditional branch generator to run-
1318   // time routines, jcc is used for branches to labels. jcc
1319   // takes a branch opcode (cc) and a label (L) and generates
1320   // either a backward branch or a forward branch and links it
1321   // to the label fixup chain. Usage:
1322   //
1323   // Label L;      // unbound label
1324   // jcc(cc, L);   // forward branch to unbound label
1325   // bind(L);      // bind label to the current pc
1326   // jcc(cc, L);   // backward branch to bound label
1327   // bind(L);      // illegal: a label may be bound only once
1328   //
1329   // Note: The same Label can be used for forward and backward branches
1330   // but it may be bound only once.
1331 
1332   void jcc(Condition cc, Label& L, bool maybe_short = true);
1333 
1334   // Conditional jump to a 8-bit offset to L.
1335   // WARNING: be very careful using this for forward jumps.  If the label is
1336   // not bound within an 8-bit offset of this instruction, a run-time error
1337   // will occur.
1338 
1339   // Use macro to record file and line number.
1340   #define jccb(cc, L) jccb_0(cc, L, __FILE__, __LINE__)
1341 
1342   void jccb_0(Condition cc, Label& L, const char* file, int line);
1343 
1344   void jmp(Address entry);    // pc <- entry
1345 
1346   // Label operations & relative jumps (PPUM Appendix D)
1347   void jmp(Label& L, bool maybe_short = true);   // unconditional jump to L
1348 
1349   void jmp(Register entry); // pc <- entry
1350 
1351   // Unconditional 8-bit offset jump to L.
1352   // WARNING: be very careful using this for forward jumps.  If the label is
1353   // not bound within an 8-bit offset of this instruction, a run-time error
1354   // will occur.
1355 
1356   // Use macro to record file and line number.
1357   #define jmpb(L) jmpb_0(L, __FILE__, __LINE__)
1358 
1359   void jmpb_0(Label& L, const char* file, int line);
1360 
1361   void ldmxcsr( Address src );
1362 
1363   void leal(Register dst, Address src);
1364 
1365   void leaq(Register dst, Address src);
1366 
1367   void lfence();
1368 
1369   void lock();
1370 
1371   void lzcntl(Register dst, Register src);
1372 
1373 #ifdef _LP64
1374   void lzcntq(Register dst, Register src);
1375 #endif
1376 
1377   enum Membar_mask_bits {
1378     StoreStore = 1 << 3,
1379     LoadStore  = 1 << 2,
1380     StoreLoad  = 1 << 1,
1381     LoadLoad   = 1 << 0
1382   };
1383 
1384   // Serializes memory and blows flags
1385   void membar(Membar_mask_bits order_constraint) {
1386     // We only have to handle StoreLoad
1387     if (order_constraint & StoreLoad) {
1388       // All usable chips support "locked" instructions which suffice
1389       // as barriers, and are much faster than the alternative of
1390       // using cpuid instruction. We use here a locked add [esp-C],0.
1391       // This is conveniently otherwise a no-op except for blowing
1392       // flags, and introducing a false dependency on target memory
1393       // location. We can't do anything with flags, but we can avoid
1394       // memory dependencies in the current method by locked-adding
1395       // somewhere else on the stack. Doing [esp+C] will collide with
1396       // something on stack in current method, hence we go for [esp-C].
1397       // It is convenient since it is almost always in data cache, for
1398       // any small C.  We need to step back from SP to avoid data
1399       // dependencies with other things on below SP (callee-saves, for
1400       // example). Without a clear way to figure out the minimal safe
1401       // distance from SP, it makes sense to step back the complete
1402       // cache line, as this will also avoid possible second-order effects
1403       // with locked ops against the cache line. Our choice of offset
1404       // is bounded by x86 operand encoding, which should stay within
1405       // [-128; +127] to have the 8-byte displacement encoding.
1406       //
1407       // Any change to this code may need to revisit other places in
1408       // the code where this idiom is used, in particular the
1409       // orderAccess code.
1410 
1411       int offset = -VM_Version::L1_line_size();
1412       if (offset < -128) {
1413         offset = -128;
1414       }
1415 
1416       lock();
1417       addl(Address(rsp, offset), 0);// Assert the lock# signal here
1418     }
1419   }
1420 
1421   void mfence();
1422   void sfence();
1423 
1424   // Moves
1425 
1426   void mov64(Register dst, int64_t imm64);
1427 
1428   void movb(Address dst, Register src);
1429   void movb(Address dst, int imm8);
1430   void movb(Register dst, Address src);
1431 
1432   void movddup(XMMRegister dst, XMMRegister src);
1433 
1434   void kmovbl(KRegister dst, Register src);
1435   void kmovbl(Register dst, KRegister src);
1436   void kmovwl(KRegister dst, Register src);
1437   void kmovwl(KRegister dst, Address src);
1438   void kmovwl(Register dst, KRegister src);
1439   void kmovdl(KRegister dst, Register src);
1440   void kmovdl(Register dst, KRegister src);
1441   void kmovql(KRegister dst, KRegister src);
1442   void kmovql(Address dst, KRegister src);
1443   void kmovql(KRegister dst, Address src);
1444   void kmovql(KRegister dst, Register src);
1445   void kmovql(Register dst, KRegister src);
1446 
1447   void knotwl(KRegister dst, KRegister src);
1448 
1449   void kortestbl(KRegister dst, KRegister src);
1450   void kortestwl(KRegister dst, KRegister src);
1451   void kortestdl(KRegister dst, KRegister src);
1452   void kortestql(KRegister dst, KRegister src);
1453 
1454   void ktestq(KRegister src1, KRegister src2);
1455   void ktestd(KRegister src1, KRegister src2);
1456 
1457   void ktestql(KRegister dst, KRegister src);
1458 
1459   void movdl(XMMRegister dst, Register src);
1460   void movdl(Register dst, XMMRegister src);
1461   void movdl(XMMRegister dst, Address src);
1462   void movdl(Address dst, XMMRegister src);
1463 
1464   // Move Double Quadword
1465   void movdq(XMMRegister dst, Register src);
1466   void movdq(Register dst, XMMRegister src);
1467 
1468   // Move Aligned Double Quadword
1469   void movdqa(XMMRegister dst, XMMRegister src);
1470   void movdqa(XMMRegister dst, Address src);
1471 
1472   // Move Unaligned Double Quadword
1473   void movdqu(Address     dst, XMMRegister src);
1474   void movdqu(XMMRegister dst, Address src);
1475   void movdqu(XMMRegister dst, XMMRegister src);
1476 
1477   // Move Unaligned 256bit Vector
1478   void vmovdqu(Address dst, XMMRegister src);
1479   void vmovdqu(XMMRegister dst, Address src);
1480   void vmovdqu(XMMRegister dst, XMMRegister src);
1481 
1482    // Move Unaligned 512bit Vector
1483   void evmovdqub(Address dst, XMMRegister src, int vector_len);
1484   void evmovdqub(XMMRegister dst, Address src, int vector_len);
1485   void evmovdqub(XMMRegister dst, XMMRegister src, int vector_len);
1486   void evmovdqub(XMMRegister dst, KRegister mask, Address src, int vector_len);
1487   void evmovdquw(Address dst, XMMRegister src, int vector_len);
1488   void evmovdquw(Address dst, KRegister mask, XMMRegister src, int vector_len);
1489   void evmovdquw(XMMRegister dst, Address src, int vector_len);
1490   void evmovdquw(XMMRegister dst, KRegister mask, Address src, int vector_len);
1491   void evmovdqul(Address dst, XMMRegister src, int vector_len);
1492   void evmovdqul(XMMRegister dst, Address src, int vector_len);
1493   void evmovdqul(XMMRegister dst, XMMRegister src, int vector_len);
1494   void evmovdquq(Address dst, XMMRegister src, int vector_len);
1495   void evmovdquq(XMMRegister dst, Address src, int vector_len);
1496   void evmovdquq(XMMRegister dst, XMMRegister src, int vector_len);
1497 
1498   // Move lower 64bit to high 64bit in 128bit register
1499   void movlhps(XMMRegister dst, XMMRegister src);
1500 
1501   void movl(Register dst, int32_t imm32);
1502   void movl(Address dst, int32_t imm32);
1503   void movl(Register dst, Register src);
1504   void movl(Register dst, Address src);
1505   void movl(Address dst, Register src);
1506 
1507   // These dummies prevent using movl from converting a zero (like NULL) into Register
1508   // by giving the compiler two choices it can't resolve
1509 
1510   void movl(Address  dst, void* junk);
1511   void movl(Register dst, void* junk);
1512 
1513 #ifdef _LP64
1514   void movq(Register dst, Register src);
1515   void movq(Register dst, Address src);
1516   void movq(Address  dst, Register src);
1517 #endif
1518 
1519   void movq(Address     dst, MMXRegister src );
1520   void movq(MMXRegister dst, Address src );
1521 
1522 #ifdef _LP64
1523   // These dummies prevent using movq from converting a zero (like NULL) into Register
1524   // by giving the compiler two choices it can't resolve
1525 
1526   void movq(Address  dst, void* dummy);
1527   void movq(Register dst, void* dummy);
1528 #endif
1529 
1530   // Move Quadword
1531   void movq(Address     dst, XMMRegister src);
1532   void movq(XMMRegister dst, Address src);
1533 
1534   void movsbl(Register dst, Address src);
1535   void movsbl(Register dst, Register src);
1536 
1537 #ifdef _LP64
1538   void movsbq(Register dst, Address src);
1539   void movsbq(Register dst, Register src);
1540 
1541   // Move signed 32bit immediate to 64bit extending sign
1542   void movslq(Address  dst, int32_t imm64);
1543   void movslq(Register dst, int32_t imm64);
1544 
1545   void movslq(Register dst, Address src);
1546   void movslq(Register dst, Register src);
1547   void movslq(Register dst, void* src); // Dummy declaration to cause NULL to be ambiguous
1548 #endif
1549 
1550   void movswl(Register dst, Address src);
1551   void movswl(Register dst, Register src);
1552 
1553 #ifdef _LP64
1554   void movswq(Register dst, Address src);
1555   void movswq(Register dst, Register src);
1556 #endif
1557 
1558   void movw(Address dst, int imm16);
1559   void movw(Register dst, Address src);
1560   void movw(Address dst, Register src);
1561 
1562   void movzbl(Register dst, Address src);
1563   void movzbl(Register dst, Register src);
1564 
1565 #ifdef _LP64
1566   void movzbq(Register dst, Address src);
1567   void movzbq(Register dst, Register src);
1568 #endif
1569 
1570   void movzwl(Register dst, Address src);
1571   void movzwl(Register dst, Register src);
1572 
1573 #ifdef _LP64
1574   void movzwq(Register dst, Address src);
1575   void movzwq(Register dst, Register src);
1576 #endif
1577 
1578   // Unsigned multiply with RAX destination register
1579   void mull(Address src);
1580   void mull(Register src);
1581 
1582 #ifdef _LP64
1583   void mulq(Address src);
1584   void mulq(Register src);
1585   void mulxq(Register dst1, Register dst2, Register src);
1586 #endif
1587 
1588   // Multiply Scalar Double-Precision Floating-Point Values
1589   void mulsd(XMMRegister dst, Address src);
1590   void mulsd(XMMRegister dst, XMMRegister src);
1591 
1592   // Multiply Scalar Single-Precision Floating-Point Values
1593   void mulss(XMMRegister dst, Address src);
1594   void mulss(XMMRegister dst, XMMRegister src);
1595 
1596   void negl(Register dst);
1597 
1598 #ifdef _LP64
1599   void negq(Register dst);
1600 #endif
1601 
1602   void nop(int i = 1);
1603 
1604   void notl(Register dst);
1605 
1606 #ifdef _LP64
1607   void notq(Register dst);
1608 
1609   void btsq(Address dst, int imm8);
1610   void btrq(Address dst, int imm8);
1611 #endif
1612 
1613   void orl(Address dst, int32_t imm32);
1614   void orl(Register dst, int32_t imm32);
1615   void orl(Register dst, Address src);
1616   void orl(Register dst, Register src);
1617   void orl(Address dst, Register src);
1618 
1619   void orb(Address dst, int imm8);
1620 
1621   void orq(Address dst, int32_t imm32);
1622   void orq(Register dst, int32_t imm32);
1623   void orq(Register dst, Address src);
1624   void orq(Register dst, Register src);
1625 
1626   // Pack with unsigned saturation
1627   void packuswb(XMMRegister dst, XMMRegister src);
1628   void packuswb(XMMRegister dst, Address src);
1629   void vpackuswb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1630 
1631   // Pemutation of 64bit words
1632   void vpermq(XMMRegister dst, XMMRegister src, int imm8, int vector_len);
1633   void vpermq(XMMRegister dst, XMMRegister src, int imm8);
1634   void vpermq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1635   void vperm2i128(XMMRegister dst,  XMMRegister nds, XMMRegister src, int imm8);
1636   void vperm2f128(XMMRegister dst, XMMRegister nds, XMMRegister src, int imm8);
1637   void evpermi2q(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1638 
1639   void pause();
1640 
1641   // Undefined Instruction
1642   void ud2();
1643 
1644   // SSE4.2 string instructions
1645   void pcmpestri(XMMRegister xmm1, XMMRegister xmm2, int imm8);
1646   void pcmpestri(XMMRegister xmm1, Address src, int imm8);
1647 
1648   void pcmpeqb(XMMRegister dst, XMMRegister src);
1649   void vpcmpeqb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1650   void evpcmpeqb(KRegister kdst, XMMRegister nds, XMMRegister src, int vector_len);
1651   void evpcmpeqb(KRegister kdst, XMMRegister nds, Address src, int vector_len);
1652   void evpcmpeqb(KRegister kdst, KRegister mask, XMMRegister nds, Address src, int vector_len);
1653 
1654   void evpcmpgtb(KRegister kdst, XMMRegister nds, Address src, int vector_len);
1655   void evpcmpgtb(KRegister kdst, KRegister mask, XMMRegister nds, Address src, int vector_len);
1656 
1657   void evpcmpuw(KRegister kdst, XMMRegister nds, XMMRegister src, ComparisonPredicate vcc, int vector_len);
1658   void evpcmpuw(KRegister kdst, KRegister mask, XMMRegister nds, XMMRegister src, ComparisonPredicate of, int vector_len);
1659   void evpcmpuw(KRegister kdst, XMMRegister nds, Address src, ComparisonPredicate vcc, int vector_len);
1660 
1661   void pcmpeqw(XMMRegister dst, XMMRegister src);
1662   void vpcmpeqw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1663   void evpcmpeqw(KRegister kdst, XMMRegister nds, XMMRegister src, int vector_len);
1664   void evpcmpeqw(KRegister kdst, XMMRegister nds, Address src, int vector_len);
1665 
1666   void pcmpeqd(XMMRegister dst, XMMRegister src);
1667   void vpcmpeqd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1668   void evpcmpeqd(KRegister kdst, XMMRegister nds, XMMRegister src, int vector_len);
1669   void evpcmpeqd(KRegister kdst, XMMRegister nds, Address src, int vector_len);
1670 
1671   void pcmpeqq(XMMRegister dst, XMMRegister src);
1672   void vpcmpeqq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1673   void evpcmpeqq(KRegister kdst, XMMRegister nds, XMMRegister src, int vector_len);
1674   void evpcmpeqq(KRegister kdst, XMMRegister nds, Address src, int vector_len);
1675 
1676   void pmovmskb(Register dst, XMMRegister src);
1677   void vpmovmskb(Register dst, XMMRegister src);
1678 
1679   // SSE 4.1 extract
1680   void pextrd(Register dst, XMMRegister src, int imm8);
1681   void pextrq(Register dst, XMMRegister src, int imm8);
1682   void pextrd(Address dst, XMMRegister src, int imm8);
1683   void pextrq(Address dst, XMMRegister src, int imm8);
1684   void pextrb(Address dst, XMMRegister src, int imm8);
1685   // SSE 2 extract
1686   void pextrw(Register dst, XMMRegister src, int imm8);
1687   void pextrw(Address dst, XMMRegister src, int imm8);
1688 
1689   // SSE 4.1 insert
1690   void pinsrd(XMMRegister dst, Register src, int imm8);
1691   void pinsrq(XMMRegister dst, Register src, int imm8);
1692   void pinsrd(XMMRegister dst, Address src, int imm8);
1693   void pinsrq(XMMRegister dst, Address src, int imm8);
1694   void pinsrb(XMMRegister dst, Address src, int imm8);
1695   // SSE 2 insert
1696   void pinsrw(XMMRegister dst, Register src, int imm8);
1697   void pinsrw(XMMRegister dst, Address src, int imm8);
1698 
1699   // SSE4.1 packed move
1700   void pmovzxbw(XMMRegister dst, XMMRegister src);
1701   void pmovzxbw(XMMRegister dst, Address src);
1702 
1703   void vpmovzxbw( XMMRegister dst, Address src, int vector_len);
1704   void vpmovzxbw(XMMRegister dst, XMMRegister src, int vector_len);
1705   void evpmovzxbw(XMMRegister dst, KRegister mask, Address src, int vector_len);
1706 
1707   void evpmovwb(Address dst, XMMRegister src, int vector_len);
1708   void evpmovwb(Address dst, KRegister mask, XMMRegister src, int vector_len);
1709 
1710   void vpmovzxwd(XMMRegister dst, XMMRegister src, int vector_len);
1711 
1712   void evpmovdb(Address dst, XMMRegister src, int vector_len);
1713 
1714   // Sign extend moves
1715   void pmovsxbw(XMMRegister dst, XMMRegister src);
1716   void vpmovsxbw(XMMRegister dst, XMMRegister src, int vector_len);
1717 
1718   // Multiply add
1719   void pmaddwd(XMMRegister dst, XMMRegister src);
1720   void vpmaddwd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1721   // Multiply add accumulate
1722   void evpdpwssd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1723 
1724 #ifndef _LP64 // no 32bit push/pop on amd64
1725   void popl(Address dst);
1726 #endif
1727 
1728 #ifdef _LP64
1729   void popq(Address dst);
1730 #endif
1731 
1732   void popcntl(Register dst, Address src);
1733   void popcntl(Register dst, Register src);
1734 
1735   void vpopcntd(XMMRegister dst, XMMRegister src, int vector_len);
1736 
1737 #ifdef _LP64
1738   void popcntq(Register dst, Address src);
1739   void popcntq(Register dst, Register src);
1740 #endif
1741 
1742   // Prefetches (SSE, SSE2, 3DNOW only)
1743 
1744   void prefetchnta(Address src);
1745   void prefetchr(Address src);
1746   void prefetcht0(Address src);
1747   void prefetcht1(Address src);
1748   void prefetcht2(Address src);
1749   void prefetchw(Address src);
1750 
1751   // Shuffle Bytes
1752   void pshufb(XMMRegister dst, XMMRegister src);
1753   void pshufb(XMMRegister dst, Address src);
1754   void vpshufb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1755 
1756   // Shuffle Packed Doublewords
1757   void pshufd(XMMRegister dst, XMMRegister src, int mode);
1758   void pshufd(XMMRegister dst, Address src,     int mode);
1759   void vpshufd(XMMRegister dst, XMMRegister src, int mode, int vector_len);
1760 
1761   // Shuffle Packed Low Words
1762   void pshuflw(XMMRegister dst, XMMRegister src, int mode);
1763   void pshuflw(XMMRegister dst, Address src,     int mode);
1764 
1765   // Shuffle packed values at 128 bit granularity
1766   void evshufi64x2(XMMRegister dst, XMMRegister nds, XMMRegister src, int imm8, int vector_len);
1767 
1768   // Shift Right by bytes Logical DoubleQuadword Immediate
1769   void psrldq(XMMRegister dst, int shift);
1770   // Shift Left by bytes Logical DoubleQuadword Immediate
1771   void pslldq(XMMRegister dst, int shift);
1772 
1773   // Logical Compare 128bit
1774   void ptest(XMMRegister dst, XMMRegister src);
1775   void ptest(XMMRegister dst, Address src);
1776   // Logical Compare 256bit
1777   void vptest(XMMRegister dst, XMMRegister src);
1778   void vptest(XMMRegister dst, Address src);
1779 
1780   // Interleave Low Bytes
1781   void punpcklbw(XMMRegister dst, XMMRegister src);
1782   void punpcklbw(XMMRegister dst, Address src);
1783 
1784   // Interleave Low Doublewords
1785   void punpckldq(XMMRegister dst, XMMRegister src);
1786   void punpckldq(XMMRegister dst, Address src);
1787 
1788   // Interleave Low Quadwords
1789   void punpcklqdq(XMMRegister dst, XMMRegister src);
1790 
1791 #ifndef _LP64 // no 32bit push/pop on amd64
1792   void pushl(Address src);
1793 #endif
1794 
1795   void pushq(Address src);
1796 
1797   void rcll(Register dst, int imm8);
1798 
1799   void rclq(Register dst, int imm8);
1800 
1801   void rcrq(Register dst, int imm8);
1802 
1803   void rcpps(XMMRegister dst, XMMRegister src);
1804 
1805   void rcpss(XMMRegister dst, XMMRegister src);
1806 
1807   void rdtsc();
1808 
1809   void ret(int imm16);
1810 
1811 #ifdef _LP64
1812   void rorq(Register dst, int imm8);
1813   void rorxq(Register dst, Register src, int imm8);
1814   void rorxd(Register dst, Register src, int imm8);
1815 #endif
1816 
1817   void sahf();
1818 
1819   void sarl(Register dst, int imm8);
1820   void sarl(Register dst);
1821 
1822   void sarq(Register dst, int imm8);
1823   void sarq(Register dst);
1824 
1825   void sbbl(Address dst, int32_t imm32);
1826   void sbbl(Register dst, int32_t imm32);
1827   void sbbl(Register dst, Address src);
1828   void sbbl(Register dst, Register src);
1829 
1830   void sbbq(Address dst, int32_t imm32);
1831   void sbbq(Register dst, int32_t imm32);
1832   void sbbq(Register dst, Address src);
1833   void sbbq(Register dst, Register src);
1834 
1835   void setb(Condition cc, Register dst);
1836 
1837   void palignr(XMMRegister dst, XMMRegister src, int imm8);
1838   void vpalignr(XMMRegister dst, XMMRegister src1, XMMRegister src2, int imm8, int vector_len);
1839   void evalignq(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8);
1840 
1841   void pblendw(XMMRegister dst, XMMRegister src, int imm8);
1842 
1843   void sha1rnds4(XMMRegister dst, XMMRegister src, int imm8);
1844   void sha1nexte(XMMRegister dst, XMMRegister src);
1845   void sha1msg1(XMMRegister dst, XMMRegister src);
1846   void sha1msg2(XMMRegister dst, XMMRegister src);
1847   // xmm0 is implicit additional source to the following instruction.
1848   void sha256rnds2(XMMRegister dst, XMMRegister src);
1849   void sha256msg1(XMMRegister dst, XMMRegister src);
1850   void sha256msg2(XMMRegister dst, XMMRegister src);
1851 
1852   void shldl(Register dst, Register src);
1853   void shldl(Register dst, Register src, int8_t imm8);
1854   void shrdl(Register dst, Register src);
1855   void shrdl(Register dst, Register src, int8_t imm8);
1856 
1857   void shll(Register dst, int imm8);
1858   void shll(Register dst);
1859 
1860   void shlq(Register dst, int imm8);
1861   void shlq(Register dst);
1862 
1863   void shrl(Register dst, int imm8);
1864   void shrl(Register dst);
1865 
1866   void shrq(Register dst, int imm8);
1867   void shrq(Register dst);
1868 
1869   void smovl(); // QQQ generic?
1870 
1871   // Compute Square Root of Scalar Double-Precision Floating-Point Value
1872   void sqrtsd(XMMRegister dst, Address src);
1873   void sqrtsd(XMMRegister dst, XMMRegister src);
1874 
1875   void roundsd(XMMRegister dst, Address src, int32_t rmode);
1876   void roundsd(XMMRegister dst, XMMRegister src, int32_t rmode);
1877 
1878   // Compute Square Root of Scalar Single-Precision Floating-Point Value
1879   void sqrtss(XMMRegister dst, Address src);
1880   void sqrtss(XMMRegister dst, XMMRegister src);
1881 
1882   void std();
1883 
1884   void stmxcsr( Address dst );
1885 
1886   void subl(Address dst, int32_t imm32);
1887   void subl(Address dst, Register src);
1888   void subl(Register dst, int32_t imm32);
1889   void subl(Register dst, Address src);
1890   void subl(Register dst, Register src);
1891 
1892   void subq(Address dst, int32_t imm32);
1893   void subq(Address dst, Register src);
1894   void subq(Register dst, int32_t imm32);
1895   void subq(Register dst, Address src);
1896   void subq(Register dst, Register src);
1897 
1898   // Force generation of a 4 byte immediate value even if it fits into 8bit
1899   void subl_imm32(Register dst, int32_t imm32);
1900   void subq_imm32(Register dst, int32_t imm32);
1901 
1902   // Subtract Scalar Double-Precision Floating-Point Values
1903   void subsd(XMMRegister dst, Address src);
1904   void subsd(XMMRegister dst, XMMRegister src);
1905 
1906   // Subtract Scalar Single-Precision Floating-Point Values
1907   void subss(XMMRegister dst, Address src);
1908   void subss(XMMRegister dst, XMMRegister src);
1909 
1910   void testb(Register dst, int imm8);
1911   void testb(Address dst, int imm8);
1912 
1913   void testl(Register dst, int32_t imm32);
1914   void testl(Register dst, Register src);
1915   void testl(Register dst, Address src);
1916 
1917   void testq(Register dst, int32_t imm32);
1918   void testq(Register dst, Register src);
1919   void testq(Register dst, Address src);
1920 
1921   // BMI - count trailing zeros
1922   void tzcntl(Register dst, Register src);
1923   void tzcntq(Register dst, Register src);
1924 
1925   // Unordered Compare Scalar Double-Precision Floating-Point Values and set EFLAGS
1926   void ucomisd(XMMRegister dst, Address src);
1927   void ucomisd(XMMRegister dst, XMMRegister src);
1928 
1929   // Unordered Compare Scalar Single-Precision Floating-Point Values and set EFLAGS
1930   void ucomiss(XMMRegister dst, Address src);
1931   void ucomiss(XMMRegister dst, XMMRegister src);
1932 
1933   void xabort(int8_t imm8);
1934 
1935   void xaddb(Address dst, Register src);
1936   void xaddw(Address dst, Register src);
1937   void xaddl(Address dst, Register src);
1938   void xaddq(Address dst, Register src);
1939 
1940   void xbegin(Label& abort, relocInfo::relocType rtype = relocInfo::none);
1941 
1942   void xchgb(Register reg, Address adr);
1943   void xchgw(Register reg, Address adr);
1944   void xchgl(Register reg, Address adr);
1945   void xchgl(Register dst, Register src);
1946 
1947   void xchgq(Register reg, Address adr);
1948   void xchgq(Register dst, Register src);
1949 
1950   void xend();
1951 
1952   // Get Value of Extended Control Register
1953   void xgetbv();
1954 
1955   void xorl(Register dst, int32_t imm32);
1956   void xorl(Register dst, Address src);
1957   void xorl(Register dst, Register src);
1958 
1959   void xorb(Register dst, Address src);
1960 
1961   void xorq(Register dst, Address src);
1962   void xorq(Register dst, Register src);
1963 
1964   void set_byte_if_not_zero(Register dst); // sets reg to 1 if not zero, otherwise 0
1965 
1966   // AVX 3-operands scalar instructions (encoded with VEX prefix)
1967 
1968   void vaddsd(XMMRegister dst, XMMRegister nds, Address src);
1969   void vaddsd(XMMRegister dst, XMMRegister nds, XMMRegister src);
1970   void vaddss(XMMRegister dst, XMMRegister nds, Address src);
1971   void vaddss(XMMRegister dst, XMMRegister nds, XMMRegister src);
1972   void vdivsd(XMMRegister dst, XMMRegister nds, Address src);
1973   void vdivsd(XMMRegister dst, XMMRegister nds, XMMRegister src);
1974   void vdivss(XMMRegister dst, XMMRegister nds, Address src);
1975   void vdivss(XMMRegister dst, XMMRegister nds, XMMRegister src);
1976   void vfmadd231sd(XMMRegister dst, XMMRegister nds, XMMRegister src);
1977   void vfmadd231ss(XMMRegister dst, XMMRegister nds, XMMRegister src);
1978   void vmulsd(XMMRegister dst, XMMRegister nds, Address src);
1979   void vmulsd(XMMRegister dst, XMMRegister nds, XMMRegister src);
1980   void vmulss(XMMRegister dst, XMMRegister nds, Address src);
1981   void vmulss(XMMRegister dst, XMMRegister nds, XMMRegister src);
1982   void vsubsd(XMMRegister dst, XMMRegister nds, Address src);
1983   void vsubsd(XMMRegister dst, XMMRegister nds, XMMRegister src);
1984   void vsubss(XMMRegister dst, XMMRegister nds, Address src);
1985   void vsubss(XMMRegister dst, XMMRegister nds, XMMRegister src);
1986 
1987   void vmaxss(XMMRegister dst, XMMRegister nds, XMMRegister src);
1988   void vmaxsd(XMMRegister dst, XMMRegister nds, XMMRegister src);
1989   void vminss(XMMRegister dst, XMMRegister nds, XMMRegister src);
1990   void vminsd(XMMRegister dst, XMMRegister nds, XMMRegister src);
1991 
1992   void shlxl(Register dst, Register src1, Register src2);
1993   void shlxq(Register dst, Register src1, Register src2);
1994 
1995   //====================VECTOR ARITHMETIC=====================================
1996 
1997   // Add Packed Floating-Point Values
1998   void addpd(XMMRegister dst, XMMRegister src);
1999   void addpd(XMMRegister dst, Address src);
2000   void addps(XMMRegister dst, XMMRegister src);
2001   void vaddpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2002   void vaddps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2003   void vaddpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2004   void vaddps(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2005 
2006   // Subtract Packed Floating-Point Values
2007   void subpd(XMMRegister dst, XMMRegister src);
2008   void subps(XMMRegister dst, XMMRegister src);
2009   void vsubpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2010   void vsubps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2011   void vsubpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2012   void vsubps(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2013 
2014   // Multiply Packed Floating-Point Values
2015   void mulpd(XMMRegister dst, XMMRegister src);
2016   void mulpd(XMMRegister dst, Address src);
2017   void mulps(XMMRegister dst, XMMRegister src);
2018   void vmulpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2019   void vmulps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2020   void vmulpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2021   void vmulps(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2022 
2023   void vfmadd231pd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2024   void vfmadd231ps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2025   void vfmadd231pd(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2026   void vfmadd231ps(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2027 
2028   // Divide Packed Floating-Point Values
2029   void divpd(XMMRegister dst, XMMRegister src);
2030   void divps(XMMRegister dst, XMMRegister src);
2031   void vdivpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2032   void vdivps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2033   void vdivpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2034   void vdivps(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2035 
2036   // Sqrt Packed Floating-Point Values
2037   void vsqrtpd(XMMRegister dst, XMMRegister src, int vector_len);
2038   void vsqrtpd(XMMRegister dst, Address src, int vector_len);
2039   void vsqrtps(XMMRegister dst, XMMRegister src, int vector_len);
2040   void vsqrtps(XMMRegister dst, Address src, int vector_len);
2041 
2042   // Round Packed Double precision value.
2043   void vroundpd(XMMRegister dst, XMMRegister src, int32_t rmode, int vector_len);
2044   void vroundpd(XMMRegister dst, Address src, int32_t rmode, int vector_len);
2045   void vrndscalepd(XMMRegister dst,  XMMRegister src,  int32_t rmode, int vector_len);
2046   void vrndscalepd(XMMRegister dst, Address src, int32_t rmode, int vector_len);
2047 
2048   // Bitwise Logical AND of Packed Floating-Point Values
2049   void andpd(XMMRegister dst, XMMRegister src);
2050   void andps(XMMRegister dst, XMMRegister src);
2051   void vandpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2052   void vandps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2053   void vandpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2054   void vandps(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2055 
2056   void unpckhpd(XMMRegister dst, XMMRegister src);
2057   void unpcklpd(XMMRegister dst, XMMRegister src);
2058 
2059   // Bitwise Logical XOR of Packed Floating-Point Values
2060   void xorpd(XMMRegister dst, XMMRegister src);
2061   void xorps(XMMRegister dst, XMMRegister src);
2062   void vxorpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2063   void vxorps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2064   void vxorpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2065   void vxorps(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2066 
2067   // Add horizontal packed integers
2068   void vphaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2069   void vphaddd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2070   void phaddw(XMMRegister dst, XMMRegister src);
2071   void phaddd(XMMRegister dst, XMMRegister src);
2072 
2073   // Add packed integers
2074   void paddb(XMMRegister dst, XMMRegister src);
2075   void paddw(XMMRegister dst, XMMRegister src);
2076   void paddd(XMMRegister dst, XMMRegister src);
2077   void paddd(XMMRegister dst, Address src);
2078   void paddq(XMMRegister dst, XMMRegister src);
2079   void vpaddb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2080   void vpaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2081   void vpaddd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2082   void vpaddq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2083   void vpaddb(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2084   void vpaddw(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2085   void vpaddd(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2086   void vpaddq(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2087 
2088   // Sub packed integers
2089   void psubb(XMMRegister dst, XMMRegister src);
2090   void psubw(XMMRegister dst, XMMRegister src);
2091   void psubd(XMMRegister dst, XMMRegister src);
2092   void psubq(XMMRegister dst, XMMRegister src);
2093   void vpsubb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2094   void vpsubw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2095   void vpsubd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2096   void vpsubq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2097   void vpsubb(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2098   void vpsubw(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2099   void vpsubd(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2100   void vpsubq(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2101 
2102   // Multiply packed integers (only shorts and ints)
2103   void pmullw(XMMRegister dst, XMMRegister src);
2104   void pmulld(XMMRegister dst, XMMRegister src);
2105   void vpmullw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2106   void vpmulld(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2107   void vpmullq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2108   void vpmullw(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2109   void vpmulld(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2110   void vpmullq(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2111 
2112   // Shift left packed integers
2113   void psllw(XMMRegister dst, int shift);
2114   void pslld(XMMRegister dst, int shift);
2115   void psllq(XMMRegister dst, int shift);
2116   void psllw(XMMRegister dst, XMMRegister shift);
2117   void pslld(XMMRegister dst, XMMRegister shift);
2118   void psllq(XMMRegister dst, XMMRegister shift);
2119   void vpsllw(XMMRegister dst, XMMRegister src, int shift, int vector_len);
2120   void vpslld(XMMRegister dst, XMMRegister src, int shift, int vector_len);
2121   void vpsllq(XMMRegister dst, XMMRegister src, int shift, int vector_len);
2122   void vpsllw(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len);
2123   void vpslld(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len);
2124   void vpsllq(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len);
2125   void vpslldq(XMMRegister dst, XMMRegister src, int shift, int vector_len);
2126 
2127   // Logical shift right packed integers
2128   void psrlw(XMMRegister dst, int shift);
2129   void psrld(XMMRegister dst, int shift);
2130   void psrlq(XMMRegister dst, int shift);
2131   void psrlw(XMMRegister dst, XMMRegister shift);
2132   void psrld(XMMRegister dst, XMMRegister shift);
2133   void psrlq(XMMRegister dst, XMMRegister shift);
2134   void vpsrlw(XMMRegister dst, XMMRegister src, int shift, int vector_len);
2135   void vpsrld(XMMRegister dst, XMMRegister src, int shift, int vector_len);
2136   void vpsrlq(XMMRegister dst, XMMRegister src, int shift, int vector_len);
2137   void vpsrlw(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len);
2138   void vpsrld(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len);
2139   void vpsrlq(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len);
2140   void vpsrldq(XMMRegister dst, XMMRegister src, int shift, int vector_len);
2141   void evpsrlvw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2142   void evpsllvw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2143 
2144   // Arithmetic shift right packed integers (only shorts and ints, no instructions for longs)
2145   void psraw(XMMRegister dst, int shift);
2146   void psrad(XMMRegister dst, int shift);
2147   void psraw(XMMRegister dst, XMMRegister shift);
2148   void psrad(XMMRegister dst, XMMRegister shift);
2149   void vpsraw(XMMRegister dst, XMMRegister src, int shift, int vector_len);
2150   void vpsrad(XMMRegister dst, XMMRegister src, int shift, int vector_len);
2151   void vpsraw(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len);
2152   void vpsrad(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len);
2153   void evpsraq(XMMRegister dst, XMMRegister src, int shift, int vector_len);
2154   void evpsraq(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len);
2155 
2156   void vpshldvd(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len);
2157   void vpshrdvd(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len);
2158 
2159   // And packed integers
2160   void pand(XMMRegister dst, XMMRegister src);
2161   void vpand(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2162   void vpand(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2163   void vpandq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2164 
2165   // Andn packed integers
2166   void pandn(XMMRegister dst, XMMRegister src);
2167   void vpandn(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2168 
2169   // Or packed integers
2170   void por(XMMRegister dst, XMMRegister src);
2171   void vpor(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2172   void vpor(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2173   void vporq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2174 
2175   // Xor packed integers
2176   void pxor(XMMRegister dst, XMMRegister src);
2177   void vpxor(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2178   void vpxor(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2179   void evpxorq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2180   void evpxorq(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2181 
2182 
2183   // vinserti forms
2184   void vinserti128(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8);
2185   void vinserti128(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8);
2186   void vinserti32x4(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8);
2187   void vinserti32x4(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8);
2188   void vinserti64x4(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8);
2189 
2190   // vinsertf forms
2191   void vinsertf128(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8);
2192   void vinsertf128(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8);
2193   void vinsertf32x4(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8);
2194   void vinsertf32x4(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8);
2195   void vinsertf64x4(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8);
2196   void vinsertf64x4(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8);
2197 
2198   // vextracti forms
2199   void vextracti128(XMMRegister dst, XMMRegister src, uint8_t imm8);
2200   void vextracti128(Address dst, XMMRegister src, uint8_t imm8);
2201   void vextracti32x4(XMMRegister dst, XMMRegister src, uint8_t imm8);
2202   void vextracti32x4(Address dst, XMMRegister src, uint8_t imm8);
2203   void vextracti64x2(XMMRegister dst, XMMRegister src, uint8_t imm8);
2204   void vextracti64x4(XMMRegister dst, XMMRegister src, uint8_t imm8);
2205   void vextracti64x4(Address dst, XMMRegister src, uint8_t imm8);
2206 
2207   // vextractf forms
2208   void vextractf128(XMMRegister dst, XMMRegister src, uint8_t imm8);
2209   void vextractf128(Address dst, XMMRegister src, uint8_t imm8);
2210   void vextractf32x4(XMMRegister dst, XMMRegister src, uint8_t imm8);
2211   void vextractf32x4(Address dst, XMMRegister src, uint8_t imm8);
2212   void vextractf64x2(XMMRegister dst, XMMRegister src, uint8_t imm8);
2213   void vextractf64x4(XMMRegister dst, XMMRegister src, uint8_t imm8);
2214   void vextractf64x4(Address dst, XMMRegister src, uint8_t imm8);
2215 
2216   // xmm/mem sourced byte/word/dword/qword replicate
2217   void vpbroadcastb(XMMRegister dst, XMMRegister src, int vector_len);
2218   void vpbroadcastb(XMMRegister dst, Address src, int vector_len);
2219   void vpbroadcastw(XMMRegister dst, XMMRegister src, int vector_len);
2220   void vpbroadcastw(XMMRegister dst, Address src, int vector_len);
2221   void vpbroadcastd(XMMRegister dst, XMMRegister src, int vector_len);
2222   void vpbroadcastd(XMMRegister dst, Address src, int vector_len);
2223   void vpbroadcastq(XMMRegister dst, XMMRegister src, int vector_len);
2224   void vpbroadcastq(XMMRegister dst, Address src, int vector_len);
2225 
2226   void evbroadcasti64x2(XMMRegister dst, XMMRegister src, int vector_len);
2227   void evbroadcasti64x2(XMMRegister dst, Address src, int vector_len);
2228 
2229   // scalar single/double precision replicate
2230   void vbroadcastss(XMMRegister dst, XMMRegister src, int vector_len);
2231   void vbroadcastss(XMMRegister dst, Address src, int vector_len);
2232   void vbroadcastsd(XMMRegister dst, XMMRegister src, int vector_len);
2233   void vbroadcastsd(XMMRegister dst, Address src, int vector_len);
2234 
2235   // gpr sourced byte/word/dword/qword replicate
2236   void evpbroadcastb(XMMRegister dst, Register src, int vector_len);
2237   void evpbroadcastw(XMMRegister dst, Register src, int vector_len);
2238   void evpbroadcastd(XMMRegister dst, Register src, int vector_len);
2239   void evpbroadcastq(XMMRegister dst, Register src, int vector_len);
2240 
2241   void evpgatherdd(XMMRegister dst, KRegister k1, Address src, int vector_len);
2242 
2243   // Carry-Less Multiplication Quadword
2244   void pclmulqdq(XMMRegister dst, XMMRegister src, int mask);
2245   void vpclmulqdq(XMMRegister dst, XMMRegister nds, XMMRegister src, int mask);
2246   void evpclmulqdq(XMMRegister dst, XMMRegister nds, XMMRegister src, int mask, int vector_len);
2247   // AVX instruction which is used to clear upper 128 bits of YMM registers and
2248   // to avoid transaction penalty between AVX and SSE states. There is no
2249   // penalty if legacy SSE instructions are encoded using VEX prefix because
2250   // they always clear upper 128 bits. It should be used before calling
2251   // runtime code and native libraries.
2252   void vzeroupper();
2253 
2254   // AVX support for vectorized conditional move (float/double). The following two instructions used only coupled.
2255   void cmppd(XMMRegister dst, XMMRegister nds, XMMRegister src, int cop, int vector_len);
2256   void blendvpd(XMMRegister dst, XMMRegister nds, XMMRegister src1, XMMRegister src2, int vector_len);
2257   void cmpps(XMMRegister dst, XMMRegister nds, XMMRegister src, int cop, int vector_len);
2258   void blendvps(XMMRegister dst, XMMRegister nds, XMMRegister src1, XMMRegister src2, int vector_len);
2259   void vpblendd(XMMRegister dst, XMMRegister nds, XMMRegister src, int imm8, int vector_len);
2260 
2261  protected:
2262   // Next instructions require address alignment 16 bytes SSE mode.
2263   // They should be called only from corresponding MacroAssembler instructions.
2264   void andpd(XMMRegister dst, Address src);
2265   void andps(XMMRegister dst, Address src);
2266   void xorpd(XMMRegister dst, Address src);
2267   void xorps(XMMRegister dst, Address src);
2268 
2269 };
2270 
2271 // The Intel x86/Amd64 Assembler attributes: All fields enclosed here are to guide encoding level decisions.
2272 // Specific set functions are for specialized use, else defaults or whatever was supplied to object construction
2273 // are applied.
2274 class InstructionAttr {
2275 public:
2276   InstructionAttr(
2277     int vector_len,     // The length of vector to be applied in encoding - for both AVX and EVEX
2278     bool rex_vex_w,     // Width of data: if 32-bits or less, false, else if 64-bit or specially defined, true
2279     bool legacy_mode,   // Details if either this instruction is conditionally encoded to AVX or earlier if true else possibly EVEX
2280     bool no_reg_mask,   // when true, k0 is used when EVEX encoding is chosen, else embedded_opmask_register_specifier is used
2281     bool uses_vl)       // This instruction may have legacy constraints based on vector length for EVEX
2282     :
2283       _avx_vector_len(vector_len),
2284       _rex_vex_w(rex_vex_w),
2285       _rex_vex_w_reverted(false),
2286       _legacy_mode(legacy_mode),
2287       _no_reg_mask(no_reg_mask),
2288       _uses_vl(uses_vl),
2289       _tuple_type(Assembler::EVEX_ETUP),
2290       _input_size_in_bits(Assembler::EVEX_NObit),
2291       _is_evex_instruction(false),
2292       _evex_encoding(0),
2293       _is_clear_context(true),
2294       _is_extended_context(false),




2295       _embedded_opmask_register_specifier(0), // hard code k0
2296       _current_assembler(NULL) {
2297     if (UseAVX < 3) _legacy_mode = true;
2298   }
2299 
2300   ~InstructionAttr() {
2301     if (_current_assembler != NULL) {
2302       _current_assembler->clear_attributes();
2303     }
2304     _current_assembler = NULL;
2305   }
2306 
2307 private:
2308   int  _avx_vector_len;
2309   bool _rex_vex_w;
2310   bool _rex_vex_w_reverted;
2311   bool _legacy_mode;
2312   bool _no_reg_mask;
2313   bool _uses_vl;
2314   int  _tuple_type;
2315   int  _input_size_in_bits;
2316   bool _is_evex_instruction;
2317   int  _evex_encoding;
2318   bool _is_clear_context;
2319   bool _is_extended_context;




2320   int _embedded_opmask_register_specifier;
2321 
2322   Assembler *_current_assembler;
2323 
2324 public:
2325   // query functions for field accessors
2326   int  get_vector_len(void) const { return _avx_vector_len; }
2327   bool is_rex_vex_w(void) const { return _rex_vex_w; }
2328   bool is_rex_vex_w_reverted(void) { return _rex_vex_w_reverted; }
2329   bool is_legacy_mode(void) const { return _legacy_mode; }
2330   bool is_no_reg_mask(void) const { return _no_reg_mask; }
2331   bool uses_vl(void) const { return _uses_vl; }





2332   int  get_tuple_type(void) const { return _tuple_type; }
2333   int  get_input_size(void) const { return _input_size_in_bits; }
2334   int  is_evex_instruction(void) const { return _is_evex_instruction; }
2335   int  get_evex_encoding(void) const { return _evex_encoding; }
2336   bool is_clear_context(void) const { return _is_clear_context; }
2337   bool is_extended_context(void) const { return _is_extended_context; }
2338   int get_embedded_opmask_register_specifier(void) const { return _embedded_opmask_register_specifier; }
2339 
2340   // Set the vector len manually
2341   void set_vector_len(int vector_len) { _avx_vector_len = vector_len; }
2342 
2343   // Set revert rex_vex_w for avx encoding
2344   void set_rex_vex_w_reverted(void) { _rex_vex_w_reverted = true; }
2345 
2346   // Set rex_vex_w based on state
2347   void set_rex_vex_w(bool state) { _rex_vex_w = state; }
2348 
2349   // Set the instruction to be encoded in AVX mode
2350   void set_is_legacy_mode(void) { _legacy_mode = true; }
2351 
2352   // Set the current instuction to be encoded as an EVEX instuction
2353   void set_is_evex_instruction(void) { _is_evex_instruction = true; }
2354 
2355   // Internal encoding data used in compressed immediate offset programming
2356   void set_evex_encoding(int value) { _evex_encoding = value; }
2357 
2358   // Set the Evex.Z field to be used to clear all non directed XMM/YMM/ZMM components
2359   void reset_is_clear_context(void) { _is_clear_context = false; }
2360 
2361   // Map back to current asembler so that we can manage object level assocation
2362   void set_current_assembler(Assembler *current_assembler) { _current_assembler = current_assembler; }
2363 
2364   // Address modifiers used for compressed displacement calculation
2365   void set_address_attributes(int tuple_type, int input_size_in_bits) {
2366     if (VM_Version::supports_evex()) {
2367       _tuple_type = tuple_type;
2368       _input_size_in_bits = input_size_in_bits;
2369     }
2370   }
2371 
2372   // Set embedded opmask register specifier.
2373   void set_embedded_opmask_register_specifier(KRegister mask) {
2374     _embedded_opmask_register_specifier = (*mask).encoding() & 0x7;
2375   }
2376 
2377 };
2378 
2379 #endif // CPU_X86_ASSEMBLER_X86_HPP
--- EOF ---