231 code_section()->relocate(inst_mark(), rspec, disp32_operand);
232 else
233 code_section()->relocate(inst_mark(), rspec, format);
234 }
235 emit_int32(data);
236 }
237
238 static int encode(Register r) {
239 int enc = r->encoding();
240 if (enc >= 8) {
241 enc -= 8;
242 }
243 return enc;
244 }
245
246 void Assembler::emit_arith_b(int op1, int op2, Register dst, int imm8) {
247 assert(dst->has_byte_register(), "must have byte register");
248 assert(isByte(op1) && isByte(op2), "wrong opcode");
249 assert(isByte(imm8), "not a byte");
250 assert((op1 & 0x01) == 0, "should be 8bit operation");
251 emit_int8(op1);
252 emit_int8(op2 | encode(dst));
253 emit_int8(imm8);
254 }
255
256
257 void Assembler::emit_arith(int op1, int op2, Register dst, int32_t imm32) {
258 assert(isByte(op1) && isByte(op2), "wrong opcode");
259 assert((op1 & 0x01) == 1, "should be 32bit operation");
260 assert((op1 & 0x02) == 0, "sign-extension bit should not be set");
261 if (is8bit(imm32)) {
262 emit_int8(op1 | 0x02); // set sign bit
263 emit_int8(op2 | encode(dst));
264 emit_int8(imm32 & 0xFF);
265 } else {
266 emit_int8(op1);
267 emit_int8(op2 | encode(dst));
268 emit_int32(imm32);
269 }
270 }
271
272 // Force generation of a 4 byte immediate value even if it fits into 8bit
273 void Assembler::emit_arith_imm32(int op1, int op2, Register dst, int32_t imm32) {
274 assert(isByte(op1) && isByte(op2), "wrong opcode");
275 assert((op1 & 0x01) == 1, "should be 32bit operation");
276 assert((op1 & 0x02) == 0, "sign-extension bit should not be set");
277 emit_int8(op1);
278 emit_int8(op2 | encode(dst));
279 emit_int32(imm32);
280 }
281
282 // immediate-to-memory forms
283 void Assembler::emit_arith_operand(int op1, Register rm, Address adr, int32_t imm32) {
284 assert((op1 & 0x01) == 1, "should be 32bit operation");
285 assert((op1 & 0x02) == 0, "sign-extension bit should not be set");
286 if (is8bit(imm32)) {
287 emit_int8(op1 | 0x02); // set sign bit
288 emit_operand(rm, adr, 1);
289 emit_int8(imm32 & 0xFF);
290 } else {
291 emit_int8(op1);
292 emit_operand(rm, adr, 4);
293 emit_int32(imm32);
294 }
295 }
296
297
298 void Assembler::emit_arith(int op1, int op2, Register dst, Register src) {
299 assert(isByte(op1) && isByte(op2), "wrong opcode");
300 emit_int8(op1);
301 emit_int8(op2 | encode(dst) << 3 | encode(src));
302 }
303
304
305 bool Assembler::query_compressed_disp_byte(int disp, bool is_evex_inst, int vector_len,
306 int cur_tuple_type, int in_size_in_bits, int cur_encoding) {
307 int mod_idx = 0;
308 // We will test if the displacement fits the compressed format and if so
309 // apply the compression to the displacment iff the result is8bit.
310 if (VM_Version::supports_evex() && is_evex_inst) {
311 switch (cur_tuple_type) {
312 case EVEX_FV:
313 if ((cur_encoding & VEX_W) == VEX_W) {
314 mod_idx = ((cur_encoding & EVEX_Rb) == EVEX_Rb) ? 3 : 2;
315 } else {
316 mod_idx = ((cur_encoding & EVEX_Rb) == EVEX_Rb) ? 1 : 0;
317 }
318 break;
319
320 case EVEX_HV:
321 mod_idx = ((cur_encoding & EVEX_Rb) == EVEX_Rb) ? 1 : 0;
463 if (vector_len >= AVX_128bit && vector_len <= AVX_512bit) {
464 int disp_factor = tuple_table[tuple_type + mod_idx][vector_len];
465 if ((disp % disp_factor) == 0) {
466 int new_disp = disp / disp_factor;
467 if (is8bit(new_disp)) {
468 disp = new_disp;
469 }
470 } else {
471 return false;
472 }
473 }
474 }
475 return is8bit(disp);
476 }
477
478
479 void Assembler::emit_operand(Register reg, Register base, Register index,
480 Address::ScaleFactor scale, int disp,
481 RelocationHolder const& rspec,
482 int rip_relative_correction) {
483 relocInfo::relocType rtype = rspec.type();
484
485 // Encode the registers as needed in the fields they are used in
486
487 int regenc = encode(reg) << 3;
488 int indexenc = index->is_valid() ? encode(index) << 3 : 0;
489 int baseenc = base->is_valid() ? encode(base) : 0;
490
491 if (base->is_valid()) {
492 if (index->is_valid()) {
493 assert(scale != Address::no_scale, "inconsistent address");
494 // [base + index*scale + disp]
495 if (disp == 0 && rtype == relocInfo::none &&
496 base != rbp LP64_ONLY(&& base != r13)) {
497 // [base + index*scale]
498 // [00 reg 100][ss index base]
499 assert(index != rsp, "illegal addressing mode");
500 emit_int8(0x04 | regenc);
501 emit_int8(scale << 6 | indexenc | baseenc);
502 } else if (emit_compressed_disp_byte(disp) && rtype == relocInfo::none) {
503 // [base + index*scale + imm8]
504 // [01 reg 100][ss index base] imm8
505 assert(index != rsp, "illegal addressing mode");
506 emit_int8(0x44 | regenc);
507 emit_int8(scale << 6 | indexenc | baseenc);
508 emit_int8(disp & 0xFF);
509 } else {
510 // [base + index*scale + disp32]
511 // [10 reg 100][ss index base] disp32
512 assert(index != rsp, "illegal addressing mode");
513 emit_int8(0x84 | regenc);
514 emit_int8(scale << 6 | indexenc | baseenc);
515 emit_data(disp, rspec, disp32_operand);
516 }
517 } else if (base == rsp LP64_ONLY(|| base == r12)) {
518 // [rsp + disp]
519 if (disp == 0 && rtype == relocInfo::none) {
520 // [rsp]
521 // [00 reg 100][00 100 100]
522 emit_int8(0x04 | regenc);
523 emit_int8(0x24);
524 } else if (emit_compressed_disp_byte(disp) && rtype == relocInfo::none) {
525 // [rsp + imm8]
526 // [01 reg 100][00 100 100] disp8
527 emit_int8(0x44 | regenc);
528 emit_int8(0x24);
529 emit_int8(disp & 0xFF);
530 } else {
531 // [rsp + imm32]
532 // [10 reg 100][00 100 100] disp32
533 emit_int8(0x84 | regenc);
534 emit_int8(0x24);
535 emit_data(disp, rspec, disp32_operand);
536 }
537 } else {
538 // [base + disp]
539 assert(base != rsp LP64_ONLY(&& base != r12), "illegal addressing mode");
540 if (disp == 0 && rtype == relocInfo::none &&
541 base != rbp LP64_ONLY(&& base != r13)) {
542 // [base]
543 // [00 reg base]
544 emit_int8(0x00 | regenc | baseenc);
545 } else if (emit_compressed_disp_byte(disp) && rtype == relocInfo::none) {
546 // [base + disp8]
547 // [01 reg base] disp8
548 emit_int8(0x40 | regenc | baseenc);
549 emit_int8(disp & 0xFF);
550 } else {
551 // [base + disp32]
552 // [10 reg base] disp32
553 emit_int8(0x80 | regenc | baseenc);
554 emit_data(disp, rspec, disp32_operand);
555 }
556 }
557 } else {
558 if (index->is_valid()) {
559 assert(scale != Address::no_scale, "inconsistent address");
560 // [index*scale + disp]
561 // [00 reg 100][ss index 101] disp32
562 assert(index != rsp, "illegal addressing mode");
563 emit_int8(0x04 | regenc);
564 emit_int8(scale << 6 | indexenc | 0x05);
565 emit_data(disp, rspec, disp32_operand);
566 } else if (rtype != relocInfo::none ) {
567 // [disp] (64bit) RIP-RELATIVE (32bit) abs
568 // [00 000 101] disp32
569
570 emit_int8(0x05 | regenc);
571 // Note that the RIP-rel. correction applies to the generated
572 // disp field, but _not_ to the target address in the rspec.
573
574 // disp was created by converting the target address minus the pc
575 // at the start of the instruction. That needs more correction here.
576 // intptr_t disp = target - next_ip;
577 assert(inst_mark() != NULL, "must be inside InstructionMark");
578 address next_ip = pc() + sizeof(int32_t) + rip_relative_correction;
579 int64_t adjusted = disp;
580 // Do rip-rel adjustment for 64bit
581 LP64_ONLY(adjusted -= (next_ip - inst_mark()));
582 assert(is_simm32(adjusted),
583 "must be 32bit offset (RIP relative address)");
584 emit_data((int32_t) adjusted, rspec, disp32_operand);
585
586 } else {
587 // 32bit never did this, did everything as the rip-rel/disp code above
588 // [disp] ABSOLUTE
589 // [00 reg 100][00 100 101] disp32
590 emit_int8(0x04 | regenc);
591 emit_int8(0x25);
592 emit_data(disp, rspec, disp32_operand);
593 }
594 }
595 }
596
597 void Assembler::emit_operand(XMMRegister reg, Register base, Register index,
598 Address::ScaleFactor scale, int disp,
599 RelocationHolder const& rspec) {
600 if (UseAVX > 2) {
601 int xreg_enc = reg->encoding();
602 if (xreg_enc > 15) {
603 XMMRegister new_reg = as_XMMRegister(xreg_enc & 0xf);
604 emit_operand((Register)new_reg, base, index, scale, disp, rspec);
605 return;
606 }
607 }
608 emit_operand((Register)reg, base, index, scale, disp, rspec);
609 }
610
611 void Assembler::emit_operand(XMMRegister reg, Register base, XMMRegister index,
1131 adr._rspec);
1132 }
1133 }
1134
1135 // MMX operations
1136 void Assembler::emit_operand(MMXRegister reg, Address adr) {
1137 assert(!adr.base_needs_rex() && !adr.index_needs_rex(), "no extended registers");
1138 emit_operand((Register)reg, adr._base, adr._index, adr._scale, adr._disp, adr._rspec);
1139 }
1140
1141 // work around gcc (3.2.1-7a) bug
1142 void Assembler::emit_operand(Address adr, MMXRegister reg) {
1143 assert(!adr.base_needs_rex() && !adr.index_needs_rex(), "no extended registers");
1144 emit_operand((Register)reg, adr._base, adr._index, adr._scale, adr._disp, adr._rspec);
1145 }
1146
1147
1148 void Assembler::emit_farith(int b1, int b2, int i) {
1149 assert(isByte(b1) && isByte(b2), "wrong opcode");
1150 assert(0 <= i && i < 8, "illegal stack offset");
1151 emit_int8(b1);
1152 emit_int8(b2 + i);
1153 }
1154
1155
1156 // Now the Assembler instructions (identical for 32/64 bits)
1157
1158 void Assembler::adcl(Address dst, int32_t imm32) {
1159 InstructionMark im(this);
1160 prefix(dst);
1161 emit_arith_operand(0x81, rdx, dst, imm32);
1162 }
1163
1164 void Assembler::adcl(Address dst, Register src) {
1165 InstructionMark im(this);
1166 prefix(dst, src);
1167 emit_int8(0x11);
1168 emit_operand(src, dst);
1169 }
1170
1171 void Assembler::adcl(Register dst, int32_t imm32) {
1172 prefix(dst);
1218 void Assembler::addl(Register dst, int32_t imm32) {
1219 prefix(dst);
1220 emit_arith(0x81, 0xC0, dst, imm32);
1221 }
1222
1223 void Assembler::addl(Register dst, Address src) {
1224 InstructionMark im(this);
1225 prefix(src, dst);
1226 emit_int8(0x03);
1227 emit_operand(dst, src);
1228 }
1229
1230 void Assembler::addl(Register dst, Register src) {
1231 (void) prefix_and_encode(dst->encoding(), src->encoding());
1232 emit_arith(0x03, 0xC0, dst, src);
1233 }
1234
1235 void Assembler::addr_nop_4() {
1236 assert(UseAddressNop, "no CPU support");
1237 // 4 bytes: NOP DWORD PTR [EAX+0]
1238 emit_int8(0x0F);
1239 emit_int8(0x1F);
1240 emit_int8(0x40); // emit_rm(cbuf, 0x1, EAX_enc, EAX_enc);
1241 emit_int8(0); // 8-bits offset (1 byte)
1242 }
1243
1244 void Assembler::addr_nop_5() {
1245 assert(UseAddressNop, "no CPU support");
1246 // 5 bytes: NOP DWORD PTR [EAX+EAX*0+0] 8-bits offset
1247 emit_int8(0x0F);
1248 emit_int8(0x1F);
1249 emit_int8(0x44); // emit_rm(cbuf, 0x1, EAX_enc, 0x4);
1250 emit_int8(0x00); // emit_rm(cbuf, 0x0, EAX_enc, EAX_enc);
1251 emit_int8(0); // 8-bits offset (1 byte)
1252 }
1253
1254 void Assembler::addr_nop_7() {
1255 assert(UseAddressNop, "no CPU support");
1256 // 7 bytes: NOP DWORD PTR [EAX+0] 32-bits offset
1257 emit_int8(0x0F);
1258 emit_int8(0x1F);
1259 emit_int8((unsigned char)0x80);
1260 // emit_rm(cbuf, 0x2, EAX_enc, EAX_enc);
1261 emit_int32(0); // 32-bits offset (4 bytes)
1262 }
1263
1264 void Assembler::addr_nop_8() {
1265 assert(UseAddressNop, "no CPU support");
1266 // 8 bytes: NOP DWORD PTR [EAX+EAX*0+0] 32-bits offset
1267 emit_int8(0x0F);
1268 emit_int8(0x1F);
1269 emit_int8((unsigned char)0x84);
1270 // emit_rm(cbuf, 0x2, EAX_enc, 0x4);
1271 emit_int8(0x00); // emit_rm(cbuf, 0x0, EAX_enc, EAX_enc);
1272 emit_int32(0); // 32-bits offset (4 bytes)
1273 }
1274
1275 void Assembler::addsd(XMMRegister dst, XMMRegister src) {
1276 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1277 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1278 attributes.set_rex_vex_w_reverted();
1279 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
1280 emit_int8(0x58);
1281 emit_int8((unsigned char)(0xC0 | encode));
1282 }
1283
1284 void Assembler::addsd(XMMRegister dst, Address src) {
1285 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1286 InstructionMark im(this);
1287 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1288 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
1289 attributes.set_rex_vex_w_reverted();
1290 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
1291 emit_int8(0x58);
1292 emit_operand(dst, src);
1293 }
1294
1295 void Assembler::addss(XMMRegister dst, XMMRegister src) {
1296 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1297 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1298 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1299 emit_int8(0x58);
1300 emit_int8((unsigned char)(0xC0 | encode));
1301 }
1302
1303 void Assembler::addss(XMMRegister dst, Address src) {
1304 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1305 InstructionMark im(this);
1306 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1307 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
1308 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1309 emit_int8(0x58);
1310 emit_operand(dst, src);
1311 }
1312
1313 void Assembler::aesdec(XMMRegister dst, Address src) {
1314 assert(VM_Version::supports_aes(), "");
1315 InstructionMark im(this);
1316 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
1317 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1318 emit_int8((unsigned char)0xDE);
1319 emit_operand(dst, src);
1320 }
1321
1322 void Assembler::aesdec(XMMRegister dst, XMMRegister src) {
1323 assert(VM_Version::supports_aes(), "");
1324 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
1325 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1326 emit_int8((unsigned char)0xDE);
1327 emit_int8(0xC0 | encode);
1328 }
1329
1330 void Assembler::vaesdec(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
1331 assert(VM_Version::supports_avx512_vaes(), "");
1332 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
1333 attributes.set_is_evex_instruction();
1334 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1335 emit_int8((unsigned char)0xDE);
1336 emit_int8((unsigned char)(0xC0 | encode));
1337 }
1338
1339
1340 void Assembler::aesdeclast(XMMRegister dst, Address src) {
1341 assert(VM_Version::supports_aes(), "");
1342 InstructionMark im(this);
1343 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
1344 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1345 emit_int8((unsigned char)0xDF);
1346 emit_operand(dst, src);
1347 }
1348
1349 void Assembler::aesdeclast(XMMRegister dst, XMMRegister src) {
1350 assert(VM_Version::supports_aes(), "");
1351 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
1352 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1353 emit_int8((unsigned char)0xDF);
1354 emit_int8((unsigned char)(0xC0 | encode));
1355 }
1356
1357 void Assembler::vaesdeclast(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
1358 assert(VM_Version::supports_avx512_vaes(), "");
1359 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
1360 attributes.set_is_evex_instruction();
1361 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1362 emit_int8((unsigned char)0xDF);
1363 emit_int8((unsigned char)(0xC0 | encode));
1364 }
1365
1366 void Assembler::aesenc(XMMRegister dst, Address src) {
1367 assert(VM_Version::supports_aes(), "");
1368 InstructionMark im(this);
1369 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
1370 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1371 emit_int8((unsigned char)0xDC);
1372 emit_operand(dst, src);
1373 }
1374
1375 void Assembler::aesenc(XMMRegister dst, XMMRegister src) {
1376 assert(VM_Version::supports_aes(), "");
1377 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
1378 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1379 emit_int8((unsigned char)0xDC);
1380 emit_int8(0xC0 | encode);
1381 }
1382
1383 void Assembler::vaesenc(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
1384 assert(VM_Version::supports_avx512_vaes(), "requires vaes support/enabling");
1385 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
1386 attributes.set_is_evex_instruction();
1387 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1388 emit_int8((unsigned char)0xDC);
1389 emit_int8((unsigned char)(0xC0 | encode));
1390 }
1391
1392 void Assembler::aesenclast(XMMRegister dst, Address src) {
1393 assert(VM_Version::supports_aes(), "");
1394 InstructionMark im(this);
1395 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
1396 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1397 emit_int8((unsigned char)0xDD);
1398 emit_operand(dst, src);
1399 }
1400
1401 void Assembler::aesenclast(XMMRegister dst, XMMRegister src) {
1402 assert(VM_Version::supports_aes(), "");
1403 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
1404 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1405 emit_int8((unsigned char)0xDD);
1406 emit_int8((unsigned char)(0xC0 | encode));
1407 }
1408
1409 void Assembler::vaesenclast(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
1410 assert(VM_Version::supports_avx512_vaes(), "requires vaes support/enabling");
1411 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
1412 attributes.set_is_evex_instruction();
1413 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1414 emit_int8((unsigned char)0xDD);
1415 emit_int8((unsigned char)(0xC0 | encode));
1416 }
1417
1418 void Assembler::andl(Address dst, int32_t imm32) {
1419 InstructionMark im(this);
1420 prefix(dst);
1421 emit_int8((unsigned char)0x81);
1422 emit_operand(rsp, dst, 4);
1423 emit_int32(imm32);
1424 }
1425
1426 void Assembler::andl(Register dst, int32_t imm32) {
1427 prefix(dst);
1428 emit_arith(0x81, 0xE0, dst, imm32);
1429 }
1430
1431 void Assembler::andl(Register dst, Address src) {
1432 InstructionMark im(this);
1433 prefix(src, dst);
1434 emit_int8(0x23);
1435 emit_operand(dst, src);
1436 }
1437
1438 void Assembler::andl(Register dst, Register src) {
1439 (void) prefix_and_encode(dst->encoding(), src->encoding());
1440 emit_arith(0x23, 0xC0, dst, src);
1441 }
1442
1443 void Assembler::andnl(Register dst, Register src1, Register src2) {
1444 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1445 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
1446 int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
1447 emit_int8((unsigned char)0xF2);
1448 emit_int8((unsigned char)(0xC0 | encode));
1449 }
1450
1451 void Assembler::andnl(Register dst, Register src1, Address src2) {
1452 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1453 InstructionMark im(this);
1454 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
1455 vex_prefix(src2, src1->encoding(), dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
1456 emit_int8((unsigned char)0xF2);
1457 emit_operand(dst, src2);
1458 }
1459
1460 void Assembler::bsfl(Register dst, Register src) {
1461 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1462 emit_int8(0x0F);
1463 emit_int8((unsigned char)0xBC);
1464 emit_int8((unsigned char)(0xC0 | encode));
1465 }
1466
1467 void Assembler::bsrl(Register dst, Register src) {
1468 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1469 emit_int8(0x0F);
1470 emit_int8((unsigned char)0xBD);
1471 emit_int8((unsigned char)(0xC0 | encode));
1472 }
1473
1474 void Assembler::bswapl(Register reg) { // bswap
1475 int encode = prefix_and_encode(reg->encoding());
1476 emit_int8(0x0F);
1477 emit_int8((unsigned char)(0xC8 | encode));
1478 }
1479
1480 void Assembler::blsil(Register dst, Register src) {
1481 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1482 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
1483 int encode = vex_prefix_and_encode(rbx->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
1484 emit_int8((unsigned char)0xF3);
1485 emit_int8((unsigned char)(0xC0 | encode));
1486 }
1487
1488 void Assembler::blsil(Register dst, Address src) {
1489 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1490 InstructionMark im(this);
1491 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
1492 vex_prefix(src, dst->encoding(), rbx->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
1493 emit_int8((unsigned char)0xF3);
1494 emit_operand(rbx, src);
1495 }
1496
1497 void Assembler::blsmskl(Register dst, Register src) {
1498 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1499 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
1500 int encode = vex_prefix_and_encode(rdx->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
1501 emit_int8((unsigned char)0xF3);
1502 emit_int8((unsigned char)(0xC0 | encode));
1503 }
1504
1505 void Assembler::blsmskl(Register dst, Address src) {
1506 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1507 InstructionMark im(this);
1508 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
1509 vex_prefix(src, dst->encoding(), rdx->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
1510 emit_int8((unsigned char)0xF3);
1511 emit_operand(rdx, src);
1512 }
1513
1514 void Assembler::blsrl(Register dst, Register src) {
1515 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1516 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
1517 int encode = vex_prefix_and_encode(rcx->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
1518 emit_int8((unsigned char)0xF3);
1519 emit_int8((unsigned char)(0xC0 | encode));
1520 }
1521
1522 void Assembler::blsrl(Register dst, Address src) {
1523 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1524 InstructionMark im(this);
1525 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
1526 vex_prefix(src, dst->encoding(), rcx->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
1527 emit_int8((unsigned char)0xF3);
1528 emit_operand(rcx, src);
1529 }
1530
1531 void Assembler::call(Label& L, relocInfo::relocType rtype) {
1532 // suspect disp32 is always good
1533 int operand = LP64_ONLY(disp32_operand) NOT_LP64(imm_operand);
1534
1535 if (L.is_bound()) {
1536 const int long_size = 5;
1537 int offs = (int)( target(L) - pc() );
1538 assert(offs <= 0, "assembler error");
1539 InstructionMark im(this);
1540 // 1110 1000 #32-bit disp
1541 emit_int8((unsigned char)0xE8);
1542 emit_data(offs - long_size, rtype, operand);
1543 } else {
1544 InstructionMark im(this);
1545 // 1110 1000 #32-bit disp
1546 L.add_patch_at(code(), locator());
1547
1548 emit_int8((unsigned char)0xE8);
1549 emit_data(int(0), rtype, operand);
1550 }
1551 }
1552
1553 void Assembler::call(Register dst) {
1554 int encode = prefix_and_encode(dst->encoding());
1555 emit_int8((unsigned char)0xFF);
1556 emit_int8((unsigned char)(0xD0 | encode));
1557 }
1558
1559
1560 void Assembler::call(Address adr) {
1561 InstructionMark im(this);
1562 prefix(adr);
1563 emit_int8((unsigned char)0xFF);
1564 emit_operand(rdx, adr);
1565 }
1566
1567 void Assembler::call_literal(address entry, RelocationHolder const& rspec) {
1568 InstructionMark im(this);
1569 emit_int8((unsigned char)0xE8);
1570 intptr_t disp = entry - (pc() + sizeof(int32_t));
1571 // Entry is NULL in case of a scratch emit.
1572 assert(entry == NULL || is_simm32(disp), "disp=" INTPTR_FORMAT " must be 32bit offset (call2)", disp);
1573 // Technically, should use call32_operand, but this format is
1574 // implied by the fact that we're emitting a call instruction.
1575
1576 int operand = LP64_ONLY(disp32_operand) NOT_LP64(call32_operand);
1577 emit_data((int) disp, rspec, operand);
1578 }
1579
1580 void Assembler::cdql() {
1581 emit_int8((unsigned char)0x99);
1582 }
1583
1584 void Assembler::cld() {
1585 emit_int8((unsigned char)0xFC);
1586 }
1587
1588 void Assembler::cmovl(Condition cc, Register dst, Register src) {
1589 NOT_LP64(guarantee(VM_Version::supports_cmov(), "illegal instruction"));
1590 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1591 emit_int8(0x0F);
1592 emit_int8(0x40 | cc);
1593 emit_int8((unsigned char)(0xC0 | encode));
1594 }
1595
1596
1597 void Assembler::cmovl(Condition cc, Register dst, Address src) {
1598 NOT_LP64(guarantee(VM_Version::supports_cmov(), "illegal instruction"));
1599 prefix(src, dst);
1600 emit_int8(0x0F);
1601 emit_int8(0x40 | cc);
1602 emit_operand(dst, src);
1603 }
1604
1605 void Assembler::cmpb(Address dst, int imm8) {
1606 InstructionMark im(this);
1607 prefix(dst);
1608 emit_int8((unsigned char)0x80);
1609 emit_operand(rdi, dst, 1);
1610 emit_int8(imm8);
1611 }
1612
1613 void Assembler::cmpl(Address dst, int32_t imm32) {
1614 InstructionMark im(this);
1615 prefix(dst);
1616 emit_int8((unsigned char)0x81);
1617 emit_operand(rdi, dst, 4);
1618 emit_int32(imm32);
1619 }
1620
1621 void Assembler::cmpl(Register dst, int32_t imm32) {
1622 prefix(dst);
1623 emit_arith(0x81, 0xF8, dst, imm32);
1624 }
1625
1626 void Assembler::cmpl(Register dst, Register src) {
1627 (void) prefix_and_encode(dst->encoding(), src->encoding());
1628 emit_arith(0x3B, 0xC0, dst, src);
1629 }
1630
1631 void Assembler::cmpl(Register dst, Address src) {
1632 InstructionMark im(this);
1633 prefix(src, dst);
1634 emit_int8((unsigned char)0x3B);
1635 emit_operand(dst, src);
1636 }
1637
1638 void Assembler::cmpw(Address dst, int imm16) {
1639 InstructionMark im(this);
1640 assert(!dst.base_needs_rex() && !dst.index_needs_rex(), "no extended registers");
1641 emit_int8(0x66);
1642 emit_int8((unsigned char)0x81);
1643 emit_operand(rdi, dst, 2);
1644 emit_int16(imm16);
1645 }
1646
1647 // The 32-bit cmpxchg compares the value at adr with the contents of rax,
1648 // and stores reg into adr if so; otherwise, the value at adr is loaded into rax,.
1649 // The ZF is set if the compared values were equal, and cleared otherwise.
1650 void Assembler::cmpxchgl(Register reg, Address adr) { // cmpxchg
1651 InstructionMark im(this);
1652 prefix(adr, reg);
1653 emit_int8(0x0F);
1654 emit_int8((unsigned char)0xB1);
1655 emit_operand(reg, adr);
1656 }
1657
1658 // The 8-bit cmpxchg compares the value at adr with the contents of rax,
1659 // and stores reg into adr if so; otherwise, the value at adr is loaded into rax,.
1660 // The ZF is set if the compared values were equal, and cleared otherwise.
1661 void Assembler::cmpxchgb(Register reg, Address adr) { // cmpxchg
1662 InstructionMark im(this);
1663 prefix(adr, reg, true);
1664 emit_int8(0x0F);
1665 emit_int8((unsigned char)0xB0);
1666 emit_operand(reg, adr);
1667 }
1668
1669 void Assembler::comisd(XMMRegister dst, Address src) {
1670 // NOTE: dbx seems to decode this as comiss even though the
1671 // 0x66 is there. Strangly ucomisd comes out correct
1672 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1673 InstructionMark im(this);
1674 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);;
1675 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
1676 attributes.set_rex_vex_w_reverted();
1677 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
1678 emit_int8(0x2F);
1679 emit_operand(dst, src);
1680 }
1681
1682 void Assembler::comisd(XMMRegister dst, XMMRegister src) {
1683 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1684 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1685 attributes.set_rex_vex_w_reverted();
1686 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
1687 emit_int8(0x2F);
1688 emit_int8((unsigned char)(0xC0 | encode));
1689 }
1690
1691 void Assembler::comiss(XMMRegister dst, Address src) {
1692 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1693 InstructionMark im(this);
1694 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1695 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
1696 simd_prefix(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
1697 emit_int8(0x2F);
1698 emit_operand(dst, src);
1699 }
1700
1701 void Assembler::comiss(XMMRegister dst, XMMRegister src) {
1702 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1703 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1704 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
1705 emit_int8(0x2F);
1706 emit_int8((unsigned char)(0xC0 | encode));
1707 }
1708
1709 void Assembler::cpuid() {
1710 emit_int8(0x0F);
1711 emit_int8((unsigned char)0xA2);
1712 }
1713
1714 // Opcode / Instruction Op / En 64 - Bit Mode Compat / Leg Mode Description Implemented
1715 // F2 0F 38 F0 / r CRC32 r32, r / m8 RM Valid Valid Accumulate CRC32 on r / m8. v
1716 // F2 REX 0F 38 F0 / r CRC32 r32, r / m8* RM Valid N.E. Accumulate CRC32 on r / m8. -
1717 // F2 REX.W 0F 38 F0 / r CRC32 r64, r / m8 RM Valid N.E. Accumulate CRC32 on r / m8. -
1718 //
1719 // F2 0F 38 F1 / r CRC32 r32, r / m16 RM Valid Valid Accumulate CRC32 on r / m16. v
1720 //
1721 // F2 0F 38 F1 / r CRC32 r32, r / m32 RM Valid Valid Accumulate CRC32 on r / m32. v
1722 //
1723 // F2 REX.W 0F 38 F1 / r CRC32 r64, r / m64 RM Valid N.E. Accumulate CRC32 on r / m64. v
1724 void Assembler::crc32(Register crc, Register v, int8_t sizeInBytes) {
1725 assert(VM_Version::supports_sse4_2(), "");
1726 int8_t w = 0x01;
1727 Prefix p = Prefix_EMPTY;
1728
1729 emit_int8((int8_t)0xF2);
1730 switch (sizeInBytes) {
1731 case 1:
1738 // This instruction is not valid in 32 bits
1739 // Note:
1740 // http://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-software-developer-instruction-set-reference-manual-325383.pdf
1741 //
1742 // Page B - 72 Vol. 2C says
1743 // qwreg2 to qwreg 1111 0010 : 0100 1R0B : 0000 1111 : 0011 1000 : 1111 0000 : 11 qwreg1 qwreg2
1744 // mem64 to qwreg 1111 0010 : 0100 1R0B : 0000 1111 : 0011 1000 : 1111 0000 : mod qwreg r / m
1745 // F0!!!
1746 // while 3 - 208 Vol. 2A
1747 // F2 REX.W 0F 38 F1 / r CRC32 r64, r / m64 RM Valid N.E.Accumulate CRC32 on r / m64.
1748 //
1749 // the 0 on a last bit is reserved for a different flavor of this instruction :
1750 // F2 REX.W 0F 38 F0 / r CRC32 r64, r / m8 RM Valid N.E.Accumulate CRC32 on r / m8.
1751 p = REX_W;
1752 break;
1753 default:
1754 assert(0, "Unsupported value for a sizeInBytes argument");
1755 break;
1756 }
1757 LP64_ONLY(prefix(crc, v, p);)
1758 emit_int8((int8_t)0x0F);
1759 emit_int8(0x38);
1760 emit_int8((int8_t)(0xF0 | w));
1761 emit_int8(0xC0 | ((crc->encoding() & 0x7) << 3) | (v->encoding() & 7));
1762 }
1763
1764 void Assembler::crc32(Register crc, Address adr, int8_t sizeInBytes) {
1765 assert(VM_Version::supports_sse4_2(), "");
1766 InstructionMark im(this);
1767 int8_t w = 0x01;
1768 Prefix p = Prefix_EMPTY;
1769
1770 emit_int8((int8_t)0xF2);
1771 switch (sizeInBytes) {
1772 case 1:
1773 w = 0;
1774 break;
1775 case 2:
1776 case 4:
1777 break;
1778 LP64_ONLY(case 8:)
1779 // This instruction is not valid in 32 bits
1780 p = REX_W;
1781 break;
1782 default:
1783 assert(0, "Unsupported value for a sizeInBytes argument");
1784 break;
1785 }
1786 LP64_ONLY(prefix(crc, adr, p);)
1787 emit_int8((int8_t)0x0F);
1788 emit_int8(0x38);
1789 emit_int8((int8_t)(0xF0 | w));
1790 emit_operand(crc, adr);
1791 }
1792
1793 void Assembler::cvtdq2pd(XMMRegister dst, XMMRegister src) {
1794 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1795 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
1796 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1797 emit_int8((unsigned char)0xE6);
1798 emit_int8((unsigned char)(0xC0 | encode));
1799 }
1800
1801 void Assembler::cvtdq2ps(XMMRegister dst, XMMRegister src) {
1802 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1803 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
1804 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
1805 emit_int8(0x5B);
1806 emit_int8((unsigned char)(0xC0 | encode));
1807 }
1808
1809 void Assembler::cvtsd2ss(XMMRegister dst, XMMRegister src) {
1810 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1811 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1812 attributes.set_rex_vex_w_reverted();
1813 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
1814 emit_int8(0x5A);
1815 emit_int8((unsigned char)(0xC0 | encode));
1816 }
1817
1818 void Assembler::cvtsd2ss(XMMRegister dst, Address src) {
1819 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1820 InstructionMark im(this);
1821 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1822 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
1823 attributes.set_rex_vex_w_reverted();
1824 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
1825 emit_int8(0x5A);
1826 emit_operand(dst, src);
1827 }
1828
1829 void Assembler::cvtsi2sdl(XMMRegister dst, Register src) {
1830 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1831 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1832 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
1833 emit_int8(0x2A);
1834 emit_int8((unsigned char)(0xC0 | encode));
1835 }
1836
1837 void Assembler::cvtsi2sdl(XMMRegister dst, Address src) {
1838 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1839 InstructionMark im(this);
1840 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1841 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
1842 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
1843 emit_int8(0x2A);
1844 emit_operand(dst, src);
1845 }
1846
1847 void Assembler::cvtsi2ssl(XMMRegister dst, Register src) {
1848 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1849 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1850 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1851 emit_int8(0x2A);
1852 emit_int8((unsigned char)(0xC0 | encode));
1853 }
1854
1855 void Assembler::cvtsi2ssl(XMMRegister dst, Address src) {
1856 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1857 InstructionMark im(this);
1858 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1859 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
1860 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1861 emit_int8(0x2A);
1862 emit_operand(dst, src);
1863 }
1864
1865 void Assembler::cvtsi2ssq(XMMRegister dst, Register src) {
1866 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1867 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1868 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1869 emit_int8(0x2A);
1870 emit_int8((unsigned char)(0xC0 | encode));
1871 }
1872
1873 void Assembler::cvtss2sd(XMMRegister dst, XMMRegister src) {
1874 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1875 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1876 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1877 emit_int8(0x5A);
1878 emit_int8((unsigned char)(0xC0 | encode));
1879 }
1880
1881 void Assembler::cvtss2sd(XMMRegister dst, Address src) {
1882 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1883 InstructionMark im(this);
1884 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1885 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
1886 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1887 emit_int8(0x5A);
1888 emit_operand(dst, src);
1889 }
1890
1891
1892 void Assembler::cvttsd2sil(Register dst, XMMRegister src) {
1893 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1894 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1895 int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
1896 emit_int8(0x2C);
1897 emit_int8((unsigned char)(0xC0 | encode));
1898 }
1899
1900 void Assembler::cvttss2sil(Register dst, XMMRegister src) {
1901 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1902 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1903 int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1904 emit_int8(0x2C);
1905 emit_int8((unsigned char)(0xC0 | encode));
1906 }
1907
1908 void Assembler::cvttpd2dq(XMMRegister dst, XMMRegister src) {
1909 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1910 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_128bit;
1911 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
1912 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
1913 emit_int8((unsigned char)0xE6);
1914 emit_int8((unsigned char)(0xC0 | encode));
1915 }
1916
1917 void Assembler::pabsb(XMMRegister dst, XMMRegister src) {
1918 assert(VM_Version::supports_ssse3(), "");
1919 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
1920 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1921 emit_int8(0x1C);
1922 emit_int8((unsigned char)(0xC0 | encode));
1923 }
1924
1925 void Assembler::pabsw(XMMRegister dst, XMMRegister src) {
1926 assert(VM_Version::supports_ssse3(), "");
1927 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
1928 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1929 emit_int8(0x1D);
1930 emit_int8((unsigned char)(0xC0 | encode));
1931 }
1932
1933 void Assembler::pabsd(XMMRegister dst, XMMRegister src) {
1934 assert(VM_Version::supports_ssse3(), "");
1935 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
1936 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1937 emit_int8(0x1E);
1938 emit_int8((unsigned char)(0xC0 | encode));
1939 }
1940
1941 void Assembler::vpabsb(XMMRegister dst, XMMRegister src, int vector_len) {
1942 assert(vector_len == AVX_128bit? VM_Version::supports_avx() :
1943 vector_len == AVX_256bit? VM_Version::supports_avx2() :
1944 vector_len == AVX_512bit? VM_Version::supports_avx512bw() : 0, "");
1945 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
1946 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1947 emit_int8((unsigned char)0x1C);
1948 emit_int8((unsigned char)(0xC0 | encode));
1949 }
1950
1951 void Assembler::vpabsw(XMMRegister dst, XMMRegister src, int vector_len) {
1952 assert(vector_len == AVX_128bit? VM_Version::supports_avx() :
1953 vector_len == AVX_256bit? VM_Version::supports_avx2() :
1954 vector_len == AVX_512bit? VM_Version::supports_avx512bw() : 0, "");
1955 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
1956 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1957 emit_int8((unsigned char)0x1D);
1958 emit_int8((unsigned char)(0xC0 | encode));
1959 }
1960
1961 void Assembler::vpabsd(XMMRegister dst, XMMRegister src, int vector_len) {
1962 assert(vector_len == AVX_128bit? VM_Version::supports_avx() :
1963 vector_len == AVX_256bit? VM_Version::supports_avx2() :
1964 vector_len == AVX_512bit? VM_Version::supports_evex() : 0, "");
1965 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
1966 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1967 emit_int8((unsigned char)0x1E);
1968 emit_int8((unsigned char)(0xC0 | encode));
1969 }
1970
1971 void Assembler::evpabsq(XMMRegister dst, XMMRegister src, int vector_len) {
1972 assert(UseAVX > 2, "");
1973 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
1974 attributes.set_is_evex_instruction();
1975 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1976 emit_int8((unsigned char)0x1F);
1977 emit_int8((unsigned char)(0xC0 | encode));
1978 }
1979
1980 void Assembler::decl(Address dst) {
1981 // Don't use it directly. Use MacroAssembler::decrement() instead.
1982 InstructionMark im(this);
1983 prefix(dst);
1984 emit_int8((unsigned char)0xFF);
1985 emit_operand(rcx, dst);
1986 }
1987
1988 void Assembler::divsd(XMMRegister dst, Address src) {
1989 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1990 InstructionMark im(this);
1991 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1992 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
1993 attributes.set_rex_vex_w_reverted();
1994 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
1995 emit_int8(0x5E);
1996 emit_operand(dst, src);
1997 }
1998
1999 void Assembler::divsd(XMMRegister dst, XMMRegister src) {
2000 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2001 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2002 attributes.set_rex_vex_w_reverted();
2003 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2004 emit_int8(0x5E);
2005 emit_int8((unsigned char)(0xC0 | encode));
2006 }
2007
2008 void Assembler::divss(XMMRegister dst, Address src) {
2009 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2010 InstructionMark im(this);
2011 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2012 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
2013 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2014 emit_int8(0x5E);
2015 emit_operand(dst, src);
2016 }
2017
2018 void Assembler::divss(XMMRegister dst, XMMRegister src) {
2019 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2020 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2021 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2022 emit_int8(0x5E);
2023 emit_int8((unsigned char)(0xC0 | encode));
2024 }
2025
2026 void Assembler::emms() {
2027 NOT_LP64(assert(VM_Version::supports_mmx(), ""));
2028 emit_int8(0x0F);
2029 emit_int8(0x77);
2030 }
2031
2032 void Assembler::hlt() {
2033 emit_int8((unsigned char)0xF4);
2034 }
2035
2036 void Assembler::idivl(Register src) {
2037 int encode = prefix_and_encode(src->encoding());
2038 emit_int8((unsigned char)0xF7);
2039 emit_int8((unsigned char)(0xF8 | encode));
2040 }
2041
2042 void Assembler::divl(Register src) { // Unsigned
2043 int encode = prefix_and_encode(src->encoding());
2044 emit_int8((unsigned char)0xF7);
2045 emit_int8((unsigned char)(0xF0 | encode));
2046 }
2047
2048 void Assembler::imull(Register src) {
2049 int encode = prefix_and_encode(src->encoding());
2050 emit_int8((unsigned char)0xF7);
2051 emit_int8((unsigned char)(0xE8 | encode));
2052 }
2053
2054 void Assembler::imull(Register dst, Register src) {
2055 int encode = prefix_and_encode(dst->encoding(), src->encoding());
2056 emit_int8(0x0F);
2057 emit_int8((unsigned char)0xAF);
2058 emit_int8((unsigned char)(0xC0 | encode));
2059 }
2060
2061
2062 void Assembler::imull(Register dst, Register src, int value) {
2063 int encode = prefix_and_encode(dst->encoding(), src->encoding());
2064 if (is8bit(value)) {
2065 emit_int8(0x6B);
2066 emit_int8((unsigned char)(0xC0 | encode));
2067 emit_int8(value & 0xFF);
2068 } else {
2069 emit_int8(0x69);
2070 emit_int8((unsigned char)(0xC0 | encode));
2071 emit_int32(value);
2072 }
2073 }
2074
2075 void Assembler::imull(Register dst, Address src) {
2076 InstructionMark im(this);
2077 prefix(src, dst);
2078 emit_int8(0x0F);
2079 emit_int8((unsigned char) 0xAF);
2080 emit_operand(dst, src);
2081 }
2082
2083
2084 void Assembler::incl(Address dst) {
2085 // Don't use it directly. Use MacroAssembler::increment() instead.
2086 InstructionMark im(this);
2087 prefix(dst);
2088 emit_int8((unsigned char)0xFF);
2089 emit_operand(rax, dst);
2090 }
2091
2092 void Assembler::jcc(Condition cc, Label& L, bool maybe_short) {
2093 InstructionMark im(this);
2094 assert((0 <= cc) && (cc < 16), "illegal cc");
2095 if (L.is_bound()) {
2096 address dst = target(L);
2097 assert(dst != NULL, "jcc most probably wrong");
2098
2099 const int short_size = 2;
2100 const int long_size = 6;
2101 intptr_t offs = (intptr_t)dst - (intptr_t)pc();
2102 if (maybe_short && is8bit(offs - short_size)) {
2103 // 0111 tttn #8-bit disp
2104 emit_int8(0x70 | cc);
2105 emit_int8((offs - short_size) & 0xFF);
2106 } else {
2107 // 0000 1111 1000 tttn #32-bit disp
2108 assert(is_simm32(offs - long_size),
2109 "must be 32bit offset (call4)");
2110 emit_int8(0x0F);
2111 emit_int8((unsigned char)(0x80 | cc));
2112 emit_int32(offs - long_size);
2113 }
2114 } else {
2115 // Note: could eliminate cond. jumps to this jump if condition
2116 // is the same however, seems to be rather unlikely case.
2117 // Note: use jccb() if label to be bound is very close to get
2118 // an 8-bit displacement
2119 L.add_patch_at(code(), locator());
2120 emit_int8(0x0F);
2121 emit_int8((unsigned char)(0x80 | cc));
2122 emit_int32(0);
2123 }
2124 }
2125
2126 void Assembler::jccb_0(Condition cc, Label& L, const char* file, int line) {
2127 if (L.is_bound()) {
2128 const int short_size = 2;
2129 address entry = target(L);
2130 #ifdef ASSERT
2131 intptr_t dist = (intptr_t)entry - ((intptr_t)pc() + short_size);
2132 intptr_t delta = short_branch_delta();
2133 if (delta != 0) {
2134 dist += (dist < 0 ? (-delta) :delta);
2135 }
2136 assert(is8bit(dist), "Dispacement too large for a short jmp at %s:%d", file, line);
2137 #endif
2138 intptr_t offs = (intptr_t)entry - (intptr_t)pc();
2139 // 0111 tttn #8-bit disp
2140 emit_int8(0x70 | cc);
2141 emit_int8((offs - short_size) & 0xFF);
2142 } else {
2143 InstructionMark im(this);
2144 L.add_patch_at(code(), locator(), file, line);
2145 emit_int8(0x70 | cc);
2146 emit_int8(0);
2147 }
2148 }
2149
2150 void Assembler::jmp(Address adr) {
2151 InstructionMark im(this);
2152 prefix(adr);
2153 emit_int8((unsigned char)0xFF);
2154 emit_operand(rsp, adr);
2155 }
2156
2157 void Assembler::jmp(Label& L, bool maybe_short) {
2158 if (L.is_bound()) {
2159 address entry = target(L);
2160 assert(entry != NULL, "jmp most probably wrong");
2161 InstructionMark im(this);
2162 const int short_size = 2;
2163 const int long_size = 5;
2164 intptr_t offs = entry - pc();
2165 if (maybe_short && is8bit(offs - short_size)) {
2166 emit_int8((unsigned char)0xEB);
2167 emit_int8((offs - short_size) & 0xFF);
2168 } else {
2169 emit_int8((unsigned char)0xE9);
2170 emit_int32(offs - long_size);
2171 }
2172 } else {
2173 // By default, forward jumps are always 32-bit displacements, since
2174 // we can't yet know where the label will be bound. If you're sure that
2175 // the forward jump will not run beyond 256 bytes, use jmpb to
2176 // force an 8-bit displacement.
2177 InstructionMark im(this);
2178 L.add_patch_at(code(), locator());
2179 emit_int8((unsigned char)0xE9);
2180 emit_int32(0);
2181 }
2182 }
2183
2184 void Assembler::jmp(Register entry) {
2185 int encode = prefix_and_encode(entry->encoding());
2186 emit_int8((unsigned char)0xFF);
2187 emit_int8((unsigned char)(0xE0 | encode));
2188 }
2189
2190 void Assembler::jmp_literal(address dest, RelocationHolder const& rspec) {
2191 InstructionMark im(this);
2192 emit_int8((unsigned char)0xE9);
2193 assert(dest != NULL, "must have a target");
2194 intptr_t disp = dest - (pc() + sizeof(int32_t));
2195 assert(is_simm32(disp), "must be 32bit offset (jmp)");
2196 emit_data(disp, rspec.reloc(), call32_operand);
2197 }
2198
2199 void Assembler::jmpb_0(Label& L, const char* file, int line) {
2200 if (L.is_bound()) {
2201 const int short_size = 2;
2202 address entry = target(L);
2203 assert(entry != NULL, "jmp most probably wrong");
2204 #ifdef ASSERT
2205 intptr_t dist = (intptr_t)entry - ((intptr_t)pc() + short_size);
2206 intptr_t delta = short_branch_delta();
2207 if (delta != 0) {
2208 dist += (dist < 0 ? (-delta) :delta);
2209 }
2210 assert(is8bit(dist), "Dispacement too large for a short jmp at %s:%d", file, line);
2211 #endif
2212 intptr_t offs = entry - pc();
2213 emit_int8((unsigned char)0xEB);
2214 emit_int8((offs - short_size) & 0xFF);
2215 } else {
2216 InstructionMark im(this);
2217 L.add_patch_at(code(), locator(), file, line);
2218 emit_int8((unsigned char)0xEB);
2219 emit_int8(0);
2220 }
2221 }
2222
2223 void Assembler::ldmxcsr( Address src) {
2224 if (UseAVX > 0 ) {
2225 InstructionMark im(this);
2226 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2227 vex_prefix(src, 0, 0, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2228 emit_int8((unsigned char)0xAE);
2229 emit_operand(as_Register(2), src);
2230 } else {
2231 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2232 InstructionMark im(this);
2233 prefix(src);
2234 emit_int8(0x0F);
2235 emit_int8((unsigned char)0xAE);
2236 emit_operand(as_Register(2), src);
2237 }
2238 }
2239
2240 void Assembler::leal(Register dst, Address src) {
2241 InstructionMark im(this);
2242 #ifdef _LP64
2243 emit_int8(0x67); // addr32
2244 prefix(src, dst);
2245 #endif // LP64
2246 emit_int8((unsigned char)0x8D);
2247 emit_operand(dst, src);
2248 }
2249
2250 void Assembler::lfence() {
2251 emit_int8(0x0F);
2252 emit_int8((unsigned char)0xAE);
2253 emit_int8((unsigned char)0xE8);
2254 }
2255
2256 void Assembler::lock() {
2257 emit_int8((unsigned char)0xF0);
2258 }
2259
2260 void Assembler::lzcntl(Register dst, Register src) {
2261 assert(VM_Version::supports_lzcnt(), "encoding is treated as BSR");
2262 emit_int8((unsigned char)0xF3);
2263 int encode = prefix_and_encode(dst->encoding(), src->encoding());
2264 emit_int8(0x0F);
2265 emit_int8((unsigned char)0xBD);
2266 emit_int8((unsigned char)(0xC0 | encode));
2267 }
2268
2269 // Emit mfence instruction
2270 void Assembler::mfence() {
2271 NOT_LP64(assert(VM_Version::supports_sse2(), "unsupported");)
2272 emit_int8(0x0F);
2273 emit_int8((unsigned char)0xAE);
2274 emit_int8((unsigned char)0xF0);
2275 }
2276
2277 // Emit sfence instruction
2278 void Assembler::sfence() {
2279 NOT_LP64(assert(VM_Version::supports_sse2(), "unsupported");)
2280 emit_int8(0x0F);
2281 emit_int8((unsigned char)0xAE);
2282 emit_int8((unsigned char)0xF8);
2283 }
2284
2285 void Assembler::mov(Register dst, Register src) {
2286 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src));
2287 }
2288
2289 void Assembler::movapd(XMMRegister dst, XMMRegister src) {
2290 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2291 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_128bit;
2292 InstructionAttr attributes(vector_len, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
2293 attributes.set_rex_vex_w_reverted();
2294 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2295 emit_int8(0x28);
2296 emit_int8((unsigned char)(0xC0 | encode));
2297 }
2298
2299 void Assembler::movaps(XMMRegister dst, XMMRegister src) {
2300 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2301 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_128bit;
2302 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
2303 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2304 emit_int8(0x28);
2305 emit_int8((unsigned char)(0xC0 | encode));
2306 }
2307
2308 void Assembler::movlhps(XMMRegister dst, XMMRegister src) {
2309 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2310 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
2311 int encode = simd_prefix_and_encode(dst, src, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2312 emit_int8(0x16);
2313 emit_int8((unsigned char)(0xC0 | encode));
2314 }
2315
2316 void Assembler::movb(Register dst, Address src) {
2317 NOT_LP64(assert(dst->has_byte_register(), "must have byte register"));
2318 InstructionMark im(this);
2319 prefix(src, dst, true);
2320 emit_int8((unsigned char)0x8A);
2321 emit_operand(dst, src);
2322 }
2323
2324 void Assembler::movddup(XMMRegister dst, XMMRegister src) {
2325 NOT_LP64(assert(VM_Version::supports_sse3(), ""));
2326 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_128bit;
2327 InstructionAttr attributes(vector_len, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
2328 attributes.set_rex_vex_w_reverted();
2329 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2330 emit_int8(0x12);
2331 emit_int8(0xC0 | encode);
2332 }
2333
2334 void Assembler::kmovbl(KRegister dst, Register src) {
2335 assert(VM_Version::supports_avx512dq(), "");
2336 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2337 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2338 emit_int8((unsigned char)0x92);
2339 emit_int8((unsigned char)(0xC0 | encode));
2340 }
2341
2342 void Assembler::kmovbl(Register dst, KRegister src) {
2343 assert(VM_Version::supports_avx512dq(), "");
2344 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2345 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2346 emit_int8((unsigned char)0x93);
2347 emit_int8((unsigned char)(0xC0 | encode));
2348 }
2349
2350 void Assembler::kmovwl(KRegister dst, Register src) {
2351 assert(VM_Version::supports_evex(), "");
2352 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2353 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2354 emit_int8((unsigned char)0x92);
2355 emit_int8((unsigned char)(0xC0 | encode));
2356 }
2357
2358 void Assembler::kmovwl(Register dst, KRegister src) {
2359 assert(VM_Version::supports_evex(), "");
2360 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2361 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2362 emit_int8((unsigned char)0x93);
2363 emit_int8((unsigned char)(0xC0 | encode));
2364 }
2365
2366 void Assembler::kmovwl(KRegister dst, Address src) {
2367 assert(VM_Version::supports_evex(), "");
2368 InstructionMark im(this);
2369 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2370 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2371 emit_int8((unsigned char)0x90);
2372 emit_operand((Register)dst, src);
2373 }
2374
2375 void Assembler::kmovdl(KRegister dst, Register src) {
2376 assert(VM_Version::supports_avx512bw(), "");
2377 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2378 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2379 emit_int8((unsigned char)0x92);
2380 emit_int8((unsigned char)(0xC0 | encode));
2381 }
2382
2383 void Assembler::kmovdl(Register dst, KRegister src) {
2384 assert(VM_Version::supports_avx512bw(), "");
2385 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2386 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2387 emit_int8((unsigned char)0x93);
2388 emit_int8((unsigned char)(0xC0 | encode));
2389 }
2390
2391 void Assembler::kmovql(KRegister dst, KRegister src) {
2392 assert(VM_Version::supports_avx512bw(), "");
2393 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2394 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2395 emit_int8((unsigned char)0x90);
2396 emit_int8((unsigned char)(0xC0 | encode));
2397 }
2398
2399 void Assembler::kmovql(KRegister dst, Address src) {
2400 assert(VM_Version::supports_avx512bw(), "");
2401 InstructionMark im(this);
2402 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2403 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2404 emit_int8((unsigned char)0x90);
2405 emit_operand((Register)dst, src);
2406 }
2407
2408 void Assembler::kmovql(Address dst, KRegister src) {
2409 assert(VM_Version::supports_avx512bw(), "");
2410 InstructionMark im(this);
2411 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2412 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2413 emit_int8((unsigned char)0x90);
2414 emit_operand((Register)src, dst);
2415 }
2416
2417 void Assembler::kmovql(KRegister dst, Register src) {
2418 assert(VM_Version::supports_avx512bw(), "");
2419 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2420 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2421 emit_int8((unsigned char)0x92);
2422 emit_int8((unsigned char)(0xC0 | encode));
2423 }
2424
2425 void Assembler::kmovql(Register dst, KRegister src) {
2426 assert(VM_Version::supports_avx512bw(), "");
2427 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2428 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2429 emit_int8((unsigned char)0x93);
2430 emit_int8((unsigned char)(0xC0 | encode));
2431 }
2432
2433 void Assembler::knotwl(KRegister dst, KRegister src) {
2434 assert(VM_Version::supports_evex(), "");
2435 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2436 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2437 emit_int8((unsigned char)0x44);
2438 emit_int8((unsigned char)(0xC0 | encode));
2439 }
2440
2441 // This instruction produces ZF or CF flags
2442 void Assembler::kortestbl(KRegister src1, KRegister src2) {
2443 assert(VM_Version::supports_avx512dq(), "");
2444 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2445 int encode = vex_prefix_and_encode(src1->encoding(), 0, src2->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2446 emit_int8((unsigned char)0x98);
2447 emit_int8((unsigned char)(0xC0 | encode));
2448 }
2449
2450 // This instruction produces ZF or CF flags
2451 void Assembler::kortestwl(KRegister src1, KRegister src2) {
2452 assert(VM_Version::supports_evex(), "");
2453 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2454 int encode = vex_prefix_and_encode(src1->encoding(), 0, src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2455 emit_int8((unsigned char)0x98);
2456 emit_int8((unsigned char)(0xC0 | encode));
2457 }
2458
2459 // This instruction produces ZF or CF flags
2460 void Assembler::kortestdl(KRegister src1, KRegister src2) {
2461 assert(VM_Version::supports_avx512bw(), "");
2462 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2463 int encode = vex_prefix_and_encode(src1->encoding(), 0, src2->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2464 emit_int8((unsigned char)0x98);
2465 emit_int8((unsigned char)(0xC0 | encode));
2466 }
2467
2468 // This instruction produces ZF or CF flags
2469 void Assembler::kortestql(KRegister src1, KRegister src2) {
2470 assert(VM_Version::supports_avx512bw(), "");
2471 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2472 int encode = vex_prefix_and_encode(src1->encoding(), 0, src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2473 emit_int8((unsigned char)0x98);
2474 emit_int8((unsigned char)(0xC0 | encode));
2475 }
2476
2477 // This instruction produces ZF or CF flags
2478 void Assembler::ktestql(KRegister src1, KRegister src2) {
2479 assert(VM_Version::supports_avx512bw(), "");
2480 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2481 int encode = vex_prefix_and_encode(src1->encoding(), 0, src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2482 emit_int8((unsigned char)0x99);
2483 emit_int8((unsigned char)(0xC0 | encode));
2484 }
2485
2486 void Assembler::ktestq(KRegister src1, KRegister src2) {
2487 assert(VM_Version::supports_avx512bw(), "");
2488 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2489 int encode = vex_prefix_and_encode(src1->encoding(), 0, src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2490 emit_int8((unsigned char)0x99);
2491 emit_int8((unsigned char)(0xC0 | encode));
2492 }
2493
2494 void Assembler::ktestd(KRegister src1, KRegister src2) {
2495 assert(VM_Version::supports_avx512bw(), "");
2496 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2497 int encode = vex_prefix_and_encode(src1->encoding(), 0, src2->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2498 emit_int8((unsigned char)0x99);
2499 emit_int8((unsigned char)(0xC0 | encode));
2500 }
2501
2502 void Assembler::movb(Address dst, int imm8) {
2503 InstructionMark im(this);
2504 prefix(dst);
2505 emit_int8((unsigned char)0xC6);
2506 emit_operand(rax, dst, 1);
2507 emit_int8(imm8);
2508 }
2509
2510
2511 void Assembler::movb(Address dst, Register src) {
2512 assert(src->has_byte_register(), "must have byte register");
2513 InstructionMark im(this);
2514 prefix(dst, src, true);
2515 emit_int8((unsigned char)0x88);
2516 emit_operand(src, dst);
2517 }
2518
2519 void Assembler::movdl(XMMRegister dst, Register src) {
2520 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2521 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2522 int encode = simd_prefix_and_encode(dst, xnoreg, as_XMMRegister(src->encoding()), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2523 emit_int8(0x6E);
2524 emit_int8((unsigned char)(0xC0 | encode));
2525 }
2526
2527 void Assembler::movdl(Register dst, XMMRegister src) {
2528 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2529 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2530 // swap src/dst to get correct prefix
2531 int encode = simd_prefix_and_encode(src, xnoreg, as_XMMRegister(dst->encoding()), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2532 emit_int8(0x7E);
2533 emit_int8((unsigned char)(0xC0 | encode));
2534 }
2535
2536 void Assembler::movdl(XMMRegister dst, Address src) {
2537 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2538 InstructionMark im(this);
2539 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2540 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
2541 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2542 emit_int8(0x6E);
2543 emit_operand(dst, src);
2544 }
2545
2546 void Assembler::movdl(Address dst, XMMRegister src) {
2547 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2548 InstructionMark im(this);
2549 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2550 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
2551 simd_prefix(src, xnoreg, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2552 emit_int8(0x7E);
2553 emit_operand(src, dst);
2554 }
2555
2556 void Assembler::movdqa(XMMRegister dst, XMMRegister src) {
2557 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2558 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
2559 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2560 emit_int8(0x6F);
2561 emit_int8((unsigned char)(0xC0 | encode));
2562 }
2563
2564 void Assembler::movdqa(XMMRegister dst, Address src) {
2565 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2566 InstructionMark im(this);
2567 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
2568 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2569 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2570 emit_int8(0x6F);
2571 emit_operand(dst, src);
2572 }
2573
2574 void Assembler::movdqu(XMMRegister dst, Address src) {
2575 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2576 InstructionMark im(this);
2577 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
2578 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2579 simd_prefix(dst, xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2580 emit_int8(0x6F);
2581 emit_operand(dst, src);
2582 }
2583
2584 void Assembler::movdqu(XMMRegister dst, XMMRegister src) {
2585 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2586 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
2587 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2588 emit_int8(0x6F);
2589 emit_int8((unsigned char)(0xC0 | encode));
2590 }
2591
2592 void Assembler::movdqu(Address dst, XMMRegister src) {
2593 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2594 InstructionMark im(this);
2595 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
2596 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2597 attributes.reset_is_clear_context();
2598 simd_prefix(src, xnoreg, dst, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2599 emit_int8(0x7F);
2600 emit_operand(src, dst);
2601 }
2602
2603 // Move Unaligned 256bit Vector
2604 void Assembler::vmovdqu(XMMRegister dst, XMMRegister src) {
2605 assert(UseAVX > 0, "");
2606 InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
2607 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2608 emit_int8(0x6F);
2609 emit_int8((unsigned char)(0xC0 | encode));
2610 }
2611
2612 void Assembler::vmovdqu(XMMRegister dst, Address src) {
2613 assert(UseAVX > 0, "");
2614 InstructionMark im(this);
2615 InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
2616 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2617 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2618 emit_int8(0x6F);
2619 emit_operand(dst, src);
2620 }
2621
2622 void Assembler::vmovdqu(Address dst, XMMRegister src) {
2623 assert(UseAVX > 0, "");
2624 InstructionMark im(this);
2625 InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
2626 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2627 attributes.reset_is_clear_context();
2628 // swap src<->dst for encoding
2629 assert(src != xnoreg, "sanity");
2630 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2631 emit_int8(0x7F);
2632 emit_operand(src, dst);
2633 }
2634
2635 // Move Unaligned EVEX enabled Vector (programmable : 8,16,32,64)
2636 void Assembler::evmovdqub(XMMRegister dst, XMMRegister src, int vector_len) {
2637 assert(VM_Version::supports_evex(), "");
2638 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
2639 attributes.set_is_evex_instruction();
2640 int prefix = (_legacy_mode_bw) ? VEX_SIMD_F2 : VEX_SIMD_F3;
2641 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), (Assembler::VexSimdPrefix)prefix, VEX_OPCODE_0F, &attributes);
2642 emit_int8(0x6F);
2643 emit_int8((unsigned char)(0xC0 | encode));
2644 }
2645
2646 void Assembler::evmovdqub(XMMRegister dst, Address src, int vector_len) {
2647 assert(VM_Version::supports_evex(), "");
2648 InstructionMark im(this);
2649 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
2650 int prefix = (_legacy_mode_bw) ? VEX_SIMD_F2 : VEX_SIMD_F3;
2651 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2652 attributes.set_is_evex_instruction();
2653 vex_prefix(src, 0, dst->encoding(), (Assembler::VexSimdPrefix)prefix, VEX_OPCODE_0F, &attributes);
2654 emit_int8(0x6F);
2655 emit_operand(dst, src);
2656 }
2657
2658 void Assembler::evmovdqub(Address dst, XMMRegister src, int vector_len) {
2659 assert(VM_Version::supports_evex(), "");
2660 assert(src != xnoreg, "sanity");
2661 InstructionMark im(this);
2662 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
2663 int prefix = (_legacy_mode_bw) ? VEX_SIMD_F2 : VEX_SIMD_F3;
2719
2720 void Assembler::evmovdquw(Address dst, KRegister mask, XMMRegister src, int vector_len) {
2721 assert(VM_Version::supports_avx512vlbw(), "");
2722 assert(src != xnoreg, "sanity");
2723 InstructionMark im(this);
2724 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2725 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2726 attributes.reset_is_clear_context();
2727 attributes.set_embedded_opmask_register_specifier(mask);
2728 attributes.set_is_evex_instruction();
2729 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2730 emit_int8(0x7F);
2731 emit_operand(src, dst);
2732 }
2733
2734 void Assembler::evmovdqul(XMMRegister dst, XMMRegister src, int vector_len) {
2735 assert(VM_Version::supports_evex(), "");
2736 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
2737 attributes.set_is_evex_instruction();
2738 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2739 emit_int8(0x6F);
2740 emit_int8((unsigned char)(0xC0 | encode));
2741 }
2742
2743 void Assembler::evmovdqul(XMMRegister dst, Address src, int vector_len) {
2744 assert(VM_Version::supports_evex(), "");
2745 InstructionMark im(this);
2746 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true , /* uses_vl */ true);
2747 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2748 attributes.set_is_evex_instruction();
2749 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2750 emit_int8(0x6F);
2751 emit_operand(dst, src);
2752 }
2753
2754 void Assembler::evmovdqul(Address dst, XMMRegister src, int vector_len) {
2755 assert(VM_Version::supports_evex(), "");
2756 assert(src != xnoreg, "sanity");
2757 InstructionMark im(this);
2758 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
2759 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2760 attributes.reset_is_clear_context();
2761 attributes.set_is_evex_instruction();
2762 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2763 emit_int8(0x7F);
2764 emit_operand(src, dst);
2765 }
2766
2767 void Assembler::evmovdquq(XMMRegister dst, XMMRegister src, int vector_len) {
2768 assert(VM_Version::supports_evex(), "");
2769 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
2770 attributes.set_is_evex_instruction();
2771 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2772 emit_int8(0x6F);
2773 emit_int8((unsigned char)(0xC0 | encode));
2774 }
2775
2776 void Assembler::evmovdquq(XMMRegister dst, Address src, int vector_len) {
2777 assert(VM_Version::supports_evex(), "");
2778 InstructionMark im(this);
2779 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
2780 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2781 attributes.set_is_evex_instruction();
2782 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2783 emit_int8(0x6F);
2784 emit_operand(dst, src);
2785 }
2786
2787 void Assembler::evmovdquq(Address dst, XMMRegister src, int vector_len) {
2788 assert(VM_Version::supports_evex(), "");
2789 assert(src != xnoreg, "sanity");
2790 InstructionMark im(this);
2791 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
2792 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2793 attributes.reset_is_clear_context();
2794 attributes.set_is_evex_instruction();
2795 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2796 emit_int8(0x7F);
2797 emit_operand(src, dst);
2798 }
2799
2800 // Uses zero extension on 64bit
2801
2802 void Assembler::movl(Register dst, int32_t imm32) {
2803 int encode = prefix_and_encode(dst->encoding());
2804 emit_int8((unsigned char)(0xB8 | encode));
2805 emit_int32(imm32);
2806 }
2807
2808 void Assembler::movl(Register dst, Register src) {
2809 int encode = prefix_and_encode(dst->encoding(), src->encoding());
2810 emit_int8((unsigned char)0x8B);
2811 emit_int8((unsigned char)(0xC0 | encode));
2812 }
2813
2814 void Assembler::movl(Register dst, Address src) {
2815 InstructionMark im(this);
2816 prefix(src, dst);
2817 emit_int8((unsigned char)0x8B);
2818 emit_operand(dst, src);
2819 }
2820
2821 void Assembler::movl(Address dst, int32_t imm32) {
2822 InstructionMark im(this);
2823 prefix(dst);
2824 emit_int8((unsigned char)0xC7);
2825 emit_operand(rax, dst, 4);
2826 emit_int32(imm32);
2827 }
2828
2829 void Assembler::movl(Address dst, Register src) {
2830 InstructionMark im(this);
2831 prefix(dst, src);
2832 emit_int8((unsigned char)0x89);
2833 emit_operand(src, dst);
2834 }
2835
2836 // New cpus require to use movsd and movss to avoid partial register stall
2837 // when loading from memory. But for old Opteron use movlpd instead of movsd.
2838 // The selection is done in MacroAssembler::movdbl() and movflt().
2839 void Assembler::movlpd(XMMRegister dst, Address src) {
2840 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2841 InstructionMark im(this);
2842 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
2843 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
2844 attributes.set_rex_vex_w_reverted();
2845 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2846 emit_int8(0x12);
2847 emit_operand(dst, src);
2848 }
2849
2850 void Assembler::movq( MMXRegister dst, Address src ) {
2851 assert( VM_Version::supports_mmx(), "" );
2852 emit_int8(0x0F);
2853 emit_int8(0x6F);
2854 emit_operand(dst, src);
2855 }
2856
2857 void Assembler::movq( Address dst, MMXRegister src ) {
2858 assert( VM_Version::supports_mmx(), "" );
2859 emit_int8(0x0F);
2860 emit_int8(0x7F);
2861 // workaround gcc (3.2.1-7a) bug
2862 // In that version of gcc with only an emit_operand(MMX, Address)
2863 // gcc will tail jump and try and reverse the parameters completely
2864 // obliterating dst in the process. By having a version available
2865 // that doesn't need to swap the args at the tail jump the bug is
2866 // avoided.
2867 emit_operand(dst, src);
2868 }
2869
2870 void Assembler::movq(XMMRegister dst, Address src) {
2871 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2872 InstructionMark im(this);
2873 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2874 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
2875 attributes.set_rex_vex_w_reverted();
2876 simd_prefix(dst, xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2877 emit_int8(0x7E);
2878 emit_operand(dst, src);
2879 }
2880
2881 void Assembler::movq(Address dst, XMMRegister src) {
2882 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2883 InstructionMark im(this);
2884 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2885 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
2886 attributes.set_rex_vex_w_reverted();
2887 simd_prefix(src, xnoreg, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2888 emit_int8((unsigned char)0xD6);
2889 emit_operand(src, dst);
2890 }
2891
2892 void Assembler::movsbl(Register dst, Address src) { // movsxb
2893 InstructionMark im(this);
2894 prefix(src, dst);
2895 emit_int8(0x0F);
2896 emit_int8((unsigned char)0xBE);
2897 emit_operand(dst, src);
2898 }
2899
2900 void Assembler::movsbl(Register dst, Register src) { // movsxb
2901 NOT_LP64(assert(src->has_byte_register(), "must have byte register"));
2902 int encode = prefix_and_encode(dst->encoding(), false, src->encoding(), true);
2903 emit_int8(0x0F);
2904 emit_int8((unsigned char)0xBE);
2905 emit_int8((unsigned char)(0xC0 | encode));
2906 }
2907
2908 void Assembler::movsd(XMMRegister dst, XMMRegister src) {
2909 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2910 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2911 attributes.set_rex_vex_w_reverted();
2912 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2913 emit_int8(0x10);
2914 emit_int8((unsigned char)(0xC0 | encode));
2915 }
2916
2917 void Assembler::movsd(XMMRegister dst, Address src) {
2918 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2919 InstructionMark im(this);
2920 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2921 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
2922 attributes.set_rex_vex_w_reverted();
2923 simd_prefix(dst, xnoreg, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2924 emit_int8(0x10);
2925 emit_operand(dst, src);
2926 }
2927
2928 void Assembler::movsd(Address dst, XMMRegister src) {
2929 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2930 InstructionMark im(this);
2931 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2932 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
2933 attributes.reset_is_clear_context();
2934 attributes.set_rex_vex_w_reverted();
2935 simd_prefix(src, xnoreg, dst, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2936 emit_int8(0x11);
2937 emit_operand(src, dst);
2938 }
2939
2940 void Assembler::movss(XMMRegister dst, XMMRegister src) {
2941 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2942 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2943 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2944 emit_int8(0x10);
2945 emit_int8((unsigned char)(0xC0 | encode));
2946 }
2947
2948 void Assembler::movss(XMMRegister dst, Address src) {
2949 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2950 InstructionMark im(this);
2951 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2952 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
2953 simd_prefix(dst, xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2954 emit_int8(0x10);
2955 emit_operand(dst, src);
2956 }
2957
2958 void Assembler::movss(Address dst, XMMRegister src) {
2959 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2960 InstructionMark im(this);
2961 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2962 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
2963 attributes.reset_is_clear_context();
2964 simd_prefix(src, xnoreg, dst, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2965 emit_int8(0x11);
2966 emit_operand(src, dst);
2967 }
2968
2969 void Assembler::movswl(Register dst, Address src) { // movsxw
2970 InstructionMark im(this);
2971 prefix(src, dst);
2972 emit_int8(0x0F);
2973 emit_int8((unsigned char)0xBF);
2974 emit_operand(dst, src);
2975 }
2976
2977 void Assembler::movswl(Register dst, Register src) { // movsxw
2978 int encode = prefix_and_encode(dst->encoding(), src->encoding());
2979 emit_int8(0x0F);
2980 emit_int8((unsigned char)0xBF);
2981 emit_int8((unsigned char)(0xC0 | encode));
2982 }
2983
2984 void Assembler::movw(Address dst, int imm16) {
2985 InstructionMark im(this);
2986
2987 emit_int8(0x66); // switch to 16-bit mode
2988 prefix(dst);
2989 emit_int8((unsigned char)0xC7);
2990 emit_operand(rax, dst, 2);
2991 emit_int16(imm16);
2992 }
2993
2994 void Assembler::movw(Register dst, Address src) {
2995 InstructionMark im(this);
2996 emit_int8(0x66);
2997 prefix(src, dst);
2998 emit_int8((unsigned char)0x8B);
2999 emit_operand(dst, src);
3000 }
3001
3002 void Assembler::movw(Address dst, Register src) {
3003 InstructionMark im(this);
3004 emit_int8(0x66);
3005 prefix(dst, src);
3006 emit_int8((unsigned char)0x89);
3007 emit_operand(src, dst);
3008 }
3009
3010 void Assembler::movzbl(Register dst, Address src) { // movzxb
3011 InstructionMark im(this);
3012 prefix(src, dst);
3013 emit_int8(0x0F);
3014 emit_int8((unsigned char)0xB6);
3015 emit_operand(dst, src);
3016 }
3017
3018 void Assembler::movzbl(Register dst, Register src) { // movzxb
3019 NOT_LP64(assert(src->has_byte_register(), "must have byte register"));
3020 int encode = prefix_and_encode(dst->encoding(), false, src->encoding(), true);
3021 emit_int8(0x0F);
3022 emit_int8((unsigned char)0xB6);
3023 emit_int8(0xC0 | encode);
3024 }
3025
3026 void Assembler::movzwl(Register dst, Address src) { // movzxw
3027 InstructionMark im(this);
3028 prefix(src, dst);
3029 emit_int8(0x0F);
3030 emit_int8((unsigned char)0xB7);
3031 emit_operand(dst, src);
3032 }
3033
3034 void Assembler::movzwl(Register dst, Register src) { // movzxw
3035 int encode = prefix_and_encode(dst->encoding(), src->encoding());
3036 emit_int8(0x0F);
3037 emit_int8((unsigned char)0xB7);
3038 emit_int8(0xC0 | encode);
3039 }
3040
3041 void Assembler::mull(Address src) {
3042 InstructionMark im(this);
3043 prefix(src);
3044 emit_int8((unsigned char)0xF7);
3045 emit_operand(rsp, src);
3046 }
3047
3048 void Assembler::mull(Register src) {
3049 int encode = prefix_and_encode(src->encoding());
3050 emit_int8((unsigned char)0xF7);
3051 emit_int8((unsigned char)(0xE0 | encode));
3052 }
3053
3054 void Assembler::mulsd(XMMRegister dst, Address src) {
3055 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3056 InstructionMark im(this);
3057 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
3058 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
3059 attributes.set_rex_vex_w_reverted();
3060 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
3061 emit_int8(0x59);
3062 emit_operand(dst, src);
3063 }
3064
3065 void Assembler::mulsd(XMMRegister dst, XMMRegister src) {
3066 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3067 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
3068 attributes.set_rex_vex_w_reverted();
3069 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
3070 emit_int8(0x59);
3071 emit_int8((unsigned char)(0xC0 | encode));
3072 }
3073
3074 void Assembler::mulss(XMMRegister dst, Address src) {
3075 NOT_LP64(assert(VM_Version::supports_sse(), ""));
3076 InstructionMark im(this);
3077 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
3078 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
3079 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
3080 emit_int8(0x59);
3081 emit_operand(dst, src);
3082 }
3083
3084 void Assembler::mulss(XMMRegister dst, XMMRegister src) {
3085 NOT_LP64(assert(VM_Version::supports_sse(), ""));
3086 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
3087 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
3088 emit_int8(0x59);
3089 emit_int8((unsigned char)(0xC0 | encode));
3090 }
3091
3092 void Assembler::negl(Register dst) {
3093 int encode = prefix_and_encode(dst->encoding());
3094 emit_int8((unsigned char)0xF7);
3095 emit_int8((unsigned char)(0xD8 | encode));
3096 }
3097
3098 void Assembler::nop(int i) {
3099 #ifdef ASSERT
3100 assert(i > 0, " ");
3101 // The fancy nops aren't currently recognized by debuggers making it a
3102 // pain to disassemble code while debugging. If asserts are on clearly
3103 // speed is not an issue so simply use the single byte traditional nop
3104 // to do alignment.
3105
3106 for (; i > 0 ; i--) emit_int8((unsigned char)0x90);
3107 return;
3108
3109 #endif // ASSERT
3110
3111 if (UseAddressNop && VM_Version::is_intel()) {
3112 //
3113 // Using multi-bytes nops "0x0F 0x1F [address]" for Intel
3114 // 1: 0x90
3115 // 2: 0x66 0x90
3116 // 3: 0x66 0x66 0x90 (don't use "0x0F 0x1F 0x00" - need patching safe padding)
3117 // 4: 0x0F 0x1F 0x40 0x00
3118 // 5: 0x0F 0x1F 0x44 0x00 0x00
3119 // 6: 0x66 0x0F 0x1F 0x44 0x00 0x00
3120 // 7: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00
3121 // 8: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
3122 // 9: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
3123 // 10: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
3124 // 11: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
3125
3126 // The rest coding is Intel specific - don't use consecutive address nops
3127
3128 // 12: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
3129 // 13: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
3130 // 14: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
3131 // 15: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
3132
3133 while(i >= 15) {
3134 // For Intel don't generate consecutive addess nops (mix with regular nops)
3135 i -= 15;
3136 emit_int8(0x66); // size prefix
3137 emit_int8(0x66); // size prefix
3138 emit_int8(0x66); // size prefix
3139 addr_nop_8();
3140 emit_int8(0x66); // size prefix
3141 emit_int8(0x66); // size prefix
3142 emit_int8(0x66); // size prefix
3143 emit_int8((unsigned char)0x90);
3144 // nop
3145 }
3146 switch (i) {
3147 case 14:
3148 emit_int8(0x66); // size prefix
3149 case 13:
3150 emit_int8(0x66); // size prefix
3151 case 12:
3152 addr_nop_8();
3153 emit_int8(0x66); // size prefix
3154 emit_int8(0x66); // size prefix
3155 emit_int8(0x66); // size prefix
3156 emit_int8((unsigned char)0x90);
3157 // nop
3158 break;
3159 case 11:
3160 emit_int8(0x66); // size prefix
3161 case 10:
3162 emit_int8(0x66); // size prefix
3163 case 9:
3164 emit_int8(0x66); // size prefix
3165 case 8:
3166 addr_nop_8();
3167 break;
3168 case 7:
3169 addr_nop_7();
3170 break;
3171 case 6:
3172 emit_int8(0x66); // size prefix
3173 case 5:
3174 addr_nop_5();
3175 break;
3176 case 4:
3177 addr_nop_4();
3199 // 4: 0x0F 0x1F 0x40 0x00
3200 // 5: 0x0F 0x1F 0x44 0x00 0x00
3201 // 6: 0x66 0x0F 0x1F 0x44 0x00 0x00
3202 // 7: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00
3203 // 8: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
3204 // 9: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
3205 // 10: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
3206 // 11: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
3207
3208 // The rest coding is AMD specific - use consecutive address nops
3209
3210 // 12: 0x66 0x0F 0x1F 0x44 0x00 0x00 0x66 0x0F 0x1F 0x44 0x00 0x00
3211 // 13: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 0x66 0x0F 0x1F 0x44 0x00 0x00
3212 // 14: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00
3213 // 15: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00
3214 // 16: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
3215 // Size prefixes (0x66) are added for larger sizes
3216
3217 while(i >= 22) {
3218 i -= 11;
3219 emit_int8(0x66); // size prefix
3220 emit_int8(0x66); // size prefix
3221 emit_int8(0x66); // size prefix
3222 addr_nop_8();
3223 }
3224 // Generate first nop for size between 21-12
3225 switch (i) {
3226 case 21:
3227 i -= 1;
3228 emit_int8(0x66); // size prefix
3229 case 20:
3230 case 19:
3231 i -= 1;
3232 emit_int8(0x66); // size prefix
3233 case 18:
3234 case 17:
3235 i -= 1;
3236 emit_int8(0x66); // size prefix
3237 case 16:
3238 case 15:
3239 i -= 8;
3240 addr_nop_8();
3241 break;
3298 // 3: 0x66 0x66 0x90 (don't use "0x0F 0x1F 0x00" - need patching safe padding)
3299 // 4: 0x0F 0x1F 0x40 0x00
3300 // 5: 0x0F 0x1F 0x44 0x00 0x00
3301 // 6: 0x66 0x0F 0x1F 0x44 0x00 0x00
3302 // 7: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00
3303 // 8: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
3304 // 9: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
3305 // 10: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
3306 // 11: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
3307
3308 // The rest coding is ZX specific - don't use consecutive address nops
3309
3310 // 12: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
3311 // 13: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
3312 // 14: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
3313 // 15: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
3314
3315 while (i >= 15) {
3316 // For ZX don't generate consecutive addess nops (mix with regular nops)
3317 i -= 15;
3318 emit_int8(0x66); // size prefix
3319 emit_int8(0x66); // size prefix
3320 emit_int8(0x66); // size prefix
3321 addr_nop_8();
3322 emit_int8(0x66); // size prefix
3323 emit_int8(0x66); // size prefix
3324 emit_int8(0x66); // size prefix
3325 emit_int8((unsigned char)0x90);
3326 // nop
3327 }
3328 switch (i) {
3329 case 14:
3330 emit_int8(0x66); // size prefix
3331 case 13:
3332 emit_int8(0x66); // size prefix
3333 case 12:
3334 addr_nop_8();
3335 emit_int8(0x66); // size prefix
3336 emit_int8(0x66); // size prefix
3337 emit_int8(0x66); // size prefix
3338 emit_int8((unsigned char)0x90);
3339 // nop
3340 break;
3341 case 11:
3342 emit_int8(0x66); // size prefix
3343 case 10:
3344 emit_int8(0x66); // size prefix
3345 case 9:
3346 emit_int8(0x66); // size prefix
3347 case 8:
3348 addr_nop_8();
3349 break;
3350 case 7:
3351 addr_nop_7();
3352 break;
3353 case 6:
3354 emit_int8(0x66); // size prefix
3355 case 5:
3356 addr_nop_5();
3357 break;
3358 case 4:
3359 addr_nop_4();
3369 break;
3370 default:
3371 assert(i == 0, " ");
3372 }
3373 return;
3374 }
3375
3376 // Using nops with size prefixes "0x66 0x90".
3377 // From AMD Optimization Guide:
3378 // 1: 0x90
3379 // 2: 0x66 0x90
3380 // 3: 0x66 0x66 0x90
3381 // 4: 0x66 0x66 0x66 0x90
3382 // 5: 0x66 0x66 0x90 0x66 0x90
3383 // 6: 0x66 0x66 0x90 0x66 0x66 0x90
3384 // 7: 0x66 0x66 0x66 0x90 0x66 0x66 0x90
3385 // 8: 0x66 0x66 0x66 0x90 0x66 0x66 0x66 0x90
3386 // 9: 0x66 0x66 0x90 0x66 0x66 0x90 0x66 0x66 0x90
3387 // 10: 0x66 0x66 0x66 0x90 0x66 0x66 0x90 0x66 0x66 0x90
3388 //
3389 while(i > 12) {
3390 i -= 4;
3391 emit_int8(0x66); // size prefix
3392 emit_int8(0x66);
3393 emit_int8(0x66);
3394 emit_int8((unsigned char)0x90);
3395 // nop
3396 }
3397 // 1 - 12 nops
3398 if(i > 8) {
3399 if(i > 9) {
3400 i -= 1;
3401 emit_int8(0x66);
3402 }
3403 i -= 3;
3404 emit_int8(0x66);
3405 emit_int8(0x66);
3406 emit_int8((unsigned char)0x90);
3407 }
3408 // 1 - 8 nops
3409 if(i > 4) {
3410 if(i > 6) {
3411 i -= 1;
3412 emit_int8(0x66);
3413 }
3414 i -= 3;
3415 emit_int8(0x66);
3416 emit_int8(0x66);
3417 emit_int8((unsigned char)0x90);
3418 }
3419 switch (i) {
3420 case 4:
3421 emit_int8(0x66);
3422 case 3:
3423 emit_int8(0x66);
3424 case 2:
3425 emit_int8(0x66);
3426 case 1:
3427 emit_int8((unsigned char)0x90);
3428 break;
3429 default:
3430 assert(i == 0, " ");
3431 }
3432 }
3433
3434 void Assembler::notl(Register dst) {
3435 int encode = prefix_and_encode(dst->encoding());
3436 emit_int8((unsigned char)0xF7);
3437 emit_int8((unsigned char)(0xD0 | encode));
3438 }
3439
3440 void Assembler::orl(Address dst, int32_t imm32) {
3441 InstructionMark im(this);
3442 prefix(dst);
3443 emit_arith_operand(0x81, rcx, dst, imm32);
3444 }
3445
3446 void Assembler::orl(Register dst, int32_t imm32) {
3447 prefix(dst);
3448 emit_arith(0x81, 0xC8, dst, imm32);
3449 }
3450
3451 void Assembler::orl(Register dst, Address src) {
3452 InstructionMark im(this);
3453 prefix(src, dst);
3454 emit_int8(0x0B);
3455 emit_operand(dst, src);
3456 }
3457
3473 emit_int8((unsigned char)0x80);
3474 emit_operand(rcx, dst, 1);
3475 emit_int8(imm8);
3476 }
3477
3478 void Assembler::packuswb(XMMRegister dst, Address src) {
3479 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3480 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
3481 InstructionMark im(this);
3482 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
3483 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
3484 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3485 emit_int8(0x67);
3486 emit_operand(dst, src);
3487 }
3488
3489 void Assembler::packuswb(XMMRegister dst, XMMRegister src) {
3490 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3491 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
3492 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3493 emit_int8(0x67);
3494 emit_int8((unsigned char)(0xC0 | encode));
3495 }
3496
3497 void Assembler::vpackuswb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3498 assert(UseAVX > 0, "some form of AVX must be enabled");
3499 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
3500 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3501 emit_int8(0x67);
3502 emit_int8((unsigned char)(0xC0 | encode));
3503 }
3504
3505 void Assembler::vpermq(XMMRegister dst, XMMRegister src, int imm8, int vector_len) {
3506 assert(VM_Version::supports_avx2(), "");
3507 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
3508 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3509 emit_int8(0x00);
3510 emit_int8((unsigned char)(0xC0 | encode));
3511 emit_int8(imm8);
3512 }
3513
3514 void Assembler::vpermq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3515 assert(UseAVX > 2, "requires AVX512F");
3516 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
3517 attributes.set_is_evex_instruction();
3518 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3519 emit_int8((unsigned char)0x36);
3520 emit_int8((unsigned char)(0xC0 | encode));
3521 }
3522
3523 void Assembler::vperm2i128(XMMRegister dst, XMMRegister nds, XMMRegister src, int imm8) {
3524 assert(VM_Version::supports_avx2(), "");
3525 InstructionAttr attributes(AVX_256bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
3526 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3527 emit_int8(0x46);
3528 emit_int8(0xC0 | encode);
3529 emit_int8(imm8);
3530 }
3531
3532 void Assembler::vperm2f128(XMMRegister dst, XMMRegister nds, XMMRegister src, int imm8) {
3533 assert(VM_Version::supports_avx(), "");
3534 InstructionAttr attributes(AVX_256bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
3535 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3536 emit_int8(0x06);
3537 emit_int8(0xC0 | encode);
3538 emit_int8(imm8);
3539 }
3540
3541 void Assembler::evpermi2q(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3542 assert(VM_Version::supports_evex(), "");
3543 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
3544 attributes.set_is_evex_instruction();
3545 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3546 emit_int8(0x76);
3547 emit_int8((unsigned char)(0xC0 | encode));
3548 }
3549
3550
3551 void Assembler::pause() {
3552 emit_int8((unsigned char)0xF3);
3553 emit_int8((unsigned char)0x90);
3554 }
3555
3556 void Assembler::ud2() {
3557 emit_int8(0x0F);
3558 emit_int8(0x0B);
3559 }
3560
3561 void Assembler::pcmpestri(XMMRegister dst, Address src, int imm8) {
3562 assert(VM_Version::supports_sse4_2(), "");
3563 InstructionMark im(this);
3564 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
3565 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3566 emit_int8(0x61);
3567 emit_operand(dst, src);
3568 emit_int8(imm8);
3569 }
3570
3571 void Assembler::pcmpestri(XMMRegister dst, XMMRegister src, int imm8) {
3572 assert(VM_Version::supports_sse4_2(), "");
3573 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
3574 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3575 emit_int8(0x61);
3576 emit_int8((unsigned char)(0xC0 | encode));
3577 emit_int8(imm8);
3578 }
3579
3580 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst
3581 void Assembler::pcmpeqb(XMMRegister dst, XMMRegister src) {
3582 assert(VM_Version::supports_sse2(), "");
3583 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
3584 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3585 emit_int8(0x74);
3586 emit_int8((unsigned char)(0xC0 | encode));
3587 }
3588
3589 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst
3590 void Assembler::vpcmpeqb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3591 assert(VM_Version::supports_avx(), "");
3592 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
3593 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3594 emit_int8(0x74);
3595 emit_int8((unsigned char)(0xC0 | encode));
3596 }
3597
3598 // In this context, kdst is written the mask used to process the equal components
3599 void Assembler::evpcmpeqb(KRegister kdst, XMMRegister nds, XMMRegister src, int vector_len) {
3600 assert(VM_Version::supports_avx512bw(), "");
3601 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
3602 attributes.set_is_evex_instruction();
3603 int encode = vex_prefix_and_encode(kdst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3604 emit_int8(0x74);
3605 emit_int8((unsigned char)(0xC0 | encode));
3606 }
3607
3608 void Assembler::evpcmpgtb(KRegister kdst, XMMRegister nds, Address src, int vector_len) {
3609 assert(VM_Version::supports_avx512vlbw(), "");
3610 InstructionMark im(this);
3611 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
3612 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
3613 attributes.set_is_evex_instruction();
3614 int dst_enc = kdst->encoding();
3615 vex_prefix(src, nds->encoding(), dst_enc, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3616 emit_int8(0x64);
3617 emit_operand(as_Register(dst_enc), src);
3618 }
3619
3620 void Assembler::evpcmpgtb(KRegister kdst, KRegister mask, XMMRegister nds, Address src, int vector_len) {
3621 assert(VM_Version::supports_avx512vlbw(), "");
3622 InstructionMark im(this);
3623 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
3624 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
3625 attributes.reset_is_clear_context();
3626 attributes.set_embedded_opmask_register_specifier(mask);
3627 attributes.set_is_evex_instruction();
3628 int dst_enc = kdst->encoding();
3629 vex_prefix(src, nds->encoding(), dst_enc, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3630 emit_int8(0x64);
3631 emit_operand(as_Register(dst_enc), src);
3632 }
3633
3634 void Assembler::evpcmpuw(KRegister kdst, XMMRegister nds, XMMRegister src, ComparisonPredicate vcc, int vector_len) {
3635 assert(VM_Version::supports_avx512vlbw(), "");
3636 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
3637 attributes.set_is_evex_instruction();
3638 int encode = vex_prefix_and_encode(kdst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3639 emit_int8(0x3E);
3640 emit_int8((unsigned char)(0xC0 | encode));
3641 emit_int8(vcc);
3642 }
3643
3644 void Assembler::evpcmpuw(KRegister kdst, KRegister mask, XMMRegister nds, XMMRegister src, ComparisonPredicate vcc, int vector_len) {
3645 assert(VM_Version::supports_avx512vlbw(), "");
3646 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
3647 attributes.reset_is_clear_context();
3648 attributes.set_embedded_opmask_register_specifier(mask);
3649 attributes.set_is_evex_instruction();
3650 int encode = vex_prefix_and_encode(kdst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3651 emit_int8(0x3E);
3652 emit_int8((unsigned char)(0xC0 | encode));
3653 emit_int8(vcc);
3654 }
3655
3656 void Assembler::evpcmpuw(KRegister kdst, XMMRegister nds, Address src, ComparisonPredicate vcc, int vector_len) {
3657 assert(VM_Version::supports_avx512vlbw(), "");
3658 InstructionMark im(this);
3659 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
3660 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
3661 attributes.set_is_evex_instruction();
3662 int dst_enc = kdst->encoding();
3663 vex_prefix(src, nds->encoding(), kdst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3664 emit_int8(0x3E);
3665 emit_operand(as_Register(dst_enc), src);
3666 emit_int8(vcc);
3667 }
3668
3669 void Assembler::evpcmpeqb(KRegister kdst, XMMRegister nds, Address src, int vector_len) {
3670 assert(VM_Version::supports_avx512bw(), "");
3671 InstructionMark im(this);
3672 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
3673 attributes.set_is_evex_instruction();
3679 }
3680
3681 void Assembler::evpcmpeqb(KRegister kdst, KRegister mask, XMMRegister nds, Address src, int vector_len) {
3682 assert(VM_Version::supports_avx512vlbw(), "");
3683 InstructionMark im(this);
3684 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_reg_mask */ false, /* uses_vl */ true);
3685 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
3686 attributes.reset_is_clear_context();
3687 attributes.set_embedded_opmask_register_specifier(mask);
3688 attributes.set_is_evex_instruction();
3689 vex_prefix(src, nds->encoding(), kdst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3690 emit_int8(0x74);
3691 emit_operand(as_Register(kdst->encoding()), src);
3692 }
3693
3694 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst
3695 void Assembler::pcmpeqw(XMMRegister dst, XMMRegister src) {
3696 assert(VM_Version::supports_sse2(), "");
3697 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
3698 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3699 emit_int8(0x75);
3700 emit_int8((unsigned char)(0xC0 | encode));
3701 }
3702
3703 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst
3704 void Assembler::vpcmpeqw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3705 assert(VM_Version::supports_avx(), "");
3706 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
3707 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3708 emit_int8(0x75);
3709 emit_int8((unsigned char)(0xC0 | encode));
3710 }
3711
3712 // In this context, kdst is written the mask used to process the equal components
3713 void Assembler::evpcmpeqw(KRegister kdst, XMMRegister nds, XMMRegister src, int vector_len) {
3714 assert(VM_Version::supports_avx512bw(), "");
3715 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
3716 attributes.set_is_evex_instruction();
3717 int encode = vex_prefix_and_encode(kdst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3718 emit_int8(0x75);
3719 emit_int8((unsigned char)(0xC0 | encode));
3720 }
3721
3722 void Assembler::evpcmpeqw(KRegister kdst, XMMRegister nds, Address src, int vector_len) {
3723 assert(VM_Version::supports_avx512bw(), "");
3724 InstructionMark im(this);
3725 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
3726 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
3727 attributes.set_is_evex_instruction();
3728 int dst_enc = kdst->encoding();
3729 vex_prefix(src, nds->encoding(), dst_enc, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3730 emit_int8(0x75);
3731 emit_operand(as_Register(dst_enc), src);
3732 }
3733
3734 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst
3735 void Assembler::pcmpeqd(XMMRegister dst, XMMRegister src) {
3736 assert(VM_Version::supports_sse2(), "");
3737 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
3738 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3739 emit_int8(0x76);
3740 emit_int8((unsigned char)(0xC0 | encode));
3741 }
3742
3743 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst
3744 void Assembler::vpcmpeqd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3745 assert(VM_Version::supports_avx(), "");
3746 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
3747 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3748 emit_int8(0x76);
3749 emit_int8((unsigned char)(0xC0 | encode));
3750 }
3751
3752 // In this context, kdst is written the mask used to process the equal components
3753 void Assembler::evpcmpeqd(KRegister kdst, XMMRegister nds, XMMRegister src, int vector_len) {
3754 assert(VM_Version::supports_evex(), "");
3755 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
3756 attributes.set_is_evex_instruction();
3757 attributes.reset_is_clear_context();
3758 int encode = vex_prefix_and_encode(kdst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3759 emit_int8(0x76);
3760 emit_int8((unsigned char)(0xC0 | encode));
3761 }
3762
3763 void Assembler::evpcmpeqd(KRegister kdst, XMMRegister nds, Address src, int vector_len) {
3764 assert(VM_Version::supports_evex(), "");
3765 InstructionMark im(this);
3766 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
3767 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
3768 attributes.reset_is_clear_context();
3769 attributes.set_is_evex_instruction();
3770 int dst_enc = kdst->encoding();
3771 vex_prefix(src, nds->encoding(), dst_enc, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3772 emit_int8(0x76);
3773 emit_operand(as_Register(dst_enc), src);
3774 }
3775
3776 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst
3777 void Assembler::pcmpeqq(XMMRegister dst, XMMRegister src) {
3778 assert(VM_Version::supports_sse4_1(), "");
3779 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
3780 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3781 emit_int8(0x29);
3782 emit_int8((unsigned char)(0xC0 | encode));
3783 }
3784
3785 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst
3786 void Assembler::vpcmpeqq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3787 assert(VM_Version::supports_avx(), "");
3788 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
3789 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3790 emit_int8(0x29);
3791 emit_int8((unsigned char)(0xC0 | encode));
3792 }
3793
3794 // In this context, kdst is written the mask used to process the equal components
3795 void Assembler::evpcmpeqq(KRegister kdst, XMMRegister nds, XMMRegister src, int vector_len) {
3796 assert(VM_Version::supports_evex(), "");
3797 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
3798 attributes.reset_is_clear_context();
3799 attributes.set_is_evex_instruction();
3800 int encode = vex_prefix_and_encode(kdst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3801 emit_int8(0x29);
3802 emit_int8((unsigned char)(0xC0 | encode));
3803 }
3804
3805 // In this context, kdst is written the mask used to process the equal components
3806 void Assembler::evpcmpeqq(KRegister kdst, XMMRegister nds, Address src, int vector_len) {
3807 assert(VM_Version::supports_evex(), "");
3808 InstructionMark im(this);
3809 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
3810 attributes.reset_is_clear_context();
3811 attributes.set_is_evex_instruction();
3812 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
3813 int dst_enc = kdst->encoding();
3814 vex_prefix(src, nds->encoding(), dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3815 emit_int8(0x29);
3816 emit_operand(as_Register(dst_enc), src);
3817 }
3818
3819 void Assembler::pmovmskb(Register dst, XMMRegister src) {
3820 assert(VM_Version::supports_sse2(), "");
3821 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
3822 int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3823 emit_int8((unsigned char)0xD7);
3824 emit_int8((unsigned char)(0xC0 | encode));
3825 }
3826
3827 void Assembler::vpmovmskb(Register dst, XMMRegister src) {
3828 assert(VM_Version::supports_avx2(), "");
3829 InstructionAttr attributes(AVX_256bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
3830 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3831 emit_int8((unsigned char)0xD7);
3832 emit_int8((unsigned char)(0xC0 | encode));
3833 }
3834
3835 void Assembler::pextrd(Register dst, XMMRegister src, int imm8) {
3836 assert(VM_Version::supports_sse4_1(), "");
3837 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true);
3838 int encode = simd_prefix_and_encode(src, xnoreg, as_XMMRegister(dst->encoding()), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3839 emit_int8(0x16);
3840 emit_int8((unsigned char)(0xC0 | encode));
3841 emit_int8(imm8);
3842 }
3843
3844 void Assembler::pextrd(Address dst, XMMRegister src, int imm8) {
3845 assert(VM_Version::supports_sse4_1(), "");
3846 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true);
3847 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
3848 simd_prefix(src, xnoreg, dst, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3849 emit_int8(0x16);
3850 emit_operand(src, dst);
3851 emit_int8(imm8);
3852 }
3853
3854 void Assembler::pextrq(Register dst, XMMRegister src, int imm8) {
3855 assert(VM_Version::supports_sse4_1(), "");
3856 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true);
3857 int encode = simd_prefix_and_encode(src, xnoreg, as_XMMRegister(dst->encoding()), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3858 emit_int8(0x16);
3859 emit_int8((unsigned char)(0xC0 | encode));
3860 emit_int8(imm8);
3861 }
3862
3863 void Assembler::pextrq(Address dst, XMMRegister src, int imm8) {
3864 assert(VM_Version::supports_sse4_1(), "");
3865 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true);
3866 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
3867 simd_prefix(src, xnoreg, dst, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3868 emit_int8(0x16);
3869 emit_operand(src, dst);
3870 emit_int8(imm8);
3871 }
3872
3873 void Assembler::pextrw(Register dst, XMMRegister src, int imm8) {
3874 assert(VM_Version::supports_sse2(), "");
3875 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
3876 int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3877 emit_int8((unsigned char)0xC5);
3878 emit_int8((unsigned char)(0xC0 | encode));
3879 emit_int8(imm8);
3880 }
3881
3882 void Assembler::pextrw(Address dst, XMMRegister src, int imm8) {
3883 assert(VM_Version::supports_sse4_1(), "");
3884 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
3885 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_16bit);
3886 simd_prefix(src, xnoreg, dst, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3887 emit_int8((unsigned char)0x15);
3888 emit_operand(src, dst);
3889 emit_int8(imm8);
3890 }
3891
3892 void Assembler::pextrb(Address dst, XMMRegister src, int imm8) {
3893 assert(VM_Version::supports_sse4_1(), "");
3894 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
3895 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_8bit);
3896 simd_prefix(src, xnoreg, dst, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3897 emit_int8(0x14);
3898 emit_operand(src, dst);
3899 emit_int8(imm8);
3900 }
3901
3902 void Assembler::pinsrd(XMMRegister dst, Register src, int imm8) {
3903 assert(VM_Version::supports_sse4_1(), "");
3904 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true);
3905 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3906 emit_int8(0x22);
3907 emit_int8((unsigned char)(0xC0 | encode));
3908 emit_int8(imm8);
3909 }
3910
3911 void Assembler::pinsrd(XMMRegister dst, Address src, int imm8) {
3912 assert(VM_Version::supports_sse4_1(), "");
3913 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true);
3914 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
3915 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3916 emit_int8(0x22);
3917 emit_operand(dst,src);
3918 emit_int8(imm8);
3919 }
3920
3921 void Assembler::pinsrq(XMMRegister dst, Register src, int imm8) {
3922 assert(VM_Version::supports_sse4_1(), "");
3923 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true);
3924 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3925 emit_int8(0x22);
3926 emit_int8((unsigned char)(0xC0 | encode));
3927 emit_int8(imm8);
3928 }
3929
3930 void Assembler::pinsrq(XMMRegister dst, Address src, int imm8) {
3931 assert(VM_Version::supports_sse4_1(), "");
3932 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true);
3933 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
3934 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3935 emit_int8(0x22);
3936 emit_operand(dst, src);
3937 emit_int8(imm8);
3938 }
3939
3940 void Assembler::pinsrw(XMMRegister dst, Register src, int imm8) {
3941 assert(VM_Version::supports_sse2(), "");
3942 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
3943 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3944 emit_int8((unsigned char)0xC4);
3945 emit_int8((unsigned char)(0xC0 | encode));
3946 emit_int8(imm8);
3947 }
3948
3949 void Assembler::pinsrw(XMMRegister dst, Address src, int imm8) {
3950 assert(VM_Version::supports_sse2(), "");
3951 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
3952 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_16bit);
3953 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3954 emit_int8((unsigned char)0xC4);
3955 emit_operand(dst, src);
3956 emit_int8(imm8);
3957 }
3958
3959 void Assembler::pinsrb(XMMRegister dst, Address src, int imm8) {
3960 assert(VM_Version::supports_sse4_1(), "");
3961 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
3962 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_8bit);
3963 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3964 emit_int8(0x20);
3965 emit_operand(dst, src);
3966 emit_int8(imm8);
3967 }
3968
3969 void Assembler::pmovzxbw(XMMRegister dst, Address src) {
3970 assert(VM_Version::supports_sse4_1(), "");
3971 InstructionMark im(this);
3972 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
3973 attributes.set_address_attributes(/* tuple_type */ EVEX_HVM, /* input_size_in_bits */ EVEX_NObit);
3974 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3975 emit_int8(0x30);
3976 emit_operand(dst, src);
3977 }
3978
3979 void Assembler::pmovzxbw(XMMRegister dst, XMMRegister src) {
3980 assert(VM_Version::supports_sse4_1(), "");
3981 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
3982 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3983 emit_int8(0x30);
3984 emit_int8((unsigned char)(0xC0 | encode));
3985 }
3986
3987 void Assembler::pmovsxbw(XMMRegister dst, XMMRegister src) {
3988 assert(VM_Version::supports_sse4_1(), "");
3989 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
3990 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3991 emit_int8(0x20);
3992 emit_int8((unsigned char)(0xC0 | encode));
3993 }
3994
3995 void Assembler::vpmovzxbw(XMMRegister dst, Address src, int vector_len) {
3996 assert(VM_Version::supports_avx(), "");
3997 InstructionMark im(this);
3998 assert(dst != xnoreg, "sanity");
3999 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
4000 attributes.set_address_attributes(/* tuple_type */ EVEX_HVM, /* input_size_in_bits */ EVEX_NObit);
4001 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4002 emit_int8(0x30);
4003 emit_operand(dst, src);
4004 }
4005
4006 void Assembler::vpmovzxbw(XMMRegister dst, XMMRegister src, int vector_len) {
4007 assert(vector_len == AVX_128bit? VM_Version::supports_avx() :
4008 vector_len == AVX_256bit? VM_Version::supports_avx2() :
4009 vector_len == AVX_512bit? VM_Version::supports_avx512bw() : 0, "");
4010 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
4011 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4012 emit_int8(0x30);
4013 emit_int8((unsigned char) (0xC0 | encode));
4014 }
4015
4016 void Assembler::vpmovsxbw(XMMRegister dst, XMMRegister src, int vector_len) {
4017 assert(vector_len == AVX_128bit? VM_Version::supports_avx() :
4018 vector_len == AVX_256bit? VM_Version::supports_avx2() :
4019 vector_len == AVX_512bit? VM_Version::supports_avx512bw() : 0, "");
4020 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
4021 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4022 emit_int8(0x20);
4023 emit_int8((unsigned char)(0xC0 | encode));
4024 }
4025
4026 void Assembler::evpmovzxbw(XMMRegister dst, KRegister mask, Address src, int vector_len) {
4027 assert(VM_Version::supports_avx512vlbw(), "");
4028 assert(dst != xnoreg, "sanity");
4029 InstructionMark im(this);
4030 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4031 attributes.set_address_attributes(/* tuple_type */ EVEX_HVM, /* input_size_in_bits */ EVEX_NObit);
4032 attributes.set_embedded_opmask_register_specifier(mask);
4033 attributes.set_is_evex_instruction();
4034 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4035 emit_int8(0x30);
4036 emit_operand(dst, src);
4037 }
4038 void Assembler::evpmovwb(Address dst, XMMRegister src, int vector_len) {
4039 assert(VM_Version::supports_avx512vlbw(), "");
4040 assert(src != xnoreg, "sanity");
4041 InstructionMark im(this);
4042 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
4043 attributes.set_address_attributes(/* tuple_type */ EVEX_HVM, /* input_size_in_bits */ EVEX_NObit);
4062 }
4063
4064 void Assembler::evpmovdb(Address dst, XMMRegister src, int vector_len) {
4065 assert(VM_Version::supports_evex(), "");
4066 assert(src != xnoreg, "sanity");
4067 InstructionMark im(this);
4068 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
4069 attributes.set_address_attributes(/* tuple_type */ EVEX_QVM, /* input_size_in_bits */ EVEX_NObit);
4070 attributes.set_is_evex_instruction();
4071 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F_38, &attributes);
4072 emit_int8(0x31);
4073 emit_operand(src, dst);
4074 }
4075
4076 void Assembler::vpmovzxwd(XMMRegister dst, XMMRegister src, int vector_len) {
4077 assert(vector_len == AVX_128bit? VM_Version::supports_avx() :
4078 vector_len == AVX_256bit? VM_Version::supports_avx2() :
4079 vector_len == AVX_512bit? VM_Version::supports_evex() : 0, " ");
4080 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
4081 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4082 emit_int8(0x33);
4083 emit_int8((unsigned char)(0xC0 | encode));
4084 }
4085
4086 void Assembler::pmaddwd(XMMRegister dst, XMMRegister src) {
4087 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4088 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
4089 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4090 emit_int8((unsigned char)0xF5);
4091 emit_int8((unsigned char)(0xC0 | encode));
4092 }
4093
4094 void Assembler::vpmaddwd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4095 assert(vector_len == AVX_128bit ? VM_Version::supports_avx() :
4096 (vector_len == AVX_256bit ? VM_Version::supports_avx2() :
4097 (vector_len == AVX_512bit ? VM_Version::supports_evex() : 0)), "");
4098 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
4099 int encode = simd_prefix_and_encode(dst, nds, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4100 emit_int8((unsigned char)0xF5);
4101 emit_int8((unsigned char)(0xC0 | encode));
4102 }
4103
4104 void Assembler::evpdpwssd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4105 assert(VM_Version::supports_evex(), "");
4106 assert(VM_Version::supports_avx512_vnni(), "must support vnni");
4107 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
4108 attributes.set_is_evex_instruction();
4109 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4110 emit_int8(0x52);
4111 emit_int8((unsigned char)(0xC0 | encode));
4112 }
4113
4114 // generic
4115 void Assembler::pop(Register dst) {
4116 int encode = prefix_and_encode(dst->encoding());
4117 emit_int8(0x58 | encode);
4118 }
4119
4120 void Assembler::popcntl(Register dst, Address src) {
4121 assert(VM_Version::supports_popcnt(), "must support");
4122 InstructionMark im(this);
4123 emit_int8((unsigned char)0xF3);
4124 prefix(src, dst);
4125 emit_int8(0x0F);
4126 emit_int8((unsigned char)0xB8);
4127 emit_operand(dst, src);
4128 }
4129
4130 void Assembler::popcntl(Register dst, Register src) {
4131 assert(VM_Version::supports_popcnt(), "must support");
4132 emit_int8((unsigned char)0xF3);
4133 int encode = prefix_and_encode(dst->encoding(), src->encoding());
4134 emit_int8(0x0F);
4135 emit_int8((unsigned char)0xB8);
4136 emit_int8((unsigned char)(0xC0 | encode));
4137 }
4138
4139 void Assembler::vpopcntd(XMMRegister dst, XMMRegister src, int vector_len) {
4140 assert(VM_Version::supports_avx512_vpopcntdq(), "must support vpopcntdq feature");
4141 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
4142 attributes.set_is_evex_instruction();
4143 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4144 emit_int8(0x55);
4145 emit_int8((unsigned char)(0xC0 | encode));
4146 }
4147
4148 void Assembler::popf() {
4149 emit_int8((unsigned char)0x9D);
4150 }
4151
4152 #ifndef _LP64 // no 32bit push/pop on amd64
4153 void Assembler::popl(Address dst) {
4154 // NOTE: this will adjust stack by 8byte on 64bits
4155 InstructionMark im(this);
4156 prefix(dst);
4157 emit_int8((unsigned char)0x8F);
4158 emit_operand(rax, dst);
4159 }
4160 #endif
4161
4162 void Assembler::prefetch_prefix(Address src) {
4163 prefix(src);
4164 emit_int8(0x0F);
4165 }
4166
4167 void Assembler::prefetchnta(Address src) {
4168 NOT_LP64(assert(VM_Version::supports_sse(), "must support"));
4169 InstructionMark im(this);
4170 prefetch_prefix(src);
4171 emit_int8(0x18);
4172 emit_operand(rax, src); // 0, src
4173 }
4174
4175 void Assembler::prefetchr(Address src) {
4176 assert(VM_Version::supports_3dnow_prefetch(), "must support");
4177 InstructionMark im(this);
4178 prefetch_prefix(src);
4179 emit_int8(0x0D);
4180 emit_operand(rax, src); // 0, src
4181 }
4182
4183 void Assembler::prefetcht0(Address src) {
4184 NOT_LP64(assert(VM_Version::supports_sse(), "must support"));
4185 InstructionMark im(this);
4186 prefetch_prefix(src);
4187 emit_int8(0x18);
4188 emit_operand(rcx, src); // 1, src
4189 }
4190
4191 void Assembler::prefetcht1(Address src) {
4192 NOT_LP64(assert(VM_Version::supports_sse(), "must support"));
4193 InstructionMark im(this);
4194 prefetch_prefix(src);
4195 emit_int8(0x18);
4196 emit_operand(rdx, src); // 2, src
4197 }
4198
4199 void Assembler::prefetcht2(Address src) {
4200 NOT_LP64(assert(VM_Version::supports_sse(), "must support"));
4201 InstructionMark im(this);
4202 prefetch_prefix(src);
4203 emit_int8(0x18);
4204 emit_operand(rbx, src); // 3, src
4205 }
4206
4207 void Assembler::prefetchw(Address src) {
4208 assert(VM_Version::supports_3dnow_prefetch(), "must support");
4209 InstructionMark im(this);
4210 prefetch_prefix(src);
4211 emit_int8(0x0D);
4212 emit_operand(rcx, src); // 1, src
4213 }
4214
4215 void Assembler::prefix(Prefix p) {
4216 emit_int8(p);
4217 }
4218
4219 void Assembler::pshufb(XMMRegister dst, XMMRegister src) {
4220 assert(VM_Version::supports_ssse3(), "");
4221 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
4222 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4223 emit_int8(0x00);
4224 emit_int8((unsigned char)(0xC0 | encode));
4225 }
4226
4227 void Assembler::vpshufb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4228 assert(vector_len == AVX_128bit? VM_Version::supports_avx() :
4229 vector_len == AVX_256bit? VM_Version::supports_avx2() :
4230 vector_len == AVX_512bit? VM_Version::supports_avx512bw() : 0, "");
4231 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
4232 int encode = simd_prefix_and_encode(dst, nds, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4233 emit_int8(0x00);
4234 emit_int8((unsigned char)(0xC0 | encode));
4235 }
4236
4237 void Assembler::pshufb(XMMRegister dst, Address src) {
4238 assert(VM_Version::supports_ssse3(), "");
4239 InstructionMark im(this);
4240 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
4241 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
4242 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4243 emit_int8(0x00);
4244 emit_operand(dst, src);
4245 }
4246
4247 void Assembler::pshufd(XMMRegister dst, XMMRegister src, int mode) {
4248 assert(isByte(mode), "invalid value");
4249 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4250 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_128bit;
4251 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
4252 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4253 emit_int8(0x70);
4254 emit_int8((unsigned char)(0xC0 | encode));
4255 emit_int8(mode & 0xFF);
4256 }
4257
4258 void Assembler::vpshufd(XMMRegister dst, XMMRegister src, int mode, int vector_len) {
4259 assert(vector_len == AVX_128bit? VM_Version::supports_avx() :
4260 (vector_len == AVX_256bit? VM_Version::supports_avx2() :
4261 (vector_len == AVX_512bit? VM_Version::supports_evex() : 0)), "");
4262 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4263 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
4264 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4265 emit_int8(0x70);
4266 emit_int8((unsigned char)(0xC0 | encode));
4267 emit_int8(mode & 0xFF);
4268 }
4269
4270 void Assembler::pshufd(XMMRegister dst, Address src, int mode) {
4271 assert(isByte(mode), "invalid value");
4272 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4273 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
4274 InstructionMark im(this);
4275 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
4276 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
4277 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4278 emit_int8(0x70);
4279 emit_operand(dst, src);
4280 emit_int8(mode & 0xFF);
4281 }
4282
4283 void Assembler::pshuflw(XMMRegister dst, XMMRegister src, int mode) {
4284 assert(isByte(mode), "invalid value");
4285 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4286 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
4287 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4288 emit_int8(0x70);
4289 emit_int8((unsigned char)(0xC0 | encode));
4290 emit_int8(mode & 0xFF);
4291 }
4292
4293 void Assembler::pshuflw(XMMRegister dst, Address src, int mode) {
4294 assert(isByte(mode), "invalid value");
4295 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4296 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
4297 InstructionMark im(this);
4298 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
4299 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
4300 simd_prefix(dst, xnoreg, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4301 emit_int8(0x70);
4302 emit_operand(dst, src);
4303 emit_int8(mode & 0xFF);
4304 }
4305
4306 void Assembler::evshufi64x2(XMMRegister dst, XMMRegister nds, XMMRegister src, int imm8, int vector_len) {
4307 assert(VM_Version::supports_evex(), "requires EVEX support");
4308 assert(vector_len == Assembler::AVX_256bit || vector_len == Assembler::AVX_512bit, "");
4309 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
4310 attributes.set_is_evex_instruction();
4311 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
4312 emit_int8(0x43);
4313 emit_int8((unsigned char)(0xC0 | encode));
4314 emit_int8(imm8 & 0xFF);
4315 }
4316
4317 void Assembler::psrldq(XMMRegister dst, int shift) {
4318 // Shift left 128 bit value in dst XMMRegister by shift number of bytes.
4319 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4320 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
4321 int encode = simd_prefix_and_encode(xmm3, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4322 emit_int8(0x73);
4323 emit_int8((unsigned char)(0xC0 | encode));
4324 emit_int8(shift);
4325 }
4326
4327 void Assembler::vpsrldq(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
4328 assert(vector_len == AVX_128bit ? VM_Version::supports_avx() :
4329 vector_len == AVX_256bit ? VM_Version::supports_avx2() :
4330 vector_len == AVX_512bit ? VM_Version::supports_avx512bw() : 0, "");
4331 InstructionAttr attributes(vector_len, /*vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
4332 int encode = vex_prefix_and_encode(xmm3->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4333 emit_int8(0x73);
4334 emit_int8((unsigned char)(0xC0 | encode));
4335 emit_int8(shift & 0xFF);
4336 }
4337
4338 void Assembler::pslldq(XMMRegister dst, int shift) {
4339 // Shift left 128 bit value in dst XMMRegister by shift number of bytes.
4340 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4341 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
4342 // XMM7 is for /7 encoding: 66 0F 73 /7 ib
4343 int encode = simd_prefix_and_encode(xmm7, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4344 emit_int8(0x73);
4345 emit_int8((unsigned char)(0xC0 | encode));
4346 emit_int8(shift);
4347 }
4348
4349 void Assembler::vpslldq(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
4350 assert(vector_len == AVX_128bit ? VM_Version::supports_avx() :
4351 vector_len == AVX_256bit ? VM_Version::supports_avx2() :
4352 vector_len == AVX_512bit ? VM_Version::supports_avx512bw() : 0, "");
4353 InstructionAttr attributes(vector_len, /*vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
4354 int encode = vex_prefix_and_encode(xmm7->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4355 emit_int8(0x73);
4356 emit_int8((unsigned char)(0xC0 | encode));
4357 emit_int8(shift & 0xFF);
4358 }
4359
4360 void Assembler::ptest(XMMRegister dst, Address src) {
4361 assert(VM_Version::supports_sse4_1(), "");
4362 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
4363 InstructionMark im(this);
4364 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
4365 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4366 emit_int8(0x17);
4367 emit_operand(dst, src);
4368 }
4369
4370 void Assembler::ptest(XMMRegister dst, XMMRegister src) {
4371 assert(VM_Version::supports_sse4_1() || VM_Version::supports_avx(), "");
4372 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
4373 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4374 emit_int8(0x17);
4375 emit_int8((unsigned char)(0xC0 | encode));
4376 }
4377
4378 void Assembler::vptest(XMMRegister dst, Address src) {
4379 assert(VM_Version::supports_avx(), "");
4380 InstructionMark im(this);
4381 InstructionAttr attributes(AVX_256bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
4382 assert(dst != xnoreg, "sanity");
4383 // swap src<->dst for encoding
4384 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4385 emit_int8(0x17);
4386 emit_operand(dst, src);
4387 }
4388
4389 void Assembler::vptest(XMMRegister dst, XMMRegister src) {
4390 assert(VM_Version::supports_avx(), "");
4391 InstructionAttr attributes(AVX_256bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
4392 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4393 emit_int8(0x17);
4394 emit_int8((unsigned char)(0xC0 | encode));
4395 }
4396
4397 void Assembler::punpcklbw(XMMRegister dst, Address src) {
4398 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4399 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
4400 InstructionMark im(this);
4401 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_vlbw, /* no_mask_reg */ true, /* uses_vl */ true);
4402 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
4403 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4404 emit_int8(0x60);
4405 emit_operand(dst, src);
4406 }
4407
4408 void Assembler::punpcklbw(XMMRegister dst, XMMRegister src) {
4409 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4410 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_vlbw, /* no_mask_reg */ true, /* uses_vl */ true);
4411 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4412 emit_int8(0x60);
4413 emit_int8((unsigned char)(0xC0 | encode));
4414 }
4415
4416 void Assembler::punpckldq(XMMRegister dst, Address src) {
4417 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4418 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
4419 InstructionMark im(this);
4420 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
4421 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
4422 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4423 emit_int8(0x62);
4424 emit_operand(dst, src);
4425 }
4426
4427 void Assembler::punpckldq(XMMRegister dst, XMMRegister src) {
4428 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4429 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
4430 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4431 emit_int8(0x62);
4432 emit_int8((unsigned char)(0xC0 | encode));
4433 }
4434
4435 void Assembler::punpcklqdq(XMMRegister dst, XMMRegister src) {
4436 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4437 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
4438 attributes.set_rex_vex_w_reverted();
4439 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4440 emit_int8(0x6C);
4441 emit_int8((unsigned char)(0xC0 | encode));
4442 }
4443
4444 void Assembler::push(int32_t imm32) {
4445 // in 64bits we push 64bits onto the stack but only
4446 // take a 32bit immediate
4447 emit_int8(0x68);
4448 emit_int32(imm32);
4449 }
4450
4451 void Assembler::push(Register src) {
4452 int encode = prefix_and_encode(src->encoding());
4453
4454 emit_int8(0x50 | encode);
4455 }
4456
4457 void Assembler::pushf() {
4458 emit_int8((unsigned char)0x9C);
4459 }
4460
4461 #ifndef _LP64 // no 32bit push/pop on amd64
4462 void Assembler::pushl(Address src) {
4463 // Note this will push 64bit on 64bit
4464 InstructionMark im(this);
4465 prefix(src);
4466 emit_int8((unsigned char)0xFF);
4467 emit_operand(rsi, src);
4468 }
4469 #endif
4470
4471 void Assembler::rcll(Register dst, int imm8) {
4472 assert(isShiftCount(imm8), "illegal shift count");
4473 int encode = prefix_and_encode(dst->encoding());
4474 if (imm8 == 1) {
4475 emit_int8((unsigned char)0xD1);
4476 emit_int8((unsigned char)(0xD0 | encode));
4477 } else {
4478 emit_int8((unsigned char)0xC1);
4479 emit_int8((unsigned char)0xD0 | encode);
4480 emit_int8(imm8);
4481 }
4482 }
4483
4484 void Assembler::rcpps(XMMRegister dst, XMMRegister src) {
4485 NOT_LP64(assert(VM_Version::supports_sse(), ""));
4486 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
4487 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4488 emit_int8(0x53);
4489 emit_int8((unsigned char)(0xC0 | encode));
4490 }
4491
4492 void Assembler::rcpss(XMMRegister dst, XMMRegister src) {
4493 NOT_LP64(assert(VM_Version::supports_sse(), ""));
4494 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
4495 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4496 emit_int8(0x53);
4497 emit_int8((unsigned char)(0xC0 | encode));
4498 }
4499
4500 void Assembler::rdtsc() {
4501 emit_int8((unsigned char)0x0F);
4502 emit_int8((unsigned char)0x31);
4503 }
4504
4505 // copies data from [esi] to [edi] using rcx pointer sized words
4506 // generic
4507 void Assembler::rep_mov() {
4508 emit_int8((unsigned char)0xF3);
4509 // MOVSQ
4510 LP64_ONLY(prefix(REX_W));
4511 emit_int8((unsigned char)0xA5);
4512 }
4513
4514 // sets rcx bytes with rax, value at [edi]
4515 void Assembler::rep_stosb() {
4516 emit_int8((unsigned char)0xF3); // REP
4517 LP64_ONLY(prefix(REX_W));
4518 emit_int8((unsigned char)0xAA); // STOSB
4519 }
4520
4521 // sets rcx pointer sized words with rax, value at [edi]
4522 // generic
4523 void Assembler::rep_stos() {
4524 emit_int8((unsigned char)0xF3); // REP
4525 LP64_ONLY(prefix(REX_W)); // LP64:STOSQ, LP32:STOSD
4526 emit_int8((unsigned char)0xAB);
4527 }
4528
4529 // scans rcx pointer sized words at [edi] for occurance of rax,
4530 // generic
4531 void Assembler::repne_scan() { // repne_scan
4532 emit_int8((unsigned char)0xF2);
4533 // SCASQ
4534 LP64_ONLY(prefix(REX_W));
4535 emit_int8((unsigned char)0xAF);
4536 }
4537
4538 #ifdef _LP64
4539 // scans rcx 4 byte words at [edi] for occurance of rax,
4540 // generic
4541 void Assembler::repne_scanl() { // repne_scan
4542 emit_int8((unsigned char)0xF2);
4543 // SCASL
4544 emit_int8((unsigned char)0xAF);
4545 }
4546 #endif
4547
4548 void Assembler::ret(int imm16) {
4549 if (imm16 == 0) {
4550 emit_int8((unsigned char)0xC3);
4551 } else {
4552 emit_int8((unsigned char)0xC2);
4553 emit_int16(imm16);
4554 }
4555 }
4556
4557 void Assembler::sahf() {
4558 #ifdef _LP64
4559 // Not supported in 64bit mode
4560 ShouldNotReachHere();
4561 #endif
4562 emit_int8((unsigned char)0x9E);
4563 }
4564
4565 void Assembler::sarl(Register dst, int imm8) {
4566 int encode = prefix_and_encode(dst->encoding());
4567 assert(isShiftCount(imm8), "illegal shift count");
4568 if (imm8 == 1) {
4569 emit_int8((unsigned char)0xD1);
4570 emit_int8((unsigned char)(0xF8 | encode));
4571 } else {
4572 emit_int8((unsigned char)0xC1);
4573 emit_int8((unsigned char)(0xF8 | encode));
4574 emit_int8(imm8);
4575 }
4576 }
4577
4578 void Assembler::sarl(Register dst) {
4579 int encode = prefix_and_encode(dst->encoding());
4580 emit_int8((unsigned char)0xD3);
4581 emit_int8((unsigned char)(0xF8 | encode));
4582 }
4583
4584 void Assembler::sbbl(Address dst, int32_t imm32) {
4585 InstructionMark im(this);
4586 prefix(dst);
4587 emit_arith_operand(0x81, rbx, dst, imm32);
4588 }
4589
4590 void Assembler::sbbl(Register dst, int32_t imm32) {
4591 prefix(dst);
4592 emit_arith(0x81, 0xD8, dst, imm32);
4593 }
4594
4595
4596 void Assembler::sbbl(Register dst, Address src) {
4597 InstructionMark im(this);
4598 prefix(src, dst);
4599 emit_int8(0x1B);
4600 emit_operand(dst, src);
4601 }
4602
4603 void Assembler::sbbl(Register dst, Register src) {
4604 (void) prefix_and_encode(dst->encoding(), src->encoding());
4605 emit_arith(0x1B, 0xC0, dst, src);
4606 }
4607
4608 void Assembler::setb(Condition cc, Register dst) {
4609 assert(0 <= cc && cc < 16, "illegal cc");
4610 int encode = prefix_and_encode(dst->encoding(), true);
4611 emit_int8(0x0F);
4612 emit_int8((unsigned char)0x90 | cc);
4613 emit_int8((unsigned char)(0xC0 | encode));
4614 }
4615
4616 void Assembler::palignr(XMMRegister dst, XMMRegister src, int imm8) {
4617 assert(VM_Version::supports_ssse3(), "");
4618 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
4619 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
4620 emit_int8((unsigned char)0x0F);
4621 emit_int8((unsigned char)(0xC0 | encode));
4622 emit_int8(imm8);
4623 }
4624
4625 void Assembler::vpalignr(XMMRegister dst, XMMRegister nds, XMMRegister src, int imm8, int vector_len) {
4626 assert(vector_len == AVX_128bit? VM_Version::supports_avx() :
4627 vector_len == AVX_256bit? VM_Version::supports_avx2() :
4628 0, "");
4629 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
4630 int encode = simd_prefix_and_encode(dst, nds, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
4631 emit_int8((unsigned char)0x0F);
4632 emit_int8((unsigned char)(0xC0 | encode));
4633 emit_int8(imm8);
4634 }
4635
4636 void Assembler::evalignq(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8) {
4637 assert(VM_Version::supports_evex(), "");
4638 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
4639 attributes.set_is_evex_instruction();
4640 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
4641 emit_int8(0x3);
4642 emit_int8((unsigned char)(0xC0 | encode));
4643 emit_int8(imm8);
4644 }
4645
4646 void Assembler::pblendw(XMMRegister dst, XMMRegister src, int imm8) {
4647 assert(VM_Version::supports_sse4_1(), "");
4648 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
4649 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
4650 emit_int8((unsigned char)0x0E);
4651 emit_int8((unsigned char)(0xC0 | encode));
4652 emit_int8(imm8);
4653 }
4654
4655 void Assembler::sha1rnds4(XMMRegister dst, XMMRegister src, int imm8) {
4656 assert(VM_Version::supports_sha(), "");
4657 int encode = rex_prefix_and_encode(dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_3A, /* rex_w */ false);
4658 emit_int8((unsigned char)0xCC);
4659 emit_int8((unsigned char)(0xC0 | encode));
4660 emit_int8((unsigned char)imm8);
4661 }
4662
4663 void Assembler::sha1nexte(XMMRegister dst, XMMRegister src) {
4664 assert(VM_Version::supports_sha(), "");
4665 int encode = rex_prefix_and_encode(dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, /* rex_w */ false);
4666 emit_int8((unsigned char)0xC8);
4667 emit_int8((unsigned char)(0xC0 | encode));
4668 }
4669
4670 void Assembler::sha1msg1(XMMRegister dst, XMMRegister src) {
4671 assert(VM_Version::supports_sha(), "");
4672 int encode = rex_prefix_and_encode(dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, /* rex_w */ false);
4673 emit_int8((unsigned char)0xC9);
4674 emit_int8((unsigned char)(0xC0 | encode));
4675 }
4676
4677 void Assembler::sha1msg2(XMMRegister dst, XMMRegister src) {
4678 assert(VM_Version::supports_sha(), "");
4679 int encode = rex_prefix_and_encode(dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, /* rex_w */ false);
4680 emit_int8((unsigned char)0xCA);
4681 emit_int8((unsigned char)(0xC0 | encode));
4682 }
4683
4684 // xmm0 is implicit additional source to this instruction.
4685 void Assembler::sha256rnds2(XMMRegister dst, XMMRegister src) {
4686 assert(VM_Version::supports_sha(), "");
4687 int encode = rex_prefix_and_encode(dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, /* rex_w */ false);
4688 emit_int8((unsigned char)0xCB);
4689 emit_int8((unsigned char)(0xC0 | encode));
4690 }
4691
4692 void Assembler::sha256msg1(XMMRegister dst, XMMRegister src) {
4693 assert(VM_Version::supports_sha(), "");
4694 int encode = rex_prefix_and_encode(dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, /* rex_w */ false);
4695 emit_int8((unsigned char)0xCC);
4696 emit_int8((unsigned char)(0xC0 | encode));
4697 }
4698
4699 void Assembler::sha256msg2(XMMRegister dst, XMMRegister src) {
4700 assert(VM_Version::supports_sha(), "");
4701 int encode = rex_prefix_and_encode(dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, /* rex_w */ false);
4702 emit_int8((unsigned char)0xCD);
4703 emit_int8((unsigned char)(0xC0 | encode));
4704 }
4705
4706
4707 void Assembler::shll(Register dst, int imm8) {
4708 assert(isShiftCount(imm8), "illegal shift count");
4709 int encode = prefix_and_encode(dst->encoding());
4710 if (imm8 == 1 ) {
4711 emit_int8((unsigned char)0xD1);
4712 emit_int8((unsigned char)(0xE0 | encode));
4713 } else {
4714 emit_int8((unsigned char)0xC1);
4715 emit_int8((unsigned char)(0xE0 | encode));
4716 emit_int8(imm8);
4717 }
4718 }
4719
4720 void Assembler::shll(Register dst) {
4721 int encode = prefix_and_encode(dst->encoding());
4722 emit_int8((unsigned char)0xD3);
4723 emit_int8((unsigned char)(0xE0 | encode));
4724 }
4725
4726 void Assembler::shrl(Register dst, int imm8) {
4727 assert(isShiftCount(imm8), "illegal shift count");
4728 int encode = prefix_and_encode(dst->encoding());
4729 emit_int8((unsigned char)0xC1);
4730 emit_int8((unsigned char)(0xE8 | encode));
4731 emit_int8(imm8);
4732 }
4733
4734 void Assembler::shrl(Register dst) {
4735 int encode = prefix_and_encode(dst->encoding());
4736 emit_int8((unsigned char)0xD3);
4737 emit_int8((unsigned char)(0xE8 | encode));
4738 }
4739
4740 void Assembler::shldl(Register dst, Register src) {
4741 int encode = prefix_and_encode(src->encoding(), dst->encoding());
4742 emit_int8(0x0F);
4743 emit_int8((unsigned char)0xA5);
4744 emit_int8((unsigned char)(0xC0 | encode));
4745 }
4746
4747 void Assembler::shldl(Register dst, Register src, int8_t imm8) {
4748 int encode = prefix_and_encode(src->encoding(), dst->encoding());
4749 emit_int8(0x0F);
4750 emit_int8((unsigned char)0xA4);
4751 emit_int8((unsigned char)(0xC0 | encode));
4752 emit_int8(imm8);
4753 }
4754
4755 void Assembler::shrdl(Register dst, Register src) {
4756 int encode = prefix_and_encode(src->encoding(), dst->encoding());
4757 emit_int8(0x0F);
4758 emit_int8((unsigned char)0xAD);
4759 emit_int8((unsigned char)(0xC0 | encode));
4760 }
4761
4762 void Assembler::shrdl(Register dst, Register src, int8_t imm8) {
4763 int encode = prefix_and_encode(src->encoding(), dst->encoding());
4764 emit_int8(0x0F);
4765 emit_int8((unsigned char)0xAC);
4766 emit_int8((unsigned char)(0xC0 | encode));
4767 emit_int8(imm8);
4768 }
4769
4770 // copies a single word from [esi] to [edi]
4771 void Assembler::smovl() {
4772 emit_int8((unsigned char)0xA5);
4773 }
4774
4775 void Assembler::roundsd(XMMRegister dst, XMMRegister src, int32_t rmode) {
4776 assert(VM_Version::supports_sse4_1(), "");
4777 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
4778 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
4779 emit_int8(0x0B);
4780 emit_int8((unsigned char)(0xC0 | encode));
4781 emit_int8((unsigned char)rmode);
4782 }
4783
4784 void Assembler::roundsd(XMMRegister dst, Address src, int32_t rmode) {
4785 assert(VM_Version::supports_sse4_1(), "");
4786 InstructionMark im(this);
4787 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
4788 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
4789 emit_int8(0x0B);
4790 emit_operand(dst, src);
4791 emit_int8((unsigned char)rmode);
4792 }
4793
4794 void Assembler::sqrtsd(XMMRegister dst, XMMRegister src) {
4795 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4796 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4797 attributes.set_rex_vex_w_reverted();
4798 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4799 emit_int8(0x51);
4800 emit_int8((unsigned char)(0xC0 | encode));
4801 }
4802
4803 void Assembler::sqrtsd(XMMRegister dst, Address src) {
4804 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4805 InstructionMark im(this);
4806 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4807 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
4808 attributes.set_rex_vex_w_reverted();
4809 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4810 emit_int8(0x51);
4811 emit_operand(dst, src);
4812 }
4813
4814 void Assembler::sqrtss(XMMRegister dst, XMMRegister src) {
4815 NOT_LP64(assert(VM_Version::supports_sse(), ""));
4816 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4817 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4818 emit_int8(0x51);
4819 emit_int8((unsigned char)(0xC0 | encode));
4820 }
4821
4822 void Assembler::std() {
4823 emit_int8((unsigned char)0xFD);
4824 }
4825
4826 void Assembler::sqrtss(XMMRegister dst, Address src) {
4827 NOT_LP64(assert(VM_Version::supports_sse(), ""));
4828 InstructionMark im(this);
4829 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4830 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
4831 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4832 emit_int8(0x51);
4833 emit_operand(dst, src);
4834 }
4835
4836 void Assembler::stmxcsr( Address dst) {
4837 if (UseAVX > 0 ) {
4838 assert(VM_Version::supports_avx(), "");
4839 InstructionMark im(this);
4840 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
4841 vex_prefix(dst, 0, 0, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4842 emit_int8((unsigned char)0xAE);
4843 emit_operand(as_Register(3), dst);
4844 } else {
4845 NOT_LP64(assert(VM_Version::supports_sse(), ""));
4846 InstructionMark im(this);
4847 prefix(dst);
4848 emit_int8(0x0F);
4849 emit_int8((unsigned char)0xAE);
4850 emit_operand(as_Register(3), dst);
4851 }
4852 }
4853
4854 void Assembler::subl(Address dst, int32_t imm32) {
4855 InstructionMark im(this);
4856 prefix(dst);
4857 emit_arith_operand(0x81, rbp, dst, imm32);
4858 }
4859
4860 void Assembler::subl(Address dst, Register src) {
4861 InstructionMark im(this);
4862 prefix(dst, src);
4863 emit_int8(0x29);
4864 emit_operand(src, dst);
4865 }
4866
4867 void Assembler::subl(Register dst, int32_t imm32) {
4868 prefix(dst);
4869 emit_arith(0x81, 0xE8, dst, imm32);
4875 emit_arith_imm32(0x81, 0xE8, dst, imm32);
4876 }
4877
4878 void Assembler::subl(Register dst, Address src) {
4879 InstructionMark im(this);
4880 prefix(src, dst);
4881 emit_int8(0x2B);
4882 emit_operand(dst, src);
4883 }
4884
4885 void Assembler::subl(Register dst, Register src) {
4886 (void) prefix_and_encode(dst->encoding(), src->encoding());
4887 emit_arith(0x2B, 0xC0, dst, src);
4888 }
4889
4890 void Assembler::subsd(XMMRegister dst, XMMRegister src) {
4891 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4892 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4893 attributes.set_rex_vex_w_reverted();
4894 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4895 emit_int8(0x5C);
4896 emit_int8((unsigned char)(0xC0 | encode));
4897 }
4898
4899 void Assembler::subsd(XMMRegister dst, Address src) {
4900 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4901 InstructionMark im(this);
4902 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4903 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
4904 attributes.set_rex_vex_w_reverted();
4905 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4906 emit_int8(0x5C);
4907 emit_operand(dst, src);
4908 }
4909
4910 void Assembler::subss(XMMRegister dst, XMMRegister src) {
4911 NOT_LP64(assert(VM_Version::supports_sse(), ""));
4912 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true , /* uses_vl */ false);
4913 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4914 emit_int8(0x5C);
4915 emit_int8((unsigned char)(0xC0 | encode));
4916 }
4917
4918 void Assembler::subss(XMMRegister dst, Address src) {
4919 NOT_LP64(assert(VM_Version::supports_sse(), ""));
4920 InstructionMark im(this);
4921 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4922 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
4923 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4924 emit_int8(0x5C);
4925 emit_operand(dst, src);
4926 }
4927
4928 void Assembler::testb(Register dst, int imm8) {
4929 NOT_LP64(assert(dst->has_byte_register(), "must have byte register"));
4930 (void) prefix_and_encode(dst->encoding(), true);
4931 emit_arith_b(0xF6, 0xC0, dst, imm8);
4932 }
4933
4934 void Assembler::testb(Address dst, int imm8) {
4935 InstructionMark im(this);
4936 prefix(dst);
4937 emit_int8((unsigned char)0xF6);
4938 emit_operand(rax, dst, 1);
4939 emit_int8(imm8);
4940 }
4941
4942 void Assembler::testl(Register dst, int32_t imm32) {
4943 // not using emit_arith because test
4944 // doesn't support sign-extension of
4945 // 8bit operands
4946 int encode = dst->encoding();
4947 if (encode == 0) {
4948 emit_int8((unsigned char)0xA9);
4949 } else {
4950 encode = prefix_and_encode(encode);
4951 emit_int8((unsigned char)0xF7);
4952 emit_int8((unsigned char)(0xC0 | encode));
4953 }
4954 emit_int32(imm32);
4955 }
4956
4957 void Assembler::testl(Register dst, Register src) {
4958 (void) prefix_and_encode(dst->encoding(), src->encoding());
4959 emit_arith(0x85, 0xC0, dst, src);
4960 }
4961
4962 void Assembler::testl(Register dst, Address src) {
4963 InstructionMark im(this);
4964 prefix(src, dst);
4965 emit_int8((unsigned char)0x85);
4966 emit_operand(dst, src);
4967 }
4968
4969 void Assembler::tzcntl(Register dst, Register src) {
4970 assert(VM_Version::supports_bmi1(), "tzcnt instruction not supported");
4971 emit_int8((unsigned char)0xF3);
4972 int encode = prefix_and_encode(dst->encoding(), src->encoding());
4973 emit_int8(0x0F);
4974 emit_int8((unsigned char)0xBC);
4975 emit_int8((unsigned char)0xC0 | encode);
4976 }
4977
4978 void Assembler::tzcntq(Register dst, Register src) {
4979 assert(VM_Version::supports_bmi1(), "tzcnt instruction not supported");
4980 emit_int8((unsigned char)0xF3);
4981 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
4982 emit_int8(0x0F);
4983 emit_int8((unsigned char)0xBC);
4984 emit_int8((unsigned char)(0xC0 | encode));
4985 }
4986
4987 void Assembler::ucomisd(XMMRegister dst, Address src) {
4988 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4989 InstructionMark im(this);
4990 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4991 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
4992 attributes.set_rex_vex_w_reverted();
4993 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4994 emit_int8(0x2E);
4995 emit_operand(dst, src);
4996 }
4997
4998 void Assembler::ucomisd(XMMRegister dst, XMMRegister src) {
4999 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5000 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
5001 attributes.set_rex_vex_w_reverted();
5002 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5003 emit_int8(0x2E);
5004 emit_int8((unsigned char)(0xC0 | encode));
5005 }
5006
5007 void Assembler::ucomiss(XMMRegister dst, Address src) {
5008 NOT_LP64(assert(VM_Version::supports_sse(), ""));
5009 InstructionMark im(this);
5010 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
5011 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
5012 simd_prefix(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5013 emit_int8(0x2E);
5014 emit_operand(dst, src);
5015 }
5016
5017 void Assembler::ucomiss(XMMRegister dst, XMMRegister src) {
5018 NOT_LP64(assert(VM_Version::supports_sse(), ""));
5019 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
5020 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5021 emit_int8(0x2E);
5022 emit_int8((unsigned char)(0xC0 | encode));
5023 }
5024
5025 void Assembler::xabort(int8_t imm8) {
5026 emit_int8((unsigned char)0xC6);
5027 emit_int8((unsigned char)0xF8);
5028 emit_int8((unsigned char)(imm8 & 0xFF));
5029 }
5030
5031 void Assembler::xaddb(Address dst, Register src) {
5032 InstructionMark im(this);
5033 prefix(dst, src, true);
5034 emit_int8(0x0F);
5035 emit_int8((unsigned char)0xC0);
5036 emit_operand(src, dst);
5037 }
5038
5039 void Assembler::xaddw(Address dst, Register src) {
5040 InstructionMark im(this);
5041 emit_int8(0x66);
5042 prefix(dst, src);
5043 emit_int8(0x0F);
5044 emit_int8((unsigned char)0xC1);
5045 emit_operand(src, dst);
5046 }
5047
5048 void Assembler::xaddl(Address dst, Register src) {
5049 InstructionMark im(this);
5050 prefix(dst, src);
5051 emit_int8(0x0F);
5052 emit_int8((unsigned char)0xC1);
5053 emit_operand(src, dst);
5054 }
5055
5056 void Assembler::xbegin(Label& abort, relocInfo::relocType rtype) {
5057 InstructionMark im(this);
5058 relocate(rtype);
5059 if (abort.is_bound()) {
5060 address entry = target(abort);
5061 assert(entry != NULL, "abort entry NULL");
5062 intptr_t offset = entry - pc();
5063 emit_int8((unsigned char)0xC7);
5064 emit_int8((unsigned char)0xF8);
5065 emit_int32(offset - 6); // 2 opcode + 4 address
5066 } else {
5067 abort.add_patch_at(code(), locator());
5068 emit_int8((unsigned char)0xC7);
5069 emit_int8((unsigned char)0xF8);
5070 emit_int32(0);
5071 }
5072 }
5073
5074 void Assembler::xchgb(Register dst, Address src) { // xchg
5075 InstructionMark im(this);
5076 prefix(src, dst, true);
5077 emit_int8((unsigned char)0x86);
5078 emit_operand(dst, src);
5079 }
5080
5081 void Assembler::xchgw(Register dst, Address src) { // xchg
5082 InstructionMark im(this);
5083 emit_int8(0x66);
5084 prefix(src, dst);
5085 emit_int8((unsigned char)0x87);
5086 emit_operand(dst, src);
5087 }
5088
5089 void Assembler::xchgl(Register dst, Address src) { // xchg
5090 InstructionMark im(this);
5091 prefix(src, dst);
5092 emit_int8((unsigned char)0x87);
5093 emit_operand(dst, src);
5094 }
5095
5096 void Assembler::xchgl(Register dst, Register src) {
5097 int encode = prefix_and_encode(dst->encoding(), src->encoding());
5098 emit_int8((unsigned char)0x87);
5099 emit_int8((unsigned char)(0xC0 | encode));
5100 }
5101
5102 void Assembler::xend() {
5103 emit_int8((unsigned char)0x0F);
5104 emit_int8((unsigned char)0x01);
5105 emit_int8((unsigned char)0xD5);
5106 }
5107
5108 void Assembler::xgetbv() {
5109 emit_int8(0x0F);
5110 emit_int8(0x01);
5111 emit_int8((unsigned char)0xD0);
5112 }
5113
5114 void Assembler::xorl(Register dst, int32_t imm32) {
5115 prefix(dst);
5116 emit_arith(0x81, 0xF0, dst, imm32);
5117 }
5118
5119 void Assembler::xorl(Register dst, Address src) {
5120 InstructionMark im(this);
5121 prefix(src, dst);
5122 emit_int8(0x33);
5123 emit_operand(dst, src);
5124 }
5125
5126 void Assembler::xorl(Register dst, Register src) {
5127 (void) prefix_and_encode(dst->encoding(), src->encoding());
5128 emit_arith(0x33, 0xC0, dst, src);
5129 }
5130
5131 void Assembler::xorb(Register dst, Address src) {
5136 }
5137
5138 // AVX 3-operands scalar float-point arithmetic instructions
5139
5140 void Assembler::vaddsd(XMMRegister dst, XMMRegister nds, Address src) {
5141 assert(VM_Version::supports_avx(), "");
5142 InstructionMark im(this);
5143 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
5144 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
5145 attributes.set_rex_vex_w_reverted();
5146 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
5147 emit_int8(0x58);
5148 emit_operand(dst, src);
5149 }
5150
5151 void Assembler::vaddsd(XMMRegister dst, XMMRegister nds, XMMRegister src) {
5152 assert(VM_Version::supports_avx(), "");
5153 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
5154 attributes.set_rex_vex_w_reverted();
5155 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
5156 emit_int8(0x58);
5157 emit_int8((unsigned char)(0xC0 | encode));
5158 }
5159
5160 void Assembler::vaddss(XMMRegister dst, XMMRegister nds, Address src) {
5161 assert(VM_Version::supports_avx(), "");
5162 InstructionMark im(this);
5163 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
5164 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
5165 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
5166 emit_int8(0x58);
5167 emit_operand(dst, src);
5168 }
5169
5170 void Assembler::vaddss(XMMRegister dst, XMMRegister nds, XMMRegister src) {
5171 assert(VM_Version::supports_avx(), "");
5172 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
5173 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
5174 emit_int8(0x58);
5175 emit_int8((unsigned char)(0xC0 | encode));
5176 }
5177
5178 void Assembler::vdivsd(XMMRegister dst, XMMRegister nds, Address src) {
5179 assert(VM_Version::supports_avx(), "");
5180 InstructionMark im(this);
5181 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
5182 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
5183 attributes.set_rex_vex_w_reverted();
5184 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
5185 emit_int8(0x5E);
5186 emit_operand(dst, src);
5187 }
5188
5189 void Assembler::vdivsd(XMMRegister dst, XMMRegister nds, XMMRegister src) {
5190 assert(VM_Version::supports_avx(), "");
5191 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
5192 attributes.set_rex_vex_w_reverted();
5193 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
5194 emit_int8(0x5E);
5195 emit_int8((unsigned char)(0xC0 | encode));
5196 }
5197
5198 void Assembler::vdivss(XMMRegister dst, XMMRegister nds, Address src) {
5199 assert(VM_Version::supports_avx(), "");
5200 InstructionMark im(this);
5201 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
5202 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
5203 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
5204 emit_int8(0x5E);
5205 emit_operand(dst, src);
5206 }
5207
5208 void Assembler::vdivss(XMMRegister dst, XMMRegister nds, XMMRegister src) {
5209 assert(VM_Version::supports_avx(), "");
5210 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
5211 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
5212 emit_int8(0x5E);
5213 emit_int8((unsigned char)(0xC0 | encode));
5214 }
5215
5216 void Assembler::vfmadd231sd(XMMRegister dst, XMMRegister src1, XMMRegister src2) {
5217 assert(VM_Version::supports_fma(), "");
5218 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
5219 int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5220 emit_int8((unsigned char)0xB9);
5221 emit_int8((unsigned char)(0xC0 | encode));
5222 }
5223
5224 void Assembler::vfmadd231ss(XMMRegister dst, XMMRegister src1, XMMRegister src2) {
5225 assert(VM_Version::supports_fma(), "");
5226 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
5227 int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5228 emit_int8((unsigned char)0xB9);
5229 emit_int8((unsigned char)(0xC0 | encode));
5230 }
5231
5232 void Assembler::vmulsd(XMMRegister dst, XMMRegister nds, Address src) {
5233 assert(VM_Version::supports_avx(), "");
5234 InstructionMark im(this);
5235 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
5236 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
5237 attributes.set_rex_vex_w_reverted();
5238 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
5239 emit_int8(0x59);
5240 emit_operand(dst, src);
5241 }
5242
5243 void Assembler::vmulsd(XMMRegister dst, XMMRegister nds, XMMRegister src) {
5244 assert(VM_Version::supports_avx(), "");
5245 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
5246 attributes.set_rex_vex_w_reverted();
5247 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
5248 emit_int8(0x59);
5249 emit_int8((unsigned char)(0xC0 | encode));
5250 }
5251
5252 void Assembler::vmulss(XMMRegister dst, XMMRegister nds, Address src) {
5253 assert(VM_Version::supports_avx(), "");
5254 InstructionMark im(this);
5255 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
5256 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
5257 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
5258 emit_int8(0x59);
5259 emit_operand(dst, src);
5260 }
5261
5262 void Assembler::vmulss(XMMRegister dst, XMMRegister nds, XMMRegister src) {
5263 assert(VM_Version::supports_avx(), "");
5264 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
5265 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
5266 emit_int8(0x59);
5267 emit_int8((unsigned char)(0xC0 | encode));
5268 }
5269
5270 void Assembler::vsubsd(XMMRegister dst, XMMRegister nds, Address src) {
5271 assert(VM_Version::supports_avx(), "");
5272 InstructionMark im(this);
5273 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
5274 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
5275 attributes.set_rex_vex_w_reverted();
5276 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
5277 emit_int8(0x5C);
5278 emit_operand(dst, src);
5279 }
5280
5281 void Assembler::vsubsd(XMMRegister dst, XMMRegister nds, XMMRegister src) {
5282 assert(VM_Version::supports_avx(), "");
5283 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
5284 attributes.set_rex_vex_w_reverted();
5285 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
5286 emit_int8(0x5C);
5287 emit_int8((unsigned char)(0xC0 | encode));
5288 }
5289
5290 void Assembler::vsubss(XMMRegister dst, XMMRegister nds, Address src) {
5291 assert(VM_Version::supports_avx(), "");
5292 InstructionMark im(this);
5293 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
5294 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
5295 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
5296 emit_int8(0x5C);
5297 emit_operand(dst, src);
5298 }
5299
5300 void Assembler::vsubss(XMMRegister dst, XMMRegister nds, XMMRegister src) {
5301 assert(VM_Version::supports_avx(), "");
5302 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
5303 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
5304 emit_int8(0x5C);
5305 emit_int8((unsigned char)(0xC0 | encode));
5306 }
5307
5308 //====================VECTOR ARITHMETIC=====================================
5309
5310 // Float-point vector arithmetic
5311
5312 void Assembler::addpd(XMMRegister dst, XMMRegister src) {
5313 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5314 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5315 attributes.set_rex_vex_w_reverted();
5316 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5317 emit_int8(0x58);
5318 emit_int8((unsigned char)(0xC0 | encode));
5319 }
5320
5321 void Assembler::addpd(XMMRegister dst, Address src) {
5322 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5323 InstructionMark im(this);
5324 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5325 attributes.set_rex_vex_w_reverted();
5326 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
5327 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5328 emit_int8(0x58);
5329 emit_operand(dst, src);
5330 }
5331
5332
5333 void Assembler::addps(XMMRegister dst, XMMRegister src) {
5334 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5335 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5336 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5337 emit_int8(0x58);
5338 emit_int8((unsigned char)(0xC0 | encode));
5339 }
5340
5341 void Assembler::vaddpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5342 assert(VM_Version::supports_avx(), "");
5343 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5344 attributes.set_rex_vex_w_reverted();
5345 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5346 emit_int8(0x58);
5347 emit_int8((unsigned char)(0xC0 | encode));
5348 }
5349
5350 void Assembler::vaddps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5351 assert(VM_Version::supports_avx(), "");
5352 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5353 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5354 emit_int8(0x58);
5355 emit_int8((unsigned char)(0xC0 | encode));
5356 }
5357
5358 void Assembler::vaddpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5359 assert(VM_Version::supports_avx(), "");
5360 InstructionMark im(this);
5361 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5362 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
5363 attributes.set_rex_vex_w_reverted();
5364 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5365 emit_int8(0x58);
5366 emit_operand(dst, src);
5367 }
5368
5369 void Assembler::vaddps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5370 assert(VM_Version::supports_avx(), "");
5371 InstructionMark im(this);
5372 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5373 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
5374 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5375 emit_int8(0x58);
5376 emit_operand(dst, src);
5377 }
5378
5379 void Assembler::subpd(XMMRegister dst, XMMRegister src) {
5380 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5381 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5382 attributes.set_rex_vex_w_reverted();
5383 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5384 emit_int8(0x5C);
5385 emit_int8((unsigned char)(0xC0 | encode));
5386 }
5387
5388 void Assembler::subps(XMMRegister dst, XMMRegister src) {
5389 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5390 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5391 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5392 emit_int8(0x5C);
5393 emit_int8((unsigned char)(0xC0 | encode));
5394 }
5395
5396 void Assembler::vsubpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5397 assert(VM_Version::supports_avx(), "");
5398 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5399 attributes.set_rex_vex_w_reverted();
5400 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5401 emit_int8(0x5C);
5402 emit_int8((unsigned char)(0xC0 | encode));
5403 }
5404
5405 void Assembler::vsubps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5406 assert(VM_Version::supports_avx(), "");
5407 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5408 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5409 emit_int8(0x5C);
5410 emit_int8((unsigned char)(0xC0 | encode));
5411 }
5412
5413 void Assembler::vsubpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5414 assert(VM_Version::supports_avx(), "");
5415 InstructionMark im(this);
5416 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5417 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
5418 attributes.set_rex_vex_w_reverted();
5419 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5420 emit_int8(0x5C);
5421 emit_operand(dst, src);
5422 }
5423
5424 void Assembler::vsubps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5425 assert(VM_Version::supports_avx(), "");
5426 InstructionMark im(this);
5427 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5428 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
5429 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5430 emit_int8(0x5C);
5431 emit_operand(dst, src);
5432 }
5433
5434 void Assembler::mulpd(XMMRegister dst, XMMRegister src) {
5435 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5436 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5437 attributes.set_rex_vex_w_reverted();
5438 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5439 emit_int8(0x59);
5440 emit_int8((unsigned char)(0xC0 | encode));
5441 }
5442
5443 void Assembler::mulpd(XMMRegister dst, Address src) {
5444 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5445 InstructionMark im(this);
5446 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5447 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
5448 attributes.set_rex_vex_w_reverted();
5449 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5450 emit_int8(0x59);
5451 emit_operand(dst, src);
5452 }
5453
5454 void Assembler::mulps(XMMRegister dst, XMMRegister src) {
5455 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5456 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5457 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5458 emit_int8(0x59);
5459 emit_int8((unsigned char)(0xC0 | encode));
5460 }
5461
5462 void Assembler::vmulpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5463 assert(VM_Version::supports_avx(), "");
5464 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5465 attributes.set_rex_vex_w_reverted();
5466 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5467 emit_int8(0x59);
5468 emit_int8((unsigned char)(0xC0 | encode));
5469 }
5470
5471 void Assembler::vmulps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5472 assert(VM_Version::supports_avx(), "");
5473 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5474 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5475 emit_int8(0x59);
5476 emit_int8((unsigned char)(0xC0 | encode));
5477 }
5478
5479 void Assembler::vmulpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5480 assert(VM_Version::supports_avx(), "");
5481 InstructionMark im(this);
5482 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5483 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
5484 attributes.set_rex_vex_w_reverted();
5485 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5486 emit_int8(0x59);
5487 emit_operand(dst, src);
5488 }
5489
5490 void Assembler::vmulps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5491 assert(VM_Version::supports_avx(), "");
5492 InstructionMark im(this);
5493 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5494 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
5495 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5496 emit_int8(0x59);
5497 emit_operand(dst, src);
5498 }
5499
5500 void Assembler::vfmadd231pd(XMMRegister dst, XMMRegister src1, XMMRegister src2, int vector_len) {
5501 assert(VM_Version::supports_fma(), "");
5502 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5503 int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5504 emit_int8((unsigned char)0xB8);
5505 emit_int8((unsigned char)(0xC0 | encode));
5506 }
5507
5508 void Assembler::vfmadd231ps(XMMRegister dst, XMMRegister src1, XMMRegister src2, int vector_len) {
5509 assert(VM_Version::supports_fma(), "");
5510 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5511 int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5512 emit_int8((unsigned char)0xB8);
5513 emit_int8((unsigned char)(0xC0 | encode));
5514 }
5515
5516 void Assembler::vfmadd231pd(XMMRegister dst, XMMRegister src1, Address src2, int vector_len) {
5517 assert(VM_Version::supports_fma(), "");
5518 InstructionMark im(this);
5519 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5520 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
5521 vex_prefix(src2, src1->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5522 emit_int8((unsigned char)0xB8);
5523 emit_operand(dst, src2);
5524 }
5525
5526 void Assembler::vfmadd231ps(XMMRegister dst, XMMRegister src1, Address src2, int vector_len) {
5527 assert(VM_Version::supports_fma(), "");
5528 InstructionMark im(this);
5529 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5530 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
5531 vex_prefix(src2, src1->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5532 emit_int8((unsigned char)0xB8);
5533 emit_operand(dst, src2);
5534 }
5535
5536 void Assembler::divpd(XMMRegister dst, XMMRegister src) {
5537 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5538 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5539 attributes.set_rex_vex_w_reverted();
5540 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5541 emit_int8(0x5E);
5542 emit_int8((unsigned char)(0xC0 | encode));
5543 }
5544
5545 void Assembler::divps(XMMRegister dst, XMMRegister src) {
5546 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5547 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5548 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5549 emit_int8(0x5E);
5550 emit_int8((unsigned char)(0xC0 | encode));
5551 }
5552
5553 void Assembler::vdivpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5554 assert(VM_Version::supports_avx(), "");
5555 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5556 attributes.set_rex_vex_w_reverted();
5557 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5558 emit_int8(0x5E);
5559 emit_int8((unsigned char)(0xC0 | encode));
5560 }
5561
5562 void Assembler::vdivps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5563 assert(VM_Version::supports_avx(), "");
5564 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5565 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5566 emit_int8(0x5E);
5567 emit_int8((unsigned char)(0xC0 | encode));
5568 }
5569
5570 void Assembler::vdivpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5571 assert(VM_Version::supports_avx(), "");
5572 InstructionMark im(this);
5573 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5574 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
5575 attributes.set_rex_vex_w_reverted();
5576 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5577 emit_int8(0x5E);
5578 emit_operand(dst, src);
5579 }
5580
5581 void Assembler::vdivps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5582 assert(VM_Version::supports_avx(), "");
5583 InstructionMark im(this);
5584 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5585 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
5586 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5587 emit_int8(0x5E);
5588 emit_operand(dst, src);
5589 }
5590
5591 void Assembler::vroundpd(XMMRegister dst, XMMRegister src, int32_t rmode, int vector_len) {
5592 assert(VM_Version::supports_avx(), "");
5593 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
5594 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
5595 emit_int8(0x09);
5596 emit_int8((unsigned char)(0xC0 | encode));
5597 emit_int8((unsigned char)(rmode));
5598 }
5599
5600 void Assembler::vroundpd(XMMRegister dst, Address src, int32_t rmode, int vector_len) {
5601 assert(VM_Version::supports_avx(), "");
5602 InstructionMark im(this);
5603 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
5604 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
5605 emit_int8(0x09);
5606 emit_operand(dst, src);
5607 emit_int8((unsigned char)(rmode));
5608 }
5609
5610 void Assembler::vrndscalepd(XMMRegister dst, XMMRegister src, int32_t rmode, int vector_len) {
5611 assert(VM_Version::supports_evex(), "requires EVEX support");
5612 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5613 attributes.set_is_evex_instruction();
5614 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
5615 emit_int8((unsigned char)0x09);
5616 emit_int8((unsigned char)(0xC0 | encode));
5617 emit_int8((unsigned char)(rmode));
5618 }
5619
5620 void Assembler::vrndscalepd(XMMRegister dst, Address src, int32_t rmode, int vector_len) {
5621 assert(VM_Version::supports_evex(), "requires EVEX support");
5622 assert(dst != xnoreg, "sanity");
5623 InstructionMark im(this);
5624 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5625 attributes.set_is_evex_instruction();
5626 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
5627 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
5628 emit_int8((unsigned char)0x09);
5629 emit_operand(dst, src);
5630 emit_int8((unsigned char)(rmode));
5631 }
5632
5633
5634 void Assembler::vsqrtpd(XMMRegister dst, XMMRegister src, int vector_len) {
5635 assert(VM_Version::supports_avx(), "");
5636 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5637 attributes.set_rex_vex_w_reverted();
5638 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5639 emit_int8(0x51);
5640 emit_int8((unsigned char)(0xC0 | encode));
5641 }
5642
5643 void Assembler::vsqrtpd(XMMRegister dst, Address src, int vector_len) {
5644 assert(VM_Version::supports_avx(), "");
5645 InstructionMark im(this);
5646 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5647 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
5648 attributes.set_rex_vex_w_reverted();
5649 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5650 emit_int8(0x51);
5651 emit_operand(dst, src);
5652 }
5653
5654 void Assembler::vsqrtps(XMMRegister dst, XMMRegister src, int vector_len) {
5655 assert(VM_Version::supports_avx(), "");
5656 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5657 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5658 emit_int8(0x51);
5659 emit_int8((unsigned char)(0xC0 | encode));
5660 }
5661
5662 void Assembler::vsqrtps(XMMRegister dst, Address src, int vector_len) {
5663 assert(VM_Version::supports_avx(), "");
5664 InstructionMark im(this);
5665 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5666 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
5667 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5668 emit_int8(0x51);
5669 emit_operand(dst, src);
5670 }
5671
5672 void Assembler::andpd(XMMRegister dst, XMMRegister src) {
5673 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5674 InstructionAttr attributes(AVX_128bit, /* rex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true);
5675 attributes.set_rex_vex_w_reverted();
5676 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5677 emit_int8(0x54);
5678 emit_int8((unsigned char)(0xC0 | encode));
5679 }
5680
5681 void Assembler::andps(XMMRegister dst, XMMRegister src) {
5682 NOT_LP64(assert(VM_Version::supports_sse(), ""));
5683 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true);
5684 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5685 emit_int8(0x54);
5686 emit_int8((unsigned char)(0xC0 | encode));
5687 }
5688
5689 void Assembler::andps(XMMRegister dst, Address src) {
5690 NOT_LP64(assert(VM_Version::supports_sse(), ""));
5691 InstructionMark im(this);
5692 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true);
5693 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
5694 simd_prefix(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5695 emit_int8(0x54);
5696 emit_operand(dst, src);
5697 }
5698
5699 void Assembler::andpd(XMMRegister dst, Address src) {
5700 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5701 InstructionMark im(this);
5702 InstructionAttr attributes(AVX_128bit, /* rex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true);
5703 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
5704 attributes.set_rex_vex_w_reverted();
5705 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5706 emit_int8(0x54);
5707 emit_operand(dst, src);
5708 }
5709
5710 void Assembler::vandpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5711 assert(VM_Version::supports_avx(), "");
5712 InstructionAttr attributes(vector_len, /* vex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true);
5713 attributes.set_rex_vex_w_reverted();
5714 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5715 emit_int8(0x54);
5716 emit_int8((unsigned char)(0xC0 | encode));
5717 }
5718
5719 void Assembler::vandps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5720 assert(VM_Version::supports_avx(), "");
5721 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true);
5722 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5723 emit_int8(0x54);
5724 emit_int8((unsigned char)(0xC0 | encode));
5725 }
5726
5727 void Assembler::vandpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5728 assert(VM_Version::supports_avx(), "");
5729 InstructionMark im(this);
5730 InstructionAttr attributes(vector_len, /* vex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true);
5731 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
5732 attributes.set_rex_vex_w_reverted();
5733 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5734 emit_int8(0x54);
5735 emit_operand(dst, src);
5736 }
5737
5738 void Assembler::vandps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5739 assert(VM_Version::supports_avx(), "");
5740 InstructionMark im(this);
5741 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true);
5742 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
5743 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5744 emit_int8(0x54);
5745 emit_operand(dst, src);
5746 }
5747
5748 void Assembler::unpckhpd(XMMRegister dst, XMMRegister src) {
5749 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5750 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5751 attributes.set_rex_vex_w_reverted();
5752 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5753 emit_int8(0x15);
5754 emit_int8((unsigned char)(0xC0 | encode));
5755 }
5756
5757 void Assembler::unpcklpd(XMMRegister dst, XMMRegister src) {
5758 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5759 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5760 attributes.set_rex_vex_w_reverted();
5761 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5762 emit_int8(0x14);
5763 emit_int8((unsigned char)(0xC0 | encode));
5764 }
5765
5766 void Assembler::xorpd(XMMRegister dst, XMMRegister src) {
5767 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5768 InstructionAttr attributes(AVX_128bit, /* rex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true);
5769 attributes.set_rex_vex_w_reverted();
5770 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5771 emit_int8(0x57);
5772 emit_int8((unsigned char)(0xC0 | encode));
5773 }
5774
5775 void Assembler::xorps(XMMRegister dst, XMMRegister src) {
5776 NOT_LP64(assert(VM_Version::supports_sse(), ""));
5777 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true);
5778 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5779 emit_int8(0x57);
5780 emit_int8((unsigned char)(0xC0 | encode));
5781 }
5782
5783 void Assembler::xorpd(XMMRegister dst, Address src) {
5784 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5785 InstructionMark im(this);
5786 InstructionAttr attributes(AVX_128bit, /* rex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true);
5787 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
5788 attributes.set_rex_vex_w_reverted();
5789 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5790 emit_int8(0x57);
5791 emit_operand(dst, src);
5792 }
5793
5794 void Assembler::xorps(XMMRegister dst, Address src) {
5795 NOT_LP64(assert(VM_Version::supports_sse(), ""));
5796 InstructionMark im(this);
5797 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true);
5798 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
5799 simd_prefix(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5800 emit_int8(0x57);
5801 emit_operand(dst, src);
5802 }
5803
5804 void Assembler::vxorpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5805 assert(VM_Version::supports_avx(), "");
5806 InstructionAttr attributes(vector_len, /* vex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true);
5807 attributes.set_rex_vex_w_reverted();
5808 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5809 emit_int8(0x57);
5810 emit_int8((unsigned char)(0xC0 | encode));
5811 }
5812
5813 void Assembler::vxorps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5814 assert(VM_Version::supports_avx(), "");
5815 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true);
5816 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5817 emit_int8(0x57);
5818 emit_int8((unsigned char)(0xC0 | encode));
5819 }
5820
5821 void Assembler::vxorpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5822 assert(VM_Version::supports_avx(), "");
5823 InstructionMark im(this);
5824 InstructionAttr attributes(vector_len, /* vex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true);
5825 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
5826 attributes.set_rex_vex_w_reverted();
5827 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5828 emit_int8(0x57);
5829 emit_operand(dst, src);
5830 }
5831
5832 void Assembler::vxorps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5833 assert(VM_Version::supports_avx(), "");
5834 InstructionMark im(this);
5835 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true);
5836 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
5837 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5838 emit_int8(0x57);
5839 emit_operand(dst, src);
5840 }
5841
5842 // Integer vector arithmetic
5843 void Assembler::vphaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5844 assert(VM_Version::supports_avx() && (vector_len == 0) ||
5845 VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
5846 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ true);
5847 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5848 emit_int8(0x01);
5849 emit_int8((unsigned char)(0xC0 | encode));
5850 }
5851
5852 void Assembler::vphaddd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5853 assert(VM_Version::supports_avx() && (vector_len == 0) ||
5854 VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
5855 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ true);
5856 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5857 emit_int8(0x02);
5858 emit_int8((unsigned char)(0xC0 | encode));
5859 }
5860
5861 void Assembler::paddb(XMMRegister dst, XMMRegister src) {
5862 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5863 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5864 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5865 emit_int8((unsigned char)0xFC);
5866 emit_int8((unsigned char)(0xC0 | encode));
5867 }
5868
5869 void Assembler::paddw(XMMRegister dst, XMMRegister src) {
5870 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5871 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5872 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5873 emit_int8((unsigned char)0xFD);
5874 emit_int8((unsigned char)(0xC0 | encode));
5875 }
5876
5877 void Assembler::paddd(XMMRegister dst, XMMRegister src) {
5878 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5879 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5880 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5881 emit_int8((unsigned char)0xFE);
5882 emit_int8((unsigned char)(0xC0 | encode));
5883 }
5884
5885 void Assembler::paddd(XMMRegister dst, Address src) {
5886 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5887 InstructionMark im(this);
5888 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5889 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5890 emit_int8((unsigned char)0xFE);
5891 emit_operand(dst, src);
5892 }
5893
5894 void Assembler::paddq(XMMRegister dst, XMMRegister src) {
5895 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5896 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5897 attributes.set_rex_vex_w_reverted();
5898 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5899 emit_int8((unsigned char)0xD4);
5900 emit_int8((unsigned char)(0xC0 | encode));
5901 }
5902
5903 void Assembler::phaddw(XMMRegister dst, XMMRegister src) {
5904 assert(VM_Version::supports_sse3(), "");
5905 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ true);
5906 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5907 emit_int8(0x01);
5908 emit_int8((unsigned char)(0xC0 | encode));
5909 }
5910
5911 void Assembler::phaddd(XMMRegister dst, XMMRegister src) {
5912 assert(VM_Version::supports_sse3(), "");
5913 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ true);
5914 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5915 emit_int8(0x02);
5916 emit_int8((unsigned char)(0xC0 | encode));
5917 }
5918
5919 void Assembler::vpaddb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5920 assert(UseAVX > 0, "requires some form of AVX");
5921 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5922 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5923 emit_int8((unsigned char)0xFC);
5924 emit_int8((unsigned char)(0xC0 | encode));
5925 }
5926
5927 void Assembler::vpaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5928 assert(UseAVX > 0, "requires some form of AVX");
5929 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5930 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5931 emit_int8((unsigned char)0xFD);
5932 emit_int8((unsigned char)(0xC0 | encode));
5933 }
5934
5935 void Assembler::vpaddd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5936 assert(UseAVX > 0, "requires some form of AVX");
5937 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5938 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5939 emit_int8((unsigned char)0xFE);
5940 emit_int8((unsigned char)(0xC0 | encode));
5941 }
5942
5943 void Assembler::vpaddq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5944 assert(UseAVX > 0, "requires some form of AVX");
5945 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5946 attributes.set_rex_vex_w_reverted();
5947 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5948 emit_int8((unsigned char)0xD4);
5949 emit_int8((unsigned char)(0xC0 | encode));
5950 }
5951
5952 void Assembler::vpaddb(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5953 assert(UseAVX > 0, "requires some form of AVX");
5954 InstructionMark im(this);
5955 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5956 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
5957 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5958 emit_int8((unsigned char)0xFC);
5959 emit_operand(dst, src);
5960 }
5961
5962 void Assembler::vpaddw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5963 assert(UseAVX > 0, "requires some form of AVX");
5964 InstructionMark im(this);
5965 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5966 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
5967 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5968 emit_int8((unsigned char)0xFD);
5969 emit_operand(dst, src);
5977 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5978 emit_int8((unsigned char)0xFE);
5979 emit_operand(dst, src);
5980 }
5981
5982 void Assembler::vpaddq(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5983 assert(UseAVX > 0, "requires some form of AVX");
5984 InstructionMark im(this);
5985 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5986 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
5987 attributes.set_rex_vex_w_reverted();
5988 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5989 emit_int8((unsigned char)0xD4);
5990 emit_operand(dst, src);
5991 }
5992
5993 void Assembler::psubb(XMMRegister dst, XMMRegister src) {
5994 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5995 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5996 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5997 emit_int8((unsigned char)0xF8);
5998 emit_int8((unsigned char)(0xC0 | encode));
5999 }
6000
6001 void Assembler::psubw(XMMRegister dst, XMMRegister src) {
6002 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6003 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
6004 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6005 emit_int8((unsigned char)0xF9);
6006 emit_int8((unsigned char)(0xC0 | encode));
6007 }
6008
6009 void Assembler::psubd(XMMRegister dst, XMMRegister src) {
6010 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6011 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6012 emit_int8((unsigned char)0xFA);
6013 emit_int8((unsigned char)(0xC0 | encode));
6014 }
6015
6016 void Assembler::psubq(XMMRegister dst, XMMRegister src) {
6017 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6018 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6019 attributes.set_rex_vex_w_reverted();
6020 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6021 emit_int8((unsigned char)0xFB);
6022 emit_int8((unsigned char)(0xC0 | encode));
6023 }
6024
6025 void Assembler::vpsubb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
6026 assert(UseAVX > 0, "requires some form of AVX");
6027 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
6028 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6029 emit_int8((unsigned char)0xF8);
6030 emit_int8((unsigned char)(0xC0 | encode));
6031 }
6032
6033 void Assembler::vpsubw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
6034 assert(UseAVX > 0, "requires some form of AVX");
6035 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
6036 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6037 emit_int8((unsigned char)0xF9);
6038 emit_int8((unsigned char)(0xC0 | encode));
6039 }
6040
6041 void Assembler::vpsubd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
6042 assert(UseAVX > 0, "requires some form of AVX");
6043 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6044 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6045 emit_int8((unsigned char)0xFA);
6046 emit_int8((unsigned char)(0xC0 | encode));
6047 }
6048
6049 void Assembler::vpsubq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
6050 assert(UseAVX > 0, "requires some form of AVX");
6051 InstructionAttr attributes(vector_len, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6052 attributes.set_rex_vex_w_reverted();
6053 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6054 emit_int8((unsigned char)0xFB);
6055 emit_int8((unsigned char)(0xC0 | encode));
6056 }
6057
6058 void Assembler::vpsubb(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
6059 assert(UseAVX > 0, "requires some form of AVX");
6060 InstructionMark im(this);
6061 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
6062 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
6063 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6064 emit_int8((unsigned char)0xF8);
6065 emit_operand(dst, src);
6066 }
6067
6068 void Assembler::vpsubw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
6069 assert(UseAVX > 0, "requires some form of AVX");
6070 InstructionMark im(this);
6071 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
6072 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
6073 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6074 emit_int8((unsigned char)0xF9);
6075 emit_operand(dst, src);
6083 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6084 emit_int8((unsigned char)0xFA);
6085 emit_operand(dst, src);
6086 }
6087
6088 void Assembler::vpsubq(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
6089 assert(UseAVX > 0, "requires some form of AVX");
6090 InstructionMark im(this);
6091 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6092 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
6093 attributes.set_rex_vex_w_reverted();
6094 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6095 emit_int8((unsigned char)0xFB);
6096 emit_operand(dst, src);
6097 }
6098
6099 void Assembler::pmullw(XMMRegister dst, XMMRegister src) {
6100 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6101 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
6102 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6103 emit_int8((unsigned char)0xD5);
6104 emit_int8((unsigned char)(0xC0 | encode));
6105 }
6106
6107 void Assembler::pmulld(XMMRegister dst, XMMRegister src) {
6108 assert(VM_Version::supports_sse4_1(), "");
6109 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6110 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6111 emit_int8(0x40);
6112 emit_int8((unsigned char)(0xC0 | encode));
6113 }
6114
6115 void Assembler::vpmullw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
6116 assert(UseAVX > 0, "requires some form of AVX");
6117 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
6118 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6119 emit_int8((unsigned char)0xD5);
6120 emit_int8((unsigned char)(0xC0 | encode));
6121 }
6122
6123 void Assembler::vpmulld(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
6124 assert(UseAVX > 0, "requires some form of AVX");
6125 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6126 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6127 emit_int8(0x40);
6128 emit_int8((unsigned char)(0xC0 | encode));
6129 }
6130
6131 void Assembler::vpmullq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
6132 assert(UseAVX > 2, "requires some form of EVEX");
6133 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true);
6134 attributes.set_is_evex_instruction();
6135 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6136 emit_int8(0x40);
6137 emit_int8((unsigned char)(0xC0 | encode));
6138 }
6139
6140 void Assembler::vpmullw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
6141 assert(UseAVX > 0, "requires some form of AVX");
6142 InstructionMark im(this);
6143 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
6144 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
6145 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6146 emit_int8((unsigned char)0xD5);
6147 emit_operand(dst, src);
6148 }
6149
6150 void Assembler::vpmulld(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
6151 assert(UseAVX > 0, "requires some form of AVX");
6152 InstructionMark im(this);
6153 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6154 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
6155 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6156 emit_int8(0x40);
6157 emit_operand(dst, src);
6158 }
6159
6160 void Assembler::vpmullq(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
6161 assert(UseAVX > 2, "requires some form of EVEX");
6162 InstructionMark im(this);
6163 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true);
6164 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
6165 attributes.set_is_evex_instruction();
6166 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6167 emit_int8(0x40);
6168 emit_operand(dst, src);
6169 }
6170
6171 // Shift packed integers left by specified number of bits.
6172 void Assembler::psllw(XMMRegister dst, int shift) {
6173 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6174 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
6175 // XMM6 is for /6 encoding: 66 0F 71 /6 ib
6176 int encode = simd_prefix_and_encode(xmm6, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6177 emit_int8(0x71);
6178 emit_int8((unsigned char)(0xC0 | encode));
6179 emit_int8(shift & 0xFF);
6180 }
6181
6182 void Assembler::pslld(XMMRegister dst, int shift) {
6183 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6184 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6185 // XMM6 is for /6 encoding: 66 0F 72 /6 ib
6186 int encode = simd_prefix_and_encode(xmm6, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6187 emit_int8(0x72);
6188 emit_int8((unsigned char)(0xC0 | encode));
6189 emit_int8(shift & 0xFF);
6190 }
6191
6192 void Assembler::psllq(XMMRegister dst, int shift) {
6193 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6194 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6195 // XMM6 is for /6 encoding: 66 0F 73 /6 ib
6196 int encode = simd_prefix_and_encode(xmm6, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6197 emit_int8(0x73);
6198 emit_int8((unsigned char)(0xC0 | encode));
6199 emit_int8(shift & 0xFF);
6200 }
6201
6202 void Assembler::psllw(XMMRegister dst, XMMRegister shift) {
6203 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6204 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
6205 int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6206 emit_int8((unsigned char)0xF1);
6207 emit_int8((unsigned char)(0xC0 | encode));
6208 }
6209
6210 void Assembler::pslld(XMMRegister dst, XMMRegister shift) {
6211 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6212 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6213 int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6214 emit_int8((unsigned char)0xF2);
6215 emit_int8((unsigned char)(0xC0 | encode));
6216 }
6217
6218 void Assembler::psllq(XMMRegister dst, XMMRegister shift) {
6219 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6220 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6221 attributes.set_rex_vex_w_reverted();
6222 int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6223 emit_int8((unsigned char)0xF3);
6224 emit_int8((unsigned char)(0xC0 | encode));
6225 }
6226
6227 void Assembler::vpsllw(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
6228 assert(UseAVX > 0, "requires some form of AVX");
6229 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
6230 // XMM6 is for /6 encoding: 66 0F 71 /6 ib
6231 int encode = vex_prefix_and_encode(xmm6->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6232 emit_int8(0x71);
6233 emit_int8((unsigned char)(0xC0 | encode));
6234 emit_int8(shift & 0xFF);
6235 }
6236
6237 void Assembler::vpslld(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
6238 assert(UseAVX > 0, "requires some form of AVX");
6239 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6240 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6241 // XMM6 is for /6 encoding: 66 0F 72 /6 ib
6242 int encode = vex_prefix_and_encode(xmm6->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6243 emit_int8(0x72);
6244 emit_int8((unsigned char)(0xC0 | encode));
6245 emit_int8(shift & 0xFF);
6246 }
6247
6248 void Assembler::vpsllq(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
6249 assert(UseAVX > 0, "requires some form of AVX");
6250 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6251 attributes.set_rex_vex_w_reverted();
6252 // XMM6 is for /6 encoding: 66 0F 73 /6 ib
6253 int encode = vex_prefix_and_encode(xmm6->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6254 emit_int8(0x73);
6255 emit_int8((unsigned char)(0xC0 | encode));
6256 emit_int8(shift & 0xFF);
6257 }
6258
6259 void Assembler::vpsllw(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
6260 assert(UseAVX > 0, "requires some form of AVX");
6261 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
6262 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6263 emit_int8((unsigned char)0xF1);
6264 emit_int8((unsigned char)(0xC0 | encode));
6265 }
6266
6267 void Assembler::vpslld(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
6268 assert(UseAVX > 0, "requires some form of AVX");
6269 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6270 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6271 emit_int8((unsigned char)0xF2);
6272 emit_int8((unsigned char)(0xC0 | encode));
6273 }
6274
6275 void Assembler::vpsllq(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
6276 assert(UseAVX > 0, "requires some form of AVX");
6277 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6278 attributes.set_rex_vex_w_reverted();
6279 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6280 emit_int8((unsigned char)0xF3);
6281 emit_int8((unsigned char)(0xC0 | encode));
6282 }
6283
6284 // Shift packed integers logically right by specified number of bits.
6285 void Assembler::psrlw(XMMRegister dst, int shift) {
6286 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6287 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
6288 // XMM2 is for /2 encoding: 66 0F 71 /2 ib
6289 int encode = simd_prefix_and_encode(xmm2, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6290 emit_int8(0x71);
6291 emit_int8((unsigned char)(0xC0 | encode));
6292 emit_int8(shift & 0xFF);
6293 }
6294
6295 void Assembler::psrld(XMMRegister dst, int shift) {
6296 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6297 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6298 // XMM2 is for /2 encoding: 66 0F 72 /2 ib
6299 int encode = simd_prefix_and_encode(xmm2, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6300 emit_int8(0x72);
6301 emit_int8((unsigned char)(0xC0 | encode));
6302 emit_int8(shift & 0xFF);
6303 }
6304
6305 void Assembler::psrlq(XMMRegister dst, int shift) {
6306 // Do not confuse it with psrldq SSE2 instruction which
6307 // shifts 128 bit value in xmm register by number of bytes.
6308 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6309 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6310 attributes.set_rex_vex_w_reverted();
6311 // XMM2 is for /2 encoding: 66 0F 73 /2 ib
6312 int encode = simd_prefix_and_encode(xmm2, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6313 emit_int8(0x73);
6314 emit_int8((unsigned char)(0xC0 | encode));
6315 emit_int8(shift & 0xFF);
6316 }
6317
6318 void Assembler::psrlw(XMMRegister dst, XMMRegister shift) {
6319 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6320 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
6321 int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6322 emit_int8((unsigned char)0xD1);
6323 emit_int8((unsigned char)(0xC0 | encode));
6324 }
6325
6326 void Assembler::psrld(XMMRegister dst, XMMRegister shift) {
6327 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6328 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6329 int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6330 emit_int8((unsigned char)0xD2);
6331 emit_int8((unsigned char)(0xC0 | encode));
6332 }
6333
6334 void Assembler::psrlq(XMMRegister dst, XMMRegister shift) {
6335 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6336 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6337 attributes.set_rex_vex_w_reverted();
6338 int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6339 emit_int8((unsigned char)0xD3);
6340 emit_int8((unsigned char)(0xC0 | encode));
6341 }
6342
6343 void Assembler::vpsrlw(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
6344 assert(UseAVX > 0, "requires some form of AVX");
6345 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
6346 // XMM2 is for /2 encoding: 66 0F 71 /2 ib
6347 int encode = vex_prefix_and_encode(xmm2->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6348 emit_int8(0x71);
6349 emit_int8((unsigned char)(0xC0 | encode));
6350 emit_int8(shift & 0xFF);
6351 }
6352
6353 void Assembler::vpsrld(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
6354 assert(UseAVX > 0, "requires some form of AVX");
6355 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6356 // XMM2 is for /2 encoding: 66 0F 72 /2 ib
6357 int encode = vex_prefix_and_encode(xmm2->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6358 emit_int8(0x72);
6359 emit_int8((unsigned char)(0xC0 | encode));
6360 emit_int8(shift & 0xFF);
6361 }
6362
6363 void Assembler::vpsrlq(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
6364 assert(UseAVX > 0, "requires some form of AVX");
6365 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6366 attributes.set_rex_vex_w_reverted();
6367 // XMM2 is for /2 encoding: 66 0F 73 /2 ib
6368 int encode = vex_prefix_and_encode(xmm2->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6369 emit_int8(0x73);
6370 emit_int8((unsigned char)(0xC0 | encode));
6371 emit_int8(shift & 0xFF);
6372 }
6373
6374 void Assembler::vpsrlw(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
6375 assert(UseAVX > 0, "requires some form of AVX");
6376 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
6377 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6378 emit_int8((unsigned char)0xD1);
6379 emit_int8((unsigned char)(0xC0 | encode));
6380 }
6381
6382 void Assembler::vpsrld(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
6383 assert(UseAVX > 0, "requires some form of AVX");
6384 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6385 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6386 emit_int8((unsigned char)0xD2);
6387 emit_int8((unsigned char)(0xC0 | encode));
6388 }
6389
6390 void Assembler::vpsrlq(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
6391 assert(UseAVX > 0, "requires some form of AVX");
6392 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6393 attributes.set_rex_vex_w_reverted();
6394 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6395 emit_int8((unsigned char)0xD3);
6396 emit_int8((unsigned char)(0xC0 | encode));
6397 }
6398
6399 void Assembler::evpsrlvw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
6400 assert(VM_Version::supports_avx512bw(), "");
6401 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6402 attributes.set_is_evex_instruction();
6403 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6404 emit_int8(0x10);
6405 emit_int8((unsigned char)(0xC0 | encode));
6406 }
6407
6408 void Assembler::evpsllvw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
6409 assert(VM_Version::supports_avx512bw(), "");
6410 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6411 attributes.set_is_evex_instruction();
6412 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6413 emit_int8(0x12);
6414 emit_int8((unsigned char)(0xC0 | encode));
6415 }
6416
6417 // Shift packed integers arithmetically right by specified number of bits.
6418 void Assembler::psraw(XMMRegister dst, int shift) {
6419 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6420 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
6421 // XMM4 is for /4 encoding: 66 0F 71 /4 ib
6422 int encode = simd_prefix_and_encode(xmm4, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6423 emit_int8(0x71);
6424 emit_int8((unsigned char)(0xC0 | encode));
6425 emit_int8(shift & 0xFF);
6426 }
6427
6428 void Assembler::psrad(XMMRegister dst, int shift) {
6429 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6430 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6431 // XMM4 is for /4 encoding: 66 0F 72 /4 ib
6432 int encode = simd_prefix_and_encode(xmm4, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6433 emit_int8(0x72);
6434 emit_int8((unsigned char)(0xC0 | encode));
6435 emit_int8(shift & 0xFF);
6436 }
6437
6438 void Assembler::psraw(XMMRegister dst, XMMRegister shift) {
6439 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6440 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
6441 int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6442 emit_int8((unsigned char)0xE1);
6443 emit_int8((unsigned char)(0xC0 | encode));
6444 }
6445
6446 void Assembler::psrad(XMMRegister dst, XMMRegister shift) {
6447 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6448 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6449 int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6450 emit_int8((unsigned char)0xE2);
6451 emit_int8((unsigned char)(0xC0 | encode));
6452 }
6453
6454 void Assembler::vpsraw(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
6455 assert(UseAVX > 0, "requires some form of AVX");
6456 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
6457 // XMM4 is for /4 encoding: 66 0F 71 /4 ib
6458 int encode = vex_prefix_and_encode(xmm4->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6459 emit_int8(0x71);
6460 emit_int8((unsigned char)(0xC0 | encode));
6461 emit_int8(shift & 0xFF);
6462 }
6463
6464 void Assembler::vpsrad(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
6465 assert(UseAVX > 0, "requires some form of AVX");
6466 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6467 // XMM4 is for /4 encoding: 66 0F 71 /4 ib
6468 int encode = vex_prefix_and_encode(xmm4->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6469 emit_int8(0x72);
6470 emit_int8((unsigned char)(0xC0 | encode));
6471 emit_int8(shift & 0xFF);
6472 }
6473
6474 void Assembler::vpsraw(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
6475 assert(UseAVX > 0, "requires some form of AVX");
6476 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
6477 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6478 emit_int8((unsigned char)0xE1);
6479 emit_int8((unsigned char)(0xC0 | encode));
6480 }
6481
6482 void Assembler::vpsrad(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
6483 assert(UseAVX > 0, "requires some form of AVX");
6484 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6485 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6486 emit_int8((unsigned char)0xE2);
6487 emit_int8((unsigned char)(0xC0 | encode));
6488 }
6489
6490 void Assembler::evpsraq(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
6491 assert(UseAVX > 2, "requires AVX512");
6492 assert ((VM_Version::supports_avx512vl() || vector_len == 2), "requires AVX512vl");
6493 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6494 attributes.set_is_evex_instruction();
6495 int encode = vex_prefix_and_encode(xmm4->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6496 emit_int8((unsigned char)0x72);
6497 emit_int8((unsigned char)(0xC0 | encode));
6498 emit_int8(shift & 0xFF);
6499 }
6500
6501 void Assembler::evpsraq(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
6502 assert(UseAVX > 2, "requires AVX512");
6503 assert ((VM_Version::supports_avx512vl() || vector_len == 2), "requires AVX512vl");
6504 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6505 attributes.set_is_evex_instruction();
6506 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6507 emit_int8((unsigned char)0xE2);
6508 emit_int8((unsigned char)(0xC0 | encode));
6509 }
6510
6511 // logical operations packed integers
6512 void Assembler::pand(XMMRegister dst, XMMRegister src) {
6513 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6514 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6515 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6516 emit_int8((unsigned char)0xDB);
6517 emit_int8((unsigned char)(0xC0 | encode));
6518 }
6519
6520 void Assembler::vpand(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
6521 assert(UseAVX > 0, "requires some form of AVX");
6522 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6523 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6524 emit_int8((unsigned char)0xDB);
6525 emit_int8((unsigned char)(0xC0 | encode));
6526 }
6527
6528 void Assembler::vpand(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
6529 assert(UseAVX > 0, "requires some form of AVX");
6530 InstructionMark im(this);
6531 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6532 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
6533 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6534 emit_int8((unsigned char)0xDB);
6535 emit_operand(dst, src);
6536 }
6537
6538 void Assembler::vpandq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
6539 assert(VM_Version::supports_evex(), "");
6540 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6541 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6542 emit_int8((unsigned char)0xDB);
6543 emit_int8((unsigned char)(0xC0 | encode));
6544 }
6545
6546 void Assembler::vpshldvd(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
6547 assert(VM_Version::supports_avx512_vbmi2(), "requires vbmi2");
6548 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6549 attributes.set_is_evex_instruction();
6550 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6551 emit_int8(0x71);
6552 emit_int8((unsigned char)(0xC0 | encode));
6553 }
6554
6555 void Assembler::vpshrdvd(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
6556 assert(VM_Version::supports_avx512_vbmi2(), "requires vbmi2");
6557 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6558 attributes.set_is_evex_instruction();
6559 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6560 emit_int8(0x73);
6561 emit_int8((unsigned char)(0xC0 | encode));
6562 }
6563
6564 void Assembler::pandn(XMMRegister dst, XMMRegister src) {
6565 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6566 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6567 attributes.set_rex_vex_w_reverted();
6568 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6569 emit_int8((unsigned char)0xDF);
6570 emit_int8((unsigned char)(0xC0 | encode));
6571 }
6572
6573 void Assembler::vpandn(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
6574 assert(UseAVX > 0, "requires some form of AVX");
6575 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6576 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6577 emit_int8((unsigned char)0xDF);
6578 emit_int8((unsigned char)(0xC0 | encode));
6579 }
6580
6581
6582 void Assembler::por(XMMRegister dst, XMMRegister src) {
6583 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6584 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6585 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6586 emit_int8((unsigned char)0xEB);
6587 emit_int8((unsigned char)(0xC0 | encode));
6588 }
6589
6590 void Assembler::vpor(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
6591 assert(UseAVX > 0, "requires some form of AVX");
6592 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6593 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6594 emit_int8((unsigned char)0xEB);
6595 emit_int8((unsigned char)(0xC0 | encode));
6596 }
6597
6598 void Assembler::vpor(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
6599 assert(UseAVX > 0, "requires some form of AVX");
6600 InstructionMark im(this);
6601 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6602 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
6603 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6604 emit_int8((unsigned char)0xEB);
6605 emit_operand(dst, src);
6606 }
6607
6608 void Assembler::vporq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
6609 assert(VM_Version::supports_evex(), "");
6610 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6611 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6612 emit_int8((unsigned char)0xEB);
6613 emit_int8((unsigned char)(0xC0 | encode));
6614 }
6615
6616
6617 void Assembler::pxor(XMMRegister dst, XMMRegister src) {
6618 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6619 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6620 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6621 emit_int8((unsigned char)0xEF);
6622 emit_int8((unsigned char)(0xC0 | encode));
6623 }
6624
6625 void Assembler::vpxor(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
6626 assert(UseAVX > 0, "requires some form of AVX");
6627 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6628 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6629 emit_int8((unsigned char)0xEF);
6630 emit_int8((unsigned char)(0xC0 | encode));
6631 }
6632
6633 void Assembler::vpxor(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
6634 assert(UseAVX > 0, "requires some form of AVX");
6635 InstructionMark im(this);
6636 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6637 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
6638 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6639 emit_int8((unsigned char)0xEF);
6640 emit_operand(dst, src);
6641 }
6642
6643 void Assembler::evpxorq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
6644 assert(VM_Version::supports_evex(), "requires EVEX support");
6645 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6646 attributes.set_is_evex_instruction();
6647 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6648 emit_int8((unsigned char)0xEF);
6649 emit_int8((unsigned char)(0xC0 | encode));
6650 }
6652 void Assembler::evpxorq(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
6653 assert(VM_Version::supports_evex(), "requires EVEX support");
6654 assert(dst != xnoreg, "sanity");
6655 InstructionMark im(this);
6656 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6657 attributes.set_is_evex_instruction();
6658 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
6659 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6660 emit_int8((unsigned char)0xEF);
6661 emit_operand(dst, src);
6662 }
6663
6664
6665 // vinserti forms
6666
6667 void Assembler::vinserti128(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8) {
6668 assert(VM_Version::supports_avx2(), "");
6669 assert(imm8 <= 0x01, "imm8: %u", imm8);
6670 InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6671 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6672 emit_int8(0x38);
6673 emit_int8((unsigned char)(0xC0 | encode));
6674 // 0x00 - insert into lower 128 bits
6675 // 0x01 - insert into upper 128 bits
6676 emit_int8(imm8 & 0x01);
6677 }
6678
6679 void Assembler::vinserti128(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8) {
6680 assert(VM_Version::supports_avx2(), "");
6681 assert(dst != xnoreg, "sanity");
6682 assert(imm8 <= 0x01, "imm8: %u", imm8);
6683 InstructionMark im(this);
6684 InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6685 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit);
6686 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6687 emit_int8(0x38);
6688 emit_operand(dst, src);
6689 // 0x00 - insert into lower 128 bits
6690 // 0x01 - insert into upper 128 bits
6691 emit_int8(imm8 & 0x01);
6692 }
6693
6694 void Assembler::vinserti32x4(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8) {
6695 assert(VM_Version::supports_evex(), "");
6696 assert(imm8 <= 0x03, "imm8: %u", imm8);
6697 InstructionAttr attributes(AVX_512bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6698 attributes.set_is_evex_instruction();
6699 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6700 emit_int8(0x38);
6701 emit_int8((unsigned char)(0xC0 | encode));
6702 // 0x00 - insert into q0 128 bits (0..127)
6703 // 0x01 - insert into q1 128 bits (128..255)
6704 // 0x02 - insert into q2 128 bits (256..383)
6705 // 0x03 - insert into q3 128 bits (384..511)
6706 emit_int8(imm8 & 0x03);
6707 }
6708
6709 void Assembler::vinserti32x4(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8) {
6710 assert(VM_Version::supports_avx(), "");
6711 assert(dst != xnoreg, "sanity");
6712 assert(imm8 <= 0x03, "imm8: %u", imm8);
6713 InstructionMark im(this);
6714 InstructionAttr attributes(AVX_512bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6715 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit);
6716 attributes.set_is_evex_instruction();
6717 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6718 emit_int8(0x18);
6719 emit_operand(dst, src);
6720 // 0x00 - insert into q0 128 bits (0..127)
6721 // 0x01 - insert into q1 128 bits (128..255)
6722 // 0x02 - insert into q2 128 bits (256..383)
6723 // 0x03 - insert into q3 128 bits (384..511)
6724 emit_int8(imm8 & 0x03);
6725 }
6726
6727 void Assembler::vinserti64x4(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8) {
6728 assert(VM_Version::supports_evex(), "");
6729 assert(imm8 <= 0x01, "imm8: %u", imm8);
6730 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6731 attributes.set_is_evex_instruction();
6732 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6733 emit_int8(0x3A);
6734 emit_int8((unsigned char)(0xC0 | encode));
6735 // 0x00 - insert into lower 256 bits
6736 // 0x01 - insert into upper 256 bits
6737 emit_int8(imm8 & 0x01);
6738 }
6739
6740
6741 // vinsertf forms
6742
6743 void Assembler::vinsertf128(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8) {
6744 assert(VM_Version::supports_avx(), "");
6745 assert(imm8 <= 0x01, "imm8: %u", imm8);
6746 InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6747 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6748 emit_int8(0x18);
6749 emit_int8((unsigned char)(0xC0 | encode));
6750 // 0x00 - insert into lower 128 bits
6751 // 0x01 - insert into upper 128 bits
6752 emit_int8(imm8 & 0x01);
6753 }
6754
6755 void Assembler::vinsertf128(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8) {
6756 assert(VM_Version::supports_avx(), "");
6757 assert(dst != xnoreg, "sanity");
6758 assert(imm8 <= 0x01, "imm8: %u", imm8);
6759 InstructionMark im(this);
6760 InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6761 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit);
6762 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6763 emit_int8(0x18);
6764 emit_operand(dst, src);
6765 // 0x00 - insert into lower 128 bits
6766 // 0x01 - insert into upper 128 bits
6767 emit_int8(imm8 & 0x01);
6768 }
6769
6770 void Assembler::vinsertf32x4(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8) {
6771 assert(VM_Version::supports_avx2(), "");
6772 assert(imm8 <= 0x03, "imm8: %u", imm8);
6773 InstructionAttr attributes(AVX_512bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6774 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6775 emit_int8(0x18);
6776 emit_int8((unsigned char)(0xC0 | encode));
6777 // 0x00 - insert into q0 128 bits (0..127)
6778 // 0x01 - insert into q1 128 bits (128..255)
6779 // 0x02 - insert into q0 128 bits (256..383)
6780 // 0x03 - insert into q1 128 bits (384..512)
6781 emit_int8(imm8 & 0x03);
6782 }
6783
6784 void Assembler::vinsertf32x4(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8) {
6785 assert(VM_Version::supports_avx(), "");
6786 assert(dst != xnoreg, "sanity");
6787 assert(imm8 <= 0x03, "imm8: %u", imm8);
6788 InstructionMark im(this);
6789 InstructionAttr attributes(AVX_512bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6790 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit);
6791 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6792 emit_int8(0x18);
6793 emit_operand(dst, src);
6794 // 0x00 - insert into q0 128 bits (0..127)
6795 // 0x01 - insert into q1 128 bits (128..255)
6796 // 0x02 - insert into q0 128 bits (256..383)
6797 // 0x03 - insert into q1 128 bits (384..512)
6798 emit_int8(imm8 & 0x03);
6799 }
6800
6801 void Assembler::vinsertf64x4(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8) {
6802 assert(VM_Version::supports_evex(), "");
6803 assert(imm8 <= 0x01, "imm8: %u", imm8);
6804 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6805 attributes.set_is_evex_instruction();
6806 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6807 emit_int8(0x1A);
6808 emit_int8((unsigned char)(0xC0 | encode));
6809 // 0x00 - insert into lower 256 bits
6810 // 0x01 - insert into upper 256 bits
6811 emit_int8(imm8 & 0x01);
6812 }
6813
6814 void Assembler::vinsertf64x4(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8) {
6815 assert(VM_Version::supports_evex(), "");
6816 assert(dst != xnoreg, "sanity");
6817 assert(imm8 <= 0x01, "imm8: %u", imm8);
6818 InstructionMark im(this);
6819 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6820 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_64bit);
6821 attributes.set_is_evex_instruction();
6822 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6823 emit_int8(0x1A);
6824 emit_operand(dst, src);
6825 // 0x00 - insert into lower 256 bits
6826 // 0x01 - insert into upper 256 bits
6827 emit_int8(imm8 & 0x01);
6828 }
6829
6830
6831 // vextracti forms
6832
6833 void Assembler::vextracti128(XMMRegister dst, XMMRegister src, uint8_t imm8) {
6834 assert(VM_Version::supports_avx2(), "");
6835 assert(imm8 <= 0x01, "imm8: %u", imm8);
6836 InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6837 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6838 emit_int8(0x39);
6839 emit_int8((unsigned char)(0xC0 | encode));
6840 // 0x00 - extract from lower 128 bits
6841 // 0x01 - extract from upper 128 bits
6842 emit_int8(imm8 & 0x01);
6843 }
6844
6845 void Assembler::vextracti128(Address dst, XMMRegister src, uint8_t imm8) {
6846 assert(VM_Version::supports_avx2(), "");
6847 assert(src != xnoreg, "sanity");
6848 assert(imm8 <= 0x01, "imm8: %u", imm8);
6849 InstructionMark im(this);
6850 InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6851 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit);
6852 attributes.reset_is_clear_context();
6853 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6854 emit_int8(0x39);
6855 emit_operand(src, dst);
6856 // 0x00 - extract from lower 128 bits
6857 // 0x01 - extract from upper 128 bits
6858 emit_int8(imm8 & 0x01);
6859 }
6860
6861 void Assembler::vextracti32x4(XMMRegister dst, XMMRegister src, uint8_t imm8) {
6862 assert(VM_Version::supports_evex(), "");
6863 assert(imm8 <= 0x03, "imm8: %u", imm8);
6864 InstructionAttr attributes(AVX_512bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6865 attributes.set_is_evex_instruction();
6866 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6867 emit_int8(0x39);
6868 emit_int8((unsigned char)(0xC0 | encode));
6869 // 0x00 - extract from bits 127:0
6870 // 0x01 - extract from bits 255:128
6871 // 0x02 - extract from bits 383:256
6872 // 0x03 - extract from bits 511:384
6873 emit_int8(imm8 & 0x03);
6874 }
6875
6876 void Assembler::vextracti32x4(Address dst, XMMRegister src, uint8_t imm8) {
6877 assert(VM_Version::supports_evex(), "");
6878 assert(src != xnoreg, "sanity");
6879 assert(imm8 <= 0x03, "imm8: %u", imm8);
6880 InstructionMark im(this);
6881 InstructionAttr attributes(AVX_512bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6882 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit);
6883 attributes.reset_is_clear_context();
6884 attributes.set_is_evex_instruction();
6885 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6886 emit_int8(0x39);
6887 emit_operand(src, dst);
6888 // 0x00 - extract from bits 127:0
6889 // 0x01 - extract from bits 255:128
6890 // 0x02 - extract from bits 383:256
6891 // 0x03 - extract from bits 511:384
6892 emit_int8(imm8 & 0x03);
6893 }
6894
6895 void Assembler::vextracti64x2(XMMRegister dst, XMMRegister src, uint8_t imm8) {
6896 assert(VM_Version::supports_avx512dq(), "");
6897 assert(imm8 <= 0x03, "imm8: %u", imm8);
6898 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6899 attributes.set_is_evex_instruction();
6900 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6901 emit_int8(0x39);
6902 emit_int8((unsigned char)(0xC0 | encode));
6903 // 0x00 - extract from bits 127:0
6904 // 0x01 - extract from bits 255:128
6905 // 0x02 - extract from bits 383:256
6906 // 0x03 - extract from bits 511:384
6907 emit_int8(imm8 & 0x03);
6908 }
6909
6910 void Assembler::vextracti64x4(XMMRegister dst, XMMRegister src, uint8_t imm8) {
6911 assert(VM_Version::supports_evex(), "");
6912 assert(imm8 <= 0x01, "imm8: %u", imm8);
6913 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6914 attributes.set_is_evex_instruction();
6915 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6916 emit_int8(0x3B);
6917 emit_int8((unsigned char)(0xC0 | encode));
6918 // 0x00 - extract from lower 256 bits
6919 // 0x01 - extract from upper 256 bits
6920 emit_int8(imm8 & 0x01);
6921 }
6922
6923 void Assembler::vextracti64x4(Address dst, XMMRegister src, uint8_t imm8) {
6924 assert(VM_Version::supports_evex(), "");
6925 assert(src != xnoreg, "sanity");
6926 assert(imm8 <= 0x01, "imm8: %u", imm8);
6927 InstructionMark im(this);
6928 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6929 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_64bit);
6930 attributes.reset_is_clear_context();
6931 attributes.set_is_evex_instruction();
6932 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6933 emit_int8(0x38);
6934 emit_operand(src, dst);
6935 // 0x00 - extract from lower 256 bits
6936 // 0x01 - extract from upper 256 bits
6937 emit_int8(imm8 & 0x01);
6938 }
6939 // vextractf forms
6940
6941 void Assembler::vextractf128(XMMRegister dst, XMMRegister src, uint8_t imm8) {
6942 assert(VM_Version::supports_avx(), "");
6943 assert(imm8 <= 0x01, "imm8: %u", imm8);
6944 InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6945 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6946 emit_int8(0x19);
6947 emit_int8((unsigned char)(0xC0 | encode));
6948 // 0x00 - extract from lower 128 bits
6949 // 0x01 - extract from upper 128 bits
6950 emit_int8(imm8 & 0x01);
6951 }
6952
6953 void Assembler::vextractf128(Address dst, XMMRegister src, uint8_t imm8) {
6954 assert(VM_Version::supports_avx(), "");
6955 assert(src != xnoreg, "sanity");
6956 assert(imm8 <= 0x01, "imm8: %u", imm8);
6957 InstructionMark im(this);
6958 InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6959 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit);
6960 attributes.reset_is_clear_context();
6961 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6962 emit_int8(0x19);
6963 emit_operand(src, dst);
6964 // 0x00 - extract from lower 128 bits
6965 // 0x01 - extract from upper 128 bits
6966 emit_int8(imm8 & 0x01);
6967 }
6968
6969 void Assembler::vextractf32x4(XMMRegister dst, XMMRegister src, uint8_t imm8) {
6970 assert(VM_Version::supports_evex(), "");
6971 assert(imm8 <= 0x03, "imm8: %u", imm8);
6972 InstructionAttr attributes(AVX_512bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6973 attributes.set_is_evex_instruction();
6974 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6975 emit_int8(0x19);
6976 emit_int8((unsigned char)(0xC0 | encode));
6977 // 0x00 - extract from bits 127:0
6978 // 0x01 - extract from bits 255:128
6979 // 0x02 - extract from bits 383:256
6980 // 0x03 - extract from bits 511:384
6981 emit_int8(imm8 & 0x03);
6982 }
6983
6984 void Assembler::vextractf32x4(Address dst, XMMRegister src, uint8_t imm8) {
6985 assert(VM_Version::supports_evex(), "");
6986 assert(src != xnoreg, "sanity");
6987 assert(imm8 <= 0x03, "imm8: %u", imm8);
6988 InstructionMark im(this);
6989 InstructionAttr attributes(AVX_512bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6990 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit);
6991 attributes.reset_is_clear_context();
6992 attributes.set_is_evex_instruction();
6993 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6994 emit_int8(0x19);
6995 emit_operand(src, dst);
6996 // 0x00 - extract from bits 127:0
6997 // 0x01 - extract from bits 255:128
6998 // 0x02 - extract from bits 383:256
6999 // 0x03 - extract from bits 511:384
7000 emit_int8(imm8 & 0x03);
7001 }
7002
7003 void Assembler::vextractf64x2(XMMRegister dst, XMMRegister src, uint8_t imm8) {
7004 assert(VM_Version::supports_avx512dq(), "");
7005 assert(imm8 <= 0x03, "imm8: %u", imm8);
7006 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
7007 attributes.set_is_evex_instruction();
7008 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
7009 emit_int8(0x19);
7010 emit_int8((unsigned char)(0xC0 | encode));
7011 // 0x00 - extract from bits 127:0
7012 // 0x01 - extract from bits 255:128
7013 // 0x02 - extract from bits 383:256
7014 // 0x03 - extract from bits 511:384
7015 emit_int8(imm8 & 0x03);
7016 }
7017
7018 void Assembler::vextractf64x4(XMMRegister dst, XMMRegister src, uint8_t imm8) {
7019 assert(VM_Version::supports_evex(), "");
7020 assert(imm8 <= 0x01, "imm8: %u", imm8);
7021 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
7022 attributes.set_is_evex_instruction();
7023 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
7024 emit_int8(0x1B);
7025 emit_int8((unsigned char)(0xC0 | encode));
7026 // 0x00 - extract from lower 256 bits
7027 // 0x01 - extract from upper 256 bits
7028 emit_int8(imm8 & 0x01);
7029 }
7030
7031 void Assembler::vextractf64x4(Address dst, XMMRegister src, uint8_t imm8) {
7032 assert(VM_Version::supports_evex(), "");
7033 assert(src != xnoreg, "sanity");
7034 assert(imm8 <= 0x01, "imm8: %u", imm8);
7035 InstructionMark im(this);
7036 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
7037 attributes.set_address_attributes(/* tuple_type */ EVEX_T4,/* input_size_in_bits */ EVEX_64bit);
7038 attributes.reset_is_clear_context();
7039 attributes.set_is_evex_instruction();
7040 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
7041 emit_int8(0x1B);
7042 emit_operand(src, dst);
7043 // 0x00 - extract from lower 256 bits
7044 // 0x01 - extract from upper 256 bits
7045 emit_int8(imm8 & 0x01);
7046 }
7047
7048 // duplicate 1-byte integer data from src into programmed locations in dest : requires AVX512BW and AVX512VL
7049 void Assembler::vpbroadcastb(XMMRegister dst, XMMRegister src, int vector_len) {
7050 assert(VM_Version::supports_avx2(), "");
7051 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
7052 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
7053 emit_int8(0x78);
7054 emit_int8((unsigned char)(0xC0 | encode));
7055 }
7056
7057 void Assembler::vpbroadcastb(XMMRegister dst, Address src, int vector_len) {
7058 assert(VM_Version::supports_avx2(), "");
7059 assert(dst != xnoreg, "sanity");
7060 InstructionMark im(this);
7061 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
7062 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_8bit);
7063 // swap src<->dst for encoding
7064 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
7065 emit_int8(0x78);
7066 emit_operand(dst, src);
7067 }
7068
7069 // duplicate 2-byte integer data from src into programmed locations in dest : requires AVX512BW and AVX512VL
7070 void Assembler::vpbroadcastw(XMMRegister dst, XMMRegister src, int vector_len) {
7071 assert(VM_Version::supports_avx2(), "");
7072 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
7073 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
7074 emit_int8(0x79);
7075 emit_int8((unsigned char)(0xC0 | encode));
7076 }
7077
7078 void Assembler::vpbroadcastw(XMMRegister dst, Address src, int vector_len) {
7079 assert(VM_Version::supports_avx2(), "");
7080 assert(dst != xnoreg, "sanity");
7081 InstructionMark im(this);
7082 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
7083 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_16bit);
7084 // swap src<->dst for encoding
7085 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
7086 emit_int8(0x79);
7087 emit_operand(dst, src);
7088 }
7089
7090 // xmm/mem sourced byte/word/dword/qword replicate
7091
7092 // duplicate 4-byte integer data from src into programmed locations in dest : requires AVX512VL
7093 void Assembler::vpbroadcastd(XMMRegister dst, XMMRegister src, int vector_len) {
7094 assert(UseAVX >= 2, "");
7095 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
7096 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
7097 emit_int8(0x58);
7098 emit_int8((unsigned char)(0xC0 | encode));
7099 }
7100
7101 void Assembler::vpbroadcastd(XMMRegister dst, Address src, int vector_len) {
7102 assert(VM_Version::supports_avx2(), "");
7103 assert(dst != xnoreg, "sanity");
7104 InstructionMark im(this);
7105 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
7106 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
7107 // swap src<->dst for encoding
7108 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
7109 emit_int8(0x58);
7110 emit_operand(dst, src);
7111 }
7112
7113 // duplicate 8-byte integer data from src into programmed locations in dest : requires AVX512VL
7114 void Assembler::vpbroadcastq(XMMRegister dst, XMMRegister src, int vector_len) {
7115 assert(VM_Version::supports_avx2(), "");
7116 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
7117 attributes.set_rex_vex_w_reverted();
7118 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
7119 emit_int8(0x59);
7120 emit_int8((unsigned char)(0xC0 | encode));
7121 }
7122
7123 void Assembler::vpbroadcastq(XMMRegister dst, Address src, int vector_len) {
7124 assert(VM_Version::supports_avx2(), "");
7125 assert(dst != xnoreg, "sanity");
7126 InstructionMark im(this);
7127 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
7128 attributes.set_rex_vex_w_reverted();
7129 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
7130 // swap src<->dst for encoding
7131 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
7132 emit_int8(0x59);
7133 emit_operand(dst, src);
7134 }
7135 void Assembler::evbroadcasti64x2(XMMRegister dst, XMMRegister src, int vector_len) {
7136 assert(vector_len != Assembler::AVX_128bit, "");
7137 assert(VM_Version::supports_avx512dq(), "");
7138 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
7139 attributes.set_rex_vex_w_reverted();
7140 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
7141 emit_int8(0x5A);
7142 emit_int8((unsigned char)(0xC0 | encode));
7143 }
7144
7145 void Assembler::evbroadcasti64x2(XMMRegister dst, Address src, int vector_len) {
7146 assert(vector_len != Assembler::AVX_128bit, "");
7147 assert(VM_Version::supports_avx512dq(), "");
7148 assert(dst != xnoreg, "sanity");
7149 InstructionMark im(this);
7150 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
7151 attributes.set_rex_vex_w_reverted();
7152 attributes.set_address_attributes(/* tuple_type */ EVEX_T2, /* input_size_in_bits */ EVEX_64bit);
7153 // swap src<->dst for encoding
7154 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
7155 emit_int8(0x5A);
7156 emit_operand(dst, src);
7157 }
7158
7159 // scalar single/double precision replicate
7160
7161 // duplicate single precision data from src into programmed locations in dest : requires AVX512VL
7162 void Assembler::vbroadcastss(XMMRegister dst, XMMRegister src, int vector_len) {
7163 assert(VM_Version::supports_avx2(), "");
7164 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
7165 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
7166 emit_int8(0x18);
7167 emit_int8((unsigned char)(0xC0 | encode));
7168 }
7169
7170 void Assembler::vbroadcastss(XMMRegister dst, Address src, int vector_len) {
7171 assert(VM_Version::supports_avx(), "");
7172 assert(dst != xnoreg, "sanity");
7173 InstructionMark im(this);
7174 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
7175 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
7176 // swap src<->dst for encoding
7177 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
7178 emit_int8(0x18);
7179 emit_operand(dst, src);
7180 }
7181
7182 // duplicate double precision data from src into programmed locations in dest : requires AVX512VL
7183 void Assembler::vbroadcastsd(XMMRegister dst, XMMRegister src, int vector_len) {
7184 assert(VM_Version::supports_avx2(), "");
7185 assert(vector_len == AVX_256bit || vector_len == AVX_512bit, "");
7186 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
7187 attributes.set_rex_vex_w_reverted();
7188 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
7189 emit_int8(0x19);
7190 emit_int8((unsigned char)(0xC0 | encode));
7191 }
7192
7193 void Assembler::vbroadcastsd(XMMRegister dst, Address src, int vector_len) {
7194 assert(VM_Version::supports_avx(), "");
7195 assert(vector_len == AVX_256bit || vector_len == AVX_512bit, "");
7196 assert(dst != xnoreg, "sanity");
7197 InstructionMark im(this);
7198 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
7199 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
7200 attributes.set_rex_vex_w_reverted();
7201 // swap src<->dst for encoding
7202 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
7203 emit_int8(0x19);
7204 emit_operand(dst, src);
7205 }
7206
7207
7208 // gpr source broadcast forms
7209
7210 // duplicate 1-byte integer data from src into programmed locations in dest : requires AVX512BW and AVX512VL
7211 void Assembler::evpbroadcastb(XMMRegister dst, Register src, int vector_len) {
7212 assert(VM_Version::supports_avx512bw(), "");
7213 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
7214 attributes.set_is_evex_instruction();
7215 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
7216 emit_int8(0x7A);
7217 emit_int8((unsigned char)(0xC0 | encode));
7218 }
7219
7220 // duplicate 2-byte integer data from src into programmed locations in dest : requires AVX512BW and AVX512VL
7221 void Assembler::evpbroadcastw(XMMRegister dst, Register src, int vector_len) {
7222 assert(VM_Version::supports_avx512bw(), "");
7223 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
7224 attributes.set_is_evex_instruction();
7225 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
7226 emit_int8(0x7B);
7227 emit_int8((unsigned char)(0xC0 | encode));
7228 }
7229
7230 // duplicate 4-byte integer data from src into programmed locations in dest : requires AVX512VL
7231 void Assembler::evpbroadcastd(XMMRegister dst, Register src, int vector_len) {
7232 assert(VM_Version::supports_evex(), "");
7233 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
7234 attributes.set_is_evex_instruction();
7235 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
7236 emit_int8(0x7C);
7237 emit_int8((unsigned char)(0xC0 | encode));
7238 }
7239
7240 // duplicate 8-byte integer data from src into programmed locations in dest : requires AVX512VL
7241 void Assembler::evpbroadcastq(XMMRegister dst, Register src, int vector_len) {
7242 assert(VM_Version::supports_evex(), "");
7243 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
7244 attributes.set_is_evex_instruction();
7245 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
7246 emit_int8(0x7C);
7247 emit_int8((unsigned char)(0xC0 | encode));
7248 }
7249 void Assembler::evpgatherdd(XMMRegister dst, KRegister mask, Address src, int vector_len) {
7250 assert(VM_Version::supports_evex(), "");
7251 assert(dst != xnoreg, "sanity");
7252 InstructionMark im(this);
7253 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
7254 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
7255 attributes.reset_is_clear_context();
7256 attributes.set_embedded_opmask_register_specifier(mask);
7257 attributes.set_is_evex_instruction();
7258 // swap src<->dst for encoding
7259 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
7260 emit_int8((unsigned char)0x90);
7261 emit_operand(dst, src);
7262 }
7263 // Carry-Less Multiplication Quadword
7264 void Assembler::pclmulqdq(XMMRegister dst, XMMRegister src, int mask) {
7265 assert(VM_Version::supports_clmul(), "");
7266 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ true);
7267 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
7268 emit_int8(0x44);
7269 emit_int8((unsigned char)(0xC0 | encode));
7270 emit_int8((unsigned char)mask);
7271 }
7272
7273 // Carry-Less Multiplication Quadword
7274 void Assembler::vpclmulqdq(XMMRegister dst, XMMRegister nds, XMMRegister src, int mask) {
7275 assert(VM_Version::supports_avx() && VM_Version::supports_clmul(), "");
7276 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ true);
7277 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
7278 emit_int8(0x44);
7279 emit_int8((unsigned char)(0xC0 | encode));
7280 emit_int8((unsigned char)mask);
7281 }
7282
7283 void Assembler::evpclmulqdq(XMMRegister dst, XMMRegister nds, XMMRegister src, int mask, int vector_len) {
7284 assert(VM_Version::supports_avx512_vpclmulqdq(), "Requires vector carryless multiplication support");
7285 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
7286 attributes.set_is_evex_instruction();
7287 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
7288 emit_int8(0x44);
7289 emit_int8((unsigned char)(0xC0 | encode));
7290 emit_int8((unsigned char)mask);
7291 }
7292
7293 void Assembler::vzeroupper_uncached() {
7294 if (VM_Version::supports_vzeroupper()) {
7295 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
7296 (void)vex_prefix_and_encode(0, 0, 0, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
7297 emit_int8(0x77);
7298 }
7299 }
7300
7301 #ifndef _LP64
7302 // 32bit only pieces of the assembler
7303
7304 void Assembler::vzeroupper() {
7305 vzeroupper_uncached();
7306 }
7307
7308 void Assembler::cmp_literal32(Register src1, int32_t imm32, RelocationHolder const& rspec) {
7309 // NO PREFIX AS NEVER 64BIT
7310 InstructionMark im(this);
7311 emit_int8((unsigned char)0x81);
7312 emit_int8((unsigned char)(0xF8 | src1->encoding()));
7313 emit_data(imm32, rspec, 0);
7314 }
7315
7316 void Assembler::cmp_literal32(Address src1, int32_t imm32, RelocationHolder const& rspec) {
7317 // NO PREFIX AS NEVER 64BIT (not even 32bit versions of 64bit regs
7318 InstructionMark im(this);
7319 emit_int8((unsigned char)0x81);
7320 emit_operand(rdi, src1);
7321 emit_data(imm32, rspec, 0);
7322 }
7323
7324 // The 64-bit (32bit platform) cmpxchg compares the value at adr with the contents of rdx:rax,
7325 // and stores rcx:rbx into adr if so; otherwise, the value at adr is loaded
7326 // into rdx:rax. The ZF is set if the compared values were equal, and cleared otherwise.
7327 void Assembler::cmpxchg8(Address adr) {
7328 InstructionMark im(this);
7329 emit_int8(0x0F);
7330 emit_int8((unsigned char)0xC7);
7331 emit_operand(rcx, adr);
7332 }
7333
7334 void Assembler::decl(Register dst) {
7335 // Don't use it directly. Use MacroAssembler::decrementl() instead.
7336 emit_int8(0x48 | dst->encoding());
7337 }
7338
7339 // 64bit doesn't use the x87
7340
7341 void Assembler::fabs() {
7342 emit_int8((unsigned char)0xD9);
7343 emit_int8((unsigned char)0xE1);
7344 }
7345
7346 void Assembler::fadd(int i) {
7347 emit_farith(0xD8, 0xC0, i);
7348 }
7349
7350 void Assembler::fadd_d(Address src) {
7351 InstructionMark im(this);
7352 emit_int8((unsigned char)0xDC);
7353 emit_operand32(rax, src);
7354 }
7355
7356 void Assembler::fadd_s(Address src) {
7357 InstructionMark im(this);
7358 emit_int8((unsigned char)0xD8);
7359 emit_operand32(rax, src);
7360 }
7361
7362 void Assembler::fadda(int i) {
7363 emit_farith(0xDC, 0xC0, i);
7364 }
7365
7366 void Assembler::faddp(int i) {
7367 emit_farith(0xDE, 0xC0, i);
7368 }
7369
7370 void Assembler::fchs() {
7371 emit_int8((unsigned char)0xD9);
7372 emit_int8((unsigned char)0xE0);
7373 }
7374
7375 void Assembler::fcom(int i) {
7376 emit_farith(0xD8, 0xD0, i);
7377 }
7378
7379 void Assembler::fcomp(int i) {
7380 emit_farith(0xD8, 0xD8, i);
7381 }
7382
7383 void Assembler::fcomp_d(Address src) {
7384 InstructionMark im(this);
7385 emit_int8((unsigned char)0xDC);
7386 emit_operand32(rbx, src);
7387 }
7388
7389 void Assembler::fcomp_s(Address src) {
7390 InstructionMark im(this);
7391 emit_int8((unsigned char)0xD8);
7392 emit_operand32(rbx, src);
7393 }
7394
7395 void Assembler::fcompp() {
7396 emit_int8((unsigned char)0xDE);
7397 emit_int8((unsigned char)0xD9);
7398 }
7399
7400 void Assembler::fcos() {
7401 emit_int8((unsigned char)0xD9);
7402 emit_int8((unsigned char)0xFF);
7403 }
7404
7405 void Assembler::fdecstp() {
7406 emit_int8((unsigned char)0xD9);
7407 emit_int8((unsigned char)0xF6);
7408 }
7409
7410 void Assembler::fdiv(int i) {
7411 emit_farith(0xD8, 0xF0, i);
7412 }
7413
7414 void Assembler::fdiv_d(Address src) {
7415 InstructionMark im(this);
7416 emit_int8((unsigned char)0xDC);
7417 emit_operand32(rsi, src);
7418 }
7419
7420 void Assembler::fdiv_s(Address src) {
7421 InstructionMark im(this);
7422 emit_int8((unsigned char)0xD8);
7423 emit_operand32(rsi, src);
7424 }
7425
7426 void Assembler::fdiva(int i) {
7427 emit_farith(0xDC, 0xF8, i);
7458 emit_farith(0xDE, 0xF0, i); // ST(0) <- ST(1) / ST(0) and pop (Intel manual wrong)
7459 }
7460
7461 void Assembler::ffree(int i) {
7462 emit_farith(0xDD, 0xC0, i);
7463 }
7464
7465 void Assembler::fild_d(Address adr) {
7466 InstructionMark im(this);
7467 emit_int8((unsigned char)0xDF);
7468 emit_operand32(rbp, adr);
7469 }
7470
7471 void Assembler::fild_s(Address adr) {
7472 InstructionMark im(this);
7473 emit_int8((unsigned char)0xDB);
7474 emit_operand32(rax, adr);
7475 }
7476
7477 void Assembler::fincstp() {
7478 emit_int8((unsigned char)0xD9);
7479 emit_int8((unsigned char)0xF7);
7480 }
7481
7482 void Assembler::finit() {
7483 emit_int8((unsigned char)0x9B);
7484 emit_int8((unsigned char)0xDB);
7485 emit_int8((unsigned char)0xE3);
7486 }
7487
7488 void Assembler::fist_s(Address adr) {
7489 InstructionMark im(this);
7490 emit_int8((unsigned char)0xDB);
7491 emit_operand32(rdx, adr);
7492 }
7493
7494 void Assembler::fistp_d(Address adr) {
7495 InstructionMark im(this);
7496 emit_int8((unsigned char)0xDF);
7497 emit_operand32(rdi, adr);
7498 }
7499
7500 void Assembler::fistp_s(Address adr) {
7501 InstructionMark im(this);
7502 emit_int8((unsigned char)0xDB);
7503 emit_operand32(rbx, adr);
7504 }
7505
7506 void Assembler::fld1() {
7507 emit_int8((unsigned char)0xD9);
7508 emit_int8((unsigned char)0xE8);
7509 }
7510
7511 void Assembler::fld_d(Address adr) {
7512 InstructionMark im(this);
7513 emit_int8((unsigned char)0xDD);
7514 emit_operand32(rax, adr);
7515 }
7516
7517 void Assembler::fld_s(Address adr) {
7518 InstructionMark im(this);
7519 emit_int8((unsigned char)0xD9);
7520 emit_operand32(rax, adr);
7521 }
7522
7523
7524 void Assembler::fld_s(int index) {
7525 emit_farith(0xD9, 0xC0, index);
7526 }
7527
7528 void Assembler::fld_x(Address adr) {
7529 InstructionMark im(this);
7530 emit_int8((unsigned char)0xDB);
7531 emit_operand32(rbp, adr);
7532 }
7533
7534 void Assembler::fldcw(Address src) {
7535 InstructionMark im(this);
7536 emit_int8((unsigned char)0xD9);
7537 emit_operand32(rbp, src);
7538 }
7539
7540 void Assembler::fldenv(Address src) {
7541 InstructionMark im(this);
7542 emit_int8((unsigned char)0xD9);
7543 emit_operand32(rsp, src);
7544 }
7545
7546 void Assembler::fldlg2() {
7547 emit_int8((unsigned char)0xD9);
7548 emit_int8((unsigned char)0xEC);
7549 }
7550
7551 void Assembler::fldln2() {
7552 emit_int8((unsigned char)0xD9);
7553 emit_int8((unsigned char)0xED);
7554 }
7555
7556 void Assembler::fldz() {
7557 emit_int8((unsigned char)0xD9);
7558 emit_int8((unsigned char)0xEE);
7559 }
7560
7561 void Assembler::flog() {
7562 fldln2();
7563 fxch();
7564 fyl2x();
7565 }
7566
7567 void Assembler::flog10() {
7568 fldlg2();
7569 fxch();
7570 fyl2x();
7571 }
7572
7573 void Assembler::fmul(int i) {
7574 emit_farith(0xD8, 0xC8, i);
7575 }
7576
7577 void Assembler::fmul_d(Address src) {
7578 InstructionMark im(this);
7585 emit_int8((unsigned char)0xD8);
7586 emit_operand32(rcx, src);
7587 }
7588
7589 void Assembler::fmula(int i) {
7590 emit_farith(0xDC, 0xC8, i);
7591 }
7592
7593 void Assembler::fmulp(int i) {
7594 emit_farith(0xDE, 0xC8, i);
7595 }
7596
7597 void Assembler::fnsave(Address dst) {
7598 InstructionMark im(this);
7599 emit_int8((unsigned char)0xDD);
7600 emit_operand32(rsi, dst);
7601 }
7602
7603 void Assembler::fnstcw(Address src) {
7604 InstructionMark im(this);
7605 emit_int8((unsigned char)0x9B);
7606 emit_int8((unsigned char)0xD9);
7607 emit_operand32(rdi, src);
7608 }
7609
7610 void Assembler::fnstsw_ax() {
7611 emit_int8((unsigned char)0xDF);
7612 emit_int8((unsigned char)0xE0);
7613 }
7614
7615 void Assembler::fprem() {
7616 emit_int8((unsigned char)0xD9);
7617 emit_int8((unsigned char)0xF8);
7618 }
7619
7620 void Assembler::fprem1() {
7621 emit_int8((unsigned char)0xD9);
7622 emit_int8((unsigned char)0xF5);
7623 }
7624
7625 void Assembler::frstor(Address src) {
7626 InstructionMark im(this);
7627 emit_int8((unsigned char)0xDD);
7628 emit_operand32(rsp, src);
7629 }
7630
7631 void Assembler::fsin() {
7632 emit_int8((unsigned char)0xD9);
7633 emit_int8((unsigned char)0xFE);
7634 }
7635
7636 void Assembler::fsqrt() {
7637 emit_int8((unsigned char)0xD9);
7638 emit_int8((unsigned char)0xFA);
7639 }
7640
7641 void Assembler::fst_d(Address adr) {
7642 InstructionMark im(this);
7643 emit_int8((unsigned char)0xDD);
7644 emit_operand32(rdx, adr);
7645 }
7646
7647 void Assembler::fst_s(Address adr) {
7648 InstructionMark im(this);
7649 emit_int8((unsigned char)0xD9);
7650 emit_operand32(rdx, adr);
7651 }
7652
7653 void Assembler::fstp_d(Address adr) {
7654 InstructionMark im(this);
7655 emit_int8((unsigned char)0xDD);
7656 emit_operand32(rbx, adr);
7657 }
7658
7704 InstructionMark im(this);
7705 emit_int8((unsigned char)0xDC);
7706 emit_operand32(rbp, src);
7707 }
7708
7709 void Assembler::fsubr_s(Address src) {
7710 InstructionMark im(this);
7711 emit_int8((unsigned char)0xD8);
7712 emit_operand32(rbp, src);
7713 }
7714
7715 void Assembler::fsubra(int i) {
7716 emit_farith(0xDC, 0xE0, i);
7717 }
7718
7719 void Assembler::fsubrp(int i) {
7720 emit_farith(0xDE, 0xE0, i); // ST(0) <- ST(1) - ST(0) and pop (Intel manual wrong)
7721 }
7722
7723 void Assembler::ftan() {
7724 emit_int8((unsigned char)0xD9);
7725 emit_int8((unsigned char)0xF2);
7726 emit_int8((unsigned char)0xDD);
7727 emit_int8((unsigned char)0xD8);
7728 }
7729
7730 void Assembler::ftst() {
7731 emit_int8((unsigned char)0xD9);
7732 emit_int8((unsigned char)0xE4);
7733 }
7734
7735 void Assembler::fucomi(int i) {
7736 // make sure the instruction is supported (introduced for P6, together with cmov)
7737 guarantee(VM_Version::supports_cmov(), "illegal instruction");
7738 emit_farith(0xDB, 0xE8, i);
7739 }
7740
7741 void Assembler::fucomip(int i) {
7742 // make sure the instruction is supported (introduced for P6, together with cmov)
7743 guarantee(VM_Version::supports_cmov(), "illegal instruction");
7744 emit_farith(0xDF, 0xE8, i);
7745 }
7746
7747 void Assembler::fwait() {
7748 emit_int8((unsigned char)0x9B);
7749 }
7750
7751 void Assembler::fxch(int i) {
7752 emit_farith(0xD9, 0xC8, i);
7753 }
7754
7755 void Assembler::fyl2x() {
7756 emit_int8((unsigned char)0xD9);
7757 emit_int8((unsigned char)0xF1);
7758 }
7759
7760 void Assembler::frndint() {
7761 emit_int8((unsigned char)0xD9);
7762 emit_int8((unsigned char)0xFC);
7763 }
7764
7765 void Assembler::f2xm1() {
7766 emit_int8((unsigned char)0xD9);
7767 emit_int8((unsigned char)0xF0);
7768 }
7769
7770 void Assembler::fldl2e() {
7771 emit_int8((unsigned char)0xD9);
7772 emit_int8((unsigned char)0xEA);
7773 }
7774 #endif // !_LP64
7775
7776 // SSE SIMD prefix byte values corresponding to VexSimdPrefix encoding.
7777 static int simd_pre[4] = { 0, 0x66, 0xF3, 0xF2 };
7778 // SSE opcode second byte values (first is 0x0F) corresponding to VexOpcode encoding.
7779 static int simd_opc[4] = { 0, 0, 0x38, 0x3A };
7780
7781 // Generate SSE legacy REX prefix and SIMD opcode based on VEX encoding.
7782 void Assembler::rex_prefix(Address adr, XMMRegister xreg, VexSimdPrefix pre, VexOpcode opc, bool rex_w) {
7783 if (pre > 0) {
7784 emit_int8(simd_pre[pre]);
7785 }
7786 if (rex_w) {
7787 prefixq(adr, xreg);
7788 } else {
7789 prefix(adr, xreg);
7790 }
7791 if (opc > 0) {
7792 emit_int8(0x0F);
7800 int Assembler::rex_prefix_and_encode(int dst_enc, int src_enc, VexSimdPrefix pre, VexOpcode opc, bool rex_w) {
7801 if (pre > 0) {
7802 emit_int8(simd_pre[pre]);
7803 }
7804 int encode = (rex_w) ? prefixq_and_encode(dst_enc, src_enc) : prefix_and_encode(dst_enc, src_enc);
7805 if (opc > 0) {
7806 emit_int8(0x0F);
7807 int opc2 = simd_opc[opc];
7808 if (opc2 > 0) {
7809 emit_int8(opc2);
7810 }
7811 }
7812 return encode;
7813 }
7814
7815
7816 void Assembler::vex_prefix(bool vex_r, bool vex_b, bool vex_x, int nds_enc, VexSimdPrefix pre, VexOpcode opc) {
7817 int vector_len = _attributes->get_vector_len();
7818 bool vex_w = _attributes->is_rex_vex_w();
7819 if (vex_b || vex_x || vex_w || (opc == VEX_OPCODE_0F_38) || (opc == VEX_OPCODE_0F_3A)) {
7820 prefix(VEX_3bytes);
7821
7822 int byte1 = (vex_r ? VEX_R : 0) | (vex_x ? VEX_X : 0) | (vex_b ? VEX_B : 0);
7823 byte1 = (~byte1) & 0xE0;
7824 byte1 |= opc;
7825 emit_int8(byte1);
7826
7827 int byte2 = ((~nds_enc) & 0xf) << 3;
7828 byte2 |= (vex_w ? VEX_W : 0) | ((vector_len > 0) ? 4 : 0) | pre;
7829 emit_int8(byte2);
7830 } else {
7831 prefix(VEX_2bytes);
7832
7833 int byte1 = vex_r ? VEX_R : 0;
7834 byte1 = (~byte1) & 0x80;
7835 byte1 |= ((~nds_enc) & 0xf) << 3;
7836 byte1 |= ((vector_len > 0 ) ? 4 : 0) | pre;
7837 emit_int8(byte1);
7838 }
7839 }
7840
7841 // This is a 4 byte encoding
7842 void Assembler::evex_prefix(bool vex_r, bool vex_b, bool vex_x, bool evex_r, bool evex_v, int nds_enc, VexSimdPrefix pre, VexOpcode opc){
7843 // EVEX 0x62 prefix
7844 prefix(EVEX_4bytes);
7845 bool vex_w = _attributes->is_rex_vex_w();
7846 int evex_encoding = (vex_w ? VEX_W : 0);
7847 // EVEX.b is not currently used for broadcast of single element or data rounding modes
7848 _attributes->set_evex_encoding(evex_encoding);
7849
7850 // P0: byte 2, initialized to RXBR`00mm
7851 // instead of not'd
7852 int byte2 = (vex_r ? VEX_R : 0) | (vex_x ? VEX_X : 0) | (vex_b ? VEX_B : 0) | (evex_r ? EVEX_Rb : 0);
7853 byte2 = (~byte2) & 0xF0;
7854 // confine opc opcode extensions in mm bits to lower two bits
7855 // of form {0F, 0F_38, 0F_3A}
7856 byte2 |= opc;
7857 emit_int8(byte2);
7858
7859 // P1: byte 3 as Wvvvv1pp
7860 int byte3 = ((~nds_enc) & 0xf) << 3;
7861 // p[10] is always 1
7862 byte3 |= EVEX_F;
7863 byte3 |= (vex_w & 1) << 7;
7864 // confine pre opcode extensions in pp bits to lower two bits
7865 // of form {66, F3, F2}
7866 byte3 |= pre;
7867 emit_int8(byte3);
7868
7869 // P2: byte 4 as zL'Lbv'aaa
7870 // kregs are implemented in the low 3 bits as aaa
7871 int byte4 = (_attributes->is_no_reg_mask()) ?
7872 0 :
7873 _attributes->get_embedded_opmask_register_specifier();
7874 // EVEX.v` for extending EVEX.vvvv or VIDX
7875 byte4 |= (evex_v ? 0: EVEX_V);
7876 // third EXEC.b for broadcast actions
7877 byte4 |= (_attributes->is_extended_context() ? EVEX_Rb : 0);
7878 // fourth EVEX.L'L for vector length : 0 is 128, 1 is 256, 2 is 512, currently we do not support 1024
7879 byte4 |= ((_attributes->get_vector_len())& 0x3) << 5;
7880 // last is EVEX.z for zero/merge actions
7881 if (_attributes->is_no_reg_mask() == false) {
7882 byte4 |= (_attributes->is_clear_context() ? EVEX_Z : 0);
7883 }
7884 emit_int8(byte4);
7885 }
7886
7887 void Assembler::vex_prefix(Address adr, int nds_enc, int xreg_enc, VexSimdPrefix pre, VexOpcode opc, InstructionAttr *attributes) {
7888 bool vex_r = ((xreg_enc & 8) == 8) ? 1 : 0;
7889 bool vex_b = adr.base_needs_rex();
7890 bool vex_x;
7891 if (adr.isxmmindex()) {
7892 vex_x = adr.xmmindex_needs_rex();
7893 } else {
7894 vex_x = adr.index_needs_rex();
7895 }
7896 set_attributes(attributes);
7897 attributes->set_current_assembler(this);
7898
7899 // For EVEX instruction (which is not marked as pure EVEX instruction) check and see if this instruction
7900 // is allowed in legacy mode and has resources which will fit in it.
7901 // Pure EVEX instructions will have is_evex_instruction set in their definition.
7902 if (!attributes->is_legacy_mode()) {
7903 if (UseAVX > 2 && !attributes->is_evex_instruction() && !_is_managed) {
7904 if ((attributes->get_vector_len() != AVX_512bit) && (nds_enc < 16) && (xreg_enc < 16)) {
7905 attributes->set_is_legacy_mode();
7906 }
7907 }
7908 }
7909
7910 if (UseAVX > 2) {
7911 assert(((!attributes->uses_vl()) ||
7912 (attributes->get_vector_len() == AVX_512bit) ||
7913 (!_legacy_mode_vl) ||
7914 (attributes->is_legacy_mode())),"XMM register should be 0-15");
7915 assert(((nds_enc < 16 && xreg_enc < 16) || (!attributes->is_legacy_mode())),"XMM register should be 0-15");
7916 }
7917
7918 _is_managed = false;
7919 if (UseAVX > 2 && !attributes->is_legacy_mode())
7920 {
7921 bool evex_r = (xreg_enc >= 16);
7922 bool evex_v;
7923 // EVEX.V' is set to true when VSIB is used as we may need to use higher order XMM registers (16-31)
7924 if (adr.isxmmindex()) {
7925 evex_v = ((adr._xmmindex->encoding() > 15) ? true : false);
7926 } else {
7927 evex_v = (nds_enc >= 16);
7928 }
7929 attributes->set_is_evex_instruction();
7930 evex_prefix(vex_r, vex_b, vex_x, evex_r, evex_v, nds_enc, pre, opc);
7931 } else {
7932 if (UseAVX > 2 && attributes->is_rex_vex_w_reverted()) {
7933 attributes->set_rex_vex_w(false);
7934 }
7935 vex_prefix(vex_r, vex_b, vex_x, nds_enc, pre, opc);
7936 }
7937 }
7938
7939 int Assembler::vex_prefix_and_encode(int dst_enc, int nds_enc, int src_enc, VexSimdPrefix pre, VexOpcode opc, InstructionAttr *attributes) {
7940 bool vex_r = ((dst_enc & 8) == 8) ? 1 : 0;
7941 bool vex_b = ((src_enc & 8) == 8) ? 1 : 0;
7942 bool vex_x = false;
7943 set_attributes(attributes);
7944 attributes->set_current_assembler(this);
7945
7946 // For EVEX instruction (which is not marked as pure EVEX instruction) check and see if this instruction
7947 // is allowed in legacy mode and has resources which will fit in it.
7948 // Pure EVEX instructions will have is_evex_instruction set in their definition.
7949 if (!attributes->is_legacy_mode()) {
7950 if (UseAVX > 2 && !attributes->is_evex_instruction() && !_is_managed) {
7951 if ((!attributes->uses_vl() || (attributes->get_vector_len() != AVX_512bit)) &&
7952 (dst_enc < 16) && (nds_enc < 16) && (src_enc < 16)) {
7953 attributes->set_is_legacy_mode();
7954 }
7955 }
7956 }
7957
7958 if (UseAVX > 2) {
7959 // All the scalar fp instructions (with uses_vl as false) can have legacy_mode as false
7960 // Instruction with uses_vl true are vector instructions
7961 // All the vector instructions with AVX_512bit length can have legacy_mode as false
7962 // All the vector instructions with < AVX_512bit length can have legacy_mode as false if AVX512vl() is supported
7963 // Rest all should have legacy_mode set as true
7964 assert(((!attributes->uses_vl()) ||
7965 (attributes->get_vector_len() == AVX_512bit) ||
7966 (!_legacy_mode_vl) ||
7967 (attributes->is_legacy_mode())),"XMM register should be 0-15");
7968 // Instruction with legacy_mode true should have dst, nds and src < 15
7969 assert(((dst_enc < 16 && nds_enc < 16 && src_enc < 16) || (!attributes->is_legacy_mode())),"XMM register should be 0-15");
7970 }
7971
7972 _is_managed = false;
7973 if (UseAVX > 2 && !attributes->is_legacy_mode())
7974 {
7975 bool evex_r = (dst_enc >= 16);
7976 bool evex_v = (nds_enc >= 16);
7977 // can use vex_x as bank extender on rm encoding
7978 vex_x = (src_enc >= 16);
7979 attributes->set_is_evex_instruction();
7980 evex_prefix(vex_r, vex_b, vex_x, evex_r, evex_v, nds_enc, pre, opc);
7981 } else {
7982 if (UseAVX > 2 && attributes->is_rex_vex_w_reverted()) {
7983 attributes->set_rex_vex_w(false);
7984 }
7985 vex_prefix(vex_r, vex_b, vex_x, nds_enc, pre, opc);
7986 }
7987
7988 // return modrm byte components for operands
7989 return (((dst_enc & 7) << 3) | (src_enc & 7));
7990 }
7991
7992
8002 }
8003 }
8004
8005 int Assembler::simd_prefix_and_encode(XMMRegister dst, XMMRegister nds, XMMRegister src, VexSimdPrefix pre,
8006 VexOpcode opc, InstructionAttr *attributes) {
8007 int dst_enc = dst->encoding();
8008 int src_enc = src->encoding();
8009 if (UseAVX > 0) {
8010 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
8011 return vex_prefix_and_encode(dst_enc, nds_enc, src_enc, pre, opc, attributes);
8012 } else {
8013 assert((nds == dst) || (nds == src) || (nds == xnoreg), "wrong sse encoding");
8014 return rex_prefix_and_encode(dst_enc, src_enc, pre, opc, attributes->is_rex_vex_w());
8015 }
8016 }
8017
8018 void Assembler::vmaxss(XMMRegister dst, XMMRegister nds, XMMRegister src) {
8019 assert(VM_Version::supports_avx(), "");
8020 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
8021 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
8022 emit_int8(0x5F);
8023 emit_int8((unsigned char)(0xC0 | encode));
8024 }
8025
8026 void Assembler::vmaxsd(XMMRegister dst, XMMRegister nds, XMMRegister src) {
8027 assert(VM_Version::supports_avx(), "");
8028 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
8029 attributes.set_rex_vex_w_reverted();
8030 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
8031 emit_int8(0x5F);
8032 emit_int8((unsigned char)(0xC0 | encode));
8033 }
8034
8035 void Assembler::vminss(XMMRegister dst, XMMRegister nds, XMMRegister src) {
8036 assert(VM_Version::supports_avx(), "");
8037 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
8038 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
8039 emit_int8(0x5D);
8040 emit_int8((unsigned char)(0xC0 | encode));
8041 }
8042
8043 void Assembler::vminsd(XMMRegister dst, XMMRegister nds, XMMRegister src) {
8044 assert(VM_Version::supports_avx(), "");
8045 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
8046 attributes.set_rex_vex_w_reverted();
8047 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
8048 emit_int8(0x5D);
8049 emit_int8((unsigned char)(0xC0 | encode));
8050 }
8051
8052 void Assembler::cmppd(XMMRegister dst, XMMRegister nds, XMMRegister src, int cop, int vector_len) {
8053 assert(VM_Version::supports_avx(), "");
8054 assert(vector_len <= AVX_256bit, "");
8055 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ true);
8056 int encode = simd_prefix_and_encode(dst, nds, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
8057 emit_int8((unsigned char)0xC2);
8058 emit_int8((unsigned char)(0xC0 | encode));
8059 emit_int8((unsigned char)(0xF & cop));
8060 }
8061
8062 void Assembler::blendvpd(XMMRegister dst, XMMRegister nds, XMMRegister src1, XMMRegister src2, int vector_len) {
8063 assert(VM_Version::supports_avx(), "");
8064 assert(vector_len <= AVX_256bit, "");
8065 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ true);
8066 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src1->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
8067 emit_int8((unsigned char)0x4B);
8068 emit_int8((unsigned char)(0xC0 | encode));
8069 int src2_enc = src2->encoding();
8070 emit_int8((unsigned char)(0xF0 & src2_enc<<4));
8071 }
8072
8073 void Assembler::cmpps(XMMRegister dst, XMMRegister nds, XMMRegister src, int cop, int vector_len) {
8074 assert(VM_Version::supports_avx(), "");
8075 assert(vector_len <= AVX_256bit, "");
8076 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ true);
8077 int encode = simd_prefix_and_encode(dst, nds, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
8078 emit_int8((unsigned char)0xC2);
8079 emit_int8((unsigned char)(0xC0 | encode));
8080 emit_int8((unsigned char)(0xF & cop));
8081 }
8082
8083 void Assembler::blendvps(XMMRegister dst, XMMRegister nds, XMMRegister src1, XMMRegister src2, int vector_len) {
8084 assert(VM_Version::supports_avx(), "");
8085 assert(vector_len <= AVX_256bit, "");
8086 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ true);
8087 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src1->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
8088 emit_int8((unsigned char)0x4A);
8089 emit_int8((unsigned char)(0xC0 | encode));
8090 int src2_enc = src2->encoding();
8091 emit_int8((unsigned char)(0xF0 & src2_enc<<4));
8092 }
8093
8094 void Assembler::vpblendd(XMMRegister dst, XMMRegister nds, XMMRegister src, int imm8, int vector_len) {
8095 assert(VM_Version::supports_avx2(), "");
8096 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ true);
8097 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
8098 emit_int8((unsigned char)0x02);
8099 emit_int8((unsigned char)(0xC0 | encode));
8100 emit_int8((unsigned char)imm8);
8101 }
8102
8103 void Assembler::shlxl(Register dst, Register src1, Register src2) {
8104 assert(VM_Version::supports_bmi2(), "");
8105 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ true);
8106 int encode = vex_prefix_and_encode(dst->encoding(), src2->encoding(), src1->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
8107 emit_int8((unsigned char)0xF7);
8108 emit_int8((unsigned char)(0xC0 | encode));
8109 }
8110
8111 void Assembler::shlxq(Register dst, Register src1, Register src2) {
8112 assert(VM_Version::supports_bmi2(), "");
8113 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ true);
8114 int encode = vex_prefix_and_encode(dst->encoding(), src2->encoding(), src1->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
8115 emit_int8((unsigned char)0xF7);
8116 emit_int8((unsigned char)(0xC0 | encode));
8117 }
8118
8119 #ifndef _LP64
8120
8121 void Assembler::incl(Register dst) {
8122 // Don't use it directly. Use MacroAssembler::incrementl() instead.
8123 emit_int8(0x40 | dst->encoding());
8124 }
8125
8126 void Assembler::lea(Register dst, Address src) {
8127 leal(dst, src);
8128 }
8129
8130 void Assembler::mov_literal32(Address dst, int32_t imm32, RelocationHolder const& rspec) {
8131 InstructionMark im(this);
8132 emit_int8((unsigned char)0xC7);
8133 emit_operand(rax, dst);
8134 emit_data((int)imm32, rspec, 0);
8135 }
8136
8139 int encode = prefix_and_encode(dst->encoding());
8140 emit_int8((unsigned char)(0xB8 | encode));
8141 emit_data((int)imm32, rspec, 0);
8142 }
8143
8144 void Assembler::popa() { // 32bit
8145 emit_int8(0x61);
8146 }
8147
8148 void Assembler::push_literal32(int32_t imm32, RelocationHolder const& rspec) {
8149 InstructionMark im(this);
8150 emit_int8(0x68);
8151 emit_data(imm32, rspec, 0);
8152 }
8153
8154 void Assembler::pusha() { // 32bit
8155 emit_int8(0x60);
8156 }
8157
8158 void Assembler::set_byte_if_not_zero(Register dst) {
8159 emit_int8(0x0F);
8160 emit_int8((unsigned char)0x95);
8161 emit_int8((unsigned char)(0xE0 | dst->encoding()));
8162 }
8163
8164 #else // LP64
8165
8166 void Assembler::set_byte_if_not_zero(Register dst) {
8167 int enc = prefix_and_encode(dst->encoding(), true);
8168 emit_int8(0x0F);
8169 emit_int8((unsigned char)0x95);
8170 emit_int8((unsigned char)(0xE0 | enc));
8171 }
8172
8173 // 64bit only pieces of the assembler
8174 // This should only be used by 64bit instructions that can use rip-relative
8175 // it cannot be used by instructions that want an immediate value.
8176
8177 bool Assembler::reachable(AddressLiteral adr) {
8178 int64_t disp;
8179 relocInfo::relocType relocType = adr.reloc();
8180
8181 // None will force a 64bit literal to the code stream. Likely a placeholder
8182 // for something that will be patched later and we need to certain it will
8183 // always be reachable.
8184 if (relocType == relocInfo::none) {
8185 return false;
8186 }
8187 if (relocType == relocInfo::internal_word_type) {
8188 // This should be rip relative and easily reachable.
8189 return true;
8190 }
8300 if (dst_enc < 8) {
8301 if (src_enc >= 8) {
8302 prefix(REX_B);
8303 src_enc -= 8;
8304 } else if ((src_is_byte && src_enc >= 4) || (dst_is_byte && dst_enc >= 4)) {
8305 prefix(REX);
8306 }
8307 } else {
8308 if (src_enc < 8) {
8309 prefix(REX_R);
8310 } else {
8311 prefix(REX_RB);
8312 src_enc -= 8;
8313 }
8314 dst_enc -= 8;
8315 }
8316 return dst_enc << 3 | src_enc;
8317 }
8318
8319 int Assembler::prefixq_and_encode(int dst_enc, int src_enc) {
8320 if (dst_enc < 8) {
8321 if (src_enc < 8) {
8322 prefix(REX_W);
8323 } else {
8324 prefix(REX_WB);
8325 src_enc -= 8;
8326 }
8327 } else {
8328 if (src_enc < 8) {
8329 prefix(REX_WR);
8330 } else {
8331 prefix(REX_WRB);
8332 src_enc -= 8;
8333 }
8334 dst_enc -= 8;
8335 }
8336 return dst_enc << 3 | src_enc;
8337 }
8338
8339 void Assembler::prefix(Register reg) {
8340 if (reg->encoding() >= 8) {
8341 prefix(REX_B);
8342 }
8343 }
8344
8345 void Assembler::prefix(Register dst, Register src, Prefix p) {
8346 if (src->encoding() >= 8) {
8347 p = (Prefix)(p | REX_B);
8348 }
8349 if (dst->encoding() >= 8) {
8350 p = (Prefix)( p | REX_R);
8351 }
8352 if (p != Prefix_EMPTY) {
8353 // do not generate an empty prefix
8354 prefix(p);
8355 }
8373 if (p != Prefix_EMPTY) {
8374 // do not generate an empty prefix
8375 prefix(p);
8376 }
8377 }
8378
8379 void Assembler::prefix(Address adr) {
8380 if (adr.base_needs_rex()) {
8381 if (adr.index_needs_rex()) {
8382 prefix(REX_XB);
8383 } else {
8384 prefix(REX_B);
8385 }
8386 } else {
8387 if (adr.index_needs_rex()) {
8388 prefix(REX_X);
8389 }
8390 }
8391 }
8392
8393 void Assembler::prefixq(Address adr) {
8394 if (adr.base_needs_rex()) {
8395 if (adr.index_needs_rex()) {
8396 prefix(REX_WXB);
8397 } else {
8398 prefix(REX_WB);
8399 }
8400 } else {
8401 if (adr.index_needs_rex()) {
8402 prefix(REX_WX);
8403 } else {
8404 prefix(REX_W);
8405 }
8406 }
8407 }
8408
8409
8410 void Assembler::prefix(Address adr, Register reg, bool byteinst) {
8411 if (reg->encoding() < 8) {
8412 if (adr.base_needs_rex()) {
8413 if (adr.index_needs_rex()) {
8414 prefix(REX_XB);
8415 } else {
8416 prefix(REX_B);
8417 }
8418 } else {
8419 if (adr.index_needs_rex()) {
8420 prefix(REX_X);
8421 } else if (byteinst && reg->encoding() >= 4 ) {
8422 prefix(REX);
8423 }
8424 }
8425 } else {
8426 if (adr.base_needs_rex()) {
8427 if (adr.index_needs_rex()) {
8428 prefix(REX_RXB);
8429 } else {
8430 prefix(REX_RB);
8431 }
8432 } else {
8433 if (adr.index_needs_rex()) {
8434 prefix(REX_RX);
8435 } else {
8436 prefix(REX_R);
8437 }
8438 }
8439 }
8440 }
8441
8442 void Assembler::prefixq(Address adr, Register src) {
8443 if (src->encoding() < 8) {
8444 if (adr.base_needs_rex()) {
8445 if (adr.index_needs_rex()) {
8446 prefix(REX_WXB);
8447 } else {
8448 prefix(REX_WB);
8449 }
8450 } else {
8451 if (adr.index_needs_rex()) {
8452 prefix(REX_WX);
8453 } else {
8454 prefix(REX_W);
8455 }
8456 }
8457 } else {
8458 if (adr.base_needs_rex()) {
8459 if (adr.index_needs_rex()) {
8460 prefix(REX_WRXB);
8461 } else {
8462 prefix(REX_WRB);
8463 }
8464 } else {
8465 if (adr.index_needs_rex()) {
8466 prefix(REX_WRX);
8467 } else {
8468 prefix(REX_WR);
8469 }
8470 }
8471 }
8472 }
8473
8474 void Assembler::prefix(Address adr, XMMRegister reg) {
8475 if (reg->encoding() < 8) {
8476 if (adr.base_needs_rex()) {
8477 if (adr.index_needs_rex()) {
8478 prefix(REX_XB);
8479 } else {
8480 prefix(REX_B);
8481 }
8482 } else {
8483 if (adr.index_needs_rex()) {
8484 prefix(REX_X);
8485 }
8486 }
8487 } else {
8488 if (adr.base_needs_rex()) {
8489 if (adr.index_needs_rex()) {
8490 prefix(REX_RXB);
8491 } else {
8523 } else {
8524 prefix(REX_WRB);
8525 }
8526 } else {
8527 if (adr.index_needs_rex()) {
8528 prefix(REX_WRX);
8529 } else {
8530 prefix(REX_WR);
8531 }
8532 }
8533 }
8534 }
8535
8536 void Assembler::adcq(Register dst, int32_t imm32) {
8537 (void) prefixq_and_encode(dst->encoding());
8538 emit_arith(0x81, 0xD0, dst, imm32);
8539 }
8540
8541 void Assembler::adcq(Register dst, Address src) {
8542 InstructionMark im(this);
8543 prefixq(src, dst);
8544 emit_int8(0x13);
8545 emit_operand(dst, src);
8546 }
8547
8548 void Assembler::adcq(Register dst, Register src) {
8549 (void) prefixq_and_encode(dst->encoding(), src->encoding());
8550 emit_arith(0x13, 0xC0, dst, src);
8551 }
8552
8553 void Assembler::addq(Address dst, int32_t imm32) {
8554 InstructionMark im(this);
8555 prefixq(dst);
8556 emit_arith_operand(0x81, rax, dst,imm32);
8557 }
8558
8559 void Assembler::addq(Address dst, Register src) {
8560 InstructionMark im(this);
8561 prefixq(dst, src);
8562 emit_int8(0x01);
8563 emit_operand(src, dst);
8564 }
8565
8566 void Assembler::addq(Register dst, int32_t imm32) {
8567 (void) prefixq_and_encode(dst->encoding());
8568 emit_arith(0x81, 0xC0, dst, imm32);
8569 }
8570
8571 void Assembler::addq(Register dst, Address src) {
8572 InstructionMark im(this);
8573 prefixq(src, dst);
8574 emit_int8(0x03);
8575 emit_operand(dst, src);
8576 }
8577
8578 void Assembler::addq(Register dst, Register src) {
8579 (void) prefixq_and_encode(dst->encoding(), src->encoding());
8580 emit_arith(0x03, 0xC0, dst, src);
8581 }
8582
8583 void Assembler::adcxq(Register dst, Register src) {
8584 //assert(VM_Version::supports_adx(), "adx instructions not supported");
8585 emit_int8((unsigned char)0x66);
8586 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
8587 emit_int8(0x0F);
8588 emit_int8(0x38);
8589 emit_int8((unsigned char)0xF6);
8590 emit_int8((unsigned char)(0xC0 | encode));
8591 }
8592
8593 void Assembler::adoxq(Register dst, Register src) {
8594 //assert(VM_Version::supports_adx(), "adx instructions not supported");
8595 emit_int8((unsigned char)0xF3);
8596 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
8597 emit_int8(0x0F);
8598 emit_int8(0x38);
8599 emit_int8((unsigned char)0xF6);
8600 emit_int8((unsigned char)(0xC0 | encode));
8601 }
8602
8603 void Assembler::andq(Address dst, int32_t imm32) {
8604 InstructionMark im(this);
8605 prefixq(dst);
8606 emit_int8((unsigned char)0x81);
8607 emit_operand(rsp, dst, 4);
8608 emit_int32(imm32);
8609 }
8610
8611 void Assembler::andq(Register dst, int32_t imm32) {
8612 (void) prefixq_and_encode(dst->encoding());
8613 emit_arith(0x81, 0xE0, dst, imm32);
8614 }
8615
8616 void Assembler::andq(Register dst, Address src) {
8617 InstructionMark im(this);
8618 prefixq(src, dst);
8619 emit_int8(0x23);
8620 emit_operand(dst, src);
8621 }
8622
8623 void Assembler::andq(Register dst, Register src) {
8624 (void) prefixq_and_encode(dst->encoding(), src->encoding());
8625 emit_arith(0x23, 0xC0, dst, src);
8626 }
8627
8628 void Assembler::andnq(Register dst, Register src1, Register src2) {
8629 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
8630 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
8631 int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
8632 emit_int8((unsigned char)0xF2);
8633 emit_int8((unsigned char)(0xC0 | encode));
8634 }
8635
8636 void Assembler::andnq(Register dst, Register src1, Address src2) {
8637 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
8638 InstructionMark im(this);
8639 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
8640 vex_prefix(src2, src1->encoding(), dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
8641 emit_int8((unsigned char)0xF2);
8642 emit_operand(dst, src2);
8643 }
8644
8645 void Assembler::bsfq(Register dst, Register src) {
8646 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
8647 emit_int8(0x0F);
8648 emit_int8((unsigned char)0xBC);
8649 emit_int8((unsigned char)(0xC0 | encode));
8650 }
8651
8652 void Assembler::bsrq(Register dst, Register src) {
8653 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
8654 emit_int8(0x0F);
8655 emit_int8((unsigned char)0xBD);
8656 emit_int8((unsigned char)(0xC0 | encode));
8657 }
8658
8659 void Assembler::bswapq(Register reg) {
8660 int encode = prefixq_and_encode(reg->encoding());
8661 emit_int8(0x0F);
8662 emit_int8((unsigned char)(0xC8 | encode));
8663 }
8664
8665 void Assembler::blsiq(Register dst, Register src) {
8666 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
8667 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
8668 int encode = vex_prefix_and_encode(rbx->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
8669 emit_int8((unsigned char)0xF3);
8670 emit_int8((unsigned char)(0xC0 | encode));
8671 }
8672
8673 void Assembler::blsiq(Register dst, Address src) {
8674 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
8675 InstructionMark im(this);
8676 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
8677 vex_prefix(src, dst->encoding(), rbx->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
8678 emit_int8((unsigned char)0xF3);
8679 emit_operand(rbx, src);
8680 }
8681
8682 void Assembler::blsmskq(Register dst, Register src) {
8683 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
8684 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
8685 int encode = vex_prefix_and_encode(rdx->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
8686 emit_int8((unsigned char)0xF3);
8687 emit_int8((unsigned char)(0xC0 | encode));
8688 }
8689
8690 void Assembler::blsmskq(Register dst, Address src) {
8691 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
8692 InstructionMark im(this);
8693 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
8694 vex_prefix(src, dst->encoding(), rdx->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
8695 emit_int8((unsigned char)0xF3);
8696 emit_operand(rdx, src);
8697 }
8698
8699 void Assembler::blsrq(Register dst, Register src) {
8700 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
8701 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
8702 int encode = vex_prefix_and_encode(rcx->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
8703 emit_int8((unsigned char)0xF3);
8704 emit_int8((unsigned char)(0xC0 | encode));
8705 }
8706
8707 void Assembler::blsrq(Register dst, Address src) {
8708 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
8709 InstructionMark im(this);
8710 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
8711 vex_prefix(src, dst->encoding(), rcx->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
8712 emit_int8((unsigned char)0xF3);
8713 emit_operand(rcx, src);
8714 }
8715
8716 void Assembler::cdqq() {
8717 prefix(REX_W);
8718 emit_int8((unsigned char)0x99);
8719 }
8720
8721 void Assembler::clflush(Address adr) {
8722 assert(VM_Version::supports_clflush(), "should do");
8723 prefix(adr);
8724 emit_int8(0x0F);
8725 emit_int8((unsigned char)0xAE);
8726 emit_operand(rdi, adr);
8727 }
8728
8729 void Assembler::clflushopt(Address adr) {
8730 assert(VM_Version::supports_clflushopt(), "should do!");
8731 // adr should be base reg only with no index or offset
8732 assert(adr.index() == noreg, "index should be noreg");
8733 assert(adr.scale() == Address::no_scale, "scale should be no_scale");
8734 assert(adr.disp() == 0, "displacement should be 0");
8735 // instruction prefix is 0x66
8736 emit_int8(0x66);
8737 prefix(adr);
8738 // opcode family is 0x0f 0xAE
8739 emit_int8(0x0F);
8740 emit_int8((unsigned char)0xAE);
8741 // extended opcode byte is 7 == rdi
8742 emit_operand(rdi, adr);
8743 }
8744
8745 void Assembler::clwb(Address adr) {
8746 assert(VM_Version::supports_clwb(), "should do!");
8747 // adr should be base reg only with no index or offset
8748 assert(adr.index() == noreg, "index should be noreg");
8749 assert(adr.scale() == Address::no_scale, "scale should be no_scale");
8750 assert(adr.disp() == 0, "displacement should be 0");
8751 // instruction prefix is 0x66
8752 emit_int8(0x66);
8753 prefix(adr);
8754 // opcode family is 0x0f 0xAE
8755 emit_int8(0x0F);
8756 emit_int8((unsigned char)0xAE);
8757 // extended opcode byte is 6 == rsi
8758 emit_operand(rsi, adr);
8759 }
8760
8761 void Assembler::cmovq(Condition cc, Register dst, Register src) {
8762 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
8763 emit_int8(0x0F);
8764 emit_int8(0x40 | cc);
8765 emit_int8((unsigned char)(0xC0 | encode));
8766 }
8767
8768 void Assembler::cmovq(Condition cc, Register dst, Address src) {
8769 InstructionMark im(this);
8770 prefixq(src, dst);
8771 emit_int8(0x0F);
8772 emit_int8(0x40 | cc);
8773 emit_operand(dst, src);
8774 }
8775
8776 void Assembler::cmpq(Address dst, int32_t imm32) {
8777 InstructionMark im(this);
8778 prefixq(dst);
8779 emit_int8((unsigned char)0x81);
8780 emit_operand(rdi, dst, 4);
8781 emit_int32(imm32);
8782 }
8783
8784 void Assembler::cmpq(Register dst, int32_t imm32) {
8785 (void) prefixq_and_encode(dst->encoding());
8786 emit_arith(0x81, 0xF8, dst, imm32);
8787 }
8788
8789 void Assembler::cmpq(Address dst, Register src) {
8790 InstructionMark im(this);
8791 prefixq(dst, src);
8792 emit_int8(0x3B);
8793 emit_operand(src, dst);
8794 }
8795
8796 void Assembler::cmpq(Register dst, Register src) {
8797 (void) prefixq_and_encode(dst->encoding(), src->encoding());
8798 emit_arith(0x3B, 0xC0, dst, src);
8799 }
8800
8801 void Assembler::cmpq(Register dst, Address src) {
8802 InstructionMark im(this);
8803 prefixq(src, dst);
8804 emit_int8(0x3B);
8805 emit_operand(dst, src);
8806 }
8807
8808 void Assembler::cmpxchgq(Register reg, Address adr) {
8809 InstructionMark im(this);
8810 prefixq(adr, reg);
8811 emit_int8(0x0F);
8812 emit_int8((unsigned char)0xB1);
8813 emit_operand(reg, adr);
8814 }
8815
8816 void Assembler::cvtsi2sdq(XMMRegister dst, Register src) {
8817 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
8818 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
8819 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
8820 emit_int8(0x2A);
8821 emit_int8((unsigned char)(0xC0 | encode));
8822 }
8823
8824 void Assembler::cvtsi2sdq(XMMRegister dst, Address src) {
8825 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
8826 InstructionMark im(this);
8827 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
8828 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
8829 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
8830 emit_int8(0x2A);
8831 emit_operand(dst, src);
8832 }
8833
8834 void Assembler::cvtsi2ssq(XMMRegister dst, Address src) {
8835 NOT_LP64(assert(VM_Version::supports_sse(), ""));
8836 InstructionMark im(this);
8837 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
8838 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
8839 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
8840 emit_int8(0x2A);
8841 emit_operand(dst, src);
8842 }
8843
8844 void Assembler::cvttsd2siq(Register dst, Address src) {
8845 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
8846 // F2 REX.W 0F 2C /r
8847 // CVTTSD2SI r64, xmm1/m64
8848 InstructionMark im(this);
8849 emit_int8((unsigned char)0xF2);
8850 prefix(REX_W);
8851 emit_int8(0x0F);
8852 emit_int8(0x2C);
8853 emit_operand(dst, src);
8854 }
8855
8856 void Assembler::cvttsd2siq(Register dst, XMMRegister src) {
8857 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
8858 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
8859 int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
8860 emit_int8(0x2C);
8861 emit_int8((unsigned char)(0xC0 | encode));
8862 }
8863
8864 void Assembler::cvttss2siq(Register dst, XMMRegister src) {
8865 NOT_LP64(assert(VM_Version::supports_sse(), ""));
8866 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
8867 int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
8868 emit_int8(0x2C);
8869 emit_int8((unsigned char)(0xC0 | encode));
8870 }
8871
8872 void Assembler::decl(Register dst) {
8873 // Don't use it directly. Use MacroAssembler::decrementl() instead.
8874 // Use two-byte form (one-byte form is a REX prefix in 64-bit mode)
8875 int encode = prefix_and_encode(dst->encoding());
8876 emit_int8((unsigned char)0xFF);
8877 emit_int8((unsigned char)(0xC8 | encode));
8878 }
8879
8880 void Assembler::decq(Register dst) {
8881 // Don't use it directly. Use MacroAssembler::decrementq() instead.
8882 // Use two-byte form (one-byte from is a REX prefix in 64-bit mode)
8883 int encode = prefixq_and_encode(dst->encoding());
8884 emit_int8((unsigned char)0xFF);
8885 emit_int8(0xC8 | encode);
8886 }
8887
8888 void Assembler::decq(Address dst) {
8889 // Don't use it directly. Use MacroAssembler::decrementq() instead.
8890 InstructionMark im(this);
8891 prefixq(dst);
8892 emit_int8((unsigned char)0xFF);
8893 emit_operand(rcx, dst);
8894 }
8895
8896 void Assembler::fxrstor(Address src) {
8897 prefixq(src);
8898 emit_int8(0x0F);
8899 emit_int8((unsigned char)0xAE);
8900 emit_operand(as_Register(1), src);
8901 }
8902
8903 void Assembler::xrstor(Address src) {
8904 prefixq(src);
8905 emit_int8(0x0F);
8906 emit_int8((unsigned char)0xAE);
8907 emit_operand(as_Register(5), src);
8908 }
8909
8910 void Assembler::fxsave(Address dst) {
8911 prefixq(dst);
8912 emit_int8(0x0F);
8913 emit_int8((unsigned char)0xAE);
8914 emit_operand(as_Register(0), dst);
8915 }
8916
8917 void Assembler::xsave(Address dst) {
8918 prefixq(dst);
8919 emit_int8(0x0F);
8920 emit_int8((unsigned char)0xAE);
8921 emit_operand(as_Register(4), dst);
8922 }
8923
8924 void Assembler::idivq(Register src) {
8925 int encode = prefixq_and_encode(src->encoding());
8926 emit_int8((unsigned char)0xF7);
8927 emit_int8((unsigned char)(0xF8 | encode));
8928 }
8929
8930 void Assembler::imulq(Register dst, Register src) {
8931 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
8932 emit_int8(0x0F);
8933 emit_int8((unsigned char)0xAF);
8934 emit_int8((unsigned char)(0xC0 | encode));
8935 }
8936
8937 void Assembler::imulq(Register dst, Register src, int value) {
8938 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
8939 if (is8bit(value)) {
8940 emit_int8(0x6B);
8941 emit_int8((unsigned char)(0xC0 | encode));
8942 emit_int8(value & 0xFF);
8943 } else {
8944 emit_int8(0x69);
8945 emit_int8((unsigned char)(0xC0 | encode));
8946 emit_int32(value);
8947 }
8948 }
8949
8950 void Assembler::imulq(Register dst, Address src) {
8951 InstructionMark im(this);
8952 prefixq(src, dst);
8953 emit_int8(0x0F);
8954 emit_int8((unsigned char) 0xAF);
8955 emit_operand(dst, src);
8956 }
8957
8958 void Assembler::incl(Register dst) {
8959 // Don't use it directly. Use MacroAssembler::incrementl() instead.
8960 // Use two-byte form (one-byte from is a REX prefix in 64-bit mode)
8961 int encode = prefix_and_encode(dst->encoding());
8962 emit_int8((unsigned char)0xFF);
8963 emit_int8((unsigned char)(0xC0 | encode));
8964 }
8965
8966 void Assembler::incq(Register dst) {
8967 // Don't use it directly. Use MacroAssembler::incrementq() instead.
8968 // Use two-byte form (one-byte from is a REX prefix in 64-bit mode)
8969 int encode = prefixq_and_encode(dst->encoding());
8970 emit_int8((unsigned char)0xFF);
8971 emit_int8((unsigned char)(0xC0 | encode));
8972 }
8973
8974 void Assembler::incq(Address dst) {
8975 // Don't use it directly. Use MacroAssembler::incrementq() instead.
8976 InstructionMark im(this);
8977 prefixq(dst);
8978 emit_int8((unsigned char)0xFF);
8979 emit_operand(rax, dst);
8980 }
8981
8982 void Assembler::lea(Register dst, Address src) {
8983 leaq(dst, src);
8984 }
8985
8986 void Assembler::leaq(Register dst, Address src) {
8987 InstructionMark im(this);
8988 prefixq(src, dst);
8989 emit_int8((unsigned char)0x8D);
8990 emit_operand(dst, src);
8991 }
8992
8993 void Assembler::mov64(Register dst, int64_t imm64) {
8994 InstructionMark im(this);
8995 int encode = prefixq_and_encode(dst->encoding());
8996 emit_int8((unsigned char)(0xB8 | encode));
8997 emit_int64(imm64);
8998 }
8999
9000 void Assembler::mov_literal64(Register dst, intptr_t imm64, RelocationHolder const& rspec) {
9001 InstructionMark im(this);
9002 int encode = prefixq_and_encode(dst->encoding());
9003 emit_int8(0xB8 | encode);
9004 emit_data64(imm64, rspec);
9005 }
9006
9007 void Assembler::mov_narrow_oop(Register dst, int32_t imm32, RelocationHolder const& rspec) {
9008 InstructionMark im(this);
9009 int encode = prefix_and_encode(dst->encoding());
9010 emit_int8((unsigned char)(0xB8 | encode));
9011 emit_data((int)imm32, rspec, narrow_oop_operand);
9012 }
9013
9014 void Assembler::mov_narrow_oop(Address dst, int32_t imm32, RelocationHolder const& rspec) {
9015 InstructionMark im(this);
9016 prefix(dst);
9017 emit_int8((unsigned char)0xC7);
9018 emit_operand(rax, dst, 4);
9019 emit_data((int)imm32, rspec, narrow_oop_operand);
9020 }
9021
9022 void Assembler::cmp_narrow_oop(Register src1, int32_t imm32, RelocationHolder const& rspec) {
9023 InstructionMark im(this);
9024 int encode = prefix_and_encode(src1->encoding());
9025 emit_int8((unsigned char)0x81);
9026 emit_int8((unsigned char)(0xF8 | encode));
9027 emit_data((int)imm32, rspec, narrow_oop_operand);
9028 }
9029
9030 void Assembler::cmp_narrow_oop(Address src1, int32_t imm32, RelocationHolder const& rspec) {
9031 InstructionMark im(this);
9032 prefix(src1);
9033 emit_int8((unsigned char)0x81);
9034 emit_operand(rax, src1, 4);
9035 emit_data((int)imm32, rspec, narrow_oop_operand);
9036 }
9037
9038 void Assembler::lzcntq(Register dst, Register src) {
9039 assert(VM_Version::supports_lzcnt(), "encoding is treated as BSR");
9040 emit_int8((unsigned char)0xF3);
9041 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
9042 emit_int8(0x0F);
9043 emit_int8((unsigned char)0xBD);
9044 emit_int8((unsigned char)(0xC0 | encode));
9045 }
9046
9047 void Assembler::movdq(XMMRegister dst, Register src) {
9048 // table D-1 says MMX/SSE2
9049 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
9050 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
9051 int encode = simd_prefix_and_encode(dst, xnoreg, as_XMMRegister(src->encoding()), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
9052 emit_int8(0x6E);
9053 emit_int8((unsigned char)(0xC0 | encode));
9054 }
9055
9056 void Assembler::movdq(Register dst, XMMRegister src) {
9057 // table D-1 says MMX/SSE2
9058 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
9059 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
9060 // swap src/dst to get correct prefix
9061 int encode = simd_prefix_and_encode(src, xnoreg, as_XMMRegister(dst->encoding()), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
9062 emit_int8(0x7E);
9063 emit_int8((unsigned char)(0xC0 | encode));
9064 }
9065
9066 void Assembler::movq(Register dst, Register src) {
9067 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
9068 emit_int8((unsigned char)0x8B);
9069 emit_int8((unsigned char)(0xC0 | encode));
9070 }
9071
9072 void Assembler::movq(Register dst, Address src) {
9073 InstructionMark im(this);
9074 prefixq(src, dst);
9075 emit_int8((unsigned char)0x8B);
9076 emit_operand(dst, src);
9077 }
9078
9079 void Assembler::movq(Address dst, Register src) {
9080 InstructionMark im(this);
9081 prefixq(dst, src);
9082 emit_int8((unsigned char)0x89);
9083 emit_operand(src, dst);
9084 }
9085
9086 void Assembler::movsbq(Register dst, Address src) {
9087 InstructionMark im(this);
9088 prefixq(src, dst);
9089 emit_int8(0x0F);
9090 emit_int8((unsigned char)0xBE);
9091 emit_operand(dst, src);
9092 }
9093
9094 void Assembler::movsbq(Register dst, Register src) {
9095 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
9096 emit_int8(0x0F);
9097 emit_int8((unsigned char)0xBE);
9098 emit_int8((unsigned char)(0xC0 | encode));
9099 }
9100
9101 void Assembler::movslq(Register dst, int32_t imm32) {
9102 // dbx shows movslq(rcx, 3) as movq $0x0000000049000000,(%rbx)
9103 // and movslq(r8, 3); as movl $0x0000000048000000,(%rbx)
9104 // as a result we shouldn't use until tested at runtime...
9105 ShouldNotReachHere();
9106 InstructionMark im(this);
9107 int encode = prefixq_and_encode(dst->encoding());
9108 emit_int8((unsigned char)(0xC7 | encode));
9109 emit_int32(imm32);
9110 }
9111
9112 void Assembler::movslq(Address dst, int32_t imm32) {
9113 assert(is_simm32(imm32), "lost bits");
9114 InstructionMark im(this);
9115 prefixq(dst);
9116 emit_int8((unsigned char)0xC7);
9117 emit_operand(rax, dst, 4);
9118 emit_int32(imm32);
9119 }
9120
9121 void Assembler::movslq(Register dst, Address src) {
9122 InstructionMark im(this);
9123 prefixq(src, dst);
9124 emit_int8(0x63);
9125 emit_operand(dst, src);
9126 }
9127
9128 void Assembler::movslq(Register dst, Register src) {
9129 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
9130 emit_int8(0x63);
9131 emit_int8((unsigned char)(0xC0 | encode));
9132 }
9133
9134 void Assembler::movswq(Register dst, Address src) {
9135 InstructionMark im(this);
9136 prefixq(src, dst);
9137 emit_int8(0x0F);
9138 emit_int8((unsigned char)0xBF);
9139 emit_operand(dst, src);
9140 }
9141
9142 void Assembler::movswq(Register dst, Register src) {
9143 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
9144 emit_int8((unsigned char)0x0F);
9145 emit_int8((unsigned char)0xBF);
9146 emit_int8((unsigned char)(0xC0 | encode));
9147 }
9148
9149 void Assembler::movzbq(Register dst, Address src) {
9150 InstructionMark im(this);
9151 prefixq(src, dst);
9152 emit_int8((unsigned char)0x0F);
9153 emit_int8((unsigned char)0xB6);
9154 emit_operand(dst, src);
9155 }
9156
9157 void Assembler::movzbq(Register dst, Register src) {
9158 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
9159 emit_int8(0x0F);
9160 emit_int8((unsigned char)0xB6);
9161 emit_int8(0xC0 | encode);
9162 }
9163
9164 void Assembler::movzwq(Register dst, Address src) {
9165 InstructionMark im(this);
9166 prefixq(src, dst);
9167 emit_int8((unsigned char)0x0F);
9168 emit_int8((unsigned char)0xB7);
9169 emit_operand(dst, src);
9170 }
9171
9172 void Assembler::movzwq(Register dst, Register src) {
9173 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
9174 emit_int8((unsigned char)0x0F);
9175 emit_int8((unsigned char)0xB7);
9176 emit_int8((unsigned char)(0xC0 | encode));
9177 }
9178
9179 void Assembler::mulq(Address src) {
9180 InstructionMark im(this);
9181 prefixq(src);
9182 emit_int8((unsigned char)0xF7);
9183 emit_operand(rsp, src);
9184 }
9185
9186 void Assembler::mulq(Register src) {
9187 int encode = prefixq_and_encode(src->encoding());
9188 emit_int8((unsigned char)0xF7);
9189 emit_int8((unsigned char)(0xE0 | encode));
9190 }
9191
9192 void Assembler::mulxq(Register dst1, Register dst2, Register src) {
9193 assert(VM_Version::supports_bmi2(), "bit manipulation instructions not supported");
9194 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
9195 int encode = vex_prefix_and_encode(dst1->encoding(), dst2->encoding(), src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F_38, &attributes);
9196 emit_int8((unsigned char)0xF6);
9197 emit_int8((unsigned char)(0xC0 | encode));
9198 }
9199
9200 void Assembler::negq(Register dst) {
9201 int encode = prefixq_and_encode(dst->encoding());
9202 emit_int8((unsigned char)0xF7);
9203 emit_int8((unsigned char)(0xD8 | encode));
9204 }
9205
9206 void Assembler::notq(Register dst) {
9207 int encode = prefixq_and_encode(dst->encoding());
9208 emit_int8((unsigned char)0xF7);
9209 emit_int8((unsigned char)(0xD0 | encode));
9210 }
9211
9212 void Assembler::btsq(Address dst, int imm8) {
9213 assert(isByte(imm8), "not a byte");
9214 InstructionMark im(this);
9215 prefixq(dst);
9216 emit_int8((unsigned char)0x0F);
9217 emit_int8((unsigned char)0xBA);
9218 emit_operand(rbp /* 5 */, dst, 1);
9219 emit_int8(imm8);
9220 }
9221
9222 void Assembler::btrq(Address dst, int imm8) {
9223 assert(isByte(imm8), "not a byte");
9224 InstructionMark im(this);
9225 prefixq(dst);
9226 emit_int8((unsigned char)0x0F);
9227 emit_int8((unsigned char)0xBA);
9228 emit_operand(rsi /* 6 */, dst, 1);
9229 emit_int8(imm8);
9230 }
9231
9232 void Assembler::orq(Address dst, int32_t imm32) {
9233 InstructionMark im(this);
9234 prefixq(dst);
9235 emit_int8((unsigned char)0x81);
9236 emit_operand(rcx, dst, 4);
9237 emit_int32(imm32);
9238 }
9239
9240 void Assembler::orq(Register dst, int32_t imm32) {
9241 (void) prefixq_and_encode(dst->encoding());
9242 emit_arith(0x81, 0xC8, dst, imm32);
9243 }
9244
9245 void Assembler::orq(Register dst, Address src) {
9246 InstructionMark im(this);
9247 prefixq(src, dst);
9248 emit_int8(0x0B);
9249 emit_operand(dst, src);
9250 }
9251
9252 void Assembler::orq(Register dst, Register src) {
9253 (void) prefixq_and_encode(dst->encoding(), src->encoding());
9254 emit_arith(0x0B, 0xC0, dst, src);
9255 }
9256
9257 void Assembler::popcntq(Register dst, Address src) {
9258 assert(VM_Version::supports_popcnt(), "must support");
9259 InstructionMark im(this);
9260 emit_int8((unsigned char)0xF3);
9261 prefixq(src, dst);
9262 emit_int8((unsigned char)0x0F);
9263 emit_int8((unsigned char)0xB8);
9264 emit_operand(dst, src);
9265 }
9266
9267 void Assembler::popcntq(Register dst, Register src) {
9268 assert(VM_Version::supports_popcnt(), "must support");
9269 emit_int8((unsigned char)0xF3);
9270 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
9271 emit_int8((unsigned char)0x0F);
9272 emit_int8((unsigned char)0xB8);
9273 emit_int8((unsigned char)(0xC0 | encode));
9274 }
9275
9276 void Assembler::popq(Address dst) {
9277 InstructionMark im(this);
9278 prefixq(dst);
9279 emit_int8((unsigned char)0x8F);
9280 emit_operand(rax, dst);
9281 }
9282
9283 // Precomputable: popa, pusha, vzeroupper
9284
9285 // The result of these routines are invariant from one invocation to another
9286 // invocation for the duration of a run. Caching the result on bootstrap
9287 // and copying it out on subsequent invocations can thus be beneficial
9288 static bool precomputed = false;
9289
9290 static u_char* popa_code = NULL;
9291 static int popa_len = 0;
9292
9293 static u_char* pusha_code = NULL;
9294 static int pusha_len = 0;
9295
9296 static u_char* vzup_code = NULL;
9297 static int vzup_len = 0;
9298
9299 void Assembler::precompute_instructions() {
9330 vzup_code = NEW_C_HEAP_ARRAY(u_char, vzup_len, mtInternal);
9331 memcpy(vzup_code, end_pusha, vzup_len);
9332 } else {
9333 vzup_code = pusha_code; // dummy
9334 }
9335
9336 assert(masm.code()->total_oop_size() == 0 &&
9337 masm.code()->total_metadata_size() == 0 &&
9338 masm.code()->total_relocation_size() == 0,
9339 "pre-computed code can't reference oops, metadata or contain relocations");
9340 }
9341
9342 static void emit_copy(CodeSection* code_section, u_char* src, int src_len) {
9343 assert(src != NULL, "code to copy must have been pre-computed");
9344 assert(code_section->limit() - code_section->end() > src_len, "code buffer not large enough");
9345 address end = code_section->end();
9346 memcpy(end, src, src_len);
9347 code_section->set_end(end + src_len);
9348 }
9349
9350 void Assembler::popa() { // 64bit
9351 emit_copy(code_section(), popa_code, popa_len);
9352 }
9353
9354 void Assembler::popa_uncached() { // 64bit
9355 movq(r15, Address(rsp, 0));
9356 movq(r14, Address(rsp, wordSize));
9357 movq(r13, Address(rsp, 2 * wordSize));
9358 movq(r12, Address(rsp, 3 * wordSize));
9359 movq(r11, Address(rsp, 4 * wordSize));
9360 movq(r10, Address(rsp, 5 * wordSize));
9361 movq(r9, Address(rsp, 6 * wordSize));
9362 movq(r8, Address(rsp, 7 * wordSize));
9363 movq(rdi, Address(rsp, 8 * wordSize));
9364 movq(rsi, Address(rsp, 9 * wordSize));
9365 movq(rbp, Address(rsp, 10 * wordSize));
9366 // skip rsp
9367 movq(rbx, Address(rsp, 12 * wordSize));
9368 movq(rdx, Address(rsp, 13 * wordSize));
9369 movq(rcx, Address(rsp, 14 * wordSize));
9390 // skip rsp
9391 movq(Address(rsp, 10 * wordSize), rbp);
9392 movq(Address(rsp, 9 * wordSize), rsi);
9393 movq(Address(rsp, 8 * wordSize), rdi);
9394 movq(Address(rsp, 7 * wordSize), r8);
9395 movq(Address(rsp, 6 * wordSize), r9);
9396 movq(Address(rsp, 5 * wordSize), r10);
9397 movq(Address(rsp, 4 * wordSize), r11);
9398 movq(Address(rsp, 3 * wordSize), r12);
9399 movq(Address(rsp, 2 * wordSize), r13);
9400 movq(Address(rsp, wordSize), r14);
9401 movq(Address(rsp, 0), r15);
9402 }
9403
9404 void Assembler::vzeroupper() {
9405 emit_copy(code_section(), vzup_code, vzup_len);
9406 }
9407
9408 void Assembler::pushq(Address src) {
9409 InstructionMark im(this);
9410 prefixq(src);
9411 emit_int8((unsigned char)0xFF);
9412 emit_operand(rsi, src);
9413 }
9414
9415 void Assembler::rclq(Register dst, int imm8) {
9416 assert(isShiftCount(imm8 >> 1), "illegal shift count");
9417 int encode = prefixq_and_encode(dst->encoding());
9418 if (imm8 == 1) {
9419 emit_int8((unsigned char)0xD1);
9420 emit_int8((unsigned char)(0xD0 | encode));
9421 } else {
9422 emit_int8((unsigned char)0xC1);
9423 emit_int8((unsigned char)(0xD0 | encode));
9424 emit_int8(imm8);
9425 }
9426 }
9427
9428 void Assembler::rcrq(Register dst, int imm8) {
9429 assert(isShiftCount(imm8 >> 1), "illegal shift count");
9430 int encode = prefixq_and_encode(dst->encoding());
9431 if (imm8 == 1) {
9432 emit_int8((unsigned char)0xD1);
9433 emit_int8((unsigned char)(0xD8 | encode));
9434 } else {
9435 emit_int8((unsigned char)0xC1);
9436 emit_int8((unsigned char)(0xD8 | encode));
9437 emit_int8(imm8);
9438 }
9439 }
9440
9441 void Assembler::rorq(Register dst, int imm8) {
9442 assert(isShiftCount(imm8 >> 1), "illegal shift count");
9443 int encode = prefixq_and_encode(dst->encoding());
9444 if (imm8 == 1) {
9445 emit_int8((unsigned char)0xD1);
9446 emit_int8((unsigned char)(0xC8 | encode));
9447 } else {
9448 emit_int8((unsigned char)0xC1);
9449 emit_int8((unsigned char)(0xc8 | encode));
9450 emit_int8(imm8);
9451 }
9452 }
9453
9454 void Assembler::rorxq(Register dst, Register src, int imm8) {
9455 assert(VM_Version::supports_bmi2(), "bit manipulation instructions not supported");
9456 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
9457 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F_3A, &attributes);
9458 emit_int8((unsigned char)0xF0);
9459 emit_int8((unsigned char)(0xC0 | encode));
9460 emit_int8(imm8);
9461 }
9462
9463 void Assembler::rorxd(Register dst, Register src, int imm8) {
9464 assert(VM_Version::supports_bmi2(), "bit manipulation instructions not supported");
9465 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
9466 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F_3A, &attributes);
9467 emit_int8((unsigned char)0xF0);
9468 emit_int8((unsigned char)(0xC0 | encode));
9469 emit_int8(imm8);
9470 }
9471
9472 void Assembler::sarq(Register dst, int imm8) {
9473 assert(isShiftCount(imm8 >> 1), "illegal shift count");
9474 int encode = prefixq_and_encode(dst->encoding());
9475 if (imm8 == 1) {
9476 emit_int8((unsigned char)0xD1);
9477 emit_int8((unsigned char)(0xF8 | encode));
9478 } else {
9479 emit_int8((unsigned char)0xC1);
9480 emit_int8((unsigned char)(0xF8 | encode));
9481 emit_int8(imm8);
9482 }
9483 }
9484
9485 void Assembler::sarq(Register dst) {
9486 int encode = prefixq_and_encode(dst->encoding());
9487 emit_int8((unsigned char)0xD3);
9488 emit_int8((unsigned char)(0xF8 | encode));
9489 }
9490
9491 void Assembler::sbbq(Address dst, int32_t imm32) {
9492 InstructionMark im(this);
9493 prefixq(dst);
9494 emit_arith_operand(0x81, rbx, dst, imm32);
9495 }
9496
9497 void Assembler::sbbq(Register dst, int32_t imm32) {
9498 (void) prefixq_and_encode(dst->encoding());
9499 emit_arith(0x81, 0xD8, dst, imm32);
9500 }
9501
9502 void Assembler::sbbq(Register dst, Address src) {
9503 InstructionMark im(this);
9504 prefixq(src, dst);
9505 emit_int8(0x1B);
9506 emit_operand(dst, src);
9507 }
9508
9509 void Assembler::sbbq(Register dst, Register src) {
9510 (void) prefixq_and_encode(dst->encoding(), src->encoding());
9511 emit_arith(0x1B, 0xC0, dst, src);
9512 }
9513
9514 void Assembler::shlq(Register dst, int imm8) {
9515 assert(isShiftCount(imm8 >> 1), "illegal shift count");
9516 int encode = prefixq_and_encode(dst->encoding());
9517 if (imm8 == 1) {
9518 emit_int8((unsigned char)0xD1);
9519 emit_int8((unsigned char)(0xE0 | encode));
9520 } else {
9521 emit_int8((unsigned char)0xC1);
9522 emit_int8((unsigned char)(0xE0 | encode));
9523 emit_int8(imm8);
9524 }
9525 }
9526
9527 void Assembler::shlq(Register dst) {
9528 int encode = prefixq_and_encode(dst->encoding());
9529 emit_int8((unsigned char)0xD3);
9530 emit_int8((unsigned char)(0xE0 | encode));
9531 }
9532
9533 void Assembler::shrq(Register dst, int imm8) {
9534 assert(isShiftCount(imm8 >> 1), "illegal shift count");
9535 int encode = prefixq_and_encode(dst->encoding());
9536 emit_int8((unsigned char)0xC1);
9537 emit_int8((unsigned char)(0xE8 | encode));
9538 emit_int8(imm8);
9539 }
9540
9541 void Assembler::shrq(Register dst) {
9542 int encode = prefixq_and_encode(dst->encoding());
9543 emit_int8((unsigned char)0xD3);
9544 emit_int8(0xE8 | encode);
9545 }
9546
9547 void Assembler::subq(Address dst, int32_t imm32) {
9548 InstructionMark im(this);
9549 prefixq(dst);
9550 emit_arith_operand(0x81, rbp, dst, imm32);
9551 }
9552
9553 void Assembler::subq(Address dst, Register src) {
9554 InstructionMark im(this);
9555 prefixq(dst, src);
9556 emit_int8(0x29);
9557 emit_operand(src, dst);
9558 }
9559
9560 void Assembler::subq(Register dst, int32_t imm32) {
9561 (void) prefixq_and_encode(dst->encoding());
9562 emit_arith(0x81, 0xE8, dst, imm32);
9563 }
9564
9565 // Force generation of a 4 byte immediate value even if it fits into 8bit
9566 void Assembler::subq_imm32(Register dst, int32_t imm32) {
9567 (void) prefixq_and_encode(dst->encoding());
9568 emit_arith_imm32(0x81, 0xE8, dst, imm32);
9569 }
9570
9571 void Assembler::subq(Register dst, Address src) {
9572 InstructionMark im(this);
9573 prefixq(src, dst);
9574 emit_int8(0x2B);
9575 emit_operand(dst, src);
9576 }
9577
9578 void Assembler::subq(Register dst, Register src) {
9579 (void) prefixq_and_encode(dst->encoding(), src->encoding());
9580 emit_arith(0x2B, 0xC0, dst, src);
9581 }
9582
9583 void Assembler::testq(Register dst, int32_t imm32) {
9584 // not using emit_arith because test
9585 // doesn't support sign-extension of
9586 // 8bit operands
9587 int encode = dst->encoding();
9588 if (encode == 0) {
9589 prefix(REX_W);
9590 emit_int8((unsigned char)0xA9);
9591 } else {
9592 encode = prefixq_and_encode(encode);
9593 emit_int8((unsigned char)0xF7);
9594 emit_int8((unsigned char)(0xC0 | encode));
9595 }
9596 emit_int32(imm32);
9597 }
9598
9599 void Assembler::testq(Register dst, Register src) {
9600 (void) prefixq_and_encode(dst->encoding(), src->encoding());
9601 emit_arith(0x85, 0xC0, dst, src);
9602 }
9603
9604 void Assembler::testq(Register dst, Address src) {
9605 InstructionMark im(this);
9606 prefixq(src, dst);
9607 emit_int8((unsigned char)0x85);
9608 emit_operand(dst, src);
9609 }
9610
9611 void Assembler::xaddq(Address dst, Register src) {
9612 InstructionMark im(this);
9613 prefixq(dst, src);
9614 emit_int8(0x0F);
9615 emit_int8((unsigned char)0xC1);
9616 emit_operand(src, dst);
9617 }
9618
9619 void Assembler::xchgq(Register dst, Address src) {
9620 InstructionMark im(this);
9621 prefixq(src, dst);
9622 emit_int8((unsigned char)0x87);
9623 emit_operand(dst, src);
9624 }
9625
9626 void Assembler::xchgq(Register dst, Register src) {
9627 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
9628 emit_int8((unsigned char)0x87);
9629 emit_int8((unsigned char)(0xc0 | encode));
9630 }
9631
9632 void Assembler::xorq(Register dst, Register src) {
9633 (void) prefixq_and_encode(dst->encoding(), src->encoding());
9634 emit_arith(0x33, 0xC0, dst, src);
9635 }
9636
9637 void Assembler::xorq(Register dst, Address src) {
9638 InstructionMark im(this);
9639 prefixq(src, dst);
9640 emit_int8(0x33);
9641 emit_operand(dst, src);
9642 }
9643
9644 #endif // !LP64
|
231 code_section()->relocate(inst_mark(), rspec, disp32_operand);
232 else
233 code_section()->relocate(inst_mark(), rspec, format);
234 }
235 emit_int32(data);
236 }
237
238 static int encode(Register r) {
239 int enc = r->encoding();
240 if (enc >= 8) {
241 enc -= 8;
242 }
243 return enc;
244 }
245
246 void Assembler::emit_arith_b(int op1, int op2, Register dst, int imm8) {
247 assert(dst->has_byte_register(), "must have byte register");
248 assert(isByte(op1) && isByte(op2), "wrong opcode");
249 assert(isByte(imm8), "not a byte");
250 assert((op1 & 0x01) == 0, "should be 8bit operation");
251 emit_int24(op1, op2 | encode(dst), imm8);
252 }
253
254
255 void Assembler::emit_arith(int op1, int op2, Register dst, int32_t imm32) {
256 assert(isByte(op1) && isByte(op2), "wrong opcode");
257 assert((op1 & 0x01) == 1, "should be 32bit operation");
258 assert((op1 & 0x02) == 0, "sign-extension bit should not be set");
259 if (is8bit(imm32)) {
260 // set sign bit
261 emit_int24(op1 | 0x02, op2 | encode(dst), imm32 & 0xFF);
262 } else {
263 emit_int16(op1, op2 | encode(dst));
264 emit_int32(imm32);
265 }
266 }
267
268 // Force generation of a 4 byte immediate value even if it fits into 8bit
269 void Assembler::emit_arith_imm32(int op1, int op2, Register dst, int32_t imm32) {
270 assert(isByte(op1) && isByte(op2), "wrong opcode");
271 assert((op1 & 0x01) == 1, "should be 32bit operation");
272 assert((op1 & 0x02) == 0, "sign-extension bit should not be set");
273 emit_int16(op1, op2 | encode(dst));
274 emit_int32(imm32);
275 }
276
277 // immediate-to-memory forms
278 void Assembler::emit_arith_operand(int op1, Register rm, Address adr, int32_t imm32) {
279 assert((op1 & 0x01) == 1, "should be 32bit operation");
280 assert((op1 & 0x02) == 0, "sign-extension bit should not be set");
281 if (is8bit(imm32)) {
282 emit_int8(op1 | 0x02); // set sign bit
283 emit_operand(rm, adr, 1);
284 emit_int8(imm32 & 0xFF);
285 } else {
286 emit_int8(op1);
287 emit_operand(rm, adr, 4);
288 emit_int32(imm32);
289 }
290 }
291
292
293 void Assembler::emit_arith(int op1, int op2, Register dst, Register src) {
294 assert(isByte(op1) && isByte(op2), "wrong opcode");
295 emit_int16(op1, op2 | encode(dst) << 3 | encode(src));
296 }
297
298
299 bool Assembler::query_compressed_disp_byte(int disp, bool is_evex_inst, int vector_len,
300 int cur_tuple_type, int in_size_in_bits, int cur_encoding) {
301 int mod_idx = 0;
302 // We will test if the displacement fits the compressed format and if so
303 // apply the compression to the displacment iff the result is8bit.
304 if (VM_Version::supports_evex() && is_evex_inst) {
305 switch (cur_tuple_type) {
306 case EVEX_FV:
307 if ((cur_encoding & VEX_W) == VEX_W) {
308 mod_idx = ((cur_encoding & EVEX_Rb) == EVEX_Rb) ? 3 : 2;
309 } else {
310 mod_idx = ((cur_encoding & EVEX_Rb) == EVEX_Rb) ? 1 : 0;
311 }
312 break;
313
314 case EVEX_HV:
315 mod_idx = ((cur_encoding & EVEX_Rb) == EVEX_Rb) ? 1 : 0;
457 if (vector_len >= AVX_128bit && vector_len <= AVX_512bit) {
458 int disp_factor = tuple_table[tuple_type + mod_idx][vector_len];
459 if ((disp % disp_factor) == 0) {
460 int new_disp = disp / disp_factor;
461 if (is8bit(new_disp)) {
462 disp = new_disp;
463 }
464 } else {
465 return false;
466 }
467 }
468 }
469 return is8bit(disp);
470 }
471
472
473 void Assembler::emit_operand(Register reg, Register base, Register index,
474 Address::ScaleFactor scale, int disp,
475 RelocationHolder const& rspec,
476 int rip_relative_correction) {
477 bool no_relocation = rspec.type() == relocInfo::none;
478
479 // Encode the registers as needed in the fields they are used in
480 int regenc = encode(reg) << 3;
481 if (base->is_valid()) {
482 int baseenc = encode(base);
483 if (index->is_valid()) {
484 assert(scale != Address::no_scale, "inconsistent address");
485 // [base + index*scale + disp]
486 int indexenc = encode(index) << 3;
487 if (disp == 0 && no_relocation &&
488 base != rbp LP64_ONLY(&& base != r13)) {
489 // [base + index*scale]
490 // [00 reg 100][ss index base]
491 assert(index != rsp, "illegal addressing mode");
492 emit_int16(0x04 | regenc, scale << 6 | indexenc | baseenc);
493 } else if (emit_compressed_disp_byte(disp) && no_relocation) {
494 // [base + index*scale + imm8]
495 // [01 reg 100][ss index base] imm8
496 assert(index != rsp, "illegal addressing mode");
497 emit_int24(0x44 | regenc, scale << 6 | indexenc | baseenc, disp & 0xFF);
498 } else {
499 // [base + index*scale + disp32]
500 // [10 reg 100][ss index base] disp32
501 assert(index != rsp, "illegal addressing mode");
502 emit_int16(0x84 | regenc, scale << 6 | indexenc | baseenc);
503 emit_data(disp, rspec, disp32_operand);
504 }
505 } else if (base == rsp LP64_ONLY(|| base == r12)) {
506 // [rsp + disp]
507 if (disp == 0 && no_relocation) {
508 // [rsp]
509 // [00 reg 100][00 100 100]
510 emit_int16(0x04 | regenc, 0x24);
511 } else if (emit_compressed_disp_byte(disp) && no_relocation) {
512 // [rsp + imm8]
513 // [01 reg 100][00 100 100] disp8
514 emit_int24(0x44 | regenc, 0x24, disp & 0xFF);
515 } else {
516 // [rsp + imm32]
517 // [10 reg 100][00 100 100] disp32
518 emit_int16(0x84 | regenc, 0x24);
519 emit_data(disp, rspec, disp32_operand);
520 }
521 } else {
522 // [base + disp]
523 assert(base != rsp LP64_ONLY(&& base != r12), "illegal addressing mode");
524 if (disp == 0 && no_relocation &&
525 base != rbp LP64_ONLY(&& base != r13)) {
526 // [base]
527 // [00 reg base]
528 emit_int8(0x00 | regenc | baseenc);
529 } else if (emit_compressed_disp_byte(disp) && no_relocation) {
530 // [base + disp8]
531 // [01 reg base] disp8
532 emit_int16(0x40 | regenc | baseenc, disp & 0xFF);
533 } else {
534 // [base + disp32]
535 // [10 reg base] disp32
536 emit_int8(0x80 | regenc | baseenc);
537 emit_data(disp, rspec, disp32_operand);
538 }
539 }
540 } else {
541 if (index->is_valid()) {
542 assert(scale != Address::no_scale, "inconsistent address");
543 // [index*scale + disp]
544 // [00 reg 100][ss index 101] disp32
545 assert(index != rsp, "illegal addressing mode");
546 emit_int16(0x04 | regenc, scale << 6 | (encode(index) << 3) | 0x05);
547 emit_data(disp, rspec, disp32_operand);
548 } else if (!no_relocation) {
549 // [disp] (64bit) RIP-RELATIVE (32bit) abs
550 // [00 000 101] disp32
551
552 emit_int8(0x05 | regenc);
553 // Note that the RIP-rel. correction applies to the generated
554 // disp field, but _not_ to the target address in the rspec.
555
556 // disp was created by converting the target address minus the pc
557 // at the start of the instruction. That needs more correction here.
558 // intptr_t disp = target - next_ip;
559 assert(inst_mark() != NULL, "must be inside InstructionMark");
560 address next_ip = pc() + sizeof(int32_t) + rip_relative_correction;
561 int64_t adjusted = disp;
562 // Do rip-rel adjustment for 64bit
563 LP64_ONLY(adjusted -= (next_ip - inst_mark()));
564 assert(is_simm32(adjusted),
565 "must be 32bit offset (RIP relative address)");
566 emit_data((int32_t) adjusted, rspec, disp32_operand);
567
568 } else {
569 // 32bit never did this, did everything as the rip-rel/disp code above
570 // [disp] ABSOLUTE
571 // [00 reg 100][00 100 101] disp32
572 emit_int16(0x04 | regenc, 0x25);
573 emit_data(disp, rspec, disp32_operand);
574 }
575 }
576 }
577
578 void Assembler::emit_operand(XMMRegister reg, Register base, Register index,
579 Address::ScaleFactor scale, int disp,
580 RelocationHolder const& rspec) {
581 if (UseAVX > 2) {
582 int xreg_enc = reg->encoding();
583 if (xreg_enc > 15) {
584 XMMRegister new_reg = as_XMMRegister(xreg_enc & 0xf);
585 emit_operand((Register)new_reg, base, index, scale, disp, rspec);
586 return;
587 }
588 }
589 emit_operand((Register)reg, base, index, scale, disp, rspec);
590 }
591
592 void Assembler::emit_operand(XMMRegister reg, Register base, XMMRegister index,
1112 adr._rspec);
1113 }
1114 }
1115
1116 // MMX operations
1117 void Assembler::emit_operand(MMXRegister reg, Address adr) {
1118 assert(!adr.base_needs_rex() && !adr.index_needs_rex(), "no extended registers");
1119 emit_operand((Register)reg, adr._base, adr._index, adr._scale, adr._disp, adr._rspec);
1120 }
1121
1122 // work around gcc (3.2.1-7a) bug
1123 void Assembler::emit_operand(Address adr, MMXRegister reg) {
1124 assert(!adr.base_needs_rex() && !adr.index_needs_rex(), "no extended registers");
1125 emit_operand((Register)reg, adr._base, adr._index, adr._scale, adr._disp, adr._rspec);
1126 }
1127
1128
1129 void Assembler::emit_farith(int b1, int b2, int i) {
1130 assert(isByte(b1) && isByte(b2), "wrong opcode");
1131 assert(0 <= i && i < 8, "illegal stack offset");
1132 emit_int16(b1, b2 + i);
1133 }
1134
1135
1136 // Now the Assembler instructions (identical for 32/64 bits)
1137
1138 void Assembler::adcl(Address dst, int32_t imm32) {
1139 InstructionMark im(this);
1140 prefix(dst);
1141 emit_arith_operand(0x81, rdx, dst, imm32);
1142 }
1143
1144 void Assembler::adcl(Address dst, Register src) {
1145 InstructionMark im(this);
1146 prefix(dst, src);
1147 emit_int8(0x11);
1148 emit_operand(src, dst);
1149 }
1150
1151 void Assembler::adcl(Register dst, int32_t imm32) {
1152 prefix(dst);
1198 void Assembler::addl(Register dst, int32_t imm32) {
1199 prefix(dst);
1200 emit_arith(0x81, 0xC0, dst, imm32);
1201 }
1202
1203 void Assembler::addl(Register dst, Address src) {
1204 InstructionMark im(this);
1205 prefix(src, dst);
1206 emit_int8(0x03);
1207 emit_operand(dst, src);
1208 }
1209
1210 void Assembler::addl(Register dst, Register src) {
1211 (void) prefix_and_encode(dst->encoding(), src->encoding());
1212 emit_arith(0x03, 0xC0, dst, src);
1213 }
1214
1215 void Assembler::addr_nop_4() {
1216 assert(UseAddressNop, "no CPU support");
1217 // 4 bytes: NOP DWORD PTR [EAX+0]
1218 emit_int32(0x0F,
1219 0x1F,
1220 0x40, // emit_rm(cbuf, 0x1, EAX_enc, EAX_enc);
1221 0); // 8-bits offset (1 byte)
1222 }
1223
1224 void Assembler::addr_nop_5() {
1225 assert(UseAddressNop, "no CPU support");
1226 // 5 bytes: NOP DWORD PTR [EAX+EAX*0+0] 8-bits offset
1227 emit_int32(0x0F,
1228 0x1F,
1229 0x44, // emit_rm(cbuf, 0x1, EAX_enc, 0x4);
1230 0x00); // emit_rm(cbuf, 0x0, EAX_enc, EAX_enc);
1231 emit_int8(0); // 8-bits offset (1 byte)
1232 }
1233
1234 void Assembler::addr_nop_7() {
1235 assert(UseAddressNop, "no CPU support");
1236 // 7 bytes: NOP DWORD PTR [EAX+0] 32-bits offset
1237 emit_int24(0x0F,
1238 0x1F,
1239 (unsigned char)0x80);
1240 // emit_rm(cbuf, 0x2, EAX_enc, EAX_enc);
1241 emit_int32(0); // 32-bits offset (4 bytes)
1242 }
1243
1244 void Assembler::addr_nop_8() {
1245 assert(UseAddressNop, "no CPU support");
1246 // 8 bytes: NOP DWORD PTR [EAX+EAX*0+0] 32-bits offset
1247 emit_int32(0x0F,
1248 0x1F,
1249 (unsigned char)0x84,
1250 // emit_rm(cbuf, 0x2, EAX_enc, 0x4);
1251 0x00); // emit_rm(cbuf, 0x0, EAX_enc, EAX_enc);
1252 emit_int32(0); // 32-bits offset (4 bytes)
1253 }
1254
1255 void Assembler::addsd(XMMRegister dst, XMMRegister src) {
1256 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1257 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1258 attributes.set_rex_vex_w_reverted();
1259 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
1260 emit_int16(0x58, (unsigned char)(0xC0 | encode));
1261 }
1262
1263 void Assembler::addsd(XMMRegister dst, Address src) {
1264 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1265 InstructionMark im(this);
1266 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1267 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
1268 attributes.set_rex_vex_w_reverted();
1269 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
1270 emit_int8(0x58);
1271 emit_operand(dst, src);
1272 }
1273
1274 void Assembler::addss(XMMRegister dst, XMMRegister src) {
1275 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1276 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1277 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1278 emit_int16(0x58, (unsigned char)(0xC0 | encode));
1279 }
1280
1281 void Assembler::addss(XMMRegister dst, Address src) {
1282 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1283 InstructionMark im(this);
1284 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1285 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
1286 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1287 emit_int8(0x58);
1288 emit_operand(dst, src);
1289 }
1290
1291 void Assembler::aesdec(XMMRegister dst, Address src) {
1292 assert(VM_Version::supports_aes(), "");
1293 InstructionMark im(this);
1294 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
1295 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1296 emit_int8((unsigned char)0xDE);
1297 emit_operand(dst, src);
1298 }
1299
1300 void Assembler::aesdec(XMMRegister dst, XMMRegister src) {
1301 assert(VM_Version::supports_aes(), "");
1302 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
1303 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1304 emit_int16((unsigned char)0xDE, 0xC0 | encode);
1305 }
1306
1307 void Assembler::vaesdec(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
1308 assert(VM_Version::supports_avx512_vaes(), "");
1309 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
1310 attributes.set_is_evex_instruction();
1311 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1312 emit_int16((unsigned char)0xDE, (unsigned char)(0xC0 | encode));
1313 }
1314
1315
1316 void Assembler::aesdeclast(XMMRegister dst, Address src) {
1317 assert(VM_Version::supports_aes(), "");
1318 InstructionMark im(this);
1319 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
1320 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1321 emit_int8((unsigned char)0xDF);
1322 emit_operand(dst, src);
1323 }
1324
1325 void Assembler::aesdeclast(XMMRegister dst, XMMRegister src) {
1326 assert(VM_Version::supports_aes(), "");
1327 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
1328 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1329 emit_int16((unsigned char)0xDF, (unsigned char)(0xC0 | encode));
1330 }
1331
1332 void Assembler::vaesdeclast(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
1333 assert(VM_Version::supports_avx512_vaes(), "");
1334 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
1335 attributes.set_is_evex_instruction();
1336 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1337 emit_int16((unsigned char)0xDF, (unsigned char)(0xC0 | encode));
1338 }
1339
1340 void Assembler::aesenc(XMMRegister dst, Address src) {
1341 assert(VM_Version::supports_aes(), "");
1342 InstructionMark im(this);
1343 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
1344 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1345 emit_int8((unsigned char)0xDC);
1346 emit_operand(dst, src);
1347 }
1348
1349 void Assembler::aesenc(XMMRegister dst, XMMRegister src) {
1350 assert(VM_Version::supports_aes(), "");
1351 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
1352 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1353 emit_int16((unsigned char)0xDC, 0xC0 | encode);
1354 }
1355
1356 void Assembler::vaesenc(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
1357 assert(VM_Version::supports_avx512_vaes(), "requires vaes support/enabling");
1358 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
1359 attributes.set_is_evex_instruction();
1360 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1361 emit_int16((unsigned char)0xDC, (unsigned char)(0xC0 | encode));
1362 }
1363
1364 void Assembler::aesenclast(XMMRegister dst, Address src) {
1365 assert(VM_Version::supports_aes(), "");
1366 InstructionMark im(this);
1367 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
1368 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1369 emit_int8((unsigned char)0xDD);
1370 emit_operand(dst, src);
1371 }
1372
1373 void Assembler::aesenclast(XMMRegister dst, XMMRegister src) {
1374 assert(VM_Version::supports_aes(), "");
1375 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
1376 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1377 emit_int16((unsigned char)0xDD, (unsigned char)(0xC0 | encode));
1378 }
1379
1380 void Assembler::vaesenclast(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
1381 assert(VM_Version::supports_avx512_vaes(), "requires vaes support/enabling");
1382 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
1383 attributes.set_is_evex_instruction();
1384 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1385 emit_int16((unsigned char)0xDD, (unsigned char)(0xC0 | encode));
1386 }
1387
1388 void Assembler::andl(Address dst, int32_t imm32) {
1389 InstructionMark im(this);
1390 prefix(dst);
1391 emit_int8((unsigned char)0x81);
1392 emit_operand(rsp, dst, 4);
1393 emit_int32(imm32);
1394 }
1395
1396 void Assembler::andl(Register dst, int32_t imm32) {
1397 prefix(dst);
1398 emit_arith(0x81, 0xE0, dst, imm32);
1399 }
1400
1401 void Assembler::andl(Register dst, Address src) {
1402 InstructionMark im(this);
1403 prefix(src, dst);
1404 emit_int8(0x23);
1405 emit_operand(dst, src);
1406 }
1407
1408 void Assembler::andl(Register dst, Register src) {
1409 (void) prefix_and_encode(dst->encoding(), src->encoding());
1410 emit_arith(0x23, 0xC0, dst, src);
1411 }
1412
1413 void Assembler::andnl(Register dst, Register src1, Register src2) {
1414 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1415 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
1416 int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
1417 emit_int16((unsigned char)0xF2, (unsigned char)(0xC0 | encode));
1418 }
1419
1420 void Assembler::andnl(Register dst, Register src1, Address src2) {
1421 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1422 InstructionMark im(this);
1423 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
1424 vex_prefix(src2, src1->encoding(), dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
1425 emit_int8((unsigned char)0xF2);
1426 emit_operand(dst, src2);
1427 }
1428
1429 void Assembler::bsfl(Register dst, Register src) {
1430 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1431 emit_int24(0x0F, (unsigned char)0xBC, (unsigned char)(0xC0 | encode));
1432 }
1433
1434 void Assembler::bsrl(Register dst, Register src) {
1435 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1436 emit_int24(0x0F, (unsigned char)0xBD, (unsigned char)(0xC0 | encode));
1437 }
1438
1439 void Assembler::bswapl(Register reg) { // bswap
1440 int encode = prefix_and_encode(reg->encoding());
1441 emit_int16(0x0F, (unsigned char)(0xC8 | encode));
1442 }
1443
1444 void Assembler::blsil(Register dst, Register src) {
1445 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1446 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
1447 int encode = vex_prefix_and_encode(rbx->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
1448 emit_int16((unsigned char)0xF3, (unsigned char)(0xC0 | encode));
1449 }
1450
1451 void Assembler::blsil(Register dst, Address src) {
1452 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1453 InstructionMark im(this);
1454 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
1455 vex_prefix(src, dst->encoding(), rbx->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
1456 emit_int8((unsigned char)0xF3);
1457 emit_operand(rbx, src);
1458 }
1459
1460 void Assembler::blsmskl(Register dst, Register src) {
1461 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1462 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
1463 int encode = vex_prefix_and_encode(rdx->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
1464 emit_int16((unsigned char)0xF3, (unsigned char)(0xC0 | encode));
1465 }
1466
1467 void Assembler::blsmskl(Register dst, Address src) {
1468 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1469 InstructionMark im(this);
1470 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
1471 vex_prefix(src, dst->encoding(), rdx->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
1472 emit_int8((unsigned char)0xF3);
1473 emit_operand(rdx, src);
1474 }
1475
1476 void Assembler::blsrl(Register dst, Register src) {
1477 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1478 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
1479 int encode = vex_prefix_and_encode(rcx->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
1480 emit_int16((unsigned char)0xF3, (unsigned char)(0xC0 | encode));
1481 }
1482
1483 void Assembler::blsrl(Register dst, Address src) {
1484 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1485 InstructionMark im(this);
1486 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
1487 vex_prefix(src, dst->encoding(), rcx->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
1488 emit_int8((unsigned char)0xF3);
1489 emit_operand(rcx, src);
1490 }
1491
1492 void Assembler::call(Label& L, relocInfo::relocType rtype) {
1493 // suspect disp32 is always good
1494 int operand = LP64_ONLY(disp32_operand) NOT_LP64(imm_operand);
1495
1496 if (L.is_bound()) {
1497 const int long_size = 5;
1498 int offs = (int)( target(L) - pc() );
1499 assert(offs <= 0, "assembler error");
1500 InstructionMark im(this);
1501 // 1110 1000 #32-bit disp
1502 emit_int8((unsigned char)0xE8);
1503 emit_data(offs - long_size, rtype, operand);
1504 } else {
1505 InstructionMark im(this);
1506 // 1110 1000 #32-bit disp
1507 L.add_patch_at(code(), locator());
1508
1509 emit_int8((unsigned char)0xE8);
1510 emit_data(int(0), rtype, operand);
1511 }
1512 }
1513
1514 void Assembler::call(Register dst) {
1515 int encode = prefix_and_encode(dst->encoding());
1516 emit_int16((unsigned char)0xFF, (unsigned char)(0xD0 | encode));
1517 }
1518
1519
1520 void Assembler::call(Address adr) {
1521 InstructionMark im(this);
1522 prefix(adr);
1523 emit_int8((unsigned char)0xFF);
1524 emit_operand(rdx, adr);
1525 }
1526
1527 void Assembler::call_literal(address entry, RelocationHolder const& rspec) {
1528 InstructionMark im(this);
1529 emit_int8((unsigned char)0xE8);
1530 intptr_t disp = entry - (pc() + sizeof(int32_t));
1531 // Entry is NULL in case of a scratch emit.
1532 assert(entry == NULL || is_simm32(disp), "disp=" INTPTR_FORMAT " must be 32bit offset (call2)", disp);
1533 // Technically, should use call32_operand, but this format is
1534 // implied by the fact that we're emitting a call instruction.
1535
1536 int operand = LP64_ONLY(disp32_operand) NOT_LP64(call32_operand);
1537 emit_data((int) disp, rspec, operand);
1538 }
1539
1540 void Assembler::cdql() {
1541 emit_int8((unsigned char)0x99);
1542 }
1543
1544 void Assembler::cld() {
1545 emit_int8((unsigned char)0xFC);
1546 }
1547
1548 void Assembler::cmovl(Condition cc, Register dst, Register src) {
1549 NOT_LP64(guarantee(VM_Version::supports_cmov(), "illegal instruction"));
1550 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1551 emit_int24(0x0F, 0x40 | cc, (unsigned char)(0xC0 | encode));
1552 }
1553
1554
1555 void Assembler::cmovl(Condition cc, Register dst, Address src) {
1556 NOT_LP64(guarantee(VM_Version::supports_cmov(), "illegal instruction"));
1557 prefix(src, dst);
1558 emit_int16(0x0F, 0x40 | cc);
1559 emit_operand(dst, src);
1560 }
1561
1562 void Assembler::cmpb(Address dst, int imm8) {
1563 InstructionMark im(this);
1564 prefix(dst);
1565 emit_int8((unsigned char)0x80);
1566 emit_operand(rdi, dst, 1);
1567 emit_int8(imm8);
1568 }
1569
1570 void Assembler::cmpl(Address dst, int32_t imm32) {
1571 InstructionMark im(this);
1572 prefix(dst);
1573 emit_int8((unsigned char)0x81);
1574 emit_operand(rdi, dst, 4);
1575 emit_int32(imm32);
1576 }
1577
1578 void Assembler::cmpl(Register dst, int32_t imm32) {
1579 prefix(dst);
1580 emit_arith(0x81, 0xF8, dst, imm32);
1581 }
1582
1583 void Assembler::cmpl(Register dst, Register src) {
1584 (void) prefix_and_encode(dst->encoding(), src->encoding());
1585 emit_arith(0x3B, 0xC0, dst, src);
1586 }
1587
1588 void Assembler::cmpl(Register dst, Address src) {
1589 InstructionMark im(this);
1590 prefix(src, dst);
1591 emit_int8((unsigned char)0x3B);
1592 emit_operand(dst, src);
1593 }
1594
1595 void Assembler::cmpw(Address dst, int imm16) {
1596 InstructionMark im(this);
1597 assert(!dst.base_needs_rex() && !dst.index_needs_rex(), "no extended registers");
1598 emit_int16(0x66, (unsigned char)0x81);
1599 emit_operand(rdi, dst, 2);
1600 emit_int16(imm16);
1601 }
1602
1603 // The 32-bit cmpxchg compares the value at adr with the contents of rax,
1604 // and stores reg into adr if so; otherwise, the value at adr is loaded into rax,.
1605 // The ZF is set if the compared values were equal, and cleared otherwise.
1606 void Assembler::cmpxchgl(Register reg, Address adr) { // cmpxchg
1607 InstructionMark im(this);
1608 prefix(adr, reg);
1609 emit_int16(0x0F, (unsigned char)0xB1);
1610 emit_operand(reg, adr);
1611 }
1612
1613 // The 8-bit cmpxchg compares the value at adr with the contents of rax,
1614 // and stores reg into adr if so; otherwise, the value at adr is loaded into rax,.
1615 // The ZF is set if the compared values were equal, and cleared otherwise.
1616 void Assembler::cmpxchgb(Register reg, Address adr) { // cmpxchg
1617 InstructionMark im(this);
1618 prefix(adr, reg, true);
1619 emit_int16(0x0F, (unsigned char)0xB0);
1620 emit_operand(reg, adr);
1621 }
1622
1623 void Assembler::comisd(XMMRegister dst, Address src) {
1624 // NOTE: dbx seems to decode this as comiss even though the
1625 // 0x66 is there. Strangly ucomisd comes out correct
1626 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1627 InstructionMark im(this);
1628 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);;
1629 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
1630 attributes.set_rex_vex_w_reverted();
1631 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
1632 emit_int8(0x2F);
1633 emit_operand(dst, src);
1634 }
1635
1636 void Assembler::comisd(XMMRegister dst, XMMRegister src) {
1637 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1638 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1639 attributes.set_rex_vex_w_reverted();
1640 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
1641 emit_int16(0x2F, (unsigned char)(0xC0 | encode));
1642 }
1643
1644 void Assembler::comiss(XMMRegister dst, Address src) {
1645 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1646 InstructionMark im(this);
1647 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1648 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
1649 simd_prefix(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
1650 emit_int8(0x2F);
1651 emit_operand(dst, src);
1652 }
1653
1654 void Assembler::comiss(XMMRegister dst, XMMRegister src) {
1655 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1656 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1657 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
1658 emit_int16(0x2F, (unsigned char)(0xC0 | encode));
1659 }
1660
1661 void Assembler::cpuid() {
1662 emit_int16(0x0F, (unsigned char)0xA2);
1663 }
1664
1665 // Opcode / Instruction Op / En 64 - Bit Mode Compat / Leg Mode Description Implemented
1666 // F2 0F 38 F0 / r CRC32 r32, r / m8 RM Valid Valid Accumulate CRC32 on r / m8. v
1667 // F2 REX 0F 38 F0 / r CRC32 r32, r / m8* RM Valid N.E. Accumulate CRC32 on r / m8. -
1668 // F2 REX.W 0F 38 F0 / r CRC32 r64, r / m8 RM Valid N.E. Accumulate CRC32 on r / m8. -
1669 //
1670 // F2 0F 38 F1 / r CRC32 r32, r / m16 RM Valid Valid Accumulate CRC32 on r / m16. v
1671 //
1672 // F2 0F 38 F1 / r CRC32 r32, r / m32 RM Valid Valid Accumulate CRC32 on r / m32. v
1673 //
1674 // F2 REX.W 0F 38 F1 / r CRC32 r64, r / m64 RM Valid N.E. Accumulate CRC32 on r / m64. v
1675 void Assembler::crc32(Register crc, Register v, int8_t sizeInBytes) {
1676 assert(VM_Version::supports_sse4_2(), "");
1677 int8_t w = 0x01;
1678 Prefix p = Prefix_EMPTY;
1679
1680 emit_int8((int8_t)0xF2);
1681 switch (sizeInBytes) {
1682 case 1:
1689 // This instruction is not valid in 32 bits
1690 // Note:
1691 // http://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-software-developer-instruction-set-reference-manual-325383.pdf
1692 //
1693 // Page B - 72 Vol. 2C says
1694 // qwreg2 to qwreg 1111 0010 : 0100 1R0B : 0000 1111 : 0011 1000 : 1111 0000 : 11 qwreg1 qwreg2
1695 // mem64 to qwreg 1111 0010 : 0100 1R0B : 0000 1111 : 0011 1000 : 1111 0000 : mod qwreg r / m
1696 // F0!!!
1697 // while 3 - 208 Vol. 2A
1698 // F2 REX.W 0F 38 F1 / r CRC32 r64, r / m64 RM Valid N.E.Accumulate CRC32 on r / m64.
1699 //
1700 // the 0 on a last bit is reserved for a different flavor of this instruction :
1701 // F2 REX.W 0F 38 F0 / r CRC32 r64, r / m8 RM Valid N.E.Accumulate CRC32 on r / m8.
1702 p = REX_W;
1703 break;
1704 default:
1705 assert(0, "Unsupported value for a sizeInBytes argument");
1706 break;
1707 }
1708 LP64_ONLY(prefix(crc, v, p);)
1709 emit_int32((int8_t)0x0F,
1710 0x38,
1711 (int8_t)(0xF0 | w),
1712 0xC0 | ((crc->encoding() & 0x7) << 3) | (v->encoding() & 7));
1713 }
1714
1715 void Assembler::crc32(Register crc, Address adr, int8_t sizeInBytes) {
1716 assert(VM_Version::supports_sse4_2(), "");
1717 InstructionMark im(this);
1718 int8_t w = 0x01;
1719 Prefix p = Prefix_EMPTY;
1720
1721 emit_int8((int8_t)0xF2);
1722 switch (sizeInBytes) {
1723 case 1:
1724 w = 0;
1725 break;
1726 case 2:
1727 case 4:
1728 break;
1729 LP64_ONLY(case 8:)
1730 // This instruction is not valid in 32 bits
1731 p = REX_W;
1732 break;
1733 default:
1734 assert(0, "Unsupported value for a sizeInBytes argument");
1735 break;
1736 }
1737 LP64_ONLY(prefix(crc, adr, p);)
1738 emit_int24(0x0F, 0x38, (unsigned char)(0xF0 | w));
1739 emit_operand(crc, adr);
1740 }
1741
1742 void Assembler::cvtdq2pd(XMMRegister dst, XMMRegister src) {
1743 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1744 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
1745 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1746 emit_int16((unsigned char)0xE6, (unsigned char)(0xC0 | encode));
1747 }
1748
1749 void Assembler::cvtdq2ps(XMMRegister dst, XMMRegister src) {
1750 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1751 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
1752 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
1753 emit_int16(0x5B, (unsigned char)(0xC0 | encode));
1754 }
1755
1756 void Assembler::cvtsd2ss(XMMRegister dst, XMMRegister src) {
1757 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1758 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1759 attributes.set_rex_vex_w_reverted();
1760 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
1761 emit_int16(0x5A, (unsigned char)(0xC0 | encode));
1762 }
1763
1764 void Assembler::cvtsd2ss(XMMRegister dst, Address src) {
1765 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1766 InstructionMark im(this);
1767 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1768 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
1769 attributes.set_rex_vex_w_reverted();
1770 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
1771 emit_int8(0x5A);
1772 emit_operand(dst, src);
1773 }
1774
1775 void Assembler::cvtsi2sdl(XMMRegister dst, Register src) {
1776 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1777 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1778 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
1779 emit_int16(0x2A, (unsigned char)(0xC0 | encode));
1780 }
1781
1782 void Assembler::cvtsi2sdl(XMMRegister dst, Address src) {
1783 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1784 InstructionMark im(this);
1785 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1786 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
1787 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
1788 emit_int8(0x2A);
1789 emit_operand(dst, src);
1790 }
1791
1792 void Assembler::cvtsi2ssl(XMMRegister dst, Register src) {
1793 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1794 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1795 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1796 emit_int16(0x2A, (unsigned char)(0xC0 | encode));
1797 }
1798
1799 void Assembler::cvtsi2ssl(XMMRegister dst, Address src) {
1800 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1801 InstructionMark im(this);
1802 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1803 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
1804 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1805 emit_int8(0x2A);
1806 emit_operand(dst, src);
1807 }
1808
1809 void Assembler::cvtsi2ssq(XMMRegister dst, Register src) {
1810 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1811 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1812 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1813 emit_int16(0x2A, (unsigned char)(0xC0 | encode));
1814 }
1815
1816 void Assembler::cvtss2sd(XMMRegister dst, XMMRegister src) {
1817 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1818 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1819 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1820 emit_int16(0x5A, (unsigned char)(0xC0 | encode));
1821 }
1822
1823 void Assembler::cvtss2sd(XMMRegister dst, Address src) {
1824 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1825 InstructionMark im(this);
1826 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1827 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
1828 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1829 emit_int8(0x5A);
1830 emit_operand(dst, src);
1831 }
1832
1833
1834 void Assembler::cvttsd2sil(Register dst, XMMRegister src) {
1835 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1836 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1837 int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
1838 emit_int16(0x2C, (unsigned char)(0xC0 | encode));
1839 }
1840
1841 void Assembler::cvttss2sil(Register dst, XMMRegister src) {
1842 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1843 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1844 int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1845 emit_int16(0x2C, (unsigned char)(0xC0 | encode));
1846 }
1847
1848 void Assembler::cvttpd2dq(XMMRegister dst, XMMRegister src) {
1849 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1850 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_128bit;
1851 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
1852 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
1853 emit_int16((unsigned char)0xE6, (unsigned char)(0xC0 | encode));
1854 }
1855
1856 void Assembler::pabsb(XMMRegister dst, XMMRegister src) {
1857 assert(VM_Version::supports_ssse3(), "");
1858 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
1859 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1860 emit_int16(0x1C, (unsigned char)(0xC0 | encode));
1861 }
1862
1863 void Assembler::pabsw(XMMRegister dst, XMMRegister src) {
1864 assert(VM_Version::supports_ssse3(), "");
1865 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
1866 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1867 emit_int16(0x1D, (unsigned char)(0xC0 | encode));
1868 }
1869
1870 void Assembler::pabsd(XMMRegister dst, XMMRegister src) {
1871 assert(VM_Version::supports_ssse3(), "");
1872 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
1873 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1874 emit_int16(0x1E, (unsigned char)(0xC0 | encode));
1875 }
1876
1877 void Assembler::vpabsb(XMMRegister dst, XMMRegister src, int vector_len) {
1878 assert(vector_len == AVX_128bit? VM_Version::supports_avx() :
1879 vector_len == AVX_256bit? VM_Version::supports_avx2() :
1880 vector_len == AVX_512bit? VM_Version::supports_avx512bw() : 0, "");
1881 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
1882 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1883 emit_int16(0x1C, (unsigned char)(0xC0 | encode));
1884 }
1885
1886 void Assembler::vpabsw(XMMRegister dst, XMMRegister src, int vector_len) {
1887 assert(vector_len == AVX_128bit? VM_Version::supports_avx() :
1888 vector_len == AVX_256bit? VM_Version::supports_avx2() :
1889 vector_len == AVX_512bit? VM_Version::supports_avx512bw() : 0, "");
1890 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
1891 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1892 emit_int16(0x1D, (unsigned char)(0xC0 | encode));
1893 }
1894
1895 void Assembler::vpabsd(XMMRegister dst, XMMRegister src, int vector_len) {
1896 assert(vector_len == AVX_128bit? VM_Version::supports_avx() :
1897 vector_len == AVX_256bit? VM_Version::supports_avx2() :
1898 vector_len == AVX_512bit? VM_Version::supports_evex() : 0, "");
1899 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
1900 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1901 emit_int16(0x1E, (unsigned char)(0xC0 | encode));
1902 }
1903
1904 void Assembler::evpabsq(XMMRegister dst, XMMRegister src, int vector_len) {
1905 assert(UseAVX > 2, "");
1906 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
1907 attributes.set_is_evex_instruction();
1908 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1909 emit_int16(0x1F, (unsigned char)(0xC0 | encode));
1910 }
1911
1912 void Assembler::decl(Address dst) {
1913 // Don't use it directly. Use MacroAssembler::decrement() instead.
1914 InstructionMark im(this);
1915 prefix(dst);
1916 emit_int8((unsigned char)0xFF);
1917 emit_operand(rcx, dst);
1918 }
1919
1920 void Assembler::divsd(XMMRegister dst, Address src) {
1921 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1922 InstructionMark im(this);
1923 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1924 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
1925 attributes.set_rex_vex_w_reverted();
1926 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
1927 emit_int8(0x5E);
1928 emit_operand(dst, src);
1929 }
1930
1931 void Assembler::divsd(XMMRegister dst, XMMRegister src) {
1932 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1933 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1934 attributes.set_rex_vex_w_reverted();
1935 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
1936 emit_int16(0x5E, (unsigned char)(0xC0 | encode));
1937 }
1938
1939 void Assembler::divss(XMMRegister dst, Address src) {
1940 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1941 InstructionMark im(this);
1942 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1943 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
1944 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1945 emit_int8(0x5E);
1946 emit_operand(dst, src);
1947 }
1948
1949 void Assembler::divss(XMMRegister dst, XMMRegister src) {
1950 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1951 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1952 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1953 emit_int16(0x5E, (unsigned char)(0xC0 | encode));
1954 }
1955
1956 void Assembler::emms() {
1957 NOT_LP64(assert(VM_Version::supports_mmx(), ""));
1958 emit_int16(0x0F, 0x77);
1959 }
1960
1961 void Assembler::hlt() {
1962 emit_int8((unsigned char)0xF4);
1963 }
1964
1965 void Assembler::idivl(Register src) {
1966 int encode = prefix_and_encode(src->encoding());
1967 emit_int16((unsigned char)0xF7, (unsigned char)(0xF8 | encode));
1968 }
1969
1970 void Assembler::divl(Register src) { // Unsigned
1971 int encode = prefix_and_encode(src->encoding());
1972 emit_int16((unsigned char)0xF7, (unsigned char)(0xF0 | encode));
1973 }
1974
1975 void Assembler::imull(Register src) {
1976 int encode = prefix_and_encode(src->encoding());
1977 emit_int16((unsigned char)0xF7, (unsigned char)(0xE8 | encode));
1978 }
1979
1980 void Assembler::imull(Register dst, Register src) {
1981 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1982 emit_int24(0x0F, (unsigned char)0xAF, (unsigned char)(0xC0 | encode));
1983 }
1984
1985
1986 void Assembler::imull(Register dst, Register src, int value) {
1987 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1988 if (is8bit(value)) {
1989 emit_int24(0x6B, (unsigned char)(0xC0 | encode), value & 0xFF);
1990 } else {
1991 emit_int16(0x69, (unsigned char)(0xC0 | encode));
1992 emit_int32(value);
1993 }
1994 }
1995
1996 void Assembler::imull(Register dst, Address src) {
1997 InstructionMark im(this);
1998 prefix(src, dst);
1999 emit_int16(0x0F, (unsigned char) 0xAF);
2000 emit_operand(dst, src);
2001 }
2002
2003
2004 void Assembler::incl(Address dst) {
2005 // Don't use it directly. Use MacroAssembler::increment() instead.
2006 InstructionMark im(this);
2007 prefix(dst);
2008 emit_int8((unsigned char)0xFF);
2009 emit_operand(rax, dst);
2010 }
2011
2012 void Assembler::jcc(Condition cc, Label& L, bool maybe_short) {
2013 InstructionMark im(this);
2014 assert((0 <= cc) && (cc < 16), "illegal cc");
2015 if (L.is_bound()) {
2016 address dst = target(L);
2017 assert(dst != NULL, "jcc most probably wrong");
2018
2019 const int short_size = 2;
2020 const int long_size = 6;
2021 intptr_t offs = (intptr_t)dst - (intptr_t)pc();
2022 if (maybe_short && is8bit(offs - short_size)) {
2023 // 0111 tttn #8-bit disp
2024 emit_int16(0x70 | cc, (offs - short_size) & 0xFF);
2025 } else {
2026 // 0000 1111 1000 tttn #32-bit disp
2027 assert(is_simm32(offs - long_size),
2028 "must be 32bit offset (call4)");
2029 emit_int16(0x0F, (unsigned char)(0x80 | cc));
2030 emit_int32(offs - long_size);
2031 }
2032 } else {
2033 // Note: could eliminate cond. jumps to this jump if condition
2034 // is the same however, seems to be rather unlikely case.
2035 // Note: use jccb() if label to be bound is very close to get
2036 // an 8-bit displacement
2037 L.add_patch_at(code(), locator());
2038 emit_int16(0x0F, (unsigned char)(0x80 | cc));
2039 emit_int32(0);
2040 }
2041 }
2042
2043 void Assembler::jccb_0(Condition cc, Label& L, const char* file, int line) {
2044 if (L.is_bound()) {
2045 const int short_size = 2;
2046 address entry = target(L);
2047 #ifdef ASSERT
2048 intptr_t dist = (intptr_t)entry - ((intptr_t)pc() + short_size);
2049 intptr_t delta = short_branch_delta();
2050 if (delta != 0) {
2051 dist += (dist < 0 ? (-delta) :delta);
2052 }
2053 assert(is8bit(dist), "Dispacement too large for a short jmp at %s:%d", file, line);
2054 #endif
2055 intptr_t offs = (intptr_t)entry - (intptr_t)pc();
2056 // 0111 tttn #8-bit disp
2057 emit_int16(0x70 | cc, (offs - short_size) & 0xFF);
2058 } else {
2059 InstructionMark im(this);
2060 L.add_patch_at(code(), locator(), file, line);
2061 emit_int16(0x70 | cc, 0);
2062 }
2063 }
2064
2065 void Assembler::jmp(Address adr) {
2066 InstructionMark im(this);
2067 prefix(adr);
2068 emit_int8((unsigned char)0xFF);
2069 emit_operand(rsp, adr);
2070 }
2071
2072 void Assembler::jmp(Label& L, bool maybe_short) {
2073 if (L.is_bound()) {
2074 address entry = target(L);
2075 assert(entry != NULL, "jmp most probably wrong");
2076 InstructionMark im(this);
2077 const int short_size = 2;
2078 const int long_size = 5;
2079 intptr_t offs = entry - pc();
2080 if (maybe_short && is8bit(offs - short_size)) {
2081 emit_int16((unsigned char)0xEB, (offs - short_size) & 0xFF);
2082 } else {
2083 emit_int8((unsigned char)0xE9);
2084 emit_int32(offs - long_size);
2085 }
2086 } else {
2087 // By default, forward jumps are always 32-bit displacements, since
2088 // we can't yet know where the label will be bound. If you're sure that
2089 // the forward jump will not run beyond 256 bytes, use jmpb to
2090 // force an 8-bit displacement.
2091 InstructionMark im(this);
2092 L.add_patch_at(code(), locator());
2093 emit_int8((unsigned char)0xE9);
2094 emit_int32(0);
2095 }
2096 }
2097
2098 void Assembler::jmp(Register entry) {
2099 int encode = prefix_and_encode(entry->encoding());
2100 emit_int16((unsigned char)0xFF, (unsigned char)(0xE0 | encode));
2101 }
2102
2103 void Assembler::jmp_literal(address dest, RelocationHolder const& rspec) {
2104 InstructionMark im(this);
2105 emit_int8((unsigned char)0xE9);
2106 assert(dest != NULL, "must have a target");
2107 intptr_t disp = dest - (pc() + sizeof(int32_t));
2108 assert(is_simm32(disp), "must be 32bit offset (jmp)");
2109 emit_data(disp, rspec.reloc(), call32_operand);
2110 }
2111
2112 void Assembler::jmpb_0(Label& L, const char* file, int line) {
2113 if (L.is_bound()) {
2114 const int short_size = 2;
2115 address entry = target(L);
2116 assert(entry != NULL, "jmp most probably wrong");
2117 #ifdef ASSERT
2118 intptr_t dist = (intptr_t)entry - ((intptr_t)pc() + short_size);
2119 intptr_t delta = short_branch_delta();
2120 if (delta != 0) {
2121 dist += (dist < 0 ? (-delta) :delta);
2122 }
2123 assert(is8bit(dist), "Dispacement too large for a short jmp at %s:%d", file, line);
2124 #endif
2125 intptr_t offs = entry - pc();
2126 emit_int16((unsigned char)0xEB, (offs - short_size) & 0xFF);
2127 } else {
2128 InstructionMark im(this);
2129 L.add_patch_at(code(), locator(), file, line);
2130 emit_int16((unsigned char)0xEB, 0);
2131 }
2132 }
2133
2134 void Assembler::ldmxcsr( Address src) {
2135 if (UseAVX > 0 ) {
2136 InstructionMark im(this);
2137 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2138 vex_prefix(src, 0, 0, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2139 emit_int8((unsigned char)0xAE);
2140 emit_operand(as_Register(2), src);
2141 } else {
2142 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2143 InstructionMark im(this);
2144 prefix(src);
2145 emit_int16(0x0F, (unsigned char)0xAE);
2146 emit_operand(as_Register(2), src);
2147 }
2148 }
2149
2150 void Assembler::leal(Register dst, Address src) {
2151 InstructionMark im(this);
2152 #ifdef _LP64
2153 emit_int8(0x67); // addr32
2154 prefix(src, dst);
2155 #endif // LP64
2156 emit_int8((unsigned char)0x8D);
2157 emit_operand(dst, src);
2158 }
2159
2160 void Assembler::lfence() {
2161 emit_int24(0x0F, (unsigned char)0xAE, (unsigned char)0xE8);
2162 }
2163
2164 void Assembler::lock() {
2165 emit_int8((unsigned char)0xF0);
2166 }
2167
2168 void Assembler::lzcntl(Register dst, Register src) {
2169 assert(VM_Version::supports_lzcnt(), "encoding is treated as BSR");
2170 emit_int8((unsigned char)0xF3);
2171 int encode = prefix_and_encode(dst->encoding(), src->encoding());
2172 emit_int24(0x0F, (unsigned char)0xBD, (unsigned char)(0xC0 | encode));
2173 }
2174
2175 // Emit mfence instruction
2176 void Assembler::mfence() {
2177 NOT_LP64(assert(VM_Version::supports_sse2(), "unsupported");)
2178 emit_int24(0x0F, (unsigned char)0xAE, (unsigned char)0xF0);
2179 }
2180
2181 // Emit sfence instruction
2182 void Assembler::sfence() {
2183 NOT_LP64(assert(VM_Version::supports_sse2(), "unsupported");)
2184 emit_int24(0x0F, (unsigned char)0xAE, (unsigned char)0xF8);
2185 }
2186
2187 void Assembler::mov(Register dst, Register src) {
2188 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src));
2189 }
2190
2191 void Assembler::movapd(XMMRegister dst, XMMRegister src) {
2192 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2193 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_128bit;
2194 InstructionAttr attributes(vector_len, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
2195 attributes.set_rex_vex_w_reverted();
2196 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2197 emit_int16(0x28, (unsigned char)(0xC0 | encode));
2198 }
2199
2200 void Assembler::movaps(XMMRegister dst, XMMRegister src) {
2201 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2202 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_128bit;
2203 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
2204 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2205 emit_int16(0x28, (unsigned char)(0xC0 | encode));
2206 }
2207
2208 void Assembler::movlhps(XMMRegister dst, XMMRegister src) {
2209 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2210 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
2211 int encode = simd_prefix_and_encode(dst, src, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2212 emit_int16(0x16, (unsigned char)(0xC0 | encode));
2213 }
2214
2215 void Assembler::movb(Register dst, Address src) {
2216 NOT_LP64(assert(dst->has_byte_register(), "must have byte register"));
2217 InstructionMark im(this);
2218 prefix(src, dst, true);
2219 emit_int8((unsigned char)0x8A);
2220 emit_operand(dst, src);
2221 }
2222
2223 void Assembler::movddup(XMMRegister dst, XMMRegister src) {
2224 NOT_LP64(assert(VM_Version::supports_sse3(), ""));
2225 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_128bit;
2226 InstructionAttr attributes(vector_len, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
2227 attributes.set_rex_vex_w_reverted();
2228 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2229 emit_int16(0x12, 0xC0 | encode);
2230 }
2231
2232 void Assembler::kmovbl(KRegister dst, Register src) {
2233 assert(VM_Version::supports_avx512dq(), "");
2234 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2235 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2236 emit_int16((unsigned char)0x92, (unsigned char)(0xC0 | encode));
2237 }
2238
2239 void Assembler::kmovbl(Register dst, KRegister src) {
2240 assert(VM_Version::supports_avx512dq(), "");
2241 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2242 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2243 emit_int16((unsigned char)0x93, (unsigned char)(0xC0 | encode));
2244 }
2245
2246 void Assembler::kmovwl(KRegister dst, Register src) {
2247 assert(VM_Version::supports_evex(), "");
2248 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2249 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2250 emit_int16((unsigned char)0x92, (unsigned char)(0xC0 | encode));
2251 }
2252
2253 void Assembler::kmovwl(Register dst, KRegister src) {
2254 assert(VM_Version::supports_evex(), "");
2255 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2256 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2257 emit_int16((unsigned char)0x93, (unsigned char)(0xC0 | encode));
2258 }
2259
2260 void Assembler::kmovwl(KRegister dst, Address src) {
2261 assert(VM_Version::supports_evex(), "");
2262 InstructionMark im(this);
2263 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2264 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2265 emit_int8((unsigned char)0x90);
2266 emit_operand((Register)dst, src);
2267 }
2268
2269 void Assembler::kmovdl(KRegister dst, Register src) {
2270 assert(VM_Version::supports_avx512bw(), "");
2271 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2272 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2273 emit_int16((unsigned char)0x92, (unsigned char)(0xC0 | encode));
2274 }
2275
2276 void Assembler::kmovdl(Register dst, KRegister src) {
2277 assert(VM_Version::supports_avx512bw(), "");
2278 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2279 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2280 emit_int16((unsigned char)0x93, (unsigned char)(0xC0 | encode));
2281 }
2282
2283 void Assembler::kmovql(KRegister dst, KRegister src) {
2284 assert(VM_Version::supports_avx512bw(), "");
2285 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2286 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2287 emit_int16((unsigned char)0x90, (unsigned char)(0xC0 | encode));
2288 }
2289
2290 void Assembler::kmovql(KRegister dst, Address src) {
2291 assert(VM_Version::supports_avx512bw(), "");
2292 InstructionMark im(this);
2293 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2294 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2295 emit_int8((unsigned char)0x90);
2296 emit_operand((Register)dst, src);
2297 }
2298
2299 void Assembler::kmovql(Address dst, KRegister src) {
2300 assert(VM_Version::supports_avx512bw(), "");
2301 InstructionMark im(this);
2302 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2303 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2304 emit_int8((unsigned char)0x90);
2305 emit_operand((Register)src, dst);
2306 }
2307
2308 void Assembler::kmovql(KRegister dst, Register src) {
2309 assert(VM_Version::supports_avx512bw(), "");
2310 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2311 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2312 emit_int16((unsigned char)0x92, (unsigned char)(0xC0 | encode));
2313 }
2314
2315 void Assembler::kmovql(Register dst, KRegister src) {
2316 assert(VM_Version::supports_avx512bw(), "");
2317 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2318 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2319 emit_int16((unsigned char)0x93, (unsigned char)(0xC0 | encode));
2320 }
2321
2322 void Assembler::knotwl(KRegister dst, KRegister src) {
2323 assert(VM_Version::supports_evex(), "");
2324 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2325 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2326 emit_int16((unsigned char)0x44, (unsigned char)(0xC0 | encode));
2327 }
2328
2329 // This instruction produces ZF or CF flags
2330 void Assembler::kortestbl(KRegister src1, KRegister src2) {
2331 assert(VM_Version::supports_avx512dq(), "");
2332 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2333 int encode = vex_prefix_and_encode(src1->encoding(), 0, src2->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2334 emit_int16((unsigned char)0x98, (unsigned char)(0xC0 | encode));
2335 }
2336
2337 // This instruction produces ZF or CF flags
2338 void Assembler::kortestwl(KRegister src1, KRegister src2) {
2339 assert(VM_Version::supports_evex(), "");
2340 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2341 int encode = vex_prefix_and_encode(src1->encoding(), 0, src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2342 emit_int16((unsigned char)0x98, (unsigned char)(0xC0 | encode));
2343 }
2344
2345 // This instruction produces ZF or CF flags
2346 void Assembler::kortestdl(KRegister src1, KRegister src2) {
2347 assert(VM_Version::supports_avx512bw(), "");
2348 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2349 int encode = vex_prefix_and_encode(src1->encoding(), 0, src2->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2350 emit_int16((unsigned char)0x98, (unsigned char)(0xC0 | encode));
2351 }
2352
2353 // This instruction produces ZF or CF flags
2354 void Assembler::kortestql(KRegister src1, KRegister src2) {
2355 assert(VM_Version::supports_avx512bw(), "");
2356 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2357 int encode = vex_prefix_and_encode(src1->encoding(), 0, src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2358 emit_int16((unsigned char)0x98, (unsigned char)(0xC0 | encode));
2359 }
2360
2361 // This instruction produces ZF or CF flags
2362 void Assembler::ktestql(KRegister src1, KRegister src2) {
2363 assert(VM_Version::supports_avx512bw(), "");
2364 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2365 int encode = vex_prefix_and_encode(src1->encoding(), 0, src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2366 emit_int16((unsigned char)0x99, (unsigned char)(0xC0 | encode));
2367 }
2368
2369 void Assembler::ktestq(KRegister src1, KRegister src2) {
2370 assert(VM_Version::supports_avx512bw(), "");
2371 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2372 int encode = vex_prefix_and_encode(src1->encoding(), 0, src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2373 emit_int16((unsigned char)0x99, (unsigned char)(0xC0 | encode));
2374 }
2375
2376 void Assembler::ktestd(KRegister src1, KRegister src2) {
2377 assert(VM_Version::supports_avx512bw(), "");
2378 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2379 int encode = vex_prefix_and_encode(src1->encoding(), 0, src2->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2380 emit_int16((unsigned char)0x99, (unsigned char)(0xC0 | encode));
2381 }
2382
2383 void Assembler::movb(Address dst, int imm8) {
2384 InstructionMark im(this);
2385 prefix(dst);
2386 emit_int8((unsigned char)0xC6);
2387 emit_operand(rax, dst, 1);
2388 emit_int8(imm8);
2389 }
2390
2391
2392 void Assembler::movb(Address dst, Register src) {
2393 assert(src->has_byte_register(), "must have byte register");
2394 InstructionMark im(this);
2395 prefix(dst, src, true);
2396 emit_int8((unsigned char)0x88);
2397 emit_operand(src, dst);
2398 }
2399
2400 void Assembler::movdl(XMMRegister dst, Register src) {
2401 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2402 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2403 int encode = simd_prefix_and_encode(dst, xnoreg, as_XMMRegister(src->encoding()), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2404 emit_int16(0x6E, (unsigned char)(0xC0 | encode));
2405 }
2406
2407 void Assembler::movdl(Register dst, XMMRegister src) {
2408 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2409 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2410 // swap src/dst to get correct prefix
2411 int encode = simd_prefix_and_encode(src, xnoreg, as_XMMRegister(dst->encoding()), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2412 emit_int16(0x7E, (unsigned char)(0xC0 | encode));
2413 }
2414
2415 void Assembler::movdl(XMMRegister dst, Address src) {
2416 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2417 InstructionMark im(this);
2418 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2419 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
2420 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2421 emit_int8(0x6E);
2422 emit_operand(dst, src);
2423 }
2424
2425 void Assembler::movdl(Address dst, XMMRegister src) {
2426 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2427 InstructionMark im(this);
2428 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2429 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
2430 simd_prefix(src, xnoreg, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2431 emit_int8(0x7E);
2432 emit_operand(src, dst);
2433 }
2434
2435 void Assembler::movdqa(XMMRegister dst, XMMRegister src) {
2436 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2437 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
2438 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2439 emit_int16(0x6F, (unsigned char)(0xC0 | encode));
2440 }
2441
2442 void Assembler::movdqa(XMMRegister dst, Address src) {
2443 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2444 InstructionMark im(this);
2445 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
2446 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2447 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2448 emit_int8(0x6F);
2449 emit_operand(dst, src);
2450 }
2451
2452 void Assembler::movdqu(XMMRegister dst, Address src) {
2453 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2454 InstructionMark im(this);
2455 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
2456 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2457 simd_prefix(dst, xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2458 emit_int8(0x6F);
2459 emit_operand(dst, src);
2460 }
2461
2462 void Assembler::movdqu(XMMRegister dst, XMMRegister src) {
2463 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2464 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
2465 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2466 emit_int16(0x6F, (unsigned char)(0xC0 | encode));
2467 }
2468
2469 void Assembler::movdqu(Address dst, XMMRegister src) {
2470 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2471 InstructionMark im(this);
2472 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
2473 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2474 attributes.reset_is_clear_context();
2475 simd_prefix(src, xnoreg, dst, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2476 emit_int8(0x7F);
2477 emit_operand(src, dst);
2478 }
2479
2480 // Move Unaligned 256bit Vector
2481 void Assembler::vmovdqu(XMMRegister dst, XMMRegister src) {
2482 assert(UseAVX > 0, "");
2483 InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
2484 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2485 emit_int16(0x6F, (unsigned char)(0xC0 | encode));
2486 }
2487
2488 void Assembler::vmovdqu(XMMRegister dst, Address src) {
2489 assert(UseAVX > 0, "");
2490 InstructionMark im(this);
2491 InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
2492 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2493 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2494 emit_int8(0x6F);
2495 emit_operand(dst, src);
2496 }
2497
2498 void Assembler::vmovdqu(Address dst, XMMRegister src) {
2499 assert(UseAVX > 0, "");
2500 InstructionMark im(this);
2501 InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
2502 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2503 attributes.reset_is_clear_context();
2504 // swap src<->dst for encoding
2505 assert(src != xnoreg, "sanity");
2506 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2507 emit_int8(0x7F);
2508 emit_operand(src, dst);
2509 }
2510
2511 // Move Unaligned EVEX enabled Vector (programmable : 8,16,32,64)
2512 void Assembler::evmovdqub(XMMRegister dst, XMMRegister src, int vector_len) {
2513 assert(VM_Version::supports_evex(), "");
2514 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
2515 attributes.set_is_evex_instruction();
2516 int prefix = (_legacy_mode_bw) ? VEX_SIMD_F2 : VEX_SIMD_F3;
2517 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), (Assembler::VexSimdPrefix)prefix, VEX_OPCODE_0F, &attributes);
2518 emit_int16(0x6F, (unsigned char)(0xC0 | encode));
2519 }
2520
2521 void Assembler::evmovdqub(XMMRegister dst, Address src, int vector_len) {
2522 assert(VM_Version::supports_evex(), "");
2523 InstructionMark im(this);
2524 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
2525 int prefix = (_legacy_mode_bw) ? VEX_SIMD_F2 : VEX_SIMD_F3;
2526 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2527 attributes.set_is_evex_instruction();
2528 vex_prefix(src, 0, dst->encoding(), (Assembler::VexSimdPrefix)prefix, VEX_OPCODE_0F, &attributes);
2529 emit_int8(0x6F);
2530 emit_operand(dst, src);
2531 }
2532
2533 void Assembler::evmovdqub(Address dst, XMMRegister src, int vector_len) {
2534 assert(VM_Version::supports_evex(), "");
2535 assert(src != xnoreg, "sanity");
2536 InstructionMark im(this);
2537 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
2538 int prefix = (_legacy_mode_bw) ? VEX_SIMD_F2 : VEX_SIMD_F3;
2594
2595 void Assembler::evmovdquw(Address dst, KRegister mask, XMMRegister src, int vector_len) {
2596 assert(VM_Version::supports_avx512vlbw(), "");
2597 assert(src != xnoreg, "sanity");
2598 InstructionMark im(this);
2599 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2600 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2601 attributes.reset_is_clear_context();
2602 attributes.set_embedded_opmask_register_specifier(mask);
2603 attributes.set_is_evex_instruction();
2604 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2605 emit_int8(0x7F);
2606 emit_operand(src, dst);
2607 }
2608
2609 void Assembler::evmovdqul(XMMRegister dst, XMMRegister src, int vector_len) {
2610 assert(VM_Version::supports_evex(), "");
2611 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
2612 attributes.set_is_evex_instruction();
2613 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2614 emit_int16(0x6F, (unsigned char)(0xC0 | encode));
2615 }
2616
2617 void Assembler::evmovdqul(XMMRegister dst, Address src, int vector_len) {
2618 assert(VM_Version::supports_evex(), "");
2619 InstructionMark im(this);
2620 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true , /* uses_vl */ true);
2621 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2622 attributes.set_is_evex_instruction();
2623 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2624 emit_int8(0x6F);
2625 emit_operand(dst, src);
2626 }
2627
2628 void Assembler::evmovdqul(Address dst, XMMRegister src, int vector_len) {
2629 assert(VM_Version::supports_evex(), "");
2630 assert(src != xnoreg, "sanity");
2631 InstructionMark im(this);
2632 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
2633 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2634 attributes.reset_is_clear_context();
2635 attributes.set_is_evex_instruction();
2636 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2637 emit_int8(0x7F);
2638 emit_operand(src, dst);
2639 }
2640
2641 void Assembler::evmovdquq(XMMRegister dst, XMMRegister src, int vector_len) {
2642 assert(VM_Version::supports_evex(), "");
2643 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
2644 attributes.set_is_evex_instruction();
2645 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2646 emit_int16(0x6F, (unsigned char)(0xC0 | encode));
2647 }
2648
2649 void Assembler::evmovdquq(XMMRegister dst, Address src, int vector_len) {
2650 assert(VM_Version::supports_evex(), "");
2651 InstructionMark im(this);
2652 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
2653 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2654 attributes.set_is_evex_instruction();
2655 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2656 emit_int8(0x6F);
2657 emit_operand(dst, src);
2658 }
2659
2660 void Assembler::evmovdquq(Address dst, XMMRegister src, int vector_len) {
2661 assert(VM_Version::supports_evex(), "");
2662 assert(src != xnoreg, "sanity");
2663 InstructionMark im(this);
2664 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
2665 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2666 attributes.reset_is_clear_context();
2667 attributes.set_is_evex_instruction();
2668 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2669 emit_int8(0x7F);
2670 emit_operand(src, dst);
2671 }
2672
2673 // Uses zero extension on 64bit
2674
2675 void Assembler::movl(Register dst, int32_t imm32) {
2676 int encode = prefix_and_encode(dst->encoding());
2677 emit_int8((unsigned char)(0xB8 | encode));
2678 emit_int32(imm32);
2679 }
2680
2681 void Assembler::movl(Register dst, Register src) {
2682 int encode = prefix_and_encode(dst->encoding(), src->encoding());
2683 emit_int16((unsigned char)0x8B, (unsigned char)(0xC0 | encode));
2684 }
2685
2686 void Assembler::movl(Register dst, Address src) {
2687 InstructionMark im(this);
2688 prefix(src, dst);
2689 emit_int8((unsigned char)0x8B);
2690 emit_operand(dst, src);
2691 }
2692
2693 void Assembler::movl(Address dst, int32_t imm32) {
2694 InstructionMark im(this);
2695 prefix(dst);
2696 emit_int8((unsigned char)0xC7);
2697 emit_operand(rax, dst, 4);
2698 emit_int32(imm32);
2699 }
2700
2701 void Assembler::movl(Address dst, Register src) {
2702 InstructionMark im(this);
2703 prefix(dst, src);
2704 emit_int8((unsigned char)0x89);
2705 emit_operand(src, dst);
2706 }
2707
2708 // New cpus require to use movsd and movss to avoid partial register stall
2709 // when loading from memory. But for old Opteron use movlpd instead of movsd.
2710 // The selection is done in MacroAssembler::movdbl() and movflt().
2711 void Assembler::movlpd(XMMRegister dst, Address src) {
2712 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2713 InstructionMark im(this);
2714 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
2715 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
2716 attributes.set_rex_vex_w_reverted();
2717 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2718 emit_int8(0x12);
2719 emit_operand(dst, src);
2720 }
2721
2722 void Assembler::movq( MMXRegister dst, Address src ) {
2723 assert( VM_Version::supports_mmx(), "" );
2724 emit_int16(0x0F, 0x6F);
2725 emit_operand(dst, src);
2726 }
2727
2728 void Assembler::movq( Address dst, MMXRegister src ) {
2729 assert( VM_Version::supports_mmx(), "" );
2730 emit_int16(0x0F, 0x7F);
2731 // workaround gcc (3.2.1-7a) bug
2732 // In that version of gcc with only an emit_operand(MMX, Address)
2733 // gcc will tail jump and try and reverse the parameters completely
2734 // obliterating dst in the process. By having a version available
2735 // that doesn't need to swap the args at the tail jump the bug is
2736 // avoided.
2737 emit_operand(dst, src);
2738 }
2739
2740 void Assembler::movq(XMMRegister dst, Address src) {
2741 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2742 InstructionMark im(this);
2743 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2744 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
2745 attributes.set_rex_vex_w_reverted();
2746 simd_prefix(dst, xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2747 emit_int8(0x7E);
2748 emit_operand(dst, src);
2749 }
2750
2751 void Assembler::movq(Address dst, XMMRegister src) {
2752 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2753 InstructionMark im(this);
2754 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2755 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
2756 attributes.set_rex_vex_w_reverted();
2757 simd_prefix(src, xnoreg, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2758 emit_int8((unsigned char)0xD6);
2759 emit_operand(src, dst);
2760 }
2761
2762 void Assembler::movsbl(Register dst, Address src) { // movsxb
2763 InstructionMark im(this);
2764 prefix(src, dst);
2765 emit_int16(0x0F, (unsigned char)0xBE);
2766 emit_operand(dst, src);
2767 }
2768
2769 void Assembler::movsbl(Register dst, Register src) { // movsxb
2770 NOT_LP64(assert(src->has_byte_register(), "must have byte register"));
2771 int encode = prefix_and_encode(dst->encoding(), false, src->encoding(), true);
2772 emit_int24(0x0F, (unsigned char)0xBE, (unsigned char)(0xC0 | encode));
2773 }
2774
2775 void Assembler::movsd(XMMRegister dst, XMMRegister src) {
2776 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2777 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2778 attributes.set_rex_vex_w_reverted();
2779 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2780 emit_int16(0x10, (unsigned char)(0xC0 | encode));
2781 }
2782
2783 void Assembler::movsd(XMMRegister dst, Address src) {
2784 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2785 InstructionMark im(this);
2786 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2787 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
2788 attributes.set_rex_vex_w_reverted();
2789 simd_prefix(dst, xnoreg, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2790 emit_int8(0x10);
2791 emit_operand(dst, src);
2792 }
2793
2794 void Assembler::movsd(Address dst, XMMRegister src) {
2795 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2796 InstructionMark im(this);
2797 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2798 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
2799 attributes.reset_is_clear_context();
2800 attributes.set_rex_vex_w_reverted();
2801 simd_prefix(src, xnoreg, dst, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2802 emit_int8(0x11);
2803 emit_operand(src, dst);
2804 }
2805
2806 void Assembler::movss(XMMRegister dst, XMMRegister src) {
2807 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2808 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2809 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2810 emit_int16(0x10, (unsigned char)(0xC0 | encode));
2811 }
2812
2813 void Assembler::movss(XMMRegister dst, Address src) {
2814 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2815 InstructionMark im(this);
2816 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2817 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
2818 simd_prefix(dst, xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2819 emit_int8(0x10);
2820 emit_operand(dst, src);
2821 }
2822
2823 void Assembler::movss(Address dst, XMMRegister src) {
2824 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2825 InstructionMark im(this);
2826 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2827 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
2828 attributes.reset_is_clear_context();
2829 simd_prefix(src, xnoreg, dst, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2830 emit_int8(0x11);
2831 emit_operand(src, dst);
2832 }
2833
2834 void Assembler::movswl(Register dst, Address src) { // movsxw
2835 InstructionMark im(this);
2836 prefix(src, dst);
2837 emit_int16(0x0F, (unsigned char)0xBF);
2838 emit_operand(dst, src);
2839 }
2840
2841 void Assembler::movswl(Register dst, Register src) { // movsxw
2842 int encode = prefix_and_encode(dst->encoding(), src->encoding());
2843 emit_int24(0x0F, (unsigned char)0xBF, (unsigned char)(0xC0 | encode));
2844 }
2845
2846 void Assembler::movw(Address dst, int imm16) {
2847 InstructionMark im(this);
2848
2849 emit_int8(0x66); // switch to 16-bit mode
2850 prefix(dst);
2851 emit_int8((unsigned char)0xC7);
2852 emit_operand(rax, dst, 2);
2853 emit_int16(imm16);
2854 }
2855
2856 void Assembler::movw(Register dst, Address src) {
2857 InstructionMark im(this);
2858 emit_int8(0x66);
2859 prefix(src, dst);
2860 emit_int8((unsigned char)0x8B);
2861 emit_operand(dst, src);
2862 }
2863
2864 void Assembler::movw(Address dst, Register src) {
2865 InstructionMark im(this);
2866 emit_int8(0x66);
2867 prefix(dst, src);
2868 emit_int8((unsigned char)0x89);
2869 emit_operand(src, dst);
2870 }
2871
2872 void Assembler::movzbl(Register dst, Address src) { // movzxb
2873 InstructionMark im(this);
2874 prefix(src, dst);
2875 emit_int16(0x0F, (unsigned char)0xB6);
2876 emit_operand(dst, src);
2877 }
2878
2879 void Assembler::movzbl(Register dst, Register src) { // movzxb
2880 NOT_LP64(assert(src->has_byte_register(), "must have byte register"));
2881 int encode = prefix_and_encode(dst->encoding(), false, src->encoding(), true);
2882 emit_int24(0x0F, (unsigned char)0xB6, 0xC0 | encode);
2883 }
2884
2885 void Assembler::movzwl(Register dst, Address src) { // movzxw
2886 InstructionMark im(this);
2887 prefix(src, dst);
2888 emit_int16(0x0F, (unsigned char)0xB7);
2889 emit_operand(dst, src);
2890 }
2891
2892 void Assembler::movzwl(Register dst, Register src) { // movzxw
2893 int encode = prefix_and_encode(dst->encoding(), src->encoding());
2894 emit_int24(0x0F, (unsigned char)0xB7, 0xC0 | encode);
2895 }
2896
2897 void Assembler::mull(Address src) {
2898 InstructionMark im(this);
2899 prefix(src);
2900 emit_int8((unsigned char)0xF7);
2901 emit_operand(rsp, src);
2902 }
2903
2904 void Assembler::mull(Register src) {
2905 int encode = prefix_and_encode(src->encoding());
2906 emit_int16((unsigned char)0xF7, (unsigned char)(0xE0 | encode));
2907 }
2908
2909 void Assembler::mulsd(XMMRegister dst, Address src) {
2910 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2911 InstructionMark im(this);
2912 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2913 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
2914 attributes.set_rex_vex_w_reverted();
2915 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2916 emit_int8(0x59);
2917 emit_operand(dst, src);
2918 }
2919
2920 void Assembler::mulsd(XMMRegister dst, XMMRegister src) {
2921 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2922 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2923 attributes.set_rex_vex_w_reverted();
2924 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2925 emit_int16(0x59, (unsigned char)(0xC0 | encode));
2926 }
2927
2928 void Assembler::mulss(XMMRegister dst, Address src) {
2929 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2930 InstructionMark im(this);
2931 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2932 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
2933 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2934 emit_int8(0x59);
2935 emit_operand(dst, src);
2936 }
2937
2938 void Assembler::mulss(XMMRegister dst, XMMRegister src) {
2939 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2940 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2941 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2942 emit_int16(0x59, (unsigned char)(0xC0 | encode));
2943 }
2944
2945 void Assembler::negl(Register dst) {
2946 int encode = prefix_and_encode(dst->encoding());
2947 emit_int16((unsigned char)0xF7, (unsigned char)(0xD8 | encode));
2948 }
2949
2950 void Assembler::nop(int i) {
2951 #ifdef ASSERT
2952 assert(i > 0, " ");
2953 // The fancy nops aren't currently recognized by debuggers making it a
2954 // pain to disassemble code while debugging. If asserts are on clearly
2955 // speed is not an issue so simply use the single byte traditional nop
2956 // to do alignment.
2957
2958 for (; i > 0 ; i--) emit_int8((unsigned char)0x90);
2959 return;
2960
2961 #endif // ASSERT
2962
2963 if (UseAddressNop && VM_Version::is_intel()) {
2964 //
2965 // Using multi-bytes nops "0x0F 0x1F [address]" for Intel
2966 // 1: 0x90
2967 // 2: 0x66 0x90
2968 // 3: 0x66 0x66 0x90 (don't use "0x0F 0x1F 0x00" - need patching safe padding)
2969 // 4: 0x0F 0x1F 0x40 0x00
2970 // 5: 0x0F 0x1F 0x44 0x00 0x00
2971 // 6: 0x66 0x0F 0x1F 0x44 0x00 0x00
2972 // 7: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00
2973 // 8: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2974 // 9: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2975 // 10: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2976 // 11: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2977
2978 // The rest coding is Intel specific - don't use consecutive address nops
2979
2980 // 12: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
2981 // 13: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
2982 // 14: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
2983 // 15: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
2984
2985 while(i >= 15) {
2986 // For Intel don't generate consecutive addess nops (mix with regular nops)
2987 i -= 15;
2988 emit_int24(0x66, 0x66, 0x66);
2989 addr_nop_8();
2990 emit_int32(0x66, 0x66, 0x66, (unsigned char)0x90);
2991 }
2992 switch (i) {
2993 case 14:
2994 emit_int8(0x66); // size prefix
2995 case 13:
2996 emit_int8(0x66); // size prefix
2997 case 12:
2998 addr_nop_8();
2999 emit_int32(0x66, 0x66, 0x66, (unsigned char)0x90);
3000 break;
3001 case 11:
3002 emit_int8(0x66); // size prefix
3003 case 10:
3004 emit_int8(0x66); // size prefix
3005 case 9:
3006 emit_int8(0x66); // size prefix
3007 case 8:
3008 addr_nop_8();
3009 break;
3010 case 7:
3011 addr_nop_7();
3012 break;
3013 case 6:
3014 emit_int8(0x66); // size prefix
3015 case 5:
3016 addr_nop_5();
3017 break;
3018 case 4:
3019 addr_nop_4();
3041 // 4: 0x0F 0x1F 0x40 0x00
3042 // 5: 0x0F 0x1F 0x44 0x00 0x00
3043 // 6: 0x66 0x0F 0x1F 0x44 0x00 0x00
3044 // 7: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00
3045 // 8: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
3046 // 9: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
3047 // 10: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
3048 // 11: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
3049
3050 // The rest coding is AMD specific - use consecutive address nops
3051
3052 // 12: 0x66 0x0F 0x1F 0x44 0x00 0x00 0x66 0x0F 0x1F 0x44 0x00 0x00
3053 // 13: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 0x66 0x0F 0x1F 0x44 0x00 0x00
3054 // 14: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00
3055 // 15: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00
3056 // 16: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
3057 // Size prefixes (0x66) are added for larger sizes
3058
3059 while(i >= 22) {
3060 i -= 11;
3061 emit_int24(0x66, 0x66, 0x66);
3062 addr_nop_8();
3063 }
3064 // Generate first nop for size between 21-12
3065 switch (i) {
3066 case 21:
3067 i -= 1;
3068 emit_int8(0x66); // size prefix
3069 case 20:
3070 case 19:
3071 i -= 1;
3072 emit_int8(0x66); // size prefix
3073 case 18:
3074 case 17:
3075 i -= 1;
3076 emit_int8(0x66); // size prefix
3077 case 16:
3078 case 15:
3079 i -= 8;
3080 addr_nop_8();
3081 break;
3138 // 3: 0x66 0x66 0x90 (don't use "0x0F 0x1F 0x00" - need patching safe padding)
3139 // 4: 0x0F 0x1F 0x40 0x00
3140 // 5: 0x0F 0x1F 0x44 0x00 0x00
3141 // 6: 0x66 0x0F 0x1F 0x44 0x00 0x00
3142 // 7: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00
3143 // 8: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
3144 // 9: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
3145 // 10: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
3146 // 11: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
3147
3148 // The rest coding is ZX specific - don't use consecutive address nops
3149
3150 // 12: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
3151 // 13: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
3152 // 14: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
3153 // 15: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
3154
3155 while (i >= 15) {
3156 // For ZX don't generate consecutive addess nops (mix with regular nops)
3157 i -= 15;
3158 emit_int24(0x66, 0x66, 0x66);
3159 addr_nop_8();
3160 emit_int32(0x66, 0x66, 0x66, (unsigned char)0x90);
3161 }
3162 switch (i) {
3163 case 14:
3164 emit_int8(0x66); // size prefix
3165 case 13:
3166 emit_int8(0x66); // size prefix
3167 case 12:
3168 addr_nop_8();
3169 emit_int32(0x66, 0x66, 0x66, (unsigned char)0x90);
3170 break;
3171 case 11:
3172 emit_int8(0x66); // size prefix
3173 case 10:
3174 emit_int8(0x66); // size prefix
3175 case 9:
3176 emit_int8(0x66); // size prefix
3177 case 8:
3178 addr_nop_8();
3179 break;
3180 case 7:
3181 addr_nop_7();
3182 break;
3183 case 6:
3184 emit_int8(0x66); // size prefix
3185 case 5:
3186 addr_nop_5();
3187 break;
3188 case 4:
3189 addr_nop_4();
3199 break;
3200 default:
3201 assert(i == 0, " ");
3202 }
3203 return;
3204 }
3205
3206 // Using nops with size prefixes "0x66 0x90".
3207 // From AMD Optimization Guide:
3208 // 1: 0x90
3209 // 2: 0x66 0x90
3210 // 3: 0x66 0x66 0x90
3211 // 4: 0x66 0x66 0x66 0x90
3212 // 5: 0x66 0x66 0x90 0x66 0x90
3213 // 6: 0x66 0x66 0x90 0x66 0x66 0x90
3214 // 7: 0x66 0x66 0x66 0x90 0x66 0x66 0x90
3215 // 8: 0x66 0x66 0x66 0x90 0x66 0x66 0x66 0x90
3216 // 9: 0x66 0x66 0x90 0x66 0x66 0x90 0x66 0x66 0x90
3217 // 10: 0x66 0x66 0x66 0x90 0x66 0x66 0x90 0x66 0x66 0x90
3218 //
3219 while (i > 12) {
3220 i -= 4;
3221 emit_int32(0x66, 0x66, 0x66, (unsigned char)0x90);
3222 }
3223 // 1 - 12 nops
3224 if (i > 8) {
3225 if (i > 9) {
3226 i -= 1;
3227 emit_int8(0x66);
3228 }
3229 i -= 3;
3230 emit_int24(0x66, 0x66, (unsigned char)0x90);
3231 }
3232 // 1 - 8 nops
3233 if (i > 4) {
3234 if (i > 6) {
3235 i -= 1;
3236 emit_int8(0x66);
3237 }
3238 i -= 3;
3239 emit_int24(0x66, 0x66, (unsigned char)0x90);
3240 }
3241 switch (i) {
3242 case 4:
3243 emit_int8(0x66);
3244 case 3:
3245 emit_int8(0x66);
3246 case 2:
3247 emit_int8(0x66);
3248 case 1:
3249 emit_int8((unsigned char)0x90);
3250 break;
3251 default:
3252 assert(i == 0, " ");
3253 }
3254 }
3255
3256 void Assembler::notl(Register dst) {
3257 int encode = prefix_and_encode(dst->encoding());
3258 emit_int16((unsigned char)0xF7, (unsigned char)(0xD0 | encode));
3259 }
3260
3261 void Assembler::orl(Address dst, int32_t imm32) {
3262 InstructionMark im(this);
3263 prefix(dst);
3264 emit_arith_operand(0x81, rcx, dst, imm32);
3265 }
3266
3267 void Assembler::orl(Register dst, int32_t imm32) {
3268 prefix(dst);
3269 emit_arith(0x81, 0xC8, dst, imm32);
3270 }
3271
3272 void Assembler::orl(Register dst, Address src) {
3273 InstructionMark im(this);
3274 prefix(src, dst);
3275 emit_int8(0x0B);
3276 emit_operand(dst, src);
3277 }
3278
3294 emit_int8((unsigned char)0x80);
3295 emit_operand(rcx, dst, 1);
3296 emit_int8(imm8);
3297 }
3298
3299 void Assembler::packuswb(XMMRegister dst, Address src) {
3300 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3301 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
3302 InstructionMark im(this);
3303 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
3304 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
3305 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3306 emit_int8(0x67);
3307 emit_operand(dst, src);
3308 }
3309
3310 void Assembler::packuswb(XMMRegister dst, XMMRegister src) {
3311 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3312 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
3313 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3314 emit_int16(0x67, (unsigned char)(0xC0 | encode));
3315 }
3316
3317 void Assembler::vpackuswb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3318 assert(UseAVX > 0, "some form of AVX must be enabled");
3319 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
3320 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3321 emit_int16(0x67, (unsigned char)(0xC0 | encode));
3322 }
3323
3324 void Assembler::vpermq(XMMRegister dst, XMMRegister src, int imm8, int vector_len) {
3325 assert(VM_Version::supports_avx2(), "");
3326 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
3327 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3328 emit_int24(0x00, (unsigned char)(0xC0 | encode), imm8);
3329 }
3330
3331 void Assembler::vpermq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3332 assert(UseAVX > 2, "requires AVX512F");
3333 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
3334 attributes.set_is_evex_instruction();
3335 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3336 emit_int16((unsigned char)0x36, (unsigned char)(0xC0 | encode));
3337 }
3338
3339 void Assembler::vperm2i128(XMMRegister dst, XMMRegister nds, XMMRegister src, int imm8) {
3340 assert(VM_Version::supports_avx2(), "");
3341 InstructionAttr attributes(AVX_256bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
3342 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3343 emit_int24(0x46, 0xC0 | encode, imm8);
3344 }
3345
3346 void Assembler::vperm2f128(XMMRegister dst, XMMRegister nds, XMMRegister src, int imm8) {
3347 assert(VM_Version::supports_avx(), "");
3348 InstructionAttr attributes(AVX_256bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
3349 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3350 emit_int24(0x06, 0xC0 | encode, imm8);
3351 }
3352
3353 void Assembler::evpermi2q(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3354 assert(VM_Version::supports_evex(), "");
3355 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
3356 attributes.set_is_evex_instruction();
3357 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3358 emit_int16(0x76, (unsigned char)(0xC0 | encode));
3359 }
3360
3361
3362 void Assembler::pause() {
3363 emit_int16((unsigned char)0xF3, (unsigned char)0x90);
3364 }
3365
3366 void Assembler::ud2() {
3367 emit_int16(0x0F, 0x0B);
3368 }
3369
3370 void Assembler::pcmpestri(XMMRegister dst, Address src, int imm8) {
3371 assert(VM_Version::supports_sse4_2(), "");
3372 InstructionMark im(this);
3373 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
3374 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3375 emit_int8(0x61);
3376 emit_operand(dst, src);
3377 emit_int8(imm8);
3378 }
3379
3380 void Assembler::pcmpestri(XMMRegister dst, XMMRegister src, int imm8) {
3381 assert(VM_Version::supports_sse4_2(), "");
3382 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
3383 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3384 emit_int24(0x61, (unsigned char)(0xC0 | encode), imm8);
3385 }
3386
3387 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst
3388 void Assembler::pcmpeqb(XMMRegister dst, XMMRegister src) {
3389 assert(VM_Version::supports_sse2(), "");
3390 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
3391 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3392 emit_int16(0x74, (unsigned char)(0xC0 | encode));
3393 }
3394
3395 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst
3396 void Assembler::vpcmpeqb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3397 assert(VM_Version::supports_avx(), "");
3398 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
3399 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3400 emit_int16(0x74, (unsigned char)(0xC0 | encode));
3401 }
3402
3403 // In this context, kdst is written the mask used to process the equal components
3404 void Assembler::evpcmpeqb(KRegister kdst, XMMRegister nds, XMMRegister src, int vector_len) {
3405 assert(VM_Version::supports_avx512bw(), "");
3406 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
3407 attributes.set_is_evex_instruction();
3408 int encode = vex_prefix_and_encode(kdst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3409 emit_int16(0x74, (unsigned char)(0xC0 | encode));
3410 }
3411
3412 void Assembler::evpcmpgtb(KRegister kdst, XMMRegister nds, Address src, int vector_len) {
3413 assert(VM_Version::supports_avx512vlbw(), "");
3414 InstructionMark im(this);
3415 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
3416 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
3417 attributes.set_is_evex_instruction();
3418 int dst_enc = kdst->encoding();
3419 vex_prefix(src, nds->encoding(), dst_enc, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3420 emit_int8(0x64);
3421 emit_operand(as_Register(dst_enc), src);
3422 }
3423
3424 void Assembler::evpcmpgtb(KRegister kdst, KRegister mask, XMMRegister nds, Address src, int vector_len) {
3425 assert(VM_Version::supports_avx512vlbw(), "");
3426 InstructionMark im(this);
3427 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
3428 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
3429 attributes.reset_is_clear_context();
3430 attributes.set_embedded_opmask_register_specifier(mask);
3431 attributes.set_is_evex_instruction();
3432 int dst_enc = kdst->encoding();
3433 vex_prefix(src, nds->encoding(), dst_enc, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3434 emit_int8(0x64);
3435 emit_operand(as_Register(dst_enc), src);
3436 }
3437
3438 void Assembler::evpcmpuw(KRegister kdst, XMMRegister nds, XMMRegister src, ComparisonPredicate vcc, int vector_len) {
3439 assert(VM_Version::supports_avx512vlbw(), "");
3440 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
3441 attributes.set_is_evex_instruction();
3442 int encode = vex_prefix_and_encode(kdst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3443 emit_int24(0x3E, (unsigned char)(0xC0 | encode), vcc);
3444 }
3445
3446 void Assembler::evpcmpuw(KRegister kdst, KRegister mask, XMMRegister nds, XMMRegister src, ComparisonPredicate vcc, int vector_len) {
3447 assert(VM_Version::supports_avx512vlbw(), "");
3448 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
3449 attributes.reset_is_clear_context();
3450 attributes.set_embedded_opmask_register_specifier(mask);
3451 attributes.set_is_evex_instruction();
3452 int encode = vex_prefix_and_encode(kdst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3453 emit_int24(0x3E, (unsigned char)(0xC0 | encode), vcc);
3454 }
3455
3456 void Assembler::evpcmpuw(KRegister kdst, XMMRegister nds, Address src, ComparisonPredicate vcc, int vector_len) {
3457 assert(VM_Version::supports_avx512vlbw(), "");
3458 InstructionMark im(this);
3459 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
3460 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
3461 attributes.set_is_evex_instruction();
3462 int dst_enc = kdst->encoding();
3463 vex_prefix(src, nds->encoding(), kdst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3464 emit_int8(0x3E);
3465 emit_operand(as_Register(dst_enc), src);
3466 emit_int8(vcc);
3467 }
3468
3469 void Assembler::evpcmpeqb(KRegister kdst, XMMRegister nds, Address src, int vector_len) {
3470 assert(VM_Version::supports_avx512bw(), "");
3471 InstructionMark im(this);
3472 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
3473 attributes.set_is_evex_instruction();
3479 }
3480
3481 void Assembler::evpcmpeqb(KRegister kdst, KRegister mask, XMMRegister nds, Address src, int vector_len) {
3482 assert(VM_Version::supports_avx512vlbw(), "");
3483 InstructionMark im(this);
3484 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_reg_mask */ false, /* uses_vl */ true);
3485 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
3486 attributes.reset_is_clear_context();
3487 attributes.set_embedded_opmask_register_specifier(mask);
3488 attributes.set_is_evex_instruction();
3489 vex_prefix(src, nds->encoding(), kdst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3490 emit_int8(0x74);
3491 emit_operand(as_Register(kdst->encoding()), src);
3492 }
3493
3494 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst
3495 void Assembler::pcmpeqw(XMMRegister dst, XMMRegister src) {
3496 assert(VM_Version::supports_sse2(), "");
3497 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
3498 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3499 emit_int16(0x75, (unsigned char)(0xC0 | encode));
3500 }
3501
3502 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst
3503 void Assembler::vpcmpeqw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3504 assert(VM_Version::supports_avx(), "");
3505 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
3506 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3507 emit_int16(0x75, (unsigned char)(0xC0 | encode));
3508 }
3509
3510 // In this context, kdst is written the mask used to process the equal components
3511 void Assembler::evpcmpeqw(KRegister kdst, XMMRegister nds, XMMRegister src, int vector_len) {
3512 assert(VM_Version::supports_avx512bw(), "");
3513 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
3514 attributes.set_is_evex_instruction();
3515 int encode = vex_prefix_and_encode(kdst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3516 emit_int16(0x75, (unsigned char)(0xC0 | encode));
3517 }
3518
3519 void Assembler::evpcmpeqw(KRegister kdst, XMMRegister nds, Address src, int vector_len) {
3520 assert(VM_Version::supports_avx512bw(), "");
3521 InstructionMark im(this);
3522 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
3523 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
3524 attributes.set_is_evex_instruction();
3525 int dst_enc = kdst->encoding();
3526 vex_prefix(src, nds->encoding(), dst_enc, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3527 emit_int8(0x75);
3528 emit_operand(as_Register(dst_enc), src);
3529 }
3530
3531 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst
3532 void Assembler::pcmpeqd(XMMRegister dst, XMMRegister src) {
3533 assert(VM_Version::supports_sse2(), "");
3534 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
3535 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3536 emit_int8(0x76);
3537 emit_int8((unsigned char)(0xC0 | encode));
3538 }
3539
3540 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst
3541 void Assembler::vpcmpeqd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3542 assert(VM_Version::supports_avx(), "");
3543 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
3544 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3545 emit_int16(0x76, (unsigned char)(0xC0 | encode));
3546 }
3547
3548 // In this context, kdst is written the mask used to process the equal components
3549 void Assembler::evpcmpeqd(KRegister kdst, XMMRegister nds, XMMRegister src, int vector_len) {
3550 assert(VM_Version::supports_evex(), "");
3551 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
3552 attributes.set_is_evex_instruction();
3553 attributes.reset_is_clear_context();
3554 int encode = vex_prefix_and_encode(kdst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3555 emit_int16(0x76, (unsigned char)(0xC0 | encode));
3556 }
3557
3558 void Assembler::evpcmpeqd(KRegister kdst, XMMRegister nds, Address src, int vector_len) {
3559 assert(VM_Version::supports_evex(), "");
3560 InstructionMark im(this);
3561 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
3562 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
3563 attributes.reset_is_clear_context();
3564 attributes.set_is_evex_instruction();
3565 int dst_enc = kdst->encoding();
3566 vex_prefix(src, nds->encoding(), dst_enc, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3567 emit_int8(0x76);
3568 emit_operand(as_Register(dst_enc), src);
3569 }
3570
3571 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst
3572 void Assembler::pcmpeqq(XMMRegister dst, XMMRegister src) {
3573 assert(VM_Version::supports_sse4_1(), "");
3574 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
3575 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3576 emit_int16(0x29, (unsigned char)(0xC0 | encode));
3577 }
3578
3579 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst
3580 void Assembler::vpcmpeqq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3581 assert(VM_Version::supports_avx(), "");
3582 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
3583 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3584 emit_int16(0x29, (unsigned char)(0xC0 | encode));
3585 }
3586
3587 // In this context, kdst is written the mask used to process the equal components
3588 void Assembler::evpcmpeqq(KRegister kdst, XMMRegister nds, XMMRegister src, int vector_len) {
3589 assert(VM_Version::supports_evex(), "");
3590 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
3591 attributes.reset_is_clear_context();
3592 attributes.set_is_evex_instruction();
3593 int encode = vex_prefix_and_encode(kdst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3594 emit_int16(0x29, (unsigned char)(0xC0 | encode));
3595 }
3596
3597 // In this context, kdst is written the mask used to process the equal components
3598 void Assembler::evpcmpeqq(KRegister kdst, XMMRegister nds, Address src, int vector_len) {
3599 assert(VM_Version::supports_evex(), "");
3600 InstructionMark im(this);
3601 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
3602 attributes.reset_is_clear_context();
3603 attributes.set_is_evex_instruction();
3604 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
3605 int dst_enc = kdst->encoding();
3606 vex_prefix(src, nds->encoding(), dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3607 emit_int8(0x29);
3608 emit_operand(as_Register(dst_enc), src);
3609 }
3610
3611 void Assembler::pmovmskb(Register dst, XMMRegister src) {
3612 assert(VM_Version::supports_sse2(), "");
3613 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
3614 int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3615 emit_int16((unsigned char)0xD7, (unsigned char)(0xC0 | encode));
3616 }
3617
3618 void Assembler::vpmovmskb(Register dst, XMMRegister src) {
3619 assert(VM_Version::supports_avx2(), "");
3620 InstructionAttr attributes(AVX_256bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
3621 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3622 emit_int16((unsigned char)0xD7, (unsigned char)(0xC0 | encode));
3623 }
3624
3625 void Assembler::pextrd(Register dst, XMMRegister src, int imm8) {
3626 assert(VM_Version::supports_sse4_1(), "");
3627 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true);
3628 int encode = simd_prefix_and_encode(src, xnoreg, as_XMMRegister(dst->encoding()), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3629 emit_int24(0x16, (unsigned char)(0xC0 | encode), imm8);
3630 }
3631
3632 void Assembler::pextrd(Address dst, XMMRegister src, int imm8) {
3633 assert(VM_Version::supports_sse4_1(), "");
3634 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true);
3635 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
3636 simd_prefix(src, xnoreg, dst, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3637 emit_int8(0x16);
3638 emit_operand(src, dst);
3639 emit_int8(imm8);
3640 }
3641
3642 void Assembler::pextrq(Register dst, XMMRegister src, int imm8) {
3643 assert(VM_Version::supports_sse4_1(), "");
3644 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true);
3645 int encode = simd_prefix_and_encode(src, xnoreg, as_XMMRegister(dst->encoding()), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3646 emit_int24(0x16, (unsigned char)(0xC0 | encode), imm8);
3647 }
3648
3649 void Assembler::pextrq(Address dst, XMMRegister src, int imm8) {
3650 assert(VM_Version::supports_sse4_1(), "");
3651 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true);
3652 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
3653 simd_prefix(src, xnoreg, dst, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3654 emit_int8(0x16);
3655 emit_operand(src, dst);
3656 emit_int8(imm8);
3657 }
3658
3659 void Assembler::pextrw(Register dst, XMMRegister src, int imm8) {
3660 assert(VM_Version::supports_sse2(), "");
3661 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
3662 int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3663 emit_int24((unsigned char)0xC5, (unsigned char)(0xC0 | encode), imm8);
3664 }
3665
3666 void Assembler::pextrw(Address dst, XMMRegister src, int imm8) {
3667 assert(VM_Version::supports_sse4_1(), "");
3668 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
3669 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_16bit);
3670 simd_prefix(src, xnoreg, dst, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3671 emit_int8((unsigned char)0x15);
3672 emit_operand(src, dst);
3673 emit_int8(imm8);
3674 }
3675
3676 void Assembler::pextrb(Address dst, XMMRegister src, int imm8) {
3677 assert(VM_Version::supports_sse4_1(), "");
3678 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
3679 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_8bit);
3680 simd_prefix(src, xnoreg, dst, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3681 emit_int8(0x14);
3682 emit_operand(src, dst);
3683 emit_int8(imm8);
3684 }
3685
3686 void Assembler::pinsrd(XMMRegister dst, Register src, int imm8) {
3687 assert(VM_Version::supports_sse4_1(), "");
3688 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true);
3689 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3690 emit_int24(0x22, (unsigned char)(0xC0 | encode), imm8);
3691 }
3692
3693 void Assembler::pinsrd(XMMRegister dst, Address src, int imm8) {
3694 assert(VM_Version::supports_sse4_1(), "");
3695 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true);
3696 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
3697 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3698 emit_int8(0x22);
3699 emit_operand(dst,src);
3700 emit_int8(imm8);
3701 }
3702
3703 void Assembler::pinsrq(XMMRegister dst, Register src, int imm8) {
3704 assert(VM_Version::supports_sse4_1(), "");
3705 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true);
3706 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3707 emit_int24(0x22, (unsigned char)(0xC0 | encode), imm8);
3708 }
3709
3710 void Assembler::pinsrq(XMMRegister dst, Address src, int imm8) {
3711 assert(VM_Version::supports_sse4_1(), "");
3712 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true);
3713 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
3714 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3715 emit_int8(0x22);
3716 emit_operand(dst, src);
3717 emit_int8(imm8);
3718 }
3719
3720 void Assembler::pinsrw(XMMRegister dst, Register src, int imm8) {
3721 assert(VM_Version::supports_sse2(), "");
3722 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
3723 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3724 emit_int24((unsigned char)0xC4, (unsigned char)(0xC0 | encode), imm8);
3725 }
3726
3727 void Assembler::pinsrw(XMMRegister dst, Address src, int imm8) {
3728 assert(VM_Version::supports_sse2(), "");
3729 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
3730 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_16bit);
3731 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3732 emit_int8((unsigned char)0xC4);
3733 emit_operand(dst, src);
3734 emit_int8(imm8);
3735 }
3736
3737 void Assembler::pinsrb(XMMRegister dst, Address src, int imm8) {
3738 assert(VM_Version::supports_sse4_1(), "");
3739 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
3740 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_8bit);
3741 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3742 emit_int8(0x20);
3743 emit_operand(dst, src);
3744 emit_int8(imm8);
3745 }
3746
3747 void Assembler::pmovzxbw(XMMRegister dst, Address src) {
3748 assert(VM_Version::supports_sse4_1(), "");
3749 InstructionMark im(this);
3750 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
3751 attributes.set_address_attributes(/* tuple_type */ EVEX_HVM, /* input_size_in_bits */ EVEX_NObit);
3752 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3753 emit_int8(0x30);
3754 emit_operand(dst, src);
3755 }
3756
3757 void Assembler::pmovzxbw(XMMRegister dst, XMMRegister src) {
3758 assert(VM_Version::supports_sse4_1(), "");
3759 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
3760 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3761 emit_int16(0x30, (unsigned char)(0xC0 | encode));
3762 }
3763
3764 void Assembler::pmovsxbw(XMMRegister dst, XMMRegister src) {
3765 assert(VM_Version::supports_sse4_1(), "");
3766 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
3767 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3768 emit_int16(0x20, (unsigned char)(0xC0 | encode));
3769 }
3770
3771 void Assembler::vpmovzxbw(XMMRegister dst, Address src, int vector_len) {
3772 assert(VM_Version::supports_avx(), "");
3773 InstructionMark im(this);
3774 assert(dst != xnoreg, "sanity");
3775 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
3776 attributes.set_address_attributes(/* tuple_type */ EVEX_HVM, /* input_size_in_bits */ EVEX_NObit);
3777 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3778 emit_int8(0x30);
3779 emit_operand(dst, src);
3780 }
3781
3782 void Assembler::vpmovzxbw(XMMRegister dst, XMMRegister src, int vector_len) {
3783 assert(vector_len == AVX_128bit? VM_Version::supports_avx() :
3784 vector_len == AVX_256bit? VM_Version::supports_avx2() :
3785 vector_len == AVX_512bit? VM_Version::supports_avx512bw() : 0, "");
3786 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
3787 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3788 emit_int16(0x30, (unsigned char) (0xC0 | encode));
3789 }
3790
3791 void Assembler::vpmovsxbw(XMMRegister dst, XMMRegister src, int vector_len) {
3792 assert(vector_len == AVX_128bit? VM_Version::supports_avx() :
3793 vector_len == AVX_256bit? VM_Version::supports_avx2() :
3794 vector_len == AVX_512bit? VM_Version::supports_avx512bw() : 0, "");
3795 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
3796 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3797 emit_int16(0x20, (unsigned char)(0xC0 | encode));
3798 }
3799
3800 void Assembler::evpmovzxbw(XMMRegister dst, KRegister mask, Address src, int vector_len) {
3801 assert(VM_Version::supports_avx512vlbw(), "");
3802 assert(dst != xnoreg, "sanity");
3803 InstructionMark im(this);
3804 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
3805 attributes.set_address_attributes(/* tuple_type */ EVEX_HVM, /* input_size_in_bits */ EVEX_NObit);
3806 attributes.set_embedded_opmask_register_specifier(mask);
3807 attributes.set_is_evex_instruction();
3808 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3809 emit_int8(0x30);
3810 emit_operand(dst, src);
3811 }
3812 void Assembler::evpmovwb(Address dst, XMMRegister src, int vector_len) {
3813 assert(VM_Version::supports_avx512vlbw(), "");
3814 assert(src != xnoreg, "sanity");
3815 InstructionMark im(this);
3816 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
3817 attributes.set_address_attributes(/* tuple_type */ EVEX_HVM, /* input_size_in_bits */ EVEX_NObit);
3836 }
3837
3838 void Assembler::evpmovdb(Address dst, XMMRegister src, int vector_len) {
3839 assert(VM_Version::supports_evex(), "");
3840 assert(src != xnoreg, "sanity");
3841 InstructionMark im(this);
3842 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
3843 attributes.set_address_attributes(/* tuple_type */ EVEX_QVM, /* input_size_in_bits */ EVEX_NObit);
3844 attributes.set_is_evex_instruction();
3845 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F_38, &attributes);
3846 emit_int8(0x31);
3847 emit_operand(src, dst);
3848 }
3849
3850 void Assembler::vpmovzxwd(XMMRegister dst, XMMRegister src, int vector_len) {
3851 assert(vector_len == AVX_128bit? VM_Version::supports_avx() :
3852 vector_len == AVX_256bit? VM_Version::supports_avx2() :
3853 vector_len == AVX_512bit? VM_Version::supports_evex() : 0, " ");
3854 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
3855 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3856 emit_int16(0x33, (unsigned char)(0xC0 | encode));
3857 }
3858
3859 void Assembler::pmaddwd(XMMRegister dst, XMMRegister src) {
3860 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3861 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
3862 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3863 emit_int16((unsigned char)0xF5, (unsigned char)(0xC0 | encode));
3864 }
3865
3866 void Assembler::vpmaddwd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3867 assert(vector_len == AVX_128bit ? VM_Version::supports_avx() :
3868 (vector_len == AVX_256bit ? VM_Version::supports_avx2() :
3869 (vector_len == AVX_512bit ? VM_Version::supports_evex() : 0)), "");
3870 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
3871 int encode = simd_prefix_and_encode(dst, nds, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3872 emit_int16((unsigned char)0xF5, (unsigned char)(0xC0 | encode));
3873 }
3874
3875 void Assembler::evpdpwssd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3876 assert(VM_Version::supports_evex(), "");
3877 assert(VM_Version::supports_avx512_vnni(), "must support vnni");
3878 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
3879 attributes.set_is_evex_instruction();
3880 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3881 emit_int16(0x52, (unsigned char)(0xC0 | encode));
3882 }
3883
3884 // generic
3885 void Assembler::pop(Register dst) {
3886 int encode = prefix_and_encode(dst->encoding());
3887 emit_int8(0x58 | encode);
3888 }
3889
3890 void Assembler::popcntl(Register dst, Address src) {
3891 assert(VM_Version::supports_popcnt(), "must support");
3892 InstructionMark im(this);
3893 emit_int8((unsigned char)0xF3);
3894 prefix(src, dst);
3895 emit_int16(0x0F, (unsigned char)0xB8);
3896 emit_operand(dst, src);
3897 }
3898
3899 void Assembler::popcntl(Register dst, Register src) {
3900 assert(VM_Version::supports_popcnt(), "must support");
3901 emit_int8((unsigned char)0xF3);
3902 int encode = prefix_and_encode(dst->encoding(), src->encoding());
3903 emit_int24(0x0F, (unsigned char)0xB8, (unsigned char)(0xC0 | encode));
3904 }
3905
3906 void Assembler::vpopcntd(XMMRegister dst, XMMRegister src, int vector_len) {
3907 assert(VM_Version::supports_avx512_vpopcntdq(), "must support vpopcntdq feature");
3908 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
3909 attributes.set_is_evex_instruction();
3910 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3911 emit_int16(0x55, (unsigned char)(0xC0 | encode));
3912 }
3913
3914 void Assembler::popf() {
3915 emit_int8((unsigned char)0x9D);
3916 }
3917
3918 #ifndef _LP64 // no 32bit push/pop on amd64
3919 void Assembler::popl(Address dst) {
3920 // NOTE: this will adjust stack by 8byte on 64bits
3921 InstructionMark im(this);
3922 prefix(dst);
3923 emit_int8((unsigned char)0x8F);
3924 emit_operand(rax, dst);
3925 }
3926 #endif
3927
3928 void Assembler::prefetchnta(Address src) {
3929 NOT_LP64(assert(VM_Version::supports_sse(), "must support"));
3930 InstructionMark im(this);
3931 prefix(src);
3932 emit_int16(0x0F, 0x18);
3933 emit_operand(rax, src); // 0, src
3934 }
3935
3936 void Assembler::prefetchr(Address src) {
3937 assert(VM_Version::supports_3dnow_prefetch(), "must support");
3938 InstructionMark im(this);
3939 prefix(src);
3940 emit_int16(0x0F, 0x0D);
3941 emit_operand(rax, src); // 0, src
3942 }
3943
3944 void Assembler::prefetcht0(Address src) {
3945 NOT_LP64(assert(VM_Version::supports_sse(), "must support"));
3946 InstructionMark im(this);
3947 prefix(src);
3948 emit_int16(0x0F, 0x18);
3949 emit_operand(rcx, src); // 1, src
3950 }
3951
3952 void Assembler::prefetcht1(Address src) {
3953 NOT_LP64(assert(VM_Version::supports_sse(), "must support"));
3954 InstructionMark im(this);
3955 prefix(src);
3956 emit_int16(0x0F, 0x18);
3957 emit_operand(rdx, src); // 2, src
3958 }
3959
3960 void Assembler::prefetcht2(Address src) {
3961 NOT_LP64(assert(VM_Version::supports_sse(), "must support"));
3962 InstructionMark im(this);
3963 prefix(src);
3964 emit_int16(0x0F, 0x18);
3965 emit_operand(rbx, src); // 3, src
3966 }
3967
3968 void Assembler::prefetchw(Address src) {
3969 assert(VM_Version::supports_3dnow_prefetch(), "must support");
3970 InstructionMark im(this);
3971 prefix(src);
3972 emit_int16(0x0F, 0x0D);
3973 emit_operand(rcx, src); // 1, src
3974 }
3975
3976 void Assembler::prefix(Prefix p) {
3977 emit_int8(p);
3978 }
3979
3980 void Assembler::pshufb(XMMRegister dst, XMMRegister src) {
3981 assert(VM_Version::supports_ssse3(), "");
3982 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
3983 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3984 emit_int16(0x00, (unsigned char)(0xC0 | encode));
3985 }
3986
3987 void Assembler::vpshufb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3988 assert(vector_len == AVX_128bit? VM_Version::supports_avx() :
3989 vector_len == AVX_256bit? VM_Version::supports_avx2() :
3990 vector_len == AVX_512bit? VM_Version::supports_avx512bw() : 0, "");
3991 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
3992 int encode = simd_prefix_and_encode(dst, nds, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3993 emit_int16(0x00, (unsigned char)(0xC0 | encode));
3994 }
3995
3996 void Assembler::pshufb(XMMRegister dst, Address src) {
3997 assert(VM_Version::supports_ssse3(), "");
3998 InstructionMark im(this);
3999 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
4000 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
4001 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4002 emit_int8(0x00);
4003 emit_operand(dst, src);
4004 }
4005
4006 void Assembler::pshufd(XMMRegister dst, XMMRegister src, int mode) {
4007 assert(isByte(mode), "invalid value");
4008 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4009 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_128bit;
4010 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
4011 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4012 emit_int24(0x70, (unsigned char)(0xC0 | encode), mode & 0xFF);
4013 }
4014
4015 void Assembler::vpshufd(XMMRegister dst, XMMRegister src, int mode, int vector_len) {
4016 assert(vector_len == AVX_128bit? VM_Version::supports_avx() :
4017 (vector_len == AVX_256bit? VM_Version::supports_avx2() :
4018 (vector_len == AVX_512bit? VM_Version::supports_evex() : 0)), "");
4019 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4020 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
4021 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4022 emit_int24(0x70, (unsigned char)(0xC0 | encode), mode & 0xFF);
4023 }
4024
4025 void Assembler::pshufd(XMMRegister dst, Address src, int mode) {
4026 assert(isByte(mode), "invalid value");
4027 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4028 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
4029 InstructionMark im(this);
4030 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
4031 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
4032 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4033 emit_int8(0x70);
4034 emit_operand(dst, src);
4035 emit_int8(mode & 0xFF);
4036 }
4037
4038 void Assembler::pshuflw(XMMRegister dst, XMMRegister src, int mode) {
4039 assert(isByte(mode), "invalid value");
4040 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4041 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
4042 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4043 emit_int24(0x70, (unsigned char)(0xC0 | encode), mode & 0xFF);
4044 }
4045
4046 void Assembler::pshuflw(XMMRegister dst, Address src, int mode) {
4047 assert(isByte(mode), "invalid value");
4048 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4049 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
4050 InstructionMark im(this);
4051 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
4052 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
4053 simd_prefix(dst, xnoreg, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4054 emit_int8(0x70);
4055 emit_operand(dst, src);
4056 emit_int8(mode & 0xFF);
4057 }
4058
4059 void Assembler::evshufi64x2(XMMRegister dst, XMMRegister nds, XMMRegister src, int imm8, int vector_len) {
4060 assert(VM_Version::supports_evex(), "requires EVEX support");
4061 assert(vector_len == Assembler::AVX_256bit || vector_len == Assembler::AVX_512bit, "");
4062 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
4063 attributes.set_is_evex_instruction();
4064 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
4065 emit_int24(0x43, (unsigned char)(0xC0 | encode), imm8 & 0xFF);
4066 }
4067
4068 void Assembler::psrldq(XMMRegister dst, int shift) {
4069 // Shift left 128 bit value in dst XMMRegister by shift number of bytes.
4070 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4071 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
4072 int encode = simd_prefix_and_encode(xmm3, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4073 emit_int24(0x73, (unsigned char)(0xC0 | encode), shift);
4074 }
4075
4076 void Assembler::vpsrldq(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
4077 assert(vector_len == AVX_128bit ? VM_Version::supports_avx() :
4078 vector_len == AVX_256bit ? VM_Version::supports_avx2() :
4079 vector_len == AVX_512bit ? VM_Version::supports_avx512bw() : 0, "");
4080 InstructionAttr attributes(vector_len, /*vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
4081 int encode = vex_prefix_and_encode(xmm3->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4082 emit_int24(0x73, (unsigned char)(0xC0 | encode), shift & 0xFF);
4083 }
4084
4085 void Assembler::pslldq(XMMRegister dst, int shift) {
4086 // Shift left 128 bit value in dst XMMRegister by shift number of bytes.
4087 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4088 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
4089 // XMM7 is for /7 encoding: 66 0F 73 /7 ib
4090 int encode = simd_prefix_and_encode(xmm7, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4091 emit_int24(0x73, (unsigned char)(0xC0 | encode), shift);
4092 }
4093
4094 void Assembler::vpslldq(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
4095 assert(vector_len == AVX_128bit ? VM_Version::supports_avx() :
4096 vector_len == AVX_256bit ? VM_Version::supports_avx2() :
4097 vector_len == AVX_512bit ? VM_Version::supports_avx512bw() : 0, "");
4098 InstructionAttr attributes(vector_len, /*vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
4099 int encode = vex_prefix_and_encode(xmm7->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4100 emit_int24(0x73, (unsigned char)(0xC0 | encode), shift & 0xFF);
4101 }
4102
4103 void Assembler::ptest(XMMRegister dst, Address src) {
4104 assert(VM_Version::supports_sse4_1(), "");
4105 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
4106 InstructionMark im(this);
4107 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
4108 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4109 emit_int8(0x17);
4110 emit_operand(dst, src);
4111 }
4112
4113 void Assembler::ptest(XMMRegister dst, XMMRegister src) {
4114 assert(VM_Version::supports_sse4_1() || VM_Version::supports_avx(), "");
4115 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
4116 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4117 emit_int8(0x17);
4118 emit_int8((unsigned char)(0xC0 | encode));
4119 }
4120
4121 void Assembler::vptest(XMMRegister dst, Address src) {
4122 assert(VM_Version::supports_avx(), "");
4123 InstructionMark im(this);
4124 InstructionAttr attributes(AVX_256bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
4125 assert(dst != xnoreg, "sanity");
4126 // swap src<->dst for encoding
4127 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4128 emit_int8(0x17);
4129 emit_operand(dst, src);
4130 }
4131
4132 void Assembler::vptest(XMMRegister dst, XMMRegister src) {
4133 assert(VM_Version::supports_avx(), "");
4134 InstructionAttr attributes(AVX_256bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
4135 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4136 emit_int16(0x17, (unsigned char)(0xC0 | encode));
4137 }
4138
4139 void Assembler::punpcklbw(XMMRegister dst, Address src) {
4140 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4141 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
4142 InstructionMark im(this);
4143 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_vlbw, /* no_mask_reg */ true, /* uses_vl */ true);
4144 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
4145 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4146 emit_int8(0x60);
4147 emit_operand(dst, src);
4148 }
4149
4150 void Assembler::punpcklbw(XMMRegister dst, XMMRegister src) {
4151 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4152 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_vlbw, /* no_mask_reg */ true, /* uses_vl */ true);
4153 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4154 emit_int16(0x60, (unsigned char)(0xC0 | encode));
4155 }
4156
4157 void Assembler::punpckldq(XMMRegister dst, Address src) {
4158 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4159 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
4160 InstructionMark im(this);
4161 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
4162 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
4163 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4164 emit_int8(0x62);
4165 emit_operand(dst, src);
4166 }
4167
4168 void Assembler::punpckldq(XMMRegister dst, XMMRegister src) {
4169 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4170 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
4171 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4172 emit_int16(0x62, (unsigned char)(0xC0 | encode));
4173 }
4174
4175 void Assembler::punpcklqdq(XMMRegister dst, XMMRegister src) {
4176 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4177 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
4178 attributes.set_rex_vex_w_reverted();
4179 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4180 emit_int16(0x6C, (unsigned char)(0xC0 | encode));
4181 }
4182
4183 void Assembler::push(int32_t imm32) {
4184 // in 64bits we push 64bits onto the stack but only
4185 // take a 32bit immediate
4186 emit_int8(0x68);
4187 emit_int32(imm32);
4188 }
4189
4190 void Assembler::push(Register src) {
4191 int encode = prefix_and_encode(src->encoding());
4192 emit_int8(0x50 | encode);
4193 }
4194
4195 void Assembler::pushf() {
4196 emit_int8((unsigned char)0x9C);
4197 }
4198
4199 #ifndef _LP64 // no 32bit push/pop on amd64
4200 void Assembler::pushl(Address src) {
4201 // Note this will push 64bit on 64bit
4202 InstructionMark im(this);
4203 prefix(src);
4204 emit_int8((unsigned char)0xFF);
4205 emit_operand(rsi, src);
4206 }
4207 #endif
4208
4209 void Assembler::rcll(Register dst, int imm8) {
4210 assert(isShiftCount(imm8), "illegal shift count");
4211 int encode = prefix_and_encode(dst->encoding());
4212 if (imm8 == 1) {
4213 emit_int16((unsigned char)0xD1, (unsigned char)(0xD0 | encode));
4214 } else {
4215 emit_int24((unsigned char)0xC1, (unsigned char)0xD0 | encode, imm8);
4216 }
4217 }
4218
4219 void Assembler::rcpps(XMMRegister dst, XMMRegister src) {
4220 NOT_LP64(assert(VM_Version::supports_sse(), ""));
4221 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
4222 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4223 emit_int16(0x53, (unsigned char)(0xC0 | encode));
4224 }
4225
4226 void Assembler::rcpss(XMMRegister dst, XMMRegister src) {
4227 NOT_LP64(assert(VM_Version::supports_sse(), ""));
4228 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
4229 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4230 emit_int16(0x53, (unsigned char)(0xC0 | encode));
4231 }
4232
4233 void Assembler::rdtsc() {
4234 emit_int16((unsigned char)0x0F, (unsigned char)0x31);
4235 }
4236
4237 // copies data from [esi] to [edi] using rcx pointer sized words
4238 // generic
4239 void Assembler::rep_mov() {
4240 // REP
4241 // MOVSQ
4242 LP64_ONLY(emit_int24((unsigned char)0xF3, REX_W, (unsigned char)0xA5);)
4243 NOT_LP64( emit_int16((unsigned char)0xF3, (unsigned char)0xA5);)
4244 }
4245
4246 // sets rcx bytes with rax, value at [edi]
4247 void Assembler::rep_stosb() {
4248 // REP
4249 // STOSB
4250 LP64_ONLY(emit_int24((unsigned char)0xF3, REX_W, (unsigned char)0xAA);)
4251 NOT_LP64( emit_int16((unsigned char)0xF3, (unsigned char)0xAA);)
4252 }
4253
4254 // sets rcx pointer sized words with rax, value at [edi]
4255 // generic
4256 void Assembler::rep_stos() {
4257 // REP
4258 // LP64:STOSQ, LP32:STOSD
4259 LP64_ONLY(emit_int24((unsigned char)0xF3, REX_W, (unsigned char)0xAB);)
4260 NOT_LP64( emit_int16((unsigned char)0xF3, (unsigned char)0xAB);)
4261 }
4262
4263 // scans rcx pointer sized words at [edi] for occurance of rax,
4264 // generic
4265 void Assembler::repne_scan() { // repne_scan
4266 // SCASQ
4267 LP64_ONLY(emit_int24((unsigned char)0xF2, REX_W, (unsigned char)0xAF);)
4268 NOT_LP64( emit_int16((unsigned char)0xF2, (unsigned char)0xAF);)
4269 }
4270
4271 #ifdef _LP64
4272 // scans rcx 4 byte words at [edi] for occurance of rax,
4273 // generic
4274 void Assembler::repne_scanl() { // repne_scan
4275 // SCASL
4276 emit_int16((unsigned char)0xF2, (unsigned char)0xAF);
4277 }
4278 #endif
4279
4280 void Assembler::ret(int imm16) {
4281 if (imm16 == 0) {
4282 emit_int8((unsigned char)0xC3);
4283 } else {
4284 emit_int8((unsigned char)0xC2);
4285 emit_int16(imm16);
4286 }
4287 }
4288
4289 void Assembler::sahf() {
4290 #ifdef _LP64
4291 // Not supported in 64bit mode
4292 ShouldNotReachHere();
4293 #endif
4294 emit_int8((unsigned char)0x9E);
4295 }
4296
4297 void Assembler::sarl(Register dst, int imm8) {
4298 int encode = prefix_and_encode(dst->encoding());
4299 assert(isShiftCount(imm8), "illegal shift count");
4300 if (imm8 == 1) {
4301 emit_int16((unsigned char)0xD1, (unsigned char)(0xF8 | encode));
4302 } else {
4303 emit_int24((unsigned char)0xC1, (unsigned char)(0xF8 | encode), imm8);
4304 }
4305 }
4306
4307 void Assembler::sarl(Register dst) {
4308 int encode = prefix_and_encode(dst->encoding());
4309 emit_int16((unsigned char)0xD3, (unsigned char)(0xF8 | encode));
4310 }
4311
4312 void Assembler::sbbl(Address dst, int32_t imm32) {
4313 InstructionMark im(this);
4314 prefix(dst);
4315 emit_arith_operand(0x81, rbx, dst, imm32);
4316 }
4317
4318 void Assembler::sbbl(Register dst, int32_t imm32) {
4319 prefix(dst);
4320 emit_arith(0x81, 0xD8, dst, imm32);
4321 }
4322
4323
4324 void Assembler::sbbl(Register dst, Address src) {
4325 InstructionMark im(this);
4326 prefix(src, dst);
4327 emit_int8(0x1B);
4328 emit_operand(dst, src);
4329 }
4330
4331 void Assembler::sbbl(Register dst, Register src) {
4332 (void) prefix_and_encode(dst->encoding(), src->encoding());
4333 emit_arith(0x1B, 0xC0, dst, src);
4334 }
4335
4336 void Assembler::setb(Condition cc, Register dst) {
4337 assert(0 <= cc && cc < 16, "illegal cc");
4338 int encode = prefix_and_encode(dst->encoding(), true);
4339 emit_int24(0x0F, (unsigned char)0x90 | cc, (unsigned char)(0xC0 | encode));
4340 }
4341
4342 void Assembler::palignr(XMMRegister dst, XMMRegister src, int imm8) {
4343 assert(VM_Version::supports_ssse3(), "");
4344 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
4345 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
4346 emit_int24((unsigned char)0x0F, (unsigned char)(0xC0 | encode), imm8);
4347 }
4348
4349 void Assembler::vpalignr(XMMRegister dst, XMMRegister nds, XMMRegister src, int imm8, int vector_len) {
4350 assert(vector_len == AVX_128bit? VM_Version::supports_avx() :
4351 vector_len == AVX_256bit? VM_Version::supports_avx2() :
4352 0, "");
4353 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
4354 int encode = simd_prefix_and_encode(dst, nds, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
4355 emit_int24((unsigned char)0x0F, (unsigned char)(0xC0 | encode), imm8);
4356 }
4357
4358 void Assembler::evalignq(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8) {
4359 assert(VM_Version::supports_evex(), "");
4360 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
4361 attributes.set_is_evex_instruction();
4362 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
4363 emit_int24(0x3, (unsigned char)(0xC0 | encode), imm8);
4364 }
4365
4366 void Assembler::pblendw(XMMRegister dst, XMMRegister src, int imm8) {
4367 assert(VM_Version::supports_sse4_1(), "");
4368 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
4369 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
4370 emit_int24((unsigned char)0x0E, (unsigned char)(0xC0 | encode), imm8);
4371 }
4372
4373 void Assembler::sha1rnds4(XMMRegister dst, XMMRegister src, int imm8) {
4374 assert(VM_Version::supports_sha(), "");
4375 int encode = rex_prefix_and_encode(dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_3A, /* rex_w */ false);
4376 emit_int24((unsigned char)0xCC, (unsigned char)(0xC0 | encode), (unsigned char)imm8);
4377 }
4378
4379 void Assembler::sha1nexte(XMMRegister dst, XMMRegister src) {
4380 assert(VM_Version::supports_sha(), "");
4381 int encode = rex_prefix_and_encode(dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, /* rex_w */ false);
4382 emit_int16((unsigned char)0xC8, (unsigned char)(0xC0 | encode));
4383 }
4384
4385 void Assembler::sha1msg1(XMMRegister dst, XMMRegister src) {
4386 assert(VM_Version::supports_sha(), "");
4387 int encode = rex_prefix_and_encode(dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, /* rex_w */ false);
4388 emit_int16((unsigned char)0xC9, (unsigned char)(0xC0 | encode));
4389 }
4390
4391 void Assembler::sha1msg2(XMMRegister dst, XMMRegister src) {
4392 assert(VM_Version::supports_sha(), "");
4393 int encode = rex_prefix_and_encode(dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, /* rex_w */ false);
4394 emit_int16((unsigned char)0xCA, (unsigned char)(0xC0 | encode));
4395 }
4396
4397 // xmm0 is implicit additional source to this instruction.
4398 void Assembler::sha256rnds2(XMMRegister dst, XMMRegister src) {
4399 assert(VM_Version::supports_sha(), "");
4400 int encode = rex_prefix_and_encode(dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, /* rex_w */ false);
4401 emit_int16((unsigned char)0xCB, (unsigned char)(0xC0 | encode));
4402 }
4403
4404 void Assembler::sha256msg1(XMMRegister dst, XMMRegister src) {
4405 assert(VM_Version::supports_sha(), "");
4406 int encode = rex_prefix_and_encode(dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, /* rex_w */ false);
4407 emit_int16((unsigned char)0xCC, (unsigned char)(0xC0 | encode));
4408 }
4409
4410 void Assembler::sha256msg2(XMMRegister dst, XMMRegister src) {
4411 assert(VM_Version::supports_sha(), "");
4412 int encode = rex_prefix_and_encode(dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, /* rex_w */ false);
4413 emit_int16((unsigned char)0xCD, (unsigned char)(0xC0 | encode));
4414 }
4415
4416
4417 void Assembler::shll(Register dst, int imm8) {
4418 assert(isShiftCount(imm8), "illegal shift count");
4419 int encode = prefix_and_encode(dst->encoding());
4420 if (imm8 == 1 ) {
4421 emit_int16((unsigned char)0xD1, (unsigned char)(0xE0 | encode));
4422 } else {
4423 emit_int24((unsigned char)0xC1, (unsigned char)(0xE0 | encode), imm8);
4424 }
4425 }
4426
4427 void Assembler::shll(Register dst) {
4428 int encode = prefix_and_encode(dst->encoding());
4429 emit_int16((unsigned char)0xD3, (unsigned char)(0xE0 | encode));
4430 }
4431
4432 void Assembler::shrl(Register dst, int imm8) {
4433 assert(isShiftCount(imm8), "illegal shift count");
4434 int encode = prefix_and_encode(dst->encoding());
4435 emit_int24((unsigned char)0xC1, (unsigned char)(0xE8 | encode), imm8);
4436 }
4437
4438 void Assembler::shrl(Register dst) {
4439 int encode = prefix_and_encode(dst->encoding());
4440 emit_int16((unsigned char)0xD3, (unsigned char)(0xE8 | encode));
4441 }
4442
4443 void Assembler::shldl(Register dst, Register src) {
4444 int encode = prefix_and_encode(src->encoding(), dst->encoding());
4445 emit_int24(0x0F, (unsigned char)0xA5, (unsigned char)(0xC0 | encode));
4446 }
4447
4448 void Assembler::shldl(Register dst, Register src, int8_t imm8) {
4449 int encode = prefix_and_encode(src->encoding(), dst->encoding());
4450 emit_int32(0x0F, (unsigned char)0xA4, (unsigned char)(0xC0 | encode), imm8);
4451 }
4452
4453 void Assembler::shrdl(Register dst, Register src) {
4454 int encode = prefix_and_encode(src->encoding(), dst->encoding());
4455 emit_int24(0x0F, (unsigned char)0xAD, (unsigned char)(0xC0 | encode));
4456 }
4457
4458 void Assembler::shrdl(Register dst, Register src, int8_t imm8) {
4459 int encode = prefix_and_encode(src->encoding(), dst->encoding());
4460 emit_int32(0x0F, (unsigned char)0xAC, (unsigned char)(0xC0 | encode), imm8);
4461 }
4462
4463 // copies a single word from [esi] to [edi]
4464 void Assembler::smovl() {
4465 emit_int8((unsigned char)0xA5);
4466 }
4467
4468 void Assembler::roundsd(XMMRegister dst, XMMRegister src, int32_t rmode) {
4469 assert(VM_Version::supports_sse4_1(), "");
4470 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
4471 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
4472 emit_int24(0x0B, (unsigned char)(0xC0 | encode), (unsigned char)rmode);
4473 }
4474
4475 void Assembler::roundsd(XMMRegister dst, Address src, int32_t rmode) {
4476 assert(VM_Version::supports_sse4_1(), "");
4477 InstructionMark im(this);
4478 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
4479 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
4480 emit_int8(0x0B);
4481 emit_operand(dst, src);
4482 emit_int8((unsigned char)rmode);
4483 }
4484
4485 void Assembler::sqrtsd(XMMRegister dst, XMMRegister src) {
4486 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4487 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4488 attributes.set_rex_vex_w_reverted();
4489 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4490 emit_int16(0x51, (unsigned char)(0xC0 | encode));
4491 }
4492
4493 void Assembler::sqrtsd(XMMRegister dst, Address src) {
4494 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4495 InstructionMark im(this);
4496 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4497 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
4498 attributes.set_rex_vex_w_reverted();
4499 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4500 emit_int8(0x51);
4501 emit_operand(dst, src);
4502 }
4503
4504 void Assembler::sqrtss(XMMRegister dst, XMMRegister src) {
4505 NOT_LP64(assert(VM_Version::supports_sse(), ""));
4506 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4507 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4508 emit_int16(0x51, (unsigned char)(0xC0 | encode));
4509 }
4510
4511 void Assembler::std() {
4512 emit_int8((unsigned char)0xFD);
4513 }
4514
4515 void Assembler::sqrtss(XMMRegister dst, Address src) {
4516 NOT_LP64(assert(VM_Version::supports_sse(), ""));
4517 InstructionMark im(this);
4518 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4519 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
4520 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4521 emit_int8(0x51);
4522 emit_operand(dst, src);
4523 }
4524
4525 void Assembler::stmxcsr( Address dst) {
4526 if (UseAVX > 0 ) {
4527 assert(VM_Version::supports_avx(), "");
4528 InstructionMark im(this);
4529 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
4530 vex_prefix(dst, 0, 0, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4531 emit_int8((unsigned char)0xAE);
4532 emit_operand(as_Register(3), dst);
4533 } else {
4534 NOT_LP64(assert(VM_Version::supports_sse(), ""));
4535 InstructionMark im(this);
4536 prefix(dst);
4537 emit_int16(0x0F, (unsigned char)0xAE);
4538 emit_operand(as_Register(3), dst);
4539 }
4540 }
4541
4542 void Assembler::subl(Address dst, int32_t imm32) {
4543 InstructionMark im(this);
4544 prefix(dst);
4545 emit_arith_operand(0x81, rbp, dst, imm32);
4546 }
4547
4548 void Assembler::subl(Address dst, Register src) {
4549 InstructionMark im(this);
4550 prefix(dst, src);
4551 emit_int8(0x29);
4552 emit_operand(src, dst);
4553 }
4554
4555 void Assembler::subl(Register dst, int32_t imm32) {
4556 prefix(dst);
4557 emit_arith(0x81, 0xE8, dst, imm32);
4563 emit_arith_imm32(0x81, 0xE8, dst, imm32);
4564 }
4565
4566 void Assembler::subl(Register dst, Address src) {
4567 InstructionMark im(this);
4568 prefix(src, dst);
4569 emit_int8(0x2B);
4570 emit_operand(dst, src);
4571 }
4572
4573 void Assembler::subl(Register dst, Register src) {
4574 (void) prefix_and_encode(dst->encoding(), src->encoding());
4575 emit_arith(0x2B, 0xC0, dst, src);
4576 }
4577
4578 void Assembler::subsd(XMMRegister dst, XMMRegister src) {
4579 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4580 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4581 attributes.set_rex_vex_w_reverted();
4582 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4583 emit_int16(0x5C, (unsigned char)(0xC0 | encode));
4584 }
4585
4586 void Assembler::subsd(XMMRegister dst, Address src) {
4587 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4588 InstructionMark im(this);
4589 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4590 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
4591 attributes.set_rex_vex_w_reverted();
4592 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4593 emit_int8(0x5C);
4594 emit_operand(dst, src);
4595 }
4596
4597 void Assembler::subss(XMMRegister dst, XMMRegister src) {
4598 NOT_LP64(assert(VM_Version::supports_sse(), ""));
4599 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true , /* uses_vl */ false);
4600 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4601 emit_int16(0x5C, (unsigned char)(0xC0 | encode));
4602 }
4603
4604 void Assembler::subss(XMMRegister dst, Address src) {
4605 NOT_LP64(assert(VM_Version::supports_sse(), ""));
4606 InstructionMark im(this);
4607 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4608 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
4609 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4610 emit_int8(0x5C);
4611 emit_operand(dst, src);
4612 }
4613
4614 void Assembler::testb(Register dst, int imm8) {
4615 NOT_LP64(assert(dst->has_byte_register(), "must have byte register"));
4616 (void) prefix_and_encode(dst->encoding(), true);
4617 emit_arith_b(0xF6, 0xC0, dst, imm8);
4618 }
4619
4620 void Assembler::testb(Address dst, int imm8) {
4621 InstructionMark im(this);
4622 prefix(dst);
4623 emit_int8((unsigned char)0xF6);
4624 emit_operand(rax, dst, 1);
4625 emit_int8(imm8);
4626 }
4627
4628 void Assembler::testl(Register dst, int32_t imm32) {
4629 // not using emit_arith because test
4630 // doesn't support sign-extension of
4631 // 8bit operands
4632 int encode = dst->encoding();
4633 if (encode == 0) {
4634 emit_int8((unsigned char)0xA9);
4635 } else {
4636 encode = prefix_and_encode(encode);
4637 emit_int16((unsigned char)0xF7, (unsigned char)(0xC0 | encode));
4638 }
4639 emit_int32(imm32);
4640 }
4641
4642 void Assembler::testl(Register dst, Register src) {
4643 (void) prefix_and_encode(dst->encoding(), src->encoding());
4644 emit_arith(0x85, 0xC0, dst, src);
4645 }
4646
4647 void Assembler::testl(Register dst, Address src) {
4648 InstructionMark im(this);
4649 prefix(src, dst);
4650 emit_int8((unsigned char)0x85);
4651 emit_operand(dst, src);
4652 }
4653
4654 void Assembler::tzcntl(Register dst, Register src) {
4655 assert(VM_Version::supports_bmi1(), "tzcnt instruction not supported");
4656 emit_int8((unsigned char)0xF3);
4657 int encode = prefix_and_encode(dst->encoding(), src->encoding());
4658 emit_int24(0x0F, (unsigned char)0xBC, (unsigned char)0xC0 | encode);
4659 }
4660
4661 void Assembler::tzcntq(Register dst, Register src) {
4662 assert(VM_Version::supports_bmi1(), "tzcnt instruction not supported");
4663 emit_int8((unsigned char)0xF3);
4664 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
4665 emit_int24(0x0F, (unsigned char)0xBC, (unsigned char)(0xC0 | encode));
4666 }
4667
4668 void Assembler::ucomisd(XMMRegister dst, Address src) {
4669 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4670 InstructionMark im(this);
4671 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4672 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
4673 attributes.set_rex_vex_w_reverted();
4674 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4675 emit_int8(0x2E);
4676 emit_operand(dst, src);
4677 }
4678
4679 void Assembler::ucomisd(XMMRegister dst, XMMRegister src) {
4680 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4681 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4682 attributes.set_rex_vex_w_reverted();
4683 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4684 emit_int16(0x2E, (unsigned char)(0xC0 | encode));
4685 }
4686
4687 void Assembler::ucomiss(XMMRegister dst, Address src) {
4688 NOT_LP64(assert(VM_Version::supports_sse(), ""));
4689 InstructionMark im(this);
4690 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4691 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
4692 simd_prefix(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4693 emit_int8(0x2E);
4694 emit_operand(dst, src);
4695 }
4696
4697 void Assembler::ucomiss(XMMRegister dst, XMMRegister src) {
4698 NOT_LP64(assert(VM_Version::supports_sse(), ""));
4699 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4700 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4701 emit_int16(0x2E, (unsigned char)(0xC0 | encode));
4702 }
4703
4704 void Assembler::xabort(int8_t imm8) {
4705 emit_int24((unsigned char)0xC6, (unsigned char)0xF8, (unsigned char)(imm8 & 0xFF));
4706 }
4707
4708 void Assembler::xaddb(Address dst, Register src) {
4709 InstructionMark im(this);
4710 prefix(dst, src, true);
4711 emit_int16(0x0F, (unsigned char)0xC0);
4712 emit_operand(src, dst);
4713 }
4714
4715 void Assembler::xaddw(Address dst, Register src) {
4716 InstructionMark im(this);
4717 emit_int8(0x66);
4718 prefix(dst, src);
4719 emit_int16(0x0F, (unsigned char)0xC1);
4720 emit_operand(src, dst);
4721 }
4722
4723 void Assembler::xaddl(Address dst, Register src) {
4724 InstructionMark im(this);
4725 prefix(dst, src);
4726 emit_int16(0x0F, (unsigned char)0xC1);
4727 emit_operand(src, dst);
4728 }
4729
4730 void Assembler::xbegin(Label& abort, relocInfo::relocType rtype) {
4731 InstructionMark im(this);
4732 relocate(rtype);
4733 if (abort.is_bound()) {
4734 address entry = target(abort);
4735 assert(entry != NULL, "abort entry NULL");
4736 intptr_t offset = entry - pc();
4737 emit_int16((unsigned char)0xC7, (unsigned char)0xF8);
4738 emit_int32(offset - 6); // 2 opcode + 4 address
4739 } else {
4740 abort.add_patch_at(code(), locator());
4741 emit_int16((unsigned char)0xC7, (unsigned char)0xF8);
4742 emit_int32(0);
4743 }
4744 }
4745
4746 void Assembler::xchgb(Register dst, Address src) { // xchg
4747 InstructionMark im(this);
4748 prefix(src, dst, true);
4749 emit_int8((unsigned char)0x86);
4750 emit_operand(dst, src);
4751 }
4752
4753 void Assembler::xchgw(Register dst, Address src) { // xchg
4754 InstructionMark im(this);
4755 emit_int8(0x66);
4756 prefix(src, dst);
4757 emit_int8((unsigned char)0x87);
4758 emit_operand(dst, src);
4759 }
4760
4761 void Assembler::xchgl(Register dst, Address src) { // xchg
4762 InstructionMark im(this);
4763 prefix(src, dst);
4764 emit_int8((unsigned char)0x87);
4765 emit_operand(dst, src);
4766 }
4767
4768 void Assembler::xchgl(Register dst, Register src) {
4769 int encode = prefix_and_encode(dst->encoding(), src->encoding());
4770 emit_int16((unsigned char)0x87, (unsigned char)(0xC0 | encode));
4771 }
4772
4773 void Assembler::xend() {
4774 emit_int24((unsigned char)0x0F, (unsigned char)0x01, (unsigned char)0xD5);
4775 }
4776
4777 void Assembler::xgetbv() {
4778 emit_int24(0x0F, 0x01, (unsigned char)0xD0);
4779 }
4780
4781 void Assembler::xorl(Register dst, int32_t imm32) {
4782 prefix(dst);
4783 emit_arith(0x81, 0xF0, dst, imm32);
4784 }
4785
4786 void Assembler::xorl(Register dst, Address src) {
4787 InstructionMark im(this);
4788 prefix(src, dst);
4789 emit_int8(0x33);
4790 emit_operand(dst, src);
4791 }
4792
4793 void Assembler::xorl(Register dst, Register src) {
4794 (void) prefix_and_encode(dst->encoding(), src->encoding());
4795 emit_arith(0x33, 0xC0, dst, src);
4796 }
4797
4798 void Assembler::xorb(Register dst, Address src) {
4803 }
4804
4805 // AVX 3-operands scalar float-point arithmetic instructions
4806
4807 void Assembler::vaddsd(XMMRegister dst, XMMRegister nds, Address src) {
4808 assert(VM_Version::supports_avx(), "");
4809 InstructionMark im(this);
4810 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4811 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
4812 attributes.set_rex_vex_w_reverted();
4813 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4814 emit_int8(0x58);
4815 emit_operand(dst, src);
4816 }
4817
4818 void Assembler::vaddsd(XMMRegister dst, XMMRegister nds, XMMRegister src) {
4819 assert(VM_Version::supports_avx(), "");
4820 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4821 attributes.set_rex_vex_w_reverted();
4822 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4823 emit_int16(0x58, (unsigned char)(0xC0 | encode));
4824 }
4825
4826 void Assembler::vaddss(XMMRegister dst, XMMRegister nds, Address src) {
4827 assert(VM_Version::supports_avx(), "");
4828 InstructionMark im(this);
4829 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4830 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
4831 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4832 emit_int8(0x58);
4833 emit_operand(dst, src);
4834 }
4835
4836 void Assembler::vaddss(XMMRegister dst, XMMRegister nds, XMMRegister src) {
4837 assert(VM_Version::supports_avx(), "");
4838 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4839 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4840 emit_int16(0x58, (unsigned char)(0xC0 | encode));
4841 }
4842
4843 void Assembler::vdivsd(XMMRegister dst, XMMRegister nds, Address src) {
4844 assert(VM_Version::supports_avx(), "");
4845 InstructionMark im(this);
4846 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4847 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
4848 attributes.set_rex_vex_w_reverted();
4849 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4850 emit_int8(0x5E);
4851 emit_operand(dst, src);
4852 }
4853
4854 void Assembler::vdivsd(XMMRegister dst, XMMRegister nds, XMMRegister src) {
4855 assert(VM_Version::supports_avx(), "");
4856 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4857 attributes.set_rex_vex_w_reverted();
4858 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4859 emit_int16(0x5E, (unsigned char)(0xC0 | encode));
4860 }
4861
4862 void Assembler::vdivss(XMMRegister dst, XMMRegister nds, Address src) {
4863 assert(VM_Version::supports_avx(), "");
4864 InstructionMark im(this);
4865 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4866 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
4867 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4868 emit_int8(0x5E);
4869 emit_operand(dst, src);
4870 }
4871
4872 void Assembler::vdivss(XMMRegister dst, XMMRegister nds, XMMRegister src) {
4873 assert(VM_Version::supports_avx(), "");
4874 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4875 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4876 emit_int16(0x5E, (unsigned char)(0xC0 | encode));
4877 }
4878
4879 void Assembler::vfmadd231sd(XMMRegister dst, XMMRegister src1, XMMRegister src2) {
4880 assert(VM_Version::supports_fma(), "");
4881 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4882 int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4883 emit_int16((unsigned char)0xB9, (unsigned char)(0xC0 | encode));
4884 }
4885
4886 void Assembler::vfmadd231ss(XMMRegister dst, XMMRegister src1, XMMRegister src2) {
4887 assert(VM_Version::supports_fma(), "");
4888 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4889 int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4890 emit_int16((unsigned char)0xB9, (unsigned char)(0xC0 | encode));
4891 }
4892
4893 void Assembler::vmulsd(XMMRegister dst, XMMRegister nds, Address src) {
4894 assert(VM_Version::supports_avx(), "");
4895 InstructionMark im(this);
4896 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4897 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
4898 attributes.set_rex_vex_w_reverted();
4899 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4900 emit_int8(0x59);
4901 emit_operand(dst, src);
4902 }
4903
4904 void Assembler::vmulsd(XMMRegister dst, XMMRegister nds, XMMRegister src) {
4905 assert(VM_Version::supports_avx(), "");
4906 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4907 attributes.set_rex_vex_w_reverted();
4908 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4909 emit_int16(0x59, (unsigned char)(0xC0 | encode));
4910 }
4911
4912 void Assembler::vmulss(XMMRegister dst, XMMRegister nds, Address src) {
4913 assert(VM_Version::supports_avx(), "");
4914 InstructionMark im(this);
4915 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4916 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
4917 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4918 emit_int8(0x59);
4919 emit_operand(dst, src);
4920 }
4921
4922 void Assembler::vmulss(XMMRegister dst, XMMRegister nds, XMMRegister src) {
4923 assert(VM_Version::supports_avx(), "");
4924 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4925 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4926 emit_int16(0x59, (unsigned char)(0xC0 | encode));
4927 }
4928
4929 void Assembler::vsubsd(XMMRegister dst, XMMRegister nds, Address src) {
4930 assert(VM_Version::supports_avx(), "");
4931 InstructionMark im(this);
4932 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4933 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
4934 attributes.set_rex_vex_w_reverted();
4935 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4936 emit_int8(0x5C);
4937 emit_operand(dst, src);
4938 }
4939
4940 void Assembler::vsubsd(XMMRegister dst, XMMRegister nds, XMMRegister src) {
4941 assert(VM_Version::supports_avx(), "");
4942 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4943 attributes.set_rex_vex_w_reverted();
4944 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4945 emit_int16(0x5C, (unsigned char)(0xC0 | encode));
4946 }
4947
4948 void Assembler::vsubss(XMMRegister dst, XMMRegister nds, Address src) {
4949 assert(VM_Version::supports_avx(), "");
4950 InstructionMark im(this);
4951 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4952 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
4953 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4954 emit_int8(0x5C);
4955 emit_operand(dst, src);
4956 }
4957
4958 void Assembler::vsubss(XMMRegister dst, XMMRegister nds, XMMRegister src) {
4959 assert(VM_Version::supports_avx(), "");
4960 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4961 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4962 emit_int16(0x5C, (unsigned char)(0xC0 | encode));
4963 }
4964
4965 //====================VECTOR ARITHMETIC=====================================
4966
4967 // Float-point vector arithmetic
4968
4969 void Assembler::addpd(XMMRegister dst, XMMRegister src) {
4970 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4971 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
4972 attributes.set_rex_vex_w_reverted();
4973 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4974 emit_int16(0x58, (unsigned char)(0xC0 | encode));
4975 }
4976
4977 void Assembler::addpd(XMMRegister dst, Address src) {
4978 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4979 InstructionMark im(this);
4980 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
4981 attributes.set_rex_vex_w_reverted();
4982 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
4983 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4984 emit_int8(0x58);
4985 emit_operand(dst, src);
4986 }
4987
4988
4989 void Assembler::addps(XMMRegister dst, XMMRegister src) {
4990 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4991 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
4992 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4993 emit_int16(0x58, (unsigned char)(0xC0 | encode));
4994 }
4995
4996 void Assembler::vaddpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4997 assert(VM_Version::supports_avx(), "");
4998 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
4999 attributes.set_rex_vex_w_reverted();
5000 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5001 emit_int16(0x58, (unsigned char)(0xC0 | encode));
5002 }
5003
5004 void Assembler::vaddps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5005 assert(VM_Version::supports_avx(), "");
5006 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5007 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5008 emit_int16(0x58, (unsigned char)(0xC0 | encode));
5009 }
5010
5011 void Assembler::vaddpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5012 assert(VM_Version::supports_avx(), "");
5013 InstructionMark im(this);
5014 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5015 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
5016 attributes.set_rex_vex_w_reverted();
5017 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5018 emit_int8(0x58);
5019 emit_operand(dst, src);
5020 }
5021
5022 void Assembler::vaddps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5023 assert(VM_Version::supports_avx(), "");
5024 InstructionMark im(this);
5025 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5026 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
5027 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5028 emit_int8(0x58);
5029 emit_operand(dst, src);
5030 }
5031
5032 void Assembler::subpd(XMMRegister dst, XMMRegister src) {
5033 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5034 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5035 attributes.set_rex_vex_w_reverted();
5036 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5037 emit_int16(0x5C, (unsigned char)(0xC0 | encode));
5038 }
5039
5040 void Assembler::subps(XMMRegister dst, XMMRegister src) {
5041 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5042 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5043 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5044 emit_int16(0x5C, (unsigned char)(0xC0 | encode));
5045 }
5046
5047 void Assembler::vsubpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5048 assert(VM_Version::supports_avx(), "");
5049 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5050 attributes.set_rex_vex_w_reverted();
5051 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5052 emit_int16(0x5C, (unsigned char)(0xC0 | encode));
5053 }
5054
5055 void Assembler::vsubps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5056 assert(VM_Version::supports_avx(), "");
5057 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5058 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5059 emit_int16(0x5C, (unsigned char)(0xC0 | encode));
5060 }
5061
5062 void Assembler::vsubpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5063 assert(VM_Version::supports_avx(), "");
5064 InstructionMark im(this);
5065 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5066 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
5067 attributes.set_rex_vex_w_reverted();
5068 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5069 emit_int8(0x5C);
5070 emit_operand(dst, src);
5071 }
5072
5073 void Assembler::vsubps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5074 assert(VM_Version::supports_avx(), "");
5075 InstructionMark im(this);
5076 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5077 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
5078 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5079 emit_int8(0x5C);
5080 emit_operand(dst, src);
5081 }
5082
5083 void Assembler::mulpd(XMMRegister dst, XMMRegister src) {
5084 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5085 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5086 attributes.set_rex_vex_w_reverted();
5087 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5088 emit_int16(0x59, (unsigned char)(0xC0 | encode));
5089 }
5090
5091 void Assembler::mulpd(XMMRegister dst, Address src) {
5092 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5093 InstructionMark im(this);
5094 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5095 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
5096 attributes.set_rex_vex_w_reverted();
5097 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5098 emit_int8(0x59);
5099 emit_operand(dst, src);
5100 }
5101
5102 void Assembler::mulps(XMMRegister dst, XMMRegister src) {
5103 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5104 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5105 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5106 emit_int16(0x59, (unsigned char)(0xC0 | encode));
5107 }
5108
5109 void Assembler::vmulpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5110 assert(VM_Version::supports_avx(), "");
5111 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5112 attributes.set_rex_vex_w_reverted();
5113 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5114 emit_int16(0x59, (unsigned char)(0xC0 | encode));
5115 }
5116
5117 void Assembler::vmulps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5118 assert(VM_Version::supports_avx(), "");
5119 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5120 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5121 emit_int16(0x59, (unsigned char)(0xC0 | encode));
5122 }
5123
5124 void Assembler::vmulpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5125 assert(VM_Version::supports_avx(), "");
5126 InstructionMark im(this);
5127 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5128 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
5129 attributes.set_rex_vex_w_reverted();
5130 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5131 emit_int8(0x59);
5132 emit_operand(dst, src);
5133 }
5134
5135 void Assembler::vmulps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5136 assert(VM_Version::supports_avx(), "");
5137 InstructionMark im(this);
5138 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5139 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
5140 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5141 emit_int8(0x59);
5142 emit_operand(dst, src);
5143 }
5144
5145 void Assembler::vfmadd231pd(XMMRegister dst, XMMRegister src1, XMMRegister src2, int vector_len) {
5146 assert(VM_Version::supports_fma(), "");
5147 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5148 int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5149 emit_int16((unsigned char)0xB8, (unsigned char)(0xC0 | encode));
5150 }
5151
5152 void Assembler::vfmadd231ps(XMMRegister dst, XMMRegister src1, XMMRegister src2, int vector_len) {
5153 assert(VM_Version::supports_fma(), "");
5154 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5155 int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5156 emit_int16((unsigned char)0xB8, (unsigned char)(0xC0 | encode));
5157 }
5158
5159 void Assembler::vfmadd231pd(XMMRegister dst, XMMRegister src1, Address src2, int vector_len) {
5160 assert(VM_Version::supports_fma(), "");
5161 InstructionMark im(this);
5162 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5163 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
5164 vex_prefix(src2, src1->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5165 emit_int8((unsigned char)0xB8);
5166 emit_operand(dst, src2);
5167 }
5168
5169 void Assembler::vfmadd231ps(XMMRegister dst, XMMRegister src1, Address src2, int vector_len) {
5170 assert(VM_Version::supports_fma(), "");
5171 InstructionMark im(this);
5172 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5173 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
5174 vex_prefix(src2, src1->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5175 emit_int8((unsigned char)0xB8);
5176 emit_operand(dst, src2);
5177 }
5178
5179 void Assembler::divpd(XMMRegister dst, XMMRegister src) {
5180 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5181 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5182 attributes.set_rex_vex_w_reverted();
5183 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5184 emit_int16(0x5E, (unsigned char)(0xC0 | encode));
5185 }
5186
5187 void Assembler::divps(XMMRegister dst, XMMRegister src) {
5188 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5189 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5190 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5191 emit_int16(0x5E, (unsigned char)(0xC0 | encode));
5192 }
5193
5194 void Assembler::vdivpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5195 assert(VM_Version::supports_avx(), "");
5196 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5197 attributes.set_rex_vex_w_reverted();
5198 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5199 emit_int16(0x5E, (unsigned char)(0xC0 | encode));
5200 }
5201
5202 void Assembler::vdivps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5203 assert(VM_Version::supports_avx(), "");
5204 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5205 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5206 emit_int16(0x5E, (unsigned char)(0xC0 | encode));
5207 }
5208
5209 void Assembler::vdivpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5210 assert(VM_Version::supports_avx(), "");
5211 InstructionMark im(this);
5212 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5213 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
5214 attributes.set_rex_vex_w_reverted();
5215 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5216 emit_int8(0x5E);
5217 emit_operand(dst, src);
5218 }
5219
5220 void Assembler::vdivps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5221 assert(VM_Version::supports_avx(), "");
5222 InstructionMark im(this);
5223 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5224 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
5225 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5226 emit_int8(0x5E);
5227 emit_operand(dst, src);
5228 }
5229
5230 void Assembler::vroundpd(XMMRegister dst, XMMRegister src, int32_t rmode, int vector_len) {
5231 assert(VM_Version::supports_avx(), "");
5232 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
5233 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
5234 emit_int24(0x09, (unsigned char)(0xC0 | encode), (unsigned char)(rmode));
5235 }
5236
5237 void Assembler::vroundpd(XMMRegister dst, Address src, int32_t rmode, int vector_len) {
5238 assert(VM_Version::supports_avx(), "");
5239 InstructionMark im(this);
5240 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
5241 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
5242 emit_int8(0x09);
5243 emit_operand(dst, src);
5244 emit_int8((unsigned char)(rmode));
5245 }
5246
5247 void Assembler::vrndscalepd(XMMRegister dst, XMMRegister src, int32_t rmode, int vector_len) {
5248 assert(VM_Version::supports_evex(), "requires EVEX support");
5249 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5250 attributes.set_is_evex_instruction();
5251 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
5252 emit_int24((unsigned char)0x09, (unsigned char)(0xC0 | encode), (unsigned char)(rmode));
5253 }
5254
5255 void Assembler::vrndscalepd(XMMRegister dst, Address src, int32_t rmode, int vector_len) {
5256 assert(VM_Version::supports_evex(), "requires EVEX support");
5257 assert(dst != xnoreg, "sanity");
5258 InstructionMark im(this);
5259 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5260 attributes.set_is_evex_instruction();
5261 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
5262 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
5263 emit_int8((unsigned char)0x09);
5264 emit_operand(dst, src);
5265 emit_int8((unsigned char)(rmode));
5266 }
5267
5268
5269 void Assembler::vsqrtpd(XMMRegister dst, XMMRegister src, int vector_len) {
5270 assert(VM_Version::supports_avx(), "");
5271 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5272 attributes.set_rex_vex_w_reverted();
5273 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5274 emit_int16(0x51, (unsigned char)(0xC0 | encode));
5275 }
5276
5277 void Assembler::vsqrtpd(XMMRegister dst, Address src, int vector_len) {
5278 assert(VM_Version::supports_avx(), "");
5279 InstructionMark im(this);
5280 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5281 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
5282 attributes.set_rex_vex_w_reverted();
5283 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5284 emit_int8(0x51);
5285 emit_operand(dst, src);
5286 }
5287
5288 void Assembler::vsqrtps(XMMRegister dst, XMMRegister src, int vector_len) {
5289 assert(VM_Version::supports_avx(), "");
5290 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5291 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5292 emit_int16(0x51, (unsigned char)(0xC0 | encode));
5293 }
5294
5295 void Assembler::vsqrtps(XMMRegister dst, Address src, int vector_len) {
5296 assert(VM_Version::supports_avx(), "");
5297 InstructionMark im(this);
5298 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5299 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
5300 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5301 emit_int8(0x51);
5302 emit_operand(dst, src);
5303 }
5304
5305 void Assembler::andpd(XMMRegister dst, XMMRegister src) {
5306 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5307 InstructionAttr attributes(AVX_128bit, /* rex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true);
5308 attributes.set_rex_vex_w_reverted();
5309 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5310 emit_int16(0x54, (unsigned char)(0xC0 | encode));
5311 }
5312
5313 void Assembler::andps(XMMRegister dst, XMMRegister src) {
5314 NOT_LP64(assert(VM_Version::supports_sse(), ""));
5315 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true);
5316 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5317 emit_int16(0x54, (unsigned char)(0xC0 | encode));
5318 }
5319
5320 void Assembler::andps(XMMRegister dst, Address src) {
5321 NOT_LP64(assert(VM_Version::supports_sse(), ""));
5322 InstructionMark im(this);
5323 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true);
5324 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
5325 simd_prefix(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5326 emit_int8(0x54);
5327 emit_operand(dst, src);
5328 }
5329
5330 void Assembler::andpd(XMMRegister dst, Address src) {
5331 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5332 InstructionMark im(this);
5333 InstructionAttr attributes(AVX_128bit, /* rex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true);
5334 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
5335 attributes.set_rex_vex_w_reverted();
5336 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5337 emit_int8(0x54);
5338 emit_operand(dst, src);
5339 }
5340
5341 void Assembler::vandpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5342 assert(VM_Version::supports_avx(), "");
5343 InstructionAttr attributes(vector_len, /* vex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true);
5344 attributes.set_rex_vex_w_reverted();
5345 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5346 emit_int16(0x54, (unsigned char)(0xC0 | encode));
5347 }
5348
5349 void Assembler::vandps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5350 assert(VM_Version::supports_avx(), "");
5351 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true);
5352 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5353 emit_int16(0x54, (unsigned char)(0xC0 | encode));
5354 }
5355
5356 void Assembler::vandpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5357 assert(VM_Version::supports_avx(), "");
5358 InstructionMark im(this);
5359 InstructionAttr attributes(vector_len, /* vex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true);
5360 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
5361 attributes.set_rex_vex_w_reverted();
5362 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5363 emit_int8(0x54);
5364 emit_operand(dst, src);
5365 }
5366
5367 void Assembler::vandps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5368 assert(VM_Version::supports_avx(), "");
5369 InstructionMark im(this);
5370 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true);
5371 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
5372 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5373 emit_int8(0x54);
5374 emit_operand(dst, src);
5375 }
5376
5377 void Assembler::unpckhpd(XMMRegister dst, XMMRegister src) {
5378 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5379 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5380 attributes.set_rex_vex_w_reverted();
5381 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5382 emit_int8(0x15);
5383 emit_int8((unsigned char)(0xC0 | encode));
5384 }
5385
5386 void Assembler::unpcklpd(XMMRegister dst, XMMRegister src) {
5387 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5388 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5389 attributes.set_rex_vex_w_reverted();
5390 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5391 emit_int16(0x14, (unsigned char)(0xC0 | encode));
5392 }
5393
5394 void Assembler::xorpd(XMMRegister dst, XMMRegister src) {
5395 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5396 InstructionAttr attributes(AVX_128bit, /* rex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true);
5397 attributes.set_rex_vex_w_reverted();
5398 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5399 emit_int16(0x57, (unsigned char)(0xC0 | encode));
5400 }
5401
5402 void Assembler::xorps(XMMRegister dst, XMMRegister src) {
5403 NOT_LP64(assert(VM_Version::supports_sse(), ""));
5404 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true);
5405 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5406 emit_int16(0x57, (unsigned char)(0xC0 | encode));
5407 }
5408
5409 void Assembler::xorpd(XMMRegister dst, Address src) {
5410 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5411 InstructionMark im(this);
5412 InstructionAttr attributes(AVX_128bit, /* rex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true);
5413 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
5414 attributes.set_rex_vex_w_reverted();
5415 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5416 emit_int8(0x57);
5417 emit_operand(dst, src);
5418 }
5419
5420 void Assembler::xorps(XMMRegister dst, Address src) {
5421 NOT_LP64(assert(VM_Version::supports_sse(), ""));
5422 InstructionMark im(this);
5423 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true);
5424 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
5425 simd_prefix(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5426 emit_int8(0x57);
5427 emit_operand(dst, src);
5428 }
5429
5430 void Assembler::vxorpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5431 assert(VM_Version::supports_avx(), "");
5432 InstructionAttr attributes(vector_len, /* vex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true);
5433 attributes.set_rex_vex_w_reverted();
5434 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5435 emit_int16(0x57, (unsigned char)(0xC0 | encode));
5436 }
5437
5438 void Assembler::vxorps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5439 assert(VM_Version::supports_avx(), "");
5440 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true);
5441 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5442 emit_int16(0x57, (unsigned char)(0xC0 | encode));
5443 }
5444
5445 void Assembler::vxorpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5446 assert(VM_Version::supports_avx(), "");
5447 InstructionMark im(this);
5448 InstructionAttr attributes(vector_len, /* vex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true);
5449 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
5450 attributes.set_rex_vex_w_reverted();
5451 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5452 emit_int8(0x57);
5453 emit_operand(dst, src);
5454 }
5455
5456 void Assembler::vxorps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5457 assert(VM_Version::supports_avx(), "");
5458 InstructionMark im(this);
5459 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true);
5460 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
5461 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5462 emit_int8(0x57);
5463 emit_operand(dst, src);
5464 }
5465
5466 // Integer vector arithmetic
5467 void Assembler::vphaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5468 assert(VM_Version::supports_avx() && (vector_len == 0) ||
5469 VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
5470 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ true);
5471 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5472 emit_int16(0x01, (unsigned char)(0xC0 | encode));
5473 }
5474
5475 void Assembler::vphaddd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5476 assert(VM_Version::supports_avx() && (vector_len == 0) ||
5477 VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
5478 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ true);
5479 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5480 emit_int16(0x02, (unsigned char)(0xC0 | encode));
5481 }
5482
5483 void Assembler::paddb(XMMRegister dst, XMMRegister src) {
5484 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5485 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5486 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5487 emit_int16((unsigned char)0xFC, (unsigned char)(0xC0 | encode));
5488 }
5489
5490 void Assembler::paddw(XMMRegister dst, XMMRegister src) {
5491 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5492 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5493 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5494 emit_int16((unsigned char)0xFD, (unsigned char)(0xC0 | encode));
5495 }
5496
5497 void Assembler::paddd(XMMRegister dst, XMMRegister src) {
5498 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5499 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5500 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5501 emit_int16((unsigned char)0xFE, (unsigned char)(0xC0 | encode));
5502 }
5503
5504 void Assembler::paddd(XMMRegister dst, Address src) {
5505 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5506 InstructionMark im(this);
5507 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5508 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5509 emit_int8((unsigned char)0xFE);
5510 emit_operand(dst, src);
5511 }
5512
5513 void Assembler::paddq(XMMRegister dst, XMMRegister src) {
5514 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5515 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5516 attributes.set_rex_vex_w_reverted();
5517 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5518 emit_int16((unsigned char)0xD4, (unsigned char)(0xC0 | encode));
5519 }
5520
5521 void Assembler::phaddw(XMMRegister dst, XMMRegister src) {
5522 assert(VM_Version::supports_sse3(), "");
5523 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ true);
5524 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5525 emit_int16(0x01, (unsigned char)(0xC0 | encode));
5526 }
5527
5528 void Assembler::phaddd(XMMRegister dst, XMMRegister src) {
5529 assert(VM_Version::supports_sse3(), "");
5530 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ true);
5531 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5532 emit_int16(0x02, (unsigned char)(0xC0 | encode));
5533 }
5534
5535 void Assembler::vpaddb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5536 assert(UseAVX > 0, "requires some form of AVX");
5537 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5538 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5539 emit_int16((unsigned char)0xFC, (unsigned char)(0xC0 | encode));
5540 }
5541
5542 void Assembler::vpaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5543 assert(UseAVX > 0, "requires some form of AVX");
5544 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5545 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5546 emit_int16((unsigned char)0xFD, (unsigned char)(0xC0 | encode));
5547 }
5548
5549 void Assembler::vpaddd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5550 assert(UseAVX > 0, "requires some form of AVX");
5551 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5552 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5553 emit_int16((unsigned char)0xFE, (unsigned char)(0xC0 | encode));
5554 }
5555
5556 void Assembler::vpaddq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5557 assert(UseAVX > 0, "requires some form of AVX");
5558 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5559 attributes.set_rex_vex_w_reverted();
5560 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5561 emit_int16((unsigned char)0xD4, (unsigned char)(0xC0 | encode));
5562 }
5563
5564 void Assembler::vpaddb(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5565 assert(UseAVX > 0, "requires some form of AVX");
5566 InstructionMark im(this);
5567 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5568 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
5569 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5570 emit_int8((unsigned char)0xFC);
5571 emit_operand(dst, src);
5572 }
5573
5574 void Assembler::vpaddw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5575 assert(UseAVX > 0, "requires some form of AVX");
5576 InstructionMark im(this);
5577 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5578 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
5579 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5580 emit_int8((unsigned char)0xFD);
5581 emit_operand(dst, src);
5589 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5590 emit_int8((unsigned char)0xFE);
5591 emit_operand(dst, src);
5592 }
5593
5594 void Assembler::vpaddq(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5595 assert(UseAVX > 0, "requires some form of AVX");
5596 InstructionMark im(this);
5597 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5598 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
5599 attributes.set_rex_vex_w_reverted();
5600 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5601 emit_int8((unsigned char)0xD4);
5602 emit_operand(dst, src);
5603 }
5604
5605 void Assembler::psubb(XMMRegister dst, XMMRegister src) {
5606 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5607 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5608 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5609 emit_int16((unsigned char)0xF8, (unsigned char)(0xC0 | encode));
5610 }
5611
5612 void Assembler::psubw(XMMRegister dst, XMMRegister src) {
5613 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5614 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5615 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5616 emit_int16((unsigned char)0xF9, (unsigned char)(0xC0 | encode));
5617 }
5618
5619 void Assembler::psubd(XMMRegister dst, XMMRegister src) {
5620 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5621 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5622 emit_int16((unsigned char)0xFA, (unsigned char)(0xC0 | encode));
5623 }
5624
5625 void Assembler::psubq(XMMRegister dst, XMMRegister src) {
5626 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5627 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5628 attributes.set_rex_vex_w_reverted();
5629 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5630 emit_int8((unsigned char)0xFB);
5631 emit_int8((unsigned char)(0xC0 | encode));
5632 }
5633
5634 void Assembler::vpsubb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5635 assert(UseAVX > 0, "requires some form of AVX");
5636 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5637 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5638 emit_int16((unsigned char)0xF8, (unsigned char)(0xC0 | encode));
5639 }
5640
5641 void Assembler::vpsubw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5642 assert(UseAVX > 0, "requires some form of AVX");
5643 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5644 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5645 emit_int16((unsigned char)0xF9, (unsigned char)(0xC0 | encode));
5646 }
5647
5648 void Assembler::vpsubd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5649 assert(UseAVX > 0, "requires some form of AVX");
5650 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5651 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5652 emit_int16((unsigned char)0xFA, (unsigned char)(0xC0 | encode));
5653 }
5654
5655 void Assembler::vpsubq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5656 assert(UseAVX > 0, "requires some form of AVX");
5657 InstructionAttr attributes(vector_len, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5658 attributes.set_rex_vex_w_reverted();
5659 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5660 emit_int16((unsigned char)0xFB, (unsigned char)(0xC0 | encode));
5661 }
5662
5663 void Assembler::vpsubb(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5664 assert(UseAVX > 0, "requires some form of AVX");
5665 InstructionMark im(this);
5666 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5667 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
5668 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5669 emit_int8((unsigned char)0xF8);
5670 emit_operand(dst, src);
5671 }
5672
5673 void Assembler::vpsubw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5674 assert(UseAVX > 0, "requires some form of AVX");
5675 InstructionMark im(this);
5676 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5677 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
5678 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5679 emit_int8((unsigned char)0xF9);
5680 emit_operand(dst, src);
5688 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5689 emit_int8((unsigned char)0xFA);
5690 emit_operand(dst, src);
5691 }
5692
5693 void Assembler::vpsubq(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5694 assert(UseAVX > 0, "requires some form of AVX");
5695 InstructionMark im(this);
5696 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5697 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
5698 attributes.set_rex_vex_w_reverted();
5699 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5700 emit_int8((unsigned char)0xFB);
5701 emit_operand(dst, src);
5702 }
5703
5704 void Assembler::pmullw(XMMRegister dst, XMMRegister src) {
5705 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5706 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5707 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5708 emit_int16((unsigned char)0xD5, (unsigned char)(0xC0 | encode));
5709 }
5710
5711 void Assembler::pmulld(XMMRegister dst, XMMRegister src) {
5712 assert(VM_Version::supports_sse4_1(), "");
5713 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5714 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5715 emit_int16(0x40, (unsigned char)(0xC0 | encode));
5716 }
5717
5718 void Assembler::vpmullw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5719 assert(UseAVX > 0, "requires some form of AVX");
5720 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5721 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5722 emit_int16((unsigned char)0xD5, (unsigned char)(0xC0 | encode));
5723 }
5724
5725 void Assembler::vpmulld(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5726 assert(UseAVX > 0, "requires some form of AVX");
5727 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5728 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5729 emit_int16(0x40, (unsigned char)(0xC0 | encode));
5730 }
5731
5732 void Assembler::vpmullq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5733 assert(UseAVX > 2, "requires some form of EVEX");
5734 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true);
5735 attributes.set_is_evex_instruction();
5736 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5737 emit_int16(0x40, (unsigned char)(0xC0 | encode));
5738 }
5739
5740 void Assembler::vpmullw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5741 assert(UseAVX > 0, "requires some form of AVX");
5742 InstructionMark im(this);
5743 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5744 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
5745 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5746 emit_int8((unsigned char)0xD5);
5747 emit_operand(dst, src);
5748 }
5749
5750 void Assembler::vpmulld(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5751 assert(UseAVX > 0, "requires some form of AVX");
5752 InstructionMark im(this);
5753 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5754 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
5755 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5756 emit_int8(0x40);
5757 emit_operand(dst, src);
5758 }
5759
5760 void Assembler::vpmullq(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5761 assert(UseAVX > 2, "requires some form of EVEX");
5762 InstructionMark im(this);
5763 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true);
5764 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
5765 attributes.set_is_evex_instruction();
5766 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5767 emit_int8(0x40);
5768 emit_operand(dst, src);
5769 }
5770
5771 // Shift packed integers left by specified number of bits.
5772 void Assembler::psllw(XMMRegister dst, int shift) {
5773 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5774 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5775 // XMM6 is for /6 encoding: 66 0F 71 /6 ib
5776 int encode = simd_prefix_and_encode(xmm6, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5777 emit_int24(0x71, (unsigned char)(0xC0 | encode), shift & 0xFF);
5778 }
5779
5780 void Assembler::pslld(XMMRegister dst, int shift) {
5781 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5782 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5783 // XMM6 is for /6 encoding: 66 0F 72 /6 ib
5784 int encode = simd_prefix_and_encode(xmm6, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5785 emit_int24(0x72, (unsigned char)(0xC0 | encode), shift & 0xFF);
5786 }
5787
5788 void Assembler::psllq(XMMRegister dst, int shift) {
5789 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5790 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5791 // XMM6 is for /6 encoding: 66 0F 73 /6 ib
5792 int encode = simd_prefix_and_encode(xmm6, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5793 emit_int24(0x73, (unsigned char)(0xC0 | encode), shift & 0xFF);
5794 }
5795
5796 void Assembler::psllw(XMMRegister dst, XMMRegister shift) {
5797 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5798 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5799 int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5800 emit_int16((unsigned char)0xF1, (unsigned char)(0xC0 | encode));
5801 }
5802
5803 void Assembler::pslld(XMMRegister dst, XMMRegister shift) {
5804 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5805 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5806 int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5807 emit_int16((unsigned char)0xF2, (unsigned char)(0xC0 | encode));
5808 }
5809
5810 void Assembler::psllq(XMMRegister dst, XMMRegister shift) {
5811 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5812 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5813 attributes.set_rex_vex_w_reverted();
5814 int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5815 emit_int16((unsigned char)0xF3, (unsigned char)(0xC0 | encode));
5816 }
5817
5818 void Assembler::vpsllw(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
5819 assert(UseAVX > 0, "requires some form of AVX");
5820 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5821 // XMM6 is for /6 encoding: 66 0F 71 /6 ib
5822 int encode = vex_prefix_and_encode(xmm6->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5823 emit_int24(0x71, (unsigned char)(0xC0 | encode), shift & 0xFF);
5824 }
5825
5826 void Assembler::vpslld(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
5827 assert(UseAVX > 0, "requires some form of AVX");
5828 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5829 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5830 // XMM6 is for /6 encoding: 66 0F 72 /6 ib
5831 int encode = vex_prefix_and_encode(xmm6->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5832 emit_int24(0x72, (unsigned char)(0xC0 | encode), shift & 0xFF);
5833 }
5834
5835 void Assembler::vpsllq(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
5836 assert(UseAVX > 0, "requires some form of AVX");
5837 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5838 attributes.set_rex_vex_w_reverted();
5839 // XMM6 is for /6 encoding: 66 0F 73 /6 ib
5840 int encode = vex_prefix_and_encode(xmm6->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5841 emit_int24(0x73, (unsigned char)(0xC0 | encode), shift & 0xFF);
5842 }
5843
5844 void Assembler::vpsllw(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
5845 assert(UseAVX > 0, "requires some form of AVX");
5846 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5847 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5848 emit_int16((unsigned char)0xF1, (unsigned char)(0xC0 | encode));
5849 }
5850
5851 void Assembler::vpslld(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
5852 assert(UseAVX > 0, "requires some form of AVX");
5853 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5854 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5855 emit_int16((unsigned char)0xF2, (unsigned char)(0xC0 | encode));
5856 }
5857
5858 void Assembler::vpsllq(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
5859 assert(UseAVX > 0, "requires some form of AVX");
5860 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5861 attributes.set_rex_vex_w_reverted();
5862 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5863 emit_int16((unsigned char)0xF3, (unsigned char)(0xC0 | encode));
5864 }
5865
5866 // Shift packed integers logically right by specified number of bits.
5867 void Assembler::psrlw(XMMRegister dst, int shift) {
5868 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5869 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5870 // XMM2 is for /2 encoding: 66 0F 71 /2 ib
5871 int encode = simd_prefix_and_encode(xmm2, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5872 emit_int24(0x71, (unsigned char)(0xC0 | encode), shift & 0xFF);
5873 }
5874
5875 void Assembler::psrld(XMMRegister dst, int shift) {
5876 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5877 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5878 // XMM2 is for /2 encoding: 66 0F 72 /2 ib
5879 int encode = simd_prefix_and_encode(xmm2, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5880 emit_int24(0x72, (unsigned char)(0xC0 | encode), shift & 0xFF);
5881 }
5882
5883 void Assembler::psrlq(XMMRegister dst, int shift) {
5884 // Do not confuse it with psrldq SSE2 instruction which
5885 // shifts 128 bit value in xmm register by number of bytes.
5886 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5887 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5888 attributes.set_rex_vex_w_reverted();
5889 // XMM2 is for /2 encoding: 66 0F 73 /2 ib
5890 int encode = simd_prefix_and_encode(xmm2, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5891 emit_int24(0x73, (unsigned char)(0xC0 | encode), shift & 0xFF);
5892 }
5893
5894 void Assembler::psrlw(XMMRegister dst, XMMRegister shift) {
5895 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5896 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5897 int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5898 emit_int16((unsigned char)0xD1, (unsigned char)(0xC0 | encode));
5899 }
5900
5901 void Assembler::psrld(XMMRegister dst, XMMRegister shift) {
5902 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5903 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5904 int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5905 emit_int16((unsigned char)0xD2, (unsigned char)(0xC0 | encode));
5906 }
5907
5908 void Assembler::psrlq(XMMRegister dst, XMMRegister shift) {
5909 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5910 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5911 attributes.set_rex_vex_w_reverted();
5912 int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5913 emit_int16((unsigned char)0xD3, (unsigned char)(0xC0 | encode));
5914 }
5915
5916 void Assembler::vpsrlw(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
5917 assert(UseAVX > 0, "requires some form of AVX");
5918 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5919 // XMM2 is for /2 encoding: 66 0F 71 /2 ib
5920 int encode = vex_prefix_and_encode(xmm2->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5921 emit_int24(0x71, (unsigned char)(0xC0 | encode), shift & 0xFF);
5922 }
5923
5924 void Assembler::vpsrld(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
5925 assert(UseAVX > 0, "requires some form of AVX");
5926 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5927 // XMM2 is for /2 encoding: 66 0F 72 /2 ib
5928 int encode = vex_prefix_and_encode(xmm2->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5929 emit_int24(0x72, (unsigned char)(0xC0 | encode), shift & 0xFF);
5930 }
5931
5932 void Assembler::vpsrlq(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
5933 assert(UseAVX > 0, "requires some form of AVX");
5934 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5935 attributes.set_rex_vex_w_reverted();
5936 // XMM2 is for /2 encoding: 66 0F 73 /2 ib
5937 int encode = vex_prefix_and_encode(xmm2->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5938 emit_int24(0x73, (unsigned char)(0xC0 | encode), shift & 0xFF);
5939 }
5940
5941 void Assembler::vpsrlw(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
5942 assert(UseAVX > 0, "requires some form of AVX");
5943 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5944 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5945 emit_int16((unsigned char)0xD1, (unsigned char)(0xC0 | encode));
5946 }
5947
5948 void Assembler::vpsrld(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
5949 assert(UseAVX > 0, "requires some form of AVX");
5950 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5951 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5952 emit_int16((unsigned char)0xD2, (unsigned char)(0xC0 | encode));
5953 }
5954
5955 void Assembler::vpsrlq(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
5956 assert(UseAVX > 0, "requires some form of AVX");
5957 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5958 attributes.set_rex_vex_w_reverted();
5959 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5960 emit_int16((unsigned char)0xD3, (unsigned char)(0xC0 | encode));
5961 }
5962
5963 void Assembler::evpsrlvw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5964 assert(VM_Version::supports_avx512bw(), "");
5965 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5966 attributes.set_is_evex_instruction();
5967 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5968 emit_int16(0x10, (unsigned char)(0xC0 | encode));
5969 }
5970
5971 void Assembler::evpsllvw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5972 assert(VM_Version::supports_avx512bw(), "");
5973 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5974 attributes.set_is_evex_instruction();
5975 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5976 emit_int16(0x12, (unsigned char)(0xC0 | encode));
5977 }
5978
5979 // Shift packed integers arithmetically right by specified number of bits.
5980 void Assembler::psraw(XMMRegister dst, int shift) {
5981 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5982 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5983 // XMM4 is for /4 encoding: 66 0F 71 /4 ib
5984 int encode = simd_prefix_and_encode(xmm4, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5985 emit_int24(0x71, (unsigned char)(0xC0 | encode), shift & 0xFF);
5986 }
5987
5988 void Assembler::psrad(XMMRegister dst, int shift) {
5989 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5990 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5991 // XMM4 is for /4 encoding: 66 0F 72 /4 ib
5992 int encode = simd_prefix_and_encode(xmm4, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5993 emit_int8(0x72);
5994 emit_int8((unsigned char)(0xC0 | encode));
5995 emit_int8(shift & 0xFF);
5996 }
5997
5998 void Assembler::psraw(XMMRegister dst, XMMRegister shift) {
5999 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6000 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
6001 int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6002 emit_int16((unsigned char)0xE1, (unsigned char)(0xC0 | encode));
6003 }
6004
6005 void Assembler::psrad(XMMRegister dst, XMMRegister shift) {
6006 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6007 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6008 int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6009 emit_int16((unsigned char)0xE2, (unsigned char)(0xC0 | encode));
6010 }
6011
6012 void Assembler::vpsraw(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
6013 assert(UseAVX > 0, "requires some form of AVX");
6014 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
6015 // XMM4 is for /4 encoding: 66 0F 71 /4 ib
6016 int encode = vex_prefix_and_encode(xmm4->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6017 emit_int24(0x71, (unsigned char)(0xC0 | encode), shift & 0xFF);
6018 }
6019
6020 void Assembler::vpsrad(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
6021 assert(UseAVX > 0, "requires some form of AVX");
6022 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6023 // XMM4 is for /4 encoding: 66 0F 71 /4 ib
6024 int encode = vex_prefix_and_encode(xmm4->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6025 emit_int24(0x72, (unsigned char)(0xC0 | encode), shift & 0xFF);
6026 }
6027
6028 void Assembler::vpsraw(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
6029 assert(UseAVX > 0, "requires some form of AVX");
6030 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
6031 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6032 emit_int16((unsigned char)0xE1, (unsigned char)(0xC0 | encode));
6033 }
6034
6035 void Assembler::vpsrad(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
6036 assert(UseAVX > 0, "requires some form of AVX");
6037 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6038 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6039 emit_int16((unsigned char)0xE2, (unsigned char)(0xC0 | encode));
6040 }
6041
6042 void Assembler::evpsraq(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
6043 assert(UseAVX > 2, "requires AVX512");
6044 assert ((VM_Version::supports_avx512vl() || vector_len == 2), "requires AVX512vl");
6045 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6046 attributes.set_is_evex_instruction();
6047 int encode = vex_prefix_and_encode(xmm4->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6048 emit_int24((unsigned char)0x72, (unsigned char)(0xC0 | encode), shift & 0xFF);
6049 }
6050
6051 void Assembler::evpsraq(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
6052 assert(UseAVX > 2, "requires AVX512");
6053 assert ((VM_Version::supports_avx512vl() || vector_len == 2), "requires AVX512vl");
6054 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6055 attributes.set_is_evex_instruction();
6056 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6057 emit_int16((unsigned char)0xE2, (unsigned char)(0xC0 | encode));
6058 }
6059
6060 // logical operations packed integers
6061 void Assembler::pand(XMMRegister dst, XMMRegister src) {
6062 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6063 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6064 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6065 emit_int16((unsigned char)0xDB, (unsigned char)(0xC0 | encode));
6066 }
6067
6068 void Assembler::vpand(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
6069 assert(UseAVX > 0, "requires some form of AVX");
6070 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6071 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6072 emit_int16((unsigned char)0xDB, (unsigned char)(0xC0 | encode));
6073 }
6074
6075 void Assembler::vpand(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
6076 assert(UseAVX > 0, "requires some form of AVX");
6077 InstructionMark im(this);
6078 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6079 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
6080 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6081 emit_int8((unsigned char)0xDB);
6082 emit_operand(dst, src);
6083 }
6084
6085 void Assembler::vpandq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
6086 assert(VM_Version::supports_evex(), "");
6087 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6088 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6089 emit_int16((unsigned char)0xDB, (unsigned char)(0xC0 | encode));
6090 }
6091
6092 void Assembler::vpshldvd(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
6093 assert(VM_Version::supports_avx512_vbmi2(), "requires vbmi2");
6094 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6095 attributes.set_is_evex_instruction();
6096 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6097 emit_int8(0x71);
6098 emit_int8((unsigned char)(0xC0 | encode));
6099 }
6100
6101 void Assembler::vpshrdvd(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
6102 assert(VM_Version::supports_avx512_vbmi2(), "requires vbmi2");
6103 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6104 attributes.set_is_evex_instruction();
6105 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6106 emit_int16(0x73, (unsigned char)(0xC0 | encode));
6107 }
6108
6109 void Assembler::pandn(XMMRegister dst, XMMRegister src) {
6110 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6111 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6112 attributes.set_rex_vex_w_reverted();
6113 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6114 emit_int16((unsigned char)0xDF, (unsigned char)(0xC0 | encode));
6115 }
6116
6117 void Assembler::vpandn(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
6118 assert(UseAVX > 0, "requires some form of AVX");
6119 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6120 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6121 emit_int16((unsigned char)0xDF, (unsigned char)(0xC0 | encode));
6122 }
6123
6124
6125 void Assembler::por(XMMRegister dst, XMMRegister src) {
6126 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6127 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6128 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6129 emit_int16((unsigned char)0xEB, (unsigned char)(0xC0 | encode));
6130 }
6131
6132 void Assembler::vpor(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
6133 assert(UseAVX > 0, "requires some form of AVX");
6134 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6135 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6136 emit_int16((unsigned char)0xEB, (unsigned char)(0xC0 | encode));
6137 }
6138
6139 void Assembler::vpor(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
6140 assert(UseAVX > 0, "requires some form of AVX");
6141 InstructionMark im(this);
6142 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6143 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
6144 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6145 emit_int8((unsigned char)0xEB);
6146 emit_operand(dst, src);
6147 }
6148
6149 void Assembler::vporq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
6150 assert(VM_Version::supports_evex(), "");
6151 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6152 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6153 emit_int16((unsigned char)0xEB, (unsigned char)(0xC0 | encode));
6154 }
6155
6156
6157 void Assembler::pxor(XMMRegister dst, XMMRegister src) {
6158 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6159 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6160 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6161 emit_int16((unsigned char)0xEF, (unsigned char)(0xC0 | encode));
6162 }
6163
6164 void Assembler::vpxor(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
6165 assert(UseAVX > 0, "requires some form of AVX");
6166 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6167 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6168 emit_int16((unsigned char)0xEF, (unsigned char)(0xC0 | encode));
6169 }
6170
6171 void Assembler::vpxor(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
6172 assert(UseAVX > 0, "requires some form of AVX");
6173 InstructionMark im(this);
6174 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6175 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
6176 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6177 emit_int8((unsigned char)0xEF);
6178 emit_operand(dst, src);
6179 }
6180
6181 void Assembler::evpxorq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
6182 assert(VM_Version::supports_evex(), "requires EVEX support");
6183 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6184 attributes.set_is_evex_instruction();
6185 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6186 emit_int8((unsigned char)0xEF);
6187 emit_int8((unsigned char)(0xC0 | encode));
6188 }
6190 void Assembler::evpxorq(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
6191 assert(VM_Version::supports_evex(), "requires EVEX support");
6192 assert(dst != xnoreg, "sanity");
6193 InstructionMark im(this);
6194 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6195 attributes.set_is_evex_instruction();
6196 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
6197 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6198 emit_int8((unsigned char)0xEF);
6199 emit_operand(dst, src);
6200 }
6201
6202
6203 // vinserti forms
6204
6205 void Assembler::vinserti128(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8) {
6206 assert(VM_Version::supports_avx2(), "");
6207 assert(imm8 <= 0x01, "imm8: %u", imm8);
6208 InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6209 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6210 // last byte:
6211 // 0x00 - insert into lower 128 bits
6212 // 0x01 - insert into upper 128 bits
6213 emit_int24(0x38, (unsigned char)(0xC0 | encode), imm8 & 0x01);
6214 }
6215
6216 void Assembler::vinserti128(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8) {
6217 assert(VM_Version::supports_avx2(), "");
6218 assert(dst != xnoreg, "sanity");
6219 assert(imm8 <= 0x01, "imm8: %u", imm8);
6220 InstructionMark im(this);
6221 InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6222 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit);
6223 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6224 emit_int8(0x38);
6225 emit_operand(dst, src);
6226 // 0x00 - insert into lower 128 bits
6227 // 0x01 - insert into upper 128 bits
6228 emit_int8(imm8 & 0x01);
6229 }
6230
6231 void Assembler::vinserti32x4(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8) {
6232 assert(VM_Version::supports_evex(), "");
6233 assert(imm8 <= 0x03, "imm8: %u", imm8);
6234 InstructionAttr attributes(AVX_512bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6235 attributes.set_is_evex_instruction();
6236 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6237 // imm8:
6238 // 0x00 - insert into q0 128 bits (0..127)
6239 // 0x01 - insert into q1 128 bits (128..255)
6240 // 0x02 - insert into q2 128 bits (256..383)
6241 // 0x03 - insert into q3 128 bits (384..511)
6242 emit_int24(0x38, (unsigned char)(0xC0 | encode), imm8 & 0x03);
6243 }
6244
6245 void Assembler::vinserti32x4(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8) {
6246 assert(VM_Version::supports_avx(), "");
6247 assert(dst != xnoreg, "sanity");
6248 assert(imm8 <= 0x03, "imm8: %u", imm8);
6249 InstructionMark im(this);
6250 InstructionAttr attributes(AVX_512bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6251 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit);
6252 attributes.set_is_evex_instruction();
6253 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6254 emit_int8(0x18);
6255 emit_operand(dst, src);
6256 // 0x00 - insert into q0 128 bits (0..127)
6257 // 0x01 - insert into q1 128 bits (128..255)
6258 // 0x02 - insert into q2 128 bits (256..383)
6259 // 0x03 - insert into q3 128 bits (384..511)
6260 emit_int8(imm8 & 0x03);
6261 }
6262
6263 void Assembler::vinserti64x4(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8) {
6264 assert(VM_Version::supports_evex(), "");
6265 assert(imm8 <= 0x01, "imm8: %u", imm8);
6266 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6267 attributes.set_is_evex_instruction();
6268 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6269 //imm8:
6270 // 0x00 - insert into lower 256 bits
6271 // 0x01 - insert into upper 256 bits
6272 emit_int24(0x3A, (unsigned char)(0xC0 | encode), imm8 & 0x01);
6273 }
6274
6275
6276 // vinsertf forms
6277
6278 void Assembler::vinsertf128(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8) {
6279 assert(VM_Version::supports_avx(), "");
6280 assert(imm8 <= 0x01, "imm8: %u", imm8);
6281 InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6282 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6283 // imm8:
6284 // 0x00 - insert into lower 128 bits
6285 // 0x01 - insert into upper 128 bits
6286 emit_int24(0x18, (unsigned char)(0xC0 | encode), imm8 & 0x01);
6287 }
6288
6289 void Assembler::vinsertf128(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8) {
6290 assert(VM_Version::supports_avx(), "");
6291 assert(dst != xnoreg, "sanity");
6292 assert(imm8 <= 0x01, "imm8: %u", imm8);
6293 InstructionMark im(this);
6294 InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6295 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit);
6296 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6297 emit_int8(0x18);
6298 emit_operand(dst, src);
6299 // 0x00 - insert into lower 128 bits
6300 // 0x01 - insert into upper 128 bits
6301 emit_int8(imm8 & 0x01);
6302 }
6303
6304 void Assembler::vinsertf32x4(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8) {
6305 assert(VM_Version::supports_avx2(), "");
6306 assert(imm8 <= 0x03, "imm8: %u", imm8);
6307 InstructionAttr attributes(AVX_512bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6308 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6309 // imm8:
6310 // 0x00 - insert into q0 128 bits (0..127)
6311 // 0x01 - insert into q1 128 bits (128..255)
6312 // 0x02 - insert into q0 128 bits (256..383)
6313 // 0x03 - insert into q1 128 bits (384..512)
6314 emit_int24(0x18, (unsigned char)(0xC0 | encode), imm8 & 0x03);
6315 }
6316
6317 void Assembler::vinsertf32x4(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8) {
6318 assert(VM_Version::supports_avx(), "");
6319 assert(dst != xnoreg, "sanity");
6320 assert(imm8 <= 0x03, "imm8: %u", imm8);
6321 InstructionMark im(this);
6322 InstructionAttr attributes(AVX_512bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6323 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit);
6324 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6325 emit_int8(0x18);
6326 emit_operand(dst, src);
6327 // 0x00 - insert into q0 128 bits (0..127)
6328 // 0x01 - insert into q1 128 bits (128..255)
6329 // 0x02 - insert into q0 128 bits (256..383)
6330 // 0x03 - insert into q1 128 bits (384..512)
6331 emit_int8(imm8 & 0x03);
6332 }
6333
6334 void Assembler::vinsertf64x4(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8) {
6335 assert(VM_Version::supports_evex(), "");
6336 assert(imm8 <= 0x01, "imm8: %u", imm8);
6337 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6338 attributes.set_is_evex_instruction();
6339 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6340 // imm8:
6341 // 0x00 - insert into lower 256 bits
6342 // 0x01 - insert into upper 256 bits
6343 emit_int24(0x1A, (unsigned char)(0xC0 | encode), imm8 & 0x01);
6344 }
6345
6346 void Assembler::vinsertf64x4(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8) {
6347 assert(VM_Version::supports_evex(), "");
6348 assert(dst != xnoreg, "sanity");
6349 assert(imm8 <= 0x01, "imm8: %u", imm8);
6350 InstructionMark im(this);
6351 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6352 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_64bit);
6353 attributes.set_is_evex_instruction();
6354 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6355 emit_int8(0x1A);
6356 emit_operand(dst, src);
6357 // 0x00 - insert into lower 256 bits
6358 // 0x01 - insert into upper 256 bits
6359 emit_int8(imm8 & 0x01);
6360 }
6361
6362
6363 // vextracti forms
6364
6365 void Assembler::vextracti128(XMMRegister dst, XMMRegister src, uint8_t imm8) {
6366 assert(VM_Version::supports_avx2(), "");
6367 assert(imm8 <= 0x01, "imm8: %u", imm8);
6368 InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6369 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6370 // imm8:
6371 // 0x00 - extract from lower 128 bits
6372 // 0x01 - extract from upper 128 bits
6373 emit_int24(0x39, (unsigned char)(0xC0 | encode), imm8 & 0x01);
6374 }
6375
6376 void Assembler::vextracti128(Address dst, XMMRegister src, uint8_t imm8) {
6377 assert(VM_Version::supports_avx2(), "");
6378 assert(src != xnoreg, "sanity");
6379 assert(imm8 <= 0x01, "imm8: %u", imm8);
6380 InstructionMark im(this);
6381 InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6382 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit);
6383 attributes.reset_is_clear_context();
6384 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6385 emit_int8(0x39);
6386 emit_operand(src, dst);
6387 // 0x00 - extract from lower 128 bits
6388 // 0x01 - extract from upper 128 bits
6389 emit_int8(imm8 & 0x01);
6390 }
6391
6392 void Assembler::vextracti32x4(XMMRegister dst, XMMRegister src, uint8_t imm8) {
6393 assert(VM_Version::supports_evex(), "");
6394 assert(imm8 <= 0x03, "imm8: %u", imm8);
6395 InstructionAttr attributes(AVX_512bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6396 attributes.set_is_evex_instruction();
6397 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6398 // imm8:
6399 // 0x00 - extract from bits 127:0
6400 // 0x01 - extract from bits 255:128
6401 // 0x02 - extract from bits 383:256
6402 // 0x03 - extract from bits 511:384
6403 emit_int24(0x39, (unsigned char)(0xC0 | encode), imm8 & 0x03);
6404 }
6405
6406 void Assembler::vextracti32x4(Address dst, XMMRegister src, uint8_t imm8) {
6407 assert(VM_Version::supports_evex(), "");
6408 assert(src != xnoreg, "sanity");
6409 assert(imm8 <= 0x03, "imm8: %u", imm8);
6410 InstructionMark im(this);
6411 InstructionAttr attributes(AVX_512bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6412 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit);
6413 attributes.reset_is_clear_context();
6414 attributes.set_is_evex_instruction();
6415 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6416 emit_int8(0x39);
6417 emit_operand(src, dst);
6418 // 0x00 - extract from bits 127:0
6419 // 0x01 - extract from bits 255:128
6420 // 0x02 - extract from bits 383:256
6421 // 0x03 - extract from bits 511:384
6422 emit_int8(imm8 & 0x03);
6423 }
6424
6425 void Assembler::vextracti64x2(XMMRegister dst, XMMRegister src, uint8_t imm8) {
6426 assert(VM_Version::supports_avx512dq(), "");
6427 assert(imm8 <= 0x03, "imm8: %u", imm8);
6428 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6429 attributes.set_is_evex_instruction();
6430 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6431 // imm8:
6432 // 0x00 - extract from bits 127:0
6433 // 0x01 - extract from bits 255:128
6434 // 0x02 - extract from bits 383:256
6435 // 0x03 - extract from bits 511:384
6436 emit_int24(0x39, (unsigned char)(0xC0 | encode), imm8 & 0x03);
6437 }
6438
6439 void Assembler::vextracti64x4(XMMRegister dst, XMMRegister src, uint8_t imm8) {
6440 assert(VM_Version::supports_evex(), "");
6441 assert(imm8 <= 0x01, "imm8: %u", imm8);
6442 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6443 attributes.set_is_evex_instruction();
6444 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6445 // imm8:
6446 // 0x00 - extract from lower 256 bits
6447 // 0x01 - extract from upper 256 bits
6448 emit_int24(0x3B, (unsigned char)(0xC0 | encode), imm8 & 0x01);
6449 }
6450
6451 void Assembler::vextracti64x4(Address dst, XMMRegister src, uint8_t imm8) {
6452 assert(VM_Version::supports_evex(), "");
6453 assert(src != xnoreg, "sanity");
6454 assert(imm8 <= 0x01, "imm8: %u", imm8);
6455 InstructionMark im(this);
6456 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6457 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_64bit);
6458 attributes.reset_is_clear_context();
6459 attributes.set_is_evex_instruction();
6460 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6461 emit_int8(0x38);
6462 emit_operand(src, dst);
6463 // 0x00 - extract from lower 256 bits
6464 // 0x01 - extract from upper 256 bits
6465 emit_int8(imm8 & 0x01);
6466 }
6467 // vextractf forms
6468
6469 void Assembler::vextractf128(XMMRegister dst, XMMRegister src, uint8_t imm8) {
6470 assert(VM_Version::supports_avx(), "");
6471 assert(imm8 <= 0x01, "imm8: %u", imm8);
6472 InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6473 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6474 // imm8:
6475 // 0x00 - extract from lower 128 bits
6476 // 0x01 - extract from upper 128 bits
6477 emit_int24(0x19, (unsigned char)(0xC0 | encode), imm8 & 0x01);
6478 }
6479
6480 void Assembler::vextractf128(Address dst, XMMRegister src, uint8_t imm8) {
6481 assert(VM_Version::supports_avx(), "");
6482 assert(src != xnoreg, "sanity");
6483 assert(imm8 <= 0x01, "imm8: %u", imm8);
6484 InstructionMark im(this);
6485 InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6486 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit);
6487 attributes.reset_is_clear_context();
6488 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6489 emit_int8(0x19);
6490 emit_operand(src, dst);
6491 // 0x00 - extract from lower 128 bits
6492 // 0x01 - extract from upper 128 bits
6493 emit_int8(imm8 & 0x01);
6494 }
6495
6496 void Assembler::vextractf32x4(XMMRegister dst, XMMRegister src, uint8_t imm8) {
6497 assert(VM_Version::supports_evex(), "");
6498 assert(imm8 <= 0x03, "imm8: %u", imm8);
6499 InstructionAttr attributes(AVX_512bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6500 attributes.set_is_evex_instruction();
6501 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6502 // imm8:
6503 // 0x00 - extract from bits 127:0
6504 // 0x01 - extract from bits 255:128
6505 // 0x02 - extract from bits 383:256
6506 // 0x03 - extract from bits 511:384
6507 emit_int24(0x19, (unsigned char)(0xC0 | encode), imm8 & 0x03);
6508 }
6509
6510 void Assembler::vextractf32x4(Address dst, XMMRegister src, uint8_t imm8) {
6511 assert(VM_Version::supports_evex(), "");
6512 assert(src != xnoreg, "sanity");
6513 assert(imm8 <= 0x03, "imm8: %u", imm8);
6514 InstructionMark im(this);
6515 InstructionAttr attributes(AVX_512bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6516 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit);
6517 attributes.reset_is_clear_context();
6518 attributes.set_is_evex_instruction();
6519 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6520 emit_int8(0x19);
6521 emit_operand(src, dst);
6522 // 0x00 - extract from bits 127:0
6523 // 0x01 - extract from bits 255:128
6524 // 0x02 - extract from bits 383:256
6525 // 0x03 - extract from bits 511:384
6526 emit_int8(imm8 & 0x03);
6527 }
6528
6529 void Assembler::vextractf64x2(XMMRegister dst, XMMRegister src, uint8_t imm8) {
6530 assert(VM_Version::supports_avx512dq(), "");
6531 assert(imm8 <= 0x03, "imm8: %u", imm8);
6532 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6533 attributes.set_is_evex_instruction();
6534 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6535 // imm8:
6536 // 0x00 - extract from bits 127:0
6537 // 0x01 - extract from bits 255:128
6538 // 0x02 - extract from bits 383:256
6539 // 0x03 - extract from bits 511:384
6540 emit_int24(0x19, (unsigned char)(0xC0 | encode), imm8 & 0x03);
6541 }
6542
6543 void Assembler::vextractf64x4(XMMRegister dst, XMMRegister src, uint8_t imm8) {
6544 assert(VM_Version::supports_evex(), "");
6545 assert(imm8 <= 0x01, "imm8: %u", imm8);
6546 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6547 attributes.set_is_evex_instruction();
6548 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6549 // imm8:
6550 // 0x00 - extract from lower 256 bits
6551 // 0x01 - extract from upper 256 bits
6552 emit_int24(0x1B, (unsigned char)(0xC0 | encode), imm8 & 0x01);
6553 }
6554
6555 void Assembler::vextractf64x4(Address dst, XMMRegister src, uint8_t imm8) {
6556 assert(VM_Version::supports_evex(), "");
6557 assert(src != xnoreg, "sanity");
6558 assert(imm8 <= 0x01, "imm8: %u", imm8);
6559 InstructionMark im(this);
6560 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6561 attributes.set_address_attributes(/* tuple_type */ EVEX_T4,/* input_size_in_bits */ EVEX_64bit);
6562 attributes.reset_is_clear_context();
6563 attributes.set_is_evex_instruction();
6564 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6565 emit_int8(0x1B);
6566 emit_operand(src, dst);
6567 // 0x00 - extract from lower 256 bits
6568 // 0x01 - extract from upper 256 bits
6569 emit_int8(imm8 & 0x01);
6570 }
6571
6572 // duplicate 1-byte integer data from src into programmed locations in dest : requires AVX512BW and AVX512VL
6573 void Assembler::vpbroadcastb(XMMRegister dst, XMMRegister src, int vector_len) {
6574 assert(VM_Version::supports_avx2(), "");
6575 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
6576 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6577 emit_int16(0x78, (unsigned char)(0xC0 | encode));
6578 }
6579
6580 void Assembler::vpbroadcastb(XMMRegister dst, Address src, int vector_len) {
6581 assert(VM_Version::supports_avx2(), "");
6582 assert(dst != xnoreg, "sanity");
6583 InstructionMark im(this);
6584 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
6585 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_8bit);
6586 // swap src<->dst for encoding
6587 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6588 emit_int8(0x78);
6589 emit_operand(dst, src);
6590 }
6591
6592 // duplicate 2-byte integer data from src into programmed locations in dest : requires AVX512BW and AVX512VL
6593 void Assembler::vpbroadcastw(XMMRegister dst, XMMRegister src, int vector_len) {
6594 assert(VM_Version::supports_avx2(), "");
6595 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
6596 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6597 emit_int16(0x79, (unsigned char)(0xC0 | encode));
6598 }
6599
6600 void Assembler::vpbroadcastw(XMMRegister dst, Address src, int vector_len) {
6601 assert(VM_Version::supports_avx2(), "");
6602 assert(dst != xnoreg, "sanity");
6603 InstructionMark im(this);
6604 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
6605 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_16bit);
6606 // swap src<->dst for encoding
6607 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6608 emit_int8(0x79);
6609 emit_operand(dst, src);
6610 }
6611
6612 // xmm/mem sourced byte/word/dword/qword replicate
6613
6614 // duplicate 4-byte integer data from src into programmed locations in dest : requires AVX512VL
6615 void Assembler::vpbroadcastd(XMMRegister dst, XMMRegister src, int vector_len) {
6616 assert(UseAVX >= 2, "");
6617 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6618 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6619 emit_int16(0x58, (unsigned char)(0xC0 | encode));
6620 }
6621
6622 void Assembler::vpbroadcastd(XMMRegister dst, Address src, int vector_len) {
6623 assert(VM_Version::supports_avx2(), "");
6624 assert(dst != xnoreg, "sanity");
6625 InstructionMark im(this);
6626 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6627 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
6628 // swap src<->dst for encoding
6629 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6630 emit_int8(0x58);
6631 emit_operand(dst, src);
6632 }
6633
6634 // duplicate 8-byte integer data from src into programmed locations in dest : requires AVX512VL
6635 void Assembler::vpbroadcastq(XMMRegister dst, XMMRegister src, int vector_len) {
6636 assert(VM_Version::supports_avx2(), "");
6637 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6638 attributes.set_rex_vex_w_reverted();
6639 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6640 emit_int16(0x59, (unsigned char)(0xC0 | encode));
6641 }
6642
6643 void Assembler::vpbroadcastq(XMMRegister dst, Address src, int vector_len) {
6644 assert(VM_Version::supports_avx2(), "");
6645 assert(dst != xnoreg, "sanity");
6646 InstructionMark im(this);
6647 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6648 attributes.set_rex_vex_w_reverted();
6649 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
6650 // swap src<->dst for encoding
6651 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6652 emit_int8(0x59);
6653 emit_operand(dst, src);
6654 }
6655 void Assembler::evbroadcasti64x2(XMMRegister dst, XMMRegister src, int vector_len) {
6656 assert(vector_len != Assembler::AVX_128bit, "");
6657 assert(VM_Version::supports_avx512dq(), "");
6658 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6659 attributes.set_rex_vex_w_reverted();
6660 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6661 emit_int16(0x5A, (unsigned char)(0xC0 | encode));
6662 }
6663
6664 void Assembler::evbroadcasti64x2(XMMRegister dst, Address src, int vector_len) {
6665 assert(vector_len != Assembler::AVX_128bit, "");
6666 assert(VM_Version::supports_avx512dq(), "");
6667 assert(dst != xnoreg, "sanity");
6668 InstructionMark im(this);
6669 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6670 attributes.set_rex_vex_w_reverted();
6671 attributes.set_address_attributes(/* tuple_type */ EVEX_T2, /* input_size_in_bits */ EVEX_64bit);
6672 // swap src<->dst for encoding
6673 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6674 emit_int8(0x5A);
6675 emit_operand(dst, src);
6676 }
6677
6678 // scalar single/double precision replicate
6679
6680 // duplicate single precision data from src into programmed locations in dest : requires AVX512VL
6681 void Assembler::vbroadcastss(XMMRegister dst, XMMRegister src, int vector_len) {
6682 assert(VM_Version::supports_avx2(), "");
6683 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6684 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6685 emit_int16(0x18, (unsigned char)(0xC0 | encode));
6686 }
6687
6688 void Assembler::vbroadcastss(XMMRegister dst, Address src, int vector_len) {
6689 assert(VM_Version::supports_avx(), "");
6690 assert(dst != xnoreg, "sanity");
6691 InstructionMark im(this);
6692 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6693 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
6694 // swap src<->dst for encoding
6695 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6696 emit_int8(0x18);
6697 emit_operand(dst, src);
6698 }
6699
6700 // duplicate double precision data from src into programmed locations in dest : requires AVX512VL
6701 void Assembler::vbroadcastsd(XMMRegister dst, XMMRegister src, int vector_len) {
6702 assert(VM_Version::supports_avx2(), "");
6703 assert(vector_len == AVX_256bit || vector_len == AVX_512bit, "");
6704 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6705 attributes.set_rex_vex_w_reverted();
6706 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6707 emit_int16(0x19, (unsigned char)(0xC0 | encode));
6708 }
6709
6710 void Assembler::vbroadcastsd(XMMRegister dst, Address src, int vector_len) {
6711 assert(VM_Version::supports_avx(), "");
6712 assert(vector_len == AVX_256bit || vector_len == AVX_512bit, "");
6713 assert(dst != xnoreg, "sanity");
6714 InstructionMark im(this);
6715 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6716 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
6717 attributes.set_rex_vex_w_reverted();
6718 // swap src<->dst for encoding
6719 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6720 emit_int8(0x19);
6721 emit_operand(dst, src);
6722 }
6723
6724
6725 // gpr source broadcast forms
6726
6727 // duplicate 1-byte integer data from src into programmed locations in dest : requires AVX512BW and AVX512VL
6728 void Assembler::evpbroadcastb(XMMRegister dst, Register src, int vector_len) {
6729 assert(VM_Version::supports_avx512bw(), "");
6730 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
6731 attributes.set_is_evex_instruction();
6732 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6733 emit_int16(0x7A, (unsigned char)(0xC0 | encode));
6734 }
6735
6736 // duplicate 2-byte integer data from src into programmed locations in dest : requires AVX512BW and AVX512VL
6737 void Assembler::evpbroadcastw(XMMRegister dst, Register src, int vector_len) {
6738 assert(VM_Version::supports_avx512bw(), "");
6739 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
6740 attributes.set_is_evex_instruction();
6741 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6742 emit_int16(0x7B, (unsigned char)(0xC0 | encode));
6743 }
6744
6745 // duplicate 4-byte integer data from src into programmed locations in dest : requires AVX512VL
6746 void Assembler::evpbroadcastd(XMMRegister dst, Register src, int vector_len) {
6747 assert(VM_Version::supports_evex(), "");
6748 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6749 attributes.set_is_evex_instruction();
6750 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6751 emit_int16(0x7C, (unsigned char)(0xC0 | encode));
6752 }
6753
6754 // duplicate 8-byte integer data from src into programmed locations in dest : requires AVX512VL
6755 void Assembler::evpbroadcastq(XMMRegister dst, Register src, int vector_len) {
6756 assert(VM_Version::supports_evex(), "");
6757 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6758 attributes.set_is_evex_instruction();
6759 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6760 emit_int16(0x7C, (unsigned char)(0xC0 | encode));
6761 }
6762 void Assembler::evpgatherdd(XMMRegister dst, KRegister mask, Address src, int vector_len) {
6763 assert(VM_Version::supports_evex(), "");
6764 assert(dst != xnoreg, "sanity");
6765 InstructionMark im(this);
6766 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6767 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
6768 attributes.reset_is_clear_context();
6769 attributes.set_embedded_opmask_register_specifier(mask);
6770 attributes.set_is_evex_instruction();
6771 // swap src<->dst for encoding
6772 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6773 emit_int8((unsigned char)0x90);
6774 emit_operand(dst, src);
6775 }
6776 // Carry-Less Multiplication Quadword
6777 void Assembler::pclmulqdq(XMMRegister dst, XMMRegister src, int mask) {
6778 assert(VM_Version::supports_clmul(), "");
6779 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ true);
6780 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6781 emit_int24(0x44, (unsigned char)(0xC0 | encode), (unsigned char)mask);
6782 }
6783
6784 // Carry-Less Multiplication Quadword
6785 void Assembler::vpclmulqdq(XMMRegister dst, XMMRegister nds, XMMRegister src, int mask) {
6786 assert(VM_Version::supports_avx() && VM_Version::supports_clmul(), "");
6787 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ true);
6788 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6789 emit_int24(0x44, (unsigned char)(0xC0 | encode), (unsigned char)mask);
6790 }
6791
6792 void Assembler::evpclmulqdq(XMMRegister dst, XMMRegister nds, XMMRegister src, int mask, int vector_len) {
6793 assert(VM_Version::supports_avx512_vpclmulqdq(), "Requires vector carryless multiplication support");
6794 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6795 attributes.set_is_evex_instruction();
6796 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6797 emit_int24(0x44, (unsigned char)(0xC0 | encode), (unsigned char)mask);
6798 }
6799
6800 void Assembler::vzeroupper_uncached() {
6801 if (VM_Version::supports_vzeroupper()) {
6802 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
6803 (void)vex_prefix_and_encode(0, 0, 0, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
6804 emit_int8(0x77);
6805 }
6806 }
6807
6808 #ifndef _LP64
6809 // 32bit only pieces of the assembler
6810
6811 void Assembler::vzeroupper() {
6812 vzeroupper_uncached();
6813 }
6814
6815 void Assembler::cmp_literal32(Register src1, int32_t imm32, RelocationHolder const& rspec) {
6816 // NO PREFIX AS NEVER 64BIT
6817 InstructionMark im(this);
6818 emit_int8((unsigned char)0x81, (unsigned char)(0xF8 | src1->encoding()));
6819 emit_data(imm32, rspec, 0);
6820 }
6821
6822 void Assembler::cmp_literal32(Address src1, int32_t imm32, RelocationHolder const& rspec) {
6823 // NO PREFIX AS NEVER 64BIT (not even 32bit versions of 64bit regs
6824 InstructionMark im(this);
6825 emit_int8((unsigned char)0x81);
6826 emit_operand(rdi, src1);
6827 emit_data(imm32, rspec, 0);
6828 }
6829
6830 // The 64-bit (32bit platform) cmpxchg compares the value at adr with the contents of rdx:rax,
6831 // and stores rcx:rbx into adr if so; otherwise, the value at adr is loaded
6832 // into rdx:rax. The ZF is set if the compared values were equal, and cleared otherwise.
6833 void Assembler::cmpxchg8(Address adr) {
6834 InstructionMark im(this);
6835 emit_int16(0x0F, (unsigned char)0xC7);
6836 emit_operand(rcx, adr);
6837 }
6838
6839 void Assembler::decl(Register dst) {
6840 // Don't use it directly. Use MacroAssembler::decrementl() instead.
6841 emit_int8(0x48 | dst->encoding());
6842 }
6843
6844 // 64bit doesn't use the x87
6845
6846 void Assembler::fabs() {
6847 emit_int16((unsigned char)0xD9, (unsigned char)0xE1);
6848 }
6849
6850 void Assembler::fadd(int i) {
6851 emit_farith(0xD8, 0xC0, i);
6852 }
6853
6854 void Assembler::fadd_d(Address src) {
6855 InstructionMark im(this);
6856 emit_int8((unsigned char)0xDC);
6857 emit_operand32(rax, src);
6858 }
6859
6860 void Assembler::fadd_s(Address src) {
6861 InstructionMark im(this);
6862 emit_int8((unsigned char)0xD8);
6863 emit_operand32(rax, src);
6864 }
6865
6866 void Assembler::fadda(int i) {
6867 emit_farith(0xDC, 0xC0, i);
6868 }
6869
6870 void Assembler::faddp(int i) {
6871 emit_farith(0xDE, 0xC0, i);
6872 }
6873
6874 void Assembler::fchs() {
6875 emit_int16((unsigned char)0xD9, (unsigned char)0xE0);
6876 }
6877
6878 void Assembler::fcom(int i) {
6879 emit_farith(0xD8, 0xD0, i);
6880 }
6881
6882 void Assembler::fcomp(int i) {
6883 emit_farith(0xD8, 0xD8, i);
6884 }
6885
6886 void Assembler::fcomp_d(Address src) {
6887 InstructionMark im(this);
6888 emit_int8((unsigned char)0xDC);
6889 emit_operand32(rbx, src);
6890 }
6891
6892 void Assembler::fcomp_s(Address src) {
6893 InstructionMark im(this);
6894 emit_int8((unsigned char)0xD8);
6895 emit_operand32(rbx, src);
6896 }
6897
6898 void Assembler::fcompp() {
6899 emit_int16((unsigned char)0xDE, (unsigned char)0xD9);
6900 }
6901
6902 void Assembler::fcos() {
6903 emit_int16((unsigned char)0xD9, (unsigned char)0xFF);
6904 }
6905
6906 void Assembler::fdecstp() {
6907 emit_int16((unsigned char)0xD9, (unsigned char)0xF6);
6908 }
6909
6910 void Assembler::fdiv(int i) {
6911 emit_farith(0xD8, 0xF0, i);
6912 }
6913
6914 void Assembler::fdiv_d(Address src) {
6915 InstructionMark im(this);
6916 emit_int8((unsigned char)0xDC);
6917 emit_operand32(rsi, src);
6918 }
6919
6920 void Assembler::fdiv_s(Address src) {
6921 InstructionMark im(this);
6922 emit_int8((unsigned char)0xD8);
6923 emit_operand32(rsi, src);
6924 }
6925
6926 void Assembler::fdiva(int i) {
6927 emit_farith(0xDC, 0xF8, i);
6958 emit_farith(0xDE, 0xF0, i); // ST(0) <- ST(1) / ST(0) and pop (Intel manual wrong)
6959 }
6960
6961 void Assembler::ffree(int i) {
6962 emit_farith(0xDD, 0xC0, i);
6963 }
6964
6965 void Assembler::fild_d(Address adr) {
6966 InstructionMark im(this);
6967 emit_int8((unsigned char)0xDF);
6968 emit_operand32(rbp, adr);
6969 }
6970
6971 void Assembler::fild_s(Address adr) {
6972 InstructionMark im(this);
6973 emit_int8((unsigned char)0xDB);
6974 emit_operand32(rax, adr);
6975 }
6976
6977 void Assembler::fincstp() {
6978 emit_int16((unsigned char)0xD9, (unsigned char)0xF7);
6979 }
6980
6981 void Assembler::finit() {
6982 emit_int24((unsigned char)0x9B, (unsigned char)0xDB, (unsigned char)0xE3);
6983 }
6984
6985 void Assembler::fist_s(Address adr) {
6986 InstructionMark im(this);
6987 emit_int8((unsigned char)0xDB);
6988 emit_operand32(rdx, adr);
6989 }
6990
6991 void Assembler::fistp_d(Address adr) {
6992 InstructionMark im(this);
6993 emit_int8((unsigned char)0xDF);
6994 emit_operand32(rdi, adr);
6995 }
6996
6997 void Assembler::fistp_s(Address adr) {
6998 InstructionMark im(this);
6999 emit_int8((unsigned char)0xDB);
7000 emit_operand32(rbx, adr);
7001 }
7002
7003 void Assembler::fld1() {
7004 emit_int16((unsigned char)0xD9, (unsigned char)0xE8);
7005 }
7006
7007 void Assembler::fld_d(Address adr) {
7008 InstructionMark im(this);
7009 emit_int8((unsigned char)0xDD);
7010 emit_operand32(rax, adr);
7011 }
7012
7013 void Assembler::fld_s(Address adr) {
7014 InstructionMark im(this);
7015 emit_int8((unsigned char)0xD9);
7016 emit_operand32(rax, adr);
7017 }
7018
7019
7020 void Assembler::fld_s(int index) {
7021 emit_farith(0xD9, 0xC0, index);
7022 }
7023
7024 void Assembler::fld_x(Address adr) {
7025 InstructionMark im(this);
7026 emit_int8((unsigned char)0xDB);
7027 emit_operand32(rbp, adr);
7028 }
7029
7030 void Assembler::fldcw(Address src) {
7031 InstructionMark im(this);
7032 emit_int8((unsigned char)0xD9);
7033 emit_operand32(rbp, src);
7034 }
7035
7036 void Assembler::fldenv(Address src) {
7037 InstructionMark im(this);
7038 emit_int8((unsigned char)0xD9);
7039 emit_operand32(rsp, src);
7040 }
7041
7042 void Assembler::fldlg2() {
7043 emit_int16((unsigned char)0xD9, (unsigned char)0xEC);
7044 }
7045
7046 void Assembler::fldln2() {
7047 emit_int16((unsigned char)0xD9, (unsigned char)0xED);
7048 }
7049
7050 void Assembler::fldz() {
7051 emit_int16((unsigned char)0xD9, (unsigned char)0xEE);
7052 }
7053
7054 void Assembler::flog() {
7055 fldln2();
7056 fxch();
7057 fyl2x();
7058 }
7059
7060 void Assembler::flog10() {
7061 fldlg2();
7062 fxch();
7063 fyl2x();
7064 }
7065
7066 void Assembler::fmul(int i) {
7067 emit_farith(0xD8, 0xC8, i);
7068 }
7069
7070 void Assembler::fmul_d(Address src) {
7071 InstructionMark im(this);
7078 emit_int8((unsigned char)0xD8);
7079 emit_operand32(rcx, src);
7080 }
7081
7082 void Assembler::fmula(int i) {
7083 emit_farith(0xDC, 0xC8, i);
7084 }
7085
7086 void Assembler::fmulp(int i) {
7087 emit_farith(0xDE, 0xC8, i);
7088 }
7089
7090 void Assembler::fnsave(Address dst) {
7091 InstructionMark im(this);
7092 emit_int8((unsigned char)0xDD);
7093 emit_operand32(rsi, dst);
7094 }
7095
7096 void Assembler::fnstcw(Address src) {
7097 InstructionMark im(this);
7098 emit_int16((unsigned char)0x9B, (unsigned char)0xD9);
7099 emit_operand32(rdi, src);
7100 }
7101
7102 void Assembler::fnstsw_ax() {
7103 emit_int16((unsigned char)0xDF, (unsigned char)0xE0);
7104 }
7105
7106 void Assembler::fprem() {
7107 emit_int16((unsigned char)0xD9, (unsigned char)0xF8);
7108 }
7109
7110 void Assembler::fprem1() {
7111 emit_int16((unsigned char)0xD9, (unsigned char)0xF5);
7112 }
7113
7114 void Assembler::frstor(Address src) {
7115 InstructionMark im(this);
7116 emit_int8((unsigned char)0xDD);
7117 emit_operand32(rsp, src);
7118 }
7119
7120 void Assembler::fsin() {
7121 emit_int16((unsigned char)0xD9, (unsigned char)0xFE);
7122 }
7123
7124 void Assembler::fsqrt() {
7125 emit_int16((unsigned char)0xD9, (unsigned char)0xFA);
7126 }
7127
7128 void Assembler::fst_d(Address adr) {
7129 InstructionMark im(this);
7130 emit_int8((unsigned char)0xDD);
7131 emit_operand32(rdx, adr);
7132 }
7133
7134 void Assembler::fst_s(Address adr) {
7135 InstructionMark im(this);
7136 emit_int8((unsigned char)0xD9);
7137 emit_operand32(rdx, adr);
7138 }
7139
7140 void Assembler::fstp_d(Address adr) {
7141 InstructionMark im(this);
7142 emit_int8((unsigned char)0xDD);
7143 emit_operand32(rbx, adr);
7144 }
7145
7191 InstructionMark im(this);
7192 emit_int8((unsigned char)0xDC);
7193 emit_operand32(rbp, src);
7194 }
7195
7196 void Assembler::fsubr_s(Address src) {
7197 InstructionMark im(this);
7198 emit_int8((unsigned char)0xD8);
7199 emit_operand32(rbp, src);
7200 }
7201
7202 void Assembler::fsubra(int i) {
7203 emit_farith(0xDC, 0xE0, i);
7204 }
7205
7206 void Assembler::fsubrp(int i) {
7207 emit_farith(0xDE, 0xE0, i); // ST(0) <- ST(1) - ST(0) and pop (Intel manual wrong)
7208 }
7209
7210 void Assembler::ftan() {
7211 emit_int32((unsigned char)0xD9, (unsigned char)0xF2, (unsigned char)0xDD, (unsigned char)0xD8);
7212 }
7213
7214 void Assembler::ftst() {
7215 emit_int16((unsigned char)0xD9, (unsigned char)0xE4);
7216 }
7217
7218 void Assembler::fucomi(int i) {
7219 // make sure the instruction is supported (introduced for P6, together with cmov)
7220 guarantee(VM_Version::supports_cmov(), "illegal instruction");
7221 emit_farith(0xDB, 0xE8, i);
7222 }
7223
7224 void Assembler::fucomip(int i) {
7225 // make sure the instruction is supported (introduced for P6, together with cmov)
7226 guarantee(VM_Version::supports_cmov(), "illegal instruction");
7227 emit_farith(0xDF, 0xE8, i);
7228 }
7229
7230 void Assembler::fwait() {
7231 emit_int8((unsigned char)0x9B);
7232 }
7233
7234 void Assembler::fxch(int i) {
7235 emit_farith(0xD9, 0xC8, i);
7236 }
7237
7238 void Assembler::fyl2x() {
7239 emit_int16((unsigned char)0xD9, (unsigned char)0xF1);
7240 }
7241
7242 void Assembler::frndint() {
7243 emit_int16((unsigned char)0xD9, (unsigned char)0xFC);
7244 }
7245
7246 void Assembler::f2xm1() {
7247 emit_int16((unsigned char)0xD9, (unsigned char)0xF0);
7248 }
7249
7250 void Assembler::fldl2e() {
7251 emit_int16((unsigned char)0xD9, (unsigned char)0xEA);
7252 }
7253 #endif // !_LP64
7254
7255 // SSE SIMD prefix byte values corresponding to VexSimdPrefix encoding.
7256 static int simd_pre[4] = { 0, 0x66, 0xF3, 0xF2 };
7257 // SSE opcode second byte values (first is 0x0F) corresponding to VexOpcode encoding.
7258 static int simd_opc[4] = { 0, 0, 0x38, 0x3A };
7259
7260 // Generate SSE legacy REX prefix and SIMD opcode based on VEX encoding.
7261 void Assembler::rex_prefix(Address adr, XMMRegister xreg, VexSimdPrefix pre, VexOpcode opc, bool rex_w) {
7262 if (pre > 0) {
7263 emit_int8(simd_pre[pre]);
7264 }
7265 if (rex_w) {
7266 prefixq(adr, xreg);
7267 } else {
7268 prefix(adr, xreg);
7269 }
7270 if (opc > 0) {
7271 emit_int8(0x0F);
7279 int Assembler::rex_prefix_and_encode(int dst_enc, int src_enc, VexSimdPrefix pre, VexOpcode opc, bool rex_w) {
7280 if (pre > 0) {
7281 emit_int8(simd_pre[pre]);
7282 }
7283 int encode = (rex_w) ? prefixq_and_encode(dst_enc, src_enc) : prefix_and_encode(dst_enc, src_enc);
7284 if (opc > 0) {
7285 emit_int8(0x0F);
7286 int opc2 = simd_opc[opc];
7287 if (opc2 > 0) {
7288 emit_int8(opc2);
7289 }
7290 }
7291 return encode;
7292 }
7293
7294
7295 void Assembler::vex_prefix(bool vex_r, bool vex_b, bool vex_x, int nds_enc, VexSimdPrefix pre, VexOpcode opc) {
7296 int vector_len = _attributes->get_vector_len();
7297 bool vex_w = _attributes->is_rex_vex_w();
7298 if (vex_b || vex_x || vex_w || (opc == VEX_OPCODE_0F_38) || (opc == VEX_OPCODE_0F_3A)) {
7299 int byte1 = (vex_r ? VEX_R : 0) | (vex_x ? VEX_X : 0) | (vex_b ? VEX_B : 0);
7300 byte1 = (~byte1) & 0xE0;
7301 byte1 |= opc;
7302
7303 int byte2 = ((~nds_enc) & 0xf) << 3;
7304 byte2 |= (vex_w ? VEX_W : 0) | ((vector_len > 0) ? 4 : 0) | pre;
7305
7306 emit_int24((unsigned char)VEX_3bytes, byte1, byte2);
7307 } else {
7308 int byte1 = vex_r ? VEX_R : 0;
7309 byte1 = (~byte1) & 0x80;
7310 byte1 |= ((~nds_enc) & 0xf) << 3;
7311 byte1 |= ((vector_len > 0 ) ? 4 : 0) | pre;
7312 emit_int16((unsigned char)VEX_2bytes, byte1);
7313 }
7314 }
7315
7316 // This is a 4 byte encoding
7317 void Assembler::evex_prefix(bool vex_r, bool vex_b, bool vex_x, bool evex_r, bool evex_v, int nds_enc, VexSimdPrefix pre, VexOpcode opc){
7318 // EVEX 0x62 prefix
7319 // byte1 = EVEX_4bytes;
7320
7321 bool vex_w = _attributes->is_rex_vex_w();
7322 int evex_encoding = (vex_w ? VEX_W : 0);
7323 // EVEX.b is not currently used for broadcast of single element or data rounding modes
7324 _attributes->set_evex_encoding(evex_encoding);
7325
7326 // P0: byte 2, initialized to RXBR`00mm
7327 // instead of not'd
7328 int byte2 = (vex_r ? VEX_R : 0) | (vex_x ? VEX_X : 0) | (vex_b ? VEX_B : 0) | (evex_r ? EVEX_Rb : 0);
7329 byte2 = (~byte2) & 0xF0;
7330 // confine opc opcode extensions in mm bits to lower two bits
7331 // of form {0F, 0F_38, 0F_3A}
7332 byte2 |= opc;
7333
7334 // P1: byte 3 as Wvvvv1pp
7335 int byte3 = ((~nds_enc) & 0xf) << 3;
7336 // p[10] is always 1
7337 byte3 |= EVEX_F;
7338 byte3 |= (vex_w & 1) << 7;
7339 // confine pre opcode extensions in pp bits to lower two bits
7340 // of form {66, F3, F2}
7341 byte3 |= pre;
7342
7343 // P2: byte 4 as zL'Lbv'aaa
7344 // kregs are implemented in the low 3 bits as aaa
7345 int byte4 = (_attributes->is_no_reg_mask()) ?
7346 0 :
7347 _attributes->get_embedded_opmask_register_specifier();
7348 // EVEX.v` for extending EVEX.vvvv or VIDX
7349 byte4 |= (evex_v ? 0: EVEX_V);
7350 // third EXEC.b for broadcast actions
7351 byte4 |= (_attributes->is_extended_context() ? EVEX_Rb : 0);
7352 // fourth EVEX.L'L for vector length : 0 is 128, 1 is 256, 2 is 512, currently we do not support 1024
7353 byte4 |= ((_attributes->get_vector_len())& 0x3) << 5;
7354 // last is EVEX.z for zero/merge actions
7355 if (_attributes->is_no_reg_mask() == false) {
7356 byte4 |= (_attributes->is_clear_context() ? EVEX_Z : 0);
7357 }
7358
7359 emit_int32(EVEX_4bytes, byte2, byte3, byte4);
7360 }
7361
7362 void Assembler::vex_prefix(Address adr, int nds_enc, int xreg_enc, VexSimdPrefix pre, VexOpcode opc, InstructionAttr *attributes) {
7363 bool vex_r = (xreg_enc & 8) == 8;
7364 bool vex_b = adr.base_needs_rex();
7365 bool vex_x;
7366 if (adr.isxmmindex()) {
7367 vex_x = adr.xmmindex_needs_rex();
7368 } else {
7369 vex_x = adr.index_needs_rex();
7370 }
7371 set_attributes(attributes);
7372 attributes->set_current_assembler(this);
7373
7374 // For EVEX instruction (which is not marked as pure EVEX instruction) check and see if this instruction
7375 // is allowed in legacy mode and has resources which will fit in it.
7376 // Pure EVEX instructions will have is_evex_instruction set in their definition.
7377 if (!attributes->is_legacy_mode()) {
7378 if (UseAVX > 2 && !attributes->is_evex_instruction() && !is_managed()) {
7379 if ((attributes->get_vector_len() != AVX_512bit) && (nds_enc < 16) && (xreg_enc < 16)) {
7380 attributes->set_is_legacy_mode();
7381 }
7382 }
7383 }
7384
7385 if (UseAVX > 2) {
7386 assert(((!attributes->uses_vl()) ||
7387 (attributes->get_vector_len() == AVX_512bit) ||
7388 (!_legacy_mode_vl) ||
7389 (attributes->is_legacy_mode())),"XMM register should be 0-15");
7390 assert(((nds_enc < 16 && xreg_enc < 16) || (!attributes->is_legacy_mode())),"XMM register should be 0-15");
7391 }
7392
7393 clear_managed();
7394 if (UseAVX > 2 && !attributes->is_legacy_mode())
7395 {
7396 bool evex_r = (xreg_enc >= 16);
7397 bool evex_v;
7398 // EVEX.V' is set to true when VSIB is used as we may need to use higher order XMM registers (16-31)
7399 if (adr.isxmmindex()) {
7400 evex_v = ((adr._xmmindex->encoding() > 15) ? true : false);
7401 } else {
7402 evex_v = (nds_enc >= 16);
7403 }
7404 attributes->set_is_evex_instruction();
7405 evex_prefix(vex_r, vex_b, vex_x, evex_r, evex_v, nds_enc, pre, opc);
7406 } else {
7407 if (UseAVX > 2 && attributes->is_rex_vex_w_reverted()) {
7408 attributes->set_rex_vex_w(false);
7409 }
7410 vex_prefix(vex_r, vex_b, vex_x, nds_enc, pre, opc);
7411 }
7412 }
7413
7414 int Assembler::vex_prefix_and_encode(int dst_enc, int nds_enc, int src_enc, VexSimdPrefix pre, VexOpcode opc, InstructionAttr *attributes) {
7415 bool vex_r = (dst_enc & 8) == 8;
7416 bool vex_b = (src_enc & 8) == 8;
7417 bool vex_x = false;
7418 set_attributes(attributes);
7419 attributes->set_current_assembler(this);
7420
7421 // For EVEX instruction (which is not marked as pure EVEX instruction) check and see if this instruction
7422 // is allowed in legacy mode and has resources which will fit in it.
7423 // Pure EVEX instructions will have is_evex_instruction set in their definition.
7424 if (!attributes->is_legacy_mode()) {
7425 if (UseAVX > 2 && !attributes->is_evex_instruction() && !is_managed()) {
7426 if ((!attributes->uses_vl() || (attributes->get_vector_len() != AVX_512bit)) &&
7427 (dst_enc < 16) && (nds_enc < 16) && (src_enc < 16)) {
7428 attributes->set_is_legacy_mode();
7429 }
7430 }
7431 }
7432
7433 if (UseAVX > 2) {
7434 // All the scalar fp instructions (with uses_vl as false) can have legacy_mode as false
7435 // Instruction with uses_vl true are vector instructions
7436 // All the vector instructions with AVX_512bit length can have legacy_mode as false
7437 // All the vector instructions with < AVX_512bit length can have legacy_mode as false if AVX512vl() is supported
7438 // Rest all should have legacy_mode set as true
7439 assert(((!attributes->uses_vl()) ||
7440 (attributes->get_vector_len() == AVX_512bit) ||
7441 (!_legacy_mode_vl) ||
7442 (attributes->is_legacy_mode())),"XMM register should be 0-15");
7443 // Instruction with legacy_mode true should have dst, nds and src < 15
7444 assert(((dst_enc < 16 && nds_enc < 16 && src_enc < 16) || (!attributes->is_legacy_mode())),"XMM register should be 0-15");
7445 }
7446
7447 clear_managed();
7448 if (UseAVX > 2 && !attributes->is_legacy_mode())
7449 {
7450 bool evex_r = (dst_enc >= 16);
7451 bool evex_v = (nds_enc >= 16);
7452 // can use vex_x as bank extender on rm encoding
7453 vex_x = (src_enc >= 16);
7454 attributes->set_is_evex_instruction();
7455 evex_prefix(vex_r, vex_b, vex_x, evex_r, evex_v, nds_enc, pre, opc);
7456 } else {
7457 if (UseAVX > 2 && attributes->is_rex_vex_w_reverted()) {
7458 attributes->set_rex_vex_w(false);
7459 }
7460 vex_prefix(vex_r, vex_b, vex_x, nds_enc, pre, opc);
7461 }
7462
7463 // return modrm byte components for operands
7464 return (((dst_enc & 7) << 3) | (src_enc & 7));
7465 }
7466
7467
7477 }
7478 }
7479
7480 int Assembler::simd_prefix_and_encode(XMMRegister dst, XMMRegister nds, XMMRegister src, VexSimdPrefix pre,
7481 VexOpcode opc, InstructionAttr *attributes) {
7482 int dst_enc = dst->encoding();
7483 int src_enc = src->encoding();
7484 if (UseAVX > 0) {
7485 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
7486 return vex_prefix_and_encode(dst_enc, nds_enc, src_enc, pre, opc, attributes);
7487 } else {
7488 assert((nds == dst) || (nds == src) || (nds == xnoreg), "wrong sse encoding");
7489 return rex_prefix_and_encode(dst_enc, src_enc, pre, opc, attributes->is_rex_vex_w());
7490 }
7491 }
7492
7493 void Assembler::vmaxss(XMMRegister dst, XMMRegister nds, XMMRegister src) {
7494 assert(VM_Version::supports_avx(), "");
7495 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
7496 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
7497 emit_int16(0x5F, (unsigned char)(0xC0 | encode));
7498 }
7499
7500 void Assembler::vmaxsd(XMMRegister dst, XMMRegister nds, XMMRegister src) {
7501 assert(VM_Version::supports_avx(), "");
7502 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
7503 attributes.set_rex_vex_w_reverted();
7504 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
7505 emit_int16(0x5F, (unsigned char)(0xC0 | encode));
7506 }
7507
7508 void Assembler::vminss(XMMRegister dst, XMMRegister nds, XMMRegister src) {
7509 assert(VM_Version::supports_avx(), "");
7510 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
7511 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
7512 emit_int16(0x5D, (unsigned char)(0xC0 | encode));
7513 }
7514
7515 void Assembler::vminsd(XMMRegister dst, XMMRegister nds, XMMRegister src) {
7516 assert(VM_Version::supports_avx(), "");
7517 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
7518 attributes.set_rex_vex_w_reverted();
7519 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
7520 emit_int16(0x5D, (unsigned char)(0xC0 | encode));
7521 }
7522
7523 void Assembler::cmppd(XMMRegister dst, XMMRegister nds, XMMRegister src, int cop, int vector_len) {
7524 assert(VM_Version::supports_avx(), "");
7525 assert(vector_len <= AVX_256bit, "");
7526 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ true);
7527 int encode = simd_prefix_and_encode(dst, nds, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7528 emit_int24((unsigned char)0xC2, (unsigned char)(0xC0 | encode), (unsigned char)(0xF & cop));
7529 }
7530
7531 void Assembler::blendvpd(XMMRegister dst, XMMRegister nds, XMMRegister src1, XMMRegister src2, int vector_len) {
7532 assert(VM_Version::supports_avx(), "");
7533 assert(vector_len <= AVX_256bit, "");
7534 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ true);
7535 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src1->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
7536 int src2_enc = src2->encoding();
7537 emit_int24((unsigned char)0x4B, (unsigned char)(0xC0 | encode), (unsigned char)(0xF0 & src2_enc << 4));
7538 }
7539
7540 void Assembler::cmpps(XMMRegister dst, XMMRegister nds, XMMRegister src, int cop, int vector_len) {
7541 assert(VM_Version::supports_avx(), "");
7542 assert(vector_len <= AVX_256bit, "");
7543 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ true);
7544 int encode = simd_prefix_and_encode(dst, nds, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
7545 emit_int24((unsigned char)0xC2, (unsigned char)(0xC0 | encode), (unsigned char)(0xF & cop));
7546 }
7547
7548 void Assembler::blendvps(XMMRegister dst, XMMRegister nds, XMMRegister src1, XMMRegister src2, int vector_len) {
7549 assert(VM_Version::supports_avx(), "");
7550 assert(vector_len <= AVX_256bit, "");
7551 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ true);
7552 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src1->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
7553 int src2_enc = src2->encoding();
7554 emit_int24((unsigned char)0x4A, (unsigned char)(0xC0 | encode), (unsigned char)(0xF0 & src2_enc << 4));
7555 }
7556
7557 void Assembler::vpblendd(XMMRegister dst, XMMRegister nds, XMMRegister src, int imm8, int vector_len) {
7558 assert(VM_Version::supports_avx2(), "");
7559 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ true);
7560 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
7561 emit_int24((unsigned char)0x02, (unsigned char)(0xC0 | encode), (unsigned char)imm8);
7562 }
7563
7564 void Assembler::shlxl(Register dst, Register src1, Register src2) {
7565 assert(VM_Version::supports_bmi2(), "");
7566 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ true);
7567 int encode = vex_prefix_and_encode(dst->encoding(), src2->encoding(), src1->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
7568 emit_int16((unsigned char)0xF7, (unsigned char)(0xC0 | encode));
7569 }
7570
7571 void Assembler::shlxq(Register dst, Register src1, Register src2) {
7572 assert(VM_Version::supports_bmi2(), "");
7573 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ true);
7574 int encode = vex_prefix_and_encode(dst->encoding(), src2->encoding(), src1->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
7575 emit_int16((unsigned char)0xF7, (unsigned char)(0xC0 | encode));
7576 }
7577
7578 #ifndef _LP64
7579
7580 void Assembler::incl(Register dst) {
7581 // Don't use it directly. Use MacroAssembler::incrementl() instead.
7582 emit_int8(0x40 | dst->encoding());
7583 }
7584
7585 void Assembler::lea(Register dst, Address src) {
7586 leal(dst, src);
7587 }
7588
7589 void Assembler::mov_literal32(Address dst, int32_t imm32, RelocationHolder const& rspec) {
7590 InstructionMark im(this);
7591 emit_int8((unsigned char)0xC7);
7592 emit_operand(rax, dst);
7593 emit_data((int)imm32, rspec, 0);
7594 }
7595
7598 int encode = prefix_and_encode(dst->encoding());
7599 emit_int8((unsigned char)(0xB8 | encode));
7600 emit_data((int)imm32, rspec, 0);
7601 }
7602
7603 void Assembler::popa() { // 32bit
7604 emit_int8(0x61);
7605 }
7606
7607 void Assembler::push_literal32(int32_t imm32, RelocationHolder const& rspec) {
7608 InstructionMark im(this);
7609 emit_int8(0x68);
7610 emit_data(imm32, rspec, 0);
7611 }
7612
7613 void Assembler::pusha() { // 32bit
7614 emit_int8(0x60);
7615 }
7616
7617 void Assembler::set_byte_if_not_zero(Register dst) {
7618 emit_int8(0x0F, (unsigned char)0x95, (unsigned char)(0xE0 | dst->encoding()));
7619 }
7620
7621 #else // LP64
7622
7623 void Assembler::set_byte_if_not_zero(Register dst) {
7624 int enc = prefix_and_encode(dst->encoding(), true);
7625 emit_int24(0x0F, (unsigned char)0x95, (unsigned char)(0xE0 | enc));
7626 }
7627
7628 // 64bit only pieces of the assembler
7629 // This should only be used by 64bit instructions that can use rip-relative
7630 // it cannot be used by instructions that want an immediate value.
7631
7632 bool Assembler::reachable(AddressLiteral adr) {
7633 int64_t disp;
7634 relocInfo::relocType relocType = adr.reloc();
7635
7636 // None will force a 64bit literal to the code stream. Likely a placeholder
7637 // for something that will be patched later and we need to certain it will
7638 // always be reachable.
7639 if (relocType == relocInfo::none) {
7640 return false;
7641 }
7642 if (relocType == relocInfo::internal_word_type) {
7643 // This should be rip relative and easily reachable.
7644 return true;
7645 }
7755 if (dst_enc < 8) {
7756 if (src_enc >= 8) {
7757 prefix(REX_B);
7758 src_enc -= 8;
7759 } else if ((src_is_byte && src_enc >= 4) || (dst_is_byte && dst_enc >= 4)) {
7760 prefix(REX);
7761 }
7762 } else {
7763 if (src_enc < 8) {
7764 prefix(REX_R);
7765 } else {
7766 prefix(REX_RB);
7767 src_enc -= 8;
7768 }
7769 dst_enc -= 8;
7770 }
7771 return dst_enc << 3 | src_enc;
7772 }
7773
7774 int Assembler::prefixq_and_encode(int dst_enc, int src_enc) {
7775 static const int8_t prefixes[] = {
7776 REX_W,
7777 REX_WB,
7778 REX_WR,
7779 REX_WRB
7780 };
7781 int idx = 0;
7782 if (dst_enc >= 8) {
7783 idx |= 2;
7784 dst_enc -= 8;
7785 }
7786 if (src_enc >= 8) {
7787 src_enc -= 8;
7788 idx |= 1;
7789 }
7790 emit_int8(prefixes[idx]);
7791 return dst_enc << 3 | src_enc;
7792 }
7793
7794 void Assembler::prefix(Register reg) {
7795 if (reg->encoding() >= 8) {
7796 prefix(REX_B);
7797 }
7798 }
7799
7800 void Assembler::prefix(Register dst, Register src, Prefix p) {
7801 if (src->encoding() >= 8) {
7802 p = (Prefix)(p | REX_B);
7803 }
7804 if (dst->encoding() >= 8) {
7805 p = (Prefix)( p | REX_R);
7806 }
7807 if (p != Prefix_EMPTY) {
7808 // do not generate an empty prefix
7809 prefix(p);
7810 }
7828 if (p != Prefix_EMPTY) {
7829 // do not generate an empty prefix
7830 prefix(p);
7831 }
7832 }
7833
7834 void Assembler::prefix(Address adr) {
7835 if (adr.base_needs_rex()) {
7836 if (adr.index_needs_rex()) {
7837 prefix(REX_XB);
7838 } else {
7839 prefix(REX_B);
7840 }
7841 } else {
7842 if (adr.index_needs_rex()) {
7843 prefix(REX_X);
7844 }
7845 }
7846 }
7847
7848 int8_t Assembler::get_prefixq(Address adr) {
7849 static const Assembler::Prefix prefixes[] = {
7850 REX_W,
7851 REX_WX,
7852 REX_WB,
7853 REX_WXB
7854 };
7855 int idx = (int)adr.index_needs_rex() | ((int)adr.base_needs_rex() << 1);
7856 Assembler::Prefix prfx = prefixes[idx];
7857 #ifdef ASSERT
7858 if (adr.base_needs_rex()) {
7859 if (adr.index_needs_rex()) {
7860 assert(prfx == REX_WXB, "must be");
7861 } else {
7862 assert(prfx == REX_WB, "must be");
7863 }
7864 } else {
7865 if (adr.index_needs_rex()) {
7866 assert(prfx == REX_WX, "must be");
7867 } else {
7868 assert(prfx == REX_W, "must be");
7869 }
7870 }
7871 #endif
7872 return (int8_t)prfx;
7873 }
7874
7875 void Assembler::prefixq(Address adr) {
7876 emit_int8(get_prefixq(adr));
7877 }
7878
7879 void Assembler::prefix(Address adr, Register reg, bool byteinst) {
7880 if (reg->encoding() < 8) {
7881 if (adr.base_needs_rex()) {
7882 if (adr.index_needs_rex()) {
7883 prefix(REX_XB);
7884 } else {
7885 prefix(REX_B);
7886 }
7887 } else {
7888 if (adr.index_needs_rex()) {
7889 prefix(REX_X);
7890 } else if (byteinst && reg->encoding() >= 4 ) {
7891 prefix(REX);
7892 }
7893 }
7894 } else {
7895 if (adr.base_needs_rex()) {
7896 if (adr.index_needs_rex()) {
7897 prefix(REX_RXB);
7898 } else {
7899 prefix(REX_RB);
7900 }
7901 } else {
7902 if (adr.index_needs_rex()) {
7903 prefix(REX_RX);
7904 } else {
7905 prefix(REX_R);
7906 }
7907 }
7908 }
7909 }
7910
7911 int8_t Assembler::get_prefixq(Address adr, Register src) {
7912 static const int8_t prefixes[] = {
7913 REX_WR,
7914 REX_WRX,
7915 REX_WRB,
7916 REX_WRXB,
7917 REX_W,
7918 REX_WX,
7919 REX_WB,
7920 REX_WXB,
7921 };
7922 int idx = (int)adr.index_needs_rex() | ((int)adr.base_needs_rex() << 1) | ((int)(src->encoding() < 8) << 2);
7923 return prefixes[idx];
7924 }
7925
7926 void Assembler::prefixq(Address adr, Register src) {
7927 emit_int8(get_prefixq(adr, src));
7928 }
7929
7930 void Assembler::prefix(Address adr, XMMRegister reg) {
7931 if (reg->encoding() < 8) {
7932 if (adr.base_needs_rex()) {
7933 if (adr.index_needs_rex()) {
7934 prefix(REX_XB);
7935 } else {
7936 prefix(REX_B);
7937 }
7938 } else {
7939 if (adr.index_needs_rex()) {
7940 prefix(REX_X);
7941 }
7942 }
7943 } else {
7944 if (adr.base_needs_rex()) {
7945 if (adr.index_needs_rex()) {
7946 prefix(REX_RXB);
7947 } else {
7979 } else {
7980 prefix(REX_WRB);
7981 }
7982 } else {
7983 if (adr.index_needs_rex()) {
7984 prefix(REX_WRX);
7985 } else {
7986 prefix(REX_WR);
7987 }
7988 }
7989 }
7990 }
7991
7992 void Assembler::adcq(Register dst, int32_t imm32) {
7993 (void) prefixq_and_encode(dst->encoding());
7994 emit_arith(0x81, 0xD0, dst, imm32);
7995 }
7996
7997 void Assembler::adcq(Register dst, Address src) {
7998 InstructionMark im(this);
7999 emit_int16(get_prefixq(src, dst),
8000 0x13);
8001 emit_operand(dst, src);
8002 }
8003
8004 void Assembler::adcq(Register dst, Register src) {
8005 (void) prefixq_and_encode(dst->encoding(), src->encoding());
8006 emit_arith(0x13, 0xC0, dst, src);
8007 }
8008
8009 void Assembler::addq(Address dst, int32_t imm32) {
8010 InstructionMark im(this);
8011 prefixq(dst);
8012 emit_arith_operand(0x81, rax, dst,imm32);
8013 }
8014
8015 void Assembler::addq(Address dst, Register src) {
8016 InstructionMark im(this);
8017 emit_int16(get_prefixq(dst, src),
8018 0x01);
8019 emit_operand(src, dst);
8020 }
8021
8022 void Assembler::addq(Register dst, int32_t imm32) {
8023 (void) prefixq_and_encode(dst->encoding());
8024 emit_arith(0x81, 0xC0, dst, imm32);
8025 }
8026
8027 void Assembler::addq(Register dst, Address src) {
8028 InstructionMark im(this);
8029 emit_int16(get_prefixq(src, dst), 0x03);
8030 emit_operand(dst, src);
8031 }
8032
8033 void Assembler::addq(Register dst, Register src) {
8034 (void) prefixq_and_encode(dst->encoding(), src->encoding());
8035 emit_arith(0x03, 0xC0, dst, src);
8036 }
8037
8038 void Assembler::adcxq(Register dst, Register src) {
8039 //assert(VM_Version::supports_adx(), "adx instructions not supported");
8040 emit_int8((unsigned char)0x66);
8041 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
8042 emit_int32(0x0F,
8043 0x38,
8044 (unsigned char)0xF6,
8045 (unsigned char)(0xC0 | encode));
8046 }
8047
8048 void Assembler::adoxq(Register dst, Register src) {
8049 //assert(VM_Version::supports_adx(), "adx instructions not supported");
8050 emit_int8((unsigned char)0xF3);
8051 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
8052 emit_int32(0x0F,
8053 0x38,
8054 (unsigned char)0xF6,
8055 (unsigned char)(0xC0 | encode));
8056 }
8057
8058 void Assembler::andq(Address dst, int32_t imm32) {
8059 InstructionMark im(this);
8060 emit_int16(get_prefixq(dst),
8061 (unsigned char)0x81);
8062 emit_operand(rsp, dst, 4);
8063 emit_int32(imm32);
8064 }
8065
8066 void Assembler::andq(Register dst, int32_t imm32) {
8067 (void) prefixq_and_encode(dst->encoding());
8068 emit_arith(0x81, 0xE0, dst, imm32);
8069 }
8070
8071 void Assembler::andq(Register dst, Address src) {
8072 InstructionMark im(this);
8073 emit_int16(get_prefixq(src, dst), 0x23);
8074 emit_operand(dst, src);
8075 }
8076
8077 void Assembler::andq(Register dst, Register src) {
8078 (void) prefixq_and_encode(dst->encoding(), src->encoding());
8079 emit_arith(0x23, 0xC0, dst, src);
8080 }
8081
8082 void Assembler::andnq(Register dst, Register src1, Register src2) {
8083 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
8084 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
8085 int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
8086 emit_int16((unsigned char)0xF2, (unsigned char)(0xC0 | encode));
8087 }
8088
8089 void Assembler::andnq(Register dst, Register src1, Address src2) {
8090 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
8091 InstructionMark im(this);
8092 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
8093 vex_prefix(src2, src1->encoding(), dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
8094 emit_int8((unsigned char)0xF2);
8095 emit_operand(dst, src2);
8096 }
8097
8098 void Assembler::bsfq(Register dst, Register src) {
8099 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
8100 emit_int24(0x0F, (unsigned char)0xBC, (unsigned char)(0xC0 | encode));
8101 }
8102
8103 void Assembler::bsrq(Register dst, Register src) {
8104 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
8105 emit_int24(0x0F, (unsigned char)0xBD, (unsigned char)(0xC0 | encode));
8106 }
8107
8108 void Assembler::bswapq(Register reg) {
8109 int encode = prefixq_and_encode(reg->encoding());
8110 emit_int16(0x0F, (unsigned char)(0xC8 | encode));
8111 }
8112
8113 void Assembler::blsiq(Register dst, Register src) {
8114 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
8115 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
8116 int encode = vex_prefix_and_encode(rbx->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
8117 emit_int16((unsigned char)0xF3, (unsigned char)(0xC0 | encode));
8118 }
8119
8120 void Assembler::blsiq(Register dst, Address src) {
8121 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
8122 InstructionMark im(this);
8123 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
8124 vex_prefix(src, dst->encoding(), rbx->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
8125 emit_int8((unsigned char)0xF3);
8126 emit_operand(rbx, src);
8127 }
8128
8129 void Assembler::blsmskq(Register dst, Register src) {
8130 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
8131 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
8132 int encode = vex_prefix_and_encode(rdx->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
8133 emit_int16((unsigned char)0xF3, (unsigned char)(0xC0 | encode));
8134 }
8135
8136 void Assembler::blsmskq(Register dst, Address src) {
8137 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
8138 InstructionMark im(this);
8139 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
8140 vex_prefix(src, dst->encoding(), rdx->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
8141 emit_int8((unsigned char)0xF3);
8142 emit_operand(rdx, src);
8143 }
8144
8145 void Assembler::blsrq(Register dst, Register src) {
8146 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
8147 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
8148 int encode = vex_prefix_and_encode(rcx->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
8149 emit_int16((unsigned char)0xF3, (unsigned char)(0xC0 | encode));
8150 }
8151
8152 void Assembler::blsrq(Register dst, Address src) {
8153 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
8154 InstructionMark im(this);
8155 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
8156 vex_prefix(src, dst->encoding(), rcx->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
8157 emit_int8((unsigned char)0xF3);
8158 emit_operand(rcx, src);
8159 }
8160
8161 void Assembler::cdqq() {
8162 emit_int16(REX_W, (unsigned char)0x99);
8163 }
8164
8165 void Assembler::clflush(Address adr) {
8166 assert(VM_Version::supports_clflush(), "should do");
8167 prefix(adr);
8168 emit_int16(0x0F, (unsigned char)0xAE);
8169 emit_operand(rdi, adr);
8170 }
8171
8172 void Assembler::clflushopt(Address adr) {
8173 assert(VM_Version::supports_clflushopt(), "should do!");
8174 // adr should be base reg only with no index or offset
8175 assert(adr.index() == noreg, "index should be noreg");
8176 assert(adr.scale() == Address::no_scale, "scale should be no_scale");
8177 assert(adr.disp() == 0, "displacement should be 0");
8178 // instruction prefix is 0x66
8179 emit_int8(0x66);
8180 prefix(adr);
8181 // opcode family is 0x0F 0xAE
8182 emit_int16(0x0F, (unsigned char)0xAE);
8183 // extended opcode byte is 7 == rdi
8184 emit_operand(rdi, adr);
8185 }
8186
8187 void Assembler::clwb(Address adr) {
8188 assert(VM_Version::supports_clwb(), "should do!");
8189 // adr should be base reg only with no index or offset
8190 assert(adr.index() == noreg, "index should be noreg");
8191 assert(adr.scale() == Address::no_scale, "scale should be no_scale");
8192 assert(adr.disp() == 0, "displacement should be 0");
8193 // instruction prefix is 0x66
8194 emit_int8(0x66);
8195 prefix(adr);
8196 // opcode family is 0x0f 0xAE
8197 emit_int16(0x0F, (unsigned char)0xAE);
8198 // extended opcode byte is 6 == rsi
8199 emit_operand(rsi, adr);
8200 }
8201
8202 void Assembler::cmovq(Condition cc, Register dst, Register src) {
8203 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
8204 emit_int24(0x0F, 0x40 | cc, (unsigned char)(0xC0 | encode));
8205 }
8206
8207 void Assembler::cmovq(Condition cc, Register dst, Address src) {
8208 InstructionMark im(this);
8209 emit_int24(get_prefixq(src, dst), 0x0F, 0x40 | cc);
8210 emit_operand(dst, src);
8211 }
8212
8213 void Assembler::cmpq(Address dst, int32_t imm32) {
8214 InstructionMark im(this);
8215 emit_int16(get_prefixq(dst), (unsigned char)0x81);
8216 emit_operand(rdi, dst, 4);
8217 emit_int32(imm32);
8218 }
8219
8220 void Assembler::cmpq(Register dst, int32_t imm32) {
8221 (void) prefixq_and_encode(dst->encoding());
8222 emit_arith(0x81, 0xF8, dst, imm32);
8223 }
8224
8225 void Assembler::cmpq(Address dst, Register src) {
8226 InstructionMark im(this);
8227 emit_int16(get_prefixq(dst, src), 0x3B);
8228 emit_operand(src, dst);
8229 }
8230
8231 void Assembler::cmpq(Register dst, Register src) {
8232 (void) prefixq_and_encode(dst->encoding(), src->encoding());
8233 emit_arith(0x3B, 0xC0, dst, src);
8234 }
8235
8236 void Assembler::cmpq(Register dst, Address src) {
8237 InstructionMark im(this);
8238 emit_int16(get_prefixq(src, dst), 0x3B);
8239 emit_operand(dst, src);
8240 }
8241
8242 void Assembler::cmpxchgq(Register reg, Address adr) {
8243 InstructionMark im(this);
8244 emit_int24(get_prefixq(adr, reg), 0x0F, (unsigned char)0xB1);
8245 emit_operand(reg, adr);
8246 }
8247
8248 void Assembler::cvtsi2sdq(XMMRegister dst, Register src) {
8249 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
8250 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
8251 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
8252 emit_int16(0x2A, (unsigned char)(0xC0 | encode));
8253 }
8254
8255 void Assembler::cvtsi2sdq(XMMRegister dst, Address src) {
8256 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
8257 InstructionMark im(this);
8258 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
8259 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
8260 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
8261 emit_int8(0x2A);
8262 emit_operand(dst, src);
8263 }
8264
8265 void Assembler::cvtsi2ssq(XMMRegister dst, Address src) {
8266 NOT_LP64(assert(VM_Version::supports_sse(), ""));
8267 InstructionMark im(this);
8268 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
8269 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
8270 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
8271 emit_int8(0x2A);
8272 emit_operand(dst, src);
8273 }
8274
8275 void Assembler::cvttsd2siq(Register dst, Address src) {
8276 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
8277 // F2 REX.W 0F 2C /r
8278 // CVTTSD2SI r64, xmm1/m64
8279 InstructionMark im(this);
8280 emit_int32((unsigned char)0xF2, REX_W, 0x0F, 0x2C);
8281 emit_operand(dst, src);
8282 }
8283
8284 void Assembler::cvttsd2siq(Register dst, XMMRegister src) {
8285 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
8286 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
8287 int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
8288 emit_int16(0x2C, (unsigned char)(0xC0 | encode));
8289 }
8290
8291 void Assembler::cvttss2siq(Register dst, XMMRegister src) {
8292 NOT_LP64(assert(VM_Version::supports_sse(), ""));
8293 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
8294 int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
8295 emit_int16(0x2C, (unsigned char)(0xC0 | encode));
8296 }
8297
8298 void Assembler::decl(Register dst) {
8299 // Don't use it directly. Use MacroAssembler::decrementl() instead.
8300 // Use two-byte form (one-byte form is a REX prefix in 64-bit mode)
8301 int encode = prefix_and_encode(dst->encoding());
8302 emit_int16((unsigned char)0xFF, (unsigned char)(0xC8 | encode));
8303 }
8304
8305 void Assembler::decq(Register dst) {
8306 // Don't use it directly. Use MacroAssembler::decrementq() instead.
8307 // Use two-byte form (one-byte from is a REX prefix in 64-bit mode)
8308 int encode = prefixq_and_encode(dst->encoding());
8309 emit_int16((unsigned char)0xFF, 0xC8 | encode);
8310 }
8311
8312 void Assembler::decq(Address dst) {
8313 // Don't use it directly. Use MacroAssembler::decrementq() instead.
8314 InstructionMark im(this);
8315 emit_int16(get_prefixq(dst), (unsigned char)0xFF);
8316 emit_operand(rcx, dst);
8317 }
8318
8319 void Assembler::fxrstor(Address src) {
8320 emit_int24(get_prefixq(src), 0x0F, (unsigned char)0xAE);
8321 emit_operand(as_Register(1), src);
8322 }
8323
8324 void Assembler::xrstor(Address src) {
8325 emit_int24(get_prefixq(src), 0x0F, (unsigned char)0xAE);
8326 emit_operand(as_Register(5), src);
8327 }
8328
8329 void Assembler::fxsave(Address dst) {
8330 emit_int24(get_prefixq(dst), 0x0F, (unsigned char)0xAE);
8331 emit_operand(as_Register(0), dst);
8332 }
8333
8334 void Assembler::xsave(Address dst) {
8335 emit_int24(get_prefixq(dst), 0x0F, (unsigned char)0xAE);
8336 emit_operand(as_Register(4), dst);
8337 }
8338
8339 void Assembler::idivq(Register src) {
8340 int encode = prefixq_and_encode(src->encoding());
8341 emit_int16((unsigned char)0xF7, (unsigned char)(0xF8 | encode));
8342 }
8343
8344 void Assembler::imulq(Register dst, Register src) {
8345 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
8346 emit_int24(0x0F, (unsigned char)0xAF, (unsigned char)(0xC0 | encode));
8347 }
8348
8349 void Assembler::imulq(Register dst, Register src, int value) {
8350 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
8351 if (is8bit(value)) {
8352 emit_int24(0x6B, (unsigned char)(0xC0 | encode), value & 0xFF);
8353 } else {
8354 emit_int16(0x69, (unsigned char)(0xC0 | encode));
8355 emit_int32(value);
8356 }
8357 }
8358
8359 void Assembler::imulq(Register dst, Address src) {
8360 InstructionMark im(this);
8361 emit_int24(get_prefixq(src, dst), 0x0F, (unsigned char)0xAF);
8362 emit_operand(dst, src);
8363 }
8364
8365 void Assembler::incl(Register dst) {
8366 // Don't use it directly. Use MacroAssembler::incrementl() instead.
8367 // Use two-byte form (one-byte from is a REX prefix in 64-bit mode)
8368 int encode = prefix_and_encode(dst->encoding());
8369 emit_int16((unsigned char)0xFF, (unsigned char)(0xC0 | encode));
8370 }
8371
8372 void Assembler::incq(Register dst) {
8373 // Don't use it directly. Use MacroAssembler::incrementq() instead.
8374 // Use two-byte form (one-byte from is a REX prefix in 64-bit mode)
8375 int encode = prefixq_and_encode(dst->encoding());
8376 emit_int16((unsigned char)0xFF, (unsigned char)(0xC0 | encode));
8377 }
8378
8379 void Assembler::incq(Address dst) {
8380 // Don't use it directly. Use MacroAssembler::incrementq() instead.
8381 InstructionMark im(this);
8382 emit_int16(get_prefixq(dst), (unsigned char)0xFF);
8383 emit_operand(rax, dst);
8384 }
8385
8386 void Assembler::lea(Register dst, Address src) {
8387 leaq(dst, src);
8388 }
8389
8390 void Assembler::leaq(Register dst, Address src) {
8391 InstructionMark im(this);
8392 emit_int16(get_prefixq(src, dst), (unsigned char)0x8D);
8393 emit_operand(dst, src);
8394 }
8395
8396 void Assembler::mov64(Register dst, int64_t imm64) {
8397 InstructionMark im(this);
8398 int encode = prefixq_and_encode(dst->encoding());
8399 emit_int8((unsigned char)(0xB8 | encode));
8400 emit_int64(imm64);
8401 }
8402
8403 void Assembler::mov_literal64(Register dst, intptr_t imm64, RelocationHolder const& rspec) {
8404 InstructionMark im(this);
8405 int encode = prefixq_and_encode(dst->encoding());
8406 emit_int8(0xB8 | encode);
8407 emit_data64(imm64, rspec);
8408 }
8409
8410 void Assembler::mov_narrow_oop(Register dst, int32_t imm32, RelocationHolder const& rspec) {
8411 InstructionMark im(this);
8412 int encode = prefix_and_encode(dst->encoding());
8413 emit_int8((unsigned char)(0xB8 | encode));
8414 emit_data((int)imm32, rspec, narrow_oop_operand);
8415 }
8416
8417 void Assembler::mov_narrow_oop(Address dst, int32_t imm32, RelocationHolder const& rspec) {
8418 InstructionMark im(this);
8419 prefix(dst);
8420 emit_int8((unsigned char)0xC7);
8421 emit_operand(rax, dst, 4);
8422 emit_data((int)imm32, rspec, narrow_oop_operand);
8423 }
8424
8425 void Assembler::cmp_narrow_oop(Register src1, int32_t imm32, RelocationHolder const& rspec) {
8426 InstructionMark im(this);
8427 int encode = prefix_and_encode(src1->encoding());
8428 emit_int16((unsigned char)0x81, (unsigned char)(0xF8 | encode));
8429 emit_data((int)imm32, rspec, narrow_oop_operand);
8430 }
8431
8432 void Assembler::cmp_narrow_oop(Address src1, int32_t imm32, RelocationHolder const& rspec) {
8433 InstructionMark im(this);
8434 prefix(src1);
8435 emit_int8((unsigned char)0x81);
8436 emit_operand(rax, src1, 4);
8437 emit_data((int)imm32, rspec, narrow_oop_operand);
8438 }
8439
8440 void Assembler::lzcntq(Register dst, Register src) {
8441 assert(VM_Version::supports_lzcnt(), "encoding is treated as BSR");
8442 emit_int8((unsigned char)0xF3);
8443 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
8444 emit_int24(0x0F, (unsigned char)0xBD, (unsigned char)(0xC0 | encode));
8445 }
8446
8447 void Assembler::movdq(XMMRegister dst, Register src) {
8448 // table D-1 says MMX/SSE2
8449 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
8450 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
8451 int encode = simd_prefix_and_encode(dst, xnoreg, as_XMMRegister(src->encoding()), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
8452 emit_int16(0x6E, (unsigned char)(0xC0 | encode));
8453 }
8454
8455 void Assembler::movdq(Register dst, XMMRegister src) {
8456 // table D-1 says MMX/SSE2
8457 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
8458 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
8459 // swap src/dst to get correct prefix
8460 int encode = simd_prefix_and_encode(src, xnoreg, as_XMMRegister(dst->encoding()), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
8461 emit_int16(0x7E, (unsigned char)(0xC0 | encode));
8462 }
8463
8464 void Assembler::movq(Register dst, Register src) {
8465 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
8466 emit_int16((unsigned char)0x8B, (unsigned char)(0xC0 | encode));
8467 }
8468
8469 void Assembler::movq(Register dst, Address src) {
8470 InstructionMark im(this);
8471 emit_int16(get_prefixq(src, dst), (unsigned char)0x8B);
8472 emit_operand(dst, src);
8473 }
8474
8475 void Assembler::movq(Address dst, Register src) {
8476 InstructionMark im(this);
8477 emit_int16(get_prefixq(dst, src), (unsigned char)0x89);
8478 emit_operand(src, dst);
8479 }
8480
8481 void Assembler::movsbq(Register dst, Address src) {
8482 InstructionMark im(this);
8483 emit_int24(get_prefixq(src, dst), 0x0F, (unsigned char)0xBE);
8484 emit_operand(dst, src);
8485 }
8486
8487 void Assembler::movsbq(Register dst, Register src) {
8488 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
8489 emit_int24(0x0F, (unsigned char)0xBE, (unsigned char)(0xC0 | encode));
8490 }
8491
8492 void Assembler::movslq(Register dst, int32_t imm32) {
8493 // dbx shows movslq(rcx, 3) as movq $0x0000000049000000,(%rbx)
8494 // and movslq(r8, 3); as movl $0x0000000048000000,(%rbx)
8495 // as a result we shouldn't use until tested at runtime...
8496 ShouldNotReachHere();
8497 InstructionMark im(this);
8498 int encode = prefixq_and_encode(dst->encoding());
8499 emit_int8((unsigned char)(0xC7 | encode));
8500 emit_int32(imm32);
8501 }
8502
8503 void Assembler::movslq(Address dst, int32_t imm32) {
8504 assert(is_simm32(imm32), "lost bits");
8505 InstructionMark im(this);
8506 emit_int16(get_prefixq(dst), (unsigned char)0xC7);
8507 emit_operand(rax, dst, 4);
8508 emit_int32(imm32);
8509 }
8510
8511 void Assembler::movslq(Register dst, Address src) {
8512 InstructionMark im(this);
8513 emit_int16(get_prefixq(src, dst), 0x63);
8514 emit_operand(dst, src);
8515 }
8516
8517 void Assembler::movslq(Register dst, Register src) {
8518 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
8519 emit_int16(0x63, (unsigned char)(0xC0 | encode));
8520 }
8521
8522 void Assembler::movswq(Register dst, Address src) {
8523 InstructionMark im(this);
8524 emit_int24(get_prefixq(src, dst), 0x0F, (unsigned char)0xBF);
8525 emit_operand(dst, src);
8526 }
8527
8528 void Assembler::movswq(Register dst, Register src) {
8529 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
8530 emit_int24((unsigned char)0x0F, (unsigned char)0xBF, (unsigned char)(0xC0 | encode));
8531 }
8532
8533 void Assembler::movzbq(Register dst, Address src) {
8534 InstructionMark im(this);
8535 emit_int24(get_prefixq(src, dst), (unsigned char)0x0F, (unsigned char)0xB6);
8536 emit_operand(dst, src);
8537 }
8538
8539 void Assembler::movzbq(Register dst, Register src) {
8540 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
8541 emit_int24(0x0F, (unsigned char)0xB6, 0xC0 | encode);
8542 }
8543
8544 void Assembler::movzwq(Register dst, Address src) {
8545 InstructionMark im(this);
8546 emit_int24(get_prefixq(src, dst), (unsigned char)0x0F, (unsigned char)0xB7);
8547 emit_operand(dst, src);
8548 }
8549
8550 void Assembler::movzwq(Register dst, Register src) {
8551 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
8552 emit_int24((unsigned char)0x0F, (unsigned char)0xB7, (unsigned char)(0xC0 | encode));
8553 }
8554
8555 void Assembler::mulq(Address src) {
8556 InstructionMark im(this);
8557 emit_int16(get_prefixq(src), (unsigned char)0xF7);
8558 emit_operand(rsp, src);
8559 }
8560
8561 void Assembler::mulq(Register src) {
8562 int encode = prefixq_and_encode(src->encoding());
8563 emit_int16((unsigned char)0xF7, (unsigned char)(0xE0 | encode));
8564 }
8565
8566 void Assembler::mulxq(Register dst1, Register dst2, Register src) {
8567 assert(VM_Version::supports_bmi2(), "bit manipulation instructions not supported");
8568 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
8569 int encode = vex_prefix_and_encode(dst1->encoding(), dst2->encoding(), src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F_38, &attributes);
8570 emit_int16((unsigned char)0xF6, (unsigned char)(0xC0 | encode));
8571 }
8572
8573 void Assembler::negq(Register dst) {
8574 int encode = prefixq_and_encode(dst->encoding());
8575 emit_int16((unsigned char)0xF7, (unsigned char)(0xD8 | encode));
8576 }
8577
8578 void Assembler::notq(Register dst) {
8579 int encode = prefixq_and_encode(dst->encoding());
8580 emit_int16((unsigned char)0xF7, (unsigned char)(0xD0 | encode));
8581 }
8582
8583 void Assembler::btsq(Address dst, int imm8) {
8584 assert(isByte(imm8), "not a byte");
8585 InstructionMark im(this);
8586 emit_int24(get_prefixq(dst), (unsigned char)0x0F, (unsigned char)0xBA);
8587 emit_operand(rbp /* 5 */, dst, 1);
8588 emit_int8(imm8);
8589 }
8590
8591 void Assembler::btrq(Address dst, int imm8) {
8592 assert(isByte(imm8), "not a byte");
8593 InstructionMark im(this);
8594 emit_int24(get_prefixq(dst), (unsigned char)0x0F, (unsigned char)0xBA);
8595 emit_operand(rsi /* 6 */, dst, 1);
8596 emit_int8(imm8);
8597 }
8598
8599 void Assembler::orq(Address dst, int32_t imm32) {
8600 InstructionMark im(this);
8601 emit_int16(get_prefixq(dst), (unsigned char)0x81);
8602 emit_operand(rcx, dst, 4);
8603 emit_int32(imm32);
8604 }
8605
8606 void Assembler::orq(Register dst, int32_t imm32) {
8607 (void) prefixq_and_encode(dst->encoding());
8608 emit_arith(0x81, 0xC8, dst, imm32);
8609 }
8610
8611 void Assembler::orq(Register dst, Address src) {
8612 InstructionMark im(this);
8613 emit_int16(get_prefixq(src, dst), 0x0B);
8614 emit_operand(dst, src);
8615 }
8616
8617 void Assembler::orq(Register dst, Register src) {
8618 (void) prefixq_and_encode(dst->encoding(), src->encoding());
8619 emit_arith(0x0B, 0xC0, dst, src);
8620 }
8621
8622 void Assembler::popcntq(Register dst, Address src) {
8623 assert(VM_Version::supports_popcnt(), "must support");
8624 InstructionMark im(this);
8625 emit_int32((unsigned char)0xF3, get_prefixq(src, dst), (unsigned char)0x0F, (unsigned char)0xB8);
8626 emit_operand(dst, src);
8627 }
8628
8629 void Assembler::popcntq(Register dst, Register src) {
8630 assert(VM_Version::supports_popcnt(), "must support");
8631 emit_int8((unsigned char)0xF3);
8632 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
8633 emit_int24((unsigned char)0x0F, (unsigned char)0xB8, (unsigned char)(0xC0 | encode));
8634 }
8635
8636 void Assembler::popq(Address dst) {
8637 InstructionMark im(this);
8638 emit_int16(get_prefixq(dst), (unsigned char)0x8F);
8639 emit_operand(rax, dst);
8640 }
8641
8642 // Precomputable: popa, pusha, vzeroupper
8643
8644 // The result of these routines are invariant from one invocation to another
8645 // invocation for the duration of a run. Caching the result on bootstrap
8646 // and copying it out on subsequent invocations can thus be beneficial
8647 static bool precomputed = false;
8648
8649 static u_char* popa_code = NULL;
8650 static int popa_len = 0;
8651
8652 static u_char* pusha_code = NULL;
8653 static int pusha_len = 0;
8654
8655 static u_char* vzup_code = NULL;
8656 static int vzup_len = 0;
8657
8658 void Assembler::precompute_instructions() {
8689 vzup_code = NEW_C_HEAP_ARRAY(u_char, vzup_len, mtInternal);
8690 memcpy(vzup_code, end_pusha, vzup_len);
8691 } else {
8692 vzup_code = pusha_code; // dummy
8693 }
8694
8695 assert(masm.code()->total_oop_size() == 0 &&
8696 masm.code()->total_metadata_size() == 0 &&
8697 masm.code()->total_relocation_size() == 0,
8698 "pre-computed code can't reference oops, metadata or contain relocations");
8699 }
8700
8701 static void emit_copy(CodeSection* code_section, u_char* src, int src_len) {
8702 assert(src != NULL, "code to copy must have been pre-computed");
8703 assert(code_section->limit() - code_section->end() > src_len, "code buffer not large enough");
8704 address end = code_section->end();
8705 memcpy(end, src, src_len);
8706 code_section->set_end(end + src_len);
8707 }
8708
8709
8710 void Assembler::popa() { // 64bit
8711 emit_copy(code_section(), popa_code, popa_len);
8712 }
8713
8714 void Assembler::popa_uncached() { // 64bit
8715 movq(r15, Address(rsp, 0));
8716 movq(r14, Address(rsp, wordSize));
8717 movq(r13, Address(rsp, 2 * wordSize));
8718 movq(r12, Address(rsp, 3 * wordSize));
8719 movq(r11, Address(rsp, 4 * wordSize));
8720 movq(r10, Address(rsp, 5 * wordSize));
8721 movq(r9, Address(rsp, 6 * wordSize));
8722 movq(r8, Address(rsp, 7 * wordSize));
8723 movq(rdi, Address(rsp, 8 * wordSize));
8724 movq(rsi, Address(rsp, 9 * wordSize));
8725 movq(rbp, Address(rsp, 10 * wordSize));
8726 // skip rsp
8727 movq(rbx, Address(rsp, 12 * wordSize));
8728 movq(rdx, Address(rsp, 13 * wordSize));
8729 movq(rcx, Address(rsp, 14 * wordSize));
8750 // skip rsp
8751 movq(Address(rsp, 10 * wordSize), rbp);
8752 movq(Address(rsp, 9 * wordSize), rsi);
8753 movq(Address(rsp, 8 * wordSize), rdi);
8754 movq(Address(rsp, 7 * wordSize), r8);
8755 movq(Address(rsp, 6 * wordSize), r9);
8756 movq(Address(rsp, 5 * wordSize), r10);
8757 movq(Address(rsp, 4 * wordSize), r11);
8758 movq(Address(rsp, 3 * wordSize), r12);
8759 movq(Address(rsp, 2 * wordSize), r13);
8760 movq(Address(rsp, wordSize), r14);
8761 movq(Address(rsp, 0), r15);
8762 }
8763
8764 void Assembler::vzeroupper() {
8765 emit_copy(code_section(), vzup_code, vzup_len);
8766 }
8767
8768 void Assembler::pushq(Address src) {
8769 InstructionMark im(this);
8770 emit_int16(get_prefixq(src), (unsigned char)0xFF);
8771 emit_operand(rsi, src);
8772 }
8773
8774 void Assembler::rclq(Register dst, int imm8) {
8775 assert(isShiftCount(imm8 >> 1), "illegal shift count");
8776 int encode = prefixq_and_encode(dst->encoding());
8777 if (imm8 == 1) {
8778 emit_int16((unsigned char)0xD1, (unsigned char)(0xD0 | encode));
8779 } else {
8780 emit_int24((unsigned char)0xC1, (unsigned char)(0xD0 | encode), imm8);
8781 }
8782 }
8783
8784 void Assembler::rcrq(Register dst, int imm8) {
8785 assert(isShiftCount(imm8 >> 1), "illegal shift count");
8786 int encode = prefixq_and_encode(dst->encoding());
8787 if (imm8 == 1) {
8788 emit_int16((unsigned char)0xD1, (unsigned char)(0xD8 | encode));
8789 } else {
8790 emit_int24((unsigned char)0xC1, (unsigned char)(0xD8 | encode), imm8);
8791 }
8792 }
8793
8794 void Assembler::rorq(Register dst, int imm8) {
8795 assert(isShiftCount(imm8 >> 1), "illegal shift count");
8796 int encode = prefixq_and_encode(dst->encoding());
8797 if (imm8 == 1) {
8798 emit_int16((unsigned char)0xD1, (unsigned char)(0xC8 | encode));
8799 } else {
8800 emit_int24((unsigned char)0xC1, (unsigned char)(0xc8 | encode), imm8);
8801 }
8802 }
8803
8804 void Assembler::rorxq(Register dst, Register src, int imm8) {
8805 assert(VM_Version::supports_bmi2(), "bit manipulation instructions not supported");
8806 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
8807 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F_3A, &attributes);
8808 emit_int24((unsigned char)0xF0, (unsigned char)(0xC0 | encode), imm8);
8809 }
8810
8811 void Assembler::rorxd(Register dst, Register src, int imm8) {
8812 assert(VM_Version::supports_bmi2(), "bit manipulation instructions not supported");
8813 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
8814 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F_3A, &attributes);
8815 emit_int24((unsigned char)0xF0, (unsigned char)(0xC0 | encode), imm8);
8816 }
8817
8818 void Assembler::sarq(Register dst, int imm8) {
8819 assert(isShiftCount(imm8 >> 1), "illegal shift count");
8820 int encode = prefixq_and_encode(dst->encoding());
8821 if (imm8 == 1) {
8822 emit_int16((unsigned char)0xD1, (unsigned char)(0xF8 | encode));
8823 } else {
8824 emit_int24((unsigned char)0xC1, (unsigned char)(0xF8 | encode), imm8);
8825 }
8826 }
8827
8828 void Assembler::sarq(Register dst) {
8829 int encode = prefixq_and_encode(dst->encoding());
8830 emit_int16((unsigned char)0xD3, (unsigned char)(0xF8 | encode));
8831 }
8832
8833 void Assembler::sbbq(Address dst, int32_t imm32) {
8834 InstructionMark im(this);
8835 prefixq(dst);
8836 emit_arith_operand(0x81, rbx, dst, imm32);
8837 }
8838
8839 void Assembler::sbbq(Register dst, int32_t imm32) {
8840 (void) prefixq_and_encode(dst->encoding());
8841 emit_arith(0x81, 0xD8, dst, imm32);
8842 }
8843
8844 void Assembler::sbbq(Register dst, Address src) {
8845 InstructionMark im(this);
8846 emit_int16(get_prefixq(src, dst), 0x1B);
8847 emit_operand(dst, src);
8848 }
8849
8850 void Assembler::sbbq(Register dst, Register src) {
8851 (void) prefixq_and_encode(dst->encoding(), src->encoding());
8852 emit_arith(0x1B, 0xC0, dst, src);
8853 }
8854
8855 void Assembler::shlq(Register dst, int imm8) {
8856 assert(isShiftCount(imm8 >> 1), "illegal shift count");
8857 int encode = prefixq_and_encode(dst->encoding());
8858 if (imm8 == 1) {
8859 emit_int16((unsigned char)0xD1, (unsigned char)(0xE0 | encode));
8860 } else {
8861 emit_int24((unsigned char)0xC1, (unsigned char)(0xE0 | encode), imm8);
8862 }
8863 }
8864
8865 void Assembler::shlq(Register dst) {
8866 int encode = prefixq_and_encode(dst->encoding());
8867 emit_int16((unsigned char)0xD3, (unsigned char)(0xE0 | encode));
8868 }
8869
8870 void Assembler::shrq(Register dst, int imm8) {
8871 assert(isShiftCount(imm8 >> 1), "illegal shift count");
8872 int encode = prefixq_and_encode(dst->encoding());
8873 emit_int24((unsigned char)0xC1, (unsigned char)(0xE8 | encode), imm8);
8874 }
8875
8876 void Assembler::shrq(Register dst) {
8877 int encode = prefixq_and_encode(dst->encoding());
8878 emit_int16((unsigned char)0xD3, 0xE8 | encode);
8879 }
8880
8881 void Assembler::subq(Address dst, int32_t imm32) {
8882 InstructionMark im(this);
8883 prefixq(dst);
8884 emit_arith_operand(0x81, rbp, dst, imm32);
8885 }
8886
8887 void Assembler::subq(Address dst, Register src) {
8888 InstructionMark im(this);
8889 emit_int16(get_prefixq(dst, src), 0x29);
8890 emit_operand(src, dst);
8891 }
8892
8893 void Assembler::subq(Register dst, int32_t imm32) {
8894 (void) prefixq_and_encode(dst->encoding());
8895 emit_arith(0x81, 0xE8, dst, imm32);
8896 }
8897
8898 // Force generation of a 4 byte immediate value even if it fits into 8bit
8899 void Assembler::subq_imm32(Register dst, int32_t imm32) {
8900 (void) prefixq_and_encode(dst->encoding());
8901 emit_arith_imm32(0x81, 0xE8, dst, imm32);
8902 }
8903
8904 void Assembler::subq(Register dst, Address src) {
8905 InstructionMark im(this);
8906 emit_int16(get_prefixq(src, dst), 0x2B);
8907 emit_operand(dst, src);
8908 }
8909
8910 void Assembler::subq(Register dst, Register src) {
8911 (void) prefixq_and_encode(dst->encoding(), src->encoding());
8912 emit_arith(0x2B, 0xC0, dst, src);
8913 }
8914
8915 void Assembler::testq(Register dst, int32_t imm32) {
8916 // not using emit_arith because test
8917 // doesn't support sign-extension of
8918 // 8bit operands
8919 int encode = dst->encoding();
8920 if (encode == 0) {
8921 emit_int16(REX_W, (unsigned char)0xA9);
8922 } else {
8923 encode = prefixq_and_encode(encode);
8924 emit_int16((unsigned char)0xF7, (unsigned char)(0xC0 | encode));
8925 }
8926 emit_int32(imm32);
8927 }
8928
8929 void Assembler::testq(Register dst, Register src) {
8930 (void) prefixq_and_encode(dst->encoding(), src->encoding());
8931 emit_arith(0x85, 0xC0, dst, src);
8932 }
8933
8934 void Assembler::testq(Register dst, Address src) {
8935 InstructionMark im(this);
8936 emit_int16(get_prefixq(src, dst), (unsigned char)0x85);
8937 emit_operand(dst, src);
8938 }
8939
8940 void Assembler::xaddq(Address dst, Register src) {
8941 InstructionMark im(this);
8942 emit_int24(get_prefixq(dst, src), 0x0F, (unsigned char)0xC1);
8943 emit_operand(src, dst);
8944 }
8945
8946 void Assembler::xchgq(Register dst, Address src) {
8947 InstructionMark im(this);
8948 emit_int16(get_prefixq(src, dst), (unsigned char)0x87);
8949 emit_operand(dst, src);
8950 }
8951
8952 void Assembler::xchgq(Register dst, Register src) {
8953 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
8954 emit_int16((unsigned char)0x87, (unsigned char)(0xc0 | encode));
8955 }
8956
8957 void Assembler::xorq(Register dst, Register src) {
8958 (void) prefixq_and_encode(dst->encoding(), src->encoding());
8959 emit_arith(0x33, 0xC0, dst, src);
8960 }
8961
8962 void Assembler::xorq(Register dst, Address src) {
8963 InstructionMark im(this);
8964 emit_int16(get_prefixq(src, dst), 0x33);
8965 emit_operand(dst, src);
8966 }
8967
8968 #endif // !LP64
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