1 //
2 // Copyright (c) 1998, 2016, Oracle and/or its affiliates. All rights reserved.
3 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 //
5 // This code is free software; you can redistribute it and/or modify it
6 // under the terms of the GNU General Public License version 2 only, as
7 // published by the Free Software Foundation.
8 //
9 // This code is distributed in the hope that it will be useful, but WITHOUT
10 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 // version 2 for more details (a copy is included in the LICENSE file that
13 // accompanied this code).
14 //
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20 // or visit www.oracle.com if you need additional information or have any
21 // questions.
22 //
23 //
24
25 // SPARC Architecture Description File
26
27 //----------REGISTER DEFINITION BLOCK------------------------------------------
28 // This information is used by the matcher and the register allocator to
29 // describe individual registers and classes of registers within the target
30 // archtecture.
31 register %{
32 //----------Architecture Description Register Definitions----------------------
33 // General Registers
34 // "reg_def" name ( register save type, C convention save type,
35 // ideal register type, encoding, vm name );
36 // Register Save Types:
37 //
38 // NS = No-Save: The register allocator assumes that these registers
39 // can be used without saving upon entry to the method, &
40 // that they do not need to be saved at call sites.
41 //
42 // SOC = Save-On-Call: The register allocator assumes that these registers
43 // can be used without saving upon entry to the method,
44 // but that they must be saved at call sites.
45 //
46 // SOE = Save-On-Entry: The register allocator assumes that these registers
47 // must be saved before using them upon entry to the
48 // method, but they do not need to be saved at call
49 // sites.
50 //
51 // AS = Always-Save: The register allocator assumes that these registers
52 // must be saved before using them upon entry to the
53 // method, & that they must be saved at call sites.
54 //
55 // Ideal Register Type is used to determine how to save & restore a
56 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get
57 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI.
58 //
59 // The encoding number is the actual bit-pattern placed into the opcodes.
60
61
62 // ----------------------------
63 // Integer/Long Registers
64 // ----------------------------
65
66 // Need to expose the hi/lo aspect of 64-bit registers
67 // This register set is used for both the 64-bit build and
68 // the 32-bit build with 1-register longs.
69
70 // Global Registers 0-7
71 reg_def R_G0H( NS, NS, Op_RegI,128, G0->as_VMReg()->next());
72 reg_def R_G0 ( NS, NS, Op_RegI, 0, G0->as_VMReg());
73 reg_def R_G1H(SOC, SOC, Op_RegI,129, G1->as_VMReg()->next());
74 reg_def R_G1 (SOC, SOC, Op_RegI, 1, G1->as_VMReg());
75 reg_def R_G2H( NS, NS, Op_RegI,130, G2->as_VMReg()->next());
76 reg_def R_G2 ( NS, NS, Op_RegI, 2, G2->as_VMReg());
77 reg_def R_G3H(SOC, SOC, Op_RegI,131, G3->as_VMReg()->next());
78 reg_def R_G3 (SOC, SOC, Op_RegI, 3, G3->as_VMReg());
79 reg_def R_G4H(SOC, SOC, Op_RegI,132, G4->as_VMReg()->next());
80 reg_def R_G4 (SOC, SOC, Op_RegI, 4, G4->as_VMReg());
81 reg_def R_G5H(SOC, SOC, Op_RegI,133, G5->as_VMReg()->next());
82 reg_def R_G5 (SOC, SOC, Op_RegI, 5, G5->as_VMReg());
83 reg_def R_G6H( NS, NS, Op_RegI,134, G6->as_VMReg()->next());
84 reg_def R_G6 ( NS, NS, Op_RegI, 6, G6->as_VMReg());
85 reg_def R_G7H( NS, NS, Op_RegI,135, G7->as_VMReg()->next());
86 reg_def R_G7 ( NS, NS, Op_RegI, 7, G7->as_VMReg());
87
88 // Output Registers 0-7
89 reg_def R_O0H(SOC, SOC, Op_RegI,136, O0->as_VMReg()->next());
90 reg_def R_O0 (SOC, SOC, Op_RegI, 8, O0->as_VMReg());
91 reg_def R_O1H(SOC, SOC, Op_RegI,137, O1->as_VMReg()->next());
92 reg_def R_O1 (SOC, SOC, Op_RegI, 9, O1->as_VMReg());
93 reg_def R_O2H(SOC, SOC, Op_RegI,138, O2->as_VMReg()->next());
94 reg_def R_O2 (SOC, SOC, Op_RegI, 10, O2->as_VMReg());
95 reg_def R_O3H(SOC, SOC, Op_RegI,139, O3->as_VMReg()->next());
96 reg_def R_O3 (SOC, SOC, Op_RegI, 11, O3->as_VMReg());
97 reg_def R_O4H(SOC, SOC, Op_RegI,140, O4->as_VMReg()->next());
98 reg_def R_O4 (SOC, SOC, Op_RegI, 12, O4->as_VMReg());
99 reg_def R_O5H(SOC, SOC, Op_RegI,141, O5->as_VMReg()->next());
100 reg_def R_O5 (SOC, SOC, Op_RegI, 13, O5->as_VMReg());
101 reg_def R_SPH( NS, NS, Op_RegI,142, SP->as_VMReg()->next());
102 reg_def R_SP ( NS, NS, Op_RegI, 14, SP->as_VMReg());
103 reg_def R_O7H(SOC, SOC, Op_RegI,143, O7->as_VMReg()->next());
104 reg_def R_O7 (SOC, SOC, Op_RegI, 15, O7->as_VMReg());
105
106 // Local Registers 0-7
107 reg_def R_L0H( NS, NS, Op_RegI,144, L0->as_VMReg()->next());
108 reg_def R_L0 ( NS, NS, Op_RegI, 16, L0->as_VMReg());
109 reg_def R_L1H( NS, NS, Op_RegI,145, L1->as_VMReg()->next());
110 reg_def R_L1 ( NS, NS, Op_RegI, 17, L1->as_VMReg());
111 reg_def R_L2H( NS, NS, Op_RegI,146, L2->as_VMReg()->next());
112 reg_def R_L2 ( NS, NS, Op_RegI, 18, L2->as_VMReg());
113 reg_def R_L3H( NS, NS, Op_RegI,147, L3->as_VMReg()->next());
114 reg_def R_L3 ( NS, NS, Op_RegI, 19, L3->as_VMReg());
115 reg_def R_L4H( NS, NS, Op_RegI,148, L4->as_VMReg()->next());
116 reg_def R_L4 ( NS, NS, Op_RegI, 20, L4->as_VMReg());
117 reg_def R_L5H( NS, NS, Op_RegI,149, L5->as_VMReg()->next());
118 reg_def R_L5 ( NS, NS, Op_RegI, 21, L5->as_VMReg());
119 reg_def R_L6H( NS, NS, Op_RegI,150, L6->as_VMReg()->next());
120 reg_def R_L6 ( NS, NS, Op_RegI, 22, L6->as_VMReg());
121 reg_def R_L7H( NS, NS, Op_RegI,151, L7->as_VMReg()->next());
122 reg_def R_L7 ( NS, NS, Op_RegI, 23, L7->as_VMReg());
123
124 // Input Registers 0-7
125 reg_def R_I0H( NS, NS, Op_RegI,152, I0->as_VMReg()->next());
126 reg_def R_I0 ( NS, NS, Op_RegI, 24, I0->as_VMReg());
127 reg_def R_I1H( NS, NS, Op_RegI,153, I1->as_VMReg()->next());
128 reg_def R_I1 ( NS, NS, Op_RegI, 25, I1->as_VMReg());
129 reg_def R_I2H( NS, NS, Op_RegI,154, I2->as_VMReg()->next());
130 reg_def R_I2 ( NS, NS, Op_RegI, 26, I2->as_VMReg());
131 reg_def R_I3H( NS, NS, Op_RegI,155, I3->as_VMReg()->next());
132 reg_def R_I3 ( NS, NS, Op_RegI, 27, I3->as_VMReg());
133 reg_def R_I4H( NS, NS, Op_RegI,156, I4->as_VMReg()->next());
134 reg_def R_I4 ( NS, NS, Op_RegI, 28, I4->as_VMReg());
135 reg_def R_I5H( NS, NS, Op_RegI,157, I5->as_VMReg()->next());
136 reg_def R_I5 ( NS, NS, Op_RegI, 29, I5->as_VMReg());
137 reg_def R_FPH( NS, NS, Op_RegI,158, FP->as_VMReg()->next());
138 reg_def R_FP ( NS, NS, Op_RegI, 30, FP->as_VMReg());
139 reg_def R_I7H( NS, NS, Op_RegI,159, I7->as_VMReg()->next());
140 reg_def R_I7 ( NS, NS, Op_RegI, 31, I7->as_VMReg());
141
142 // ----------------------------
143 // Float/Double Registers
144 // ----------------------------
145
146 // Float Registers
147 reg_def R_F0 ( SOC, SOC, Op_RegF, 0, F0->as_VMReg());
148 reg_def R_F1 ( SOC, SOC, Op_RegF, 1, F1->as_VMReg());
149 reg_def R_F2 ( SOC, SOC, Op_RegF, 2, F2->as_VMReg());
150 reg_def R_F3 ( SOC, SOC, Op_RegF, 3, F3->as_VMReg());
151 reg_def R_F4 ( SOC, SOC, Op_RegF, 4, F4->as_VMReg());
152 reg_def R_F5 ( SOC, SOC, Op_RegF, 5, F5->as_VMReg());
153 reg_def R_F6 ( SOC, SOC, Op_RegF, 6, F6->as_VMReg());
154 reg_def R_F7 ( SOC, SOC, Op_RegF, 7, F7->as_VMReg());
155 reg_def R_F8 ( SOC, SOC, Op_RegF, 8, F8->as_VMReg());
156 reg_def R_F9 ( SOC, SOC, Op_RegF, 9, F9->as_VMReg());
157 reg_def R_F10( SOC, SOC, Op_RegF, 10, F10->as_VMReg());
158 reg_def R_F11( SOC, SOC, Op_RegF, 11, F11->as_VMReg());
159 reg_def R_F12( SOC, SOC, Op_RegF, 12, F12->as_VMReg());
160 reg_def R_F13( SOC, SOC, Op_RegF, 13, F13->as_VMReg());
161 reg_def R_F14( SOC, SOC, Op_RegF, 14, F14->as_VMReg());
162 reg_def R_F15( SOC, SOC, Op_RegF, 15, F15->as_VMReg());
163 reg_def R_F16( SOC, SOC, Op_RegF, 16, F16->as_VMReg());
164 reg_def R_F17( SOC, SOC, Op_RegF, 17, F17->as_VMReg());
165 reg_def R_F18( SOC, SOC, Op_RegF, 18, F18->as_VMReg());
166 reg_def R_F19( SOC, SOC, Op_RegF, 19, F19->as_VMReg());
167 reg_def R_F20( SOC, SOC, Op_RegF, 20, F20->as_VMReg());
168 reg_def R_F21( SOC, SOC, Op_RegF, 21, F21->as_VMReg());
169 reg_def R_F22( SOC, SOC, Op_RegF, 22, F22->as_VMReg());
170 reg_def R_F23( SOC, SOC, Op_RegF, 23, F23->as_VMReg());
171 reg_def R_F24( SOC, SOC, Op_RegF, 24, F24->as_VMReg());
172 reg_def R_F25( SOC, SOC, Op_RegF, 25, F25->as_VMReg());
173 reg_def R_F26( SOC, SOC, Op_RegF, 26, F26->as_VMReg());
174 reg_def R_F27( SOC, SOC, Op_RegF, 27, F27->as_VMReg());
175 reg_def R_F28( SOC, SOC, Op_RegF, 28, F28->as_VMReg());
176 reg_def R_F29( SOC, SOC, Op_RegF, 29, F29->as_VMReg());
177 reg_def R_F30( SOC, SOC, Op_RegF, 30, F30->as_VMReg());
178 reg_def R_F31( SOC, SOC, Op_RegF, 31, F31->as_VMReg());
179
180 // Double Registers
181 // The rules of ADL require that double registers be defined in pairs.
182 // Each pair must be two 32-bit values, but not necessarily a pair of
183 // single float registers. In each pair, ADLC-assigned register numbers
184 // must be adjacent, with the lower number even. Finally, when the
185 // CPU stores such a register pair to memory, the word associated with
186 // the lower ADLC-assigned number must be stored to the lower address.
187
188 // These definitions specify the actual bit encodings of the sparc
189 // double fp register numbers. FloatRegisterImpl in register_sparc.hpp
190 // wants 0-63, so we have to convert every time we want to use fp regs
191 // with the macroassembler, using reg_to_DoubleFloatRegister_object().
192 // 255 is a flag meaning "don't go here".
193 // I believe we can't handle callee-save doubles D32 and up until
194 // the place in the sparc stack crawler that asserts on the 255 is
195 // fixed up.
196 reg_def R_D32 (SOC, SOC, Op_RegD, 1, F32->as_VMReg());
197 reg_def R_D32x(SOC, SOC, Op_RegD,255, F32->as_VMReg()->next());
198 reg_def R_D34 (SOC, SOC, Op_RegD, 3, F34->as_VMReg());
199 reg_def R_D34x(SOC, SOC, Op_RegD,255, F34->as_VMReg()->next());
200 reg_def R_D36 (SOC, SOC, Op_RegD, 5, F36->as_VMReg());
201 reg_def R_D36x(SOC, SOC, Op_RegD,255, F36->as_VMReg()->next());
202 reg_def R_D38 (SOC, SOC, Op_RegD, 7, F38->as_VMReg());
203 reg_def R_D38x(SOC, SOC, Op_RegD,255, F38->as_VMReg()->next());
204 reg_def R_D40 (SOC, SOC, Op_RegD, 9, F40->as_VMReg());
205 reg_def R_D40x(SOC, SOC, Op_RegD,255, F40->as_VMReg()->next());
206 reg_def R_D42 (SOC, SOC, Op_RegD, 11, F42->as_VMReg());
207 reg_def R_D42x(SOC, SOC, Op_RegD,255, F42->as_VMReg()->next());
208 reg_def R_D44 (SOC, SOC, Op_RegD, 13, F44->as_VMReg());
209 reg_def R_D44x(SOC, SOC, Op_RegD,255, F44->as_VMReg()->next());
210 reg_def R_D46 (SOC, SOC, Op_RegD, 15, F46->as_VMReg());
211 reg_def R_D46x(SOC, SOC, Op_RegD,255, F46->as_VMReg()->next());
212 reg_def R_D48 (SOC, SOC, Op_RegD, 17, F48->as_VMReg());
213 reg_def R_D48x(SOC, SOC, Op_RegD,255, F48->as_VMReg()->next());
214 reg_def R_D50 (SOC, SOC, Op_RegD, 19, F50->as_VMReg());
215 reg_def R_D50x(SOC, SOC, Op_RegD,255, F50->as_VMReg()->next());
216 reg_def R_D52 (SOC, SOC, Op_RegD, 21, F52->as_VMReg());
217 reg_def R_D52x(SOC, SOC, Op_RegD,255, F52->as_VMReg()->next());
218 reg_def R_D54 (SOC, SOC, Op_RegD, 23, F54->as_VMReg());
219 reg_def R_D54x(SOC, SOC, Op_RegD,255, F54->as_VMReg()->next());
220 reg_def R_D56 (SOC, SOC, Op_RegD, 25, F56->as_VMReg());
221 reg_def R_D56x(SOC, SOC, Op_RegD,255, F56->as_VMReg()->next());
222 reg_def R_D58 (SOC, SOC, Op_RegD, 27, F58->as_VMReg());
223 reg_def R_D58x(SOC, SOC, Op_RegD,255, F58->as_VMReg()->next());
224 reg_def R_D60 (SOC, SOC, Op_RegD, 29, F60->as_VMReg());
225 reg_def R_D60x(SOC, SOC, Op_RegD,255, F60->as_VMReg()->next());
226 reg_def R_D62 (SOC, SOC, Op_RegD, 31, F62->as_VMReg());
227 reg_def R_D62x(SOC, SOC, Op_RegD,255, F62->as_VMReg()->next());
228
229
230 // ----------------------------
231 // Special Registers
232 // Condition Codes Flag Registers
233 // I tried to break out ICC and XCC but it's not very pretty.
234 // Every Sparc instruction which defs/kills one also kills the other.
235 // Hence every compare instruction which defs one kind of flags ends
236 // up needing a kill of the other.
237 reg_def CCR (SOC, SOC, Op_RegFlags, 0, VMRegImpl::Bad());
238
239 reg_def FCC0(SOC, SOC, Op_RegFlags, 0, VMRegImpl::Bad());
240 reg_def FCC1(SOC, SOC, Op_RegFlags, 1, VMRegImpl::Bad());
241 reg_def FCC2(SOC, SOC, Op_RegFlags, 2, VMRegImpl::Bad());
242 reg_def FCC3(SOC, SOC, Op_RegFlags, 3, VMRegImpl::Bad());
243
244 // ----------------------------
245 // Specify the enum values for the registers. These enums are only used by the
246 // OptoReg "class". We can convert these enum values at will to VMReg when needed
247 // for visibility to the rest of the vm. The order of this enum influences the
248 // register allocator so having the freedom to set this order and not be stuck
249 // with the order that is natural for the rest of the vm is worth it.
250 alloc_class chunk0(
251 R_L0,R_L0H, R_L1,R_L1H, R_L2,R_L2H, R_L3,R_L3H, R_L4,R_L4H, R_L5,R_L5H, R_L6,R_L6H, R_L7,R_L7H,
252 R_G0,R_G0H, R_G1,R_G1H, R_G2,R_G2H, R_G3,R_G3H, R_G4,R_G4H, R_G5,R_G5H, R_G6,R_G6H, R_G7,R_G7H,
253 R_O7,R_O7H, R_SP,R_SPH, R_O0,R_O0H, R_O1,R_O1H, R_O2,R_O2H, R_O3,R_O3H, R_O4,R_O4H, R_O5,R_O5H,
254 R_I0,R_I0H, R_I1,R_I1H, R_I2,R_I2H, R_I3,R_I3H, R_I4,R_I4H, R_I5,R_I5H, R_FP,R_FPH, R_I7,R_I7H);
255
256 // Note that a register is not allocatable unless it is also mentioned
257 // in a widely-used reg_class below. Thus, R_G7 and R_G0 are outside i_reg.
258
259 alloc_class chunk1(
260 // The first registers listed here are those most likely to be used
261 // as temporaries. We move F0..F7 away from the front of the list,
262 // to reduce the likelihood of interferences with parameters and
263 // return values. Likewise, we avoid using F0/F1 for parameters,
264 // since they are used for return values.
265 // This FPU fine-tuning is worth about 1% on the SPEC geomean.
266 R_F8 ,R_F9 ,R_F10,R_F11,R_F12,R_F13,R_F14,R_F15,
267 R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,
268 R_F24,R_F25,R_F26,R_F27,R_F28,R_F29,R_F30,R_F31,
269 R_F0 ,R_F1 ,R_F2 ,R_F3 ,R_F4 ,R_F5 ,R_F6 ,R_F7 , // used for arguments and return values
270 R_D32,R_D32x,R_D34,R_D34x,R_D36,R_D36x,R_D38,R_D38x,
271 R_D40,R_D40x,R_D42,R_D42x,R_D44,R_D44x,R_D46,R_D46x,
272 R_D48,R_D48x,R_D50,R_D50x,R_D52,R_D52x,R_D54,R_D54x,
273 R_D56,R_D56x,R_D58,R_D58x,R_D60,R_D60x,R_D62,R_D62x);
274
275 alloc_class chunk2(CCR, FCC0, FCC1, FCC2, FCC3);
276
277 //----------Architecture Description Register Classes--------------------------
278 // Several register classes are automatically defined based upon information in
279 // this architecture description.
280 // 1) reg_class inline_cache_reg ( as defined in frame section )
281 // 2) reg_class interpreter_method_oop_reg ( as defined in frame section )
282 // 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ )
283 //
284
285 // G0 is not included in integer class since it has special meaning.
286 reg_class g0_reg(R_G0);
287
288 // ----------------------------
289 // Integer Register Classes
290 // ----------------------------
291 // Exclusions from i_reg:
292 // R_G0: hardwired zero
293 // R_G2: reserved by HotSpot to the TLS register (invariant within Java)
294 // R_G6: reserved by Solaris ABI to tools
295 // R_G7: reserved by Solaris ABI to libthread
296 // R_O7: Used as a temp in many encodings
297 reg_class int_reg(R_G1,R_G3,R_G4,R_G5,R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,R_I0,R_I1,R_I2,R_I3,R_I4,R_I5);
298
299 // Class for all integer registers, except the G registers. This is used for
300 // encodings which use G registers as temps. The regular inputs to such
301 // instructions use a "notemp_" prefix, as a hack to ensure that the allocator
302 // will not put an input into a temp register.
303 reg_class notemp_int_reg(R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,R_I0,R_I1,R_I2,R_I3,R_I4,R_I5);
304
305 reg_class g1_regI(R_G1);
306 reg_class g3_regI(R_G3);
307 reg_class g4_regI(R_G4);
308 reg_class o0_regI(R_O0);
309 reg_class o7_regI(R_O7);
310
311 // ----------------------------
312 // Pointer Register Classes
313 // ----------------------------
314 #ifdef _LP64
315 // 64-bit build means 64-bit pointers means hi/lo pairs
316 reg_class ptr_reg( R_G1H,R_G1, R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5,
317 R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5,
318 R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7,
319 R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5 );
320 // Lock encodings use G3 and G4 internally
321 reg_class lock_ptr_reg( R_G1H,R_G1, R_G5H,R_G5,
322 R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5,
323 R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7,
324 R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5 );
325 // Special class for storeP instructions, which can store SP or RPC to TLS.
326 // It is also used for memory addressing, allowing direct TLS addressing.
327 reg_class sp_ptr_reg( R_G1H,R_G1, R_G2H,R_G2, R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5,
328 R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5, R_SPH,R_SP,
329 R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7,
330 R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5, R_FPH,R_FP );
331 // R_L7 is the lowest-priority callee-save (i.e., NS) register
332 // We use it to save R_G2 across calls out of Java.
333 reg_class l7_regP(R_L7H,R_L7);
334
335 // Other special pointer regs
336 reg_class g1_regP(R_G1H,R_G1);
337 reg_class g2_regP(R_G2H,R_G2);
338 reg_class g3_regP(R_G3H,R_G3);
339 reg_class g4_regP(R_G4H,R_G4);
340 reg_class g5_regP(R_G5H,R_G5);
341 reg_class i0_regP(R_I0H,R_I0);
342 reg_class o0_regP(R_O0H,R_O0);
343 reg_class o1_regP(R_O1H,R_O1);
344 reg_class o2_regP(R_O2H,R_O2);
345 reg_class o7_regP(R_O7H,R_O7);
346
347 #else // _LP64
348 // 32-bit build means 32-bit pointers means 1 register.
349 reg_class ptr_reg( R_G1, R_G3,R_G4,R_G5,
350 R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,
351 R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,
352 R_I0,R_I1,R_I2,R_I3,R_I4,R_I5);
353 // Lock encodings use G3 and G4 internally
354 reg_class lock_ptr_reg(R_G1, R_G5,
355 R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,
356 R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,
357 R_I0,R_I1,R_I2,R_I3,R_I4,R_I5);
358 // Special class for storeP instructions, which can store SP or RPC to TLS.
359 // It is also used for memory addressing, allowing direct TLS addressing.
360 reg_class sp_ptr_reg( R_G1,R_G2,R_G3,R_G4,R_G5,
361 R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_SP,
362 R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,
363 R_I0,R_I1,R_I2,R_I3,R_I4,R_I5,R_FP);
364 // R_L7 is the lowest-priority callee-save (i.e., NS) register
365 // We use it to save R_G2 across calls out of Java.
366 reg_class l7_regP(R_L7);
367
368 // Other special pointer regs
369 reg_class g1_regP(R_G1);
370 reg_class g2_regP(R_G2);
371 reg_class g3_regP(R_G3);
372 reg_class g4_regP(R_G4);
373 reg_class g5_regP(R_G5);
374 reg_class i0_regP(R_I0);
375 reg_class o0_regP(R_O0);
376 reg_class o1_regP(R_O1);
377 reg_class o2_regP(R_O2);
378 reg_class o7_regP(R_O7);
379 #endif // _LP64
380
381
382 // ----------------------------
383 // Long Register Classes
384 // ----------------------------
385 // Longs in 1 register. Aligned adjacent hi/lo pairs.
386 // Note: O7 is never in this class; it is sometimes used as an encoding temp.
387 reg_class long_reg( R_G1H,R_G1, R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5
388 ,R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5
389 #ifdef _LP64
390 // 64-bit, longs in 1 register: use all 64-bit integer registers
391 // 32-bit, longs in 1 register: cannot use I's and L's. Restrict to O's and G's.
392 ,R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7
393 ,R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5
394 #endif // _LP64
395 );
396
397 reg_class g1_regL(R_G1H,R_G1);
398 reg_class g3_regL(R_G3H,R_G3);
399 reg_class o2_regL(R_O2H,R_O2);
400 reg_class o7_regL(R_O7H,R_O7);
401
402 // ----------------------------
403 // Special Class for Condition Code Flags Register
404 reg_class int_flags(CCR);
405 reg_class float_flags(FCC0,FCC1,FCC2,FCC3);
406 reg_class float_flag0(FCC0);
407
408
409 // ----------------------------
410 // Float Point Register Classes
411 // ----------------------------
412 // Skip F30/F31, they are reserved for mem-mem copies
413 reg_class sflt_reg(R_F0,R_F1,R_F2,R_F3,R_F4,R_F5,R_F6,R_F7,R_F8,R_F9,R_F10,R_F11,R_F12,R_F13,R_F14,R_F15,R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29);
414
415 // Paired floating point registers--they show up in the same order as the floats,
416 // but they are used with the "Op_RegD" type, and always occur in even/odd pairs.
417 reg_class dflt_reg(R_F0, R_F1, R_F2, R_F3, R_F4, R_F5, R_F6, R_F7, R_F8, R_F9, R_F10,R_F11,R_F12,R_F13,R_F14,R_F15,
418 R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29,
419 /* Use extra V9 double registers; this AD file does not support V8 */
420 R_D32,R_D32x,R_D34,R_D34x,R_D36,R_D36x,R_D38,R_D38x,R_D40,R_D40x,R_D42,R_D42x,R_D44,R_D44x,R_D46,R_D46x,
421 R_D48,R_D48x,R_D50,R_D50x,R_D52,R_D52x,R_D54,R_D54x,R_D56,R_D56x,R_D58,R_D58x,R_D60,R_D60x,R_D62,R_D62x
422 );
423
424 // Paired floating point registers--they show up in the same order as the floats,
425 // but they are used with the "Op_RegD" type, and always occur in even/odd pairs.
426 // This class is usable for mis-aligned loads as happen in I2C adapters.
427 reg_class dflt_low_reg(R_F0, R_F1, R_F2, R_F3, R_F4, R_F5, R_F6, R_F7, R_F8, R_F9, R_F10,R_F11,R_F12,R_F13,R_F14,R_F15,
428 R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29);
429 %}
430
431 //----------DEFINITION BLOCK---------------------------------------------------
432 // Define name --> value mappings to inform the ADLC of an integer valued name
433 // Current support includes integer values in the range [0, 0x7FFFFFFF]
434 // Format:
435 // int_def <name> ( <int_value>, <expression>);
436 // Generated Code in ad_<arch>.hpp
437 // #define <name> (<expression>)
438 // // value == <int_value>
439 // Generated code in ad_<arch>.cpp adlc_verification()
440 // assert( <name> == <int_value>, "Expect (<expression>) to equal <int_value>");
441 //
442 definitions %{
443 // The default cost (of an ALU instruction).
444 int_def DEFAULT_COST ( 100, 100);
445 int_def HUGE_COST (1000000, 1000000);
446
447 // Memory refs are twice as expensive as run-of-the-mill.
448 int_def MEMORY_REF_COST ( 200, DEFAULT_COST * 2);
449
450 // Branches are even more expensive.
451 int_def BRANCH_COST ( 300, DEFAULT_COST * 3);
452 int_def CALL_COST ( 300, DEFAULT_COST * 3);
453 %}
454
455
456 //----------SOURCE BLOCK-------------------------------------------------------
457 // This is a block of C++ code which provides values, functions, and
458 // definitions necessary in the rest of the architecture description
459 source_hpp %{
460 // Header information of the source block.
461 // Method declarations/definitions which are used outside
462 // the ad-scope can conveniently be defined here.
463 //
464 // To keep related declarations/definitions/uses close together,
465 // we switch between source %{ }% and source_hpp %{ }% freely as needed.
466
467 // Must be visible to the DFA in dfa_sparc.cpp
468 extern bool can_branch_register( Node *bol, Node *cmp );
469
470 extern bool use_block_zeroing(Node* count);
471
472 // Macros to extract hi & lo halves from a long pair.
473 // G0 is not part of any long pair, so assert on that.
474 // Prevents accidentally using G1 instead of G0.
475 #define LONG_HI_REG(x) (x)
476 #define LONG_LO_REG(x) (x)
477
478 class CallStubImpl {
479
480 //--------------------------------------------------------------
481 //---< Used for optimization in Compile::Shorten_branches >---
482 //--------------------------------------------------------------
483
484 public:
485 // Size of call trampoline stub.
486 static uint size_call_trampoline() {
487 return 0; // no call trampolines on this platform
488 }
489
490 // number of relocations needed by a call trampoline stub
491 static uint reloc_call_trampoline() {
492 return 0; // no call trampolines on this platform
493 }
494 };
495
496 class HandlerImpl {
497
498 public:
499
500 static int emit_exception_handler(CodeBuffer &cbuf);
501 static int emit_deopt_handler(CodeBuffer& cbuf);
502
503 static uint size_exception_handler() {
504 if (TraceJumps) {
505 return (400); // just a guess
506 }
507 return ( NativeJump::instruction_size ); // sethi;jmp;nop
508 }
509
510 static uint size_deopt_handler() {
511 if (TraceJumps) {
512 return (400); // just a guess
513 }
514 return ( 4+ NativeJump::instruction_size ); // save;sethi;jmp;restore
515 }
516 };
517
518 %}
519
520 source %{
521 #define __ _masm.
522
523 // tertiary op of a LoadP or StoreP encoding
524 #define REGP_OP true
525
526 static FloatRegister reg_to_SingleFloatRegister_object(int register_encoding);
527 static FloatRegister reg_to_DoubleFloatRegister_object(int register_encoding);
528 static Register reg_to_register_object(int register_encoding);
529
530 // Used by the DFA in dfa_sparc.cpp.
531 // Check for being able to use a V9 branch-on-register. Requires a
532 // compare-vs-zero, equal/not-equal, of a value which was zero- or sign-
533 // extended. Doesn't work following an integer ADD, for example, because of
534 // overflow (-1 incremented yields 0 plus a carry in the high-order word). On
535 // 32-bit V9 systems, interrupts currently blow away the high-order 32 bits and
536 // replace them with zero, which could become sign-extension in a different OS
537 // release. There's no obvious reason why an interrupt will ever fill these
538 // bits with non-zero junk (the registers are reloaded with standard LD
539 // instructions which either zero-fill or sign-fill).
540 bool can_branch_register( Node *bol, Node *cmp ) {
541 if( !BranchOnRegister ) return false;
542 #ifdef _LP64
543 if( cmp->Opcode() == Op_CmpP )
544 return true; // No problems with pointer compares
545 #endif
546 if( cmp->Opcode() == Op_CmpL )
547 return true; // No problems with long compares
548
549 if( !SparcV9RegsHiBitsZero ) return false;
550 if( bol->as_Bool()->_test._test != BoolTest::ne &&
551 bol->as_Bool()->_test._test != BoolTest::eq )
552 return false;
553
554 // Check for comparing against a 'safe' value. Any operation which
555 // clears out the high word is safe. Thus, loads and certain shifts
556 // are safe, as are non-negative constants. Any operation which
557 // preserves zero bits in the high word is safe as long as each of its
558 // inputs are safe. Thus, phis and bitwise booleans are safe if their
559 // inputs are safe. At present, the only important case to recognize
560 // seems to be loads. Constants should fold away, and shifts &
561 // logicals can use the 'cc' forms.
562 Node *x = cmp->in(1);
563 if( x->is_Load() ) return true;
564 if( x->is_Phi() ) {
565 for( uint i = 1; i < x->req(); i++ )
566 if( !x->in(i)->is_Load() )
567 return false;
568 return true;
569 }
570 return false;
571 }
572
573 bool use_block_zeroing(Node* count) {
574 // Use BIS for zeroing if count is not constant
575 // or it is >= BlockZeroingLowLimit.
576 return UseBlockZeroing && (count->find_intptr_t_con(BlockZeroingLowLimit) >= BlockZeroingLowLimit);
577 }
578
579 // ****************************************************************************
580
581 // REQUIRED FUNCTIONALITY
582
583 // !!!!! Special hack to get all type of calls to specify the byte offset
584 // from the start of the call to the point where the return address
585 // will point.
586 // The "return address" is the address of the call instruction, plus 8.
587
588 int MachCallStaticJavaNode::ret_addr_offset() {
589 int offset = NativeCall::instruction_size; // call; delay slot
590 if (_method_handle_invoke)
591 offset += 4; // restore SP
592 return offset;
593 }
594
595 int MachCallDynamicJavaNode::ret_addr_offset() {
596 int vtable_index = this->_vtable_index;
597 if (vtable_index < 0) {
598 // must be invalid_vtable_index, not nonvirtual_vtable_index
599 assert(vtable_index == Method::invalid_vtable_index, "correct sentinel value");
600 return (NativeMovConstReg::instruction_size +
601 NativeCall::instruction_size); // sethi; setlo; call; delay slot
602 } else {
603 assert(!UseInlineCaches, "expect vtable calls only if not using ICs");
604 int entry_offset = in_bytes(InstanceKlass::vtable_start_offset()) + vtable_index*vtableEntry::size_in_bytes();
605 int v_off = entry_offset + vtableEntry::method_offset_in_bytes();
606 int klass_load_size;
607 if (UseCompressedClassPointers) {
608 assert(Universe::heap() != NULL, "java heap should be initialized");
609 klass_load_size = MacroAssembler::instr_size_for_decode_klass_not_null() + 1*BytesPerInstWord;
610 } else {
611 klass_load_size = 1*BytesPerInstWord;
612 }
613 if (Assembler::is_simm13(v_off)) {
614 return klass_load_size +
615 (2*BytesPerInstWord + // ld_ptr, ld_ptr
616 NativeCall::instruction_size); // call; delay slot
617 } else {
618 return klass_load_size +
619 (4*BytesPerInstWord + // set_hi, set, ld_ptr, ld_ptr
620 NativeCall::instruction_size); // call; delay slot
621 }
622 }
623 }
624
625 int MachCallRuntimeNode::ret_addr_offset() {
626 #ifdef _LP64
627 if (MacroAssembler::is_far_target(entry_point())) {
628 return NativeFarCall::instruction_size;
629 } else {
630 return NativeCall::instruction_size;
631 }
632 #else
633 return NativeCall::instruction_size; // call; delay slot
634 #endif
635 }
636
637 // Indicate if the safepoint node needs the polling page as an input.
638 // Since Sparc does not have absolute addressing, it does.
639 bool SafePointNode::needs_polling_address_input() {
640 return true;
641 }
642
643 // emit an interrupt that is caught by the debugger (for debugging compiler)
644 void emit_break(CodeBuffer &cbuf) {
645 MacroAssembler _masm(&cbuf);
646 __ breakpoint_trap();
647 }
648
649 #ifndef PRODUCT
650 void MachBreakpointNode::format( PhaseRegAlloc *, outputStream *st ) const {
651 st->print("TA");
652 }
653 #endif
654
655 void MachBreakpointNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
656 emit_break(cbuf);
657 }
658
659 uint MachBreakpointNode::size(PhaseRegAlloc *ra_) const {
660 return MachNode::size(ra_);
661 }
662
663 // Traceable jump
664 void emit_jmpl(CodeBuffer &cbuf, int jump_target) {
665 MacroAssembler _masm(&cbuf);
666 Register rdest = reg_to_register_object(jump_target);
667 __ JMP(rdest, 0);
668 __ delayed()->nop();
669 }
670
671 // Traceable jump and set exception pc
672 void emit_jmpl_set_exception_pc(CodeBuffer &cbuf, int jump_target) {
673 MacroAssembler _masm(&cbuf);
674 Register rdest = reg_to_register_object(jump_target);
675 __ JMP(rdest, 0);
676 __ delayed()->add(O7, frame::pc_return_offset, Oissuing_pc );
677 }
678
679 void emit_nop(CodeBuffer &cbuf) {
680 MacroAssembler _masm(&cbuf);
681 __ nop();
682 }
683
684 void emit_illtrap(CodeBuffer &cbuf) {
685 MacroAssembler _masm(&cbuf);
686 __ illtrap(0);
687 }
688
689
690 intptr_t get_offset_from_base(const MachNode* n, const TypePtr* atype, int disp32) {
691 assert(n->rule() != loadUB_rule, "");
692
693 intptr_t offset = 0;
694 const TypePtr *adr_type = TYPE_PTR_SENTINAL; // Check for base==RegI, disp==immP
695 const Node* addr = n->get_base_and_disp(offset, adr_type);
696 assert(adr_type == (const TypePtr*)-1, "VerifyOops: no support for sparc operands with base==RegI, disp==immP");
697 assert(addr != NULL && addr != (Node*)-1, "invalid addr");
698 assert(addr->bottom_type()->isa_oopptr() == atype, "");
699 atype = atype->add_offset(offset);
700 assert(disp32 == offset, "wrong disp32");
701 return atype->_offset;
702 }
703
704
705 intptr_t get_offset_from_base_2(const MachNode* n, const TypePtr* atype, int disp32) {
706 assert(n->rule() != loadUB_rule, "");
707
708 intptr_t offset = 0;
709 Node* addr = n->in(2);
710 assert(addr->bottom_type()->isa_oopptr() == atype, "");
711 if (addr->is_Mach() && addr->as_Mach()->ideal_Opcode() == Op_AddP) {
712 Node* a = addr->in(2/*AddPNode::Address*/);
713 Node* o = addr->in(3/*AddPNode::Offset*/);
714 offset = o->is_Con() ? o->bottom_type()->is_intptr_t()->get_con() : Type::OffsetBot;
715 atype = a->bottom_type()->is_ptr()->add_offset(offset);
716 assert(atype->isa_oop_ptr(), "still an oop");
717 }
718 offset = atype->is_ptr()->_offset;
719 if (offset != Type::OffsetBot) offset += disp32;
720 return offset;
721 }
722
723 static inline jdouble replicate_immI(int con, int count, int width) {
724 // Load a constant replicated "count" times with width "width"
725 assert(count*width == 8 && width <= 4, "sanity");
726 int bit_width = width * 8;
727 jlong val = con;
728 val &= (((jlong) 1) << bit_width) - 1; // mask off sign bits
729 for (int i = 0; i < count - 1; i++) {
730 val |= (val << bit_width);
731 }
732 jdouble dval = *((jdouble*) &val); // coerce to double type
733 return dval;
734 }
735
736 static inline jdouble replicate_immF(float con) {
737 // Replicate float con 2 times and pack into vector.
738 int val = *((int*)&con);
739 jlong lval = val;
740 lval = (lval << 32) | (lval & 0xFFFFFFFFl);
741 jdouble dval = *((jdouble*) &lval); // coerce to double type
742 return dval;
743 }
744
745 // Standard Sparc opcode form2 field breakdown
746 static inline void emit2_19(CodeBuffer &cbuf, int f30, int f29, int f25, int f22, int f20, int f19, int f0 ) {
747 f0 &= (1<<19)-1; // Mask displacement to 19 bits
748 int op = (f30 << 30) |
749 (f29 << 29) |
750 (f25 << 25) |
751 (f22 << 22) |
752 (f20 << 20) |
753 (f19 << 19) |
754 (f0 << 0);
755 cbuf.insts()->emit_int32(op);
756 }
757
758 // Standard Sparc opcode form2 field breakdown
759 static inline void emit2_22(CodeBuffer &cbuf, int f30, int f25, int f22, int f0 ) {
760 f0 >>= 10; // Drop 10 bits
761 f0 &= (1<<22)-1; // Mask displacement to 22 bits
762 int op = (f30 << 30) |
763 (f25 << 25) |
764 (f22 << 22) |
765 (f0 << 0);
766 cbuf.insts()->emit_int32(op);
767 }
768
769 // Standard Sparc opcode form3 field breakdown
770 static inline void emit3(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int f5, int f0 ) {
771 int op = (f30 << 30) |
772 (f25 << 25) |
773 (f19 << 19) |
774 (f14 << 14) |
775 (f5 << 5) |
776 (f0 << 0);
777 cbuf.insts()->emit_int32(op);
778 }
779
780 // Standard Sparc opcode form3 field breakdown
781 static inline void emit3_simm13(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int simm13 ) {
782 simm13 &= (1<<13)-1; // Mask to 13 bits
783 int op = (f30 << 30) |
784 (f25 << 25) |
785 (f19 << 19) |
786 (f14 << 14) |
787 (1 << 13) | // bit to indicate immediate-mode
788 (simm13<<0);
789 cbuf.insts()->emit_int32(op);
790 }
791
792 static inline void emit3_simm10(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int simm10 ) {
793 simm10 &= (1<<10)-1; // Mask to 10 bits
794 emit3_simm13(cbuf,f30,f25,f19,f14,simm10);
795 }
796
797 #ifdef ASSERT
798 // Helper function for VerifyOops in emit_form3_mem_reg
799 void verify_oops_warning(const MachNode *n, int ideal_op, int mem_op) {
800 warning("VerifyOops encountered unexpected instruction:");
801 n->dump(2);
802 warning("Instruction has ideal_Opcode==Op_%s and op_ld==Op_%s \n", NodeClassNames[ideal_op], NodeClassNames[mem_op]);
803 }
804 #endif
805
806
807 void emit_form3_mem_reg(CodeBuffer &cbuf, PhaseRegAlloc* ra, const MachNode* n, int primary, int tertiary,
808 int src1_enc, int disp32, int src2_enc, int dst_enc) {
809
810 #ifdef ASSERT
811 // The following code implements the +VerifyOops feature.
812 // It verifies oop values which are loaded into or stored out of
813 // the current method activation. +VerifyOops complements techniques
814 // like ScavengeALot, because it eagerly inspects oops in transit,
815 // as they enter or leave the stack, as opposed to ScavengeALot,
816 // which inspects oops "at rest", in the stack or heap, at safepoints.
817 // For this reason, +VerifyOops can sometimes detect bugs very close
818 // to their point of creation. It can also serve as a cross-check
819 // on the validity of oop maps, when used toegether with ScavengeALot.
820
821 // It would be good to verify oops at other points, especially
822 // when an oop is used as a base pointer for a load or store.
823 // This is presently difficult, because it is hard to know when
824 // a base address is biased or not. (If we had such information,
825 // it would be easy and useful to make a two-argument version of
826 // verify_oop which unbiases the base, and performs verification.)
827
828 assert((uint)tertiary == 0xFFFFFFFF || tertiary == REGP_OP, "valid tertiary");
829 bool is_verified_oop_base = false;
830 bool is_verified_oop_load = false;
831 bool is_verified_oop_store = false;
832 int tmp_enc = -1;
833 if (VerifyOops && src1_enc != R_SP_enc) {
834 // classify the op, mainly for an assert check
835 int st_op = 0, ld_op = 0;
836 switch (primary) {
837 case Assembler::stb_op3: st_op = Op_StoreB; break;
838 case Assembler::sth_op3: st_op = Op_StoreC; break;
839 case Assembler::stx_op3: // may become StoreP or stay StoreI or StoreD0
840 case Assembler::stw_op3: st_op = Op_StoreI; break;
841 case Assembler::std_op3: st_op = Op_StoreL; break;
842 case Assembler::stf_op3: st_op = Op_StoreF; break;
843 case Assembler::stdf_op3: st_op = Op_StoreD; break;
844
845 case Assembler::ldsb_op3: ld_op = Op_LoadB; break;
846 case Assembler::ldub_op3: ld_op = Op_LoadUB; break;
847 case Assembler::lduh_op3: ld_op = Op_LoadUS; break;
848 case Assembler::ldsh_op3: ld_op = Op_LoadS; break;
849 case Assembler::ldx_op3: // may become LoadP or stay LoadI
850 case Assembler::ldsw_op3: // may become LoadP or stay LoadI
851 case Assembler::lduw_op3: ld_op = Op_LoadI; break;
852 case Assembler::ldd_op3: ld_op = Op_LoadL; break;
853 case Assembler::ldf_op3: ld_op = Op_LoadF; break;
854 case Assembler::lddf_op3: ld_op = Op_LoadD; break;
855 case Assembler::prefetch_op3: ld_op = Op_LoadI; break;
856
857 default: ShouldNotReachHere();
858 }
859 if (tertiary == REGP_OP) {
860 if (st_op == Op_StoreI) st_op = Op_StoreP;
861 else if (ld_op == Op_LoadI) ld_op = Op_LoadP;
862 else ShouldNotReachHere();
863 if (st_op) {
864 // a store
865 // inputs are (0:control, 1:memory, 2:address, 3:value)
866 Node* n2 = n->in(3);
867 if (n2 != NULL) {
868 const Type* t = n2->bottom_type();
869 is_verified_oop_store = t->isa_oop_ptr() ? (t->is_ptr()->_offset==0) : false;
870 }
871 } else {
872 // a load
873 const Type* t = n->bottom_type();
874 is_verified_oop_load = t->isa_oop_ptr() ? (t->is_ptr()->_offset==0) : false;
875 }
876 }
877
878 if (ld_op) {
879 // a Load
880 // inputs are (0:control, 1:memory, 2:address)
881 if (!(n->ideal_Opcode()==ld_op) && // Following are special cases
882 !(n->ideal_Opcode()==Op_LoadPLocked && ld_op==Op_LoadP) &&
883 !(n->ideal_Opcode()==Op_LoadI && ld_op==Op_LoadF) &&
884 !(n->ideal_Opcode()==Op_LoadF && ld_op==Op_LoadI) &&
885 !(n->ideal_Opcode()==Op_LoadRange && ld_op==Op_LoadI) &&
886 !(n->ideal_Opcode()==Op_LoadKlass && ld_op==Op_LoadP) &&
887 !(n->ideal_Opcode()==Op_LoadL && ld_op==Op_LoadI) &&
888 !(n->ideal_Opcode()==Op_LoadL_unaligned && ld_op==Op_LoadI) &&
889 !(n->ideal_Opcode()==Op_LoadD_unaligned && ld_op==Op_LoadF) &&
890 !(n->ideal_Opcode()==Op_ConvI2F && ld_op==Op_LoadF) &&
891 !(n->ideal_Opcode()==Op_ConvI2D && ld_op==Op_LoadF) &&
892 !(n->ideal_Opcode()==Op_PrefetchAllocation && ld_op==Op_LoadI) &&
893 !(n->ideal_Opcode()==Op_LoadVector && ld_op==Op_LoadD) &&
894 !(n->rule() == loadUB_rule)) {
895 verify_oops_warning(n, n->ideal_Opcode(), ld_op);
896 }
897 } else if (st_op) {
898 // a Store
899 // inputs are (0:control, 1:memory, 2:address, 3:value)
900 if (!(n->ideal_Opcode()==st_op) && // Following are special cases
901 !(n->ideal_Opcode()==Op_StoreCM && st_op==Op_StoreB) &&
902 !(n->ideal_Opcode()==Op_StoreI && st_op==Op_StoreF) &&
903 !(n->ideal_Opcode()==Op_StoreF && st_op==Op_StoreI) &&
904 !(n->ideal_Opcode()==Op_StoreL && st_op==Op_StoreI) &&
905 !(n->ideal_Opcode()==Op_StoreVector && st_op==Op_StoreD) &&
906 !(n->ideal_Opcode()==Op_StoreD && st_op==Op_StoreI && n->rule() == storeD0_rule)) {
907 verify_oops_warning(n, n->ideal_Opcode(), st_op);
908 }
909 }
910
911 if (src2_enc == R_G0_enc && n->rule() != loadUB_rule && n->ideal_Opcode() != Op_StoreCM ) {
912 Node* addr = n->in(2);
913 if (!(addr->is_Mach() && addr->as_Mach()->ideal_Opcode() == Op_AddP)) {
914 const TypeOopPtr* atype = addr->bottom_type()->isa_instptr(); // %%% oopptr?
915 if (atype != NULL) {
916 intptr_t offset = get_offset_from_base(n, atype, disp32);
917 intptr_t offset_2 = get_offset_from_base_2(n, atype, disp32);
918 if (offset != offset_2) {
919 get_offset_from_base(n, atype, disp32);
920 get_offset_from_base_2(n, atype, disp32);
921 }
922 assert(offset == offset_2, "different offsets");
923 if (offset == disp32) {
924 // we now know that src1 is a true oop pointer
925 is_verified_oop_base = true;
926 if (ld_op && src1_enc == dst_enc && ld_op != Op_LoadF && ld_op != Op_LoadD) {
927 if( primary == Assembler::ldd_op3 ) {
928 is_verified_oop_base = false; // Cannot 'ldd' into O7
929 } else {
930 tmp_enc = dst_enc;
931 dst_enc = R_O7_enc; // Load into O7; preserve source oop
932 assert(src1_enc != dst_enc, "");
933 }
934 }
935 }
936 if (st_op && (( offset == oopDesc::klass_offset_in_bytes())
937 || offset == oopDesc::mark_offset_in_bytes())) {
938 // loading the mark should not be allowed either, but
939 // we don't check this since it conflicts with InlineObjectHash
940 // usage of LoadINode to get the mark. We could keep the
941 // check if we create a new LoadMarkNode
942 // but do not verify the object before its header is initialized
943 ShouldNotReachHere();
944 }
945 }
946 }
947 }
948 }
949 #endif
950
951 uint instr;
952 instr = (Assembler::ldst_op << 30)
953 | (dst_enc << 25)
954 | (primary << 19)
955 | (src1_enc << 14);
956
957 uint index = src2_enc;
958 int disp = disp32;
959
960 if (src1_enc == R_SP_enc || src1_enc == R_FP_enc) {
961 disp += STACK_BIAS;
962 // Quick fix for JDK-8029668: check that stack offset fits, bailout if not
963 if (!Assembler::is_simm13(disp)) {
964 ra->C->record_method_not_compilable("unable to handle large constant offsets");
965 return;
966 }
967 }
968
969 // We should have a compiler bailout here rather than a guarantee.
970 // Better yet would be some mechanism to handle variable-size matches correctly.
971 guarantee(Assembler::is_simm13(disp), "Do not match large constant offsets" );
972
973 if( disp == 0 ) {
974 // use reg-reg form
975 // bit 13 is already zero
976 instr |= index;
977 } else {
978 // use reg-imm form
979 instr |= 0x00002000; // set bit 13 to one
980 instr |= disp & 0x1FFF;
981 }
982
983 cbuf.insts()->emit_int32(instr);
984
985 #ifdef ASSERT
986 {
987 MacroAssembler _masm(&cbuf);
988 if (is_verified_oop_base) {
989 __ verify_oop(reg_to_register_object(src1_enc));
990 }
991 if (is_verified_oop_store) {
992 __ verify_oop(reg_to_register_object(dst_enc));
993 }
994 if (tmp_enc != -1) {
995 __ mov(O7, reg_to_register_object(tmp_enc));
996 }
997 if (is_verified_oop_load) {
998 __ verify_oop(reg_to_register_object(dst_enc));
999 }
1000 }
1001 #endif
1002 }
1003
1004 void emit_call_reloc(CodeBuffer &cbuf, intptr_t entry_point, RelocationHolder const& rspec, bool preserve_g2 = false) {
1005 // The method which records debug information at every safepoint
1006 // expects the call to be the first instruction in the snippet as
1007 // it creates a PcDesc structure which tracks the offset of a call
1008 // from the start of the codeBlob. This offset is computed as
1009 // code_end() - code_begin() of the code which has been emitted
1010 // so far.
1011 // In this particular case we have skirted around the problem by
1012 // putting the "mov" instruction in the delay slot but the problem
1013 // may bite us again at some other point and a cleaner/generic
1014 // solution using relocations would be needed.
1015 MacroAssembler _masm(&cbuf);
1016 __ set_inst_mark();
1017
1018 // We flush the current window just so that there is a valid stack copy
1019 // the fact that the current window becomes active again instantly is
1020 // not a problem there is nothing live in it.
1021
1022 #ifdef ASSERT
1023 int startpos = __ offset();
1024 #endif /* ASSERT */
1025
1026 __ call((address)entry_point, rspec);
1027
1028 if (preserve_g2) __ delayed()->mov(G2, L7);
1029 else __ delayed()->nop();
1030
1031 if (preserve_g2) __ mov(L7, G2);
1032
1033 #ifdef ASSERT
1034 if (preserve_g2 && (VerifyCompiledCode || VerifyOops)) {
1035 #ifdef _LP64
1036 // Trash argument dump slots.
1037 __ set(0xb0b8ac0db0b8ac0d, G1);
1038 __ mov(G1, G5);
1039 __ stx(G1, SP, STACK_BIAS + 0x80);
1040 __ stx(G1, SP, STACK_BIAS + 0x88);
1041 __ stx(G1, SP, STACK_BIAS + 0x90);
1042 __ stx(G1, SP, STACK_BIAS + 0x98);
1043 __ stx(G1, SP, STACK_BIAS + 0xA0);
1044 __ stx(G1, SP, STACK_BIAS + 0xA8);
1045 #else // _LP64
1046 // this is also a native call, so smash the first 7 stack locations,
1047 // and the various registers
1048
1049 // Note: [SP+0x40] is sp[callee_aggregate_return_pointer_sp_offset],
1050 // while [SP+0x44..0x58] are the argument dump slots.
1051 __ set((intptr_t)0xbaadf00d, G1);
1052 __ mov(G1, G5);
1053 __ sllx(G1, 32, G1);
1054 __ or3(G1, G5, G1);
1055 __ mov(G1, G5);
1056 __ stx(G1, SP, 0x40);
1057 __ stx(G1, SP, 0x48);
1058 __ stx(G1, SP, 0x50);
1059 __ stw(G1, SP, 0x58); // Do not trash [SP+0x5C] which is a usable spill slot
1060 #endif // _LP64
1061 }
1062 #endif /*ASSERT*/
1063 }
1064
1065 //=============================================================================
1066 // REQUIRED FUNCTIONALITY for encoding
1067 void emit_lo(CodeBuffer &cbuf, int val) { }
1068 void emit_hi(CodeBuffer &cbuf, int val) { }
1069
1070
1071 //=============================================================================
1072 const RegMask& MachConstantBaseNode::_out_RegMask = PTR_REG_mask();
1073
1074 int Compile::ConstantTable::calculate_table_base_offset() const {
1075 if (UseRDPCForConstantTableBase) {
1076 // The table base offset might be less but then it fits into
1077 // simm13 anyway and we are good (cf. MachConstantBaseNode::emit).
1078 return Assembler::min_simm13();
1079 } else {
1080 int offset = -(size() / 2);
1081 if (!Assembler::is_simm13(offset)) {
1082 offset = Assembler::min_simm13();
1083 }
1084 return offset;
1085 }
1086 }
1087
1088 bool MachConstantBaseNode::requires_postalloc_expand() const { return false; }
1089 void MachConstantBaseNode::postalloc_expand(GrowableArray <Node *> *nodes, PhaseRegAlloc *ra_) {
1090 ShouldNotReachHere();
1091 }
1092
1093 void MachConstantBaseNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
1094 Compile* C = ra_->C;
1095 Compile::ConstantTable& constant_table = C->constant_table();
1096 MacroAssembler _masm(&cbuf);
1097
1098 Register r = as_Register(ra_->get_encode(this));
1099 CodeSection* consts_section = __ code()->consts();
1100 int consts_size = consts_section->align_at_start(consts_section->size());
1101 assert(constant_table.size() == consts_size, "must be: %d == %d", constant_table.size(), consts_size);
1102
1103 if (UseRDPCForConstantTableBase) {
1104 // For the following RDPC logic to work correctly the consts
1105 // section must be allocated right before the insts section. This
1106 // assert checks for that. The layout and the SECT_* constants
1107 // are defined in src/share/vm/asm/codeBuffer.hpp.
1108 assert(CodeBuffer::SECT_CONSTS + 1 == CodeBuffer::SECT_INSTS, "must be");
1109 int insts_offset = __ offset();
1110
1111 // Layout:
1112 //
1113 // |----------- consts section ------------|----------- insts section -----------...
1114 // |------ constant table -----|- padding -|------------------x----
1115 // \ current PC (RDPC instruction)
1116 // |<------------- consts_size ----------->|<- insts_offset ->|
1117 // \ table base
1118 // The table base offset is later added to the load displacement
1119 // so it has to be negative.
1120 int table_base_offset = -(consts_size + insts_offset);
1121 int disp;
1122
1123 // If the displacement from the current PC to the constant table
1124 // base fits into simm13 we set the constant table base to the
1125 // current PC.
1126 if (Assembler::is_simm13(table_base_offset)) {
1127 constant_table.set_table_base_offset(table_base_offset);
1128 disp = 0;
1129 } else {
1130 // Otherwise we set the constant table base offset to the
1131 // maximum negative displacement of load instructions to keep
1132 // the disp as small as possible:
1133 //
1134 // |<------------- consts_size ----------->|<- insts_offset ->|
1135 // |<--------- min_simm13 --------->|<-------- disp --------->|
1136 // \ table base
1137 table_base_offset = Assembler::min_simm13();
1138 constant_table.set_table_base_offset(table_base_offset);
1139 disp = (consts_size + insts_offset) + table_base_offset;
1140 }
1141
1142 __ rdpc(r);
1143
1144 if (disp != 0) {
1145 assert(r != O7, "need temporary");
1146 __ sub(r, __ ensure_simm13_or_reg(disp, O7), r);
1147 }
1148 }
1149 else {
1150 // Materialize the constant table base.
1151 address baseaddr = consts_section->start() + -(constant_table.table_base_offset());
1152 RelocationHolder rspec = internal_word_Relocation::spec(baseaddr);
1153 AddressLiteral base(baseaddr, rspec);
1154 __ set(base, r);
1155 }
1156 }
1157
1158 uint MachConstantBaseNode::size(PhaseRegAlloc*) const {
1159 if (UseRDPCForConstantTableBase) {
1160 // This is really the worst case but generally it's only 1 instruction.
1161 return (1 /*rdpc*/ + 1 /*sub*/ + MacroAssembler::worst_case_insts_for_set()) * BytesPerInstWord;
1162 } else {
1163 return MacroAssembler::worst_case_insts_for_set() * BytesPerInstWord;
1164 }
1165 }
1166
1167 #ifndef PRODUCT
1168 void MachConstantBaseNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
1169 char reg[128];
1170 ra_->dump_register(this, reg);
1171 if (UseRDPCForConstantTableBase) {
1172 st->print("RDPC %s\t! constant table base", reg);
1173 } else {
1174 st->print("SET &constanttable,%s\t! constant table base", reg);
1175 }
1176 }
1177 #endif
1178
1179
1180 //=============================================================================
1181
1182 #ifndef PRODUCT
1183 void MachPrologNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
1184 Compile* C = ra_->C;
1185
1186 for (int i = 0; i < OptoPrologueNops; i++) {
1187 st->print_cr("NOP"); st->print("\t");
1188 }
1189
1190 if( VerifyThread ) {
1191 st->print_cr("Verify_Thread"); st->print("\t");
1192 }
1193
1194 size_t framesize = C->frame_size_in_bytes();
1195 int bangsize = C->bang_size_in_bytes();
1196
1197 // Calls to C2R adapters often do not accept exceptional returns.
1198 // We require that their callers must bang for them. But be careful, because
1199 // some VM calls (such as call site linkage) can use several kilobytes of
1200 // stack. But the stack safety zone should account for that.
1201 // See bugs 4446381, 4468289, 4497237.
1202 if (C->need_stack_bang(bangsize)) {
1203 st->print_cr("! stack bang (%d bytes)", bangsize); st->print("\t");
1204 }
1205
1206 if (Assembler::is_simm13(-framesize)) {
1207 st->print ("SAVE R_SP,-" SIZE_FORMAT ",R_SP",framesize);
1208 } else {
1209 st->print_cr("SETHI R_SP,hi%%(-" SIZE_FORMAT "),R_G3",framesize); st->print("\t");
1210 st->print_cr("ADD R_G3,lo%%(-" SIZE_FORMAT "),R_G3",framesize); st->print("\t");
1211 st->print ("SAVE R_SP,R_G3,R_SP");
1212 }
1213
1214 }
1215 #endif
1216
1217 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1218 Compile* C = ra_->C;
1219 MacroAssembler _masm(&cbuf);
1220
1221 for (int i = 0; i < OptoPrologueNops; i++) {
1222 __ nop();
1223 }
1224
1225 __ verify_thread();
1226
1227 size_t framesize = C->frame_size_in_bytes();
1228 assert(framesize >= 16*wordSize, "must have room for reg. save area");
1229 assert(framesize%(2*wordSize) == 0, "must preserve 2*wordSize alignment");
1230 int bangsize = C->bang_size_in_bytes();
1231
1232 // Calls to C2R adapters often do not accept exceptional returns.
1233 // We require that their callers must bang for them. But be careful, because
1234 // some VM calls (such as call site linkage) can use several kilobytes of
1235 // stack. But the stack safety zone should account for that.
1236 // See bugs 4446381, 4468289, 4497237.
1237 if (C->need_stack_bang(bangsize)) {
1238 __ generate_stack_overflow_check(bangsize);
1239 }
1240
1241 if (Assembler::is_simm13(-framesize)) {
1242 __ save(SP, -framesize, SP);
1243 } else {
1244 __ sethi(-framesize & ~0x3ff, G3);
1245 __ add(G3, -framesize & 0x3ff, G3);
1246 __ save(SP, G3, SP);
1247 }
1248 C->set_frame_complete( __ offset() );
1249
1250 if (!UseRDPCForConstantTableBase && C->has_mach_constant_base_node()) {
1251 // NOTE: We set the table base offset here because users might be
1252 // emitted before MachConstantBaseNode.
1253 Compile::ConstantTable& constant_table = C->constant_table();
1254 constant_table.set_table_base_offset(constant_table.calculate_table_base_offset());
1255 }
1256 }
1257
1258 uint MachPrologNode::size(PhaseRegAlloc *ra_) const {
1259 return MachNode::size(ra_);
1260 }
1261
1262 int MachPrologNode::reloc() const {
1263 return 10; // a large enough number
1264 }
1265
1266 //=============================================================================
1267 #ifndef PRODUCT
1268 void MachEpilogNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
1269 Compile* C = ra_->C;
1270
1271 if(do_polling() && ra_->C->is_method_compilation()) {
1272 st->print("SETHI #PollAddr,L0\t! Load Polling address\n\t");
1273 #ifdef _LP64
1274 st->print("LDX [L0],G0\t!Poll for Safepointing\n\t");
1275 #else
1276 st->print("LDUW [L0],G0\t!Poll for Safepointing\n\t");
1277 #endif
1278 }
1279
1280 if(do_polling()) {
1281 if (UseCBCond && !ra_->C->is_method_compilation()) {
1282 st->print("NOP\n\t");
1283 }
1284 st->print("RET\n\t");
1285 }
1286
1287 st->print("RESTORE");
1288 }
1289 #endif
1290
1291 void MachEpilogNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1292 MacroAssembler _masm(&cbuf);
1293 Compile* C = ra_->C;
1294
1295 __ verify_thread();
1296
1297 if (StackReservedPages > 0 && C->has_reserved_stack_access()) {
1298 __ reserved_stack_check();
1299 }
1300
1301 // If this does safepoint polling, then do it here
1302 if(do_polling() && ra_->C->is_method_compilation()) {
1303 AddressLiteral polling_page(os::get_polling_page());
1304 __ sethi(polling_page, L0);
1305 __ relocate(relocInfo::poll_return_type);
1306 __ ld_ptr(L0, 0, G0);
1307 }
1308
1309 // If this is a return, then stuff the restore in the delay slot
1310 if(do_polling()) {
1311 if (UseCBCond && !ra_->C->is_method_compilation()) {
1312 // Insert extra padding for the case when the epilogue is preceded by
1313 // a cbcond jump, which can't be followed by a CTI instruction
1314 __ nop();
1315 }
1316 __ ret();
1317 __ delayed()->restore();
1318 } else {
1319 __ restore();
1320 }
1321 }
1322
1323 uint MachEpilogNode::size(PhaseRegAlloc *ra_) const {
1324 return MachNode::size(ra_);
1325 }
1326
1327 int MachEpilogNode::reloc() const {
1328 return 16; // a large enough number
1329 }
1330
1331 const Pipeline * MachEpilogNode::pipeline() const {
1332 return MachNode::pipeline_class();
1333 }
1334
1335 int MachEpilogNode::safepoint_offset() const {
1336 assert( do_polling(), "no return for this epilog node");
1337 return MacroAssembler::insts_for_sethi(os::get_polling_page()) * BytesPerInstWord;
1338 }
1339
1340 //=============================================================================
1341
1342 // Figure out which register class each belongs in: rc_int, rc_float, rc_stack
1343 enum RC { rc_bad, rc_int, rc_float, rc_stack };
1344 static enum RC rc_class( OptoReg::Name reg ) {
1345 if( !OptoReg::is_valid(reg) ) return rc_bad;
1346 if (OptoReg::is_stack(reg)) return rc_stack;
1347 VMReg r = OptoReg::as_VMReg(reg);
1348 if (r->is_Register()) return rc_int;
1349 assert(r->is_FloatRegister(), "must be");
1350 return rc_float;
1351 }
1352
1353 static int impl_helper(const MachNode* mach, CodeBuffer* cbuf, PhaseRegAlloc* ra, bool do_size, bool is_load, int offset, int reg, int opcode, const char *op_str, int size, outputStream* st ) {
1354 if (cbuf) {
1355 emit_form3_mem_reg(*cbuf, ra, mach, opcode, -1, R_SP_enc, offset, 0, Matcher::_regEncode[reg]);
1356 }
1357 #ifndef PRODUCT
1358 else if (!do_size) {
1359 if (size != 0) st->print("\n\t");
1360 if (is_load) st->print("%s [R_SP + #%d],R_%s\t! spill",op_str,offset,OptoReg::regname(reg));
1361 else st->print("%s R_%s,[R_SP + #%d]\t! spill",op_str,OptoReg::regname(reg),offset);
1362 }
1363 #endif
1364 return size+4;
1365 }
1366
1367 static int impl_mov_helper( CodeBuffer *cbuf, bool do_size, int src, int dst, int op1, int op2, const char *op_str, int size, outputStream* st ) {
1368 if( cbuf ) emit3( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst], op1, 0, op2, Matcher::_regEncode[src] );
1369 #ifndef PRODUCT
1370 else if( !do_size ) {
1371 if( size != 0 ) st->print("\n\t");
1372 st->print("%s R_%s,R_%s\t! spill",op_str,OptoReg::regname(src),OptoReg::regname(dst));
1373 }
1374 #endif
1375 return size+4;
1376 }
1377
1378 uint MachSpillCopyNode::implementation( CodeBuffer *cbuf,
1379 PhaseRegAlloc *ra_,
1380 bool do_size,
1381 outputStream* st ) const {
1382 // Get registers to move
1383 OptoReg::Name src_second = ra_->get_reg_second(in(1));
1384 OptoReg::Name src_first = ra_->get_reg_first(in(1));
1385 OptoReg::Name dst_second = ra_->get_reg_second(this );
1386 OptoReg::Name dst_first = ra_->get_reg_first(this );
1387
1388 enum RC src_second_rc = rc_class(src_second);
1389 enum RC src_first_rc = rc_class(src_first);
1390 enum RC dst_second_rc = rc_class(dst_second);
1391 enum RC dst_first_rc = rc_class(dst_first);
1392
1393 assert( OptoReg::is_valid(src_first) && OptoReg::is_valid(dst_first), "must move at least 1 register" );
1394
1395 // Generate spill code!
1396 int size = 0;
1397
1398 if( src_first == dst_first && src_second == dst_second )
1399 return size; // Self copy, no move
1400
1401 // --------------------------------------
1402 // Check for mem-mem move. Load into unused float registers and fall into
1403 // the float-store case.
1404 if( src_first_rc == rc_stack && dst_first_rc == rc_stack ) {
1405 int offset = ra_->reg2offset(src_first);
1406 // Further check for aligned-adjacent pair, so we can use a double load
1407 if( (src_first&1)==0 && src_first+1 == src_second ) {
1408 src_second = OptoReg::Name(R_F31_num);
1409 src_second_rc = rc_float;
1410 size = impl_helper(this,cbuf,ra_,do_size,true,offset,R_F30_num,Assembler::lddf_op3,"LDDF",size, st);
1411 } else {
1412 size = impl_helper(this,cbuf,ra_,do_size,true,offset,R_F30_num,Assembler::ldf_op3 ,"LDF ",size, st);
1413 }
1414 src_first = OptoReg::Name(R_F30_num);
1415 src_first_rc = rc_float;
1416 }
1417
1418 if( src_second_rc == rc_stack && dst_second_rc == rc_stack ) {
1419 int offset = ra_->reg2offset(src_second);
1420 size = impl_helper(this,cbuf,ra_,do_size,true,offset,R_F31_num,Assembler::ldf_op3,"LDF ",size, st);
1421 src_second = OptoReg::Name(R_F31_num);
1422 src_second_rc = rc_float;
1423 }
1424
1425 // --------------------------------------
1426 // Check for float->int copy; requires a trip through memory
1427 if (src_first_rc == rc_float && dst_first_rc == rc_int && UseVIS < 3) {
1428 int offset = frame::register_save_words*wordSize;
1429 if (cbuf) {
1430 emit3_simm13( *cbuf, Assembler::arith_op, R_SP_enc, Assembler::sub_op3, R_SP_enc, 16 );
1431 impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stf_op3 ,"STF ",size, st);
1432 impl_helper(this,cbuf,ra_,do_size,true ,offset,dst_first,Assembler::lduw_op3,"LDUW",size, st);
1433 emit3_simm13( *cbuf, Assembler::arith_op, R_SP_enc, Assembler::add_op3, R_SP_enc, 16 );
1434 }
1435 #ifndef PRODUCT
1436 else if (!do_size) {
1437 if (size != 0) st->print("\n\t");
1438 st->print( "SUB R_SP,16,R_SP\n");
1439 impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stf_op3 ,"STF ",size, st);
1440 impl_helper(this,cbuf,ra_,do_size,true ,offset,dst_first,Assembler::lduw_op3,"LDUW",size, st);
1441 st->print("\tADD R_SP,16,R_SP\n");
1442 }
1443 #endif
1444 size += 16;
1445 }
1446
1447 // Check for float->int copy on T4
1448 if (src_first_rc == rc_float && dst_first_rc == rc_int && UseVIS >= 3) {
1449 // Further check for aligned-adjacent pair, so we can use a double move
1450 if ((src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second)
1451 return impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::mftoi_op3,Assembler::mdtox_opf,"MOVDTOX",size, st);
1452 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::mftoi_op3,Assembler::mstouw_opf,"MOVSTOUW",size, st);
1453 }
1454 // Check for int->float copy on T4
1455 if (src_first_rc == rc_int && dst_first_rc == rc_float && UseVIS >= 3) {
1456 // Further check for aligned-adjacent pair, so we can use a double move
1457 if ((src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second)
1458 return impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::mftoi_op3,Assembler::mxtod_opf,"MOVXTOD",size, st);
1459 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::mftoi_op3,Assembler::mwtos_opf,"MOVWTOS",size, st);
1460 }
1461
1462 // --------------------------------------
1463 // In the 32-bit 1-reg-longs build ONLY, I see mis-aligned long destinations.
1464 // In such cases, I have to do the big-endian swap. For aligned targets, the
1465 // hardware does the flop for me. Doubles are always aligned, so no problem
1466 // there. Misaligned sources only come from native-long-returns (handled
1467 // special below).
1468 #ifndef _LP64
1469 if( src_first_rc == rc_int && // source is already big-endian
1470 src_second_rc != rc_bad && // 64-bit move
1471 ((dst_first&1)!=0 || dst_second != dst_first+1) ) { // misaligned dst
1472 assert( (src_first&1)==0 && src_second == src_first+1, "source must be aligned" );
1473 // Do the big-endian flop.
1474 OptoReg::Name tmp = dst_first ; dst_first = dst_second ; dst_second = tmp ;
1475 enum RC tmp_rc = dst_first_rc; dst_first_rc = dst_second_rc; dst_second_rc = tmp_rc;
1476 }
1477 #endif
1478
1479 // --------------------------------------
1480 // Check for integer reg-reg copy
1481 if( src_first_rc == rc_int && dst_first_rc == rc_int ) {
1482 #ifndef _LP64
1483 if( src_first == R_O0_num && src_second == R_O1_num ) { // Check for the evil O0/O1 native long-return case
1484 // Note: The _first and _second suffixes refer to the addresses of the the 2 halves of the 64-bit value
1485 // as stored in memory. On a big-endian machine like SPARC, this means that the _second
1486 // operand contains the least significant word of the 64-bit value and vice versa.
1487 OptoReg::Name tmp = OptoReg::Name(R_O7_num);
1488 assert( (dst_first&1)==0 && dst_second == dst_first+1, "return a native O0/O1 long to an aligned-adjacent 64-bit reg" );
1489 // Shift O0 left in-place, zero-extend O1, then OR them into the dst
1490 if( cbuf ) {
1491 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[tmp], Assembler::sllx_op3, Matcher::_regEncode[src_first], 0x1020 );
1492 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[src_second], Assembler::srl_op3, Matcher::_regEncode[src_second], 0x0000 );
1493 emit3 ( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_first], Assembler:: or_op3, Matcher::_regEncode[tmp], 0, Matcher::_regEncode[src_second] );
1494 #ifndef PRODUCT
1495 } else if( !do_size ) {
1496 if( size != 0 ) st->print("\n\t");
1497 st->print("SLLX R_%s,32,R_%s\t! Move O0-first to O7-high\n\t", OptoReg::regname(src_first), OptoReg::regname(tmp));
1498 st->print("SRL R_%s, 0,R_%s\t! Zero-extend O1\n\t", OptoReg::regname(src_second), OptoReg::regname(src_second));
1499 st->print("OR R_%s,R_%s,R_%s\t! spill",OptoReg::regname(tmp), OptoReg::regname(src_second), OptoReg::regname(dst_first));
1500 #endif
1501 }
1502 return size+12;
1503 }
1504 else if( dst_first == R_I0_num && dst_second == R_I1_num ) {
1505 // returning a long value in I0/I1
1506 // a SpillCopy must be able to target a return instruction's reg_class
1507 // Note: The _first and _second suffixes refer to the addresses of the the 2 halves of the 64-bit value
1508 // as stored in memory. On a big-endian machine like SPARC, this means that the _second
1509 // operand contains the least significant word of the 64-bit value and vice versa.
1510 OptoReg::Name tdest = dst_first;
1511
1512 if (src_first == dst_first) {
1513 tdest = OptoReg::Name(R_O7_num);
1514 size += 4;
1515 }
1516
1517 if( cbuf ) {
1518 assert( (src_first&1) == 0 && (src_first+1) == src_second, "return value was in an aligned-adjacent 64-bit reg");
1519 // Shift value in upper 32-bits of src to lower 32-bits of I0; move lower 32-bits to I1
1520 // ShrL_reg_imm6
1521 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[tdest], Assembler::srlx_op3, Matcher::_regEncode[src_second], 32 | 0x1000 );
1522 // ShrR_reg_imm6 src, 0, dst
1523 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_second], Assembler::srl_op3, Matcher::_regEncode[src_first], 0x0000 );
1524 if (tdest != dst_first) {
1525 emit3 ( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_first], Assembler::or_op3, 0/*G0*/, 0/*op2*/, Matcher::_regEncode[tdest] );
1526 }
1527 }
1528 #ifndef PRODUCT
1529 else if( !do_size ) {
1530 if( size != 0 ) st->print("\n\t"); // %%%%% !!!!!
1531 st->print("SRLX R_%s,32,R_%s\t! Extract MSW\n\t",OptoReg::regname(src_second),OptoReg::regname(tdest));
1532 st->print("SRL R_%s, 0,R_%s\t! Extract LSW\n\t",OptoReg::regname(src_first),OptoReg::regname(dst_second));
1533 if (tdest != dst_first) {
1534 st->print("MOV R_%s,R_%s\t! spill\n\t", OptoReg::regname(tdest), OptoReg::regname(dst_first));
1535 }
1536 }
1537 #endif // PRODUCT
1538 return size+8;
1539 }
1540 #endif // !_LP64
1541 // Else normal reg-reg copy
1542 assert( src_second != dst_first, "smashed second before evacuating it" );
1543 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::or_op3,0,"MOV ",size, st);
1544 assert( (src_first&1) == 0 && (dst_first&1) == 0, "never move second-halves of int registers" );
1545 // This moves an aligned adjacent pair.
1546 // See if we are done.
1547 if( src_first+1 == src_second && dst_first+1 == dst_second )
1548 return size;
1549 }
1550
1551 // Check for integer store
1552 if( src_first_rc == rc_int && dst_first_rc == rc_stack ) {
1553 int offset = ra_->reg2offset(dst_first);
1554 // Further check for aligned-adjacent pair, so we can use a double store
1555 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second )
1556 return impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stx_op3,"STX ",size, st);
1557 size = impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stw_op3,"STW ",size, st);
1558 }
1559
1560 // Check for integer load
1561 if( dst_first_rc == rc_int && src_first_rc == rc_stack ) {
1562 int offset = ra_->reg2offset(src_first);
1563 // Further check for aligned-adjacent pair, so we can use a double load
1564 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second )
1565 return impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::ldx_op3 ,"LDX ",size, st);
1566 size = impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::lduw_op3,"LDUW",size, st);
1567 }
1568
1569 // Check for float reg-reg copy
1570 if( src_first_rc == rc_float && dst_first_rc == rc_float ) {
1571 // Further check for aligned-adjacent pair, so we can use a double move
1572 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second )
1573 return impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::fpop1_op3,Assembler::fmovd_opf,"FMOVD",size, st);
1574 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::fpop1_op3,Assembler::fmovs_opf,"FMOVS",size, st);
1575 }
1576
1577 // Check for float store
1578 if( src_first_rc == rc_float && dst_first_rc == rc_stack ) {
1579 int offset = ra_->reg2offset(dst_first);
1580 // Further check for aligned-adjacent pair, so we can use a double store
1581 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second )
1582 return impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stdf_op3,"STDF",size, st);
1583 size = impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stf_op3 ,"STF ",size, st);
1584 }
1585
1586 // Check for float load
1587 if( dst_first_rc == rc_float && src_first_rc == rc_stack ) {
1588 int offset = ra_->reg2offset(src_first);
1589 // Further check for aligned-adjacent pair, so we can use a double load
1590 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second )
1591 return impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::lddf_op3,"LDDF",size, st);
1592 size = impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::ldf_op3 ,"LDF ",size, st);
1593 }
1594
1595 // --------------------------------------------------------------------
1596 // Check for hi bits still needing moving. Only happens for misaligned
1597 // arguments to native calls.
1598 if( src_second == dst_second )
1599 return size; // Self copy; no move
1600 assert( src_second_rc != rc_bad && dst_second_rc != rc_bad, "src_second & dst_second cannot be Bad" );
1601
1602 #ifndef _LP64
1603 // In the LP64 build, all registers can be moved as aligned/adjacent
1604 // pairs, so there's never any need to move the high bits separately.
1605 // The 32-bit builds have to deal with the 32-bit ABI which can force
1606 // all sorts of silly alignment problems.
1607
1608 // Check for integer reg-reg copy. Hi bits are stuck up in the top
1609 // 32-bits of a 64-bit register, but are needed in low bits of another
1610 // register (else it's a hi-bits-to-hi-bits copy which should have
1611 // happened already as part of a 64-bit move)
1612 if( src_second_rc == rc_int && dst_second_rc == rc_int ) {
1613 assert( (src_second&1)==1, "its the evil O0/O1 native return case" );
1614 assert( (dst_second&1)==0, "should have moved with 1 64-bit move" );
1615 // Shift src_second down to dst_second's low bits.
1616 if( cbuf ) {
1617 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_second], Assembler::srlx_op3, Matcher::_regEncode[src_second-1], 0x1020 );
1618 #ifndef PRODUCT
1619 } else if( !do_size ) {
1620 if( size != 0 ) st->print("\n\t");
1621 st->print("SRLX R_%s,32,R_%s\t! spill: Move high bits down low",OptoReg::regname(src_second-1),OptoReg::regname(dst_second));
1622 #endif
1623 }
1624 return size+4;
1625 }
1626
1627 // Check for high word integer store. Must down-shift the hi bits
1628 // into a temp register, then fall into the case of storing int bits.
1629 if( src_second_rc == rc_int && dst_second_rc == rc_stack && (src_second&1)==1 ) {
1630 // Shift src_second down to dst_second's low bits.
1631 if( cbuf ) {
1632 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[R_O7_num], Assembler::srlx_op3, Matcher::_regEncode[src_second-1], 0x1020 );
1633 #ifndef PRODUCT
1634 } else if( !do_size ) {
1635 if( size != 0 ) st->print("\n\t");
1636 st->print("SRLX R_%s,32,R_%s\t! spill: Move high bits down low",OptoReg::regname(src_second-1),OptoReg::regname(R_O7_num));
1637 #endif
1638 }
1639 size+=4;
1640 src_second = OptoReg::Name(R_O7_num); // Not R_O7H_num!
1641 }
1642
1643 // Check for high word integer load
1644 if( dst_second_rc == rc_int && src_second_rc == rc_stack )
1645 return impl_helper(this,cbuf,ra_,do_size,true ,ra_->reg2offset(src_second),dst_second,Assembler::lduw_op3,"LDUW",size, st);
1646
1647 // Check for high word integer store
1648 if( src_second_rc == rc_int && dst_second_rc == rc_stack )
1649 return impl_helper(this,cbuf,ra_,do_size,false,ra_->reg2offset(dst_second),src_second,Assembler::stw_op3 ,"STW ",size, st);
1650
1651 // Check for high word float store
1652 if( src_second_rc == rc_float && dst_second_rc == rc_stack )
1653 return impl_helper(this,cbuf,ra_,do_size,false,ra_->reg2offset(dst_second),src_second,Assembler::stf_op3 ,"STF ",size, st);
1654
1655 #endif // !_LP64
1656
1657 Unimplemented();
1658 return 0;
1659 }
1660
1661 #ifndef PRODUCT
1662 void MachSpillCopyNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
1663 implementation( NULL, ra_, false, st );
1664 }
1665 #endif
1666
1667 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1668 implementation( &cbuf, ra_, false, NULL );
1669 }
1670
1671 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const {
1672 return implementation( NULL, ra_, true, NULL );
1673 }
1674
1675 //=============================================================================
1676 #ifndef PRODUCT
1677 void MachNopNode::format( PhaseRegAlloc *, outputStream *st ) const {
1678 st->print("NOP \t# %d bytes pad for loops and calls", 4 * _count);
1679 }
1680 #endif
1681
1682 void MachNopNode::emit(CodeBuffer &cbuf, PhaseRegAlloc * ) const {
1683 MacroAssembler _masm(&cbuf);
1684 for(int i = 0; i < _count; i += 1) {
1685 __ nop();
1686 }
1687 }
1688
1689 uint MachNopNode::size(PhaseRegAlloc *ra_) const {
1690 return 4 * _count;
1691 }
1692
1693
1694 //=============================================================================
1695 #ifndef PRODUCT
1696 void BoxLockNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
1697 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1698 int reg = ra_->get_reg_first(this);
1699 st->print("LEA [R_SP+#%d+BIAS],%s",offset,Matcher::regName[reg]);
1700 }
1701 #endif
1702
1703 void BoxLockNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1704 MacroAssembler _masm(&cbuf);
1705 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem()) + STACK_BIAS;
1706 int reg = ra_->get_encode(this);
1707
1708 if (Assembler::is_simm13(offset)) {
1709 __ add(SP, offset, reg_to_register_object(reg));
1710 } else {
1711 __ set(offset, O7);
1712 __ add(SP, O7, reg_to_register_object(reg));
1713 }
1714 }
1715
1716 uint BoxLockNode::size(PhaseRegAlloc *ra_) const {
1717 // BoxLockNode is not a MachNode, so we can't just call MachNode::size(ra_)
1718 assert(ra_ == ra_->C->regalloc(), "sanity");
1719 return ra_->C->scratch_emit_size(this);
1720 }
1721
1722 //=============================================================================
1723 #ifndef PRODUCT
1724 void MachUEPNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
1725 st->print_cr("\nUEP:");
1726 #ifdef _LP64
1727 if (UseCompressedClassPointers) {
1728 assert(Universe::heap() != NULL, "java heap should be initialized");
1729 st->print_cr("\tLDUW [R_O0 + oopDesc::klass_offset_in_bytes],R_G5\t! Inline cache check - compressed klass");
1730 if (Universe::narrow_klass_base() != 0) {
1731 st->print_cr("\tSET Universe::narrow_klass_base,R_G6_heap_base");
1732 if (Universe::narrow_klass_shift() != 0) {
1733 st->print_cr("\tSLL R_G5,Universe::narrow_klass_shift,R_G5");
1734 }
1735 st->print_cr("\tADD R_G5,R_G6_heap_base,R_G5");
1736 st->print_cr("\tSET Universe::narrow_ptrs_base,R_G6_heap_base");
1737 } else {
1738 st->print_cr("\tSLL R_G5,Universe::narrow_klass_shift,R_G5");
1739 }
1740 } else {
1741 st->print_cr("\tLDX [R_O0 + oopDesc::klass_offset_in_bytes],R_G5\t! Inline cache check");
1742 }
1743 st->print_cr("\tCMP R_G5,R_G3" );
1744 st->print ("\tTne xcc,R_G0+ST_RESERVED_FOR_USER_0+2");
1745 #else // _LP64
1746 st->print_cr("\tLDUW [R_O0 + oopDesc::klass_offset_in_bytes],R_G5\t! Inline cache check");
1747 st->print_cr("\tCMP R_G5,R_G3" );
1748 st->print ("\tTne icc,R_G0+ST_RESERVED_FOR_USER_0+2");
1749 #endif // _LP64
1750 }
1751 #endif
1752
1753 void MachUEPNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1754 MacroAssembler _masm(&cbuf);
1755 Register G5_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode());
1756 Register temp_reg = G3;
1757 assert( G5_ic_reg != temp_reg, "conflicting registers" );
1758
1759 // Load klass from receiver
1760 __ load_klass(O0, temp_reg);
1761 // Compare against expected klass
1762 __ cmp(temp_reg, G5_ic_reg);
1763 // Branch to miss code, checks xcc or icc depending
1764 __ trap(Assembler::notEqual, Assembler::ptr_cc, G0, ST_RESERVED_FOR_USER_0+2);
1765 }
1766
1767 uint MachUEPNode::size(PhaseRegAlloc *ra_) const {
1768 return MachNode::size(ra_);
1769 }
1770
1771
1772 //=============================================================================
1773
1774
1775 // Emit exception handler code.
1776 int HandlerImpl::emit_exception_handler(CodeBuffer& cbuf) {
1777 Register temp_reg = G3;
1778 AddressLiteral exception_blob(OptoRuntime::exception_blob()->entry_point());
1779 MacroAssembler _masm(&cbuf);
1780
1781 address base = __ start_a_stub(size_exception_handler());
1782 if (base == NULL) {
1783 ciEnv::current()->record_failure("CodeCache is full");
1784 return 0; // CodeBuffer::expand failed
1785 }
1786
1787 int offset = __ offset();
1788
1789 __ JUMP(exception_blob, temp_reg, 0); // sethi;jmp
1790 __ delayed()->nop();
1791
1792 assert(__ offset() - offset <= (int) size_exception_handler(), "overflow");
1793
1794 __ end_a_stub();
1795
1796 return offset;
1797 }
1798
1799 int HandlerImpl::emit_deopt_handler(CodeBuffer& cbuf) {
1800 // Can't use any of the current frame's registers as we may have deopted
1801 // at a poll and everything (including G3) can be live.
1802 Register temp_reg = L0;
1803 AddressLiteral deopt_blob(SharedRuntime::deopt_blob()->unpack());
1804 MacroAssembler _masm(&cbuf);
1805
1806 address base = __ start_a_stub(size_deopt_handler());
1807 if (base == NULL) {
1808 ciEnv::current()->record_failure("CodeCache is full");
1809 return 0; // CodeBuffer::expand failed
1810 }
1811
1812 int offset = __ offset();
1813 __ save_frame(0);
1814 __ JUMP(deopt_blob, temp_reg, 0); // sethi;jmp
1815 __ delayed()->restore();
1816
1817 assert(__ offset() - offset <= (int) size_deopt_handler(), "overflow");
1818
1819 __ end_a_stub();
1820 return offset;
1821
1822 }
1823
1824 // Given a register encoding, produce a Integer Register object
1825 static Register reg_to_register_object(int register_encoding) {
1826 assert(L5->encoding() == R_L5_enc && G1->encoding() == R_G1_enc, "right coding");
1827 return as_Register(register_encoding);
1828 }
1829
1830 // Given a register encoding, produce a single-precision Float Register object
1831 static FloatRegister reg_to_SingleFloatRegister_object(int register_encoding) {
1832 assert(F5->encoding(FloatRegisterImpl::S) == R_F5_enc && F12->encoding(FloatRegisterImpl::S) == R_F12_enc, "right coding");
1833 return as_SingleFloatRegister(register_encoding);
1834 }
1835
1836 // Given a register encoding, produce a double-precision Float Register object
1837 static FloatRegister reg_to_DoubleFloatRegister_object(int register_encoding) {
1838 assert(F4->encoding(FloatRegisterImpl::D) == R_F4_enc, "right coding");
1839 assert(F32->encoding(FloatRegisterImpl::D) == R_D32_enc, "right coding");
1840 return as_DoubleFloatRegister(register_encoding);
1841 }
1842
1843 const bool Matcher::match_rule_supported(int opcode) {
1844 if (!has_match_rule(opcode))
1845 return false;
1846
1847 switch (opcode) {
1848 case Op_CountLeadingZerosI:
1849 case Op_CountLeadingZerosL:
1850 case Op_CountTrailingZerosI:
1851 case Op_CountTrailingZerosL:
1852 case Op_PopCountI:
1853 case Op_PopCountL:
1854 if (!UsePopCountInstruction)
1855 return false;
1856 case Op_CompareAndSwapL:
1857 #ifdef _LP64
1858 case Op_CompareAndSwapP:
1859 #endif
1860 if (!VM_Version::supports_cx8())
1861 return false;
1862 break;
1863 }
1864
1865 return true; // Per default match rules are supported.
1866 }
1867
1868 const bool Matcher::match_rule_supported_vector(int opcode, int vlen) {
1869
1870 // TODO
1871 // identify extra cases that we might want to provide match rules for
1872 // e.g. Op_ vector nodes and other intrinsics while guarding with vlen
1873 bool ret_value = match_rule_supported(opcode);
1874 // Add rules here.
1875
1876 return ret_value; // Per default match rules are supported.
1877 }
1878
1879 const int Matcher::float_pressure(int default_pressure_threshold) {
1880 return default_pressure_threshold;
1881 }
1882
1883 int Matcher::regnum_to_fpu_offset(int regnum) {
1884 return regnum - 32; // The FP registers are in the second chunk
1885 }
1886
1887 #ifdef ASSERT
1888 address last_rethrow = NULL; // debugging aid for Rethrow encoding
1889 #endif
1890
1891 // Vector width in bytes
1892 const int Matcher::vector_width_in_bytes(BasicType bt) {
1893 assert(MaxVectorSize == 8, "");
1894 return 8;
1895 }
1896
1897 // Vector ideal reg
1898 const int Matcher::vector_ideal_reg(int size) {
1899 assert(MaxVectorSize == 8, "");
1900 return Op_RegD;
1901 }
1902
1903 const int Matcher::vector_shift_count_ideal_reg(int size) {
1904 fatal("vector shift is not supported");
1905 return Node::NotAMachineReg;
1906 }
1907
1908 // Limits on vector size (number of elements) loaded into vector.
1909 const int Matcher::max_vector_size(const BasicType bt) {
1910 assert(is_java_primitive(bt), "only primitive type vectors");
1911 return vector_width_in_bytes(bt)/type2aelembytes(bt);
1912 }
1913
1914 const int Matcher::min_vector_size(const BasicType bt) {
1915 return max_vector_size(bt); // Same as max.
1916 }
1917
1918 // SPARC doesn't support misaligned vectors store/load.
1919 const bool Matcher::misaligned_vectors_ok() {
1920 return false;
1921 }
1922
1923 // Current (2013) SPARC platforms need to read original key
1924 // to construct decryption expanded key
1925 const bool Matcher::pass_original_key_for_aes() {
1926 return true;
1927 }
1928
1929 // USII supports fxtof through the whole range of number, USIII doesn't
1930 const bool Matcher::convL2FSupported(void) {
1931 return VM_Version::has_fast_fxtof();
1932 }
1933
1934 // Is this branch offset short enough that a short branch can be used?
1935 //
1936 // NOTE: If the platform does not provide any short branch variants, then
1937 // this method should return false for offset 0.
1938 bool Matcher::is_short_branch_offset(int rule, int br_size, int offset) {
1939 // The passed offset is relative to address of the branch.
1940 // Don't need to adjust the offset.
1941 return UseCBCond && Assembler::is_simm12(offset);
1942 }
1943
1944 const bool Matcher::isSimpleConstant64(jlong value) {
1945 // Will one (StoreL ConL) be cheaper than two (StoreI ConI)?.
1946 // Depends on optimizations in MacroAssembler::setx.
1947 int hi = (int)(value >> 32);
1948 int lo = (int)(value & ~0);
1949 return (hi == 0) || (hi == -1) || (lo == 0);
1950 }
1951
1952 // No scaling for the parameter the ClearArray node.
1953 const bool Matcher::init_array_count_is_in_bytes = true;
1954
1955 // Threshold size for cleararray.
1956 const int Matcher::init_array_short_size = 8 * BytesPerLong;
1957
1958 // No additional cost for CMOVL.
1959 const int Matcher::long_cmove_cost() { return 0; }
1960
1961 // CMOVF/CMOVD are expensive on T4 and on SPARC64.
1962 const int Matcher::float_cmove_cost() {
1963 return (VM_Version::is_T4() || VM_Version::is_sparc64()) ? ConditionalMoveLimit : 0;
1964 }
1965
1966 // Does the CPU require late expand (see block.cpp for description of late expand)?
1967 const bool Matcher::require_postalloc_expand = false;
1968
1969 // Should the Matcher clone shifts on addressing modes, expecting them to
1970 // be subsumed into complex addressing expressions or compute them into
1971 // registers? True for Intel but false for most RISCs
1972 const bool Matcher::clone_shift_expressions = false;
1973
1974 // Do we need to mask the count passed to shift instructions or does
1975 // the cpu only look at the lower 5/6 bits anyway?
1976 const bool Matcher::need_masked_shift_count = false;
1977
1978 bool Matcher::narrow_oop_use_complex_address() {
1979 NOT_LP64(ShouldNotCallThis());
1980 assert(UseCompressedOops, "only for compressed oops code");
1981 return false;
1982 }
1983
1984 bool Matcher::narrow_klass_use_complex_address() {
1985 NOT_LP64(ShouldNotCallThis());
1986 assert(UseCompressedClassPointers, "only for compressed klass code");
1987 return false;
1988 }
1989
1990 // Is it better to copy float constants, or load them directly from memory?
1991 // Intel can load a float constant from a direct address, requiring no
1992 // extra registers. Most RISCs will have to materialize an address into a
1993 // register first, so they would do better to copy the constant from stack.
1994 const bool Matcher::rematerialize_float_constants = false;
1995
1996 // If CPU can load and store mis-aligned doubles directly then no fixup is
1997 // needed. Else we split the double into 2 integer pieces and move it
1998 // piece-by-piece. Only happens when passing doubles into C code as the
1999 // Java calling convention forces doubles to be aligned.
2000 #ifdef _LP64
2001 const bool Matcher::misaligned_doubles_ok = true;
2002 #else
2003 const bool Matcher::misaligned_doubles_ok = false;
2004 #endif
2005
2006 // No-op on SPARC.
2007 void Matcher::pd_implicit_null_fixup(MachNode *node, uint idx) {
2008 }
2009
2010 // Advertise here if the CPU requires explicit rounding operations
2011 // to implement the UseStrictFP mode.
2012 const bool Matcher::strict_fp_requires_explicit_rounding = false;
2013
2014 // Are floats converted to double when stored to stack during deoptimization?
2015 // Sparc does not handle callee-save floats.
2016 bool Matcher::float_in_double() { return false; }
2017
2018 // Do ints take an entire long register or just half?
2019 // Note that we if-def off of _LP64.
2020 // The relevant question is how the int is callee-saved. In _LP64
2021 // the whole long is written but de-opt'ing will have to extract
2022 // the relevant 32 bits, in not-_LP64 only the low 32 bits is written.
2023 #ifdef _LP64
2024 const bool Matcher::int_in_long = true;
2025 #else
2026 const bool Matcher::int_in_long = false;
2027 #endif
2028
2029 // Return whether or not this register is ever used as an argument. This
2030 // function is used on startup to build the trampoline stubs in generateOptoStub.
2031 // Registers not mentioned will be killed by the VM call in the trampoline, and
2032 // arguments in those registers not be available to the callee.
2033 bool Matcher::can_be_java_arg( int reg ) {
2034 // Standard sparc 6 args in registers
2035 if( reg == R_I0_num ||
2036 reg == R_I1_num ||
2037 reg == R_I2_num ||
2038 reg == R_I3_num ||
2039 reg == R_I4_num ||
2040 reg == R_I5_num ) return true;
2041 #ifdef _LP64
2042 // 64-bit builds can pass 64-bit pointers and longs in
2043 // the high I registers
2044 if( reg == R_I0H_num ||
2045 reg == R_I1H_num ||
2046 reg == R_I2H_num ||
2047 reg == R_I3H_num ||
2048 reg == R_I4H_num ||
2049 reg == R_I5H_num ) return true;
2050
2051 if ((UseCompressedOops) && (reg == R_G6_num || reg == R_G6H_num)) {
2052 return true;
2053 }
2054
2055 #else
2056 // 32-bit builds with longs-in-one-entry pass longs in G1 & G4.
2057 // Longs cannot be passed in O regs, because O regs become I regs
2058 // after a 'save' and I regs get their high bits chopped off on
2059 // interrupt.
2060 if( reg == R_G1H_num || reg == R_G1_num ) return true;
2061 if( reg == R_G4H_num || reg == R_G4_num ) return true;
2062 #endif
2063 // A few float args in registers
2064 if( reg >= R_F0_num && reg <= R_F7_num ) return true;
2065
2066 return false;
2067 }
2068
2069 bool Matcher::is_spillable_arg( int reg ) {
2070 return can_be_java_arg(reg);
2071 }
2072
2073 bool Matcher::use_asm_for_ldiv_by_con( jlong divisor ) {
2074 // Use hardware SDIVX instruction when it is
2075 // faster than a code which use multiply.
2076 return VM_Version::has_fast_idiv();
2077 }
2078
2079 // Register for DIVI projection of divmodI
2080 RegMask Matcher::divI_proj_mask() {
2081 ShouldNotReachHere();
2082 return RegMask();
2083 }
2084
2085 // Register for MODI projection of divmodI
2086 RegMask Matcher::modI_proj_mask() {
2087 ShouldNotReachHere();
2088 return RegMask();
2089 }
2090
2091 // Register for DIVL projection of divmodL
2092 RegMask Matcher::divL_proj_mask() {
2093 ShouldNotReachHere();
2094 return RegMask();
2095 }
2096
2097 // Register for MODL projection of divmodL
2098 RegMask Matcher::modL_proj_mask() {
2099 ShouldNotReachHere();
2100 return RegMask();
2101 }
2102
2103 const RegMask Matcher::method_handle_invoke_SP_save_mask() {
2104 return L7_REGP_mask();
2105 }
2106
2107 %}
2108
2109
2110 // The intptr_t operand types, defined by textual substitution.
2111 // (Cf. opto/type.hpp. This lets us avoid many, many other ifdefs.)
2112 #ifdef _LP64
2113 #define immX immL
2114 #define immX13 immL13
2115 #define immX13m7 immL13m7
2116 #define iRegX iRegL
2117 #define g1RegX g1RegL
2118 #else
2119 #define immX immI
2120 #define immX13 immI13
2121 #define immX13m7 immI13m7
2122 #define iRegX iRegI
2123 #define g1RegX g1RegI
2124 #endif
2125
2126 //----------ENCODING BLOCK-----------------------------------------------------
2127 // This block specifies the encoding classes used by the compiler to output
2128 // byte streams. Encoding classes are parameterized macros used by
2129 // Machine Instruction Nodes in order to generate the bit encoding of the
2130 // instruction. Operands specify their base encoding interface with the
2131 // interface keyword. There are currently supported four interfaces,
2132 // REG_INTER, CONST_INTER, MEMORY_INTER, & COND_INTER. REG_INTER causes an
2133 // operand to generate a function which returns its register number when
2134 // queried. CONST_INTER causes an operand to generate a function which
2135 // returns the value of the constant when queried. MEMORY_INTER causes an
2136 // operand to generate four functions which return the Base Register, the
2137 // Index Register, the Scale Value, and the Offset Value of the operand when
2138 // queried. COND_INTER causes an operand to generate six functions which
2139 // return the encoding code (ie - encoding bits for the instruction)
2140 // associated with each basic boolean condition for a conditional instruction.
2141 //
2142 // Instructions specify two basic values for encoding. Again, a function
2143 // is available to check if the constant displacement is an oop. They use the
2144 // ins_encode keyword to specify their encoding classes (which must be
2145 // a sequence of enc_class names, and their parameters, specified in
2146 // the encoding block), and they use the
2147 // opcode keyword to specify, in order, their primary, secondary, and
2148 // tertiary opcode. Only the opcode sections which a particular instruction
2149 // needs for encoding need to be specified.
2150 encode %{
2151 enc_class enc_untested %{
2152 #ifdef ASSERT
2153 MacroAssembler _masm(&cbuf);
2154 __ untested("encoding");
2155 #endif
2156 %}
2157
2158 enc_class form3_mem_reg( memory mem, iRegI dst ) %{
2159 emit_form3_mem_reg(cbuf, ra_, this, $primary, $tertiary,
2160 $mem$$base, $mem$$disp, $mem$$index, $dst$$reg);
2161 %}
2162
2163 enc_class simple_form3_mem_reg( memory mem, iRegI dst ) %{
2164 emit_form3_mem_reg(cbuf, ra_, this, $primary, -1,
2165 $mem$$base, $mem$$disp, $mem$$index, $dst$$reg);
2166 %}
2167
2168 enc_class form3_mem_prefetch_read( memory mem ) %{
2169 emit_form3_mem_reg(cbuf, ra_, this, $primary, -1,
2170 $mem$$base, $mem$$disp, $mem$$index, 0/*prefetch function many-reads*/);
2171 %}
2172
2173 enc_class form3_mem_prefetch_write( memory mem ) %{
2174 emit_form3_mem_reg(cbuf, ra_, this, $primary, -1,
2175 $mem$$base, $mem$$disp, $mem$$index, 2/*prefetch function many-writes*/);
2176 %}
2177
2178 enc_class form3_mem_reg_long_unaligned_marshal( memory mem, iRegL reg ) %{
2179 assert(Assembler::is_simm13($mem$$disp ), "need disp and disp+4");
2180 assert(Assembler::is_simm13($mem$$disp+4), "need disp and disp+4");
2181 guarantee($mem$$index == R_G0_enc, "double index?");
2182 emit_form3_mem_reg(cbuf, ra_, this, $primary, -1, $mem$$base, $mem$$disp+4, R_G0_enc, R_O7_enc );
2183 emit_form3_mem_reg(cbuf, ra_, this, $primary, -1, $mem$$base, $mem$$disp, R_G0_enc, $reg$$reg );
2184 emit3_simm13( cbuf, Assembler::arith_op, $reg$$reg, Assembler::sllx_op3, $reg$$reg, 0x1020 );
2185 emit3( cbuf, Assembler::arith_op, $reg$$reg, Assembler::or_op3, $reg$$reg, 0, R_O7_enc );
2186 %}
2187
2188 enc_class form3_mem_reg_double_unaligned( memory mem, RegD_low reg ) %{
2189 assert(Assembler::is_simm13($mem$$disp ), "need disp and disp+4");
2190 assert(Assembler::is_simm13($mem$$disp+4), "need disp and disp+4");
2191 guarantee($mem$$index == R_G0_enc, "double index?");
2192 // Load long with 2 instructions
2193 emit_form3_mem_reg(cbuf, ra_, this, $primary, -1, $mem$$base, $mem$$disp, R_G0_enc, $reg$$reg+0 );
2194 emit_form3_mem_reg(cbuf, ra_, this, $primary, -1, $mem$$base, $mem$$disp+4, R_G0_enc, $reg$$reg+1 );
2195 %}
2196
2197 //%%% form3_mem_plus_4_reg is a hack--get rid of it
2198 enc_class form3_mem_plus_4_reg( memory mem, iRegI dst ) %{
2199 guarantee($mem$$disp, "cannot offset a reg-reg operand by 4");
2200 emit_form3_mem_reg(cbuf, ra_, this, $primary, -1, $mem$$base, $mem$$disp + 4, $mem$$index, $dst$$reg);
2201 %}
2202
2203 enc_class form3_g0_rs2_rd_move( iRegI rs2, iRegI rd ) %{
2204 // Encode a reg-reg copy. If it is useless, then empty encoding.
2205 if( $rs2$$reg != $rd$$reg )
2206 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, $rs2$$reg );
2207 %}
2208
2209 // Target lo half of long
2210 enc_class form3_g0_rs2_rd_move_lo( iRegI rs2, iRegL rd ) %{
2211 // Encode a reg-reg copy. If it is useless, then empty encoding.
2212 if( $rs2$$reg != LONG_LO_REG($rd$$reg) )
2213 emit3( cbuf, Assembler::arith_op, LONG_LO_REG($rd$$reg), Assembler::or_op3, 0, 0, $rs2$$reg );
2214 %}
2215
2216 // Source lo half of long
2217 enc_class form3_g0_rs2_rd_move_lo2( iRegL rs2, iRegI rd ) %{
2218 // Encode a reg-reg copy. If it is useless, then empty encoding.
2219 if( LONG_LO_REG($rs2$$reg) != $rd$$reg )
2220 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, LONG_LO_REG($rs2$$reg) );
2221 %}
2222
2223 // Target hi half of long
2224 enc_class form3_rs1_rd_copysign_hi( iRegI rs1, iRegL rd ) %{
2225 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::sra_op3, $rs1$$reg, 31 );
2226 %}
2227
2228 // Source lo half of long, and leave it sign extended.
2229 enc_class form3_rs1_rd_signextend_lo1( iRegL rs1, iRegI rd ) %{
2230 // Sign extend low half
2231 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::sra_op3, $rs1$$reg, 0, 0 );
2232 %}
2233
2234 // Source hi half of long, and leave it sign extended.
2235 enc_class form3_rs1_rd_copy_hi1( iRegL rs1, iRegI rd ) %{
2236 // Shift high half to low half
2237 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::srlx_op3, $rs1$$reg, 32 );
2238 %}
2239
2240 // Source hi half of long
2241 enc_class form3_g0_rs2_rd_move_hi2( iRegL rs2, iRegI rd ) %{
2242 // Encode a reg-reg copy. If it is useless, then empty encoding.
2243 if( LONG_HI_REG($rs2$$reg) != $rd$$reg )
2244 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, LONG_HI_REG($rs2$$reg) );
2245 %}
2246
2247 enc_class form3_rs1_rs2_rd( iRegI rs1, iRegI rs2, iRegI rd ) %{
2248 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, 0, $rs2$$reg );
2249 %}
2250
2251 enc_class enc_to_bool( iRegI src, iRegI dst ) %{
2252 emit3 ( cbuf, Assembler::arith_op, 0, Assembler::subcc_op3, 0, 0, $src$$reg );
2253 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::addc_op3 , 0, 0 );
2254 %}
2255
2256 enc_class enc_ltmask( iRegI p, iRegI q, iRegI dst ) %{
2257 emit3 ( cbuf, Assembler::arith_op, 0, Assembler::subcc_op3, $p$$reg, 0, $q$$reg );
2258 // clear if nothing else is happening
2259 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, 0 );
2260 // blt,a,pn done
2261 emit2_19 ( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::less, Assembler::bp_op2, Assembler::icc, 0/*predict not taken*/, 2 );
2262 // mov dst,-1 in delay slot
2263 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, -1 );
2264 %}
2265
2266 enc_class form3_rs1_imm5_rd( iRegI rs1, immU5 imm5, iRegI rd ) %{
2267 emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $imm5$$constant & 0x1F );
2268 %}
2269
2270 enc_class form3_sd_rs1_imm6_rd( iRegL rs1, immU6 imm6, iRegL rd ) %{
2271 emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, ($imm6$$constant & 0x3F) | 0x1000 );
2272 %}
2273
2274 enc_class form3_sd_rs1_rs2_rd( iRegL rs1, iRegI rs2, iRegL rd ) %{
2275 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, 0x80, $rs2$$reg );
2276 %}
2277
2278 enc_class form3_rs1_simm13_rd( iRegI rs1, immI13 simm13, iRegI rd ) %{
2279 emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $simm13$$constant );
2280 %}
2281
2282 enc_class move_return_pc_to_o1() %{
2283 emit3_simm13( cbuf, Assembler::arith_op, R_O1_enc, Assembler::add_op3, R_O7_enc, frame::pc_return_offset );
2284 %}
2285
2286 #ifdef _LP64
2287 /* %%% merge with enc_to_bool */
2288 enc_class enc_convP2B( iRegI dst, iRegP src ) %{
2289 MacroAssembler _masm(&cbuf);
2290
2291 Register src_reg = reg_to_register_object($src$$reg);
2292 Register dst_reg = reg_to_register_object($dst$$reg);
2293 __ movr(Assembler::rc_nz, src_reg, 1, dst_reg);
2294 %}
2295 #endif
2296
2297 enc_class enc_cadd_cmpLTMask( iRegI p, iRegI q, iRegI y, iRegI tmp ) %{
2298 // (Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q)))
2299 MacroAssembler _masm(&cbuf);
2300
2301 Register p_reg = reg_to_register_object($p$$reg);
2302 Register q_reg = reg_to_register_object($q$$reg);
2303 Register y_reg = reg_to_register_object($y$$reg);
2304 Register tmp_reg = reg_to_register_object($tmp$$reg);
2305
2306 __ subcc( p_reg, q_reg, p_reg );
2307 __ add ( p_reg, y_reg, tmp_reg );
2308 __ movcc( Assembler::less, false, Assembler::icc, tmp_reg, p_reg );
2309 %}
2310
2311 enc_class form_d2i_helper(regD src, regF dst) %{
2312 // fcmp %fcc0,$src,$src
2313 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmpd_opf, $src$$reg );
2314 // branch %fcc0 not-nan, predict taken
2315 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 );
2316 // fdtoi $src,$dst
2317 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fdtoi_opf, $src$$reg );
2318 // fitos $dst,$dst (if nan)
2319 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fitos_opf, $dst$$reg );
2320 // clear $dst (if nan)
2321 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubs_opf, $dst$$reg );
2322 // carry on here...
2323 %}
2324
2325 enc_class form_d2l_helper(regD src, regD dst) %{
2326 // fcmp %fcc0,$src,$src check for NAN
2327 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmpd_opf, $src$$reg );
2328 // branch %fcc0 not-nan, predict taken
2329 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 );
2330 // fdtox $src,$dst convert in delay slot
2331 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fdtox_opf, $src$$reg );
2332 // fxtod $dst,$dst (if nan)
2333 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fxtod_opf, $dst$$reg );
2334 // clear $dst (if nan)
2335 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubd_opf, $dst$$reg );
2336 // carry on here...
2337 %}
2338
2339 enc_class form_f2i_helper(regF src, regF dst) %{
2340 // fcmps %fcc0,$src,$src
2341 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmps_opf, $src$$reg );
2342 // branch %fcc0 not-nan, predict taken
2343 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 );
2344 // fstoi $src,$dst
2345 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fstoi_opf, $src$$reg );
2346 // fitos $dst,$dst (if nan)
2347 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fitos_opf, $dst$$reg );
2348 // clear $dst (if nan)
2349 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubs_opf, $dst$$reg );
2350 // carry on here...
2351 %}
2352
2353 enc_class form_f2l_helper(regF src, regD dst) %{
2354 // fcmps %fcc0,$src,$src
2355 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmps_opf, $src$$reg );
2356 // branch %fcc0 not-nan, predict taken
2357 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 );
2358 // fstox $src,$dst
2359 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fstox_opf, $src$$reg );
2360 // fxtod $dst,$dst (if nan)
2361 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fxtod_opf, $dst$$reg );
2362 // clear $dst (if nan)
2363 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubd_opf, $dst$$reg );
2364 // carry on here...
2365 %}
2366
2367 enc_class form3_opf_rs2F_rdF(regF rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
2368 enc_class form3_opf_rs2F_rdD(regF rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
2369 enc_class form3_opf_rs2D_rdF(regD rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
2370 enc_class form3_opf_rs2D_rdD(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
2371
2372 enc_class form3_opf_rs2D_lo_rdF(regD rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg+1); %}
2373
2374 enc_class form3_opf_rs2D_hi_rdD_hi(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
2375 enc_class form3_opf_rs2D_lo_rdD_lo(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg+1,$primary,0,$tertiary,$rs2$$reg+1); %}
2376
2377 enc_class form3_opf_rs1F_rs2F_rdF( regF rs1, regF rs2, regF rd ) %{
2378 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg );
2379 %}
2380
2381 enc_class form3_opf_rs1D_rs2D_rdD( regD rs1, regD rs2, regD rd ) %{
2382 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg );
2383 %}
2384
2385 enc_class form3_opf_rs1F_rs2F_fcc( regF rs1, regF rs2, flagsRegF fcc ) %{
2386 emit3( cbuf, $secondary, $fcc$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg );
2387 %}
2388
2389 enc_class form3_opf_rs1D_rs2D_fcc( regD rs1, regD rs2, flagsRegF fcc ) %{
2390 emit3( cbuf, $secondary, $fcc$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg );
2391 %}
2392
2393 enc_class form3_convI2F(regF rs2, regF rd) %{
2394 emit3(cbuf,Assembler::arith_op,$rd$$reg,Assembler::fpop1_op3,0,$secondary,$rs2$$reg);
2395 %}
2396
2397 // Encloding class for traceable jumps
2398 enc_class form_jmpl(g3RegP dest) %{
2399 emit_jmpl(cbuf, $dest$$reg);
2400 %}
2401
2402 enc_class form_jmpl_set_exception_pc(g1RegP dest) %{
2403 emit_jmpl_set_exception_pc(cbuf, $dest$$reg);
2404 %}
2405
2406 enc_class form2_nop() %{
2407 emit_nop(cbuf);
2408 %}
2409
2410 enc_class form2_illtrap() %{
2411 emit_illtrap(cbuf);
2412 %}
2413
2414
2415 // Compare longs and convert into -1, 0, 1.
2416 enc_class cmpl_flag( iRegL src1, iRegL src2, iRegI dst ) %{
2417 // CMP $src1,$src2
2418 emit3( cbuf, Assembler::arith_op, 0, Assembler::subcc_op3, $src1$$reg, 0, $src2$$reg );
2419 // blt,a,pn done
2420 emit2_19( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::less , Assembler::bp_op2, Assembler::xcc, 0/*predict not taken*/, 5 );
2421 // mov dst,-1 in delay slot
2422 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, -1 );
2423 // bgt,a,pn done
2424 emit2_19( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::greater, Assembler::bp_op2, Assembler::xcc, 0/*predict not taken*/, 3 );
2425 // mov dst,1 in delay slot
2426 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, 1 );
2427 // CLR $dst
2428 emit3( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3 , 0, 0, 0 );
2429 %}
2430
2431 enc_class enc_PartialSubtypeCheck() %{
2432 MacroAssembler _masm(&cbuf);
2433 __ call(StubRoutines::Sparc::partial_subtype_check(), relocInfo::runtime_call_type);
2434 __ delayed()->nop();
2435 %}
2436
2437 enc_class enc_bp( label labl, cmpOp cmp, flagsReg cc ) %{
2438 MacroAssembler _masm(&cbuf);
2439 Label* L = $labl$$label;
2440 Assembler::Predict predict_taken =
2441 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
2442
2443 __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
2444 __ delayed()->nop();
2445 %}
2446
2447 enc_class enc_bpr( label labl, cmpOp_reg cmp, iRegI op1 ) %{
2448 MacroAssembler _masm(&cbuf);
2449 Label* L = $labl$$label;
2450 Assembler::Predict predict_taken =
2451 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
2452
2453 __ bpr( (Assembler::RCondition)($cmp$$cmpcode), false, predict_taken, as_Register($op1$$reg), *L);
2454 __ delayed()->nop();
2455 %}
2456
2457 enc_class enc_cmov_reg( cmpOp cmp, iRegI dst, iRegI src, immI pcc) %{
2458 int op = (Assembler::arith_op << 30) |
2459 ($dst$$reg << 25) |
2460 (Assembler::movcc_op3 << 19) |
2461 (1 << 18) | // cc2 bit for 'icc'
2462 ($cmp$$cmpcode << 14) |
2463 (0 << 13) | // select register move
2464 ($pcc$$constant << 11) | // cc1, cc0 bits for 'icc' or 'xcc'
2465 ($src$$reg << 0);
2466 cbuf.insts()->emit_int32(op);
2467 %}
2468
2469 enc_class enc_cmov_imm( cmpOp cmp, iRegI dst, immI11 src, immI pcc ) %{
2470 int simm11 = $src$$constant & ((1<<11)-1); // Mask to 11 bits
2471 int op = (Assembler::arith_op << 30) |
2472 ($dst$$reg << 25) |
2473 (Assembler::movcc_op3 << 19) |
2474 (1 << 18) | // cc2 bit for 'icc'
2475 ($cmp$$cmpcode << 14) |
2476 (1 << 13) | // select immediate move
2477 ($pcc$$constant << 11) | // cc1, cc0 bits for 'icc'
2478 (simm11 << 0);
2479 cbuf.insts()->emit_int32(op);
2480 %}
2481
2482 enc_class enc_cmov_reg_f( cmpOpF cmp, iRegI dst, iRegI src, flagsRegF fcc ) %{
2483 int op = (Assembler::arith_op << 30) |
2484 ($dst$$reg << 25) |
2485 (Assembler::movcc_op3 << 19) |
2486 (0 << 18) | // cc2 bit for 'fccX'
2487 ($cmp$$cmpcode << 14) |
2488 (0 << 13) | // select register move
2489 ($fcc$$reg << 11) | // cc1, cc0 bits for fcc0-fcc3
2490 ($src$$reg << 0);
2491 cbuf.insts()->emit_int32(op);
2492 %}
2493
2494 enc_class enc_cmov_imm_f( cmpOp cmp, iRegI dst, immI11 src, flagsRegF fcc ) %{
2495 int simm11 = $src$$constant & ((1<<11)-1); // Mask to 11 bits
2496 int op = (Assembler::arith_op << 30) |
2497 ($dst$$reg << 25) |
2498 (Assembler::movcc_op3 << 19) |
2499 (0 << 18) | // cc2 bit for 'fccX'
2500 ($cmp$$cmpcode << 14) |
2501 (1 << 13) | // select immediate move
2502 ($fcc$$reg << 11) | // cc1, cc0 bits for fcc0-fcc3
2503 (simm11 << 0);
2504 cbuf.insts()->emit_int32(op);
2505 %}
2506
2507 enc_class enc_cmovf_reg( cmpOp cmp, regD dst, regD src, immI pcc ) %{
2508 int op = (Assembler::arith_op << 30) |
2509 ($dst$$reg << 25) |
2510 (Assembler::fpop2_op3 << 19) |
2511 (0 << 18) |
2512 ($cmp$$cmpcode << 14) |
2513 (1 << 13) | // select register move
2514 ($pcc$$constant << 11) | // cc1-cc0 bits for 'icc' or 'xcc'
2515 ($primary << 5) | // select single, double or quad
2516 ($src$$reg << 0);
2517 cbuf.insts()->emit_int32(op);
2518 %}
2519
2520 enc_class enc_cmovff_reg( cmpOpF cmp, flagsRegF fcc, regD dst, regD src ) %{
2521 int op = (Assembler::arith_op << 30) |
2522 ($dst$$reg << 25) |
2523 (Assembler::fpop2_op3 << 19) |
2524 (0 << 18) |
2525 ($cmp$$cmpcode << 14) |
2526 ($fcc$$reg << 11) | // cc2-cc0 bits for 'fccX'
2527 ($primary << 5) | // select single, double or quad
2528 ($src$$reg << 0);
2529 cbuf.insts()->emit_int32(op);
2530 %}
2531
2532 // Used by the MIN/MAX encodings. Same as a CMOV, but
2533 // the condition comes from opcode-field instead of an argument.
2534 enc_class enc_cmov_reg_minmax( iRegI dst, iRegI src ) %{
2535 int op = (Assembler::arith_op << 30) |
2536 ($dst$$reg << 25) |
2537 (Assembler::movcc_op3 << 19) |
2538 (1 << 18) | // cc2 bit for 'icc'
2539 ($primary << 14) |
2540 (0 << 13) | // select register move
2541 (0 << 11) | // cc1, cc0 bits for 'icc'
2542 ($src$$reg << 0);
2543 cbuf.insts()->emit_int32(op);
2544 %}
2545
2546 enc_class enc_cmov_reg_minmax_long( iRegL dst, iRegL src ) %{
2547 int op = (Assembler::arith_op << 30) |
2548 ($dst$$reg << 25) |
2549 (Assembler::movcc_op3 << 19) |
2550 (6 << 16) | // cc2 bit for 'xcc'
2551 ($primary << 14) |
2552 (0 << 13) | // select register move
2553 (0 << 11) | // cc1, cc0 bits for 'icc'
2554 ($src$$reg << 0);
2555 cbuf.insts()->emit_int32(op);
2556 %}
2557
2558 enc_class Set13( immI13 src, iRegI rd ) %{
2559 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, $src$$constant );
2560 %}
2561
2562 enc_class SetHi22( immI src, iRegI rd ) %{
2563 emit2_22( cbuf, Assembler::branch_op, $rd$$reg, Assembler::sethi_op2, $src$$constant );
2564 %}
2565
2566 enc_class Set32( immI src, iRegI rd ) %{
2567 MacroAssembler _masm(&cbuf);
2568 __ set($src$$constant, reg_to_register_object($rd$$reg));
2569 %}
2570
2571 enc_class call_epilog %{
2572 if( VerifyStackAtCalls ) {
2573 MacroAssembler _masm(&cbuf);
2574 int framesize = ra_->C->frame_size_in_bytes();
2575 Register temp_reg = G3;
2576 __ add(SP, framesize, temp_reg);
2577 __ cmp(temp_reg, FP);
2578 __ breakpoint_trap(Assembler::notEqual, Assembler::ptr_cc);
2579 }
2580 %}
2581
2582 // Long values come back from native calls in O0:O1 in the 32-bit VM, copy the value
2583 // to G1 so the register allocator will not have to deal with the misaligned register
2584 // pair.
2585 enc_class adjust_long_from_native_call %{
2586 #ifndef _LP64
2587 if (returns_long()) {
2588 // sllx O0,32,O0
2589 emit3_simm13( cbuf, Assembler::arith_op, R_O0_enc, Assembler::sllx_op3, R_O0_enc, 0x1020 );
2590 // srl O1,0,O1
2591 emit3_simm13( cbuf, Assembler::arith_op, R_O1_enc, Assembler::srl_op3, R_O1_enc, 0x0000 );
2592 // or O0,O1,G1
2593 emit3 ( cbuf, Assembler::arith_op, R_G1_enc, Assembler:: or_op3, R_O0_enc, 0, R_O1_enc );
2594 }
2595 #endif
2596 %}
2597
2598 enc_class Java_To_Runtime (method meth) %{ // CALL Java_To_Runtime
2599 // CALL directly to the runtime
2600 // The user of this is responsible for ensuring that R_L7 is empty (killed).
2601 emit_call_reloc(cbuf, $meth$$method, runtime_call_Relocation::spec(), /*preserve_g2=*/true);
2602 %}
2603
2604 enc_class preserve_SP %{
2605 MacroAssembler _masm(&cbuf);
2606 __ mov(SP, L7_mh_SP_save);
2607 %}
2608
2609 enc_class restore_SP %{
2610 MacroAssembler _masm(&cbuf);
2611 __ mov(L7_mh_SP_save, SP);
2612 %}
2613
2614 enc_class Java_Static_Call (method meth) %{ // JAVA STATIC CALL
2615 // CALL to fixup routine. Fixup routine uses ScopeDesc info to determine
2616 // who we intended to call.
2617 if (!_method) {
2618 emit_call_reloc(cbuf, $meth$$method, runtime_call_Relocation::spec());
2619 } else {
2620 int method_index = resolved_method_index(cbuf);
2621 RelocationHolder rspec = _optimized_virtual ? opt_virtual_call_Relocation::spec(method_index)
2622 : static_call_Relocation::spec(method_index);
2623 emit_call_reloc(cbuf, $meth$$method, rspec);
2624
2625 // Emit stub for static call.
2626 address stub = CompiledStaticCall::emit_to_interp_stub(cbuf);
2627 // Stub does not fit into scratch buffer if TraceJumps is enabled
2628 if (stub == NULL && !(TraceJumps && Compile::current()->in_scratch_emit_size())) {
2629 ciEnv::current()->record_failure("CodeCache is full");
2630 return;
2631 }
2632 }
2633 %}
2634
2635 enc_class Java_Dynamic_Call (method meth) %{ // JAVA DYNAMIC CALL
2636 MacroAssembler _masm(&cbuf);
2637 __ set_inst_mark();
2638 int vtable_index = this->_vtable_index;
2639 // MachCallDynamicJavaNode::ret_addr_offset uses this same test
2640 if (vtable_index < 0) {
2641 // must be invalid_vtable_index, not nonvirtual_vtable_index
2642 assert(vtable_index == Method::invalid_vtable_index, "correct sentinel value");
2643 Register G5_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode());
2644 assert(G5_ic_reg == G5_inline_cache_reg, "G5_inline_cache_reg used in assemble_ic_buffer_code()");
2645 assert(G5_ic_reg == G5_megamorphic_method, "G5_megamorphic_method used in megamorphic call stub");
2646 __ ic_call((address)$meth$$method, /*emit_delay=*/true, resolved_method_index(cbuf));
2647 } else {
2648 assert(!UseInlineCaches, "expect vtable calls only if not using ICs");
2649 // Just go thru the vtable
2650 // get receiver klass (receiver already checked for non-null)
2651 // If we end up going thru a c2i adapter interpreter expects method in G5
2652 int off = __ offset();
2653 __ load_klass(O0, G3_scratch);
2654 int klass_load_size;
2655 if (UseCompressedClassPointers) {
2656 assert(Universe::heap() != NULL, "java heap should be initialized");
2657 klass_load_size = MacroAssembler::instr_size_for_decode_klass_not_null() + 1*BytesPerInstWord;
2658 } else {
2659 klass_load_size = 1*BytesPerInstWord;
2660 }
2661 int entry_offset = in_bytes(InstanceKlass::vtable_start_offset()) + vtable_index*vtableEntry::size_in_bytes();
2662 int v_off = entry_offset + vtableEntry::method_offset_in_bytes();
2663 if (Assembler::is_simm13(v_off)) {
2664 __ ld_ptr(G3, v_off, G5_method);
2665 } else {
2666 // Generate 2 instructions
2667 __ Assembler::sethi(v_off & ~0x3ff, G5_method);
2668 __ or3(G5_method, v_off & 0x3ff, G5_method);
2669 // ld_ptr, set_hi, set
2670 assert(__ offset() - off == klass_load_size + 2*BytesPerInstWord,
2671 "Unexpected instruction size(s)");
2672 __ ld_ptr(G3, G5_method, G5_method);
2673 }
2674 // NOTE: for vtable dispatches, the vtable entry will never be null.
2675 // However it may very well end up in handle_wrong_method if the
2676 // method is abstract for the particular class.
2677 __ ld_ptr(G5_method, in_bytes(Method::from_compiled_offset()), G3_scratch);
2678 // jump to target (either compiled code or c2iadapter)
2679 __ jmpl(G3_scratch, G0, O7);
2680 __ delayed()->nop();
2681 }
2682 %}
2683
2684 enc_class Java_Compiled_Call (method meth) %{ // JAVA COMPILED CALL
2685 MacroAssembler _masm(&cbuf);
2686
2687 Register G5_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode());
2688 Register temp_reg = G3; // caller must kill G3! We cannot reuse G5_ic_reg here because
2689 // we might be calling a C2I adapter which needs it.
2690
2691 assert(temp_reg != G5_ic_reg, "conflicting registers");
2692 // Load nmethod
2693 __ ld_ptr(G5_ic_reg, in_bytes(Method::from_compiled_offset()), temp_reg);
2694
2695 // CALL to compiled java, indirect the contents of G3
2696 __ set_inst_mark();
2697 __ callr(temp_reg, G0);
2698 __ delayed()->nop();
2699 %}
2700
2701 enc_class idiv_reg(iRegIsafe src1, iRegIsafe src2, iRegIsafe dst) %{
2702 MacroAssembler _masm(&cbuf);
2703 Register Rdividend = reg_to_register_object($src1$$reg);
2704 Register Rdivisor = reg_to_register_object($src2$$reg);
2705 Register Rresult = reg_to_register_object($dst$$reg);
2706
2707 __ sra(Rdivisor, 0, Rdivisor);
2708 __ sra(Rdividend, 0, Rdividend);
2709 __ sdivx(Rdividend, Rdivisor, Rresult);
2710 %}
2711
2712 enc_class idiv_imm(iRegIsafe src1, immI13 imm, iRegIsafe dst) %{
2713 MacroAssembler _masm(&cbuf);
2714
2715 Register Rdividend = reg_to_register_object($src1$$reg);
2716 int divisor = $imm$$constant;
2717 Register Rresult = reg_to_register_object($dst$$reg);
2718
2719 __ sra(Rdividend, 0, Rdividend);
2720 __ sdivx(Rdividend, divisor, Rresult);
2721 %}
2722
2723 enc_class enc_mul_hi(iRegIsafe dst, iRegIsafe src1, iRegIsafe src2) %{
2724 MacroAssembler _masm(&cbuf);
2725 Register Rsrc1 = reg_to_register_object($src1$$reg);
2726 Register Rsrc2 = reg_to_register_object($src2$$reg);
2727 Register Rdst = reg_to_register_object($dst$$reg);
2728
2729 __ sra( Rsrc1, 0, Rsrc1 );
2730 __ sra( Rsrc2, 0, Rsrc2 );
2731 __ mulx( Rsrc1, Rsrc2, Rdst );
2732 __ srlx( Rdst, 32, Rdst );
2733 %}
2734
2735 enc_class irem_reg(iRegIsafe src1, iRegIsafe src2, iRegIsafe dst, o7RegL scratch) %{
2736 MacroAssembler _masm(&cbuf);
2737 Register Rdividend = reg_to_register_object($src1$$reg);
2738 Register Rdivisor = reg_to_register_object($src2$$reg);
2739 Register Rresult = reg_to_register_object($dst$$reg);
2740 Register Rscratch = reg_to_register_object($scratch$$reg);
2741
2742 assert(Rdividend != Rscratch, "");
2743 assert(Rdivisor != Rscratch, "");
2744
2745 __ sra(Rdividend, 0, Rdividend);
2746 __ sra(Rdivisor, 0, Rdivisor);
2747 __ sdivx(Rdividend, Rdivisor, Rscratch);
2748 __ mulx(Rscratch, Rdivisor, Rscratch);
2749 __ sub(Rdividend, Rscratch, Rresult);
2750 %}
2751
2752 enc_class irem_imm(iRegIsafe src1, immI13 imm, iRegIsafe dst, o7RegL scratch) %{
2753 MacroAssembler _masm(&cbuf);
2754
2755 Register Rdividend = reg_to_register_object($src1$$reg);
2756 int divisor = $imm$$constant;
2757 Register Rresult = reg_to_register_object($dst$$reg);
2758 Register Rscratch = reg_to_register_object($scratch$$reg);
2759
2760 assert(Rdividend != Rscratch, "");
2761
2762 __ sra(Rdividend, 0, Rdividend);
2763 __ sdivx(Rdividend, divisor, Rscratch);
2764 __ mulx(Rscratch, divisor, Rscratch);
2765 __ sub(Rdividend, Rscratch, Rresult);
2766 %}
2767
2768 enc_class fabss (sflt_reg dst, sflt_reg src) %{
2769 MacroAssembler _masm(&cbuf);
2770
2771 FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg);
2772 FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg);
2773
2774 __ fabs(FloatRegisterImpl::S, Fsrc, Fdst);
2775 %}
2776
2777 enc_class fabsd (dflt_reg dst, dflt_reg src) %{
2778 MacroAssembler _masm(&cbuf);
2779
2780 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg);
2781 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg);
2782
2783 __ fabs(FloatRegisterImpl::D, Fsrc, Fdst);
2784 %}
2785
2786 enc_class fnegd (dflt_reg dst, dflt_reg src) %{
2787 MacroAssembler _masm(&cbuf);
2788
2789 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg);
2790 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg);
2791
2792 __ fneg(FloatRegisterImpl::D, Fsrc, Fdst);
2793 %}
2794
2795 enc_class fsqrts (sflt_reg dst, sflt_reg src) %{
2796 MacroAssembler _masm(&cbuf);
2797
2798 FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg);
2799 FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg);
2800
2801 __ fsqrt(FloatRegisterImpl::S, Fsrc, Fdst);
2802 %}
2803
2804 enc_class fsqrtd (dflt_reg dst, dflt_reg src) %{
2805 MacroAssembler _masm(&cbuf);
2806
2807 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg);
2808 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg);
2809
2810 __ fsqrt(FloatRegisterImpl::D, Fsrc, Fdst);
2811 %}
2812
2813 enc_class fmovs (dflt_reg dst, dflt_reg src) %{
2814 MacroAssembler _masm(&cbuf);
2815
2816 FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg);
2817 FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg);
2818
2819 __ fmov(FloatRegisterImpl::S, Fsrc, Fdst);
2820 %}
2821
2822 enc_class fmovd (dflt_reg dst, dflt_reg src) %{
2823 MacroAssembler _masm(&cbuf);
2824
2825 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg);
2826 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg);
2827
2828 __ fmov(FloatRegisterImpl::D, Fsrc, Fdst);
2829 %}
2830
2831 enc_class Fast_Lock(iRegP oop, iRegP box, o7RegP scratch, iRegP scratch2) %{
2832 MacroAssembler _masm(&cbuf);
2833
2834 Register Roop = reg_to_register_object($oop$$reg);
2835 Register Rbox = reg_to_register_object($box$$reg);
2836 Register Rscratch = reg_to_register_object($scratch$$reg);
2837 Register Rmark = reg_to_register_object($scratch2$$reg);
2838
2839 assert(Roop != Rscratch, "");
2840 assert(Roop != Rmark, "");
2841 assert(Rbox != Rscratch, "");
2842 assert(Rbox != Rmark, "");
2843
2844 __ compiler_lock_object(Roop, Rmark, Rbox, Rscratch, _counters, UseBiasedLocking && !UseOptoBiasInlining);
2845 %}
2846
2847 enc_class Fast_Unlock(iRegP oop, iRegP box, o7RegP scratch, iRegP scratch2) %{
2848 MacroAssembler _masm(&cbuf);
2849
2850 Register Roop = reg_to_register_object($oop$$reg);
2851 Register Rbox = reg_to_register_object($box$$reg);
2852 Register Rscratch = reg_to_register_object($scratch$$reg);
2853 Register Rmark = reg_to_register_object($scratch2$$reg);
2854
2855 assert(Roop != Rscratch, "");
2856 assert(Roop != Rmark, "");
2857 assert(Rbox != Rscratch, "");
2858 assert(Rbox != Rmark, "");
2859
2860 __ compiler_unlock_object(Roop, Rmark, Rbox, Rscratch, UseBiasedLocking && !UseOptoBiasInlining);
2861 %}
2862
2863 enc_class enc_cas( iRegP mem, iRegP old, iRegP new ) %{
2864 MacroAssembler _masm(&cbuf);
2865 Register Rmem = reg_to_register_object($mem$$reg);
2866 Register Rold = reg_to_register_object($old$$reg);
2867 Register Rnew = reg_to_register_object($new$$reg);
2868
2869 __ cas_ptr(Rmem, Rold, Rnew); // Swap(*Rmem,Rnew) if *Rmem == Rold
2870 __ cmp( Rold, Rnew );
2871 %}
2872
2873 enc_class enc_casx( iRegP mem, iRegL old, iRegL new) %{
2874 Register Rmem = reg_to_register_object($mem$$reg);
2875 Register Rold = reg_to_register_object($old$$reg);
2876 Register Rnew = reg_to_register_object($new$$reg);
2877
2878 MacroAssembler _masm(&cbuf);
2879 __ mov(Rnew, O7);
2880 __ casx(Rmem, Rold, O7);
2881 __ cmp( Rold, O7 );
2882 %}
2883
2884 // raw int cas, used for compareAndSwap
2885 enc_class enc_casi( iRegP mem, iRegL old, iRegL new) %{
2886 Register Rmem = reg_to_register_object($mem$$reg);
2887 Register Rold = reg_to_register_object($old$$reg);
2888 Register Rnew = reg_to_register_object($new$$reg);
2889
2890 MacroAssembler _masm(&cbuf);
2891 __ mov(Rnew, O7);
2892 __ cas(Rmem, Rold, O7);
2893 __ cmp( Rold, O7 );
2894 %}
2895
2896 enc_class enc_lflags_ne_to_boolean( iRegI res ) %{
2897 Register Rres = reg_to_register_object($res$$reg);
2898
2899 MacroAssembler _masm(&cbuf);
2900 __ mov(1, Rres);
2901 __ movcc( Assembler::notEqual, false, Assembler::xcc, G0, Rres );
2902 %}
2903
2904 enc_class enc_iflags_ne_to_boolean( iRegI res ) %{
2905 Register Rres = reg_to_register_object($res$$reg);
2906
2907 MacroAssembler _masm(&cbuf);
2908 __ mov(1, Rres);
2909 __ movcc( Assembler::notEqual, false, Assembler::icc, G0, Rres );
2910 %}
2911
2912 enc_class floating_cmp ( iRegP dst, regF src1, regF src2 ) %{
2913 MacroAssembler _masm(&cbuf);
2914 Register Rdst = reg_to_register_object($dst$$reg);
2915 FloatRegister Fsrc1 = $primary ? reg_to_SingleFloatRegister_object($src1$$reg)
2916 : reg_to_DoubleFloatRegister_object($src1$$reg);
2917 FloatRegister Fsrc2 = $primary ? reg_to_SingleFloatRegister_object($src2$$reg)
2918 : reg_to_DoubleFloatRegister_object($src2$$reg);
2919
2920 // Convert condition code fcc0 into -1,0,1; unordered reports less-than (-1)
2921 __ float_cmp( $primary, -1, Fsrc1, Fsrc2, Rdst);
2922 %}
2923
2924 enc_class enc_rethrow() %{
2925 cbuf.set_insts_mark();
2926 Register temp_reg = G3;
2927 AddressLiteral rethrow_stub(OptoRuntime::rethrow_stub());
2928 assert(temp_reg != reg_to_register_object(R_I0_num), "temp must not break oop_reg");
2929 MacroAssembler _masm(&cbuf);
2930 #ifdef ASSERT
2931 __ save_frame(0);
2932 AddressLiteral last_rethrow_addrlit(&last_rethrow);
2933 __ sethi(last_rethrow_addrlit, L1);
2934 Address addr(L1, last_rethrow_addrlit.low10());
2935 __ rdpc(L2);
2936 __ inc(L2, 3 * BytesPerInstWord); // skip this & 2 more insns to point at jump_to
2937 __ st_ptr(L2, addr);
2938 __ restore();
2939 #endif
2940 __ JUMP(rethrow_stub, temp_reg, 0); // sethi;jmp
2941 __ delayed()->nop();
2942 %}
2943
2944 enc_class emit_mem_nop() %{
2945 // Generates the instruction LDUXA [o6,g0],#0x82,g0
2946 cbuf.insts()->emit_int32((unsigned int) 0xc0839040);
2947 %}
2948
2949 enc_class emit_fadd_nop() %{
2950 // Generates the instruction FMOVS f31,f31
2951 cbuf.insts()->emit_int32((unsigned int) 0xbfa0003f);
2952 %}
2953
2954 enc_class emit_br_nop() %{
2955 // Generates the instruction BPN,PN .
2956 cbuf.insts()->emit_int32((unsigned int) 0x00400000);
2957 %}
2958
2959 enc_class enc_membar_acquire %{
2960 MacroAssembler _masm(&cbuf);
2961 __ membar( Assembler::Membar_mask_bits(Assembler::LoadStore | Assembler::LoadLoad) );
2962 %}
2963
2964 enc_class enc_membar_release %{
2965 MacroAssembler _masm(&cbuf);
2966 __ membar( Assembler::Membar_mask_bits(Assembler::LoadStore | Assembler::StoreStore) );
2967 %}
2968
2969 enc_class enc_membar_volatile %{
2970 MacroAssembler _masm(&cbuf);
2971 __ membar( Assembler::Membar_mask_bits(Assembler::StoreLoad) );
2972 %}
2973
2974 %}
2975
2976 //----------FRAME--------------------------------------------------------------
2977 // Definition of frame structure and management information.
2978 //
2979 // S T A C K L A Y O U T Allocators stack-slot number
2980 // | (to get allocators register number
2981 // G Owned by | | v add VMRegImpl::stack0)
2982 // r CALLER | |
2983 // o | +--------+ pad to even-align allocators stack-slot
2984 // w V | pad0 | numbers; owned by CALLER
2985 // t -----------+--------+----> Matcher::_in_arg_limit, unaligned
2986 // h ^ | in | 5
2987 // | | args | 4 Holes in incoming args owned by SELF
2988 // | | | | 3
2989 // | | +--------+
2990 // V | | old out| Empty on Intel, window on Sparc
2991 // | old |preserve| Must be even aligned.
2992 // | SP-+--------+----> Matcher::_old_SP, 8 (or 16 in LP64)-byte aligned
2993 // | | in | 3 area for Intel ret address
2994 // Owned by |preserve| Empty on Sparc.
2995 // SELF +--------+
2996 // | | pad2 | 2 pad to align old SP
2997 // | +--------+ 1
2998 // | | locks | 0
2999 // | +--------+----> VMRegImpl::stack0, 8 (or 16 in LP64)-byte aligned
3000 // | | pad1 | 11 pad to align new SP
3001 // | +--------+
3002 // | | | 10
3003 // | | spills | 9 spills
3004 // V | | 8 (pad0 slot for callee)
3005 // -----------+--------+----> Matcher::_out_arg_limit, unaligned
3006 // ^ | out | 7
3007 // | | args | 6 Holes in outgoing args owned by CALLEE
3008 // Owned by +--------+
3009 // CALLEE | new out| 6 Empty on Intel, window on Sparc
3010 // | new |preserve| Must be even-aligned.
3011 // | SP-+--------+----> Matcher::_new_SP, even aligned
3012 // | | |
3013 //
3014 // Note 1: Only region 8-11 is determined by the allocator. Region 0-5 is
3015 // known from SELF's arguments and the Java calling convention.
3016 // Region 6-7 is determined per call site.
3017 // Note 2: If the calling convention leaves holes in the incoming argument
3018 // area, those holes are owned by SELF. Holes in the outgoing area
3019 // are owned by the CALLEE. Holes should not be nessecary in the
3020 // incoming area, as the Java calling convention is completely under
3021 // the control of the AD file. Doubles can be sorted and packed to
3022 // avoid holes. Holes in the outgoing arguments may be necessary for
3023 // varargs C calling conventions.
3024 // Note 3: Region 0-3 is even aligned, with pad2 as needed. Region 3-5 is
3025 // even aligned with pad0 as needed.
3026 // Region 6 is even aligned. Region 6-7 is NOT even aligned;
3027 // region 6-11 is even aligned; it may be padded out more so that
3028 // the region from SP to FP meets the minimum stack alignment.
3029
3030 frame %{
3031 // What direction does stack grow in (assumed to be same for native & Java)
3032 stack_direction(TOWARDS_LOW);
3033
3034 // These two registers define part of the calling convention
3035 // between compiled code and the interpreter.
3036 inline_cache_reg(R_G5); // Inline Cache Register or Method* for I2C
3037 interpreter_method_oop_reg(R_G5); // Method Oop Register when calling interpreter
3038
3039 // Optional: name the operand used by cisc-spilling to access [stack_pointer + offset]
3040 cisc_spilling_operand_name(indOffset);
3041
3042 // Number of stack slots consumed by a Monitor enter
3043 #ifdef _LP64
3044 sync_stack_slots(2);
3045 #else
3046 sync_stack_slots(1);
3047 #endif
3048
3049 // Compiled code's Frame Pointer
3050 frame_pointer(R_SP);
3051
3052 // Stack alignment requirement
3053 stack_alignment(StackAlignmentInBytes);
3054 // LP64: Alignment size in bytes (128-bit -> 16 bytes)
3055 // !LP64: Alignment size in bytes (64-bit -> 8 bytes)
3056
3057 // Number of stack slots between incoming argument block and the start of
3058 // a new frame. The PROLOG must add this many slots to the stack. The
3059 // EPILOG must remove this many slots.
3060 in_preserve_stack_slots(0);
3061
3062 // Number of outgoing stack slots killed above the out_preserve_stack_slots
3063 // for calls to C. Supports the var-args backing area for register parms.
3064 // ADLC doesn't support parsing expressions, so I folded the math by hand.
3065 #ifdef _LP64
3066 // (callee_register_argument_save_area_words (6) + callee_aggregate_return_pointer_words (0)) * 2-stack-slots-per-word
3067 varargs_C_out_slots_killed(12);
3068 #else
3069 // (callee_register_argument_save_area_words (6) + callee_aggregate_return_pointer_words (1)) * 1-stack-slots-per-word
3070 varargs_C_out_slots_killed( 7);
3071 #endif
3072
3073 // The after-PROLOG location of the return address. Location of
3074 // return address specifies a type (REG or STACK) and a number
3075 // representing the register number (i.e. - use a register name) or
3076 // stack slot.
3077 return_addr(REG R_I7); // Ret Addr is in register I7
3078
3079 // Body of function which returns an OptoRegs array locating
3080 // arguments either in registers or in stack slots for calling
3081 // java
3082 calling_convention %{
3083 (void) SharedRuntime::java_calling_convention(sig_bt, regs, length, is_outgoing);
3084
3085 %}
3086
3087 // Body of function which returns an OptoRegs array locating
3088 // arguments either in registers or in stack slots for calling
3089 // C.
3090 c_calling_convention %{
3091 // This is obviously always outgoing
3092 (void) SharedRuntime::c_calling_convention(sig_bt, regs, /*regs2=*/NULL, length);
3093 %}
3094
3095 // Location of native (C/C++) and interpreter return values. This is specified to
3096 // be the same as Java. In the 32-bit VM, long values are actually returned from
3097 // native calls in O0:O1 and returned to the interpreter in I0:I1. The copying
3098 // to and from the register pairs is done by the appropriate call and epilog
3099 // opcodes. This simplifies the register allocator.
3100 c_return_value %{
3101 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" );
3102 #ifdef _LP64
3103 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_O0_num };
3104 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_O0H_num, OptoReg::Bad, R_F1_num, R_O0H_num};
3105 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_I0_num };
3106 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_I0H_num, OptoReg::Bad, R_F1_num, R_I0H_num};
3107 #else // !_LP64
3108 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_G1_num };
3109 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num };
3110 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_G1_num };
3111 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num };
3112 #endif
3113 return OptoRegPair( (is_outgoing?hi_out:hi_in)[ideal_reg],
3114 (is_outgoing?lo_out:lo_in)[ideal_reg] );
3115 %}
3116
3117 // Location of compiled Java return values. Same as C
3118 return_value %{
3119 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" );
3120 #ifdef _LP64
3121 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_O0_num };
3122 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_O0H_num, OptoReg::Bad, R_F1_num, R_O0H_num};
3123 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_I0_num };
3124 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_I0H_num, OptoReg::Bad, R_F1_num, R_I0H_num};
3125 #else // !_LP64
3126 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_G1_num };
3127 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num};
3128 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_G1_num };
3129 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num};
3130 #endif
3131 return OptoRegPair( (is_outgoing?hi_out:hi_in)[ideal_reg],
3132 (is_outgoing?lo_out:lo_in)[ideal_reg] );
3133 %}
3134
3135 %}
3136
3137
3138 //----------ATTRIBUTES---------------------------------------------------------
3139 //----------Operand Attributes-------------------------------------------------
3140 op_attrib op_cost(1); // Required cost attribute
3141
3142 //----------Instruction Attributes---------------------------------------------
3143 ins_attrib ins_cost(DEFAULT_COST); // Required cost attribute
3144 ins_attrib ins_size(32); // Required size attribute (in bits)
3145
3146 // avoid_back_to_back attribute is an expression that must return
3147 // one of the following values defined in MachNode:
3148 // AVOID_NONE - instruction can be placed anywhere
3149 // AVOID_BEFORE - instruction cannot be placed after an
3150 // instruction with MachNode::AVOID_AFTER
3151 // AVOID_AFTER - the next instruction cannot be the one
3152 // with MachNode::AVOID_BEFORE
3153 // AVOID_BEFORE_AND_AFTER - BEFORE and AFTER attributes at
3154 // the same time
3155 ins_attrib ins_avoid_back_to_back(MachNode::AVOID_NONE);
3156
3157 ins_attrib ins_short_branch(0); // Required flag: is this instruction a
3158 // non-matching short branch variant of some
3159 // long branch?
3160
3161 //----------OPERANDS-----------------------------------------------------------
3162 // Operand definitions must precede instruction definitions for correct parsing
3163 // in the ADLC because operands constitute user defined types which are used in
3164 // instruction definitions.
3165
3166 //----------Simple Operands----------------------------------------------------
3167 // Immediate Operands
3168 // Integer Immediate: 32-bit
3169 operand immI() %{
3170 match(ConI);
3171
3172 op_cost(0);
3173 // formats are generated automatically for constants and base registers
3174 format %{ %}
3175 interface(CONST_INTER);
3176 %}
3177
3178 // Integer Immediate: 0-bit
3179 operand immI0() %{
3180 predicate(n->get_int() == 0);
3181 match(ConI);
3182 op_cost(0);
3183
3184 format %{ %}
3185 interface(CONST_INTER);
3186 %}
3187
3188 // Integer Immediate: 5-bit
3189 operand immI5() %{
3190 predicate(Assembler::is_simm5(n->get_int()));
3191 match(ConI);
3192 op_cost(0);
3193 format %{ %}
3194 interface(CONST_INTER);
3195 %}
3196
3197 // Integer Immediate: 8-bit
3198 operand immI8() %{
3199 predicate(Assembler::is_simm8(n->get_int()));
3200 match(ConI);
3201 op_cost(0);
3202 format %{ %}
3203 interface(CONST_INTER);
3204 %}
3205
3206 // Integer Immediate: the value 10
3207 operand immI10() %{
3208 predicate(n->get_int() == 10);
3209 match(ConI);
3210 op_cost(0);
3211
3212 format %{ %}
3213 interface(CONST_INTER);
3214 %}
3215
3216 // Integer Immediate: 11-bit
3217 operand immI11() %{
3218 predicate(Assembler::is_simm11(n->get_int()));
3219 match(ConI);
3220 op_cost(0);
3221 format %{ %}
3222 interface(CONST_INTER);
3223 %}
3224
3225 // Integer Immediate: 13-bit
3226 operand immI13() %{
3227 predicate(Assembler::is_simm13(n->get_int()));
3228 match(ConI);
3229 op_cost(0);
3230
3231 format %{ %}
3232 interface(CONST_INTER);
3233 %}
3234
3235 // Integer Immediate: 13-bit minus 7
3236 operand immI13m7() %{
3237 predicate((-4096 < n->get_int()) && ((n->get_int() + 7) <= 4095));
3238 match(ConI);
3239 op_cost(0);
3240
3241 format %{ %}
3242 interface(CONST_INTER);
3243 %}
3244
3245 // Integer Immediate: 16-bit
3246 operand immI16() %{
3247 predicate(Assembler::is_simm16(n->get_int()));
3248 match(ConI);
3249 op_cost(0);
3250 format %{ %}
3251 interface(CONST_INTER);
3252 %}
3253
3254 // Integer Immediate: the values 1-31
3255 operand immI_1_31() %{
3256 predicate(n->get_int() >= 1 && n->get_int() <= 31);
3257 match(ConI);
3258 op_cost(0);
3259
3260 format %{ %}
3261 interface(CONST_INTER);
3262 %}
3263
3264 // Integer Immediate: the values 32-63
3265 operand immI_32_63() %{
3266 predicate(n->get_int() >= 32 && n->get_int() <= 63);
3267 match(ConI);
3268 op_cost(0);
3269
3270 format %{ %}
3271 interface(CONST_INTER);
3272 %}
3273
3274 // Immediates for special shifts (sign extend)
3275
3276 // Integer Immediate: the value 16
3277 operand immI_16() %{
3278 predicate(n->get_int() == 16);
3279 match(ConI);
3280 op_cost(0);
3281
3282 format %{ %}
3283 interface(CONST_INTER);
3284 %}
3285
3286 // Integer Immediate: the value 24
3287 operand immI_24() %{
3288 predicate(n->get_int() == 24);
3289 match(ConI);
3290 op_cost(0);
3291
3292 format %{ %}
3293 interface(CONST_INTER);
3294 %}
3295 // Integer Immediate: the value 255
3296 operand immI_255() %{
3297 predicate( n->get_int() == 255 );
3298 match(ConI);
3299 op_cost(0);
3300
3301 format %{ %}
3302 interface(CONST_INTER);
3303 %}
3304
3305 // Integer Immediate: the value 65535
3306 operand immI_65535() %{
3307 predicate(n->get_int() == 65535);
3308 match(ConI);
3309 op_cost(0);
3310
3311 format %{ %}
3312 interface(CONST_INTER);
3313 %}
3314
3315 // Integer Immediate: the values 0-31
3316 operand immU5() %{
3317 predicate(n->get_int() >= 0 && n->get_int() <= 31);
3318 match(ConI);
3319 op_cost(0);
3320
3321 format %{ %}
3322 interface(CONST_INTER);
3323 %}
3324
3325 // Integer Immediate: 6-bit
3326 operand immU6() %{
3327 predicate(n->get_int() >= 0 && n->get_int() <= 63);
3328 match(ConI);
3329 op_cost(0);
3330 format %{ %}
3331 interface(CONST_INTER);
3332 %}
3333
3334 // Unsigned Integer Immediate: 12-bit (non-negative that fits in simm13)
3335 operand immU12() %{
3336 predicate((0 <= n->get_int()) && Assembler::is_simm13(n->get_int()));
3337 match(ConI);
3338 op_cost(0);
3339
3340 format %{ %}
3341 interface(CONST_INTER);
3342 %}
3343
3344 // Integer Immediate non-negative
3345 operand immU31()
3346 %{
3347 predicate(n->get_int() >= 0);
3348 match(ConI);
3349
3350 op_cost(0);
3351 format %{ %}
3352 interface(CONST_INTER);
3353 %}
3354
3355 // Long Immediate: the value FF
3356 operand immL_FF() %{
3357 predicate( n->get_long() == 0xFFL );
3358 match(ConL);
3359 op_cost(0);
3360
3361 format %{ %}
3362 interface(CONST_INTER);
3363 %}
3364
3365 // Long Immediate: the value FFFF
3366 operand immL_FFFF() %{
3367 predicate( n->get_long() == 0xFFFFL );
3368 match(ConL);
3369 op_cost(0);
3370
3371 format %{ %}
3372 interface(CONST_INTER);
3373 %}
3374
3375 // Pointer Immediate: 32 or 64-bit
3376 operand immP() %{
3377 match(ConP);
3378
3379 op_cost(5);
3380 // formats are generated automatically for constants and base registers
3381 format %{ %}
3382 interface(CONST_INTER);
3383 %}
3384
3385 #ifdef _LP64
3386 // Pointer Immediate: 64-bit
3387 operand immP_set() %{
3388 predicate(!VM_Version::is_niagara_plus());
3389 match(ConP);
3390
3391 op_cost(5);
3392 // formats are generated automatically for constants and base registers
3393 format %{ %}
3394 interface(CONST_INTER);
3395 %}
3396
3397 // Pointer Immediate: 64-bit
3398 // From Niagara2 processors on a load should be better than materializing.
3399 operand immP_load() %{
3400 predicate(VM_Version::is_niagara_plus() && (n->bottom_type()->isa_oop_ptr() || (MacroAssembler::insts_for_set(n->get_ptr()) > 3)));
3401 match(ConP);
3402
3403 op_cost(5);
3404 // formats are generated automatically for constants and base registers
3405 format %{ %}
3406 interface(CONST_INTER);
3407 %}
3408
3409 // Pointer Immediate: 64-bit
3410 operand immP_no_oop_cheap() %{
3411 predicate(VM_Version::is_niagara_plus() && !n->bottom_type()->isa_oop_ptr() && (MacroAssembler::insts_for_set(n->get_ptr()) <= 3));
3412 match(ConP);
3413
3414 op_cost(5);
3415 // formats are generated automatically for constants and base registers
3416 format %{ %}
3417 interface(CONST_INTER);
3418 %}
3419 #endif
3420
3421 operand immP13() %{
3422 predicate((-4096 < n->get_ptr()) && (n->get_ptr() <= 4095));
3423 match(ConP);
3424 op_cost(0);
3425
3426 format %{ %}
3427 interface(CONST_INTER);
3428 %}
3429
3430 operand immP0() %{
3431 predicate(n->get_ptr() == 0);
3432 match(ConP);
3433 op_cost(0);
3434
3435 format %{ %}
3436 interface(CONST_INTER);
3437 %}
3438
3439 operand immP_poll() %{
3440 predicate(n->get_ptr() != 0 && n->get_ptr() == (intptr_t)os::get_polling_page());
3441 match(ConP);
3442
3443 // formats are generated automatically for constants and base registers
3444 format %{ %}
3445 interface(CONST_INTER);
3446 %}
3447
3448 // Pointer Immediate
3449 operand immN()
3450 %{
3451 match(ConN);
3452
3453 op_cost(10);
3454 format %{ %}
3455 interface(CONST_INTER);
3456 %}
3457
3458 operand immNKlass()
3459 %{
3460 match(ConNKlass);
3461
3462 op_cost(10);
3463 format %{ %}
3464 interface(CONST_INTER);
3465 %}
3466
3467 // NULL Pointer Immediate
3468 operand immN0()
3469 %{
3470 predicate(n->get_narrowcon() == 0);
3471 match(ConN);
3472
3473 op_cost(0);
3474 format %{ %}
3475 interface(CONST_INTER);
3476 %}
3477
3478 operand immL() %{
3479 match(ConL);
3480 op_cost(40);
3481 // formats are generated automatically for constants and base registers
3482 format %{ %}
3483 interface(CONST_INTER);
3484 %}
3485
3486 operand immL0() %{
3487 predicate(n->get_long() == 0L);
3488 match(ConL);
3489 op_cost(0);
3490 // formats are generated automatically for constants and base registers
3491 format %{ %}
3492 interface(CONST_INTER);
3493 %}
3494
3495 // Integer Immediate: 5-bit
3496 operand immL5() %{
3497 predicate(n->get_long() == (int)n->get_long() && Assembler::is_simm5((int)n->get_long()));
3498 match(ConL);
3499 op_cost(0);
3500 format %{ %}
3501 interface(CONST_INTER);
3502 %}
3503
3504 // Long Immediate: 13-bit
3505 operand immL13() %{
3506 predicate((-4096L < n->get_long()) && (n->get_long() <= 4095L));
3507 match(ConL);
3508 op_cost(0);
3509
3510 format %{ %}
3511 interface(CONST_INTER);
3512 %}
3513
3514 // Long Immediate: 13-bit minus 7
3515 operand immL13m7() %{
3516 predicate((-4096L < n->get_long()) && ((n->get_long() + 7L) <= 4095L));
3517 match(ConL);
3518 op_cost(0);
3519
3520 format %{ %}
3521 interface(CONST_INTER);
3522 %}
3523
3524 // Long Immediate: low 32-bit mask
3525 operand immL_32bits() %{
3526 predicate(n->get_long() == 0xFFFFFFFFL);
3527 match(ConL);
3528 op_cost(0);
3529
3530 format %{ %}
3531 interface(CONST_INTER);
3532 %}
3533
3534 // Long Immediate: cheap (materialize in <= 3 instructions)
3535 operand immL_cheap() %{
3536 predicate(!VM_Version::is_niagara_plus() || MacroAssembler::insts_for_set64(n->get_long()) <= 3);
3537 match(ConL);
3538 op_cost(0);
3539
3540 format %{ %}
3541 interface(CONST_INTER);
3542 %}
3543
3544 // Long Immediate: expensive (materialize in > 3 instructions)
3545 operand immL_expensive() %{
3546 predicate(VM_Version::is_niagara_plus() && MacroAssembler::insts_for_set64(n->get_long()) > 3);
3547 match(ConL);
3548 op_cost(0);
3549
3550 format %{ %}
3551 interface(CONST_INTER);
3552 %}
3553
3554 // Double Immediate
3555 operand immD() %{
3556 match(ConD);
3557
3558 op_cost(40);
3559 format %{ %}
3560 interface(CONST_INTER);
3561 %}
3562
3563 // Double Immediate: +0.0d
3564 operand immD0() %{
3565 predicate(jlong_cast(n->getd()) == 0);
3566 match(ConD);
3567
3568 op_cost(0);
3569 format %{ %}
3570 interface(CONST_INTER);
3571 %}
3572
3573 // Float Immediate
3574 operand immF() %{
3575 match(ConF);
3576
3577 op_cost(20);
3578 format %{ %}
3579 interface(CONST_INTER);
3580 %}
3581
3582 // Float Immediate: +0.0f
3583 operand immF0() %{
3584 predicate(jint_cast(n->getf()) == 0);
3585 match(ConF);
3586
3587 op_cost(0);
3588 format %{ %}
3589 interface(CONST_INTER);
3590 %}
3591
3592 // Integer Register Operands
3593 // Integer Register
3594 operand iRegI() %{
3595 constraint(ALLOC_IN_RC(int_reg));
3596 match(RegI);
3597
3598 match(notemp_iRegI);
3599 match(g1RegI);
3600 match(o0RegI);
3601 match(iRegIsafe);
3602
3603 format %{ %}
3604 interface(REG_INTER);
3605 %}
3606
3607 operand notemp_iRegI() %{
3608 constraint(ALLOC_IN_RC(notemp_int_reg));
3609 match(RegI);
3610
3611 match(o0RegI);
3612
3613 format %{ %}
3614 interface(REG_INTER);
3615 %}
3616
3617 operand o0RegI() %{
3618 constraint(ALLOC_IN_RC(o0_regI));
3619 match(iRegI);
3620
3621 format %{ %}
3622 interface(REG_INTER);
3623 %}
3624
3625 // Pointer Register
3626 operand iRegP() %{
3627 constraint(ALLOC_IN_RC(ptr_reg));
3628 match(RegP);
3629
3630 match(lock_ptr_RegP);
3631 match(g1RegP);
3632 match(g2RegP);
3633 match(g3RegP);
3634 match(g4RegP);
3635 match(i0RegP);
3636 match(o0RegP);
3637 match(o1RegP);
3638 match(l7RegP);
3639
3640 format %{ %}
3641 interface(REG_INTER);
3642 %}
3643
3644 operand sp_ptr_RegP() %{
3645 constraint(ALLOC_IN_RC(sp_ptr_reg));
3646 match(RegP);
3647 match(iRegP);
3648
3649 format %{ %}
3650 interface(REG_INTER);
3651 %}
3652
3653 operand lock_ptr_RegP() %{
3654 constraint(ALLOC_IN_RC(lock_ptr_reg));
3655 match(RegP);
3656 match(i0RegP);
3657 match(o0RegP);
3658 match(o1RegP);
3659 match(l7RegP);
3660
3661 format %{ %}
3662 interface(REG_INTER);
3663 %}
3664
3665 operand g1RegP() %{
3666 constraint(ALLOC_IN_RC(g1_regP));
3667 match(iRegP);
3668
3669 format %{ %}
3670 interface(REG_INTER);
3671 %}
3672
3673 operand g2RegP() %{
3674 constraint(ALLOC_IN_RC(g2_regP));
3675 match(iRegP);
3676
3677 format %{ %}
3678 interface(REG_INTER);
3679 %}
3680
3681 operand g3RegP() %{
3682 constraint(ALLOC_IN_RC(g3_regP));
3683 match(iRegP);
3684
3685 format %{ %}
3686 interface(REG_INTER);
3687 %}
3688
3689 operand g1RegI() %{
3690 constraint(ALLOC_IN_RC(g1_regI));
3691 match(iRegI);
3692
3693 format %{ %}
3694 interface(REG_INTER);
3695 %}
3696
3697 operand g3RegI() %{
3698 constraint(ALLOC_IN_RC(g3_regI));
3699 match(iRegI);
3700
3701 format %{ %}
3702 interface(REG_INTER);
3703 %}
3704
3705 operand g4RegI() %{
3706 constraint(ALLOC_IN_RC(g4_regI));
3707 match(iRegI);
3708
3709 format %{ %}
3710 interface(REG_INTER);
3711 %}
3712
3713 operand g4RegP() %{
3714 constraint(ALLOC_IN_RC(g4_regP));
3715 match(iRegP);
3716
3717 format %{ %}
3718 interface(REG_INTER);
3719 %}
3720
3721 operand i0RegP() %{
3722 constraint(ALLOC_IN_RC(i0_regP));
3723 match(iRegP);
3724
3725 format %{ %}
3726 interface(REG_INTER);
3727 %}
3728
3729 operand o0RegP() %{
3730 constraint(ALLOC_IN_RC(o0_regP));
3731 match(iRegP);
3732
3733 format %{ %}
3734 interface(REG_INTER);
3735 %}
3736
3737 operand o1RegP() %{
3738 constraint(ALLOC_IN_RC(o1_regP));
3739 match(iRegP);
3740
3741 format %{ %}
3742 interface(REG_INTER);
3743 %}
3744
3745 operand o2RegP() %{
3746 constraint(ALLOC_IN_RC(o2_regP));
3747 match(iRegP);
3748
3749 format %{ %}
3750 interface(REG_INTER);
3751 %}
3752
3753 operand o7RegP() %{
3754 constraint(ALLOC_IN_RC(o7_regP));
3755 match(iRegP);
3756
3757 format %{ %}
3758 interface(REG_INTER);
3759 %}
3760
3761 operand l7RegP() %{
3762 constraint(ALLOC_IN_RC(l7_regP));
3763 match(iRegP);
3764
3765 format %{ %}
3766 interface(REG_INTER);
3767 %}
3768
3769 operand o7RegI() %{
3770 constraint(ALLOC_IN_RC(o7_regI));
3771 match(iRegI);
3772
3773 format %{ %}
3774 interface(REG_INTER);
3775 %}
3776
3777 operand iRegN() %{
3778 constraint(ALLOC_IN_RC(int_reg));
3779 match(RegN);
3780
3781 format %{ %}
3782 interface(REG_INTER);
3783 %}
3784
3785 // Long Register
3786 operand iRegL() %{
3787 constraint(ALLOC_IN_RC(long_reg));
3788 match(RegL);
3789
3790 format %{ %}
3791 interface(REG_INTER);
3792 %}
3793
3794 operand o2RegL() %{
3795 constraint(ALLOC_IN_RC(o2_regL));
3796 match(iRegL);
3797
3798 format %{ %}
3799 interface(REG_INTER);
3800 %}
3801
3802 operand o7RegL() %{
3803 constraint(ALLOC_IN_RC(o7_regL));
3804 match(iRegL);
3805
3806 format %{ %}
3807 interface(REG_INTER);
3808 %}
3809
3810 operand g1RegL() %{
3811 constraint(ALLOC_IN_RC(g1_regL));
3812 match(iRegL);
3813
3814 format %{ %}
3815 interface(REG_INTER);
3816 %}
3817
3818 operand g3RegL() %{
3819 constraint(ALLOC_IN_RC(g3_regL));
3820 match(iRegL);
3821
3822 format %{ %}
3823 interface(REG_INTER);
3824 %}
3825
3826 // Int Register safe
3827 // This is 64bit safe
3828 operand iRegIsafe() %{
3829 constraint(ALLOC_IN_RC(long_reg));
3830
3831 match(iRegI);
3832
3833 format %{ %}
3834 interface(REG_INTER);
3835 %}
3836
3837 // Condition Code Flag Register
3838 operand flagsReg() %{
3839 constraint(ALLOC_IN_RC(int_flags));
3840 match(RegFlags);
3841
3842 format %{ "ccr" %} // both ICC and XCC
3843 interface(REG_INTER);
3844 %}
3845
3846 // Condition Code Register, unsigned comparisons.
3847 operand flagsRegU() %{
3848 constraint(ALLOC_IN_RC(int_flags));
3849 match(RegFlags);
3850
3851 format %{ "icc_U" %}
3852 interface(REG_INTER);
3853 %}
3854
3855 // Condition Code Register, pointer comparisons.
3856 operand flagsRegP() %{
3857 constraint(ALLOC_IN_RC(int_flags));
3858 match(RegFlags);
3859
3860 #ifdef _LP64
3861 format %{ "xcc_P" %}
3862 #else
3863 format %{ "icc_P" %}
3864 #endif
3865 interface(REG_INTER);
3866 %}
3867
3868 // Condition Code Register, long comparisons.
3869 operand flagsRegL() %{
3870 constraint(ALLOC_IN_RC(int_flags));
3871 match(RegFlags);
3872
3873 format %{ "xcc_L" %}
3874 interface(REG_INTER);
3875 %}
3876
3877 // Condition Code Register, floating comparisons, unordered same as "less".
3878 operand flagsRegF() %{
3879 constraint(ALLOC_IN_RC(float_flags));
3880 match(RegFlags);
3881 match(flagsRegF0);
3882
3883 format %{ %}
3884 interface(REG_INTER);
3885 %}
3886
3887 operand flagsRegF0() %{
3888 constraint(ALLOC_IN_RC(float_flag0));
3889 match(RegFlags);
3890
3891 format %{ %}
3892 interface(REG_INTER);
3893 %}
3894
3895
3896 // Condition Code Flag Register used by long compare
3897 operand flagsReg_long_LTGE() %{
3898 constraint(ALLOC_IN_RC(int_flags));
3899 match(RegFlags);
3900 format %{ "icc_LTGE" %}
3901 interface(REG_INTER);
3902 %}
3903 operand flagsReg_long_EQNE() %{
3904 constraint(ALLOC_IN_RC(int_flags));
3905 match(RegFlags);
3906 format %{ "icc_EQNE" %}
3907 interface(REG_INTER);
3908 %}
3909 operand flagsReg_long_LEGT() %{
3910 constraint(ALLOC_IN_RC(int_flags));
3911 match(RegFlags);
3912 format %{ "icc_LEGT" %}
3913 interface(REG_INTER);
3914 %}
3915
3916
3917 operand regD() %{
3918 constraint(ALLOC_IN_RC(dflt_reg));
3919 match(RegD);
3920
3921 match(regD_low);
3922
3923 format %{ %}
3924 interface(REG_INTER);
3925 %}
3926
3927 operand regF() %{
3928 constraint(ALLOC_IN_RC(sflt_reg));
3929 match(RegF);
3930
3931 format %{ %}
3932 interface(REG_INTER);
3933 %}
3934
3935 operand regD_low() %{
3936 constraint(ALLOC_IN_RC(dflt_low_reg));
3937 match(regD);
3938
3939 format %{ %}
3940 interface(REG_INTER);
3941 %}
3942
3943 // Special Registers
3944
3945 // Method Register
3946 operand inline_cache_regP(iRegP reg) %{
3947 constraint(ALLOC_IN_RC(g5_regP)); // G5=inline_cache_reg but uses 2 bits instead of 1
3948 match(reg);
3949 format %{ %}
3950 interface(REG_INTER);
3951 %}
3952
3953 operand interpreter_method_oop_regP(iRegP reg) %{
3954 constraint(ALLOC_IN_RC(g5_regP)); // G5=interpreter_method_oop_reg but uses 2 bits instead of 1
3955 match(reg);
3956 format %{ %}
3957 interface(REG_INTER);
3958 %}
3959
3960
3961 //----------Complex Operands---------------------------------------------------
3962 // Indirect Memory Reference
3963 operand indirect(sp_ptr_RegP reg) %{
3964 constraint(ALLOC_IN_RC(sp_ptr_reg));
3965 match(reg);
3966
3967 op_cost(100);
3968 format %{ "[$reg]" %}
3969 interface(MEMORY_INTER) %{
3970 base($reg);
3971 index(0x0);
3972 scale(0x0);
3973 disp(0x0);
3974 %}
3975 %}
3976
3977 // Indirect with simm13 Offset
3978 operand indOffset13(sp_ptr_RegP reg, immX13 offset) %{
3979 constraint(ALLOC_IN_RC(sp_ptr_reg));
3980 match(AddP reg offset);
3981
3982 op_cost(100);
3983 format %{ "[$reg + $offset]" %}
3984 interface(MEMORY_INTER) %{
3985 base($reg);
3986 index(0x0);
3987 scale(0x0);
3988 disp($offset);
3989 %}
3990 %}
3991
3992 // Indirect with simm13 Offset minus 7
3993 operand indOffset13m7(sp_ptr_RegP reg, immX13m7 offset) %{
3994 constraint(ALLOC_IN_RC(sp_ptr_reg));
3995 match(AddP reg offset);
3996
3997 op_cost(100);
3998 format %{ "[$reg + $offset]" %}
3999 interface(MEMORY_INTER) %{
4000 base($reg);
4001 index(0x0);
4002 scale(0x0);
4003 disp($offset);
4004 %}
4005 %}
4006
4007 // Note: Intel has a swapped version also, like this:
4008 //operand indOffsetX(iRegI reg, immP offset) %{
4009 // constraint(ALLOC_IN_RC(int_reg));
4010 // match(AddP offset reg);
4011 //
4012 // op_cost(100);
4013 // format %{ "[$reg + $offset]" %}
4014 // interface(MEMORY_INTER) %{
4015 // base($reg);
4016 // index(0x0);
4017 // scale(0x0);
4018 // disp($offset);
4019 // %}
4020 //%}
4021 //// However, it doesn't make sense for SPARC, since
4022 // we have no particularly good way to embed oops in
4023 // single instructions.
4024
4025 // Indirect with Register Index
4026 operand indIndex(iRegP addr, iRegX index) %{
4027 constraint(ALLOC_IN_RC(ptr_reg));
4028 match(AddP addr index);
4029
4030 op_cost(100);
4031 format %{ "[$addr + $index]" %}
4032 interface(MEMORY_INTER) %{
4033 base($addr);
4034 index($index);
4035 scale(0x0);
4036 disp(0x0);
4037 %}
4038 %}
4039
4040 //----------Special Memory Operands--------------------------------------------
4041 // Stack Slot Operand - This operand is used for loading and storing temporary
4042 // values on the stack where a match requires a value to
4043 // flow through memory.
4044 operand stackSlotI(sRegI reg) %{
4045 constraint(ALLOC_IN_RC(stack_slots));
4046 op_cost(100);
4047 //match(RegI);
4048 format %{ "[$reg]" %}
4049 interface(MEMORY_INTER) %{
4050 base(0xE); // R_SP
4051 index(0x0);
4052 scale(0x0);
4053 disp($reg); // Stack Offset
4054 %}
4055 %}
4056
4057 operand stackSlotP(sRegP reg) %{
4058 constraint(ALLOC_IN_RC(stack_slots));
4059 op_cost(100);
4060 //match(RegP);
4061 format %{ "[$reg]" %}
4062 interface(MEMORY_INTER) %{
4063 base(0xE); // R_SP
4064 index(0x0);
4065 scale(0x0);
4066 disp($reg); // Stack Offset
4067 %}
4068 %}
4069
4070 operand stackSlotF(sRegF reg) %{
4071 constraint(ALLOC_IN_RC(stack_slots));
4072 op_cost(100);
4073 //match(RegF);
4074 format %{ "[$reg]" %}
4075 interface(MEMORY_INTER) %{
4076 base(0xE); // R_SP
4077 index(0x0);
4078 scale(0x0);
4079 disp($reg); // Stack Offset
4080 %}
4081 %}
4082 operand stackSlotD(sRegD reg) %{
4083 constraint(ALLOC_IN_RC(stack_slots));
4084 op_cost(100);
4085 //match(RegD);
4086 format %{ "[$reg]" %}
4087 interface(MEMORY_INTER) %{
4088 base(0xE); // R_SP
4089 index(0x0);
4090 scale(0x0);
4091 disp($reg); // Stack Offset
4092 %}
4093 %}
4094 operand stackSlotL(sRegL reg) %{
4095 constraint(ALLOC_IN_RC(stack_slots));
4096 op_cost(100);
4097 //match(RegL);
4098 format %{ "[$reg]" %}
4099 interface(MEMORY_INTER) %{
4100 base(0xE); // R_SP
4101 index(0x0);
4102 scale(0x0);
4103 disp($reg); // Stack Offset
4104 %}
4105 %}
4106
4107 // Operands for expressing Control Flow
4108 // NOTE: Label is a predefined operand which should not be redefined in
4109 // the AD file. It is generically handled within the ADLC.
4110
4111 //----------Conditional Branch Operands----------------------------------------
4112 // Comparison Op - This is the operation of the comparison, and is limited to
4113 // the following set of codes:
4114 // L (<), LE (<=), G (>), GE (>=), E (==), NE (!=)
4115 //
4116 // Other attributes of the comparison, such as unsignedness, are specified
4117 // by the comparison instruction that sets a condition code flags register.
4118 // That result is represented by a flags operand whose subtype is appropriate
4119 // to the unsignedness (etc.) of the comparison.
4120 //
4121 // Later, the instruction which matches both the Comparison Op (a Bool) and
4122 // the flags (produced by the Cmp) specifies the coding of the comparison op
4123 // by matching a specific subtype of Bool operand below, such as cmpOpU.
4124
4125 operand cmpOp() %{
4126 match(Bool);
4127
4128 format %{ "" %}
4129 interface(COND_INTER) %{
4130 equal(0x1);
4131 not_equal(0x9);
4132 less(0x3);
4133 greater_equal(0xB);
4134 less_equal(0x2);
4135 greater(0xA);
4136 overflow(0x7);
4137 no_overflow(0xF);
4138 %}
4139 %}
4140
4141 // Comparison Op, unsigned
4142 operand cmpOpU() %{
4143 match(Bool);
4144 predicate(n->as_Bool()->_test._test != BoolTest::overflow &&
4145 n->as_Bool()->_test._test != BoolTest::no_overflow);
4146
4147 format %{ "u" %}
4148 interface(COND_INTER) %{
4149 equal(0x1);
4150 not_equal(0x9);
4151 less(0x5);
4152 greater_equal(0xD);
4153 less_equal(0x4);
4154 greater(0xC);
4155 overflow(0x7);
4156 no_overflow(0xF);
4157 %}
4158 %}
4159
4160 // Comparison Op, pointer (same as unsigned)
4161 operand cmpOpP() %{
4162 match(Bool);
4163 predicate(n->as_Bool()->_test._test != BoolTest::overflow &&
4164 n->as_Bool()->_test._test != BoolTest::no_overflow);
4165
4166 format %{ "p" %}
4167 interface(COND_INTER) %{
4168 equal(0x1);
4169 not_equal(0x9);
4170 less(0x5);
4171 greater_equal(0xD);
4172 less_equal(0x4);
4173 greater(0xC);
4174 overflow(0x7);
4175 no_overflow(0xF);
4176 %}
4177 %}
4178
4179 // Comparison Op, branch-register encoding
4180 operand cmpOp_reg() %{
4181 match(Bool);
4182 predicate(n->as_Bool()->_test._test != BoolTest::overflow &&
4183 n->as_Bool()->_test._test != BoolTest::no_overflow);
4184
4185 format %{ "" %}
4186 interface(COND_INTER) %{
4187 equal (0x1);
4188 not_equal (0x5);
4189 less (0x3);
4190 greater_equal(0x7);
4191 less_equal (0x2);
4192 greater (0x6);
4193 overflow(0x7); // not supported
4194 no_overflow(0xF); // not supported
4195 %}
4196 %}
4197
4198 // Comparison Code, floating, unordered same as less
4199 operand cmpOpF() %{
4200 match(Bool);
4201 predicate(n->as_Bool()->_test._test != BoolTest::overflow &&
4202 n->as_Bool()->_test._test != BoolTest::no_overflow);
4203
4204 format %{ "fl" %}
4205 interface(COND_INTER) %{
4206 equal(0x9);
4207 not_equal(0x1);
4208 less(0x3);
4209 greater_equal(0xB);
4210 less_equal(0xE);
4211 greater(0x6);
4212
4213 overflow(0x7); // not supported
4214 no_overflow(0xF); // not supported
4215 %}
4216 %}
4217
4218 // Used by long compare
4219 operand cmpOp_commute() %{
4220 match(Bool);
4221 predicate(n->as_Bool()->_test._test != BoolTest::overflow &&
4222 n->as_Bool()->_test._test != BoolTest::no_overflow);
4223
4224 format %{ "" %}
4225 interface(COND_INTER) %{
4226 equal(0x1);
4227 not_equal(0x9);
4228 less(0xA);
4229 greater_equal(0x2);
4230 less_equal(0xB);
4231 greater(0x3);
4232 overflow(0x7);
4233 no_overflow(0xF);
4234 %}
4235 %}
4236
4237 //----------OPERAND CLASSES----------------------------------------------------
4238 // Operand Classes are groups of operands that are used to simplify
4239 // instruction definitions by not requiring the AD writer to specify separate
4240 // instructions for every form of operand when the instruction accepts
4241 // multiple operand types with the same basic encoding and format. The classic
4242 // case of this is memory operands.
4243 opclass memory( indirect, indOffset13, indIndex );
4244 opclass indIndexMemory( indIndex );
4245
4246 //----------PIPELINE-----------------------------------------------------------
4247 pipeline %{
4248
4249 //----------ATTRIBUTES---------------------------------------------------------
4250 attributes %{
4251 fixed_size_instructions; // Fixed size instructions
4252 branch_has_delay_slot; // Branch has delay slot following
4253 max_instructions_per_bundle = 4; // Up to 4 instructions per bundle
4254 instruction_unit_size = 4; // An instruction is 4 bytes long
4255 instruction_fetch_unit_size = 16; // The processor fetches one line
4256 instruction_fetch_units = 1; // of 16 bytes
4257
4258 // List of nop instructions
4259 nops( Nop_A0, Nop_A1, Nop_MS, Nop_FA, Nop_BR );
4260 %}
4261
4262 //----------RESOURCES----------------------------------------------------------
4263 // Resources are the functional units available to the machine
4264 resources(A0, A1, MS, BR, FA, FM, IDIV, FDIV, IALU = A0 | A1);
4265
4266 //----------PIPELINE DESCRIPTION-----------------------------------------------
4267 // Pipeline Description specifies the stages in the machine's pipeline
4268
4269 pipe_desc(A, P, F, B, I, J, S, R, E, C, M, W, X, T, D);
4270
4271 //----------PIPELINE CLASSES---------------------------------------------------
4272 // Pipeline Classes describe the stages in which input and output are
4273 // referenced by the hardware pipeline.
4274
4275 // Integer ALU reg-reg operation
4276 pipe_class ialu_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
4277 single_instruction;
4278 dst : E(write);
4279 src1 : R(read);
4280 src2 : R(read);
4281 IALU : R;
4282 %}
4283
4284 // Integer ALU reg-reg long operation
4285 pipe_class ialu_reg_reg_2(iRegL dst, iRegL src1, iRegL src2) %{
4286 instruction_count(2);
4287 dst : E(write);
4288 src1 : R(read);
4289 src2 : R(read);
4290 IALU : R;
4291 IALU : R;
4292 %}
4293
4294 // Integer ALU reg-reg long dependent operation
4295 pipe_class ialu_reg_reg_2_dep(iRegL dst, iRegL src1, iRegL src2, flagsReg cr) %{
4296 instruction_count(1); multiple_bundles;
4297 dst : E(write);
4298 src1 : R(read);
4299 src2 : R(read);
4300 cr : E(write);
4301 IALU : R(2);
4302 %}
4303
4304 // Integer ALU reg-imm operaion
4305 pipe_class ialu_reg_imm(iRegI dst, iRegI src1, immI13 src2) %{
4306 single_instruction;
4307 dst : E(write);
4308 src1 : R(read);
4309 IALU : R;
4310 %}
4311
4312 // Integer ALU reg-reg operation with condition code
4313 pipe_class ialu_cc_reg_reg(iRegI dst, iRegI src1, iRegI src2, flagsReg cr) %{
4314 single_instruction;
4315 dst : E(write);
4316 cr : E(write);
4317 src1 : R(read);
4318 src2 : R(read);
4319 IALU : R;
4320 %}
4321
4322 // Integer ALU reg-imm operation with condition code
4323 pipe_class ialu_cc_reg_imm(iRegI dst, iRegI src1, immI13 src2, flagsReg cr) %{
4324 single_instruction;
4325 dst : E(write);
4326 cr : E(write);
4327 src1 : R(read);
4328 IALU : R;
4329 %}
4330
4331 // Integer ALU zero-reg operation
4332 pipe_class ialu_zero_reg(iRegI dst, immI0 zero, iRegI src2) %{
4333 single_instruction;
4334 dst : E(write);
4335 src2 : R(read);
4336 IALU : R;
4337 %}
4338
4339 // Integer ALU zero-reg operation with condition code only
4340 pipe_class ialu_cconly_zero_reg(flagsReg cr, iRegI src) %{
4341 single_instruction;
4342 cr : E(write);
4343 src : R(read);
4344 IALU : R;
4345 %}
4346
4347 // Integer ALU reg-reg operation with condition code only
4348 pipe_class ialu_cconly_reg_reg(flagsReg cr, iRegI src1, iRegI src2) %{
4349 single_instruction;
4350 cr : E(write);
4351 src1 : R(read);
4352 src2 : R(read);
4353 IALU : R;
4354 %}
4355
4356 // Integer ALU reg-imm operation with condition code only
4357 pipe_class ialu_cconly_reg_imm(flagsReg cr, iRegI src1, immI13 src2) %{
4358 single_instruction;
4359 cr : E(write);
4360 src1 : R(read);
4361 IALU : R;
4362 %}
4363
4364 // Integer ALU reg-reg-zero operation with condition code only
4365 pipe_class ialu_cconly_reg_reg_zero(flagsReg cr, iRegI src1, iRegI src2, immI0 zero) %{
4366 single_instruction;
4367 cr : E(write);
4368 src1 : R(read);
4369 src2 : R(read);
4370 IALU : R;
4371 %}
4372
4373 // Integer ALU reg-imm-zero operation with condition code only
4374 pipe_class ialu_cconly_reg_imm_zero(flagsReg cr, iRegI src1, immI13 src2, immI0 zero) %{
4375 single_instruction;
4376 cr : E(write);
4377 src1 : R(read);
4378 IALU : R;
4379 %}
4380
4381 // Integer ALU reg-reg operation with condition code, src1 modified
4382 pipe_class ialu_cc_rwreg_reg(flagsReg cr, iRegI src1, iRegI src2) %{
4383 single_instruction;
4384 cr : E(write);
4385 src1 : E(write);
4386 src1 : R(read);
4387 src2 : R(read);
4388 IALU : R;
4389 %}
4390
4391 // Integer ALU reg-imm operation with condition code, src1 modified
4392 pipe_class ialu_cc_rwreg_imm(flagsReg cr, iRegI src1, immI13 src2) %{
4393 single_instruction;
4394 cr : E(write);
4395 src1 : E(write);
4396 src1 : R(read);
4397 IALU : R;
4398 %}
4399
4400 pipe_class cmpL_reg(iRegI dst, iRegL src1, iRegL src2, flagsReg cr ) %{
4401 multiple_bundles;
4402 dst : E(write)+4;
4403 cr : E(write);
4404 src1 : R(read);
4405 src2 : R(read);
4406 IALU : R(3);
4407 BR : R(2);
4408 %}
4409
4410 // Integer ALU operation
4411 pipe_class ialu_none(iRegI dst) %{
4412 single_instruction;
4413 dst : E(write);
4414 IALU : R;
4415 %}
4416
4417 // Integer ALU reg operation
4418 pipe_class ialu_reg(iRegI dst, iRegI src) %{
4419 single_instruction; may_have_no_code;
4420 dst : E(write);
4421 src : R(read);
4422 IALU : R;
4423 %}
4424
4425 // Integer ALU reg conditional operation
4426 // This instruction has a 1 cycle stall, and cannot execute
4427 // in the same cycle as the instruction setting the condition
4428 // code. We kludge this by pretending to read the condition code
4429 // 1 cycle earlier, and by marking the functional units as busy
4430 // for 2 cycles with the result available 1 cycle later than
4431 // is really the case.
4432 pipe_class ialu_reg_flags( iRegI op2_out, iRegI op2_in, iRegI op1, flagsReg cr ) %{
4433 single_instruction;
4434 op2_out : C(write);
4435 op1 : R(read);
4436 cr : R(read); // This is really E, with a 1 cycle stall
4437 BR : R(2);
4438 MS : R(2);
4439 %}
4440
4441 #ifdef _LP64
4442 pipe_class ialu_clr_and_mover( iRegI dst, iRegP src ) %{
4443 instruction_count(1); multiple_bundles;
4444 dst : C(write)+1;
4445 src : R(read)+1;
4446 IALU : R(1);
4447 BR : E(2);
4448 MS : E(2);
4449 %}
4450 #endif
4451
4452 // Integer ALU reg operation
4453 pipe_class ialu_move_reg_L_to_I(iRegI dst, iRegL src) %{
4454 single_instruction; may_have_no_code;
4455 dst : E(write);
4456 src : R(read);
4457 IALU : R;
4458 %}
4459 pipe_class ialu_move_reg_I_to_L(iRegL dst, iRegI src) %{
4460 single_instruction; may_have_no_code;
4461 dst : E(write);
4462 src : R(read);
4463 IALU : R;
4464 %}
4465
4466 // Two integer ALU reg operations
4467 pipe_class ialu_reg_2(iRegL dst, iRegL src) %{
4468 instruction_count(2);
4469 dst : E(write);
4470 src : R(read);
4471 A0 : R;
4472 A1 : R;
4473 %}
4474
4475 // Two integer ALU reg operations
4476 pipe_class ialu_move_reg_L_to_L(iRegL dst, iRegL src) %{
4477 instruction_count(2); may_have_no_code;
4478 dst : E(write);
4479 src : R(read);
4480 A0 : R;
4481 A1 : R;
4482 %}
4483
4484 // Integer ALU imm operation
4485 pipe_class ialu_imm(iRegI dst, immI13 src) %{
4486 single_instruction;
4487 dst : E(write);
4488 IALU : R;
4489 %}
4490
4491 // Integer ALU reg-reg with carry operation
4492 pipe_class ialu_reg_reg_cy(iRegI dst, iRegI src1, iRegI src2, iRegI cy) %{
4493 single_instruction;
4494 dst : E(write);
4495 src1 : R(read);
4496 src2 : R(read);
4497 IALU : R;
4498 %}
4499
4500 // Integer ALU cc operation
4501 pipe_class ialu_cc(iRegI dst, flagsReg cc) %{
4502 single_instruction;
4503 dst : E(write);
4504 cc : R(read);
4505 IALU : R;
4506 %}
4507
4508 // Integer ALU cc / second IALU operation
4509 pipe_class ialu_reg_ialu( iRegI dst, iRegI src ) %{
4510 instruction_count(1); multiple_bundles;
4511 dst : E(write)+1;
4512 src : R(read);
4513 IALU : R;
4514 %}
4515
4516 // Integer ALU cc / second IALU operation
4517 pipe_class ialu_reg_reg_ialu( iRegI dst, iRegI p, iRegI q ) %{
4518 instruction_count(1); multiple_bundles;
4519 dst : E(write)+1;
4520 p : R(read);
4521 q : R(read);
4522 IALU : R;
4523 %}
4524
4525 // Integer ALU hi-lo-reg operation
4526 pipe_class ialu_hi_lo_reg(iRegI dst, immI src) %{
4527 instruction_count(1); multiple_bundles;
4528 dst : E(write)+1;
4529 IALU : R(2);
4530 %}
4531
4532 // Float ALU hi-lo-reg operation (with temp)
4533 pipe_class ialu_hi_lo_reg_temp(regF dst, immF src, g3RegP tmp) %{
4534 instruction_count(1); multiple_bundles;
4535 dst : E(write)+1;
4536 IALU : R(2);
4537 %}
4538
4539 // Long Constant
4540 pipe_class loadConL( iRegL dst, immL src ) %{
4541 instruction_count(2); multiple_bundles;
4542 dst : E(write)+1;
4543 IALU : R(2);
4544 IALU : R(2);
4545 %}
4546
4547 // Pointer Constant
4548 pipe_class loadConP( iRegP dst, immP src ) %{
4549 instruction_count(0); multiple_bundles;
4550 fixed_latency(6);
4551 %}
4552
4553 // Polling Address
4554 pipe_class loadConP_poll( iRegP dst, immP_poll src ) %{
4555 #ifdef _LP64
4556 instruction_count(0); multiple_bundles;
4557 fixed_latency(6);
4558 #else
4559 dst : E(write);
4560 IALU : R;
4561 #endif
4562 %}
4563
4564 // Long Constant small
4565 pipe_class loadConLlo( iRegL dst, immL src ) %{
4566 instruction_count(2);
4567 dst : E(write);
4568 IALU : R;
4569 IALU : R;
4570 %}
4571
4572 // [PHH] This is wrong for 64-bit. See LdImmF/D.
4573 pipe_class loadConFD(regF dst, immF src, g3RegP tmp) %{
4574 instruction_count(1); multiple_bundles;
4575 src : R(read);
4576 dst : M(write)+1;
4577 IALU : R;
4578 MS : E;
4579 %}
4580
4581 // Integer ALU nop operation
4582 pipe_class ialu_nop() %{
4583 single_instruction;
4584 IALU : R;
4585 %}
4586
4587 // Integer ALU nop operation
4588 pipe_class ialu_nop_A0() %{
4589 single_instruction;
4590 A0 : R;
4591 %}
4592
4593 // Integer ALU nop operation
4594 pipe_class ialu_nop_A1() %{
4595 single_instruction;
4596 A1 : R;
4597 %}
4598
4599 // Integer Multiply reg-reg operation
4600 pipe_class imul_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
4601 single_instruction;
4602 dst : E(write);
4603 src1 : R(read);
4604 src2 : R(read);
4605 MS : R(5);
4606 %}
4607
4608 // Integer Multiply reg-imm operation
4609 pipe_class imul_reg_imm(iRegI dst, iRegI src1, immI13 src2) %{
4610 single_instruction;
4611 dst : E(write);
4612 src1 : R(read);
4613 MS : R(5);
4614 %}
4615
4616 pipe_class mulL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
4617 single_instruction;
4618 dst : E(write)+4;
4619 src1 : R(read);
4620 src2 : R(read);
4621 MS : R(6);
4622 %}
4623
4624 pipe_class mulL_reg_imm(iRegL dst, iRegL src1, immL13 src2) %{
4625 single_instruction;
4626 dst : E(write)+4;
4627 src1 : R(read);
4628 MS : R(6);
4629 %}
4630
4631 // Integer Divide reg-reg
4632 pipe_class sdiv_reg_reg(iRegI dst, iRegI src1, iRegI src2, iRegI temp, flagsReg cr) %{
4633 instruction_count(1); multiple_bundles;
4634 dst : E(write);
4635 temp : E(write);
4636 src1 : R(read);
4637 src2 : R(read);
4638 temp : R(read);
4639 MS : R(38);
4640 %}
4641
4642 // Integer Divide reg-imm
4643 pipe_class sdiv_reg_imm(iRegI dst, iRegI src1, immI13 src2, iRegI temp, flagsReg cr) %{
4644 instruction_count(1); multiple_bundles;
4645 dst : E(write);
4646 temp : E(write);
4647 src1 : R(read);
4648 temp : R(read);
4649 MS : R(38);
4650 %}
4651
4652 // Long Divide
4653 pipe_class divL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
4654 dst : E(write)+71;
4655 src1 : R(read);
4656 src2 : R(read)+1;
4657 MS : R(70);
4658 %}
4659
4660 pipe_class divL_reg_imm(iRegL dst, iRegL src1, immL13 src2) %{
4661 dst : E(write)+71;
4662 src1 : R(read);
4663 MS : R(70);
4664 %}
4665
4666 // Floating Point Add Float
4667 pipe_class faddF_reg_reg(regF dst, regF src1, regF src2) %{
4668 single_instruction;
4669 dst : X(write);
4670 src1 : E(read);
4671 src2 : E(read);
4672 FA : R;
4673 %}
4674
4675 // Floating Point Add Double
4676 pipe_class faddD_reg_reg(regD dst, regD src1, regD src2) %{
4677 single_instruction;
4678 dst : X(write);
4679 src1 : E(read);
4680 src2 : E(read);
4681 FA : R;
4682 %}
4683
4684 // Floating Point Conditional Move based on integer flags
4685 pipe_class int_conditional_float_move (cmpOp cmp, flagsReg cr, regF dst, regF src) %{
4686 single_instruction;
4687 dst : X(write);
4688 src : E(read);
4689 cr : R(read);
4690 FA : R(2);
4691 BR : R(2);
4692 %}
4693
4694 // Floating Point Conditional Move based on integer flags
4695 pipe_class int_conditional_double_move (cmpOp cmp, flagsReg cr, regD dst, regD src) %{
4696 single_instruction;
4697 dst : X(write);
4698 src : E(read);
4699 cr : R(read);
4700 FA : R(2);
4701 BR : R(2);
4702 %}
4703
4704 // Floating Point Multiply Float
4705 pipe_class fmulF_reg_reg(regF dst, regF src1, regF src2) %{
4706 single_instruction;
4707 dst : X(write);
4708 src1 : E(read);
4709 src2 : E(read);
4710 FM : R;
4711 %}
4712
4713 // Floating Point Multiply Double
4714 pipe_class fmulD_reg_reg(regD dst, regD src1, regD src2) %{
4715 single_instruction;
4716 dst : X(write);
4717 src1 : E(read);
4718 src2 : E(read);
4719 FM : R;
4720 %}
4721
4722 // Floating Point Divide Float
4723 pipe_class fdivF_reg_reg(regF dst, regF src1, regF src2) %{
4724 single_instruction;
4725 dst : X(write);
4726 src1 : E(read);
4727 src2 : E(read);
4728 FM : R;
4729 FDIV : C(14);
4730 %}
4731
4732 // Floating Point Divide Double
4733 pipe_class fdivD_reg_reg(regD dst, regD src1, regD src2) %{
4734 single_instruction;
4735 dst : X(write);
4736 src1 : E(read);
4737 src2 : E(read);
4738 FM : R;
4739 FDIV : C(17);
4740 %}
4741
4742 // Floating Point Move/Negate/Abs Float
4743 pipe_class faddF_reg(regF dst, regF src) %{
4744 single_instruction;
4745 dst : W(write);
4746 src : E(read);
4747 FA : R(1);
4748 %}
4749
4750 // Floating Point Move/Negate/Abs Double
4751 pipe_class faddD_reg(regD dst, regD src) %{
4752 single_instruction;
4753 dst : W(write);
4754 src : E(read);
4755 FA : R;
4756 %}
4757
4758 // Floating Point Convert F->D
4759 pipe_class fcvtF2D(regD dst, regF src) %{
4760 single_instruction;
4761 dst : X(write);
4762 src : E(read);
4763 FA : R;
4764 %}
4765
4766 // Floating Point Convert I->D
4767 pipe_class fcvtI2D(regD dst, regF src) %{
4768 single_instruction;
4769 dst : X(write);
4770 src : E(read);
4771 FA : R;
4772 %}
4773
4774 // Floating Point Convert LHi->D
4775 pipe_class fcvtLHi2D(regD dst, regD src) %{
4776 single_instruction;
4777 dst : X(write);
4778 src : E(read);
4779 FA : R;
4780 %}
4781
4782 // Floating Point Convert L->D
4783 pipe_class fcvtL2D(regD dst, regF src) %{
4784 single_instruction;
4785 dst : X(write);
4786 src : E(read);
4787 FA : R;
4788 %}
4789
4790 // Floating Point Convert L->F
4791 pipe_class fcvtL2F(regD dst, regF src) %{
4792 single_instruction;
4793 dst : X(write);
4794 src : E(read);
4795 FA : R;
4796 %}
4797
4798 // Floating Point Convert D->F
4799 pipe_class fcvtD2F(regD dst, regF src) %{
4800 single_instruction;
4801 dst : X(write);
4802 src : E(read);
4803 FA : R;
4804 %}
4805
4806 // Floating Point Convert I->L
4807 pipe_class fcvtI2L(regD dst, regF src) %{
4808 single_instruction;
4809 dst : X(write);
4810 src : E(read);
4811 FA : R;
4812 %}
4813
4814 // Floating Point Convert D->F
4815 pipe_class fcvtD2I(regF dst, regD src, flagsReg cr) %{
4816 instruction_count(1); multiple_bundles;
4817 dst : X(write)+6;
4818 src : E(read);
4819 FA : R;
4820 %}
4821
4822 // Floating Point Convert D->L
4823 pipe_class fcvtD2L(regD dst, regD src, flagsReg cr) %{
4824 instruction_count(1); multiple_bundles;
4825 dst : X(write)+6;
4826 src : E(read);
4827 FA : R;
4828 %}
4829
4830 // Floating Point Convert F->I
4831 pipe_class fcvtF2I(regF dst, regF src, flagsReg cr) %{
4832 instruction_count(1); multiple_bundles;
4833 dst : X(write)+6;
4834 src : E(read);
4835 FA : R;
4836 %}
4837
4838 // Floating Point Convert F->L
4839 pipe_class fcvtF2L(regD dst, regF src, flagsReg cr) %{
4840 instruction_count(1); multiple_bundles;
4841 dst : X(write)+6;
4842 src : E(read);
4843 FA : R;
4844 %}
4845
4846 // Floating Point Convert I->F
4847 pipe_class fcvtI2F(regF dst, regF src) %{
4848 single_instruction;
4849 dst : X(write);
4850 src : E(read);
4851 FA : R;
4852 %}
4853
4854 // Floating Point Compare
4855 pipe_class faddF_fcc_reg_reg_zero(flagsRegF cr, regF src1, regF src2, immI0 zero) %{
4856 single_instruction;
4857 cr : X(write);
4858 src1 : E(read);
4859 src2 : E(read);
4860 FA : R;
4861 %}
4862
4863 // Floating Point Compare
4864 pipe_class faddD_fcc_reg_reg_zero(flagsRegF cr, regD src1, regD src2, immI0 zero) %{
4865 single_instruction;
4866 cr : X(write);
4867 src1 : E(read);
4868 src2 : E(read);
4869 FA : R;
4870 %}
4871
4872 // Floating Add Nop
4873 pipe_class fadd_nop() %{
4874 single_instruction;
4875 FA : R;
4876 %}
4877
4878 // Integer Store to Memory
4879 pipe_class istore_mem_reg(memory mem, iRegI src) %{
4880 single_instruction;
4881 mem : R(read);
4882 src : C(read);
4883 MS : R;
4884 %}
4885
4886 // Integer Store to Memory
4887 pipe_class istore_mem_spORreg(memory mem, sp_ptr_RegP src) %{
4888 single_instruction;
4889 mem : R(read);
4890 src : C(read);
4891 MS : R;
4892 %}
4893
4894 // Integer Store Zero to Memory
4895 pipe_class istore_mem_zero(memory mem, immI0 src) %{
4896 single_instruction;
4897 mem : R(read);
4898 MS : R;
4899 %}
4900
4901 // Special Stack Slot Store
4902 pipe_class istore_stk_reg(stackSlotI stkSlot, iRegI src) %{
4903 single_instruction;
4904 stkSlot : R(read);
4905 src : C(read);
4906 MS : R;
4907 %}
4908
4909 // Special Stack Slot Store
4910 pipe_class lstoreI_stk_reg(stackSlotL stkSlot, iRegI src) %{
4911 instruction_count(2); multiple_bundles;
4912 stkSlot : R(read);
4913 src : C(read);
4914 MS : R(2);
4915 %}
4916
4917 // Float Store
4918 pipe_class fstoreF_mem_reg(memory mem, RegF src) %{
4919 single_instruction;
4920 mem : R(read);
4921 src : C(read);
4922 MS : R;
4923 %}
4924
4925 // Float Store
4926 pipe_class fstoreF_mem_zero(memory mem, immF0 src) %{
4927 single_instruction;
4928 mem : R(read);
4929 MS : R;
4930 %}
4931
4932 // Double Store
4933 pipe_class fstoreD_mem_reg(memory mem, RegD src) %{
4934 instruction_count(1);
4935 mem : R(read);
4936 src : C(read);
4937 MS : R;
4938 %}
4939
4940 // Double Store
4941 pipe_class fstoreD_mem_zero(memory mem, immD0 src) %{
4942 single_instruction;
4943 mem : R(read);
4944 MS : R;
4945 %}
4946
4947 // Special Stack Slot Float Store
4948 pipe_class fstoreF_stk_reg(stackSlotI stkSlot, RegF src) %{
4949 single_instruction;
4950 stkSlot : R(read);
4951 src : C(read);
4952 MS : R;
4953 %}
4954
4955 // Special Stack Slot Double Store
4956 pipe_class fstoreD_stk_reg(stackSlotI stkSlot, RegD src) %{
4957 single_instruction;
4958 stkSlot : R(read);
4959 src : C(read);
4960 MS : R;
4961 %}
4962
4963 // Integer Load (when sign bit propagation not needed)
4964 pipe_class iload_mem(iRegI dst, memory mem) %{
4965 single_instruction;
4966 mem : R(read);
4967 dst : C(write);
4968 MS : R;
4969 %}
4970
4971 // Integer Load from stack operand
4972 pipe_class iload_stkD(iRegI dst, stackSlotD mem ) %{
4973 single_instruction;
4974 mem : R(read);
4975 dst : C(write);
4976 MS : R;
4977 %}
4978
4979 // Integer Load (when sign bit propagation or masking is needed)
4980 pipe_class iload_mask_mem(iRegI dst, memory mem) %{
4981 single_instruction;
4982 mem : R(read);
4983 dst : M(write);
4984 MS : R;
4985 %}
4986
4987 // Float Load
4988 pipe_class floadF_mem(regF dst, memory mem) %{
4989 single_instruction;
4990 mem : R(read);
4991 dst : M(write);
4992 MS : R;
4993 %}
4994
4995 // Float Load
4996 pipe_class floadD_mem(regD dst, memory mem) %{
4997 instruction_count(1); multiple_bundles; // Again, unaligned argument is only multiple case
4998 mem : R(read);
4999 dst : M(write);
5000 MS : R;
5001 %}
5002
5003 // Float Load
5004 pipe_class floadF_stk(regF dst, stackSlotI stkSlot) %{
5005 single_instruction;
5006 stkSlot : R(read);
5007 dst : M(write);
5008 MS : R;
5009 %}
5010
5011 // Float Load
5012 pipe_class floadD_stk(regD dst, stackSlotI stkSlot) %{
5013 single_instruction;
5014 stkSlot : R(read);
5015 dst : M(write);
5016 MS : R;
5017 %}
5018
5019 // Memory Nop
5020 pipe_class mem_nop() %{
5021 single_instruction;
5022 MS : R;
5023 %}
5024
5025 pipe_class sethi(iRegP dst, immI src) %{
5026 single_instruction;
5027 dst : E(write);
5028 IALU : R;
5029 %}
5030
5031 pipe_class loadPollP(iRegP poll) %{
5032 single_instruction;
5033 poll : R(read);
5034 MS : R;
5035 %}
5036
5037 pipe_class br(Universe br, label labl) %{
5038 single_instruction_with_delay_slot;
5039 BR : R;
5040 %}
5041
5042 pipe_class br_cc(Universe br, cmpOp cmp, flagsReg cr, label labl) %{
5043 single_instruction_with_delay_slot;
5044 cr : E(read);
5045 BR : R;
5046 %}
5047
5048 pipe_class br_reg(Universe br, cmpOp cmp, iRegI op1, label labl) %{
5049 single_instruction_with_delay_slot;
5050 op1 : E(read);
5051 BR : R;
5052 MS : R;
5053 %}
5054
5055 // Compare and branch
5056 pipe_class cmp_br_reg_reg(Universe br, cmpOp cmp, iRegI src1, iRegI src2, label labl, flagsReg cr) %{
5057 instruction_count(2); has_delay_slot;
5058 cr : E(write);
5059 src1 : R(read);
5060 src2 : R(read);
5061 IALU : R;
5062 BR : R;
5063 %}
5064
5065 // Compare and branch
5066 pipe_class cmp_br_reg_imm(Universe br, cmpOp cmp, iRegI src1, immI13 src2, label labl, flagsReg cr) %{
5067 instruction_count(2); has_delay_slot;
5068 cr : E(write);
5069 src1 : R(read);
5070 IALU : R;
5071 BR : R;
5072 %}
5073
5074 // Compare and branch using cbcond
5075 pipe_class cbcond_reg_reg(Universe br, cmpOp cmp, iRegI src1, iRegI src2, label labl) %{
5076 single_instruction;
5077 src1 : E(read);
5078 src2 : E(read);
5079 IALU : R;
5080 BR : R;
5081 %}
5082
5083 // Compare and branch using cbcond
5084 pipe_class cbcond_reg_imm(Universe br, cmpOp cmp, iRegI src1, immI5 src2, label labl) %{
5085 single_instruction;
5086 src1 : E(read);
5087 IALU : R;
5088 BR : R;
5089 %}
5090
5091 pipe_class br_fcc(Universe br, cmpOpF cc, flagsReg cr, label labl) %{
5092 single_instruction_with_delay_slot;
5093 cr : E(read);
5094 BR : R;
5095 %}
5096
5097 pipe_class br_nop() %{
5098 single_instruction;
5099 BR : R;
5100 %}
5101
5102 pipe_class simple_call(method meth) %{
5103 instruction_count(2); multiple_bundles; force_serialization;
5104 fixed_latency(100);
5105 BR : R(1);
5106 MS : R(1);
5107 A0 : R(1);
5108 %}
5109
5110 pipe_class compiled_call(method meth) %{
5111 instruction_count(1); multiple_bundles; force_serialization;
5112 fixed_latency(100);
5113 MS : R(1);
5114 %}
5115
5116 pipe_class call(method meth) %{
5117 instruction_count(0); multiple_bundles; force_serialization;
5118 fixed_latency(100);
5119 %}
5120
5121 pipe_class tail_call(Universe ignore, label labl) %{
5122 single_instruction; has_delay_slot;
5123 fixed_latency(100);
5124 BR : R(1);
5125 MS : R(1);
5126 %}
5127
5128 pipe_class ret(Universe ignore) %{
5129 single_instruction; has_delay_slot;
5130 BR : R(1);
5131 MS : R(1);
5132 %}
5133
5134 pipe_class ret_poll(g3RegP poll) %{
5135 instruction_count(3); has_delay_slot;
5136 poll : E(read);
5137 MS : R;
5138 %}
5139
5140 // The real do-nothing guy
5141 pipe_class empty( ) %{
5142 instruction_count(0);
5143 %}
5144
5145 pipe_class long_memory_op() %{
5146 instruction_count(0); multiple_bundles; force_serialization;
5147 fixed_latency(25);
5148 MS : R(1);
5149 %}
5150
5151 // Check-cast
5152 pipe_class partial_subtype_check_pipe(Universe ignore, iRegP array, iRegP match ) %{
5153 array : R(read);
5154 match : R(read);
5155 IALU : R(2);
5156 BR : R(2);
5157 MS : R;
5158 %}
5159
5160 // Convert FPU flags into +1,0,-1
5161 pipe_class floating_cmp( iRegI dst, regF src1, regF src2 ) %{
5162 src1 : E(read);
5163 src2 : E(read);
5164 dst : E(write);
5165 FA : R;
5166 MS : R(2);
5167 BR : R(2);
5168 %}
5169
5170 // Compare for p < q, and conditionally add y
5171 pipe_class cadd_cmpltmask( iRegI p, iRegI q, iRegI y ) %{
5172 p : E(read);
5173 q : E(read);
5174 y : E(read);
5175 IALU : R(3)
5176 %}
5177
5178 // Perform a compare, then move conditionally in a branch delay slot.
5179 pipe_class min_max( iRegI src2, iRegI srcdst ) %{
5180 src2 : E(read);
5181 srcdst : E(read);
5182 IALU : R;
5183 BR : R;
5184 %}
5185
5186 // Define the class for the Nop node
5187 define %{
5188 MachNop = ialu_nop;
5189 %}
5190
5191 %}
5192
5193 //----------INSTRUCTIONS-------------------------------------------------------
5194
5195 //------------Special Stack Slot instructions - no match rules-----------------
5196 instruct stkI_to_regF(regF dst, stackSlotI src) %{
5197 // No match rule to avoid chain rule match.
5198 effect(DEF dst, USE src);
5199 ins_cost(MEMORY_REF_COST);
5200 size(4);
5201 format %{ "LDF $src,$dst\t! stkI to regF" %}
5202 opcode(Assembler::ldf_op3);
5203 ins_encode(simple_form3_mem_reg(src, dst));
5204 ins_pipe(floadF_stk);
5205 %}
5206
5207 instruct stkL_to_regD(regD dst, stackSlotL src) %{
5208 // No match rule to avoid chain rule match.
5209 effect(DEF dst, USE src);
5210 ins_cost(MEMORY_REF_COST);
5211 size(4);
5212 format %{ "LDDF $src,$dst\t! stkL to regD" %}
5213 opcode(Assembler::lddf_op3);
5214 ins_encode(simple_form3_mem_reg(src, dst));
5215 ins_pipe(floadD_stk);
5216 %}
5217
5218 instruct regF_to_stkI(stackSlotI dst, regF src) %{
5219 // No match rule to avoid chain rule match.
5220 effect(DEF dst, USE src);
5221 ins_cost(MEMORY_REF_COST);
5222 size(4);
5223 format %{ "STF $src,$dst\t! regF to stkI" %}
5224 opcode(Assembler::stf_op3);
5225 ins_encode(simple_form3_mem_reg(dst, src));
5226 ins_pipe(fstoreF_stk_reg);
5227 %}
5228
5229 instruct regD_to_stkL(stackSlotL dst, regD src) %{
5230 // No match rule to avoid chain rule match.
5231 effect(DEF dst, USE src);
5232 ins_cost(MEMORY_REF_COST);
5233 size(4);
5234 format %{ "STDF $src,$dst\t! regD to stkL" %}
5235 opcode(Assembler::stdf_op3);
5236 ins_encode(simple_form3_mem_reg(dst, src));
5237 ins_pipe(fstoreD_stk_reg);
5238 %}
5239
5240 instruct regI_to_stkLHi(stackSlotL dst, iRegI src) %{
5241 effect(DEF dst, USE src);
5242 ins_cost(MEMORY_REF_COST*2);
5243 size(8);
5244 format %{ "STW $src,$dst.hi\t! long\n\t"
5245 "STW R_G0,$dst.lo" %}
5246 opcode(Assembler::stw_op3);
5247 ins_encode(simple_form3_mem_reg(dst, src), form3_mem_plus_4_reg(dst, R_G0));
5248 ins_pipe(lstoreI_stk_reg);
5249 %}
5250
5251 instruct regL_to_stkD(stackSlotD dst, iRegL src) %{
5252 // No match rule to avoid chain rule match.
5253 effect(DEF dst, USE src);
5254 ins_cost(MEMORY_REF_COST);
5255 size(4);
5256 format %{ "STX $src,$dst\t! regL to stkD" %}
5257 opcode(Assembler::stx_op3);
5258 ins_encode(simple_form3_mem_reg( dst, src ) );
5259 ins_pipe(istore_stk_reg);
5260 %}
5261
5262 //---------- Chain stack slots between similar types --------
5263
5264 // Load integer from stack slot
5265 instruct stkI_to_regI( iRegI dst, stackSlotI src ) %{
5266 match(Set dst src);
5267 ins_cost(MEMORY_REF_COST);
5268
5269 size(4);
5270 format %{ "LDUW $src,$dst\t!stk" %}
5271 opcode(Assembler::lduw_op3);
5272 ins_encode(simple_form3_mem_reg( src, dst ) );
5273 ins_pipe(iload_mem);
5274 %}
5275
5276 // Store integer to stack slot
5277 instruct regI_to_stkI( stackSlotI dst, iRegI src ) %{
5278 match(Set dst src);
5279 ins_cost(MEMORY_REF_COST);
5280
5281 size(4);
5282 format %{ "STW $src,$dst\t!stk" %}
5283 opcode(Assembler::stw_op3);
5284 ins_encode(simple_form3_mem_reg( dst, src ) );
5285 ins_pipe(istore_mem_reg);
5286 %}
5287
5288 // Load long from stack slot
5289 instruct stkL_to_regL( iRegL dst, stackSlotL src ) %{
5290 match(Set dst src);
5291
5292 ins_cost(MEMORY_REF_COST);
5293 size(4);
5294 format %{ "LDX $src,$dst\t! long" %}
5295 opcode(Assembler::ldx_op3);
5296 ins_encode(simple_form3_mem_reg( src, dst ) );
5297 ins_pipe(iload_mem);
5298 %}
5299
5300 // Store long to stack slot
5301 instruct regL_to_stkL(stackSlotL dst, iRegL src) %{
5302 match(Set dst src);
5303
5304 ins_cost(MEMORY_REF_COST);
5305 size(4);
5306 format %{ "STX $src,$dst\t! long" %}
5307 opcode(Assembler::stx_op3);
5308 ins_encode(simple_form3_mem_reg( dst, src ) );
5309 ins_pipe(istore_mem_reg);
5310 %}
5311
5312 #ifdef _LP64
5313 // Load pointer from stack slot, 64-bit encoding
5314 instruct stkP_to_regP( iRegP dst, stackSlotP src ) %{
5315 match(Set dst src);
5316 ins_cost(MEMORY_REF_COST);
5317 size(4);
5318 format %{ "LDX $src,$dst\t!ptr" %}
5319 opcode(Assembler::ldx_op3);
5320 ins_encode(simple_form3_mem_reg( src, dst ) );
5321 ins_pipe(iload_mem);
5322 %}
5323
5324 // Store pointer to stack slot
5325 instruct regP_to_stkP(stackSlotP dst, iRegP src) %{
5326 match(Set dst src);
5327 ins_cost(MEMORY_REF_COST);
5328 size(4);
5329 format %{ "STX $src,$dst\t!ptr" %}
5330 opcode(Assembler::stx_op3);
5331 ins_encode(simple_form3_mem_reg( dst, src ) );
5332 ins_pipe(istore_mem_reg);
5333 %}
5334 #else // _LP64
5335 // Load pointer from stack slot, 32-bit encoding
5336 instruct stkP_to_regP( iRegP dst, stackSlotP src ) %{
5337 match(Set dst src);
5338 ins_cost(MEMORY_REF_COST);
5339 format %{ "LDUW $src,$dst\t!ptr" %}
5340 opcode(Assembler::lduw_op3, Assembler::ldst_op);
5341 ins_encode(simple_form3_mem_reg( src, dst ) );
5342 ins_pipe(iload_mem);
5343 %}
5344
5345 // Store pointer to stack slot
5346 instruct regP_to_stkP(stackSlotP dst, iRegP src) %{
5347 match(Set dst src);
5348 ins_cost(MEMORY_REF_COST);
5349 format %{ "STW $src,$dst\t!ptr" %}
5350 opcode(Assembler::stw_op3, Assembler::ldst_op);
5351 ins_encode(simple_form3_mem_reg( dst, src ) );
5352 ins_pipe(istore_mem_reg);
5353 %}
5354 #endif // _LP64
5355
5356 //------------Special Nop instructions for bundling - no match rules-----------
5357 // Nop using the A0 functional unit
5358 instruct Nop_A0() %{
5359 ins_cost(0);
5360
5361 format %{ "NOP ! Alu Pipeline" %}
5362 opcode(Assembler::or_op3, Assembler::arith_op);
5363 ins_encode( form2_nop() );
5364 ins_pipe(ialu_nop_A0);
5365 %}
5366
5367 // Nop using the A1 functional unit
5368 instruct Nop_A1( ) %{
5369 ins_cost(0);
5370
5371 format %{ "NOP ! Alu Pipeline" %}
5372 opcode(Assembler::or_op3, Assembler::arith_op);
5373 ins_encode( form2_nop() );
5374 ins_pipe(ialu_nop_A1);
5375 %}
5376
5377 // Nop using the memory functional unit
5378 instruct Nop_MS( ) %{
5379 ins_cost(0);
5380
5381 format %{ "NOP ! Memory Pipeline" %}
5382 ins_encode( emit_mem_nop );
5383 ins_pipe(mem_nop);
5384 %}
5385
5386 // Nop using the floating add functional unit
5387 instruct Nop_FA( ) %{
5388 ins_cost(0);
5389
5390 format %{ "NOP ! Floating Add Pipeline" %}
5391 ins_encode( emit_fadd_nop );
5392 ins_pipe(fadd_nop);
5393 %}
5394
5395 // Nop using the branch functional unit
5396 instruct Nop_BR( ) %{
5397 ins_cost(0);
5398
5399 format %{ "NOP ! Branch Pipeline" %}
5400 ins_encode( emit_br_nop );
5401 ins_pipe(br_nop);
5402 %}
5403
5404 //----------Load/Store/Move Instructions---------------------------------------
5405 //----------Load Instructions--------------------------------------------------
5406 // Load Byte (8bit signed)
5407 instruct loadB(iRegI dst, memory mem) %{
5408 match(Set dst (LoadB mem));
5409 ins_cost(MEMORY_REF_COST);
5410
5411 size(4);
5412 format %{ "LDSB $mem,$dst\t! byte" %}
5413 ins_encode %{
5414 __ ldsb($mem$$Address, $dst$$Register);
5415 %}
5416 ins_pipe(iload_mask_mem);
5417 %}
5418
5419 // Load Byte (8bit signed) into a Long Register
5420 instruct loadB2L(iRegL dst, memory mem) %{
5421 match(Set dst (ConvI2L (LoadB mem)));
5422 ins_cost(MEMORY_REF_COST);
5423
5424 size(4);
5425 format %{ "LDSB $mem,$dst\t! byte -> long" %}
5426 ins_encode %{
5427 __ ldsb($mem$$Address, $dst$$Register);
5428 %}
5429 ins_pipe(iload_mask_mem);
5430 %}
5431
5432 // Load Unsigned Byte (8bit UNsigned) into an int reg
5433 instruct loadUB(iRegI dst, memory mem) %{
5434 match(Set dst (LoadUB mem));
5435 ins_cost(MEMORY_REF_COST);
5436
5437 size(4);
5438 format %{ "LDUB $mem,$dst\t! ubyte" %}
5439 ins_encode %{
5440 __ ldub($mem$$Address, $dst$$Register);
5441 %}
5442 ins_pipe(iload_mem);
5443 %}
5444
5445 // Load Unsigned Byte (8bit UNsigned) into a Long Register
5446 instruct loadUB2L(iRegL dst, memory mem) %{
5447 match(Set dst (ConvI2L (LoadUB mem)));
5448 ins_cost(MEMORY_REF_COST);
5449
5450 size(4);
5451 format %{ "LDUB $mem,$dst\t! ubyte -> long" %}
5452 ins_encode %{
5453 __ ldub($mem$$Address, $dst$$Register);
5454 %}
5455 ins_pipe(iload_mem);
5456 %}
5457
5458 // Load Unsigned Byte (8 bit UNsigned) with 32-bit mask into Long Register
5459 instruct loadUB2L_immI(iRegL dst, memory mem, immI mask) %{
5460 match(Set dst (ConvI2L (AndI (LoadUB mem) mask)));
5461 ins_cost(MEMORY_REF_COST + DEFAULT_COST);
5462
5463 size(2*4);
5464 format %{ "LDUB $mem,$dst\t# ubyte & 32-bit mask -> long\n\t"
5465 "AND $dst,right_n_bits($mask, 8),$dst" %}
5466 ins_encode %{
5467 __ ldub($mem$$Address, $dst$$Register);
5468 __ and3($dst$$Register, $mask$$constant & right_n_bits(8), $dst$$Register);
5469 %}
5470 ins_pipe(iload_mem);
5471 %}
5472
5473 // Load Short (16bit signed)
5474 instruct loadS(iRegI dst, memory mem) %{
5475 match(Set dst (LoadS mem));
5476 ins_cost(MEMORY_REF_COST);
5477
5478 size(4);
5479 format %{ "LDSH $mem,$dst\t! short" %}
5480 ins_encode %{
5481 __ ldsh($mem$$Address, $dst$$Register);
5482 %}
5483 ins_pipe(iload_mask_mem);
5484 %}
5485
5486 // Load Short (16 bit signed) to Byte (8 bit signed)
5487 instruct loadS2B(iRegI dst, indOffset13m7 mem, immI_24 twentyfour) %{
5488 match(Set dst (RShiftI (LShiftI (LoadS mem) twentyfour) twentyfour));
5489 ins_cost(MEMORY_REF_COST);
5490
5491 size(4);
5492
5493 format %{ "LDSB $mem+1,$dst\t! short -> byte" %}
5494 ins_encode %{
5495 __ ldsb($mem$$Address, $dst$$Register, 1);
5496 %}
5497 ins_pipe(iload_mask_mem);
5498 %}
5499
5500 // Load Short (16bit signed) into a Long Register
5501 instruct loadS2L(iRegL dst, memory mem) %{
5502 match(Set dst (ConvI2L (LoadS mem)));
5503 ins_cost(MEMORY_REF_COST);
5504
5505 size(4);
5506 format %{ "LDSH $mem,$dst\t! short -> long" %}
5507 ins_encode %{
5508 __ ldsh($mem$$Address, $dst$$Register);
5509 %}
5510 ins_pipe(iload_mask_mem);
5511 %}
5512
5513 // Load Unsigned Short/Char (16bit UNsigned)
5514 instruct loadUS(iRegI dst, memory mem) %{
5515 match(Set dst (LoadUS mem));
5516 ins_cost(MEMORY_REF_COST);
5517
5518 size(4);
5519 format %{ "LDUH $mem,$dst\t! ushort/char" %}
5520 ins_encode %{
5521 __ lduh($mem$$Address, $dst$$Register);
5522 %}
5523 ins_pipe(iload_mem);
5524 %}
5525
5526 // Load Unsigned Short/Char (16 bit UNsigned) to Byte (8 bit signed)
5527 instruct loadUS2B(iRegI dst, indOffset13m7 mem, immI_24 twentyfour) %{
5528 match(Set dst (RShiftI (LShiftI (LoadUS mem) twentyfour) twentyfour));
5529 ins_cost(MEMORY_REF_COST);
5530
5531 size(4);
5532 format %{ "LDSB $mem+1,$dst\t! ushort -> byte" %}
5533 ins_encode %{
5534 __ ldsb($mem$$Address, $dst$$Register, 1);
5535 %}
5536 ins_pipe(iload_mask_mem);
5537 %}
5538
5539 // Load Unsigned Short/Char (16bit UNsigned) into a Long Register
5540 instruct loadUS2L(iRegL dst, memory mem) %{
5541 match(Set dst (ConvI2L (LoadUS mem)));
5542 ins_cost(MEMORY_REF_COST);
5543
5544 size(4);
5545 format %{ "LDUH $mem,$dst\t! ushort/char -> long" %}
5546 ins_encode %{
5547 __ lduh($mem$$Address, $dst$$Register);
5548 %}
5549 ins_pipe(iload_mem);
5550 %}
5551
5552 // Load Unsigned Short/Char (16bit UNsigned) with mask 0xFF into a Long Register
5553 instruct loadUS2L_immI_255(iRegL dst, indOffset13m7 mem, immI_255 mask) %{
5554 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
5555 ins_cost(MEMORY_REF_COST);
5556
5557 size(4);
5558 format %{ "LDUB $mem+1,$dst\t! ushort/char & 0xFF -> long" %}
5559 ins_encode %{
5560 __ ldub($mem$$Address, $dst$$Register, 1); // LSB is index+1 on BE
5561 %}
5562 ins_pipe(iload_mem);
5563 %}
5564
5565 // Load Unsigned Short/Char (16bit UNsigned) with a 13-bit mask into a Long Register
5566 instruct loadUS2L_immI13(iRegL dst, memory mem, immI13 mask) %{
5567 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
5568 ins_cost(MEMORY_REF_COST + DEFAULT_COST);
5569
5570 size(2*4);
5571 format %{ "LDUH $mem,$dst\t! ushort/char & 13-bit mask -> long\n\t"
5572 "AND $dst,$mask,$dst" %}
5573 ins_encode %{
5574 Register Rdst = $dst$$Register;
5575 __ lduh($mem$$Address, Rdst);
5576 __ and3(Rdst, $mask$$constant, Rdst);
5577 %}
5578 ins_pipe(iload_mem);
5579 %}
5580
5581 // Load Unsigned Short/Char (16bit UNsigned) with a 32-bit mask into a Long Register
5582 instruct loadUS2L_immI(iRegL dst, memory mem, immI mask, iRegL tmp) %{
5583 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
5584 effect(TEMP dst, TEMP tmp);
5585 ins_cost(MEMORY_REF_COST + 2*DEFAULT_COST);
5586
5587 format %{ "LDUH $mem,$dst\t! ushort/char & 32-bit mask -> long\n\t"
5588 "SET right_n_bits($mask, 16),$tmp\n\t"
5589 "AND $dst,$tmp,$dst" %}
5590 ins_encode %{
5591 Register Rdst = $dst$$Register;
5592 Register Rtmp = $tmp$$Register;
5593 __ lduh($mem$$Address, Rdst);
5594 __ set($mask$$constant & right_n_bits(16), Rtmp);
5595 __ and3(Rdst, Rtmp, Rdst);
5596 %}
5597 ins_pipe(iload_mem);
5598 %}
5599
5600 // Load Integer
5601 instruct loadI(iRegI dst, memory mem) %{
5602 match(Set dst (LoadI mem));
5603 ins_cost(MEMORY_REF_COST);
5604
5605 size(4);
5606 format %{ "LDUW $mem,$dst\t! int" %}
5607 ins_encode %{
5608 __ lduw($mem$$Address, $dst$$Register);
5609 %}
5610 ins_pipe(iload_mem);
5611 %}
5612
5613 // Load Integer to Byte (8 bit signed)
5614 instruct loadI2B(iRegI dst, indOffset13m7 mem, immI_24 twentyfour) %{
5615 match(Set dst (RShiftI (LShiftI (LoadI mem) twentyfour) twentyfour));
5616 ins_cost(MEMORY_REF_COST);
5617
5618 size(4);
5619
5620 format %{ "LDSB $mem+3,$dst\t! int -> byte" %}
5621 ins_encode %{
5622 __ ldsb($mem$$Address, $dst$$Register, 3);
5623 %}
5624 ins_pipe(iload_mask_mem);
5625 %}
5626
5627 // Load Integer to Unsigned Byte (8 bit UNsigned)
5628 instruct loadI2UB(iRegI dst, indOffset13m7 mem, immI_255 mask) %{
5629 match(Set dst (AndI (LoadI mem) mask));
5630 ins_cost(MEMORY_REF_COST);
5631
5632 size(4);
5633
5634 format %{ "LDUB $mem+3,$dst\t! int -> ubyte" %}
5635 ins_encode %{
5636 __ ldub($mem$$Address, $dst$$Register, 3);
5637 %}
5638 ins_pipe(iload_mask_mem);
5639 %}
5640
5641 // Load Integer to Short (16 bit signed)
5642 instruct loadI2S(iRegI dst, indOffset13m7 mem, immI_16 sixteen) %{
5643 match(Set dst (RShiftI (LShiftI (LoadI mem) sixteen) sixteen));
5644 ins_cost(MEMORY_REF_COST);
5645
5646 size(4);
5647
5648 format %{ "LDSH $mem+2,$dst\t! int -> short" %}
5649 ins_encode %{
5650 __ ldsh($mem$$Address, $dst$$Register, 2);
5651 %}
5652 ins_pipe(iload_mask_mem);
5653 %}
5654
5655 // Load Integer to Unsigned Short (16 bit UNsigned)
5656 instruct loadI2US(iRegI dst, indOffset13m7 mem, immI_65535 mask) %{
5657 match(Set dst (AndI (LoadI mem) mask));
5658 ins_cost(MEMORY_REF_COST);
5659
5660 size(4);
5661
5662 format %{ "LDUH $mem+2,$dst\t! int -> ushort/char" %}
5663 ins_encode %{
5664 __ lduh($mem$$Address, $dst$$Register, 2);
5665 %}
5666 ins_pipe(iload_mask_mem);
5667 %}
5668
5669 // Load Integer into a Long Register
5670 instruct loadI2L(iRegL dst, memory mem) %{
5671 match(Set dst (ConvI2L (LoadI mem)));
5672 ins_cost(MEMORY_REF_COST);
5673
5674 size(4);
5675 format %{ "LDSW $mem,$dst\t! int -> long" %}
5676 ins_encode %{
5677 __ ldsw($mem$$Address, $dst$$Register);
5678 %}
5679 ins_pipe(iload_mask_mem);
5680 %}
5681
5682 // Load Integer with mask 0xFF into a Long Register
5683 instruct loadI2L_immI_255(iRegL dst, indOffset13m7 mem, immI_255 mask) %{
5684 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5685 ins_cost(MEMORY_REF_COST);
5686
5687 size(4);
5688 format %{ "LDUB $mem+3,$dst\t! int & 0xFF -> long" %}
5689 ins_encode %{
5690 __ ldub($mem$$Address, $dst$$Register, 3); // LSB is index+3 on BE
5691 %}
5692 ins_pipe(iload_mem);
5693 %}
5694
5695 // Load Integer with mask 0xFFFF into a Long Register
5696 instruct loadI2L_immI_65535(iRegL dst, indOffset13m7 mem, immI_65535 mask) %{
5697 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5698 ins_cost(MEMORY_REF_COST);
5699
5700 size(4);
5701 format %{ "LDUH $mem+2,$dst\t! int & 0xFFFF -> long" %}
5702 ins_encode %{
5703 __ lduh($mem$$Address, $dst$$Register, 2); // LSW is index+2 on BE
5704 %}
5705 ins_pipe(iload_mem);
5706 %}
5707
5708 // Load Integer with a 12-bit mask into a Long Register
5709 instruct loadI2L_immU12(iRegL dst, memory mem, immU12 mask) %{
5710 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5711 ins_cost(MEMORY_REF_COST + DEFAULT_COST);
5712
5713 size(2*4);
5714 format %{ "LDUW $mem,$dst\t! int & 12-bit mask -> long\n\t"
5715 "AND $dst,$mask,$dst" %}
5716 ins_encode %{
5717 Register Rdst = $dst$$Register;
5718 __ lduw($mem$$Address, Rdst);
5719 __ and3(Rdst, $mask$$constant, Rdst);
5720 %}
5721 ins_pipe(iload_mem);
5722 %}
5723
5724 // Load Integer with a 31-bit mask into a Long Register
5725 instruct loadI2L_immU31(iRegL dst, memory mem, immU31 mask, iRegL tmp) %{
5726 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5727 effect(TEMP dst, TEMP tmp);
5728 ins_cost(MEMORY_REF_COST + 2*DEFAULT_COST);
5729
5730 format %{ "LDUW $mem,$dst\t! int & 31-bit mask -> long\n\t"
5731 "SET $mask,$tmp\n\t"
5732 "AND $dst,$tmp,$dst" %}
5733 ins_encode %{
5734 Register Rdst = $dst$$Register;
5735 Register Rtmp = $tmp$$Register;
5736 __ lduw($mem$$Address, Rdst);
5737 __ set($mask$$constant, Rtmp);
5738 __ and3(Rdst, Rtmp, Rdst);
5739 %}
5740 ins_pipe(iload_mem);
5741 %}
5742
5743 // Load Unsigned Integer into a Long Register
5744 instruct loadUI2L(iRegL dst, memory mem, immL_32bits mask) %{
5745 match(Set dst (AndL (ConvI2L (LoadI mem)) mask));
5746 ins_cost(MEMORY_REF_COST);
5747
5748 size(4);
5749 format %{ "LDUW $mem,$dst\t! uint -> long" %}
5750 ins_encode %{
5751 __ lduw($mem$$Address, $dst$$Register);
5752 %}
5753 ins_pipe(iload_mem);
5754 %}
5755
5756 // Load Long - aligned
5757 instruct loadL(iRegL dst, memory mem ) %{
5758 match(Set dst (LoadL mem));
5759 ins_cost(MEMORY_REF_COST);
5760
5761 size(4);
5762 format %{ "LDX $mem,$dst\t! long" %}
5763 ins_encode %{
5764 __ ldx($mem$$Address, $dst$$Register);
5765 %}
5766 ins_pipe(iload_mem);
5767 %}
5768
5769 // Load Long - UNaligned
5770 instruct loadL_unaligned(iRegL dst, memory mem, o7RegI tmp) %{
5771 match(Set dst (LoadL_unaligned mem));
5772 effect(KILL tmp);
5773 ins_cost(MEMORY_REF_COST*2+DEFAULT_COST);
5774 size(16);
5775 format %{ "LDUW $mem+4,R_O7\t! misaligned long\n"
5776 "\tLDUW $mem ,$dst\n"
5777 "\tSLLX #32, $dst, $dst\n"
5778 "\tOR $dst, R_O7, $dst" %}
5779 opcode(Assembler::lduw_op3);
5780 ins_encode(form3_mem_reg_long_unaligned_marshal( mem, dst ));
5781 ins_pipe(iload_mem);
5782 %}
5783
5784 // Load Range
5785 instruct loadRange(iRegI dst, memory mem) %{
5786 match(Set dst (LoadRange mem));
5787 ins_cost(MEMORY_REF_COST);
5788
5789 size(4);
5790 format %{ "LDUW $mem,$dst\t! range" %}
5791 opcode(Assembler::lduw_op3);
5792 ins_encode(simple_form3_mem_reg( mem, dst ) );
5793 ins_pipe(iload_mem);
5794 %}
5795
5796 // Load Integer into %f register (for fitos/fitod)
5797 instruct loadI_freg(regF dst, memory mem) %{
5798 match(Set dst (LoadI mem));
5799 ins_cost(MEMORY_REF_COST);
5800 size(4);
5801
5802 format %{ "LDF $mem,$dst\t! for fitos/fitod" %}
5803 opcode(Assembler::ldf_op3);
5804 ins_encode(simple_form3_mem_reg( mem, dst ) );
5805 ins_pipe(floadF_mem);
5806 %}
5807
5808 // Load Pointer
5809 instruct loadP(iRegP dst, memory mem) %{
5810 match(Set dst (LoadP mem));
5811 ins_cost(MEMORY_REF_COST);
5812 size(4);
5813
5814 #ifndef _LP64
5815 format %{ "LDUW $mem,$dst\t! ptr" %}
5816 ins_encode %{
5817 __ lduw($mem$$Address, $dst$$Register);
5818 %}
5819 #else
5820 format %{ "LDX $mem,$dst\t! ptr" %}
5821 ins_encode %{
5822 __ ldx($mem$$Address, $dst$$Register);
5823 %}
5824 #endif
5825 ins_pipe(iload_mem);
5826 %}
5827
5828 // Load Compressed Pointer
5829 instruct loadN(iRegN dst, memory mem) %{
5830 match(Set dst (LoadN mem));
5831 ins_cost(MEMORY_REF_COST);
5832 size(4);
5833
5834 format %{ "LDUW $mem,$dst\t! compressed ptr" %}
5835 ins_encode %{
5836 __ lduw($mem$$Address, $dst$$Register);
5837 %}
5838 ins_pipe(iload_mem);
5839 %}
5840
5841 // Load Klass Pointer
5842 instruct loadKlass(iRegP dst, memory mem) %{
5843 match(Set dst (LoadKlass mem));
5844 ins_cost(MEMORY_REF_COST);
5845 size(4);
5846
5847 #ifndef _LP64
5848 format %{ "LDUW $mem,$dst\t! klass ptr" %}
5849 ins_encode %{
5850 __ lduw($mem$$Address, $dst$$Register);
5851 %}
5852 #else
5853 format %{ "LDX $mem,$dst\t! klass ptr" %}
5854 ins_encode %{
5855 __ ldx($mem$$Address, $dst$$Register);
5856 %}
5857 #endif
5858 ins_pipe(iload_mem);
5859 %}
5860
5861 // Load narrow Klass Pointer
5862 instruct loadNKlass(iRegN dst, memory mem) %{
5863 match(Set dst (LoadNKlass mem));
5864 ins_cost(MEMORY_REF_COST);
5865 size(4);
5866
5867 format %{ "LDUW $mem,$dst\t! compressed klass ptr" %}
5868 ins_encode %{
5869 __ lduw($mem$$Address, $dst$$Register);
5870 %}
5871 ins_pipe(iload_mem);
5872 %}
5873
5874 // Load Double
5875 instruct loadD(regD dst, memory mem) %{
5876 match(Set dst (LoadD mem));
5877 ins_cost(MEMORY_REF_COST);
5878
5879 size(4);
5880 format %{ "LDDF $mem,$dst" %}
5881 opcode(Assembler::lddf_op3);
5882 ins_encode(simple_form3_mem_reg( mem, dst ) );
5883 ins_pipe(floadD_mem);
5884 %}
5885
5886 // Load Double - UNaligned
5887 instruct loadD_unaligned(regD_low dst, memory mem ) %{
5888 match(Set dst (LoadD_unaligned mem));
5889 ins_cost(MEMORY_REF_COST*2+DEFAULT_COST);
5890 size(8);
5891 format %{ "LDF $mem ,$dst.hi\t! misaligned double\n"
5892 "\tLDF $mem+4,$dst.lo\t!" %}
5893 opcode(Assembler::ldf_op3);
5894 ins_encode( form3_mem_reg_double_unaligned( mem, dst ));
5895 ins_pipe(iload_mem);
5896 %}
5897
5898 // Load Float
5899 instruct loadF(regF dst, memory mem) %{
5900 match(Set dst (LoadF mem));
5901 ins_cost(MEMORY_REF_COST);
5902
5903 size(4);
5904 format %{ "LDF $mem,$dst" %}
5905 opcode(Assembler::ldf_op3);
5906 ins_encode(simple_form3_mem_reg( mem, dst ) );
5907 ins_pipe(floadF_mem);
5908 %}
5909
5910 // Load Constant
5911 instruct loadConI( iRegI dst, immI src ) %{
5912 match(Set dst src);
5913 ins_cost(DEFAULT_COST * 3/2);
5914 format %{ "SET $src,$dst" %}
5915 ins_encode( Set32(src, dst) );
5916 ins_pipe(ialu_hi_lo_reg);
5917 %}
5918
5919 instruct loadConI13( iRegI dst, immI13 src ) %{
5920 match(Set dst src);
5921
5922 size(4);
5923 format %{ "MOV $src,$dst" %}
5924 ins_encode( Set13( src, dst ) );
5925 ins_pipe(ialu_imm);
5926 %}
5927
5928 #ifndef _LP64
5929 instruct loadConP(iRegP dst, immP con) %{
5930 match(Set dst con);
5931 ins_cost(DEFAULT_COST * 3/2);
5932 format %{ "SET $con,$dst\t!ptr" %}
5933 ins_encode %{
5934 relocInfo::relocType constant_reloc = _opnds[1]->constant_reloc();
5935 intptr_t val = $con$$constant;
5936 if (constant_reloc == relocInfo::oop_type) {
5937 __ set_oop_constant((jobject) val, $dst$$Register);
5938 } else if (constant_reloc == relocInfo::metadata_type) {
5939 __ set_metadata_constant((Metadata*)val, $dst$$Register);
5940 } else { // non-oop pointers, e.g. card mark base, heap top
5941 assert(constant_reloc == relocInfo::none, "unexpected reloc type");
5942 __ set(val, $dst$$Register);
5943 }
5944 %}
5945 ins_pipe(loadConP);
5946 %}
5947 #else
5948 instruct loadConP_set(iRegP dst, immP_set con) %{
5949 match(Set dst con);
5950 ins_cost(DEFAULT_COST * 3/2);
5951 format %{ "SET $con,$dst\t! ptr" %}
5952 ins_encode %{
5953 relocInfo::relocType constant_reloc = _opnds[1]->constant_reloc();
5954 intptr_t val = $con$$constant;
5955 if (constant_reloc == relocInfo::oop_type) {
5956 __ set_oop_constant((jobject) val, $dst$$Register);
5957 } else if (constant_reloc == relocInfo::metadata_type) {
5958 __ set_metadata_constant((Metadata*)val, $dst$$Register);
5959 } else { // non-oop pointers, e.g. card mark base, heap top
5960 assert(constant_reloc == relocInfo::none, "unexpected reloc type");
5961 __ set(val, $dst$$Register);
5962 }
5963 %}
5964 ins_pipe(loadConP);
5965 %}
5966
5967 instruct loadConP_load(iRegP dst, immP_load con) %{
5968 match(Set dst con);
5969 ins_cost(MEMORY_REF_COST);
5970 format %{ "LD [$constanttablebase + $constantoffset],$dst\t! load from constant table: ptr=$con" %}
5971 ins_encode %{
5972 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset($con), $dst$$Register);
5973 __ ld_ptr($constanttablebase, con_offset, $dst$$Register);
5974 %}
5975 ins_pipe(loadConP);
5976 %}
5977
5978 instruct loadConP_no_oop_cheap(iRegP dst, immP_no_oop_cheap con) %{
5979 match(Set dst con);
5980 ins_cost(DEFAULT_COST * 3/2);
5981 format %{ "SET $con,$dst\t! non-oop ptr" %}
5982 ins_encode %{
5983 if (_opnds[1]->constant_reloc() == relocInfo::metadata_type) {
5984 __ set_metadata_constant((Metadata*)$con$$constant, $dst$$Register);
5985 } else {
5986 __ set($con$$constant, $dst$$Register);
5987 }
5988 %}
5989 ins_pipe(loadConP);
5990 %}
5991 #endif // _LP64
5992
5993 instruct loadConP0(iRegP dst, immP0 src) %{
5994 match(Set dst src);
5995
5996 size(4);
5997 format %{ "CLR $dst\t!ptr" %}
5998 ins_encode %{
5999 __ clr($dst$$Register);
6000 %}
6001 ins_pipe(ialu_imm);
6002 %}
6003
6004 instruct loadConP_poll(iRegP dst, immP_poll src) %{
6005 match(Set dst src);
6006 ins_cost(DEFAULT_COST);
6007 format %{ "SET $src,$dst\t!ptr" %}
6008 ins_encode %{
6009 AddressLiteral polling_page(os::get_polling_page());
6010 __ sethi(polling_page, reg_to_register_object($dst$$reg));
6011 %}
6012 ins_pipe(loadConP_poll);
6013 %}
6014
6015 instruct loadConN0(iRegN dst, immN0 src) %{
6016 match(Set dst src);
6017
6018 size(4);
6019 format %{ "CLR $dst\t! compressed NULL ptr" %}
6020 ins_encode %{
6021 __ clr($dst$$Register);
6022 %}
6023 ins_pipe(ialu_imm);
6024 %}
6025
6026 instruct loadConN(iRegN dst, immN src) %{
6027 match(Set dst src);
6028 ins_cost(DEFAULT_COST * 3/2);
6029 format %{ "SET $src,$dst\t! compressed ptr" %}
6030 ins_encode %{
6031 Register dst = $dst$$Register;
6032 __ set_narrow_oop((jobject)$src$$constant, dst);
6033 %}
6034 ins_pipe(ialu_hi_lo_reg);
6035 %}
6036
6037 instruct loadConNKlass(iRegN dst, immNKlass src) %{
6038 match(Set dst src);
6039 ins_cost(DEFAULT_COST * 3/2);
6040 format %{ "SET $src,$dst\t! compressed klass ptr" %}
6041 ins_encode %{
6042 Register dst = $dst$$Register;
6043 __ set_narrow_klass((Klass*)$src$$constant, dst);
6044 %}
6045 ins_pipe(ialu_hi_lo_reg);
6046 %}
6047
6048 // Materialize long value (predicated by immL_cheap).
6049 instruct loadConL_set64(iRegL dst, immL_cheap con, o7RegL tmp) %{
6050 match(Set dst con);
6051 effect(KILL tmp);
6052 ins_cost(DEFAULT_COST * 3);
6053 format %{ "SET64 $con,$dst KILL $tmp\t! cheap long" %}
6054 ins_encode %{
6055 __ set64($con$$constant, $dst$$Register, $tmp$$Register);
6056 %}
6057 ins_pipe(loadConL);
6058 %}
6059
6060 // Load long value from constant table (predicated by immL_expensive).
6061 instruct loadConL_ldx(iRegL dst, immL_expensive con) %{
6062 match(Set dst con);
6063 ins_cost(MEMORY_REF_COST);
6064 format %{ "LDX [$constanttablebase + $constantoffset],$dst\t! load from constant table: long=$con" %}
6065 ins_encode %{
6066 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset($con), $dst$$Register);
6067 __ ldx($constanttablebase, con_offset, $dst$$Register);
6068 %}
6069 ins_pipe(loadConL);
6070 %}
6071
6072 instruct loadConL0( iRegL dst, immL0 src ) %{
6073 match(Set dst src);
6074 ins_cost(DEFAULT_COST);
6075 size(4);
6076 format %{ "CLR $dst\t! long" %}
6077 ins_encode( Set13( src, dst ) );
6078 ins_pipe(ialu_imm);
6079 %}
6080
6081 instruct loadConL13( iRegL dst, immL13 src ) %{
6082 match(Set dst src);
6083 ins_cost(DEFAULT_COST * 2);
6084
6085 size(4);
6086 format %{ "MOV $src,$dst\t! long" %}
6087 ins_encode( Set13( src, dst ) );
6088 ins_pipe(ialu_imm);
6089 %}
6090
6091 instruct loadConF(regF dst, immF con, o7RegI tmp) %{
6092 match(Set dst con);
6093 effect(KILL tmp);
6094 format %{ "LDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: float=$con" %}
6095 ins_encode %{
6096 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset($con), $tmp$$Register);
6097 __ ldf(FloatRegisterImpl::S, $constanttablebase, con_offset, $dst$$FloatRegister);
6098 %}
6099 ins_pipe(loadConFD);
6100 %}
6101
6102 instruct loadConD(regD dst, immD con, o7RegI tmp) %{
6103 match(Set dst con);
6104 effect(KILL tmp);
6105 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: double=$con" %}
6106 ins_encode %{
6107 // XXX This is a quick fix for 6833573.
6108 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset($con), $dst$$FloatRegister);
6109 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset($con), $tmp$$Register);
6110 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg));
6111 %}
6112 ins_pipe(loadConFD);
6113 %}
6114
6115 // Prefetch instructions for allocation.
6116 // Must be safe to execute with invalid address (cannot fault).
6117
6118 instruct prefetchAlloc( memory mem ) %{
6119 predicate(AllocatePrefetchInstr == 0);
6120 match( PrefetchAllocation mem );
6121 ins_cost(MEMORY_REF_COST);
6122 size(4);
6123
6124 format %{ "PREFETCH $mem,2\t! Prefetch allocation" %}
6125 opcode(Assembler::prefetch_op3);
6126 ins_encode( form3_mem_prefetch_write( mem ) );
6127 ins_pipe(iload_mem);
6128 %}
6129
6130 // Use BIS instruction to prefetch for allocation.
6131 // Could fault, need space at the end of TLAB.
6132 instruct prefetchAlloc_bis( iRegP dst ) %{
6133 predicate(AllocatePrefetchInstr == 1);
6134 match( PrefetchAllocation dst );
6135 ins_cost(MEMORY_REF_COST);
6136 size(4);
6137
6138 format %{ "STXA [$dst]\t! // Prefetch allocation using BIS" %}
6139 ins_encode %{
6140 __ stxa(G0, $dst$$Register, G0, Assembler::ASI_ST_BLKINIT_PRIMARY);
6141 %}
6142 ins_pipe(istore_mem_reg);
6143 %}
6144
6145 // Next code is used for finding next cache line address to prefetch.
6146 #ifndef _LP64
6147 instruct cacheLineAdr( iRegP dst, iRegP src, immI13 mask ) %{
6148 match(Set dst (CastX2P (AndI (CastP2X src) mask)));
6149 ins_cost(DEFAULT_COST);
6150 size(4);
6151
6152 format %{ "AND $src,$mask,$dst\t! next cache line address" %}
6153 ins_encode %{
6154 __ and3($src$$Register, $mask$$constant, $dst$$Register);
6155 %}
6156 ins_pipe(ialu_reg_imm);
6157 %}
6158 #else
6159 instruct cacheLineAdr( iRegP dst, iRegP src, immL13 mask ) %{
6160 match(Set dst (CastX2P (AndL (CastP2X src) mask)));
6161 ins_cost(DEFAULT_COST);
6162 size(4);
6163
6164 format %{ "AND $src,$mask,$dst\t! next cache line address" %}
6165 ins_encode %{
6166 __ and3($src$$Register, $mask$$constant, $dst$$Register);
6167 %}
6168 ins_pipe(ialu_reg_imm);
6169 %}
6170 #endif
6171
6172 //----------Store Instructions-------------------------------------------------
6173 // Store Byte
6174 instruct storeB(memory mem, iRegI src) %{
6175 match(Set mem (StoreB mem src));
6176 ins_cost(MEMORY_REF_COST);
6177
6178 size(4);
6179 format %{ "STB $src,$mem\t! byte" %}
6180 opcode(Assembler::stb_op3);
6181 ins_encode(simple_form3_mem_reg( mem, src ) );
6182 ins_pipe(istore_mem_reg);
6183 %}
6184
6185 instruct storeB0(memory mem, immI0 src) %{
6186 match(Set mem (StoreB mem src));
6187 ins_cost(MEMORY_REF_COST);
6188
6189 size(4);
6190 format %{ "STB $src,$mem\t! byte" %}
6191 opcode(Assembler::stb_op3);
6192 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6193 ins_pipe(istore_mem_zero);
6194 %}
6195
6196 instruct storeCM0(memory mem, immI0 src) %{
6197 match(Set mem (StoreCM mem src));
6198 ins_cost(MEMORY_REF_COST);
6199
6200 size(4);
6201 format %{ "STB $src,$mem\t! CMS card-mark byte 0" %}
6202 opcode(Assembler::stb_op3);
6203 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6204 ins_pipe(istore_mem_zero);
6205 %}
6206
6207 // Store Char/Short
6208 instruct storeC(memory mem, iRegI src) %{
6209 match(Set mem (StoreC mem src));
6210 ins_cost(MEMORY_REF_COST);
6211
6212 size(4);
6213 format %{ "STH $src,$mem\t! short" %}
6214 opcode(Assembler::sth_op3);
6215 ins_encode(simple_form3_mem_reg( mem, src ) );
6216 ins_pipe(istore_mem_reg);
6217 %}
6218
6219 instruct storeC0(memory mem, immI0 src) %{
6220 match(Set mem (StoreC mem src));
6221 ins_cost(MEMORY_REF_COST);
6222
6223 size(4);
6224 format %{ "STH $src,$mem\t! short" %}
6225 opcode(Assembler::sth_op3);
6226 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6227 ins_pipe(istore_mem_zero);
6228 %}
6229
6230 // Store Integer
6231 instruct storeI(memory mem, iRegI src) %{
6232 match(Set mem (StoreI mem src));
6233 ins_cost(MEMORY_REF_COST);
6234
6235 size(4);
6236 format %{ "STW $src,$mem" %}
6237 opcode(Assembler::stw_op3);
6238 ins_encode(simple_form3_mem_reg( mem, src ) );
6239 ins_pipe(istore_mem_reg);
6240 %}
6241
6242 // Store Long
6243 instruct storeL(memory mem, iRegL src) %{
6244 match(Set mem (StoreL mem src));
6245 ins_cost(MEMORY_REF_COST);
6246 size(4);
6247 format %{ "STX $src,$mem\t! long" %}
6248 opcode(Assembler::stx_op3);
6249 ins_encode(simple_form3_mem_reg( mem, src ) );
6250 ins_pipe(istore_mem_reg);
6251 %}
6252
6253 instruct storeI0(memory mem, immI0 src) %{
6254 match(Set mem (StoreI mem src));
6255 ins_cost(MEMORY_REF_COST);
6256
6257 size(4);
6258 format %{ "STW $src,$mem" %}
6259 opcode(Assembler::stw_op3);
6260 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6261 ins_pipe(istore_mem_zero);
6262 %}
6263
6264 instruct storeL0(memory mem, immL0 src) %{
6265 match(Set mem (StoreL mem src));
6266 ins_cost(MEMORY_REF_COST);
6267
6268 size(4);
6269 format %{ "STX $src,$mem" %}
6270 opcode(Assembler::stx_op3);
6271 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6272 ins_pipe(istore_mem_zero);
6273 %}
6274
6275 // Store Integer from float register (used after fstoi)
6276 instruct storeI_Freg(memory mem, regF src) %{
6277 match(Set mem (StoreI mem src));
6278 ins_cost(MEMORY_REF_COST);
6279
6280 size(4);
6281 format %{ "STF $src,$mem\t! after fstoi/fdtoi" %}
6282 opcode(Assembler::stf_op3);
6283 ins_encode(simple_form3_mem_reg( mem, src ) );
6284 ins_pipe(fstoreF_mem_reg);
6285 %}
6286
6287 // Store Pointer
6288 instruct storeP(memory dst, sp_ptr_RegP src) %{
6289 match(Set dst (StoreP dst src));
6290 ins_cost(MEMORY_REF_COST);
6291 size(4);
6292
6293 #ifndef _LP64
6294 format %{ "STW $src,$dst\t! ptr" %}
6295 opcode(Assembler::stw_op3, 0, REGP_OP);
6296 #else
6297 format %{ "STX $src,$dst\t! ptr" %}
6298 opcode(Assembler::stx_op3, 0, REGP_OP);
6299 #endif
6300 ins_encode( form3_mem_reg( dst, src ) );
6301 ins_pipe(istore_mem_spORreg);
6302 %}
6303
6304 instruct storeP0(memory dst, immP0 src) %{
6305 match(Set dst (StoreP dst src));
6306 ins_cost(MEMORY_REF_COST);
6307 size(4);
6308
6309 #ifndef _LP64
6310 format %{ "STW $src,$dst\t! ptr" %}
6311 opcode(Assembler::stw_op3, 0, REGP_OP);
6312 #else
6313 format %{ "STX $src,$dst\t! ptr" %}
6314 opcode(Assembler::stx_op3, 0, REGP_OP);
6315 #endif
6316 ins_encode( form3_mem_reg( dst, R_G0 ) );
6317 ins_pipe(istore_mem_zero);
6318 %}
6319
6320 // Store Compressed Pointer
6321 instruct storeN(memory dst, iRegN src) %{
6322 match(Set dst (StoreN dst src));
6323 ins_cost(MEMORY_REF_COST);
6324 size(4);
6325
6326 format %{ "STW $src,$dst\t! compressed ptr" %}
6327 ins_encode %{
6328 Register base = as_Register($dst$$base);
6329 Register index = as_Register($dst$$index);
6330 Register src = $src$$Register;
6331 if (index != G0) {
6332 __ stw(src, base, index);
6333 } else {
6334 __ stw(src, base, $dst$$disp);
6335 }
6336 %}
6337 ins_pipe(istore_mem_spORreg);
6338 %}
6339
6340 instruct storeNKlass(memory dst, iRegN src) %{
6341 match(Set dst (StoreNKlass dst src));
6342 ins_cost(MEMORY_REF_COST);
6343 size(4);
6344
6345 format %{ "STW $src,$dst\t! compressed klass ptr" %}
6346 ins_encode %{
6347 Register base = as_Register($dst$$base);
6348 Register index = as_Register($dst$$index);
6349 Register src = $src$$Register;
6350 if (index != G0) {
6351 __ stw(src, base, index);
6352 } else {
6353 __ stw(src, base, $dst$$disp);
6354 }
6355 %}
6356 ins_pipe(istore_mem_spORreg);
6357 %}
6358
6359 instruct storeN0(memory dst, immN0 src) %{
6360 match(Set dst (StoreN dst src));
6361 ins_cost(MEMORY_REF_COST);
6362 size(4);
6363
6364 format %{ "STW $src,$dst\t! compressed ptr" %}
6365 ins_encode %{
6366 Register base = as_Register($dst$$base);
6367 Register index = as_Register($dst$$index);
6368 if (index != G0) {
6369 __ stw(0, base, index);
6370 } else {
6371 __ stw(0, base, $dst$$disp);
6372 }
6373 %}
6374 ins_pipe(istore_mem_zero);
6375 %}
6376
6377 // Store Double
6378 instruct storeD( memory mem, regD src) %{
6379 match(Set mem (StoreD mem src));
6380 ins_cost(MEMORY_REF_COST);
6381
6382 size(4);
6383 format %{ "STDF $src,$mem" %}
6384 opcode(Assembler::stdf_op3);
6385 ins_encode(simple_form3_mem_reg( mem, src ) );
6386 ins_pipe(fstoreD_mem_reg);
6387 %}
6388
6389 instruct storeD0( memory mem, immD0 src) %{
6390 match(Set mem (StoreD mem src));
6391 ins_cost(MEMORY_REF_COST);
6392
6393 size(4);
6394 format %{ "STX $src,$mem" %}
6395 opcode(Assembler::stx_op3);
6396 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6397 ins_pipe(fstoreD_mem_zero);
6398 %}
6399
6400 // Store Float
6401 instruct storeF( memory mem, regF src) %{
6402 match(Set mem (StoreF mem src));
6403 ins_cost(MEMORY_REF_COST);
6404
6405 size(4);
6406 format %{ "STF $src,$mem" %}
6407 opcode(Assembler::stf_op3);
6408 ins_encode(simple_form3_mem_reg( mem, src ) );
6409 ins_pipe(fstoreF_mem_reg);
6410 %}
6411
6412 instruct storeF0( memory mem, immF0 src) %{
6413 match(Set mem (StoreF mem src));
6414 ins_cost(MEMORY_REF_COST);
6415
6416 size(4);
6417 format %{ "STW $src,$mem\t! storeF0" %}
6418 opcode(Assembler::stw_op3);
6419 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6420 ins_pipe(fstoreF_mem_zero);
6421 %}
6422
6423 // Convert oop pointer into compressed form
6424 instruct encodeHeapOop(iRegN dst, iRegP src) %{
6425 predicate(n->bottom_type()->make_ptr()->ptr() != TypePtr::NotNull);
6426 match(Set dst (EncodeP src));
6427 format %{ "encode_heap_oop $src, $dst" %}
6428 ins_encode %{
6429 __ encode_heap_oop($src$$Register, $dst$$Register);
6430 %}
6431 ins_avoid_back_to_back(Universe::narrow_oop_base() == NULL ? AVOID_NONE : AVOID_BEFORE);
6432 ins_pipe(ialu_reg);
6433 %}
6434
6435 instruct encodeHeapOop_not_null(iRegN dst, iRegP src) %{
6436 predicate(n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull);
6437 match(Set dst (EncodeP src));
6438 format %{ "encode_heap_oop_not_null $src, $dst" %}
6439 ins_encode %{
6440 __ encode_heap_oop_not_null($src$$Register, $dst$$Register);
6441 %}
6442 ins_pipe(ialu_reg);
6443 %}
6444
6445 instruct decodeHeapOop(iRegP dst, iRegN src) %{
6446 predicate(n->bottom_type()->is_oopptr()->ptr() != TypePtr::NotNull &&
6447 n->bottom_type()->is_oopptr()->ptr() != TypePtr::Constant);
6448 match(Set dst (DecodeN src));
6449 format %{ "decode_heap_oop $src, $dst" %}
6450 ins_encode %{
6451 __ decode_heap_oop($src$$Register, $dst$$Register);
6452 %}
6453 ins_pipe(ialu_reg);
6454 %}
6455
6456 instruct decodeHeapOop_not_null(iRegP dst, iRegN src) %{
6457 predicate(n->bottom_type()->is_oopptr()->ptr() == TypePtr::NotNull ||
6458 n->bottom_type()->is_oopptr()->ptr() == TypePtr::Constant);
6459 match(Set dst (DecodeN src));
6460 format %{ "decode_heap_oop_not_null $src, $dst" %}
6461 ins_encode %{
6462 __ decode_heap_oop_not_null($src$$Register, $dst$$Register);
6463 %}
6464 ins_pipe(ialu_reg);
6465 %}
6466
6467 instruct encodeKlass_not_null(iRegN dst, iRegP src) %{
6468 match(Set dst (EncodePKlass src));
6469 format %{ "encode_klass_not_null $src, $dst" %}
6470 ins_encode %{
6471 __ encode_klass_not_null($src$$Register, $dst$$Register);
6472 %}
6473 ins_pipe(ialu_reg);
6474 %}
6475
6476 instruct decodeKlass_not_null(iRegP dst, iRegN src) %{
6477 match(Set dst (DecodeNKlass src));
6478 format %{ "decode_klass_not_null $src, $dst" %}
6479 ins_encode %{
6480 __ decode_klass_not_null($src$$Register, $dst$$Register);
6481 %}
6482 ins_pipe(ialu_reg);
6483 %}
6484
6485 //----------MemBar Instructions-----------------------------------------------
6486 // Memory barrier flavors
6487
6488 instruct membar_acquire() %{
6489 match(MemBarAcquire);
6490 match(LoadFence);
6491 ins_cost(4*MEMORY_REF_COST);
6492
6493 size(0);
6494 format %{ "MEMBAR-acquire" %}
6495 ins_encode( enc_membar_acquire );
6496 ins_pipe(long_memory_op);
6497 %}
6498
6499 instruct membar_acquire_lock() %{
6500 match(MemBarAcquireLock);
6501 ins_cost(0);
6502
6503 size(0);
6504 format %{ "!MEMBAR-acquire (CAS in prior FastLock so empty encoding)" %}
6505 ins_encode( );
6506 ins_pipe(empty);
6507 %}
6508
6509 instruct membar_release() %{
6510 match(MemBarRelease);
6511 match(StoreFence);
6512 ins_cost(4*MEMORY_REF_COST);
6513
6514 size(0);
6515 format %{ "MEMBAR-release" %}
6516 ins_encode( enc_membar_release );
6517 ins_pipe(long_memory_op);
6518 %}
6519
6520 instruct membar_release_lock() %{
6521 match(MemBarReleaseLock);
6522 ins_cost(0);
6523
6524 size(0);
6525 format %{ "!MEMBAR-release (CAS in succeeding FastUnlock so empty encoding)" %}
6526 ins_encode( );
6527 ins_pipe(empty);
6528 %}
6529
6530 instruct membar_volatile() %{
6531 match(MemBarVolatile);
6532 ins_cost(4*MEMORY_REF_COST);
6533
6534 size(4);
6535 format %{ "MEMBAR-volatile" %}
6536 ins_encode( enc_membar_volatile );
6537 ins_pipe(long_memory_op);
6538 %}
6539
6540 instruct unnecessary_membar_volatile() %{
6541 match(MemBarVolatile);
6542 predicate(Matcher::post_store_load_barrier(n));
6543 ins_cost(0);
6544
6545 size(0);
6546 format %{ "!MEMBAR-volatile (unnecessary so empty encoding)" %}
6547 ins_encode( );
6548 ins_pipe(empty);
6549 %}
6550
6551 instruct membar_storestore() %{
6552 match(MemBarStoreStore);
6553 ins_cost(0);
6554
6555 size(0);
6556 format %{ "!MEMBAR-storestore (empty encoding)" %}
6557 ins_encode( );
6558 ins_pipe(empty);
6559 %}
6560
6561 //----------Register Move Instructions-----------------------------------------
6562 instruct roundDouble_nop(regD dst) %{
6563 match(Set dst (RoundDouble dst));
6564 ins_cost(0);
6565 // SPARC results are already "rounded" (i.e., normal-format IEEE)
6566 ins_encode( );
6567 ins_pipe(empty);
6568 %}
6569
6570
6571 instruct roundFloat_nop(regF dst) %{
6572 match(Set dst (RoundFloat dst));
6573 ins_cost(0);
6574 // SPARC results are already "rounded" (i.e., normal-format IEEE)
6575 ins_encode( );
6576 ins_pipe(empty);
6577 %}
6578
6579
6580 // Cast Index to Pointer for unsafe natives
6581 instruct castX2P(iRegX src, iRegP dst) %{
6582 match(Set dst (CastX2P src));
6583
6584 format %{ "MOV $src,$dst\t! IntX->Ptr" %}
6585 ins_encode( form3_g0_rs2_rd_move( src, dst ) );
6586 ins_pipe(ialu_reg);
6587 %}
6588
6589 // Cast Pointer to Index for unsafe natives
6590 instruct castP2X(iRegP src, iRegX dst) %{
6591 match(Set dst (CastP2X src));
6592
6593 format %{ "MOV $src,$dst\t! Ptr->IntX" %}
6594 ins_encode( form3_g0_rs2_rd_move( src, dst ) );
6595 ins_pipe(ialu_reg);
6596 %}
6597
6598 instruct stfSSD(stackSlotD stkSlot, regD src) %{
6599 // %%%% TO DO: Tell the coalescer that this kind of node is a copy!
6600 match(Set stkSlot src); // chain rule
6601 ins_cost(MEMORY_REF_COST);
6602 format %{ "STDF $src,$stkSlot\t!stk" %}
6603 opcode(Assembler::stdf_op3);
6604 ins_encode(simple_form3_mem_reg(stkSlot, src));
6605 ins_pipe(fstoreD_stk_reg);
6606 %}
6607
6608 instruct ldfSSD(regD dst, stackSlotD stkSlot) %{
6609 // %%%% TO DO: Tell the coalescer that this kind of node is a copy!
6610 match(Set dst stkSlot); // chain rule
6611 ins_cost(MEMORY_REF_COST);
6612 format %{ "LDDF $stkSlot,$dst\t!stk" %}
6613 opcode(Assembler::lddf_op3);
6614 ins_encode(simple_form3_mem_reg(stkSlot, dst));
6615 ins_pipe(floadD_stk);
6616 %}
6617
6618 instruct stfSSF(stackSlotF stkSlot, regF src) %{
6619 // %%%% TO DO: Tell the coalescer that this kind of node is a copy!
6620 match(Set stkSlot src); // chain rule
6621 ins_cost(MEMORY_REF_COST);
6622 format %{ "STF $src,$stkSlot\t!stk" %}
6623 opcode(Assembler::stf_op3);
6624 ins_encode(simple_form3_mem_reg(stkSlot, src));
6625 ins_pipe(fstoreF_stk_reg);
6626 %}
6627
6628 //----------Conditional Move---------------------------------------------------
6629 // Conditional move
6630 instruct cmovIP_reg(cmpOpP cmp, flagsRegP pcc, iRegI dst, iRegI src) %{
6631 match(Set dst (CMoveI (Binary cmp pcc) (Binary dst src)));
6632 ins_cost(150);
6633 format %{ "MOV$cmp $pcc,$src,$dst" %}
6634 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) );
6635 ins_pipe(ialu_reg);
6636 %}
6637
6638 instruct cmovIP_imm(cmpOpP cmp, flagsRegP pcc, iRegI dst, immI11 src) %{
6639 match(Set dst (CMoveI (Binary cmp pcc) (Binary dst src)));
6640 ins_cost(140);
6641 format %{ "MOV$cmp $pcc,$src,$dst" %}
6642 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) );
6643 ins_pipe(ialu_imm);
6644 %}
6645
6646 instruct cmovII_reg(cmpOp cmp, flagsReg icc, iRegI dst, iRegI src) %{
6647 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src)));
6648 ins_cost(150);
6649 size(4);
6650 format %{ "MOV$cmp $icc,$src,$dst" %}
6651 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6652 ins_pipe(ialu_reg);
6653 %}
6654
6655 instruct cmovII_imm(cmpOp cmp, flagsReg icc, iRegI dst, immI11 src) %{
6656 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src)));
6657 ins_cost(140);
6658 size(4);
6659 format %{ "MOV$cmp $icc,$src,$dst" %}
6660 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) );
6661 ins_pipe(ialu_imm);
6662 %}
6663
6664 instruct cmovIIu_reg(cmpOpU cmp, flagsRegU icc, iRegI dst, iRegI src) %{
6665 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src)));
6666 ins_cost(150);
6667 size(4);
6668 format %{ "MOV$cmp $icc,$src,$dst" %}
6669 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6670 ins_pipe(ialu_reg);
6671 %}
6672
6673 instruct cmovIIu_imm(cmpOpU cmp, flagsRegU icc, iRegI dst, immI11 src) %{
6674 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src)));
6675 ins_cost(140);
6676 size(4);
6677 format %{ "MOV$cmp $icc,$src,$dst" %}
6678 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) );
6679 ins_pipe(ialu_imm);
6680 %}
6681
6682 instruct cmovIF_reg(cmpOpF cmp, flagsRegF fcc, iRegI dst, iRegI src) %{
6683 match(Set dst (CMoveI (Binary cmp fcc) (Binary dst src)));
6684 ins_cost(150);
6685 size(4);
6686 format %{ "MOV$cmp $fcc,$src,$dst" %}
6687 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) );
6688 ins_pipe(ialu_reg);
6689 %}
6690
6691 instruct cmovIF_imm(cmpOpF cmp, flagsRegF fcc, iRegI dst, immI11 src) %{
6692 match(Set dst (CMoveI (Binary cmp fcc) (Binary dst src)));
6693 ins_cost(140);
6694 size(4);
6695 format %{ "MOV$cmp $fcc,$src,$dst" %}
6696 ins_encode( enc_cmov_imm_f(cmp,dst,src, fcc) );
6697 ins_pipe(ialu_imm);
6698 %}
6699
6700 // Conditional move for RegN. Only cmov(reg,reg).
6701 instruct cmovNP_reg(cmpOpP cmp, flagsRegP pcc, iRegN dst, iRegN src) %{
6702 match(Set dst (CMoveN (Binary cmp pcc) (Binary dst src)));
6703 ins_cost(150);
6704 format %{ "MOV$cmp $pcc,$src,$dst" %}
6705 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) );
6706 ins_pipe(ialu_reg);
6707 %}
6708
6709 // This instruction also works with CmpN so we don't need cmovNN_reg.
6710 instruct cmovNI_reg(cmpOp cmp, flagsReg icc, iRegN dst, iRegN src) %{
6711 match(Set dst (CMoveN (Binary cmp icc) (Binary dst src)));
6712 ins_cost(150);
6713 size(4);
6714 format %{ "MOV$cmp $icc,$src,$dst" %}
6715 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6716 ins_pipe(ialu_reg);
6717 %}
6718
6719 // This instruction also works with CmpN so we don't need cmovNN_reg.
6720 instruct cmovNIu_reg(cmpOpU cmp, flagsRegU icc, iRegN dst, iRegN src) %{
6721 match(Set dst (CMoveN (Binary cmp icc) (Binary dst src)));
6722 ins_cost(150);
6723 size(4);
6724 format %{ "MOV$cmp $icc,$src,$dst" %}
6725 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6726 ins_pipe(ialu_reg);
6727 %}
6728
6729 instruct cmovNF_reg(cmpOpF cmp, flagsRegF fcc, iRegN dst, iRegN src) %{
6730 match(Set dst (CMoveN (Binary cmp fcc) (Binary dst src)));
6731 ins_cost(150);
6732 size(4);
6733 format %{ "MOV$cmp $fcc,$src,$dst" %}
6734 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) );
6735 ins_pipe(ialu_reg);
6736 %}
6737
6738 // Conditional move
6739 instruct cmovPP_reg(cmpOpP cmp, flagsRegP pcc, iRegP dst, iRegP src) %{
6740 match(Set dst (CMoveP (Binary cmp pcc) (Binary dst src)));
6741 ins_cost(150);
6742 format %{ "MOV$cmp $pcc,$src,$dst\t! ptr" %}
6743 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) );
6744 ins_pipe(ialu_reg);
6745 %}
6746
6747 instruct cmovPP_imm(cmpOpP cmp, flagsRegP pcc, iRegP dst, immP0 src) %{
6748 match(Set dst (CMoveP (Binary cmp pcc) (Binary dst src)));
6749 ins_cost(140);
6750 format %{ "MOV$cmp $pcc,$src,$dst\t! ptr" %}
6751 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) );
6752 ins_pipe(ialu_imm);
6753 %}
6754
6755 // This instruction also works with CmpN so we don't need cmovPN_reg.
6756 instruct cmovPI_reg(cmpOp cmp, flagsReg icc, iRegP dst, iRegP src) %{
6757 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src)));
6758 ins_cost(150);
6759
6760 size(4);
6761 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %}
6762 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6763 ins_pipe(ialu_reg);
6764 %}
6765
6766 instruct cmovPIu_reg(cmpOpU cmp, flagsRegU icc, iRegP dst, iRegP src) %{
6767 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src)));
6768 ins_cost(150);
6769
6770 size(4);
6771 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %}
6772 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6773 ins_pipe(ialu_reg);
6774 %}
6775
6776 instruct cmovPI_imm(cmpOp cmp, flagsReg icc, iRegP dst, immP0 src) %{
6777 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src)));
6778 ins_cost(140);
6779
6780 size(4);
6781 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %}
6782 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) );
6783 ins_pipe(ialu_imm);
6784 %}
6785
6786 instruct cmovPIu_imm(cmpOpU cmp, flagsRegU icc, iRegP dst, immP0 src) %{
6787 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src)));
6788 ins_cost(140);
6789
6790 size(4);
6791 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %}
6792 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) );
6793 ins_pipe(ialu_imm);
6794 %}
6795
6796 instruct cmovPF_reg(cmpOpF cmp, flagsRegF fcc, iRegP dst, iRegP src) %{
6797 match(Set dst (CMoveP (Binary cmp fcc) (Binary dst src)));
6798 ins_cost(150);
6799 size(4);
6800 format %{ "MOV$cmp $fcc,$src,$dst" %}
6801 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) );
6802 ins_pipe(ialu_imm);
6803 %}
6804
6805 instruct cmovPF_imm(cmpOpF cmp, flagsRegF fcc, iRegP dst, immP0 src) %{
6806 match(Set dst (CMoveP (Binary cmp fcc) (Binary dst src)));
6807 ins_cost(140);
6808 size(4);
6809 format %{ "MOV$cmp $fcc,$src,$dst" %}
6810 ins_encode( enc_cmov_imm_f(cmp,dst,src, fcc) );
6811 ins_pipe(ialu_imm);
6812 %}
6813
6814 // Conditional move
6815 instruct cmovFP_reg(cmpOpP cmp, flagsRegP pcc, regF dst, regF src) %{
6816 match(Set dst (CMoveF (Binary cmp pcc) (Binary dst src)));
6817 ins_cost(150);
6818 opcode(0x101);
6819 format %{ "FMOVD$cmp $pcc,$src,$dst" %}
6820 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::ptr_cc)) );
6821 ins_pipe(int_conditional_float_move);
6822 %}
6823
6824 instruct cmovFI_reg(cmpOp cmp, flagsReg icc, regF dst, regF src) %{
6825 match(Set dst (CMoveF (Binary cmp icc) (Binary dst src)));
6826 ins_cost(150);
6827
6828 size(4);
6829 format %{ "FMOVS$cmp $icc,$src,$dst" %}
6830 opcode(0x101);
6831 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) );
6832 ins_pipe(int_conditional_float_move);
6833 %}
6834
6835 instruct cmovFIu_reg(cmpOpU cmp, flagsRegU icc, regF dst, regF src) %{
6836 match(Set dst (CMoveF (Binary cmp icc) (Binary dst src)));
6837 ins_cost(150);
6838
6839 size(4);
6840 format %{ "FMOVS$cmp $icc,$src,$dst" %}
6841 opcode(0x101);
6842 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) );
6843 ins_pipe(int_conditional_float_move);
6844 %}
6845
6846 // Conditional move,
6847 instruct cmovFF_reg(cmpOpF cmp, flagsRegF fcc, regF dst, regF src) %{
6848 match(Set dst (CMoveF (Binary cmp fcc) (Binary dst src)));
6849 ins_cost(150);
6850 size(4);
6851 format %{ "FMOVF$cmp $fcc,$src,$dst" %}
6852 opcode(0x1);
6853 ins_encode( enc_cmovff_reg(cmp,fcc,dst,src) );
6854 ins_pipe(int_conditional_double_move);
6855 %}
6856
6857 // Conditional move
6858 instruct cmovDP_reg(cmpOpP cmp, flagsRegP pcc, regD dst, regD src) %{
6859 match(Set dst (CMoveD (Binary cmp pcc) (Binary dst src)));
6860 ins_cost(150);
6861 size(4);
6862 opcode(0x102);
6863 format %{ "FMOVD$cmp $pcc,$src,$dst" %}
6864 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::ptr_cc)) );
6865 ins_pipe(int_conditional_double_move);
6866 %}
6867
6868 instruct cmovDI_reg(cmpOp cmp, flagsReg icc, regD dst, regD src) %{
6869 match(Set dst (CMoveD (Binary cmp icc) (Binary dst src)));
6870 ins_cost(150);
6871
6872 size(4);
6873 format %{ "FMOVD$cmp $icc,$src,$dst" %}
6874 opcode(0x102);
6875 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) );
6876 ins_pipe(int_conditional_double_move);
6877 %}
6878
6879 instruct cmovDIu_reg(cmpOpU cmp, flagsRegU icc, regD dst, regD src) %{
6880 match(Set dst (CMoveD (Binary cmp icc) (Binary dst src)));
6881 ins_cost(150);
6882
6883 size(4);
6884 format %{ "FMOVD$cmp $icc,$src,$dst" %}
6885 opcode(0x102);
6886 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) );
6887 ins_pipe(int_conditional_double_move);
6888 %}
6889
6890 // Conditional move,
6891 instruct cmovDF_reg(cmpOpF cmp, flagsRegF fcc, regD dst, regD src) %{
6892 match(Set dst (CMoveD (Binary cmp fcc) (Binary dst src)));
6893 ins_cost(150);
6894 size(4);
6895 format %{ "FMOVD$cmp $fcc,$src,$dst" %}
6896 opcode(0x2);
6897 ins_encode( enc_cmovff_reg(cmp,fcc,dst,src) );
6898 ins_pipe(int_conditional_double_move);
6899 %}
6900
6901 // Conditional move
6902 instruct cmovLP_reg(cmpOpP cmp, flagsRegP pcc, iRegL dst, iRegL src) %{
6903 match(Set dst (CMoveL (Binary cmp pcc) (Binary dst src)));
6904 ins_cost(150);
6905 format %{ "MOV$cmp $pcc,$src,$dst\t! long" %}
6906 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) );
6907 ins_pipe(ialu_reg);
6908 %}
6909
6910 instruct cmovLP_imm(cmpOpP cmp, flagsRegP pcc, iRegL dst, immI11 src) %{
6911 match(Set dst (CMoveL (Binary cmp pcc) (Binary dst src)));
6912 ins_cost(140);
6913 format %{ "MOV$cmp $pcc,$src,$dst\t! long" %}
6914 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) );
6915 ins_pipe(ialu_imm);
6916 %}
6917
6918 instruct cmovLI_reg(cmpOp cmp, flagsReg icc, iRegL dst, iRegL src) %{
6919 match(Set dst (CMoveL (Binary cmp icc) (Binary dst src)));
6920 ins_cost(150);
6921
6922 size(4);
6923 format %{ "MOV$cmp $icc,$src,$dst\t! long" %}
6924 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6925 ins_pipe(ialu_reg);
6926 %}
6927
6928
6929 instruct cmovLIu_reg(cmpOpU cmp, flagsRegU icc, iRegL dst, iRegL src) %{
6930 match(Set dst (CMoveL (Binary cmp icc) (Binary dst src)));
6931 ins_cost(150);
6932
6933 size(4);
6934 format %{ "MOV$cmp $icc,$src,$dst\t! long" %}
6935 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6936 ins_pipe(ialu_reg);
6937 %}
6938
6939
6940 instruct cmovLF_reg(cmpOpF cmp, flagsRegF fcc, iRegL dst, iRegL src) %{
6941 match(Set dst (CMoveL (Binary cmp fcc) (Binary dst src)));
6942 ins_cost(150);
6943
6944 size(4);
6945 format %{ "MOV$cmp $fcc,$src,$dst\t! long" %}
6946 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) );
6947 ins_pipe(ialu_reg);
6948 %}
6949
6950
6951
6952 //----------OS and Locking Instructions----------------------------------------
6953
6954 // This name is KNOWN by the ADLC and cannot be changed.
6955 // The ADLC forces a 'TypeRawPtr::BOTTOM' output type
6956 // for this guy.
6957 instruct tlsLoadP(g2RegP dst) %{
6958 match(Set dst (ThreadLocal));
6959
6960 size(0);
6961 ins_cost(0);
6962 format %{ "# TLS is in G2" %}
6963 ins_encode( /*empty encoding*/ );
6964 ins_pipe(ialu_none);
6965 %}
6966
6967 instruct checkCastPP( iRegP dst ) %{
6968 match(Set dst (CheckCastPP dst));
6969
6970 size(0);
6971 format %{ "# checkcastPP of $dst" %}
6972 ins_encode( /*empty encoding*/ );
6973 ins_pipe(empty);
6974 %}
6975
6976
6977 instruct castPP( iRegP dst ) %{
6978 match(Set dst (CastPP dst));
6979 format %{ "# castPP of $dst" %}
6980 ins_encode( /*empty encoding*/ );
6981 ins_pipe(empty);
6982 %}
6983
6984 instruct castII( iRegI dst ) %{
6985 match(Set dst (CastII dst));
6986 format %{ "# castII of $dst" %}
6987 ins_encode( /*empty encoding*/ );
6988 ins_cost(0);
6989 ins_pipe(empty);
6990 %}
6991
6992 //----------Arithmetic Instructions--------------------------------------------
6993 // Addition Instructions
6994 // Register Addition
6995 instruct addI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
6996 match(Set dst (AddI src1 src2));
6997
6998 size(4);
6999 format %{ "ADD $src1,$src2,$dst" %}
7000 ins_encode %{
7001 __ add($src1$$Register, $src2$$Register, $dst$$Register);
7002 %}
7003 ins_pipe(ialu_reg_reg);
7004 %}
7005
7006 // Immediate Addition
7007 instruct addI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
7008 match(Set dst (AddI src1 src2));
7009
7010 size(4);
7011 format %{ "ADD $src1,$src2,$dst" %}
7012 opcode(Assembler::add_op3, Assembler::arith_op);
7013 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7014 ins_pipe(ialu_reg_imm);
7015 %}
7016
7017 // Pointer Register Addition
7018 instruct addP_reg_reg(iRegP dst, iRegP src1, iRegX src2) %{
7019 match(Set dst (AddP src1 src2));
7020
7021 size(4);
7022 format %{ "ADD $src1,$src2,$dst" %}
7023 opcode(Assembler::add_op3, Assembler::arith_op);
7024 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7025 ins_pipe(ialu_reg_reg);
7026 %}
7027
7028 // Pointer Immediate Addition
7029 instruct addP_reg_imm13(iRegP dst, iRegP src1, immX13 src2) %{
7030 match(Set dst (AddP src1 src2));
7031
7032 size(4);
7033 format %{ "ADD $src1,$src2,$dst" %}
7034 opcode(Assembler::add_op3, Assembler::arith_op);
7035 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7036 ins_pipe(ialu_reg_imm);
7037 %}
7038
7039 // Long Addition
7040 instruct addL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7041 match(Set dst (AddL src1 src2));
7042
7043 size(4);
7044 format %{ "ADD $src1,$src2,$dst\t! long" %}
7045 opcode(Assembler::add_op3, Assembler::arith_op);
7046 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7047 ins_pipe(ialu_reg_reg);
7048 %}
7049
7050 instruct addL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{
7051 match(Set dst (AddL src1 con));
7052
7053 size(4);
7054 format %{ "ADD $src1,$con,$dst" %}
7055 opcode(Assembler::add_op3, Assembler::arith_op);
7056 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
7057 ins_pipe(ialu_reg_imm);
7058 %}
7059
7060 //----------Conditional_store--------------------------------------------------
7061 // Conditional-store of the updated heap-top.
7062 // Used during allocation of the shared heap.
7063 // Sets flags (EQ) on success. Implemented with a CASA on Sparc.
7064
7065 // LoadP-locked. Same as a regular pointer load when used with a compare-swap
7066 instruct loadPLocked(iRegP dst, memory mem) %{
7067 match(Set dst (LoadPLocked mem));
7068 ins_cost(MEMORY_REF_COST);
7069
7070 #ifndef _LP64
7071 size(4);
7072 format %{ "LDUW $mem,$dst\t! ptr" %}
7073 opcode(Assembler::lduw_op3, 0, REGP_OP);
7074 #else
7075 format %{ "LDX $mem,$dst\t! ptr" %}
7076 opcode(Assembler::ldx_op3, 0, REGP_OP);
7077 #endif
7078 ins_encode( form3_mem_reg( mem, dst ) );
7079 ins_pipe(iload_mem);
7080 %}
7081
7082 instruct storePConditional( iRegP heap_top_ptr, iRegP oldval, g3RegP newval, flagsRegP pcc ) %{
7083 match(Set pcc (StorePConditional heap_top_ptr (Binary oldval newval)));
7084 effect( KILL newval );
7085 format %{ "CASA [$heap_top_ptr],$oldval,R_G3\t! If $oldval==[$heap_top_ptr] Then store R_G3 into [$heap_top_ptr], set R_G3=[$heap_top_ptr] in any case\n\t"
7086 "CMP R_G3,$oldval\t\t! See if we made progress" %}
7087 ins_encode( enc_cas(heap_top_ptr,oldval,newval) );
7088 ins_pipe( long_memory_op );
7089 %}
7090
7091 // Conditional-store of an int value.
7092 instruct storeIConditional( iRegP mem_ptr, iRegI oldval, g3RegI newval, flagsReg icc ) %{
7093 match(Set icc (StoreIConditional mem_ptr (Binary oldval newval)));
7094 effect( KILL newval );
7095 format %{ "CASA [$mem_ptr],$oldval,$newval\t! If $oldval==[$mem_ptr] Then store $newval into [$mem_ptr], set $newval=[$mem_ptr] in any case\n\t"
7096 "CMP $oldval,$newval\t\t! See if we made progress" %}
7097 ins_encode( enc_cas(mem_ptr,oldval,newval) );
7098 ins_pipe( long_memory_op );
7099 %}
7100
7101 // Conditional-store of a long value.
7102 instruct storeLConditional( iRegP mem_ptr, iRegL oldval, g3RegL newval, flagsRegL xcc ) %{
7103 match(Set xcc (StoreLConditional mem_ptr (Binary oldval newval)));
7104 effect( KILL newval );
7105 format %{ "CASXA [$mem_ptr],$oldval,$newval\t! If $oldval==[$mem_ptr] Then store $newval into [$mem_ptr], set $newval=[$mem_ptr] in any case\n\t"
7106 "CMP $oldval,$newval\t\t! See if we made progress" %}
7107 ins_encode( enc_cas(mem_ptr,oldval,newval) );
7108 ins_pipe( long_memory_op );
7109 %}
7110
7111 // No flag versions for CompareAndSwap{P,I,L} because matcher can't match them
7112
7113 instruct compareAndSwapL_bool(iRegP mem_ptr, iRegL oldval, iRegL newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{
7114 predicate(VM_Version::supports_cx8());
7115 match(Set res (CompareAndSwapL mem_ptr (Binary oldval newval)));
7116 effect( USE mem_ptr, KILL ccr, KILL tmp1);
7117 format %{
7118 "MOV $newval,O7\n\t"
7119 "CASXA [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t"
7120 "CMP $oldval,O7\t\t! See if we made progress\n\t"
7121 "MOV 1,$res\n\t"
7122 "MOVne xcc,R_G0,$res"
7123 %}
7124 ins_encode( enc_casx(mem_ptr, oldval, newval),
7125 enc_lflags_ne_to_boolean(res) );
7126 ins_pipe( long_memory_op );
7127 %}
7128
7129
7130 instruct compareAndSwapI_bool(iRegP mem_ptr, iRegI oldval, iRegI newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{
7131 match(Set res (CompareAndSwapI mem_ptr (Binary oldval newval)));
7132 effect( USE mem_ptr, KILL ccr, KILL tmp1);
7133 format %{
7134 "MOV $newval,O7\n\t"
7135 "CASA [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t"
7136 "CMP $oldval,O7\t\t! See if we made progress\n\t"
7137 "MOV 1,$res\n\t"
7138 "MOVne icc,R_G0,$res"
7139 %}
7140 ins_encode( enc_casi(mem_ptr, oldval, newval),
7141 enc_iflags_ne_to_boolean(res) );
7142 ins_pipe( long_memory_op );
7143 %}
7144
7145 instruct compareAndSwapP_bool(iRegP mem_ptr, iRegP oldval, iRegP newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{
7146 #ifdef _LP64
7147 predicate(VM_Version::supports_cx8());
7148 #endif
7149 match(Set res (CompareAndSwapP mem_ptr (Binary oldval newval)));
7150 effect( USE mem_ptr, KILL ccr, KILL tmp1);
7151 format %{
7152 "MOV $newval,O7\n\t"
7153 "CASA_PTR [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t"
7154 "CMP $oldval,O7\t\t! See if we made progress\n\t"
7155 "MOV 1,$res\n\t"
7156 "MOVne xcc,R_G0,$res"
7157 %}
7158 #ifdef _LP64
7159 ins_encode( enc_casx(mem_ptr, oldval, newval),
7160 enc_lflags_ne_to_boolean(res) );
7161 #else
7162 ins_encode( enc_casi(mem_ptr, oldval, newval),
7163 enc_iflags_ne_to_boolean(res) );
7164 #endif
7165 ins_pipe( long_memory_op );
7166 %}
7167
7168 instruct compareAndSwapN_bool(iRegP mem_ptr, iRegN oldval, iRegN newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{
7169 match(Set res (CompareAndSwapN mem_ptr (Binary oldval newval)));
7170 effect( USE mem_ptr, KILL ccr, KILL tmp1);
7171 format %{
7172 "MOV $newval,O7\n\t"
7173 "CASA [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t"
7174 "CMP $oldval,O7\t\t! See if we made progress\n\t"
7175 "MOV 1,$res\n\t"
7176 "MOVne icc,R_G0,$res"
7177 %}
7178 ins_encode( enc_casi(mem_ptr, oldval, newval),
7179 enc_iflags_ne_to_boolean(res) );
7180 ins_pipe( long_memory_op );
7181 %}
7182
7183 instruct xchgI( memory mem, iRegI newval) %{
7184 match(Set newval (GetAndSetI mem newval));
7185 format %{ "SWAP [$mem],$newval" %}
7186 size(4);
7187 ins_encode %{
7188 __ swap($mem$$Address, $newval$$Register);
7189 %}
7190 ins_pipe( long_memory_op );
7191 %}
7192
7193 #ifndef _LP64
7194 instruct xchgP( memory mem, iRegP newval) %{
7195 match(Set newval (GetAndSetP mem newval));
7196 format %{ "SWAP [$mem],$newval" %}
7197 size(4);
7198 ins_encode %{
7199 __ swap($mem$$Address, $newval$$Register);
7200 %}
7201 ins_pipe( long_memory_op );
7202 %}
7203 #endif
7204
7205 instruct xchgN( memory mem, iRegN newval) %{
7206 match(Set newval (GetAndSetN mem newval));
7207 format %{ "SWAP [$mem],$newval" %}
7208 size(4);
7209 ins_encode %{
7210 __ swap($mem$$Address, $newval$$Register);
7211 %}
7212 ins_pipe( long_memory_op );
7213 %}
7214
7215 //---------------------
7216 // Subtraction Instructions
7217 // Register Subtraction
7218 instruct subI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7219 match(Set dst (SubI src1 src2));
7220
7221 size(4);
7222 format %{ "SUB $src1,$src2,$dst" %}
7223 opcode(Assembler::sub_op3, Assembler::arith_op);
7224 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7225 ins_pipe(ialu_reg_reg);
7226 %}
7227
7228 // Immediate Subtraction
7229 instruct subI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
7230 match(Set dst (SubI src1 src2));
7231
7232 size(4);
7233 format %{ "SUB $src1,$src2,$dst" %}
7234 opcode(Assembler::sub_op3, Assembler::arith_op);
7235 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7236 ins_pipe(ialu_reg_imm);
7237 %}
7238
7239 instruct subI_zero_reg(iRegI dst, immI0 zero, iRegI src2) %{
7240 match(Set dst (SubI zero src2));
7241
7242 size(4);
7243 format %{ "NEG $src2,$dst" %}
7244 opcode(Assembler::sub_op3, Assembler::arith_op);
7245 ins_encode( form3_rs1_rs2_rd( R_G0, src2, dst ) );
7246 ins_pipe(ialu_zero_reg);
7247 %}
7248
7249 // Long subtraction
7250 instruct subL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7251 match(Set dst (SubL src1 src2));
7252
7253 size(4);
7254 format %{ "SUB $src1,$src2,$dst\t! long" %}
7255 opcode(Assembler::sub_op3, Assembler::arith_op);
7256 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7257 ins_pipe(ialu_reg_reg);
7258 %}
7259
7260 // Immediate Subtraction
7261 instruct subL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{
7262 match(Set dst (SubL src1 con));
7263
7264 size(4);
7265 format %{ "SUB $src1,$con,$dst\t! long" %}
7266 opcode(Assembler::sub_op3, Assembler::arith_op);
7267 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
7268 ins_pipe(ialu_reg_imm);
7269 %}
7270
7271 // Long negation
7272 instruct negL_reg_reg(iRegL dst, immL0 zero, iRegL src2) %{
7273 match(Set dst (SubL zero src2));
7274
7275 size(4);
7276 format %{ "NEG $src2,$dst\t! long" %}
7277 opcode(Assembler::sub_op3, Assembler::arith_op);
7278 ins_encode( form3_rs1_rs2_rd( R_G0, src2, dst ) );
7279 ins_pipe(ialu_zero_reg);
7280 %}
7281
7282 // Multiplication Instructions
7283 // Integer Multiplication
7284 // Register Multiplication
7285 instruct mulI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7286 match(Set dst (MulI src1 src2));
7287
7288 size(4);
7289 format %{ "MULX $src1,$src2,$dst" %}
7290 opcode(Assembler::mulx_op3, Assembler::arith_op);
7291 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7292 ins_pipe(imul_reg_reg);
7293 %}
7294
7295 // Immediate Multiplication
7296 instruct mulI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
7297 match(Set dst (MulI src1 src2));
7298
7299 size(4);
7300 format %{ "MULX $src1,$src2,$dst" %}
7301 opcode(Assembler::mulx_op3, Assembler::arith_op);
7302 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7303 ins_pipe(imul_reg_imm);
7304 %}
7305
7306 instruct mulL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7307 match(Set dst (MulL src1 src2));
7308 ins_cost(DEFAULT_COST * 5);
7309 size(4);
7310 format %{ "MULX $src1,$src2,$dst\t! long" %}
7311 opcode(Assembler::mulx_op3, Assembler::arith_op);
7312 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7313 ins_pipe(mulL_reg_reg);
7314 %}
7315
7316 // Immediate Multiplication
7317 instruct mulL_reg_imm13(iRegL dst, iRegL src1, immL13 src2) %{
7318 match(Set dst (MulL src1 src2));
7319 ins_cost(DEFAULT_COST * 5);
7320 size(4);
7321 format %{ "MULX $src1,$src2,$dst" %}
7322 opcode(Assembler::mulx_op3, Assembler::arith_op);
7323 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7324 ins_pipe(mulL_reg_imm);
7325 %}
7326
7327 // Integer Division
7328 // Register Division
7329 instruct divI_reg_reg(iRegI dst, iRegIsafe src1, iRegIsafe src2) %{
7330 match(Set dst (DivI src1 src2));
7331 ins_cost((2+71)*DEFAULT_COST);
7332
7333 format %{ "SRA $src2,0,$src2\n\t"
7334 "SRA $src1,0,$src1\n\t"
7335 "SDIVX $src1,$src2,$dst" %}
7336 ins_encode( idiv_reg( src1, src2, dst ) );
7337 ins_pipe(sdiv_reg_reg);
7338 %}
7339
7340 // Immediate Division
7341 instruct divI_reg_imm13(iRegI dst, iRegIsafe src1, immI13 src2) %{
7342 match(Set dst (DivI src1 src2));
7343 ins_cost((2+71)*DEFAULT_COST);
7344
7345 format %{ "SRA $src1,0,$src1\n\t"
7346 "SDIVX $src1,$src2,$dst" %}
7347 ins_encode( idiv_imm( src1, src2, dst ) );
7348 ins_pipe(sdiv_reg_imm);
7349 %}
7350
7351 //----------Div-By-10-Expansion------------------------------------------------
7352 // Extract hi bits of a 32x32->64 bit multiply.
7353 // Expand rule only, not matched
7354 instruct mul_hi(iRegIsafe dst, iRegIsafe src1, iRegIsafe src2 ) %{
7355 effect( DEF dst, USE src1, USE src2 );
7356 format %{ "MULX $src1,$src2,$dst\t! Used in div-by-10\n\t"
7357 "SRLX $dst,#32,$dst\t\t! Extract only hi word of result" %}
7358 ins_encode( enc_mul_hi(dst,src1,src2));
7359 ins_pipe(sdiv_reg_reg);
7360 %}
7361
7362 // Magic constant, reciprocal of 10
7363 instruct loadConI_x66666667(iRegIsafe dst) %{
7364 effect( DEF dst );
7365
7366 size(8);
7367 format %{ "SET 0x66666667,$dst\t! Used in div-by-10" %}
7368 ins_encode( Set32(0x66666667, dst) );
7369 ins_pipe(ialu_hi_lo_reg);
7370 %}
7371
7372 // Register Shift Right Arithmetic Long by 32-63
7373 instruct sra_31( iRegI dst, iRegI src ) %{
7374 effect( DEF dst, USE src );
7375 format %{ "SRA $src,31,$dst\t! Used in div-by-10" %}
7376 ins_encode( form3_rs1_rd_copysign_hi(src,dst) );
7377 ins_pipe(ialu_reg_reg);
7378 %}
7379
7380 // Arithmetic Shift Right by 8-bit immediate
7381 instruct sra_reg_2( iRegI dst, iRegI src ) %{
7382 effect( DEF dst, USE src );
7383 format %{ "SRA $src,2,$dst\t! Used in div-by-10" %}
7384 opcode(Assembler::sra_op3, Assembler::arith_op);
7385 ins_encode( form3_rs1_simm13_rd( src, 0x2, dst ) );
7386 ins_pipe(ialu_reg_imm);
7387 %}
7388
7389 // Integer DIV with 10
7390 instruct divI_10( iRegI dst, iRegIsafe src, immI10 div ) %{
7391 match(Set dst (DivI src div));
7392 ins_cost((6+6)*DEFAULT_COST);
7393 expand %{
7394 iRegIsafe tmp1; // Killed temps;
7395 iRegIsafe tmp2; // Killed temps;
7396 iRegI tmp3; // Killed temps;
7397 iRegI tmp4; // Killed temps;
7398 loadConI_x66666667( tmp1 ); // SET 0x66666667 -> tmp1
7399 mul_hi( tmp2, src, tmp1 ); // MUL hibits(src * tmp1) -> tmp2
7400 sra_31( tmp3, src ); // SRA src,31 -> tmp3
7401 sra_reg_2( tmp4, tmp2 ); // SRA tmp2,2 -> tmp4
7402 subI_reg_reg( dst,tmp4,tmp3); // SUB tmp4 - tmp3 -> dst
7403 %}
7404 %}
7405
7406 // Register Long Division
7407 instruct divL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7408 match(Set dst (DivL src1 src2));
7409 ins_cost(DEFAULT_COST*71);
7410 size(4);
7411 format %{ "SDIVX $src1,$src2,$dst\t! long" %}
7412 opcode(Assembler::sdivx_op3, Assembler::arith_op);
7413 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7414 ins_pipe(divL_reg_reg);
7415 %}
7416
7417 // Register Long Division
7418 instruct divL_reg_imm13(iRegL dst, iRegL src1, immL13 src2) %{
7419 match(Set dst (DivL src1 src2));
7420 ins_cost(DEFAULT_COST*71);
7421 size(4);
7422 format %{ "SDIVX $src1,$src2,$dst\t! long" %}
7423 opcode(Assembler::sdivx_op3, Assembler::arith_op);
7424 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7425 ins_pipe(divL_reg_imm);
7426 %}
7427
7428 // Integer Remainder
7429 // Register Remainder
7430 instruct modI_reg_reg(iRegI dst, iRegIsafe src1, iRegIsafe src2, o7RegP temp, flagsReg ccr ) %{
7431 match(Set dst (ModI src1 src2));
7432 effect( KILL ccr, KILL temp);
7433
7434 format %{ "SREM $src1,$src2,$dst" %}
7435 ins_encode( irem_reg(src1, src2, dst, temp) );
7436 ins_pipe(sdiv_reg_reg);
7437 %}
7438
7439 // Immediate Remainder
7440 instruct modI_reg_imm13(iRegI dst, iRegIsafe src1, immI13 src2, o7RegP temp, flagsReg ccr ) %{
7441 match(Set dst (ModI src1 src2));
7442 effect( KILL ccr, KILL temp);
7443
7444 format %{ "SREM $src1,$src2,$dst" %}
7445 ins_encode( irem_imm(src1, src2, dst, temp) );
7446 ins_pipe(sdiv_reg_imm);
7447 %}
7448
7449 // Register Long Remainder
7450 instruct divL_reg_reg_1(iRegL dst, iRegL src1, iRegL src2) %{
7451 effect(DEF dst, USE src1, USE src2);
7452 size(4);
7453 format %{ "SDIVX $src1,$src2,$dst\t! long" %}
7454 opcode(Assembler::sdivx_op3, Assembler::arith_op);
7455 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7456 ins_pipe(divL_reg_reg);
7457 %}
7458
7459 // Register Long Division
7460 instruct divL_reg_imm13_1(iRegL dst, iRegL src1, immL13 src2) %{
7461 effect(DEF dst, USE src1, USE src2);
7462 size(4);
7463 format %{ "SDIVX $src1,$src2,$dst\t! long" %}
7464 opcode(Assembler::sdivx_op3, Assembler::arith_op);
7465 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7466 ins_pipe(divL_reg_imm);
7467 %}
7468
7469 instruct mulL_reg_reg_1(iRegL dst, iRegL src1, iRegL src2) %{
7470 effect(DEF dst, USE src1, USE src2);
7471 size(4);
7472 format %{ "MULX $src1,$src2,$dst\t! long" %}
7473 opcode(Assembler::mulx_op3, Assembler::arith_op);
7474 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7475 ins_pipe(mulL_reg_reg);
7476 %}
7477
7478 // Immediate Multiplication
7479 instruct mulL_reg_imm13_1(iRegL dst, iRegL src1, immL13 src2) %{
7480 effect(DEF dst, USE src1, USE src2);
7481 size(4);
7482 format %{ "MULX $src1,$src2,$dst" %}
7483 opcode(Assembler::mulx_op3, Assembler::arith_op);
7484 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7485 ins_pipe(mulL_reg_imm);
7486 %}
7487
7488 instruct subL_reg_reg_1(iRegL dst, iRegL src1, iRegL src2) %{
7489 effect(DEF dst, USE src1, USE src2);
7490 size(4);
7491 format %{ "SUB $src1,$src2,$dst\t! long" %}
7492 opcode(Assembler::sub_op3, Assembler::arith_op);
7493 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7494 ins_pipe(ialu_reg_reg);
7495 %}
7496
7497 instruct subL_reg_reg_2(iRegL dst, iRegL src1, iRegL src2) %{
7498 effect(DEF dst, USE src1, USE src2);
7499 size(4);
7500 format %{ "SUB $src1,$src2,$dst\t! long" %}
7501 opcode(Assembler::sub_op3, Assembler::arith_op);
7502 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7503 ins_pipe(ialu_reg_reg);
7504 %}
7505
7506 // Register Long Remainder
7507 instruct modL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7508 match(Set dst (ModL src1 src2));
7509 ins_cost(DEFAULT_COST*(71 + 6 + 1));
7510 expand %{
7511 iRegL tmp1;
7512 iRegL tmp2;
7513 divL_reg_reg_1(tmp1, src1, src2);
7514 mulL_reg_reg_1(tmp2, tmp1, src2);
7515 subL_reg_reg_1(dst, src1, tmp2);
7516 %}
7517 %}
7518
7519 // Register Long Remainder
7520 instruct modL_reg_imm13(iRegL dst, iRegL src1, immL13 src2) %{
7521 match(Set dst (ModL src1 src2));
7522 ins_cost(DEFAULT_COST*(71 + 6 + 1));
7523 expand %{
7524 iRegL tmp1;
7525 iRegL tmp2;
7526 divL_reg_imm13_1(tmp1, src1, src2);
7527 mulL_reg_imm13_1(tmp2, tmp1, src2);
7528 subL_reg_reg_2 (dst, src1, tmp2);
7529 %}
7530 %}
7531
7532 // Integer Shift Instructions
7533 // Register Shift Left
7534 instruct shlI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7535 match(Set dst (LShiftI src1 src2));
7536
7537 size(4);
7538 format %{ "SLL $src1,$src2,$dst" %}
7539 opcode(Assembler::sll_op3, Assembler::arith_op);
7540 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7541 ins_pipe(ialu_reg_reg);
7542 %}
7543
7544 // Register Shift Left Immediate
7545 instruct shlI_reg_imm5(iRegI dst, iRegI src1, immU5 src2) %{
7546 match(Set dst (LShiftI src1 src2));
7547
7548 size(4);
7549 format %{ "SLL $src1,$src2,$dst" %}
7550 opcode(Assembler::sll_op3, Assembler::arith_op);
7551 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) );
7552 ins_pipe(ialu_reg_imm);
7553 %}
7554
7555 // Register Shift Left
7556 instruct shlL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{
7557 match(Set dst (LShiftL src1 src2));
7558
7559 size(4);
7560 format %{ "SLLX $src1,$src2,$dst" %}
7561 opcode(Assembler::sllx_op3, Assembler::arith_op);
7562 ins_encode( form3_sd_rs1_rs2_rd( src1, src2, dst ) );
7563 ins_pipe(ialu_reg_reg);
7564 %}
7565
7566 // Register Shift Left Immediate
7567 instruct shlL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{
7568 match(Set dst (LShiftL src1 src2));
7569
7570 size(4);
7571 format %{ "SLLX $src1,$src2,$dst" %}
7572 opcode(Assembler::sllx_op3, Assembler::arith_op);
7573 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) );
7574 ins_pipe(ialu_reg_imm);
7575 %}
7576
7577 // Register Arithmetic Shift Right
7578 instruct sarI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7579 match(Set dst (RShiftI src1 src2));
7580 size(4);
7581 format %{ "SRA $src1,$src2,$dst" %}
7582 opcode(Assembler::sra_op3, Assembler::arith_op);
7583 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7584 ins_pipe(ialu_reg_reg);
7585 %}
7586
7587 // Register Arithmetic Shift Right Immediate
7588 instruct sarI_reg_imm5(iRegI dst, iRegI src1, immU5 src2) %{
7589 match(Set dst (RShiftI src1 src2));
7590
7591 size(4);
7592 format %{ "SRA $src1,$src2,$dst" %}
7593 opcode(Assembler::sra_op3, Assembler::arith_op);
7594 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) );
7595 ins_pipe(ialu_reg_imm);
7596 %}
7597
7598 // Register Shift Right Arithmatic Long
7599 instruct sarL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{
7600 match(Set dst (RShiftL src1 src2));
7601
7602 size(4);
7603 format %{ "SRAX $src1,$src2,$dst" %}
7604 opcode(Assembler::srax_op3, Assembler::arith_op);
7605 ins_encode( form3_sd_rs1_rs2_rd( src1, src2, dst ) );
7606 ins_pipe(ialu_reg_reg);
7607 %}
7608
7609 // Register Shift Left Immediate
7610 instruct sarL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{
7611 match(Set dst (RShiftL src1 src2));
7612
7613 size(4);
7614 format %{ "SRAX $src1,$src2,$dst" %}
7615 opcode(Assembler::srax_op3, Assembler::arith_op);
7616 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) );
7617 ins_pipe(ialu_reg_imm);
7618 %}
7619
7620 // Register Shift Right
7621 instruct shrI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7622 match(Set dst (URShiftI src1 src2));
7623
7624 size(4);
7625 format %{ "SRL $src1,$src2,$dst" %}
7626 opcode(Assembler::srl_op3, Assembler::arith_op);
7627 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7628 ins_pipe(ialu_reg_reg);
7629 %}
7630
7631 // Register Shift Right Immediate
7632 instruct shrI_reg_imm5(iRegI dst, iRegI src1, immU5 src2) %{
7633 match(Set dst (URShiftI src1 src2));
7634
7635 size(4);
7636 format %{ "SRL $src1,$src2,$dst" %}
7637 opcode(Assembler::srl_op3, Assembler::arith_op);
7638 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) );
7639 ins_pipe(ialu_reg_imm);
7640 %}
7641
7642 // Register Shift Right
7643 instruct shrL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{
7644 match(Set dst (URShiftL src1 src2));
7645
7646 size(4);
7647 format %{ "SRLX $src1,$src2,$dst" %}
7648 opcode(Assembler::srlx_op3, Assembler::arith_op);
7649 ins_encode( form3_sd_rs1_rs2_rd( src1, src2, dst ) );
7650 ins_pipe(ialu_reg_reg);
7651 %}
7652
7653 // Register Shift Right Immediate
7654 instruct shrL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{
7655 match(Set dst (URShiftL src1 src2));
7656
7657 size(4);
7658 format %{ "SRLX $src1,$src2,$dst" %}
7659 opcode(Assembler::srlx_op3, Assembler::arith_op);
7660 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) );
7661 ins_pipe(ialu_reg_imm);
7662 %}
7663
7664 // Register Shift Right Immediate with a CastP2X
7665 #ifdef _LP64
7666 instruct shrP_reg_imm6(iRegL dst, iRegP src1, immU6 src2) %{
7667 match(Set dst (URShiftL (CastP2X src1) src2));
7668 size(4);
7669 format %{ "SRLX $src1,$src2,$dst\t! Cast ptr $src1 to long and shift" %}
7670 opcode(Assembler::srlx_op3, Assembler::arith_op);
7671 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) );
7672 ins_pipe(ialu_reg_imm);
7673 %}
7674 #else
7675 instruct shrP_reg_imm5(iRegI dst, iRegP src1, immU5 src2) %{
7676 match(Set dst (URShiftI (CastP2X src1) src2));
7677 size(4);
7678 format %{ "SRL $src1,$src2,$dst\t! Cast ptr $src1 to int and shift" %}
7679 opcode(Assembler::srl_op3, Assembler::arith_op);
7680 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) );
7681 ins_pipe(ialu_reg_imm);
7682 %}
7683 #endif
7684
7685
7686 //----------Floating Point Arithmetic Instructions-----------------------------
7687
7688 // Add float single precision
7689 instruct addF_reg_reg(regF dst, regF src1, regF src2) %{
7690 match(Set dst (AddF src1 src2));
7691
7692 size(4);
7693 format %{ "FADDS $src1,$src2,$dst" %}
7694 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fadds_opf);
7695 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst));
7696 ins_pipe(faddF_reg_reg);
7697 %}
7698
7699 // Add float double precision
7700 instruct addD_reg_reg(regD dst, regD src1, regD src2) %{
7701 match(Set dst (AddD src1 src2));
7702
7703 size(4);
7704 format %{ "FADDD $src1,$src2,$dst" %}
7705 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::faddd_opf);
7706 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
7707 ins_pipe(faddD_reg_reg);
7708 %}
7709
7710 // Sub float single precision
7711 instruct subF_reg_reg(regF dst, regF src1, regF src2) %{
7712 match(Set dst (SubF src1 src2));
7713
7714 size(4);
7715 format %{ "FSUBS $src1,$src2,$dst" %}
7716 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fsubs_opf);
7717 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst));
7718 ins_pipe(faddF_reg_reg);
7719 %}
7720
7721 // Sub float double precision
7722 instruct subD_reg_reg(regD dst, regD src1, regD src2) %{
7723 match(Set dst (SubD src1 src2));
7724
7725 size(4);
7726 format %{ "FSUBD $src1,$src2,$dst" %}
7727 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fsubd_opf);
7728 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
7729 ins_pipe(faddD_reg_reg);
7730 %}
7731
7732 // Mul float single precision
7733 instruct mulF_reg_reg(regF dst, regF src1, regF src2) %{
7734 match(Set dst (MulF src1 src2));
7735
7736 size(4);
7737 format %{ "FMULS $src1,$src2,$dst" %}
7738 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmuls_opf);
7739 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst));
7740 ins_pipe(fmulF_reg_reg);
7741 %}
7742
7743 // Mul float double precision
7744 instruct mulD_reg_reg(regD dst, regD src1, regD src2) %{
7745 match(Set dst (MulD src1 src2));
7746
7747 size(4);
7748 format %{ "FMULD $src1,$src2,$dst" %}
7749 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmuld_opf);
7750 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
7751 ins_pipe(fmulD_reg_reg);
7752 %}
7753
7754 // Div float single precision
7755 instruct divF_reg_reg(regF dst, regF src1, regF src2) %{
7756 match(Set dst (DivF src1 src2));
7757
7758 size(4);
7759 format %{ "FDIVS $src1,$src2,$dst" %}
7760 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdivs_opf);
7761 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst));
7762 ins_pipe(fdivF_reg_reg);
7763 %}
7764
7765 // Div float double precision
7766 instruct divD_reg_reg(regD dst, regD src1, regD src2) %{
7767 match(Set dst (DivD src1 src2));
7768
7769 size(4);
7770 format %{ "FDIVD $src1,$src2,$dst" %}
7771 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdivd_opf);
7772 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
7773 ins_pipe(fdivD_reg_reg);
7774 %}
7775
7776 // Absolute float double precision
7777 instruct absD_reg(regD dst, regD src) %{
7778 match(Set dst (AbsD src));
7779
7780 format %{ "FABSd $src,$dst" %}
7781 ins_encode(fabsd(dst, src));
7782 ins_pipe(faddD_reg);
7783 %}
7784
7785 // Absolute float single precision
7786 instruct absF_reg(regF dst, regF src) %{
7787 match(Set dst (AbsF src));
7788
7789 format %{ "FABSs $src,$dst" %}
7790 ins_encode(fabss(dst, src));
7791 ins_pipe(faddF_reg);
7792 %}
7793
7794 instruct negF_reg(regF dst, regF src) %{
7795 match(Set dst (NegF src));
7796
7797 size(4);
7798 format %{ "FNEGs $src,$dst" %}
7799 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fnegs_opf);
7800 ins_encode(form3_opf_rs2F_rdF(src, dst));
7801 ins_pipe(faddF_reg);
7802 %}
7803
7804 instruct negD_reg(regD dst, regD src) %{
7805 match(Set dst (NegD src));
7806
7807 format %{ "FNEGd $src,$dst" %}
7808 ins_encode(fnegd(dst, src));
7809 ins_pipe(faddD_reg);
7810 %}
7811
7812 // Sqrt float double precision
7813 instruct sqrtF_reg_reg(regF dst, regF src) %{
7814 match(Set dst (ConvD2F (SqrtD (ConvF2D src))));
7815
7816 size(4);
7817 format %{ "FSQRTS $src,$dst" %}
7818 ins_encode(fsqrts(dst, src));
7819 ins_pipe(fdivF_reg_reg);
7820 %}
7821
7822 // Sqrt float double precision
7823 instruct sqrtD_reg_reg(regD dst, regD src) %{
7824 match(Set dst (SqrtD src));
7825
7826 size(4);
7827 format %{ "FSQRTD $src,$dst" %}
7828 ins_encode(fsqrtd(dst, src));
7829 ins_pipe(fdivD_reg_reg);
7830 %}
7831
7832 //----------Logical Instructions-----------------------------------------------
7833 // And Instructions
7834 // Register And
7835 instruct andI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7836 match(Set dst (AndI src1 src2));
7837
7838 size(4);
7839 format %{ "AND $src1,$src2,$dst" %}
7840 opcode(Assembler::and_op3, Assembler::arith_op);
7841 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7842 ins_pipe(ialu_reg_reg);
7843 %}
7844
7845 // Immediate And
7846 instruct andI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
7847 match(Set dst (AndI src1 src2));
7848
7849 size(4);
7850 format %{ "AND $src1,$src2,$dst" %}
7851 opcode(Assembler::and_op3, Assembler::arith_op);
7852 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7853 ins_pipe(ialu_reg_imm);
7854 %}
7855
7856 // Register And Long
7857 instruct andL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7858 match(Set dst (AndL src1 src2));
7859
7860 ins_cost(DEFAULT_COST);
7861 size(4);
7862 format %{ "AND $src1,$src2,$dst\t! long" %}
7863 opcode(Assembler::and_op3, Assembler::arith_op);
7864 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7865 ins_pipe(ialu_reg_reg);
7866 %}
7867
7868 instruct andL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{
7869 match(Set dst (AndL src1 con));
7870
7871 ins_cost(DEFAULT_COST);
7872 size(4);
7873 format %{ "AND $src1,$con,$dst\t! long" %}
7874 opcode(Assembler::and_op3, Assembler::arith_op);
7875 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
7876 ins_pipe(ialu_reg_imm);
7877 %}
7878
7879 // Or Instructions
7880 // Register Or
7881 instruct orI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7882 match(Set dst (OrI src1 src2));
7883
7884 size(4);
7885 format %{ "OR $src1,$src2,$dst" %}
7886 opcode(Assembler::or_op3, Assembler::arith_op);
7887 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7888 ins_pipe(ialu_reg_reg);
7889 %}
7890
7891 // Immediate Or
7892 instruct orI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
7893 match(Set dst (OrI src1 src2));
7894
7895 size(4);
7896 format %{ "OR $src1,$src2,$dst" %}
7897 opcode(Assembler::or_op3, Assembler::arith_op);
7898 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7899 ins_pipe(ialu_reg_imm);
7900 %}
7901
7902 // Register Or Long
7903 instruct orL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7904 match(Set dst (OrL src1 src2));
7905
7906 ins_cost(DEFAULT_COST);
7907 size(4);
7908 format %{ "OR $src1,$src2,$dst\t! long" %}
7909 opcode(Assembler::or_op3, Assembler::arith_op);
7910 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7911 ins_pipe(ialu_reg_reg);
7912 %}
7913
7914 instruct orL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{
7915 match(Set dst (OrL src1 con));
7916 ins_cost(DEFAULT_COST*2);
7917
7918 ins_cost(DEFAULT_COST);
7919 size(4);
7920 format %{ "OR $src1,$con,$dst\t! long" %}
7921 opcode(Assembler::or_op3, Assembler::arith_op);
7922 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
7923 ins_pipe(ialu_reg_imm);
7924 %}
7925
7926 #ifndef _LP64
7927
7928 // Use sp_ptr_RegP to match G2 (TLS register) without spilling.
7929 instruct orI_reg_castP2X(iRegI dst, iRegI src1, sp_ptr_RegP src2) %{
7930 match(Set dst (OrI src1 (CastP2X src2)));
7931
7932 size(4);
7933 format %{ "OR $src1,$src2,$dst" %}
7934 opcode(Assembler::or_op3, Assembler::arith_op);
7935 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7936 ins_pipe(ialu_reg_reg);
7937 %}
7938
7939 #else
7940
7941 instruct orL_reg_castP2X(iRegL dst, iRegL src1, sp_ptr_RegP src2) %{
7942 match(Set dst (OrL src1 (CastP2X src2)));
7943
7944 ins_cost(DEFAULT_COST);
7945 size(4);
7946 format %{ "OR $src1,$src2,$dst\t! long" %}
7947 opcode(Assembler::or_op3, Assembler::arith_op);
7948 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7949 ins_pipe(ialu_reg_reg);
7950 %}
7951
7952 #endif
7953
7954 // Xor Instructions
7955 // Register Xor
7956 instruct xorI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7957 match(Set dst (XorI src1 src2));
7958
7959 size(4);
7960 format %{ "XOR $src1,$src2,$dst" %}
7961 opcode(Assembler::xor_op3, Assembler::arith_op);
7962 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7963 ins_pipe(ialu_reg_reg);
7964 %}
7965
7966 // Immediate Xor
7967 instruct xorI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
7968 match(Set dst (XorI src1 src2));
7969
7970 size(4);
7971 format %{ "XOR $src1,$src2,$dst" %}
7972 opcode(Assembler::xor_op3, Assembler::arith_op);
7973 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7974 ins_pipe(ialu_reg_imm);
7975 %}
7976
7977 // Register Xor Long
7978 instruct xorL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7979 match(Set dst (XorL src1 src2));
7980
7981 ins_cost(DEFAULT_COST);
7982 size(4);
7983 format %{ "XOR $src1,$src2,$dst\t! long" %}
7984 opcode(Assembler::xor_op3, Assembler::arith_op);
7985 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7986 ins_pipe(ialu_reg_reg);
7987 %}
7988
7989 instruct xorL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{
7990 match(Set dst (XorL src1 con));
7991
7992 ins_cost(DEFAULT_COST);
7993 size(4);
7994 format %{ "XOR $src1,$con,$dst\t! long" %}
7995 opcode(Assembler::xor_op3, Assembler::arith_op);
7996 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
7997 ins_pipe(ialu_reg_imm);
7998 %}
7999
8000 //----------Convert to Boolean-------------------------------------------------
8001 // Nice hack for 32-bit tests but doesn't work for
8002 // 64-bit pointers.
8003 instruct convI2B( iRegI dst, iRegI src, flagsReg ccr ) %{
8004 match(Set dst (Conv2B src));
8005 effect( KILL ccr );
8006 ins_cost(DEFAULT_COST*2);
8007 format %{ "CMP R_G0,$src\n\t"
8008 "ADDX R_G0,0,$dst" %}
8009 ins_encode( enc_to_bool( src, dst ) );
8010 ins_pipe(ialu_reg_ialu);
8011 %}
8012
8013 #ifndef _LP64
8014 instruct convP2B( iRegI dst, iRegP src, flagsReg ccr ) %{
8015 match(Set dst (Conv2B src));
8016 effect( KILL ccr );
8017 ins_cost(DEFAULT_COST*2);
8018 format %{ "CMP R_G0,$src\n\t"
8019 "ADDX R_G0,0,$dst" %}
8020 ins_encode( enc_to_bool( src, dst ) );
8021 ins_pipe(ialu_reg_ialu);
8022 %}
8023 #else
8024 instruct convP2B( iRegI dst, iRegP src ) %{
8025 match(Set dst (Conv2B src));
8026 ins_cost(DEFAULT_COST*2);
8027 format %{ "MOV $src,$dst\n\t"
8028 "MOVRNZ $src,1,$dst" %}
8029 ins_encode( form3_g0_rs2_rd_move( src, dst ), enc_convP2B( dst, src ) );
8030 ins_pipe(ialu_clr_and_mover);
8031 %}
8032 #endif
8033
8034 instruct cmpLTMask0( iRegI dst, iRegI src, immI0 zero, flagsReg ccr ) %{
8035 match(Set dst (CmpLTMask src zero));
8036 effect(KILL ccr);
8037 size(4);
8038 format %{ "SRA $src,#31,$dst\t# cmpLTMask0" %}
8039 ins_encode %{
8040 __ sra($src$$Register, 31, $dst$$Register);
8041 %}
8042 ins_pipe(ialu_reg_imm);
8043 %}
8044
8045 instruct cmpLTMask_reg_reg( iRegI dst, iRegI p, iRegI q, flagsReg ccr ) %{
8046 match(Set dst (CmpLTMask p q));
8047 effect( KILL ccr );
8048 ins_cost(DEFAULT_COST*4);
8049 format %{ "CMP $p,$q\n\t"
8050 "MOV #0,$dst\n\t"
8051 "BLT,a .+8\n\t"
8052 "MOV #-1,$dst" %}
8053 ins_encode( enc_ltmask(p,q,dst) );
8054 ins_pipe(ialu_reg_reg_ialu);
8055 %}
8056
8057 instruct cadd_cmpLTMask( iRegI p, iRegI q, iRegI y, iRegI tmp, flagsReg ccr ) %{
8058 match(Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q)));
8059 effect(KILL ccr, TEMP tmp);
8060 ins_cost(DEFAULT_COST*3);
8061
8062 format %{ "SUBcc $p,$q,$p\t! p' = p-q\n\t"
8063 "ADD $p,$y,$tmp\t! g3=p-q+y\n\t"
8064 "MOVlt $tmp,$p\t! p' < 0 ? p'+y : p'" %}
8065 ins_encode(enc_cadd_cmpLTMask(p, q, y, tmp));
8066 ins_pipe(cadd_cmpltmask);
8067 %}
8068
8069 instruct and_cmpLTMask(iRegI p, iRegI q, iRegI y, flagsReg ccr) %{
8070 match(Set p (AndI (CmpLTMask p q) y));
8071 effect(KILL ccr);
8072 ins_cost(DEFAULT_COST*3);
8073
8074 format %{ "CMP $p,$q\n\t"
8075 "MOV $y,$p\n\t"
8076 "MOVge G0,$p" %}
8077 ins_encode %{
8078 __ cmp($p$$Register, $q$$Register);
8079 __ mov($y$$Register, $p$$Register);
8080 __ movcc(Assembler::greaterEqual, false, Assembler::icc, G0, $p$$Register);
8081 %}
8082 ins_pipe(ialu_reg_reg_ialu);
8083 %}
8084
8085 //-----------------------------------------------------------------
8086 // Direct raw moves between float and general registers using VIS3.
8087
8088 // ins_pipe(faddF_reg);
8089 instruct MoveF2I_reg_reg(iRegI dst, regF src) %{
8090 predicate(UseVIS >= 3);
8091 match(Set dst (MoveF2I src));
8092
8093 format %{ "MOVSTOUW $src,$dst\t! MoveF2I" %}
8094 ins_encode %{
8095 __ movstouw($src$$FloatRegister, $dst$$Register);
8096 %}
8097 ins_pipe(ialu_reg_reg);
8098 %}
8099
8100 instruct MoveI2F_reg_reg(regF dst, iRegI src) %{
8101 predicate(UseVIS >= 3);
8102 match(Set dst (MoveI2F src));
8103
8104 format %{ "MOVWTOS $src,$dst\t! MoveI2F" %}
8105 ins_encode %{
8106 __ movwtos($src$$Register, $dst$$FloatRegister);
8107 %}
8108 ins_pipe(ialu_reg_reg);
8109 %}
8110
8111 instruct MoveD2L_reg_reg(iRegL dst, regD src) %{
8112 predicate(UseVIS >= 3);
8113 match(Set dst (MoveD2L src));
8114
8115 format %{ "MOVDTOX $src,$dst\t! MoveD2L" %}
8116 ins_encode %{
8117 __ movdtox(as_DoubleFloatRegister($src$$reg), $dst$$Register);
8118 %}
8119 ins_pipe(ialu_reg_reg);
8120 %}
8121
8122 instruct MoveL2D_reg_reg(regD dst, iRegL src) %{
8123 predicate(UseVIS >= 3);
8124 match(Set dst (MoveL2D src));
8125
8126 format %{ "MOVXTOD $src,$dst\t! MoveL2D" %}
8127 ins_encode %{
8128 __ movxtod($src$$Register, as_DoubleFloatRegister($dst$$reg));
8129 %}
8130 ins_pipe(ialu_reg_reg);
8131 %}
8132
8133
8134 // Raw moves between float and general registers using stack.
8135
8136 instruct MoveF2I_stack_reg(iRegI dst, stackSlotF src) %{
8137 match(Set dst (MoveF2I src));
8138 effect(DEF dst, USE src);
8139 ins_cost(MEMORY_REF_COST);
8140
8141 size(4);
8142 format %{ "LDUW $src,$dst\t! MoveF2I" %}
8143 opcode(Assembler::lduw_op3);
8144 ins_encode(simple_form3_mem_reg( src, dst ) );
8145 ins_pipe(iload_mem);
8146 %}
8147
8148 instruct MoveI2F_stack_reg(regF dst, stackSlotI src) %{
8149 match(Set dst (MoveI2F src));
8150 effect(DEF dst, USE src);
8151 ins_cost(MEMORY_REF_COST);
8152
8153 size(4);
8154 format %{ "LDF $src,$dst\t! MoveI2F" %}
8155 opcode(Assembler::ldf_op3);
8156 ins_encode(simple_form3_mem_reg(src, dst));
8157 ins_pipe(floadF_stk);
8158 %}
8159
8160 instruct MoveD2L_stack_reg(iRegL dst, stackSlotD src) %{
8161 match(Set dst (MoveD2L src));
8162 effect(DEF dst, USE src);
8163 ins_cost(MEMORY_REF_COST);
8164
8165 size(4);
8166 format %{ "LDX $src,$dst\t! MoveD2L" %}
8167 opcode(Assembler::ldx_op3);
8168 ins_encode(simple_form3_mem_reg( src, dst ) );
8169 ins_pipe(iload_mem);
8170 %}
8171
8172 instruct MoveL2D_stack_reg(regD dst, stackSlotL src) %{
8173 match(Set dst (MoveL2D src));
8174 effect(DEF dst, USE src);
8175 ins_cost(MEMORY_REF_COST);
8176
8177 size(4);
8178 format %{ "LDDF $src,$dst\t! MoveL2D" %}
8179 opcode(Assembler::lddf_op3);
8180 ins_encode(simple_form3_mem_reg(src, dst));
8181 ins_pipe(floadD_stk);
8182 %}
8183
8184 instruct MoveF2I_reg_stack(stackSlotI dst, regF src) %{
8185 match(Set dst (MoveF2I src));
8186 effect(DEF dst, USE src);
8187 ins_cost(MEMORY_REF_COST);
8188
8189 size(4);
8190 format %{ "STF $src,$dst\t! MoveF2I" %}
8191 opcode(Assembler::stf_op3);
8192 ins_encode(simple_form3_mem_reg(dst, src));
8193 ins_pipe(fstoreF_stk_reg);
8194 %}
8195
8196 instruct MoveI2F_reg_stack(stackSlotF dst, iRegI src) %{
8197 match(Set dst (MoveI2F src));
8198 effect(DEF dst, USE src);
8199 ins_cost(MEMORY_REF_COST);
8200
8201 size(4);
8202 format %{ "STW $src,$dst\t! MoveI2F" %}
8203 opcode(Assembler::stw_op3);
8204 ins_encode(simple_form3_mem_reg( dst, src ) );
8205 ins_pipe(istore_mem_reg);
8206 %}
8207
8208 instruct MoveD2L_reg_stack(stackSlotL dst, regD src) %{
8209 match(Set dst (MoveD2L src));
8210 effect(DEF dst, USE src);
8211 ins_cost(MEMORY_REF_COST);
8212
8213 size(4);
8214 format %{ "STDF $src,$dst\t! MoveD2L" %}
8215 opcode(Assembler::stdf_op3);
8216 ins_encode(simple_form3_mem_reg(dst, src));
8217 ins_pipe(fstoreD_stk_reg);
8218 %}
8219
8220 instruct MoveL2D_reg_stack(stackSlotD dst, iRegL src) %{
8221 match(Set dst (MoveL2D src));
8222 effect(DEF dst, USE src);
8223 ins_cost(MEMORY_REF_COST);
8224
8225 size(4);
8226 format %{ "STX $src,$dst\t! MoveL2D" %}
8227 opcode(Assembler::stx_op3);
8228 ins_encode(simple_form3_mem_reg( dst, src ) );
8229 ins_pipe(istore_mem_reg);
8230 %}
8231
8232
8233 //----------Arithmetic Conversion Instructions---------------------------------
8234 // The conversions operations are all Alpha sorted. Please keep it that way!
8235
8236 instruct convD2F_reg(regF dst, regD src) %{
8237 match(Set dst (ConvD2F src));
8238 size(4);
8239 format %{ "FDTOS $src,$dst" %}
8240 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdtos_opf);
8241 ins_encode(form3_opf_rs2D_rdF(src, dst));
8242 ins_pipe(fcvtD2F);
8243 %}
8244
8245
8246 // Convert a double to an int in a float register.
8247 // If the double is a NAN, stuff a zero in instead.
8248 instruct convD2I_helper(regF dst, regD src, flagsRegF0 fcc0) %{
8249 effect(DEF dst, USE src, KILL fcc0);
8250 format %{ "FCMPd fcc0,$src,$src\t! check for NAN\n\t"
8251 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t"
8252 "FDTOI $src,$dst\t! convert in delay slot\n\t"
8253 "FITOS $dst,$dst\t! change NaN/max-int to valid float\n\t"
8254 "FSUBs $dst,$dst,$dst\t! cleared only if nan\n"
8255 "skip:" %}
8256 ins_encode(form_d2i_helper(src,dst));
8257 ins_pipe(fcvtD2I);
8258 %}
8259
8260 instruct convD2I_stk(stackSlotI dst, regD src) %{
8261 match(Set dst (ConvD2I src));
8262 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST);
8263 expand %{
8264 regF tmp;
8265 convD2I_helper(tmp, src);
8266 regF_to_stkI(dst, tmp);
8267 %}
8268 %}
8269
8270 instruct convD2I_reg(iRegI dst, regD src) %{
8271 predicate(UseVIS >= 3);
8272 match(Set dst (ConvD2I src));
8273 ins_cost(DEFAULT_COST*2 + BRANCH_COST);
8274 expand %{
8275 regF tmp;
8276 convD2I_helper(tmp, src);
8277 MoveF2I_reg_reg(dst, tmp);
8278 %}
8279 %}
8280
8281
8282 // Convert a double to a long in a double register.
8283 // If the double is a NAN, stuff a zero in instead.
8284 instruct convD2L_helper(regD dst, regD src, flagsRegF0 fcc0) %{
8285 effect(DEF dst, USE src, KILL fcc0);
8286 format %{ "FCMPd fcc0,$src,$src\t! check for NAN\n\t"
8287 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t"
8288 "FDTOX $src,$dst\t! convert in delay slot\n\t"
8289 "FXTOD $dst,$dst\t! change NaN/max-long to valid double\n\t"
8290 "FSUBd $dst,$dst,$dst\t! cleared only if nan\n"
8291 "skip:" %}
8292 ins_encode(form_d2l_helper(src,dst));
8293 ins_pipe(fcvtD2L);
8294 %}
8295
8296 instruct convD2L_stk(stackSlotL dst, regD src) %{
8297 match(Set dst (ConvD2L src));
8298 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST);
8299 expand %{
8300 regD tmp;
8301 convD2L_helper(tmp, src);
8302 regD_to_stkL(dst, tmp);
8303 %}
8304 %}
8305
8306 instruct convD2L_reg(iRegL dst, regD src) %{
8307 predicate(UseVIS >= 3);
8308 match(Set dst (ConvD2L src));
8309 ins_cost(DEFAULT_COST*2 + BRANCH_COST);
8310 expand %{
8311 regD tmp;
8312 convD2L_helper(tmp, src);
8313 MoveD2L_reg_reg(dst, tmp);
8314 %}
8315 %}
8316
8317
8318 instruct convF2D_reg(regD dst, regF src) %{
8319 match(Set dst (ConvF2D src));
8320 format %{ "FSTOD $src,$dst" %}
8321 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fstod_opf);
8322 ins_encode(form3_opf_rs2F_rdD(src, dst));
8323 ins_pipe(fcvtF2D);
8324 %}
8325
8326
8327 // Convert a float to an int in a float register.
8328 // If the float is a NAN, stuff a zero in instead.
8329 instruct convF2I_helper(regF dst, regF src, flagsRegF0 fcc0) %{
8330 effect(DEF dst, USE src, KILL fcc0);
8331 format %{ "FCMPs fcc0,$src,$src\t! check for NAN\n\t"
8332 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t"
8333 "FSTOI $src,$dst\t! convert in delay slot\n\t"
8334 "FITOS $dst,$dst\t! change NaN/max-int to valid float\n\t"
8335 "FSUBs $dst,$dst,$dst\t! cleared only if nan\n"
8336 "skip:" %}
8337 ins_encode(form_f2i_helper(src,dst));
8338 ins_pipe(fcvtF2I);
8339 %}
8340
8341 instruct convF2I_stk(stackSlotI dst, regF src) %{
8342 match(Set dst (ConvF2I src));
8343 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST);
8344 expand %{
8345 regF tmp;
8346 convF2I_helper(tmp, src);
8347 regF_to_stkI(dst, tmp);
8348 %}
8349 %}
8350
8351 instruct convF2I_reg(iRegI dst, regF src) %{
8352 predicate(UseVIS >= 3);
8353 match(Set dst (ConvF2I src));
8354 ins_cost(DEFAULT_COST*2 + BRANCH_COST);
8355 expand %{
8356 regF tmp;
8357 convF2I_helper(tmp, src);
8358 MoveF2I_reg_reg(dst, tmp);
8359 %}
8360 %}
8361
8362
8363 // Convert a float to a long in a float register.
8364 // If the float is a NAN, stuff a zero in instead.
8365 instruct convF2L_helper(regD dst, regF src, flagsRegF0 fcc0) %{
8366 effect(DEF dst, USE src, KILL fcc0);
8367 format %{ "FCMPs fcc0,$src,$src\t! check for NAN\n\t"
8368 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t"
8369 "FSTOX $src,$dst\t! convert in delay slot\n\t"
8370 "FXTOD $dst,$dst\t! change NaN/max-long to valid double\n\t"
8371 "FSUBd $dst,$dst,$dst\t! cleared only if nan\n"
8372 "skip:" %}
8373 ins_encode(form_f2l_helper(src,dst));
8374 ins_pipe(fcvtF2L);
8375 %}
8376
8377 instruct convF2L_stk(stackSlotL dst, regF src) %{
8378 match(Set dst (ConvF2L src));
8379 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST);
8380 expand %{
8381 regD tmp;
8382 convF2L_helper(tmp, src);
8383 regD_to_stkL(dst, tmp);
8384 %}
8385 %}
8386
8387 instruct convF2L_reg(iRegL dst, regF src) %{
8388 predicate(UseVIS >= 3);
8389 match(Set dst (ConvF2L src));
8390 ins_cost(DEFAULT_COST*2 + BRANCH_COST);
8391 expand %{
8392 regD tmp;
8393 convF2L_helper(tmp, src);
8394 MoveD2L_reg_reg(dst, tmp);
8395 %}
8396 %}
8397
8398
8399 instruct convI2D_helper(regD dst, regF tmp) %{
8400 effect(USE tmp, DEF dst);
8401 format %{ "FITOD $tmp,$dst" %}
8402 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitod_opf);
8403 ins_encode(form3_opf_rs2F_rdD(tmp, dst));
8404 ins_pipe(fcvtI2D);
8405 %}
8406
8407 instruct convI2D_stk(stackSlotI src, regD dst) %{
8408 match(Set dst (ConvI2D src));
8409 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
8410 expand %{
8411 regF tmp;
8412 stkI_to_regF(tmp, src);
8413 convI2D_helper(dst, tmp);
8414 %}
8415 %}
8416
8417 instruct convI2D_reg(regD_low dst, iRegI src) %{
8418 predicate(UseVIS >= 3);
8419 match(Set dst (ConvI2D src));
8420 expand %{
8421 regF tmp;
8422 MoveI2F_reg_reg(tmp, src);
8423 convI2D_helper(dst, tmp);
8424 %}
8425 %}
8426
8427 instruct convI2D_mem(regD_low dst, memory mem) %{
8428 match(Set dst (ConvI2D (LoadI mem)));
8429 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
8430 size(8);
8431 format %{ "LDF $mem,$dst\n\t"
8432 "FITOD $dst,$dst" %}
8433 opcode(Assembler::ldf_op3, Assembler::fitod_opf);
8434 ins_encode(simple_form3_mem_reg( mem, dst ), form3_convI2F(dst, dst));
8435 ins_pipe(floadF_mem);
8436 %}
8437
8438
8439 instruct convI2F_helper(regF dst, regF tmp) %{
8440 effect(DEF dst, USE tmp);
8441 format %{ "FITOS $tmp,$dst" %}
8442 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitos_opf);
8443 ins_encode(form3_opf_rs2F_rdF(tmp, dst));
8444 ins_pipe(fcvtI2F);
8445 %}
8446
8447 instruct convI2F_stk(regF dst, stackSlotI src) %{
8448 match(Set dst (ConvI2F src));
8449 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
8450 expand %{
8451 regF tmp;
8452 stkI_to_regF(tmp,src);
8453 convI2F_helper(dst, tmp);
8454 %}
8455 %}
8456
8457 instruct convI2F_reg(regF dst, iRegI src) %{
8458 predicate(UseVIS >= 3);
8459 match(Set dst (ConvI2F src));
8460 ins_cost(DEFAULT_COST);
8461 expand %{
8462 regF tmp;
8463 MoveI2F_reg_reg(tmp, src);
8464 convI2F_helper(dst, tmp);
8465 %}
8466 %}
8467
8468 instruct convI2F_mem( regF dst, memory mem ) %{
8469 match(Set dst (ConvI2F (LoadI mem)));
8470 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
8471 size(8);
8472 format %{ "LDF $mem,$dst\n\t"
8473 "FITOS $dst,$dst" %}
8474 opcode(Assembler::ldf_op3, Assembler::fitos_opf);
8475 ins_encode(simple_form3_mem_reg( mem, dst ), form3_convI2F(dst, dst));
8476 ins_pipe(floadF_mem);
8477 %}
8478
8479
8480 instruct convI2L_reg(iRegL dst, iRegI src) %{
8481 match(Set dst (ConvI2L src));
8482 size(4);
8483 format %{ "SRA $src,0,$dst\t! int->long" %}
8484 opcode(Assembler::sra_op3, Assembler::arith_op);
8485 ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) );
8486 ins_pipe(ialu_reg_reg);
8487 %}
8488
8489 // Zero-extend convert int to long
8490 instruct convI2L_reg_zex(iRegL dst, iRegI src, immL_32bits mask ) %{
8491 match(Set dst (AndL (ConvI2L src) mask) );
8492 size(4);
8493 format %{ "SRL $src,0,$dst\t! zero-extend int to long" %}
8494 opcode(Assembler::srl_op3, Assembler::arith_op);
8495 ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) );
8496 ins_pipe(ialu_reg_reg);
8497 %}
8498
8499 // Zero-extend long
8500 instruct zerox_long(iRegL dst, iRegL src, immL_32bits mask ) %{
8501 match(Set dst (AndL src mask) );
8502 size(4);
8503 format %{ "SRL $src,0,$dst\t! zero-extend long" %}
8504 opcode(Assembler::srl_op3, Assembler::arith_op);
8505 ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) );
8506 ins_pipe(ialu_reg_reg);
8507 %}
8508
8509
8510 //-----------
8511 // Long to Double conversion using V8 opcodes.
8512 // Still useful because cheetah traps and becomes
8513 // amazingly slow for some common numbers.
8514
8515 // Magic constant, 0x43300000
8516 instruct loadConI_x43300000(iRegI dst) %{
8517 effect(DEF dst);
8518 size(4);
8519 format %{ "SETHI HI(0x43300000),$dst\t! 2^52" %}
8520 ins_encode(SetHi22(0x43300000, dst));
8521 ins_pipe(ialu_none);
8522 %}
8523
8524 // Magic constant, 0x41f00000
8525 instruct loadConI_x41f00000(iRegI dst) %{
8526 effect(DEF dst);
8527 size(4);
8528 format %{ "SETHI HI(0x41f00000),$dst\t! 2^32" %}
8529 ins_encode(SetHi22(0x41f00000, dst));
8530 ins_pipe(ialu_none);
8531 %}
8532
8533 // Construct a double from two float halves
8534 instruct regDHi_regDLo_to_regD(regD_low dst, regD_low src1, regD_low src2) %{
8535 effect(DEF dst, USE src1, USE src2);
8536 size(8);
8537 format %{ "FMOVS $src1.hi,$dst.hi\n\t"
8538 "FMOVS $src2.lo,$dst.lo" %}
8539 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmovs_opf);
8540 ins_encode(form3_opf_rs2D_hi_rdD_hi(src1, dst), form3_opf_rs2D_lo_rdD_lo(src2, dst));
8541 ins_pipe(faddD_reg_reg);
8542 %}
8543
8544 // Convert integer in high half of a double register (in the lower half of
8545 // the double register file) to double
8546 instruct convI2D_regDHi_regD(regD dst, regD_low src) %{
8547 effect(DEF dst, USE src);
8548 size(4);
8549 format %{ "FITOD $src,$dst" %}
8550 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitod_opf);
8551 ins_encode(form3_opf_rs2D_rdD(src, dst));
8552 ins_pipe(fcvtLHi2D);
8553 %}
8554
8555 // Add float double precision
8556 instruct addD_regD_regD(regD dst, regD src1, regD src2) %{
8557 effect(DEF dst, USE src1, USE src2);
8558 size(4);
8559 format %{ "FADDD $src1,$src2,$dst" %}
8560 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::faddd_opf);
8561 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
8562 ins_pipe(faddD_reg_reg);
8563 %}
8564
8565 // Sub float double precision
8566 instruct subD_regD_regD(regD dst, regD src1, regD src2) %{
8567 effect(DEF dst, USE src1, USE src2);
8568 size(4);
8569 format %{ "FSUBD $src1,$src2,$dst" %}
8570 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fsubd_opf);
8571 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
8572 ins_pipe(faddD_reg_reg);
8573 %}
8574
8575 // Mul float double precision
8576 instruct mulD_regD_regD(regD dst, regD src1, regD src2) %{
8577 effect(DEF dst, USE src1, USE src2);
8578 size(4);
8579 format %{ "FMULD $src1,$src2,$dst" %}
8580 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmuld_opf);
8581 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
8582 ins_pipe(fmulD_reg_reg);
8583 %}
8584
8585 instruct convL2D_reg_slow_fxtof(regD dst, stackSlotL src) %{
8586 match(Set dst (ConvL2D src));
8587 ins_cost(DEFAULT_COST*8 + MEMORY_REF_COST*6);
8588
8589 expand %{
8590 regD_low tmpsrc;
8591 iRegI ix43300000;
8592 iRegI ix41f00000;
8593 stackSlotL lx43300000;
8594 stackSlotL lx41f00000;
8595 regD_low dx43300000;
8596 regD dx41f00000;
8597 regD tmp1;
8598 regD_low tmp2;
8599 regD tmp3;
8600 regD tmp4;
8601
8602 stkL_to_regD(tmpsrc, src);
8603
8604 loadConI_x43300000(ix43300000);
8605 loadConI_x41f00000(ix41f00000);
8606 regI_to_stkLHi(lx43300000, ix43300000);
8607 regI_to_stkLHi(lx41f00000, ix41f00000);
8608 stkL_to_regD(dx43300000, lx43300000);
8609 stkL_to_regD(dx41f00000, lx41f00000);
8610
8611 convI2D_regDHi_regD(tmp1, tmpsrc);
8612 regDHi_regDLo_to_regD(tmp2, dx43300000, tmpsrc);
8613 subD_regD_regD(tmp3, tmp2, dx43300000);
8614 mulD_regD_regD(tmp4, tmp1, dx41f00000);
8615 addD_regD_regD(dst, tmp3, tmp4);
8616 %}
8617 %}
8618
8619 // Long to Double conversion using fast fxtof
8620 instruct convL2D_helper(regD dst, regD tmp) %{
8621 effect(DEF dst, USE tmp);
8622 size(4);
8623 format %{ "FXTOD $tmp,$dst" %}
8624 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fxtod_opf);
8625 ins_encode(form3_opf_rs2D_rdD(tmp, dst));
8626 ins_pipe(fcvtL2D);
8627 %}
8628
8629 instruct convL2D_stk_fast_fxtof(regD dst, stackSlotL src) %{
8630 predicate(VM_Version::has_fast_fxtof());
8631 match(Set dst (ConvL2D src));
8632 ins_cost(DEFAULT_COST + 3 * MEMORY_REF_COST);
8633 expand %{
8634 regD tmp;
8635 stkL_to_regD(tmp, src);
8636 convL2D_helper(dst, tmp);
8637 %}
8638 %}
8639
8640 instruct convL2D_reg(regD dst, iRegL src) %{
8641 predicate(UseVIS >= 3);
8642 match(Set dst (ConvL2D src));
8643 expand %{
8644 regD tmp;
8645 MoveL2D_reg_reg(tmp, src);
8646 convL2D_helper(dst, tmp);
8647 %}
8648 %}
8649
8650 // Long to Float conversion using fast fxtof
8651 instruct convL2F_helper(regF dst, regD tmp) %{
8652 effect(DEF dst, USE tmp);
8653 size(4);
8654 format %{ "FXTOS $tmp,$dst" %}
8655 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fxtos_opf);
8656 ins_encode(form3_opf_rs2D_rdF(tmp, dst));
8657 ins_pipe(fcvtL2F);
8658 %}
8659
8660 instruct convL2F_stk_fast_fxtof(regF dst, stackSlotL src) %{
8661 match(Set dst (ConvL2F src));
8662 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
8663 expand %{
8664 regD tmp;
8665 stkL_to_regD(tmp, src);
8666 convL2F_helper(dst, tmp);
8667 %}
8668 %}
8669
8670 instruct convL2F_reg(regF dst, iRegL src) %{
8671 predicate(UseVIS >= 3);
8672 match(Set dst (ConvL2F src));
8673 ins_cost(DEFAULT_COST);
8674 expand %{
8675 regD tmp;
8676 MoveL2D_reg_reg(tmp, src);
8677 convL2F_helper(dst, tmp);
8678 %}
8679 %}
8680
8681 //-----------
8682
8683 instruct convL2I_reg(iRegI dst, iRegL src) %{
8684 match(Set dst (ConvL2I src));
8685 #ifndef _LP64
8686 format %{ "MOV $src.lo,$dst\t! long->int" %}
8687 ins_encode( form3_g0_rs2_rd_move_lo2( src, dst ) );
8688 ins_pipe(ialu_move_reg_I_to_L);
8689 #else
8690 size(4);
8691 format %{ "SRA $src,R_G0,$dst\t! long->int" %}
8692 ins_encode( form3_rs1_rd_signextend_lo1( src, dst ) );
8693 ins_pipe(ialu_reg);
8694 #endif
8695 %}
8696
8697 // Register Shift Right Immediate
8698 instruct shrL_reg_imm6_L2I(iRegI dst, iRegL src, immI_32_63 cnt) %{
8699 match(Set dst (ConvL2I (RShiftL src cnt)));
8700
8701 size(4);
8702 format %{ "SRAX $src,$cnt,$dst" %}
8703 opcode(Assembler::srax_op3, Assembler::arith_op);
8704 ins_encode( form3_sd_rs1_imm6_rd( src, cnt, dst ) );
8705 ins_pipe(ialu_reg_imm);
8706 %}
8707
8708 //----------Control Flow Instructions------------------------------------------
8709 // Compare Instructions
8710 // Compare Integers
8711 instruct compI_iReg(flagsReg icc, iRegI op1, iRegI op2) %{
8712 match(Set icc (CmpI op1 op2));
8713 effect( DEF icc, USE op1, USE op2 );
8714
8715 size(4);
8716 format %{ "CMP $op1,$op2" %}
8717 opcode(Assembler::subcc_op3, Assembler::arith_op);
8718 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8719 ins_pipe(ialu_cconly_reg_reg);
8720 %}
8721
8722 instruct compU_iReg(flagsRegU icc, iRegI op1, iRegI op2) %{
8723 match(Set icc (CmpU op1 op2));
8724
8725 size(4);
8726 format %{ "CMP $op1,$op2\t! unsigned" %}
8727 opcode(Assembler::subcc_op3, Assembler::arith_op);
8728 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8729 ins_pipe(ialu_cconly_reg_reg);
8730 %}
8731
8732 instruct compI_iReg_imm13(flagsReg icc, iRegI op1, immI13 op2) %{
8733 match(Set icc (CmpI op1 op2));
8734 effect( DEF icc, USE op1 );
8735
8736 size(4);
8737 format %{ "CMP $op1,$op2" %}
8738 opcode(Assembler::subcc_op3, Assembler::arith_op);
8739 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
8740 ins_pipe(ialu_cconly_reg_imm);
8741 %}
8742
8743 instruct testI_reg_reg( flagsReg icc, iRegI op1, iRegI op2, immI0 zero ) %{
8744 match(Set icc (CmpI (AndI op1 op2) zero));
8745
8746 size(4);
8747 format %{ "BTST $op2,$op1" %}
8748 opcode(Assembler::andcc_op3, Assembler::arith_op);
8749 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8750 ins_pipe(ialu_cconly_reg_reg_zero);
8751 %}
8752
8753 instruct testI_reg_imm( flagsReg icc, iRegI op1, immI13 op2, immI0 zero ) %{
8754 match(Set icc (CmpI (AndI op1 op2) zero));
8755
8756 size(4);
8757 format %{ "BTST $op2,$op1" %}
8758 opcode(Assembler::andcc_op3, Assembler::arith_op);
8759 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
8760 ins_pipe(ialu_cconly_reg_imm_zero);
8761 %}
8762
8763 instruct compL_reg_reg(flagsRegL xcc, iRegL op1, iRegL op2 ) %{
8764 match(Set xcc (CmpL op1 op2));
8765 effect( DEF xcc, USE op1, USE op2 );
8766
8767 size(4);
8768 format %{ "CMP $op1,$op2\t\t! long" %}
8769 opcode(Assembler::subcc_op3, Assembler::arith_op);
8770 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8771 ins_pipe(ialu_cconly_reg_reg);
8772 %}
8773
8774 instruct compL_reg_con(flagsRegL xcc, iRegL op1, immL13 con) %{
8775 match(Set xcc (CmpL op1 con));
8776 effect( DEF xcc, USE op1, USE con );
8777
8778 size(4);
8779 format %{ "CMP $op1,$con\t\t! long" %}
8780 opcode(Assembler::subcc_op3, Assembler::arith_op);
8781 ins_encode( form3_rs1_simm13_rd( op1, con, R_G0 ) );
8782 ins_pipe(ialu_cconly_reg_reg);
8783 %}
8784
8785 instruct testL_reg_reg(flagsRegL xcc, iRegL op1, iRegL op2, immL0 zero) %{
8786 match(Set xcc (CmpL (AndL op1 op2) zero));
8787 effect( DEF xcc, USE op1, USE op2 );
8788
8789 size(4);
8790 format %{ "BTST $op1,$op2\t\t! long" %}
8791 opcode(Assembler::andcc_op3, Assembler::arith_op);
8792 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8793 ins_pipe(ialu_cconly_reg_reg);
8794 %}
8795
8796 // useful for checking the alignment of a pointer:
8797 instruct testL_reg_con(flagsRegL xcc, iRegL op1, immL13 con, immL0 zero) %{
8798 match(Set xcc (CmpL (AndL op1 con) zero));
8799 effect( DEF xcc, USE op1, USE con );
8800
8801 size(4);
8802 format %{ "BTST $op1,$con\t\t! long" %}
8803 opcode(Assembler::andcc_op3, Assembler::arith_op);
8804 ins_encode( form3_rs1_simm13_rd( op1, con, R_G0 ) );
8805 ins_pipe(ialu_cconly_reg_reg);
8806 %}
8807
8808 instruct compU_iReg_imm13(flagsRegU icc, iRegI op1, immU12 op2 ) %{
8809 match(Set icc (CmpU op1 op2));
8810
8811 size(4);
8812 format %{ "CMP $op1,$op2\t! unsigned" %}
8813 opcode(Assembler::subcc_op3, Assembler::arith_op);
8814 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
8815 ins_pipe(ialu_cconly_reg_imm);
8816 %}
8817
8818 // Compare Pointers
8819 instruct compP_iRegP(flagsRegP pcc, iRegP op1, iRegP op2 ) %{
8820 match(Set pcc (CmpP op1 op2));
8821
8822 size(4);
8823 format %{ "CMP $op1,$op2\t! ptr" %}
8824 opcode(Assembler::subcc_op3, Assembler::arith_op);
8825 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8826 ins_pipe(ialu_cconly_reg_reg);
8827 %}
8828
8829 instruct compP_iRegP_imm13(flagsRegP pcc, iRegP op1, immP13 op2 ) %{
8830 match(Set pcc (CmpP op1 op2));
8831
8832 size(4);
8833 format %{ "CMP $op1,$op2\t! ptr" %}
8834 opcode(Assembler::subcc_op3, Assembler::arith_op);
8835 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
8836 ins_pipe(ialu_cconly_reg_imm);
8837 %}
8838
8839 // Compare Narrow oops
8840 instruct compN_iRegN(flagsReg icc, iRegN op1, iRegN op2 ) %{
8841 match(Set icc (CmpN op1 op2));
8842
8843 size(4);
8844 format %{ "CMP $op1,$op2\t! compressed ptr" %}
8845 opcode(Assembler::subcc_op3, Assembler::arith_op);
8846 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8847 ins_pipe(ialu_cconly_reg_reg);
8848 %}
8849
8850 instruct compN_iRegN_immN0(flagsReg icc, iRegN op1, immN0 op2 ) %{
8851 match(Set icc (CmpN op1 op2));
8852
8853 size(4);
8854 format %{ "CMP $op1,$op2\t! compressed ptr" %}
8855 opcode(Assembler::subcc_op3, Assembler::arith_op);
8856 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
8857 ins_pipe(ialu_cconly_reg_imm);
8858 %}
8859
8860 //----------Max and Min--------------------------------------------------------
8861 // Min Instructions
8862 // Conditional move for min
8863 instruct cmovI_reg_lt( iRegI op2, iRegI op1, flagsReg icc ) %{
8864 effect( USE_DEF op2, USE op1, USE icc );
8865
8866 size(4);
8867 format %{ "MOVlt icc,$op1,$op2\t! min" %}
8868 opcode(Assembler::less);
8869 ins_encode( enc_cmov_reg_minmax(op2,op1) );
8870 ins_pipe(ialu_reg_flags);
8871 %}
8872
8873 // Min Register with Register.
8874 instruct minI_eReg(iRegI op1, iRegI op2) %{
8875 match(Set op2 (MinI op1 op2));
8876 ins_cost(DEFAULT_COST*2);
8877 expand %{
8878 flagsReg icc;
8879 compI_iReg(icc,op1,op2);
8880 cmovI_reg_lt(op2,op1,icc);
8881 %}
8882 %}
8883
8884 // Max Instructions
8885 // Conditional move for max
8886 instruct cmovI_reg_gt( iRegI op2, iRegI op1, flagsReg icc ) %{
8887 effect( USE_DEF op2, USE op1, USE icc );
8888 format %{ "MOVgt icc,$op1,$op2\t! max" %}
8889 opcode(Assembler::greater);
8890 ins_encode( enc_cmov_reg_minmax(op2,op1) );
8891 ins_pipe(ialu_reg_flags);
8892 %}
8893
8894 // Max Register with Register
8895 instruct maxI_eReg(iRegI op1, iRegI op2) %{
8896 match(Set op2 (MaxI op1 op2));
8897 ins_cost(DEFAULT_COST*2);
8898 expand %{
8899 flagsReg icc;
8900 compI_iReg(icc,op1,op2);
8901 cmovI_reg_gt(op2,op1,icc);
8902 %}
8903 %}
8904
8905
8906 //----------Float Compares----------------------------------------------------
8907 // Compare floating, generate condition code
8908 instruct cmpF_cc(flagsRegF fcc, regF src1, regF src2) %{
8909 match(Set fcc (CmpF src1 src2));
8910
8911 size(4);
8912 format %{ "FCMPs $fcc,$src1,$src2" %}
8913 opcode(Assembler::fpop2_op3, Assembler::arith_op, Assembler::fcmps_opf);
8914 ins_encode( form3_opf_rs1F_rs2F_fcc( src1, src2, fcc ) );
8915 ins_pipe(faddF_fcc_reg_reg_zero);
8916 %}
8917
8918 instruct cmpD_cc(flagsRegF fcc, regD src1, regD src2) %{
8919 match(Set fcc (CmpD src1 src2));
8920
8921 size(4);
8922 format %{ "FCMPd $fcc,$src1,$src2" %}
8923 opcode(Assembler::fpop2_op3, Assembler::arith_op, Assembler::fcmpd_opf);
8924 ins_encode( form3_opf_rs1D_rs2D_fcc( src1, src2, fcc ) );
8925 ins_pipe(faddD_fcc_reg_reg_zero);
8926 %}
8927
8928
8929 // Compare floating, generate -1,0,1
8930 instruct cmpF_reg(iRegI dst, regF src1, regF src2, flagsRegF0 fcc0) %{
8931 match(Set dst (CmpF3 src1 src2));
8932 effect(KILL fcc0);
8933 ins_cost(DEFAULT_COST*3+BRANCH_COST*3);
8934 format %{ "fcmpl $dst,$src1,$src2" %}
8935 // Primary = float
8936 opcode( true );
8937 ins_encode( floating_cmp( dst, src1, src2 ) );
8938 ins_pipe( floating_cmp );
8939 %}
8940
8941 instruct cmpD_reg(iRegI dst, regD src1, regD src2, flagsRegF0 fcc0) %{
8942 match(Set dst (CmpD3 src1 src2));
8943 effect(KILL fcc0);
8944 ins_cost(DEFAULT_COST*3+BRANCH_COST*3);
8945 format %{ "dcmpl $dst,$src1,$src2" %}
8946 // Primary = double (not float)
8947 opcode( false );
8948 ins_encode( floating_cmp( dst, src1, src2 ) );
8949 ins_pipe( floating_cmp );
8950 %}
8951
8952 //----------Branches---------------------------------------------------------
8953 // Jump
8954 // (compare 'operand indIndex' and 'instruct addP_reg_reg' above)
8955 instruct jumpXtnd(iRegX switch_val, o7RegI table) %{
8956 match(Jump switch_val);
8957 effect(TEMP table);
8958
8959 ins_cost(350);
8960
8961 format %{ "ADD $constanttablebase, $constantoffset, O7\n\t"
8962 "LD [O7 + $switch_val], O7\n\t"
8963 "JUMP O7" %}
8964 ins_encode %{
8965 // Calculate table address into a register.
8966 Register table_reg;
8967 Register label_reg = O7;
8968 // If we are calculating the size of this instruction don't trust
8969 // zero offsets because they might change when
8970 // MachConstantBaseNode decides to optimize the constant table
8971 // base.
8972 if ((constant_offset() == 0) && !Compile::current()->in_scratch_emit_size()) {
8973 table_reg = $constanttablebase;
8974 } else {
8975 table_reg = O7;
8976 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset, O7);
8977 __ add($constanttablebase, con_offset, table_reg);
8978 }
8979
8980 // Jump to base address + switch value
8981 __ ld_ptr(table_reg, $switch_val$$Register, label_reg);
8982 __ jmp(label_reg, G0);
8983 __ delayed()->nop();
8984 %}
8985 ins_pipe(ialu_reg_reg);
8986 %}
8987
8988 // Direct Branch. Use V8 version with longer range.
8989 instruct branch(label labl) %{
8990 match(Goto);
8991 effect(USE labl);
8992
8993 size(8);
8994 ins_cost(BRANCH_COST);
8995 format %{ "BA $labl" %}
8996 ins_encode %{
8997 Label* L = $labl$$label;
8998 __ ba(*L);
8999 __ delayed()->nop();
9000 %}
9001 ins_avoid_back_to_back(AVOID_BEFORE);
9002 ins_pipe(br);
9003 %}
9004
9005 // Direct Branch, short with no delay slot
9006 instruct branch_short(label labl) %{
9007 match(Goto);
9008 predicate(UseCBCond);
9009 effect(USE labl);
9010
9011 size(4);
9012 ins_cost(BRANCH_COST);
9013 format %{ "BA $labl\t! short branch" %}
9014 ins_encode %{
9015 Label* L = $labl$$label;
9016 assert(__ use_cbcond(*L), "back to back cbcond");
9017 __ ba_short(*L);
9018 %}
9019 ins_short_branch(1);
9020 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
9021 ins_pipe(cbcond_reg_imm);
9022 %}
9023
9024 // Conditional Direct Branch
9025 instruct branchCon(cmpOp cmp, flagsReg icc, label labl) %{
9026 match(If cmp icc);
9027 effect(USE labl);
9028
9029 size(8);
9030 ins_cost(BRANCH_COST);
9031 format %{ "BP$cmp $icc,$labl" %}
9032 // Prim = bits 24-22, Secnd = bits 31-30
9033 ins_encode( enc_bp( labl, cmp, icc ) );
9034 ins_avoid_back_to_back(AVOID_BEFORE);
9035 ins_pipe(br_cc);
9036 %}
9037
9038 instruct branchConU(cmpOpU cmp, flagsRegU icc, label labl) %{
9039 match(If cmp icc);
9040 effect(USE labl);
9041
9042 ins_cost(BRANCH_COST);
9043 format %{ "BP$cmp $icc,$labl" %}
9044 // Prim = bits 24-22, Secnd = bits 31-30
9045 ins_encode( enc_bp( labl, cmp, icc ) );
9046 ins_avoid_back_to_back(AVOID_BEFORE);
9047 ins_pipe(br_cc);
9048 %}
9049
9050 instruct branchConP(cmpOpP cmp, flagsRegP pcc, label labl) %{
9051 match(If cmp pcc);
9052 effect(USE labl);
9053
9054 size(8);
9055 ins_cost(BRANCH_COST);
9056 format %{ "BP$cmp $pcc,$labl" %}
9057 ins_encode %{
9058 Label* L = $labl$$label;
9059 Assembler::Predict predict_taken =
9060 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9061
9062 __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::ptr_cc, predict_taken, *L);
9063 __ delayed()->nop();
9064 %}
9065 ins_avoid_back_to_back(AVOID_BEFORE);
9066 ins_pipe(br_cc);
9067 %}
9068
9069 instruct branchConF(cmpOpF cmp, flagsRegF fcc, label labl) %{
9070 match(If cmp fcc);
9071 effect(USE labl);
9072
9073 size(8);
9074 ins_cost(BRANCH_COST);
9075 format %{ "FBP$cmp $fcc,$labl" %}
9076 ins_encode %{
9077 Label* L = $labl$$label;
9078 Assembler::Predict predict_taken =
9079 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9080
9081 __ fbp( (Assembler::Condition)($cmp$$cmpcode), false, (Assembler::CC)($fcc$$reg), predict_taken, *L);
9082 __ delayed()->nop();
9083 %}
9084 ins_avoid_back_to_back(AVOID_BEFORE);
9085 ins_pipe(br_fcc);
9086 %}
9087
9088 instruct branchLoopEnd(cmpOp cmp, flagsReg icc, label labl) %{
9089 match(CountedLoopEnd cmp icc);
9090 effect(USE labl);
9091
9092 size(8);
9093 ins_cost(BRANCH_COST);
9094 format %{ "BP$cmp $icc,$labl\t! Loop end" %}
9095 // Prim = bits 24-22, Secnd = bits 31-30
9096 ins_encode( enc_bp( labl, cmp, icc ) );
9097 ins_avoid_back_to_back(AVOID_BEFORE);
9098 ins_pipe(br_cc);
9099 %}
9100
9101 instruct branchLoopEndU(cmpOpU cmp, flagsRegU icc, label labl) %{
9102 match(CountedLoopEnd cmp icc);
9103 effect(USE labl);
9104
9105 size(8);
9106 ins_cost(BRANCH_COST);
9107 format %{ "BP$cmp $icc,$labl\t! Loop end" %}
9108 // Prim = bits 24-22, Secnd = bits 31-30
9109 ins_encode( enc_bp( labl, cmp, icc ) );
9110 ins_avoid_back_to_back(AVOID_BEFORE);
9111 ins_pipe(br_cc);
9112 %}
9113
9114 // Compare and branch instructions
9115 instruct cmpI_reg_branch(cmpOp cmp, iRegI op1, iRegI op2, label labl, flagsReg icc) %{
9116 match(If cmp (CmpI op1 op2));
9117 effect(USE labl, KILL icc);
9118
9119 size(12);
9120 ins_cost(BRANCH_COST);
9121 format %{ "CMP $op1,$op2\t! int\n\t"
9122 "BP$cmp $labl" %}
9123 ins_encode %{
9124 Label* L = $labl$$label;
9125 Assembler::Predict predict_taken =
9126 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9127 __ cmp($op1$$Register, $op2$$Register);
9128 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
9129 __ delayed()->nop();
9130 %}
9131 ins_pipe(cmp_br_reg_reg);
9132 %}
9133
9134 instruct cmpI_imm_branch(cmpOp cmp, iRegI op1, immI5 op2, label labl, flagsReg icc) %{
9135 match(If cmp (CmpI op1 op2));
9136 effect(USE labl, KILL icc);
9137
9138 size(12);
9139 ins_cost(BRANCH_COST);
9140 format %{ "CMP $op1,$op2\t! int\n\t"
9141 "BP$cmp $labl" %}
9142 ins_encode %{
9143 Label* L = $labl$$label;
9144 Assembler::Predict predict_taken =
9145 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9146 __ cmp($op1$$Register, $op2$$constant);
9147 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
9148 __ delayed()->nop();
9149 %}
9150 ins_pipe(cmp_br_reg_imm);
9151 %}
9152
9153 instruct cmpU_reg_branch(cmpOpU cmp, iRegI op1, iRegI op2, label labl, flagsRegU icc) %{
9154 match(If cmp (CmpU op1 op2));
9155 effect(USE labl, KILL icc);
9156
9157 size(12);
9158 ins_cost(BRANCH_COST);
9159 format %{ "CMP $op1,$op2\t! unsigned\n\t"
9160 "BP$cmp $labl" %}
9161 ins_encode %{
9162 Label* L = $labl$$label;
9163 Assembler::Predict predict_taken =
9164 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9165 __ cmp($op1$$Register, $op2$$Register);
9166 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
9167 __ delayed()->nop();
9168 %}
9169 ins_pipe(cmp_br_reg_reg);
9170 %}
9171
9172 instruct cmpU_imm_branch(cmpOpU cmp, iRegI op1, immI5 op2, label labl, flagsRegU icc) %{
9173 match(If cmp (CmpU op1 op2));
9174 effect(USE labl, KILL icc);
9175
9176 size(12);
9177 ins_cost(BRANCH_COST);
9178 format %{ "CMP $op1,$op2\t! unsigned\n\t"
9179 "BP$cmp $labl" %}
9180 ins_encode %{
9181 Label* L = $labl$$label;
9182 Assembler::Predict predict_taken =
9183 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9184 __ cmp($op1$$Register, $op2$$constant);
9185 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
9186 __ delayed()->nop();
9187 %}
9188 ins_pipe(cmp_br_reg_imm);
9189 %}
9190
9191 instruct cmpL_reg_branch(cmpOp cmp, iRegL op1, iRegL op2, label labl, flagsRegL xcc) %{
9192 match(If cmp (CmpL op1 op2));
9193 effect(USE labl, KILL xcc);
9194
9195 size(12);
9196 ins_cost(BRANCH_COST);
9197 format %{ "CMP $op1,$op2\t! long\n\t"
9198 "BP$cmp $labl" %}
9199 ins_encode %{
9200 Label* L = $labl$$label;
9201 Assembler::Predict predict_taken =
9202 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9203 __ cmp($op1$$Register, $op2$$Register);
9204 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::xcc, predict_taken, *L);
9205 __ delayed()->nop();
9206 %}
9207 ins_pipe(cmp_br_reg_reg);
9208 %}
9209
9210 instruct cmpL_imm_branch(cmpOp cmp, iRegL op1, immL5 op2, label labl, flagsRegL xcc) %{
9211 match(If cmp (CmpL op1 op2));
9212 effect(USE labl, KILL xcc);
9213
9214 size(12);
9215 ins_cost(BRANCH_COST);
9216 format %{ "CMP $op1,$op2\t! long\n\t"
9217 "BP$cmp $labl" %}
9218 ins_encode %{
9219 Label* L = $labl$$label;
9220 Assembler::Predict predict_taken =
9221 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9222 __ cmp($op1$$Register, $op2$$constant);
9223 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::xcc, predict_taken, *L);
9224 __ delayed()->nop();
9225 %}
9226 ins_pipe(cmp_br_reg_imm);
9227 %}
9228
9229 // Compare Pointers and branch
9230 instruct cmpP_reg_branch(cmpOpP cmp, iRegP op1, iRegP op2, label labl, flagsRegP pcc) %{
9231 match(If cmp (CmpP op1 op2));
9232 effect(USE labl, KILL pcc);
9233
9234 size(12);
9235 ins_cost(BRANCH_COST);
9236 format %{ "CMP $op1,$op2\t! ptr\n\t"
9237 "B$cmp $labl" %}
9238 ins_encode %{
9239 Label* L = $labl$$label;
9240 Assembler::Predict predict_taken =
9241 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9242 __ cmp($op1$$Register, $op2$$Register);
9243 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::ptr_cc, predict_taken, *L);
9244 __ delayed()->nop();
9245 %}
9246 ins_pipe(cmp_br_reg_reg);
9247 %}
9248
9249 instruct cmpP_null_branch(cmpOpP cmp, iRegP op1, immP0 null, label labl, flagsRegP pcc) %{
9250 match(If cmp (CmpP op1 null));
9251 effect(USE labl, KILL pcc);
9252
9253 size(12);
9254 ins_cost(BRANCH_COST);
9255 format %{ "CMP $op1,0\t! ptr\n\t"
9256 "B$cmp $labl" %}
9257 ins_encode %{
9258 Label* L = $labl$$label;
9259 Assembler::Predict predict_taken =
9260 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9261 __ cmp($op1$$Register, G0);
9262 // bpr() is not used here since it has shorter distance.
9263 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::ptr_cc, predict_taken, *L);
9264 __ delayed()->nop();
9265 %}
9266 ins_pipe(cmp_br_reg_reg);
9267 %}
9268
9269 instruct cmpN_reg_branch(cmpOp cmp, iRegN op1, iRegN op2, label labl, flagsReg icc) %{
9270 match(If cmp (CmpN op1 op2));
9271 effect(USE labl, KILL icc);
9272
9273 size(12);
9274 ins_cost(BRANCH_COST);
9275 format %{ "CMP $op1,$op2\t! compressed ptr\n\t"
9276 "BP$cmp $labl" %}
9277 ins_encode %{
9278 Label* L = $labl$$label;
9279 Assembler::Predict predict_taken =
9280 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9281 __ cmp($op1$$Register, $op2$$Register);
9282 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
9283 __ delayed()->nop();
9284 %}
9285 ins_pipe(cmp_br_reg_reg);
9286 %}
9287
9288 instruct cmpN_null_branch(cmpOp cmp, iRegN op1, immN0 null, label labl, flagsReg icc) %{
9289 match(If cmp (CmpN op1 null));
9290 effect(USE labl, KILL icc);
9291
9292 size(12);
9293 ins_cost(BRANCH_COST);
9294 format %{ "CMP $op1,0\t! compressed ptr\n\t"
9295 "BP$cmp $labl" %}
9296 ins_encode %{
9297 Label* L = $labl$$label;
9298 Assembler::Predict predict_taken =
9299 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9300 __ cmp($op1$$Register, G0);
9301 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
9302 __ delayed()->nop();
9303 %}
9304 ins_pipe(cmp_br_reg_reg);
9305 %}
9306
9307 // Loop back branch
9308 instruct cmpI_reg_branchLoopEnd(cmpOp cmp, iRegI op1, iRegI op2, label labl, flagsReg icc) %{
9309 match(CountedLoopEnd cmp (CmpI op1 op2));
9310 effect(USE labl, KILL icc);
9311
9312 size(12);
9313 ins_cost(BRANCH_COST);
9314 format %{ "CMP $op1,$op2\t! int\n\t"
9315 "BP$cmp $labl\t! Loop end" %}
9316 ins_encode %{
9317 Label* L = $labl$$label;
9318 Assembler::Predict predict_taken =
9319 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9320 __ cmp($op1$$Register, $op2$$Register);
9321 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
9322 __ delayed()->nop();
9323 %}
9324 ins_pipe(cmp_br_reg_reg);
9325 %}
9326
9327 instruct cmpI_imm_branchLoopEnd(cmpOp cmp, iRegI op1, immI5 op2, label labl, flagsReg icc) %{
9328 match(CountedLoopEnd cmp (CmpI op1 op2));
9329 effect(USE labl, KILL icc);
9330
9331 size(12);
9332 ins_cost(BRANCH_COST);
9333 format %{ "CMP $op1,$op2\t! int\n\t"
9334 "BP$cmp $labl\t! Loop end" %}
9335 ins_encode %{
9336 Label* L = $labl$$label;
9337 Assembler::Predict predict_taken =
9338 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9339 __ cmp($op1$$Register, $op2$$constant);
9340 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
9341 __ delayed()->nop();
9342 %}
9343 ins_pipe(cmp_br_reg_imm);
9344 %}
9345
9346 // Short compare and branch instructions
9347 instruct cmpI_reg_branch_short(cmpOp cmp, iRegI op1, iRegI op2, label labl, flagsReg icc) %{
9348 match(If cmp (CmpI op1 op2));
9349 predicate(UseCBCond);
9350 effect(USE labl, KILL icc);
9351
9352 size(4);
9353 ins_cost(BRANCH_COST);
9354 format %{ "CWB$cmp $op1,$op2,$labl\t! int" %}
9355 ins_encode %{
9356 Label* L = $labl$$label;
9357 assert(__ use_cbcond(*L), "back to back cbcond");
9358 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$Register, *L);
9359 %}
9360 ins_short_branch(1);
9361 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
9362 ins_pipe(cbcond_reg_reg);
9363 %}
9364
9365 instruct cmpI_imm_branch_short(cmpOp cmp, iRegI op1, immI5 op2, label labl, flagsReg icc) %{
9366 match(If cmp (CmpI op1 op2));
9367 predicate(UseCBCond);
9368 effect(USE labl, KILL icc);
9369
9370 size(4);
9371 ins_cost(BRANCH_COST);
9372 format %{ "CWB$cmp $op1,$op2,$labl\t! int" %}
9373 ins_encode %{
9374 Label* L = $labl$$label;
9375 assert(__ use_cbcond(*L), "back to back cbcond");
9376 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$constant, *L);
9377 %}
9378 ins_short_branch(1);
9379 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
9380 ins_pipe(cbcond_reg_imm);
9381 %}
9382
9383 instruct cmpU_reg_branch_short(cmpOpU cmp, iRegI op1, iRegI op2, label labl, flagsRegU icc) %{
9384 match(If cmp (CmpU op1 op2));
9385 predicate(UseCBCond);
9386 effect(USE labl, KILL icc);
9387
9388 size(4);
9389 ins_cost(BRANCH_COST);
9390 format %{ "CWB$cmp $op1,$op2,$labl\t! unsigned" %}
9391 ins_encode %{
9392 Label* L = $labl$$label;
9393 assert(__ use_cbcond(*L), "back to back cbcond");
9394 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$Register, *L);
9395 %}
9396 ins_short_branch(1);
9397 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
9398 ins_pipe(cbcond_reg_reg);
9399 %}
9400
9401 instruct cmpU_imm_branch_short(cmpOpU cmp, iRegI op1, immI5 op2, label labl, flagsRegU icc) %{
9402 match(If cmp (CmpU op1 op2));
9403 predicate(UseCBCond);
9404 effect(USE labl, KILL icc);
9405
9406 size(4);
9407 ins_cost(BRANCH_COST);
9408 format %{ "CWB$cmp $op1,$op2,$labl\t! unsigned" %}
9409 ins_encode %{
9410 Label* L = $labl$$label;
9411 assert(__ use_cbcond(*L), "back to back cbcond");
9412 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$constant, *L);
9413 %}
9414 ins_short_branch(1);
9415 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
9416 ins_pipe(cbcond_reg_imm);
9417 %}
9418
9419 instruct cmpL_reg_branch_short(cmpOp cmp, iRegL op1, iRegL op2, label labl, flagsRegL xcc) %{
9420 match(If cmp (CmpL op1 op2));
9421 predicate(UseCBCond);
9422 effect(USE labl, KILL xcc);
9423
9424 size(4);
9425 ins_cost(BRANCH_COST);
9426 format %{ "CXB$cmp $op1,$op2,$labl\t! long" %}
9427 ins_encode %{
9428 Label* L = $labl$$label;
9429 assert(__ use_cbcond(*L), "back to back cbcond");
9430 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::xcc, $op1$$Register, $op2$$Register, *L);
9431 %}
9432 ins_short_branch(1);
9433 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
9434 ins_pipe(cbcond_reg_reg);
9435 %}
9436
9437 instruct cmpL_imm_branch_short(cmpOp cmp, iRegL op1, immL5 op2, label labl, flagsRegL xcc) %{
9438 match(If cmp (CmpL op1 op2));
9439 predicate(UseCBCond);
9440 effect(USE labl, KILL xcc);
9441
9442 size(4);
9443 ins_cost(BRANCH_COST);
9444 format %{ "CXB$cmp $op1,$op2,$labl\t! long" %}
9445 ins_encode %{
9446 Label* L = $labl$$label;
9447 assert(__ use_cbcond(*L), "back to back cbcond");
9448 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::xcc, $op1$$Register, $op2$$constant, *L);
9449 %}
9450 ins_short_branch(1);
9451 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
9452 ins_pipe(cbcond_reg_imm);
9453 %}
9454
9455 // Compare Pointers and branch
9456 instruct cmpP_reg_branch_short(cmpOpP cmp, iRegP op1, iRegP op2, label labl, flagsRegP pcc) %{
9457 match(If cmp (CmpP op1 op2));
9458 predicate(UseCBCond);
9459 effect(USE labl, KILL pcc);
9460
9461 size(4);
9462 ins_cost(BRANCH_COST);
9463 #ifdef _LP64
9464 format %{ "CXB$cmp $op1,$op2,$labl\t! ptr" %}
9465 #else
9466 format %{ "CWB$cmp $op1,$op2,$labl\t! ptr" %}
9467 #endif
9468 ins_encode %{
9469 Label* L = $labl$$label;
9470 assert(__ use_cbcond(*L), "back to back cbcond");
9471 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::ptr_cc, $op1$$Register, $op2$$Register, *L);
9472 %}
9473 ins_short_branch(1);
9474 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
9475 ins_pipe(cbcond_reg_reg);
9476 %}
9477
9478 instruct cmpP_null_branch_short(cmpOpP cmp, iRegP op1, immP0 null, label labl, flagsRegP pcc) %{
9479 match(If cmp (CmpP op1 null));
9480 predicate(UseCBCond);
9481 effect(USE labl, KILL pcc);
9482
9483 size(4);
9484 ins_cost(BRANCH_COST);
9485 #ifdef _LP64
9486 format %{ "CXB$cmp $op1,0,$labl\t! ptr" %}
9487 #else
9488 format %{ "CWB$cmp $op1,0,$labl\t! ptr" %}
9489 #endif
9490 ins_encode %{
9491 Label* L = $labl$$label;
9492 assert(__ use_cbcond(*L), "back to back cbcond");
9493 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::ptr_cc, $op1$$Register, G0, *L);
9494 %}
9495 ins_short_branch(1);
9496 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
9497 ins_pipe(cbcond_reg_reg);
9498 %}
9499
9500 instruct cmpN_reg_branch_short(cmpOp cmp, iRegN op1, iRegN op2, label labl, flagsReg icc) %{
9501 match(If cmp (CmpN op1 op2));
9502 predicate(UseCBCond);
9503 effect(USE labl, KILL icc);
9504
9505 size(4);
9506 ins_cost(BRANCH_COST);
9507 format %{ "CWB$cmp $op1,$op2,$labl\t! compressed ptr" %}
9508 ins_encode %{
9509 Label* L = $labl$$label;
9510 assert(__ use_cbcond(*L), "back to back cbcond");
9511 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$Register, *L);
9512 %}
9513 ins_short_branch(1);
9514 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
9515 ins_pipe(cbcond_reg_reg);
9516 %}
9517
9518 instruct cmpN_null_branch_short(cmpOp cmp, iRegN op1, immN0 null, label labl, flagsReg icc) %{
9519 match(If cmp (CmpN op1 null));
9520 predicate(UseCBCond);
9521 effect(USE labl, KILL icc);
9522
9523 size(4);
9524 ins_cost(BRANCH_COST);
9525 format %{ "CWB$cmp $op1,0,$labl\t! compressed ptr" %}
9526 ins_encode %{
9527 Label* L = $labl$$label;
9528 assert(__ use_cbcond(*L), "back to back cbcond");
9529 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, G0, *L);
9530 %}
9531 ins_short_branch(1);
9532 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
9533 ins_pipe(cbcond_reg_reg);
9534 %}
9535
9536 // Loop back branch
9537 instruct cmpI_reg_branchLoopEnd_short(cmpOp cmp, iRegI op1, iRegI op2, label labl, flagsReg icc) %{
9538 match(CountedLoopEnd cmp (CmpI op1 op2));
9539 predicate(UseCBCond);
9540 effect(USE labl, KILL icc);
9541
9542 size(4);
9543 ins_cost(BRANCH_COST);
9544 format %{ "CWB$cmp $op1,$op2,$labl\t! Loop end" %}
9545 ins_encode %{
9546 Label* L = $labl$$label;
9547 assert(__ use_cbcond(*L), "back to back cbcond");
9548 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$Register, *L);
9549 %}
9550 ins_short_branch(1);
9551 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
9552 ins_pipe(cbcond_reg_reg);
9553 %}
9554
9555 instruct cmpI_imm_branchLoopEnd_short(cmpOp cmp, iRegI op1, immI5 op2, label labl, flagsReg icc) %{
9556 match(CountedLoopEnd cmp (CmpI op1 op2));
9557 predicate(UseCBCond);
9558 effect(USE labl, KILL icc);
9559
9560 size(4);
9561 ins_cost(BRANCH_COST);
9562 format %{ "CWB$cmp $op1,$op2,$labl\t! Loop end" %}
9563 ins_encode %{
9564 Label* L = $labl$$label;
9565 assert(__ use_cbcond(*L), "back to back cbcond");
9566 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$constant, *L);
9567 %}
9568 ins_short_branch(1);
9569 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
9570 ins_pipe(cbcond_reg_imm);
9571 %}
9572
9573 // Branch-on-register tests all 64 bits. We assume that values
9574 // in 64-bit registers always remains zero or sign extended
9575 // unless our code munges the high bits. Interrupts can chop
9576 // the high order bits to zero or sign at any time.
9577 instruct branchCon_regI(cmpOp_reg cmp, iRegI op1, immI0 zero, label labl) %{
9578 match(If cmp (CmpI op1 zero));
9579 predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf));
9580 effect(USE labl);
9581
9582 size(8);
9583 ins_cost(BRANCH_COST);
9584 format %{ "BR$cmp $op1,$labl" %}
9585 ins_encode( enc_bpr( labl, cmp, op1 ) );
9586 ins_avoid_back_to_back(AVOID_BEFORE);
9587 ins_pipe(br_reg);
9588 %}
9589
9590 instruct branchCon_regP(cmpOp_reg cmp, iRegP op1, immP0 null, label labl) %{
9591 match(If cmp (CmpP op1 null));
9592 predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf));
9593 effect(USE labl);
9594
9595 size(8);
9596 ins_cost(BRANCH_COST);
9597 format %{ "BR$cmp $op1,$labl" %}
9598 ins_encode( enc_bpr( labl, cmp, op1 ) );
9599 ins_avoid_back_to_back(AVOID_BEFORE);
9600 ins_pipe(br_reg);
9601 %}
9602
9603 instruct branchCon_regL(cmpOp_reg cmp, iRegL op1, immL0 zero, label labl) %{
9604 match(If cmp (CmpL op1 zero));
9605 predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf));
9606 effect(USE labl);
9607
9608 size(8);
9609 ins_cost(BRANCH_COST);
9610 format %{ "BR$cmp $op1,$labl" %}
9611 ins_encode( enc_bpr( labl, cmp, op1 ) );
9612 ins_avoid_back_to_back(AVOID_BEFORE);
9613 ins_pipe(br_reg);
9614 %}
9615
9616
9617 // ============================================================================
9618 // Long Compare
9619 //
9620 // Currently we hold longs in 2 registers. Comparing such values efficiently
9621 // is tricky. The flavor of compare used depends on whether we are testing
9622 // for LT, LE, or EQ. For a simple LT test we can check just the sign bit.
9623 // The GE test is the negated LT test. The LE test can be had by commuting
9624 // the operands (yielding a GE test) and then negating; negate again for the
9625 // GT test. The EQ test is done by ORcc'ing the high and low halves, and the
9626 // NE test is negated from that.
9627
9628 // Due to a shortcoming in the ADLC, it mixes up expressions like:
9629 // (foo (CmpI (CmpL X Y) 0)) and (bar (CmpI (CmpL X 0L) 0)). Note the
9630 // difference between 'Y' and '0L'. The tree-matches for the CmpI sections
9631 // are collapsed internally in the ADLC's dfa-gen code. The match for
9632 // (CmpI (CmpL X Y) 0) is silently replaced with (CmpI (CmpL X 0L) 0) and the
9633 // foo match ends up with the wrong leaf. One fix is to not match both
9634 // reg-reg and reg-zero forms of long-compare. This is unfortunate because
9635 // both forms beat the trinary form of long-compare and both are very useful
9636 // on Intel which has so few registers.
9637
9638 instruct branchCon_long(cmpOp cmp, flagsRegL xcc, label labl) %{
9639 match(If cmp xcc);
9640 effect(USE labl);
9641
9642 size(8);
9643 ins_cost(BRANCH_COST);
9644 format %{ "BP$cmp $xcc,$labl" %}
9645 ins_encode %{
9646 Label* L = $labl$$label;
9647 Assembler::Predict predict_taken =
9648 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9649
9650 __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::xcc, predict_taken, *L);
9651 __ delayed()->nop();
9652 %}
9653 ins_avoid_back_to_back(AVOID_BEFORE);
9654 ins_pipe(br_cc);
9655 %}
9656
9657 // Manifest a CmpL3 result in an integer register. Very painful.
9658 // This is the test to avoid.
9659 instruct cmpL3_reg_reg(iRegI dst, iRegL src1, iRegL src2, flagsReg ccr ) %{
9660 match(Set dst (CmpL3 src1 src2) );
9661 effect( KILL ccr );
9662 ins_cost(6*DEFAULT_COST);
9663 size(24);
9664 format %{ "CMP $src1,$src2\t\t! long\n"
9665 "\tBLT,a,pn done\n"
9666 "\tMOV -1,$dst\t! delay slot\n"
9667 "\tBGT,a,pn done\n"
9668 "\tMOV 1,$dst\t! delay slot\n"
9669 "\tCLR $dst\n"
9670 "done:" %}
9671 ins_encode( cmpl_flag(src1,src2,dst) );
9672 ins_pipe(cmpL_reg);
9673 %}
9674
9675 // Conditional move
9676 instruct cmovLL_reg(cmpOp cmp, flagsRegL xcc, iRegL dst, iRegL src) %{
9677 match(Set dst (CMoveL (Binary cmp xcc) (Binary dst src)));
9678 ins_cost(150);
9679 format %{ "MOV$cmp $xcc,$src,$dst\t! long" %}
9680 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) );
9681 ins_pipe(ialu_reg);
9682 %}
9683
9684 instruct cmovLL_imm(cmpOp cmp, flagsRegL xcc, iRegL dst, immL0 src) %{
9685 match(Set dst (CMoveL (Binary cmp xcc) (Binary dst src)));
9686 ins_cost(140);
9687 format %{ "MOV$cmp $xcc,$src,$dst\t! long" %}
9688 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) );
9689 ins_pipe(ialu_imm);
9690 %}
9691
9692 instruct cmovIL_reg(cmpOp cmp, flagsRegL xcc, iRegI dst, iRegI src) %{
9693 match(Set dst (CMoveI (Binary cmp xcc) (Binary dst src)));
9694 ins_cost(150);
9695 format %{ "MOV$cmp $xcc,$src,$dst" %}
9696 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) );
9697 ins_pipe(ialu_reg);
9698 %}
9699
9700 instruct cmovIL_imm(cmpOp cmp, flagsRegL xcc, iRegI dst, immI11 src) %{
9701 match(Set dst (CMoveI (Binary cmp xcc) (Binary dst src)));
9702 ins_cost(140);
9703 format %{ "MOV$cmp $xcc,$src,$dst" %}
9704 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) );
9705 ins_pipe(ialu_imm);
9706 %}
9707
9708 instruct cmovNL_reg(cmpOp cmp, flagsRegL xcc, iRegN dst, iRegN src) %{
9709 match(Set dst (CMoveN (Binary cmp xcc) (Binary dst src)));
9710 ins_cost(150);
9711 format %{ "MOV$cmp $xcc,$src,$dst" %}
9712 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) );
9713 ins_pipe(ialu_reg);
9714 %}
9715
9716 instruct cmovPL_reg(cmpOp cmp, flagsRegL xcc, iRegP dst, iRegP src) %{
9717 match(Set dst (CMoveP (Binary cmp xcc) (Binary dst src)));
9718 ins_cost(150);
9719 format %{ "MOV$cmp $xcc,$src,$dst" %}
9720 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) );
9721 ins_pipe(ialu_reg);
9722 %}
9723
9724 instruct cmovPL_imm(cmpOp cmp, flagsRegL xcc, iRegP dst, immP0 src) %{
9725 match(Set dst (CMoveP (Binary cmp xcc) (Binary dst src)));
9726 ins_cost(140);
9727 format %{ "MOV$cmp $xcc,$src,$dst" %}
9728 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) );
9729 ins_pipe(ialu_imm);
9730 %}
9731
9732 instruct cmovFL_reg(cmpOp cmp, flagsRegL xcc, regF dst, regF src) %{
9733 match(Set dst (CMoveF (Binary cmp xcc) (Binary dst src)));
9734 ins_cost(150);
9735 opcode(0x101);
9736 format %{ "FMOVS$cmp $xcc,$src,$dst" %}
9737 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::xcc)) );
9738 ins_pipe(int_conditional_float_move);
9739 %}
9740
9741 instruct cmovDL_reg(cmpOp cmp, flagsRegL xcc, regD dst, regD src) %{
9742 match(Set dst (CMoveD (Binary cmp xcc) (Binary dst src)));
9743 ins_cost(150);
9744 opcode(0x102);
9745 format %{ "FMOVD$cmp $xcc,$src,$dst" %}
9746 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::xcc)) );
9747 ins_pipe(int_conditional_float_move);
9748 %}
9749
9750 // ============================================================================
9751 // Safepoint Instruction
9752 instruct safePoint_poll(iRegP poll) %{
9753 match(SafePoint poll);
9754 effect(USE poll);
9755
9756 size(4);
9757 #ifdef _LP64
9758 format %{ "LDX [$poll],R_G0\t! Safepoint: poll for GC" %}
9759 #else
9760 format %{ "LDUW [$poll],R_G0\t! Safepoint: poll for GC" %}
9761 #endif
9762 ins_encode %{
9763 __ relocate(relocInfo::poll_type);
9764 __ ld_ptr($poll$$Register, 0, G0);
9765 %}
9766 ins_pipe(loadPollP);
9767 %}
9768
9769 // ============================================================================
9770 // Call Instructions
9771 // Call Java Static Instruction
9772 instruct CallStaticJavaDirect( method meth ) %{
9773 match(CallStaticJava);
9774 predicate(! ((CallStaticJavaNode*)n)->is_method_handle_invoke());
9775 effect(USE meth);
9776
9777 size(8);
9778 ins_cost(CALL_COST);
9779 format %{ "CALL,static ; NOP ==> " %}
9780 ins_encode( Java_Static_Call( meth ), call_epilog );
9781 ins_avoid_back_to_back(AVOID_BEFORE);
9782 ins_pipe(simple_call);
9783 %}
9784
9785 // Call Java Static Instruction (method handle version)
9786 instruct CallStaticJavaHandle(method meth, l7RegP l7_mh_SP_save) %{
9787 match(CallStaticJava);
9788 predicate(((CallStaticJavaNode*)n)->is_method_handle_invoke());
9789 effect(USE meth, KILL l7_mh_SP_save);
9790
9791 size(16);
9792 ins_cost(CALL_COST);
9793 format %{ "CALL,static/MethodHandle" %}
9794 ins_encode(preserve_SP, Java_Static_Call(meth), restore_SP, call_epilog);
9795 ins_pipe(simple_call);
9796 %}
9797
9798 // Call Java Dynamic Instruction
9799 instruct CallDynamicJavaDirect( method meth ) %{
9800 match(CallDynamicJava);
9801 effect(USE meth);
9802
9803 ins_cost(CALL_COST);
9804 format %{ "SET (empty),R_G5\n\t"
9805 "CALL,dynamic ; NOP ==> " %}
9806 ins_encode( Java_Dynamic_Call( meth ), call_epilog );
9807 ins_pipe(call);
9808 %}
9809
9810 // Call Runtime Instruction
9811 instruct CallRuntimeDirect(method meth, l7RegP l7) %{
9812 match(CallRuntime);
9813 effect(USE meth, KILL l7);
9814 ins_cost(CALL_COST);
9815 format %{ "CALL,runtime" %}
9816 ins_encode( Java_To_Runtime( meth ),
9817 call_epilog, adjust_long_from_native_call );
9818 ins_avoid_back_to_back(AVOID_BEFORE);
9819 ins_pipe(simple_call);
9820 %}
9821
9822 // Call runtime without safepoint - same as CallRuntime
9823 instruct CallLeafDirect(method meth, l7RegP l7) %{
9824 match(CallLeaf);
9825 effect(USE meth, KILL l7);
9826 ins_cost(CALL_COST);
9827 format %{ "CALL,runtime leaf" %}
9828 ins_encode( Java_To_Runtime( meth ),
9829 call_epilog,
9830 adjust_long_from_native_call );
9831 ins_avoid_back_to_back(AVOID_BEFORE);
9832 ins_pipe(simple_call);
9833 %}
9834
9835 // Call runtime without safepoint - same as CallLeaf
9836 instruct CallLeafNoFPDirect(method meth, l7RegP l7) %{
9837 match(CallLeafNoFP);
9838 effect(USE meth, KILL l7);
9839 ins_cost(CALL_COST);
9840 format %{ "CALL,runtime leaf nofp" %}
9841 ins_encode( Java_To_Runtime( meth ),
9842 call_epilog,
9843 adjust_long_from_native_call );
9844 ins_avoid_back_to_back(AVOID_BEFORE);
9845 ins_pipe(simple_call);
9846 %}
9847
9848 // Tail Call; Jump from runtime stub to Java code.
9849 // Also known as an 'interprocedural jump'.
9850 // Target of jump will eventually return to caller.
9851 // TailJump below removes the return address.
9852 instruct TailCalljmpInd(g3RegP jump_target, inline_cache_regP method_oop) %{
9853 match(TailCall jump_target method_oop );
9854
9855 ins_cost(CALL_COST);
9856 format %{ "Jmp $jump_target ; NOP \t! $method_oop holds method oop" %}
9857 ins_encode(form_jmpl(jump_target));
9858 ins_avoid_back_to_back(AVOID_BEFORE);
9859 ins_pipe(tail_call);
9860 %}
9861
9862
9863 // Return Instruction
9864 instruct Ret() %{
9865 match(Return);
9866
9867 // The epilogue node did the ret already.
9868 size(0);
9869 format %{ "! return" %}
9870 ins_encode();
9871 ins_pipe(empty);
9872 %}
9873
9874
9875 // Tail Jump; remove the return address; jump to target.
9876 // TailCall above leaves the return address around.
9877 // TailJump is used in only one place, the rethrow_Java stub (fancy_jump=2).
9878 // ex_oop (Exception Oop) is needed in %o0 at the jump. As there would be a
9879 // "restore" before this instruction (in Epilogue), we need to materialize it
9880 // in %i0.
9881 instruct tailjmpInd(g1RegP jump_target, i0RegP ex_oop) %{
9882 match( TailJump jump_target ex_oop );
9883 ins_cost(CALL_COST);
9884 format %{ "! discard R_O7\n\t"
9885 "Jmp $jump_target ; ADD O7,8,O1 \t! $ex_oop holds exc. oop" %}
9886 ins_encode(form_jmpl_set_exception_pc(jump_target));
9887 // opcode(Assembler::jmpl_op3, Assembler::arith_op);
9888 // The hack duplicates the exception oop into G3, so that CreateEx can use it there.
9889 // ins_encode( form3_rs1_simm13_rd( jump_target, 0x00, R_G0 ), move_return_pc_to_o1() );
9890 ins_avoid_back_to_back(AVOID_BEFORE);
9891 ins_pipe(tail_call);
9892 %}
9893
9894 // Create exception oop: created by stack-crawling runtime code.
9895 // Created exception is now available to this handler, and is setup
9896 // just prior to jumping to this handler. No code emitted.
9897 instruct CreateException( o0RegP ex_oop )
9898 %{
9899 match(Set ex_oop (CreateEx));
9900 ins_cost(0);
9901
9902 size(0);
9903 // use the following format syntax
9904 format %{ "! exception oop is in R_O0; no code emitted" %}
9905 ins_encode();
9906 ins_pipe(empty);
9907 %}
9908
9909
9910 // Rethrow exception:
9911 // The exception oop will come in the first argument position.
9912 // Then JUMP (not call) to the rethrow stub code.
9913 instruct RethrowException()
9914 %{
9915 match(Rethrow);
9916 ins_cost(CALL_COST);
9917
9918 // use the following format syntax
9919 format %{ "Jmp rethrow_stub" %}
9920 ins_encode(enc_rethrow);
9921 ins_avoid_back_to_back(AVOID_BEFORE);
9922 ins_pipe(tail_call);
9923 %}
9924
9925
9926 // Die now
9927 instruct ShouldNotReachHere( )
9928 %{
9929 match(Halt);
9930 ins_cost(CALL_COST);
9931
9932 size(4);
9933 // Use the following format syntax
9934 format %{ "ILLTRAP ; ShouldNotReachHere" %}
9935 ins_encode( form2_illtrap() );
9936 ins_pipe(tail_call);
9937 %}
9938
9939 // ============================================================================
9940 // The 2nd slow-half of a subtype check. Scan the subklass's 2ndary superklass
9941 // array for an instance of the superklass. Set a hidden internal cache on a
9942 // hit (cache is checked with exposed code in gen_subtype_check()). Return
9943 // not zero for a miss or zero for a hit. The encoding ALSO sets flags.
9944 instruct partialSubtypeCheck( o0RegP index, o1RegP sub, o2RegP super, flagsRegP pcc, o7RegP o7 ) %{
9945 match(Set index (PartialSubtypeCheck sub super));
9946 effect( KILL pcc, KILL o7 );
9947 ins_cost(DEFAULT_COST*10);
9948 format %{ "CALL PartialSubtypeCheck\n\tNOP" %}
9949 ins_encode( enc_PartialSubtypeCheck() );
9950 ins_avoid_back_to_back(AVOID_BEFORE);
9951 ins_pipe(partial_subtype_check_pipe);
9952 %}
9953
9954 instruct partialSubtypeCheck_vs_zero( flagsRegP pcc, o1RegP sub, o2RegP super, immP0 zero, o0RegP idx, o7RegP o7 ) %{
9955 match(Set pcc (CmpP (PartialSubtypeCheck sub super) zero));
9956 effect( KILL idx, KILL o7 );
9957 ins_cost(DEFAULT_COST*10);
9958 format %{ "CALL PartialSubtypeCheck\n\tNOP\t# (sets condition codes)" %}
9959 ins_encode( enc_PartialSubtypeCheck() );
9960 ins_avoid_back_to_back(AVOID_BEFORE);
9961 ins_pipe(partial_subtype_check_pipe);
9962 %}
9963
9964
9965 // ============================================================================
9966 // inlined locking and unlocking
9967
9968 instruct cmpFastLock(flagsRegP pcc, iRegP object, o1RegP box, iRegP scratch2, o7RegP scratch ) %{
9969 match(Set pcc (FastLock object box));
9970
9971 effect(TEMP scratch2, USE_KILL box, KILL scratch);
9972 ins_cost(100);
9973
9974 format %{ "FASTLOCK $object,$box\t! kills $box,$scratch,$scratch2" %}
9975 ins_encode( Fast_Lock(object, box, scratch, scratch2) );
9976 ins_pipe(long_memory_op);
9977 %}
9978
9979
9980 instruct cmpFastUnlock(flagsRegP pcc, iRegP object, o1RegP box, iRegP scratch2, o7RegP scratch ) %{
9981 match(Set pcc (FastUnlock object box));
9982 effect(TEMP scratch2, USE_KILL box, KILL scratch);
9983 ins_cost(100);
9984
9985 format %{ "FASTUNLOCK $object,$box\t! kills $box,$scratch,$scratch2" %}
9986 ins_encode( Fast_Unlock(object, box, scratch, scratch2) );
9987 ins_pipe(long_memory_op);
9988 %}
9989
9990 // The encodings are generic.
9991 instruct clear_array(iRegX cnt, iRegP base, iRegX temp, Universe dummy, flagsReg ccr) %{
9992 predicate(!use_block_zeroing(n->in(2)) );
9993 match(Set dummy (ClearArray cnt base));
9994 effect(TEMP temp, KILL ccr);
9995 ins_cost(300);
9996 format %{ "MOV $cnt,$temp\n"
9997 "loop: SUBcc $temp,8,$temp\t! Count down a dword of bytes\n"
9998 " BRge loop\t\t! Clearing loop\n"
9999 " STX G0,[$base+$temp]\t! delay slot" %}
10000
10001 ins_encode %{
10002 // Compiler ensures base is doubleword aligned and cnt is count of doublewords
10003 Register nof_bytes_arg = $cnt$$Register;
10004 Register nof_bytes_tmp = $temp$$Register;
10005 Register base_pointer_arg = $base$$Register;
10006
10007 Label loop;
10008 __ mov(nof_bytes_arg, nof_bytes_tmp);
10009
10010 // Loop and clear, walking backwards through the array.
10011 // nof_bytes_tmp (if >0) is always the number of bytes to zero
10012 __ bind(loop);
10013 __ deccc(nof_bytes_tmp, 8);
10014 __ br(Assembler::greaterEqual, true, Assembler::pt, loop);
10015 __ delayed()-> stx(G0, base_pointer_arg, nof_bytes_tmp);
10016 // %%%% this mini-loop must not cross a cache boundary!
10017 %}
10018 ins_pipe(long_memory_op);
10019 %}
10020
10021 instruct clear_array_bis(g1RegX cnt, o0RegP base, Universe dummy, flagsReg ccr) %{
10022 predicate(use_block_zeroing(n->in(2)));
10023 match(Set dummy (ClearArray cnt base));
10024 effect(USE_KILL cnt, USE_KILL base, KILL ccr);
10025 ins_cost(300);
10026 format %{ "CLEAR [$base, $cnt]\t! ClearArray" %}
10027
10028 ins_encode %{
10029
10030 assert(MinObjAlignmentInBytes >= BytesPerLong, "need alternate implementation");
10031 Register to = $base$$Register;
10032 Register count = $cnt$$Register;
10033
10034 Label Ldone;
10035 __ nop(); // Separate short branches
10036 // Use BIS for zeroing (temp is not used).
10037 __ bis_zeroing(to, count, G0, Ldone);
10038 __ bind(Ldone);
10039
10040 %}
10041 ins_pipe(long_memory_op);
10042 %}
10043
10044 instruct clear_array_bis_2(g1RegX cnt, o0RegP base, iRegX tmp, Universe dummy, flagsReg ccr) %{
10045 predicate(use_block_zeroing(n->in(2)) && !Assembler::is_simm13((int)BlockZeroingLowLimit));
10046 match(Set dummy (ClearArray cnt base));
10047 effect(TEMP tmp, USE_KILL cnt, USE_KILL base, KILL ccr);
10048 ins_cost(300);
10049 format %{ "CLEAR [$base, $cnt]\t! ClearArray" %}
10050
10051 ins_encode %{
10052
10053 assert(MinObjAlignmentInBytes >= BytesPerLong, "need alternate implementation");
10054 Register to = $base$$Register;
10055 Register count = $cnt$$Register;
10056 Register temp = $tmp$$Register;
10057
10058 Label Ldone;
10059 __ nop(); // Separate short branches
10060 // Use BIS for zeroing
10061 __ bis_zeroing(to, count, temp, Ldone);
10062 __ bind(Ldone);
10063
10064 %}
10065 ins_pipe(long_memory_op);
10066 %}
10067
10068 instruct string_compareL(o0RegP str1, o1RegP str2, g3RegI cnt1, g4RegI cnt2, notemp_iRegI result,
10069 o7RegI tmp, flagsReg ccr) %{
10070 predicate(((StrCompNode*)n)->encoding() == StrIntrinsicNode::LL);
10071 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
10072 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL ccr, KILL tmp);
10073 ins_cost(300);
10074 format %{ "String Compare byte[] $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp" %}
10075 ins_encode %{
10076 __ string_compare($str1$$Register, $str2$$Register,
10077 $cnt1$$Register, $cnt2$$Register,
10078 $tmp$$Register, $tmp$$Register,
10079 $result$$Register, StrIntrinsicNode::LL);
10080 %}
10081 ins_pipe(long_memory_op);
10082 %}
10083
10084 instruct string_compareU(o0RegP str1, o1RegP str2, g3RegI cnt1, g4RegI cnt2, notemp_iRegI result,
10085 o7RegI tmp, flagsReg ccr) %{
10086 predicate(((StrCompNode*)n)->encoding() == StrIntrinsicNode::UU);
10087 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
10088 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL ccr, KILL tmp);
10089 ins_cost(300);
10090 format %{ "String Compare char[] $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp" %}
10091 ins_encode %{
10092 __ string_compare($str1$$Register, $str2$$Register,
10093 $cnt1$$Register, $cnt2$$Register,
10094 $tmp$$Register, $tmp$$Register,
10095 $result$$Register, StrIntrinsicNode::UU);
10096 %}
10097 ins_pipe(long_memory_op);
10098 %}
10099
10100 instruct string_compareLU(o0RegP str1, o1RegP str2, g3RegI cnt1, g4RegI cnt2, notemp_iRegI result,
10101 o7RegI tmp1, g1RegI tmp2, flagsReg ccr) %{
10102 predicate(((StrCompNode*)n)->encoding() == StrIntrinsicNode::LU);
10103 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
10104 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL ccr, KILL tmp1, KILL tmp2);
10105 ins_cost(300);
10106 format %{ "String Compare byte[] $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp1,$tmp2" %}
10107 ins_encode %{
10108 __ string_compare($str1$$Register, $str2$$Register,
10109 $cnt1$$Register, $cnt2$$Register,
10110 $tmp1$$Register, $tmp2$$Register,
10111 $result$$Register, StrIntrinsicNode::LU);
10112 %}
10113 ins_pipe(long_memory_op);
10114 %}
10115
10116 instruct string_compareUL(o0RegP str1, o1RegP str2, g3RegI cnt1, g4RegI cnt2, notemp_iRegI result,
10117 o7RegI tmp1, g1RegI tmp2, flagsReg ccr) %{
10118 predicate(((StrCompNode*)n)->encoding() == StrIntrinsicNode::UL);
10119 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
10120 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL ccr, KILL tmp1, KILL tmp2);
10121 ins_cost(300);
10122 format %{ "String Compare byte[] $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp1,$tmp2" %}
10123 ins_encode %{
10124 __ string_compare($str2$$Register, $str1$$Register,
10125 $cnt2$$Register, $cnt1$$Register,
10126 $tmp1$$Register, $tmp2$$Register,
10127 $result$$Register, StrIntrinsicNode::UL);
10128 %}
10129 ins_pipe(long_memory_op);
10130 %}
10131
10132 instruct string_equalsL(o0RegP str1, o1RegP str2, g3RegI cnt, notemp_iRegI result,
10133 o7RegI tmp, flagsReg ccr) %{
10134 predicate(((StrEqualsNode*)n)->encoding() == StrIntrinsicNode::LL);
10135 match(Set result (StrEquals (Binary str1 str2) cnt));
10136 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt, KILL tmp, KILL ccr);
10137 ins_cost(300);
10138 format %{ "String Equals byte[] $str1,$str2,$cnt -> $result // KILL $tmp" %}
10139 ins_encode %{
10140 __ array_equals(false, $str1$$Register, $str2$$Register,
10141 $cnt$$Register, $tmp$$Register,
10142 $result$$Register, true /* byte */);
10143 %}
10144 ins_pipe(long_memory_op);
10145 %}
10146
10147 instruct string_equalsU(o0RegP str1, o1RegP str2, g3RegI cnt, notemp_iRegI result,
10148 o7RegI tmp, flagsReg ccr) %{
10149 predicate(((StrEqualsNode*)n)->encoding() == StrIntrinsicNode::UU);
10150 match(Set result (StrEquals (Binary str1 str2) cnt));
10151 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt, KILL tmp, KILL ccr);
10152 ins_cost(300);
10153 format %{ "String Equals char[] $str1,$str2,$cnt -> $result // KILL $tmp" %}
10154 ins_encode %{
10155 __ array_equals(false, $str1$$Register, $str2$$Register,
10156 $cnt$$Register, $tmp$$Register,
10157 $result$$Register, false /* byte */);
10158 %}
10159 ins_pipe(long_memory_op);
10160 %}
10161
10162 instruct array_equalsB(o0RegP ary1, o1RegP ary2, g3RegI tmp1, notemp_iRegI result,
10163 o7RegI tmp2, flagsReg ccr) %{
10164 predicate(((AryEqNode*)n)->encoding() == StrIntrinsicNode::LL);
10165 match(Set result (AryEq ary1 ary2));
10166 effect(USE_KILL ary1, USE_KILL ary2, KILL tmp1, KILL tmp2, KILL ccr);
10167 ins_cost(300);
10168 format %{ "Array Equals $ary1,$ary2 -> $result // KILL $tmp1,$tmp2" %}
10169 ins_encode %{
10170 __ array_equals(true, $ary1$$Register, $ary2$$Register,
10171 $tmp1$$Register, $tmp2$$Register,
10172 $result$$Register, true /* byte */);
10173 %}
10174 ins_pipe(long_memory_op);
10175 %}
10176
10177 instruct array_equalsC(o0RegP ary1, o1RegP ary2, g3RegI tmp1, notemp_iRegI result,
10178 o7RegI tmp2, flagsReg ccr) %{
10179 predicate(((AryEqNode*)n)->encoding() == StrIntrinsicNode::UU);
10180 match(Set result (AryEq ary1 ary2));
10181 effect(USE_KILL ary1, USE_KILL ary2, KILL tmp1, KILL tmp2, KILL ccr);
10182 ins_cost(300);
10183 format %{ "Array Equals $ary1,$ary2 -> $result // KILL $tmp1,$tmp2" %}
10184 ins_encode %{
10185 __ array_equals(true, $ary1$$Register, $ary2$$Register,
10186 $tmp1$$Register, $tmp2$$Register,
10187 $result$$Register, false /* byte */);
10188 %}
10189 ins_pipe(long_memory_op);
10190 %}
10191
10192 // char[] to byte[] compression
10193 instruct string_compress(o0RegP src, o1RegP dst, g3RegI len, notemp_iRegI result, iRegL tmp, flagsReg ccr) %{
10194 predicate(UseVIS < 3);
10195 match(Set result (StrCompressedCopy src (Binary dst len)));
10196 effect(TEMP result, TEMP tmp, USE_KILL src, USE_KILL dst, USE_KILL len, KILL ccr);
10197 ins_cost(300);
10198 format %{ "String Compress $src,$dst,$len -> $result // KILL $tmp" %}
10199 ins_encode %{
10200 Label Ldone;
10201 __ signx($len$$Register);
10202 __ cmp_zero_and_br(Assembler::zero, $len$$Register, Ldone, false, Assembler::pn);
10203 __ delayed()->mov($len$$Register, $result$$Register); // copy count
10204 __ string_compress($src$$Register, $dst$$Register, $len$$Register, $result$$Register, $tmp$$Register, Ldone);
10205 __ bind(Ldone);
10206 %}
10207 ins_pipe(long_memory_op);
10208 %}
10209
10210 // fast char[] to byte[] compression using VIS instructions
10211 instruct string_compress_fast(o0RegP src, o1RegP dst, g3RegI len, notemp_iRegI result,
10212 iRegL tmp1, iRegL tmp2, iRegL tmp3, iRegL tmp4,
10213 regD ftmp1, regD ftmp2, regD ftmp3, flagsReg ccr) %{
10214 predicate(UseVIS >= 3);
10215 match(Set result (StrCompressedCopy src (Binary dst len)));
10216 effect(TEMP result, TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, TEMP ftmp1, TEMP ftmp2, TEMP ftmp3, USE_KILL src, USE_KILL dst, USE_KILL len, KILL ccr);
10217 ins_cost(300);
10218 format %{ "String Compress Fast $src,$dst,$len -> $result // KILL $tmp1,$tmp2,$tmp3,$tmp4,$ftmp1,$ftmp2,$ftmp3" %}
10219 ins_encode %{
10220 Label Ldone;
10221 __ signx($len$$Register);
10222 __ string_compress_16($src$$Register, $dst$$Register, $len$$Register, $result$$Register,
10223 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register, $tmp4$$Register,
10224 $ftmp1$$FloatRegister, $ftmp2$$FloatRegister, $ftmp3$$FloatRegister, Ldone);
10225 __ cmp_and_brx_short($len$$Register, 0, Assembler::equal, Assembler::pn, Ldone);
10226 __ string_compress($src$$Register, $dst$$Register, $len$$Register, $result$$Register, $tmp1$$Register, Ldone);
10227 __ bind(Ldone);
10228 %}
10229 ins_pipe(long_memory_op);
10230 %}
10231
10232 // byte[] to char[] inflation
10233 instruct string_inflate(Universe dummy, o0RegP src, o1RegP dst, g3RegI len,
10234 iRegL tmp, flagsReg ccr) %{
10235 match(Set dummy (StrInflatedCopy src (Binary dst len)));
10236 effect(TEMP tmp, USE_KILL src, USE_KILL dst, USE_KILL len, KILL ccr);
10237 ins_cost(300);
10238 format %{ "String Inflate $src,$dst,$len // KILL $tmp" %}
10239 ins_encode %{
10240 Label Ldone;
10241 __ signx($len$$Register);
10242 __ cmp_and_brx_short($len$$Register, 0, Assembler::equal, Assembler::pn, Ldone);
10243 __ string_inflate($src$$Register, $dst$$Register, $len$$Register, $tmp$$Register, Ldone);
10244 __ bind(Ldone);
10245 %}
10246 ins_pipe(long_memory_op);
10247 %}
10248
10249 // fast byte[] to char[] inflation using VIS instructions
10250 instruct string_inflate_fast(Universe dummy, o0RegP src, o1RegP dst, g3RegI len,
10251 iRegL tmp, regD ftmp1, regD ftmp2, regD ftmp3, regD ftmp4, flagsReg ccr) %{
10252 predicate(UseVIS >= 3);
10253 match(Set dummy (StrInflatedCopy src (Binary dst len)));
10254 effect(TEMP tmp, TEMP ftmp1, TEMP ftmp2, TEMP ftmp3, TEMP ftmp4, USE_KILL src, USE_KILL dst, USE_KILL len, KILL ccr);
10255 ins_cost(300);
10256 format %{ "String Inflate Fast $src,$dst,$len // KILL $tmp,$ftmp1,$ftmp2,$ftmp3,$ftmp4" %}
10257 ins_encode %{
10258 Label Ldone;
10259 __ signx($len$$Register);
10260 __ string_inflate_16($src$$Register, $dst$$Register, $len$$Register, $tmp$$Register,
10261 $ftmp1$$FloatRegister, $ftmp2$$FloatRegister, $ftmp3$$FloatRegister, $ftmp4$$FloatRegister, Ldone);
10262 __ cmp_and_brx_short($len$$Register, 0, Assembler::equal, Assembler::pn, Ldone);
10263 __ string_inflate($src$$Register, $dst$$Register, $len$$Register, $tmp$$Register, Ldone);
10264 __ bind(Ldone);
10265 %}
10266 ins_pipe(long_memory_op);
10267 %}
10268
10269
10270 //---------- Zeros Count Instructions ------------------------------------------
10271
10272 instruct countLeadingZerosI(iRegIsafe dst, iRegI src, iRegI tmp, flagsReg cr) %{
10273 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported
10274 match(Set dst (CountLeadingZerosI src));
10275 effect(TEMP dst, TEMP tmp, KILL cr);
10276
10277 // x |= (x >> 1);
10278 // x |= (x >> 2);
10279 // x |= (x >> 4);
10280 // x |= (x >> 8);
10281 // x |= (x >> 16);
10282 // return (WORDBITS - popc(x));
10283 format %{ "SRL $src,1,$tmp\t! count leading zeros (int)\n\t"
10284 "SRL $src,0,$dst\t! 32-bit zero extend\n\t"
10285 "OR $dst,$tmp,$dst\n\t"
10286 "SRL $dst,2,$tmp\n\t"
10287 "OR $dst,$tmp,$dst\n\t"
10288 "SRL $dst,4,$tmp\n\t"
10289 "OR $dst,$tmp,$dst\n\t"
10290 "SRL $dst,8,$tmp\n\t"
10291 "OR $dst,$tmp,$dst\n\t"
10292 "SRL $dst,16,$tmp\n\t"
10293 "OR $dst,$tmp,$dst\n\t"
10294 "POPC $dst,$dst\n\t"
10295 "MOV 32,$tmp\n\t"
10296 "SUB $tmp,$dst,$dst" %}
10297 ins_encode %{
10298 Register Rdst = $dst$$Register;
10299 Register Rsrc = $src$$Register;
10300 Register Rtmp = $tmp$$Register;
10301 __ srl(Rsrc, 1, Rtmp);
10302 __ srl(Rsrc, 0, Rdst);
10303 __ or3(Rdst, Rtmp, Rdst);
10304 __ srl(Rdst, 2, Rtmp);
10305 __ or3(Rdst, Rtmp, Rdst);
10306 __ srl(Rdst, 4, Rtmp);
10307 __ or3(Rdst, Rtmp, Rdst);
10308 __ srl(Rdst, 8, Rtmp);
10309 __ or3(Rdst, Rtmp, Rdst);
10310 __ srl(Rdst, 16, Rtmp);
10311 __ or3(Rdst, Rtmp, Rdst);
10312 __ popc(Rdst, Rdst);
10313 __ mov(BitsPerInt, Rtmp);
10314 __ sub(Rtmp, Rdst, Rdst);
10315 %}
10316 ins_pipe(ialu_reg);
10317 %}
10318
10319 instruct countLeadingZerosL(iRegIsafe dst, iRegL src, iRegL tmp, flagsReg cr) %{
10320 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported
10321 match(Set dst (CountLeadingZerosL src));
10322 effect(TEMP dst, TEMP tmp, KILL cr);
10323
10324 // x |= (x >> 1);
10325 // x |= (x >> 2);
10326 // x |= (x >> 4);
10327 // x |= (x >> 8);
10328 // x |= (x >> 16);
10329 // x |= (x >> 32);
10330 // return (WORDBITS - popc(x));
10331 format %{ "SRLX $src,1,$tmp\t! count leading zeros (long)\n\t"
10332 "OR $src,$tmp,$dst\n\t"
10333 "SRLX $dst,2,$tmp\n\t"
10334 "OR $dst,$tmp,$dst\n\t"
10335 "SRLX $dst,4,$tmp\n\t"
10336 "OR $dst,$tmp,$dst\n\t"
10337 "SRLX $dst,8,$tmp\n\t"
10338 "OR $dst,$tmp,$dst\n\t"
10339 "SRLX $dst,16,$tmp\n\t"
10340 "OR $dst,$tmp,$dst\n\t"
10341 "SRLX $dst,32,$tmp\n\t"
10342 "OR $dst,$tmp,$dst\n\t"
10343 "POPC $dst,$dst\n\t"
10344 "MOV 64,$tmp\n\t"
10345 "SUB $tmp,$dst,$dst" %}
10346 ins_encode %{
10347 Register Rdst = $dst$$Register;
10348 Register Rsrc = $src$$Register;
10349 Register Rtmp = $tmp$$Register;
10350 __ srlx(Rsrc, 1, Rtmp);
10351 __ or3( Rsrc, Rtmp, Rdst);
10352 __ srlx(Rdst, 2, Rtmp);
10353 __ or3( Rdst, Rtmp, Rdst);
10354 __ srlx(Rdst, 4, Rtmp);
10355 __ or3( Rdst, Rtmp, Rdst);
10356 __ srlx(Rdst, 8, Rtmp);
10357 __ or3( Rdst, Rtmp, Rdst);
10358 __ srlx(Rdst, 16, Rtmp);
10359 __ or3( Rdst, Rtmp, Rdst);
10360 __ srlx(Rdst, 32, Rtmp);
10361 __ or3( Rdst, Rtmp, Rdst);
10362 __ popc(Rdst, Rdst);
10363 __ mov(BitsPerLong, Rtmp);
10364 __ sub(Rtmp, Rdst, Rdst);
10365 %}
10366 ins_pipe(ialu_reg);
10367 %}
10368
10369 instruct countTrailingZerosI(iRegIsafe dst, iRegI src, flagsReg cr) %{
10370 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported
10371 match(Set dst (CountTrailingZerosI src));
10372 effect(TEMP dst, KILL cr);
10373
10374 // return popc(~x & (x - 1));
10375 format %{ "SUB $src,1,$dst\t! count trailing zeros (int)\n\t"
10376 "ANDN $dst,$src,$dst\n\t"
10377 "SRL $dst,R_G0,$dst\n\t"
10378 "POPC $dst,$dst" %}
10379 ins_encode %{
10380 Register Rdst = $dst$$Register;
10381 Register Rsrc = $src$$Register;
10382 __ sub(Rsrc, 1, Rdst);
10383 __ andn(Rdst, Rsrc, Rdst);
10384 __ srl(Rdst, G0, Rdst);
10385 __ popc(Rdst, Rdst);
10386 %}
10387 ins_pipe(ialu_reg);
10388 %}
10389
10390 instruct countTrailingZerosL(iRegIsafe dst, iRegL src, flagsReg cr) %{
10391 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported
10392 match(Set dst (CountTrailingZerosL src));
10393 effect(TEMP dst, KILL cr);
10394
10395 // return popc(~x & (x - 1));
10396 format %{ "SUB $src,1,$dst\t! count trailing zeros (long)\n\t"
10397 "ANDN $dst,$src,$dst\n\t"
10398 "POPC $dst,$dst" %}
10399 ins_encode %{
10400 Register Rdst = $dst$$Register;
10401 Register Rsrc = $src$$Register;
10402 __ sub(Rsrc, 1, Rdst);
10403 __ andn(Rdst, Rsrc, Rdst);
10404 __ popc(Rdst, Rdst);
10405 %}
10406 ins_pipe(ialu_reg);
10407 %}
10408
10409
10410 //---------- Population Count Instructions -------------------------------------
10411
10412 instruct popCountI(iRegIsafe dst, iRegI src) %{
10413 predicate(UsePopCountInstruction);
10414 match(Set dst (PopCountI src));
10415
10416 format %{ "SRL $src, G0, $dst\t! clear upper word for 64 bit POPC\n\t"
10417 "POPC $dst, $dst" %}
10418 ins_encode %{
10419 __ srl($src$$Register, G0, $dst$$Register);
10420 __ popc($dst$$Register, $dst$$Register);
10421 %}
10422 ins_pipe(ialu_reg);
10423 %}
10424
10425 // Note: Long.bitCount(long) returns an int.
10426 instruct popCountL(iRegIsafe dst, iRegL src) %{
10427 predicate(UsePopCountInstruction);
10428 match(Set dst (PopCountL src));
10429
10430 format %{ "POPC $src, $dst" %}
10431 ins_encode %{
10432 __ popc($src$$Register, $dst$$Register);
10433 %}
10434 ins_pipe(ialu_reg);
10435 %}
10436
10437
10438 // ============================================================================
10439 //------------Bytes reverse--------------------------------------------------
10440
10441 instruct bytes_reverse_int(iRegI dst, stackSlotI src) %{
10442 match(Set dst (ReverseBytesI src));
10443
10444 // Op cost is artificially doubled to make sure that load or store
10445 // instructions are preferred over this one which requires a spill
10446 // onto a stack slot.
10447 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST);
10448 format %{ "LDUWA $src, $dst\t!asi=primary_little" %}
10449
10450 ins_encode %{
10451 __ set($src$$disp + STACK_BIAS, O7);
10452 __ lduwa($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
10453 %}
10454 ins_pipe( iload_mem );
10455 %}
10456
10457 instruct bytes_reverse_long(iRegL dst, stackSlotL src) %{
10458 match(Set dst (ReverseBytesL src));
10459
10460 // Op cost is artificially doubled to make sure that load or store
10461 // instructions are preferred over this one which requires a spill
10462 // onto a stack slot.
10463 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST);
10464 format %{ "LDXA $src, $dst\t!asi=primary_little" %}
10465
10466 ins_encode %{
10467 __ set($src$$disp + STACK_BIAS, O7);
10468 __ ldxa($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
10469 %}
10470 ins_pipe( iload_mem );
10471 %}
10472
10473 instruct bytes_reverse_unsigned_short(iRegI dst, stackSlotI src) %{
10474 match(Set dst (ReverseBytesUS src));
10475
10476 // Op cost is artificially doubled to make sure that load or store
10477 // instructions are preferred over this one which requires a spill
10478 // onto a stack slot.
10479 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST);
10480 format %{ "LDUHA $src, $dst\t!asi=primary_little\n\t" %}
10481
10482 ins_encode %{
10483 // the value was spilled as an int so bias the load
10484 __ set($src$$disp + STACK_BIAS + 2, O7);
10485 __ lduha($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
10486 %}
10487 ins_pipe( iload_mem );
10488 %}
10489
10490 instruct bytes_reverse_short(iRegI dst, stackSlotI src) %{
10491 match(Set dst (ReverseBytesS src));
10492
10493 // Op cost is artificially doubled to make sure that load or store
10494 // instructions are preferred over this one which requires a spill
10495 // onto a stack slot.
10496 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST);
10497 format %{ "LDSHA $src, $dst\t!asi=primary_little\n\t" %}
10498
10499 ins_encode %{
10500 // the value was spilled as an int so bias the load
10501 __ set($src$$disp + STACK_BIAS + 2, O7);
10502 __ ldsha($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
10503 %}
10504 ins_pipe( iload_mem );
10505 %}
10506
10507 // Load Integer reversed byte order
10508 instruct loadI_reversed(iRegI dst, indIndexMemory src) %{
10509 match(Set dst (ReverseBytesI (LoadI src)));
10510
10511 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
10512 size(4);
10513 format %{ "LDUWA $src, $dst\t!asi=primary_little" %}
10514
10515 ins_encode %{
10516 __ lduwa($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
10517 %}
10518 ins_pipe(iload_mem);
10519 %}
10520
10521 // Load Long - aligned and reversed
10522 instruct loadL_reversed(iRegL dst, indIndexMemory src) %{
10523 match(Set dst (ReverseBytesL (LoadL src)));
10524
10525 ins_cost(MEMORY_REF_COST);
10526 size(4);
10527 format %{ "LDXA $src, $dst\t!asi=primary_little" %}
10528
10529 ins_encode %{
10530 __ ldxa($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
10531 %}
10532 ins_pipe(iload_mem);
10533 %}
10534
10535 // Load unsigned short / char reversed byte order
10536 instruct loadUS_reversed(iRegI dst, indIndexMemory src) %{
10537 match(Set dst (ReverseBytesUS (LoadUS src)));
10538
10539 ins_cost(MEMORY_REF_COST);
10540 size(4);
10541 format %{ "LDUHA $src, $dst\t!asi=primary_little" %}
10542
10543 ins_encode %{
10544 __ lduha($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
10545 %}
10546 ins_pipe(iload_mem);
10547 %}
10548
10549 // Load short reversed byte order
10550 instruct loadS_reversed(iRegI dst, indIndexMemory src) %{
10551 match(Set dst (ReverseBytesS (LoadS src)));
10552
10553 ins_cost(MEMORY_REF_COST);
10554 size(4);
10555 format %{ "LDSHA $src, $dst\t!asi=primary_little" %}
10556
10557 ins_encode %{
10558 __ ldsha($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
10559 %}
10560 ins_pipe(iload_mem);
10561 %}
10562
10563 // Store Integer reversed byte order
10564 instruct storeI_reversed(indIndexMemory dst, iRegI src) %{
10565 match(Set dst (StoreI dst (ReverseBytesI src)));
10566
10567 ins_cost(MEMORY_REF_COST);
10568 size(4);
10569 format %{ "STWA $src, $dst\t!asi=primary_little" %}
10570
10571 ins_encode %{
10572 __ stwa($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE);
10573 %}
10574 ins_pipe(istore_mem_reg);
10575 %}
10576
10577 // Store Long reversed byte order
10578 instruct storeL_reversed(indIndexMemory dst, iRegL src) %{
10579 match(Set dst (StoreL dst (ReverseBytesL src)));
10580
10581 ins_cost(MEMORY_REF_COST);
10582 size(4);
10583 format %{ "STXA $src, $dst\t!asi=primary_little" %}
10584
10585 ins_encode %{
10586 __ stxa($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE);
10587 %}
10588 ins_pipe(istore_mem_reg);
10589 %}
10590
10591 // Store unsighed short/char reversed byte order
10592 instruct storeUS_reversed(indIndexMemory dst, iRegI src) %{
10593 match(Set dst (StoreC dst (ReverseBytesUS src)));
10594
10595 ins_cost(MEMORY_REF_COST);
10596 size(4);
10597 format %{ "STHA $src, $dst\t!asi=primary_little" %}
10598
10599 ins_encode %{
10600 __ stha($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE);
10601 %}
10602 ins_pipe(istore_mem_reg);
10603 %}
10604
10605 // Store short reversed byte order
10606 instruct storeS_reversed(indIndexMemory dst, iRegI src) %{
10607 match(Set dst (StoreC dst (ReverseBytesS src)));
10608
10609 ins_cost(MEMORY_REF_COST);
10610 size(4);
10611 format %{ "STHA $src, $dst\t!asi=primary_little" %}
10612
10613 ins_encode %{
10614 __ stha($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE);
10615 %}
10616 ins_pipe(istore_mem_reg);
10617 %}
10618
10619 // ====================VECTOR INSTRUCTIONS=====================================
10620
10621 // Load Aligned Packed values into a Double Register
10622 instruct loadV8(regD dst, memory mem) %{
10623 predicate(n->as_LoadVector()->memory_size() == 8);
10624 match(Set dst (LoadVector mem));
10625 ins_cost(MEMORY_REF_COST);
10626 size(4);
10627 format %{ "LDDF $mem,$dst\t! load vector (8 bytes)" %}
10628 ins_encode %{
10629 __ ldf(FloatRegisterImpl::D, $mem$$Address, as_DoubleFloatRegister($dst$$reg));
10630 %}
10631 ins_pipe(floadD_mem);
10632 %}
10633
10634 // Store Vector in Double register to memory
10635 instruct storeV8(memory mem, regD src) %{
10636 predicate(n->as_StoreVector()->memory_size() == 8);
10637 match(Set mem (StoreVector mem src));
10638 ins_cost(MEMORY_REF_COST);
10639 size(4);
10640 format %{ "STDF $src,$mem\t! store vector (8 bytes)" %}
10641 ins_encode %{
10642 __ stf(FloatRegisterImpl::D, as_DoubleFloatRegister($src$$reg), $mem$$Address);
10643 %}
10644 ins_pipe(fstoreD_mem_reg);
10645 %}
10646
10647 // Store Zero into vector in memory
10648 instruct storeV8B_zero(memory mem, immI0 zero) %{
10649 predicate(n->as_StoreVector()->memory_size() == 8);
10650 match(Set mem (StoreVector mem (ReplicateB zero)));
10651 ins_cost(MEMORY_REF_COST);
10652 size(4);
10653 format %{ "STX $zero,$mem\t! store zero vector (8 bytes)" %}
10654 ins_encode %{
10655 __ stx(G0, $mem$$Address);
10656 %}
10657 ins_pipe(fstoreD_mem_zero);
10658 %}
10659
10660 instruct storeV4S_zero(memory mem, immI0 zero) %{
10661 predicate(n->as_StoreVector()->memory_size() == 8);
10662 match(Set mem (StoreVector mem (ReplicateS zero)));
10663 ins_cost(MEMORY_REF_COST);
10664 size(4);
10665 format %{ "STX $zero,$mem\t! store zero vector (4 shorts)" %}
10666 ins_encode %{
10667 __ stx(G0, $mem$$Address);
10668 %}
10669 ins_pipe(fstoreD_mem_zero);
10670 %}
10671
10672 instruct storeV2I_zero(memory mem, immI0 zero) %{
10673 predicate(n->as_StoreVector()->memory_size() == 8);
10674 match(Set mem (StoreVector mem (ReplicateI zero)));
10675 ins_cost(MEMORY_REF_COST);
10676 size(4);
10677 format %{ "STX $zero,$mem\t! store zero vector (2 ints)" %}
10678 ins_encode %{
10679 __ stx(G0, $mem$$Address);
10680 %}
10681 ins_pipe(fstoreD_mem_zero);
10682 %}
10683
10684 instruct storeV2F_zero(memory mem, immF0 zero) %{
10685 predicate(n->as_StoreVector()->memory_size() == 8);
10686 match(Set mem (StoreVector mem (ReplicateF zero)));
10687 ins_cost(MEMORY_REF_COST);
10688 size(4);
10689 format %{ "STX $zero,$mem\t! store zero vector (2 floats)" %}
10690 ins_encode %{
10691 __ stx(G0, $mem$$Address);
10692 %}
10693 ins_pipe(fstoreD_mem_zero);
10694 %}
10695
10696 // Replicate scalar to packed byte values into Double register
10697 instruct Repl8B_reg(regD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{
10698 predicate(n->as_Vector()->length() == 8 && UseVIS >= 3);
10699 match(Set dst (ReplicateB src));
10700 effect(DEF dst, USE src, TEMP tmp, KILL tmp2);
10701 format %{ "SLLX $src,56,$tmp\n\t"
10702 "SRLX $tmp, 8,$tmp2\n\t"
10703 "OR $tmp,$tmp2,$tmp\n\t"
10704 "SRLX $tmp,16,$tmp2\n\t"
10705 "OR $tmp,$tmp2,$tmp\n\t"
10706 "SRLX $tmp,32,$tmp2\n\t"
10707 "OR $tmp,$tmp2,$tmp\t! replicate8B\n\t"
10708 "MOVXTOD $tmp,$dst\t! MoveL2D" %}
10709 ins_encode %{
10710 Register Rsrc = $src$$Register;
10711 Register Rtmp = $tmp$$Register;
10712 Register Rtmp2 = $tmp2$$Register;
10713 __ sllx(Rsrc, 56, Rtmp);
10714 __ srlx(Rtmp, 8, Rtmp2);
10715 __ or3 (Rtmp, Rtmp2, Rtmp);
10716 __ srlx(Rtmp, 16, Rtmp2);
10717 __ or3 (Rtmp, Rtmp2, Rtmp);
10718 __ srlx(Rtmp, 32, Rtmp2);
10719 __ or3 (Rtmp, Rtmp2, Rtmp);
10720 __ movxtod(Rtmp, as_DoubleFloatRegister($dst$$reg));
10721 %}
10722 ins_pipe(ialu_reg);
10723 %}
10724
10725 // Replicate scalar to packed byte values into Double stack
10726 instruct Repl8B_stk(stackSlotD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{
10727 predicate(n->as_Vector()->length() == 8 && UseVIS < 3);
10728 match(Set dst (ReplicateB src));
10729 effect(DEF dst, USE src, TEMP tmp, KILL tmp2);
10730 format %{ "SLLX $src,56,$tmp\n\t"
10731 "SRLX $tmp, 8,$tmp2\n\t"
10732 "OR $tmp,$tmp2,$tmp\n\t"
10733 "SRLX $tmp,16,$tmp2\n\t"
10734 "OR $tmp,$tmp2,$tmp\n\t"
10735 "SRLX $tmp,32,$tmp2\n\t"
10736 "OR $tmp,$tmp2,$tmp\t! replicate8B\n\t"
10737 "STX $tmp,$dst\t! regL to stkD" %}
10738 ins_encode %{
10739 Register Rsrc = $src$$Register;
10740 Register Rtmp = $tmp$$Register;
10741 Register Rtmp2 = $tmp2$$Register;
10742 __ sllx(Rsrc, 56, Rtmp);
10743 __ srlx(Rtmp, 8, Rtmp2);
10744 __ or3 (Rtmp, Rtmp2, Rtmp);
10745 __ srlx(Rtmp, 16, Rtmp2);
10746 __ or3 (Rtmp, Rtmp2, Rtmp);
10747 __ srlx(Rtmp, 32, Rtmp2);
10748 __ or3 (Rtmp, Rtmp2, Rtmp);
10749 __ set ($dst$$disp + STACK_BIAS, Rtmp2);
10750 __ stx (Rtmp, Rtmp2, $dst$$base$$Register);
10751 %}
10752 ins_pipe(ialu_reg);
10753 %}
10754
10755 // Replicate scalar constant to packed byte values in Double register
10756 instruct Repl8B_immI(regD dst, immI13 con, o7RegI tmp) %{
10757 predicate(n->as_Vector()->length() == 8);
10758 match(Set dst (ReplicateB con));
10759 effect(KILL tmp);
10760 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl8B($con)" %}
10761 ins_encode %{
10762 // XXX This is a quick fix for 6833573.
10763 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immI($con$$constant, 8, 1)), $dst$$FloatRegister);
10764 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset(replicate_immI($con$$constant, 8, 1)), $tmp$$Register);
10765 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg));
10766 %}
10767 ins_pipe(loadConFD);
10768 %}
10769
10770 // Replicate scalar to packed char/short values into Double register
10771 instruct Repl4S_reg(regD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{
10772 predicate(n->as_Vector()->length() == 4 && UseVIS >= 3);
10773 match(Set dst (ReplicateS src));
10774 effect(DEF dst, USE src, TEMP tmp, KILL tmp2);
10775 format %{ "SLLX $src,48,$tmp\n\t"
10776 "SRLX $tmp,16,$tmp2\n\t"
10777 "OR $tmp,$tmp2,$tmp\n\t"
10778 "SRLX $tmp,32,$tmp2\n\t"
10779 "OR $tmp,$tmp2,$tmp\t! replicate4S\n\t"
10780 "MOVXTOD $tmp,$dst\t! MoveL2D" %}
10781 ins_encode %{
10782 Register Rsrc = $src$$Register;
10783 Register Rtmp = $tmp$$Register;
10784 Register Rtmp2 = $tmp2$$Register;
10785 __ sllx(Rsrc, 48, Rtmp);
10786 __ srlx(Rtmp, 16, Rtmp2);
10787 __ or3 (Rtmp, Rtmp2, Rtmp);
10788 __ srlx(Rtmp, 32, Rtmp2);
10789 __ or3 (Rtmp, Rtmp2, Rtmp);
10790 __ movxtod(Rtmp, as_DoubleFloatRegister($dst$$reg));
10791 %}
10792 ins_pipe(ialu_reg);
10793 %}
10794
10795 // Replicate scalar to packed char/short values into Double stack
10796 instruct Repl4S_stk(stackSlotD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{
10797 predicate(n->as_Vector()->length() == 4 && UseVIS < 3);
10798 match(Set dst (ReplicateS src));
10799 effect(DEF dst, USE src, TEMP tmp, KILL tmp2);
10800 format %{ "SLLX $src,48,$tmp\n\t"
10801 "SRLX $tmp,16,$tmp2\n\t"
10802 "OR $tmp,$tmp2,$tmp\n\t"
10803 "SRLX $tmp,32,$tmp2\n\t"
10804 "OR $tmp,$tmp2,$tmp\t! replicate4S\n\t"
10805 "STX $tmp,$dst\t! regL to stkD" %}
10806 ins_encode %{
10807 Register Rsrc = $src$$Register;
10808 Register Rtmp = $tmp$$Register;
10809 Register Rtmp2 = $tmp2$$Register;
10810 __ sllx(Rsrc, 48, Rtmp);
10811 __ srlx(Rtmp, 16, Rtmp2);
10812 __ or3 (Rtmp, Rtmp2, Rtmp);
10813 __ srlx(Rtmp, 32, Rtmp2);
10814 __ or3 (Rtmp, Rtmp2, Rtmp);
10815 __ set ($dst$$disp + STACK_BIAS, Rtmp2);
10816 __ stx (Rtmp, Rtmp2, $dst$$base$$Register);
10817 %}
10818 ins_pipe(ialu_reg);
10819 %}
10820
10821 // Replicate scalar constant to packed char/short values in Double register
10822 instruct Repl4S_immI(regD dst, immI con, o7RegI tmp) %{
10823 predicate(n->as_Vector()->length() == 4);
10824 match(Set dst (ReplicateS con));
10825 effect(KILL tmp);
10826 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl4S($con)" %}
10827 ins_encode %{
10828 // XXX This is a quick fix for 6833573.
10829 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immI($con$$constant, 4, 2)), $dst$$FloatRegister);
10830 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset(replicate_immI($con$$constant, 4, 2)), $tmp$$Register);
10831 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg));
10832 %}
10833 ins_pipe(loadConFD);
10834 %}
10835
10836 // Replicate scalar to packed int values into Double register
10837 instruct Repl2I_reg(regD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{
10838 predicate(n->as_Vector()->length() == 2 && UseVIS >= 3);
10839 match(Set dst (ReplicateI src));
10840 effect(DEF dst, USE src, TEMP tmp, KILL tmp2);
10841 format %{ "SLLX $src,32,$tmp\n\t"
10842 "SRLX $tmp,32,$tmp2\n\t"
10843 "OR $tmp,$tmp2,$tmp\t! replicate2I\n\t"
10844 "MOVXTOD $tmp,$dst\t! MoveL2D" %}
10845 ins_encode %{
10846 Register Rsrc = $src$$Register;
10847 Register Rtmp = $tmp$$Register;
10848 Register Rtmp2 = $tmp2$$Register;
10849 __ sllx(Rsrc, 32, Rtmp);
10850 __ srlx(Rtmp, 32, Rtmp2);
10851 __ or3 (Rtmp, Rtmp2, Rtmp);
10852 __ movxtod(Rtmp, as_DoubleFloatRegister($dst$$reg));
10853 %}
10854 ins_pipe(ialu_reg);
10855 %}
10856
10857 // Replicate scalar to packed int values into Double stack
10858 instruct Repl2I_stk(stackSlotD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{
10859 predicate(n->as_Vector()->length() == 2 && UseVIS < 3);
10860 match(Set dst (ReplicateI src));
10861 effect(DEF dst, USE src, TEMP tmp, KILL tmp2);
10862 format %{ "SLLX $src,32,$tmp\n\t"
10863 "SRLX $tmp,32,$tmp2\n\t"
10864 "OR $tmp,$tmp2,$tmp\t! replicate2I\n\t"
10865 "STX $tmp,$dst\t! regL to stkD" %}
10866 ins_encode %{
10867 Register Rsrc = $src$$Register;
10868 Register Rtmp = $tmp$$Register;
10869 Register Rtmp2 = $tmp2$$Register;
10870 __ sllx(Rsrc, 32, Rtmp);
10871 __ srlx(Rtmp, 32, Rtmp2);
10872 __ or3 (Rtmp, Rtmp2, Rtmp);
10873 __ set ($dst$$disp + STACK_BIAS, Rtmp2);
10874 __ stx (Rtmp, Rtmp2, $dst$$base$$Register);
10875 %}
10876 ins_pipe(ialu_reg);
10877 %}
10878
10879 // Replicate scalar zero constant to packed int values in Double register
10880 instruct Repl2I_immI(regD dst, immI con, o7RegI tmp) %{
10881 predicate(n->as_Vector()->length() == 2);
10882 match(Set dst (ReplicateI con));
10883 effect(KILL tmp);
10884 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl2I($con)" %}
10885 ins_encode %{
10886 // XXX This is a quick fix for 6833573.
10887 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immI($con$$constant, 2, 4)), $dst$$FloatRegister);
10888 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset(replicate_immI($con$$constant, 2, 4)), $tmp$$Register);
10889 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg));
10890 %}
10891 ins_pipe(loadConFD);
10892 %}
10893
10894 // Replicate scalar to packed float values into Double stack
10895 instruct Repl2F_stk(stackSlotD dst, regF src) %{
10896 predicate(n->as_Vector()->length() == 2);
10897 match(Set dst (ReplicateF src));
10898 ins_cost(MEMORY_REF_COST*2);
10899 format %{ "STF $src,$dst.hi\t! packed2F\n\t"
10900 "STF $src,$dst.lo" %}
10901 opcode(Assembler::stf_op3);
10902 ins_encode(simple_form3_mem_reg(dst, src), form3_mem_plus_4_reg(dst, src));
10903 ins_pipe(fstoreF_stk_reg);
10904 %}
10905
10906 // Replicate scalar zero constant to packed float values in Double register
10907 instruct Repl2F_immF(regD dst, immF con, o7RegI tmp) %{
10908 predicate(n->as_Vector()->length() == 2);
10909 match(Set dst (ReplicateF con));
10910 effect(KILL tmp);
10911 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl2F($con)" %}
10912 ins_encode %{
10913 // XXX This is a quick fix for 6833573.
10914 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immF($con$$constant)), $dst$$FloatRegister);
10915 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset(replicate_immF($con$$constant)), $tmp$$Register);
10916 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg));
10917 %}
10918 ins_pipe(loadConFD);
10919 %}
10920
10921 //----------PEEPHOLE RULES-----------------------------------------------------
10922 // These must follow all instruction definitions as they use the names
10923 // defined in the instructions definitions.
10924 //
10925 // peepmatch ( root_instr_name [preceding_instruction]* );
10926 //
10927 // peepconstraint %{
10928 // (instruction_number.operand_name relational_op instruction_number.operand_name
10929 // [, ...] );
10930 // // instruction numbers are zero-based using left to right order in peepmatch
10931 //
10932 // peepreplace ( instr_name ( [instruction_number.operand_name]* ) );
10933 // // provide an instruction_number.operand_name for each operand that appears
10934 // // in the replacement instruction's match rule
10935 //
10936 // ---------VM FLAGS---------------------------------------------------------
10937 //
10938 // All peephole optimizations can be turned off using -XX:-OptoPeephole
10939 //
10940 // Each peephole rule is given an identifying number starting with zero and
10941 // increasing by one in the order seen by the parser. An individual peephole
10942 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=#
10943 // on the command-line.
10944 //
10945 // ---------CURRENT LIMITATIONS----------------------------------------------
10946 //
10947 // Only match adjacent instructions in same basic block
10948 // Only equality constraints
10949 // Only constraints between operands, not (0.dest_reg == EAX_enc)
10950 // Only one replacement instruction
10951 //
10952 // ---------EXAMPLE----------------------------------------------------------
10953 //
10954 // // pertinent parts of existing instructions in architecture description
10955 // instruct movI(eRegI dst, eRegI src) %{
10956 // match(Set dst (CopyI src));
10957 // %}
10958 //
10959 // instruct incI_eReg(eRegI dst, immI1 src, eFlagsReg cr) %{
10960 // match(Set dst (AddI dst src));
10961 // effect(KILL cr);
10962 // %}
10963 //
10964 // // Change (inc mov) to lea
10965 // peephole %{
10966 // // increment preceeded by register-register move
10967 // peepmatch ( incI_eReg movI );
10968 // // require that the destination register of the increment
10969 // // match the destination register of the move
10970 // peepconstraint ( 0.dst == 1.dst );
10971 // // construct a replacement instruction that sets
10972 // // the destination to ( move's source register + one )
10973 // peepreplace ( incI_eReg_immI1( 0.dst 1.src 0.src ) );
10974 // %}
10975 //
10976
10977 // // Change load of spilled value to only a spill
10978 // instruct storeI(memory mem, eRegI src) %{
10979 // match(Set mem (StoreI mem src));
10980 // %}
10981 //
10982 // instruct loadI(eRegI dst, memory mem) %{
10983 // match(Set dst (LoadI mem));
10984 // %}
10985 //
10986 // peephole %{
10987 // peepmatch ( loadI storeI );
10988 // peepconstraint ( 1.src == 0.dst, 1.mem == 0.mem );
10989 // peepreplace ( storeI( 1.mem 1.mem 1.src ) );
10990 // %}
10991
10992 //----------SMARTSPILL RULES---------------------------------------------------
10993 // These must follow all instruction definitions as they use the names
10994 // defined in the instructions definitions.
10995 //
10996 // SPARC will probably not have any of these rules due to RISC instruction set.
10997
10998 //----------PIPELINE-----------------------------------------------------------
10999 // Rules which define the behavior of the target architectures pipeline.
--- EOF ---