1 /*
2 * Copyright (c) 1997, 2016, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #include "precompiled.hpp"
26 #include "asm/macroAssembler.inline.hpp"
27 #include "compiler/disassembler.hpp"
28 #include "gc/shared/cardTableModRefBS.hpp"
29 #include "gc/shared/collectedHeap.inline.hpp"
30 #include "interpreter/interpreter.hpp"
31 #include "memory/resourceArea.hpp"
32 #include "memory/universe.hpp"
33 #include "oops/klass.inline.hpp"
34 #include "prims/methodHandles.hpp"
35 #include "runtime/biasedLocking.hpp"
36 #include "runtime/interfaceSupport.hpp"
37 #include "runtime/objectMonitor.hpp"
38 #include "runtime/os.inline.hpp"
39 #include "runtime/sharedRuntime.hpp"
40 #include "runtime/stubRoutines.hpp"
41 #include "utilities/macros.hpp"
42 #if INCLUDE_ALL_GCS
43 #include "gc/g1/g1CollectedHeap.inline.hpp"
44 #include "gc/g1/g1SATBCardTableModRefBS.hpp"
45 #include "gc/g1/heapRegion.hpp"
46 #endif // INCLUDE_ALL_GCS
47 #ifdef COMPILER2
48 #include "opto/intrinsicnode.hpp"
49 #endif
50
51 #ifdef PRODUCT
52 #define BLOCK_COMMENT(str) /* nothing */
53 #define STOP(error) stop(error)
54 #else
55 #define BLOCK_COMMENT(str) block_comment(str)
56 #define STOP(error) block_comment(error); stop(error)
57 #endif
58
59 // Convert the raw encoding form into the form expected by the
60 // constructor for Address.
61 Address Address::make_raw(int base, int index, int scale, int disp, relocInfo::relocType disp_reloc) {
62 assert(scale == 0, "not supported");
63 RelocationHolder rspec;
64 if (disp_reloc != relocInfo::none) {
65 rspec = Relocation::spec_simple(disp_reloc);
66 }
67
68 Register rindex = as_Register(index);
69 if (rindex != G0) {
70 Address madr(as_Register(base), rindex);
71 madr._rspec = rspec;
72 return madr;
73 } else {
74 Address madr(as_Register(base), disp);
75 madr._rspec = rspec;
76 return madr;
77 }
78 }
79
80 Address Argument::address_in_frame() const {
81 // Warning: In LP64 mode disp will occupy more than 10 bits, but
82 // op codes such as ld or ldx, only access disp() to get
83 // their simm13 argument.
84 int disp = ((_number - Argument::n_register_parameters + frame::memory_parameter_word_sp_offset) * BytesPerWord) + STACK_BIAS;
85 if (is_in())
86 return Address(FP, disp); // In argument.
87 else
88 return Address(SP, disp); // Out argument.
89 }
90
91 static const char* argumentNames[][2] = {
92 {"A0","P0"}, {"A1","P1"}, {"A2","P2"}, {"A3","P3"}, {"A4","P4"},
93 {"A5","P5"}, {"A6","P6"}, {"A7","P7"}, {"A8","P8"}, {"A9","P9"},
94 {"A(n>9)","P(n>9)"}
95 };
96
97 const char* Argument::name() const {
98 int nofArgs = sizeof argumentNames / sizeof argumentNames[0];
99 int num = number();
100 if (num >= nofArgs) num = nofArgs - 1;
101 return argumentNames[num][is_in() ? 1 : 0];
102 }
103
104 #ifdef ASSERT
105 // On RISC, there's no benefit to verifying instruction boundaries.
106 bool AbstractAssembler::pd_check_instruction_mark() { return false; }
107 #endif
108
109 // Patch instruction inst at offset inst_pos to refer to dest_pos
110 // and return the resulting instruction.
111 // We should have pcs, not offsets, but since all is relative, it will work out
112 // OK.
113 int MacroAssembler::patched_branch(int dest_pos, int inst, int inst_pos) {
114 int m; // mask for displacement field
115 int v; // new value for displacement field
116 const int word_aligned_ones = -4;
117 switch (inv_op(inst)) {
118 default: ShouldNotReachHere();
119 case call_op: m = wdisp(word_aligned_ones, 0, 30); v = wdisp(dest_pos, inst_pos, 30); break;
120 case branch_op:
121 switch (inv_op2(inst)) {
122 case fbp_op2: m = wdisp( word_aligned_ones, 0, 19); v = wdisp( dest_pos, inst_pos, 19); break;
123 case bp_op2: m = wdisp( word_aligned_ones, 0, 19); v = wdisp( dest_pos, inst_pos, 19); break;
124 case fb_op2: m = wdisp( word_aligned_ones, 0, 22); v = wdisp( dest_pos, inst_pos, 22); break;
125 case br_op2: m = wdisp( word_aligned_ones, 0, 22); v = wdisp( dest_pos, inst_pos, 22); break;
126 case bpr_op2: {
127 if (is_cbcond(inst)) {
128 m = wdisp10(word_aligned_ones, 0);
129 v = wdisp10(dest_pos, inst_pos);
130 } else {
131 m = wdisp16(word_aligned_ones, 0);
132 v = wdisp16(dest_pos, inst_pos);
133 }
134 break;
135 }
136 default: ShouldNotReachHere();
137 }
138 }
139 return inst & ~m | v;
140 }
141
142 // Return the offset of the branch destionation of instruction inst
143 // at offset pos.
144 // Should have pcs, but since all is relative, it works out.
145 int MacroAssembler::branch_destination(int inst, int pos) {
146 int r;
147 switch (inv_op(inst)) {
148 default: ShouldNotReachHere();
149 case call_op: r = inv_wdisp(inst, pos, 30); break;
150 case branch_op:
151 switch (inv_op2(inst)) {
152 case fbp_op2: r = inv_wdisp( inst, pos, 19); break;
153 case bp_op2: r = inv_wdisp( inst, pos, 19); break;
154 case fb_op2: r = inv_wdisp( inst, pos, 22); break;
155 case br_op2: r = inv_wdisp( inst, pos, 22); break;
156 case bpr_op2: {
157 if (is_cbcond(inst)) {
158 r = inv_wdisp10(inst, pos);
159 } else {
160 r = inv_wdisp16(inst, pos);
161 }
162 break;
163 }
164 default: ShouldNotReachHere();
165 }
166 }
167 return r;
168 }
169
170 void MacroAssembler::null_check(Register reg, int offset) {
171 if (needs_explicit_null_check((intptr_t)offset)) {
172 // provoke OS NULL exception if reg = NULL by
173 // accessing M[reg] w/o changing any registers
174 ld_ptr(reg, 0, G0);
175 }
176 else {
177 // nothing to do, (later) access of M[reg + offset]
178 // will provoke OS NULL exception if reg = NULL
179 }
180 }
181
182 // Ring buffer jumps
183
184 #ifndef PRODUCT
185 void MacroAssembler::ret( bool trace ) { if (trace) {
186 mov(I7, O7); // traceable register
187 JMP(O7, 2 * BytesPerInstWord);
188 } else {
189 jmpl( I7, 2 * BytesPerInstWord, G0 );
190 }
191 }
192
193 void MacroAssembler::retl( bool trace ) { if (trace) JMP(O7, 2 * BytesPerInstWord);
194 else jmpl( O7, 2 * BytesPerInstWord, G0 ); }
195 #endif /* PRODUCT */
196
197
198 void MacroAssembler::jmp2(Register r1, Register r2, const char* file, int line ) {
199 assert_not_delayed();
200 // This can only be traceable if r1 & r2 are visible after a window save
201 if (TraceJumps) {
202 #ifndef PRODUCT
203 save_frame(0);
204 verify_thread();
205 ld(G2_thread, in_bytes(JavaThread::jmp_ring_index_offset()), O0);
206 add(G2_thread, in_bytes(JavaThread::jmp_ring_offset()), O1);
207 sll(O0, exact_log2(4*sizeof(intptr_t)), O2);
208 add(O2, O1, O1);
209
210 add(r1->after_save(), r2->after_save(), O2);
211 set((intptr_t)file, O3);
212 set(line, O4);
213 Label L;
214 // get nearby pc, store jmp target
215 call(L, relocInfo::none); // No relocation for call to pc+0x8
216 delayed()->st(O2, O1, 0);
217 bind(L);
218
219 // store nearby pc
220 st(O7, O1, sizeof(intptr_t));
221 // store file
222 st(O3, O1, 2*sizeof(intptr_t));
223 // store line
224 st(O4, O1, 3*sizeof(intptr_t));
225 add(O0, 1, O0);
226 and3(O0, JavaThread::jump_ring_buffer_size - 1, O0);
227 st(O0, G2_thread, in_bytes(JavaThread::jmp_ring_index_offset()));
228 restore();
229 #endif /* PRODUCT */
230 }
231 jmpl(r1, r2, G0);
232 }
233 void MacroAssembler::jmp(Register r1, int offset, const char* file, int line ) {
234 assert_not_delayed();
235 // This can only be traceable if r1 is visible after a window save
236 if (TraceJumps) {
237 #ifndef PRODUCT
238 save_frame(0);
239 verify_thread();
240 ld(G2_thread, in_bytes(JavaThread::jmp_ring_index_offset()), O0);
241 add(G2_thread, in_bytes(JavaThread::jmp_ring_offset()), O1);
242 sll(O0, exact_log2(4*sizeof(intptr_t)), O2);
243 add(O2, O1, O1);
244
245 add(r1->after_save(), offset, O2);
246 set((intptr_t)file, O3);
247 set(line, O4);
248 Label L;
249 // get nearby pc, store jmp target
250 call(L, relocInfo::none); // No relocation for call to pc+0x8
251 delayed()->st(O2, O1, 0);
252 bind(L);
253
254 // store nearby pc
255 st(O7, O1, sizeof(intptr_t));
256 // store file
257 st(O3, O1, 2*sizeof(intptr_t));
258 // store line
259 st(O4, O1, 3*sizeof(intptr_t));
260 add(O0, 1, O0);
261 and3(O0, JavaThread::jump_ring_buffer_size - 1, O0);
262 st(O0, G2_thread, in_bytes(JavaThread::jmp_ring_index_offset()));
263 restore();
264 #endif /* PRODUCT */
265 }
266 jmp(r1, offset);
267 }
268
269 // This code sequence is relocatable to any address, even on LP64.
270 void MacroAssembler::jumpl(const AddressLiteral& addrlit, Register temp, Register d, int offset, const char* file, int line) {
271 assert_not_delayed();
272 // Force fixed length sethi because NativeJump and NativeFarCall don't handle
273 // variable length instruction streams.
274 patchable_sethi(addrlit, temp);
275 Address a(temp, addrlit.low10() + offset); // Add the offset to the displacement.
276 if (TraceJumps) {
277 #ifndef PRODUCT
278 // Must do the add here so relocation can find the remainder of the
279 // value to be relocated.
280 add(a.base(), a.disp(), a.base(), addrlit.rspec(offset));
281 save_frame(0);
282 verify_thread();
283 ld(G2_thread, in_bytes(JavaThread::jmp_ring_index_offset()), O0);
284 add(G2_thread, in_bytes(JavaThread::jmp_ring_offset()), O1);
285 sll(O0, exact_log2(4*sizeof(intptr_t)), O2);
286 add(O2, O1, O1);
287
288 set((intptr_t)file, O3);
289 set(line, O4);
290 Label L;
291
292 // get nearby pc, store jmp target
293 call(L, relocInfo::none); // No relocation for call to pc+0x8
294 delayed()->st(a.base()->after_save(), O1, 0);
295 bind(L);
296
297 // store nearby pc
298 st(O7, O1, sizeof(intptr_t));
299 // store file
300 st(O3, O1, 2*sizeof(intptr_t));
301 // store line
302 st(O4, O1, 3*sizeof(intptr_t));
303 add(O0, 1, O0);
304 and3(O0, JavaThread::jump_ring_buffer_size - 1, O0);
305 st(O0, G2_thread, in_bytes(JavaThread::jmp_ring_index_offset()));
306 restore();
307 jmpl(a.base(), G0, d);
308 #else
309 jmpl(a.base(), a.disp(), d);
310 #endif /* PRODUCT */
311 } else {
312 jmpl(a.base(), a.disp(), d);
313 }
314 }
315
316 void MacroAssembler::jump(const AddressLiteral& addrlit, Register temp, int offset, const char* file, int line) {
317 jumpl(addrlit, temp, G0, offset, file, line);
318 }
319
320
321 // Conditional breakpoint (for assertion checks in assembly code)
322 void MacroAssembler::breakpoint_trap(Condition c, CC cc) {
323 trap(c, cc, G0, ST_RESERVED_FOR_USER_0);
324 }
325
326 // We want to use ST_BREAKPOINT here, but the debugger is confused by it.
327 void MacroAssembler::breakpoint_trap() {
328 trap(ST_RESERVED_FOR_USER_0);
329 }
330
331 // Write serialization page so VM thread can do a pseudo remote membar
332 // We use the current thread pointer to calculate a thread specific
333 // offset to write to within the page. This minimizes bus traffic
334 // due to cache line collision.
335 void MacroAssembler::serialize_memory(Register thread, Register tmp1, Register tmp2) {
336 srl(thread, os::get_serialize_page_shift_count(), tmp2);
337 if (Assembler::is_simm13(os::vm_page_size())) {
338 and3(tmp2, (os::vm_page_size() - sizeof(int)), tmp2);
339 }
340 else {
341 set((os::vm_page_size() - sizeof(int)), tmp1);
342 and3(tmp2, tmp1, tmp2);
343 }
344 set(os::get_memory_serialize_page(), tmp1);
345 st(G0, tmp1, tmp2);
346 }
347
348
349
350 void MacroAssembler::enter() {
351 Unimplemented();
352 }
353
354 void MacroAssembler::leave() {
355 Unimplemented();
356 }
357
358 // Calls to C land
359
360 #ifdef ASSERT
361 // a hook for debugging
362 static Thread* reinitialize_thread() {
363 return Thread::current();
364 }
365 #else
366 #define reinitialize_thread Thread::current
367 #endif
368
369 #ifdef ASSERT
370 address last_get_thread = NULL;
371 #endif
372
373 // call this when G2_thread is not known to be valid
374 void MacroAssembler::get_thread() {
375 save_frame(0); // to avoid clobbering O0
376 mov(G1, L0); // avoid clobbering G1
377 mov(G5_method, L1); // avoid clobbering G5
378 mov(G3, L2); // avoid clobbering G3 also
379 mov(G4, L5); // avoid clobbering G4
380 #ifdef ASSERT
381 AddressLiteral last_get_thread_addrlit(&last_get_thread);
382 set(last_get_thread_addrlit, L3);
383 rdpc(L4);
384 inc(L4, 3 * BytesPerInstWord); // skip rdpc + inc + st_ptr to point L4 at call st_ptr(L4, L3, 0);
385 #endif
386 call(CAST_FROM_FN_PTR(address, reinitialize_thread), relocInfo::runtime_call_type);
387 delayed()->nop();
388 mov(L0, G1);
389 mov(L1, G5_method);
390 mov(L2, G3);
391 mov(L5, G4);
392 restore(O0, 0, G2_thread);
393 }
394
395 static Thread* verify_thread_subroutine(Thread* gthread_value) {
396 Thread* correct_value = Thread::current();
397 guarantee(gthread_value == correct_value, "G2_thread value must be the thread");
398 return correct_value;
399 }
400
401 void MacroAssembler::verify_thread() {
402 if (VerifyThread) {
403 // NOTE: this chops off the heads of the 64-bit O registers.
404 // make sure G2_thread contains the right value
405 save_frame_and_mov(0, Lmethod, Lmethod); // to avoid clobbering O0 (and propagate Lmethod for -Xprof)
406 mov(G1, L1); // avoid clobbering G1
407 // G2 saved below
408 mov(G3, L3); // avoid clobbering G3
409 mov(G4, L4); // avoid clobbering G4
410 mov(G5_method, L5); // avoid clobbering G5_method
411 #if defined(COMPILER2) && !defined(_LP64)
412 // Save & restore possible 64-bit Long arguments in G-regs
413 srlx(G1,32,L0);
414 srlx(G4,32,L6);
415 #endif
416 call(CAST_FROM_FN_PTR(address,verify_thread_subroutine), relocInfo::runtime_call_type);
417 delayed()->mov(G2_thread, O0);
418
419 mov(L1, G1); // Restore G1
420 // G2 restored below
421 mov(L3, G3); // restore G3
422 mov(L4, G4); // restore G4
423 mov(L5, G5_method); // restore G5_method
424 #if defined(COMPILER2) && !defined(_LP64)
425 // Save & restore possible 64-bit Long arguments in G-regs
426 sllx(L0,32,G2); // Move old high G1 bits high in G2
427 srl(G1, 0,G1); // Clear current high G1 bits
428 or3 (G1,G2,G1); // Recover 64-bit G1
429 sllx(L6,32,G2); // Move old high G4 bits high in G2
430 srl(G4, 0,G4); // Clear current high G4 bits
431 or3 (G4,G2,G4); // Recover 64-bit G4
432 #endif
433 restore(O0, 0, G2_thread);
434 }
435 }
436
437
438 void MacroAssembler::save_thread(const Register thread_cache) {
439 verify_thread();
440 if (thread_cache->is_valid()) {
441 assert(thread_cache->is_local() || thread_cache->is_in(), "bad volatile");
442 mov(G2_thread, thread_cache);
443 }
444 if (VerifyThread) {
445 // smash G2_thread, as if the VM were about to anyway
446 set(0x67676767, G2_thread);
447 }
448 }
449
450
451 void MacroAssembler::restore_thread(const Register thread_cache) {
452 if (thread_cache->is_valid()) {
453 assert(thread_cache->is_local() || thread_cache->is_in(), "bad volatile");
454 mov(thread_cache, G2_thread);
455 verify_thread();
456 } else {
457 // do it the slow way
458 get_thread();
459 }
460 }
461
462
463 // %%% maybe get rid of [re]set_last_Java_frame
464 void MacroAssembler::set_last_Java_frame(Register last_java_sp, Register last_Java_pc) {
465 assert_not_delayed();
466 Address flags(G2_thread, JavaThread::frame_anchor_offset() +
467 JavaFrameAnchor::flags_offset());
468 Address pc_addr(G2_thread, JavaThread::last_Java_pc_offset());
469
470 // Always set last_Java_pc and flags first because once last_Java_sp is visible
471 // has_last_Java_frame is true and users will look at the rest of the fields.
472 // (Note: flags should always be zero before we get here so doesn't need to be set.)
473
474 #ifdef ASSERT
475 // Verify that flags was zeroed on return to Java
476 Label PcOk;
477 save_frame(0); // to avoid clobbering O0
478 ld_ptr(pc_addr, L0);
479 br_null_short(L0, Assembler::pt, PcOk);
480 STOP("last_Java_pc not zeroed before leaving Java");
481 bind(PcOk);
482
483 // Verify that flags was zeroed on return to Java
484 Label FlagsOk;
485 ld(flags, L0);
486 tst(L0);
487 br(Assembler::zero, false, Assembler::pt, FlagsOk);
488 delayed() -> restore();
489 STOP("flags not zeroed before leaving Java");
490 bind(FlagsOk);
491 #endif /* ASSERT */
492 //
493 // When returning from calling out from Java mode the frame anchor's last_Java_pc
494 // will always be set to NULL. It is set here so that if we are doing a call to
495 // native (not VM) that we capture the known pc and don't have to rely on the
496 // native call having a standard frame linkage where we can find the pc.
497
498 if (last_Java_pc->is_valid()) {
499 st_ptr(last_Java_pc, pc_addr);
500 }
501
502 #ifdef _LP64
503 #ifdef ASSERT
504 // Make sure that we have an odd stack
505 Label StackOk;
506 andcc(last_java_sp, 0x01, G0);
507 br(Assembler::notZero, false, Assembler::pt, StackOk);
508 delayed()->nop();
509 STOP("Stack Not Biased in set_last_Java_frame");
510 bind(StackOk);
511 #endif // ASSERT
512 assert( last_java_sp != G4_scratch, "bad register usage in set_last_Java_frame");
513 add( last_java_sp, STACK_BIAS, G4_scratch );
514 st_ptr(G4_scratch, G2_thread, JavaThread::last_Java_sp_offset());
515 #else
516 st_ptr(last_java_sp, G2_thread, JavaThread::last_Java_sp_offset());
517 #endif // _LP64
518 }
519
520 void MacroAssembler::reset_last_Java_frame(void) {
521 assert_not_delayed();
522
523 Address sp_addr(G2_thread, JavaThread::last_Java_sp_offset());
524 Address pc_addr(G2_thread, JavaThread::frame_anchor_offset() + JavaFrameAnchor::last_Java_pc_offset());
525 Address flags (G2_thread, JavaThread::frame_anchor_offset() + JavaFrameAnchor::flags_offset());
526
527 #ifdef ASSERT
528 // check that it WAS previously set
529 save_frame_and_mov(0, Lmethod, Lmethod); // Propagate Lmethod to helper frame for -Xprof
530 ld_ptr(sp_addr, L0);
531 tst(L0);
532 breakpoint_trap(Assembler::zero, Assembler::ptr_cc);
533 restore();
534 #endif // ASSERT
535
536 st_ptr(G0, sp_addr);
537 // Always return last_Java_pc to zero
538 st_ptr(G0, pc_addr);
539 // Always null flags after return to Java
540 st(G0, flags);
541 }
542
543
544 void MacroAssembler::call_VM_base(
545 Register oop_result,
546 Register thread_cache,
547 Register last_java_sp,
548 address entry_point,
549 int number_of_arguments,
550 bool check_exceptions)
551 {
552 assert_not_delayed();
553
554 // determine last_java_sp register
555 if (!last_java_sp->is_valid()) {
556 last_java_sp = SP;
557 }
558 // debugging support
559 assert(number_of_arguments >= 0 , "cannot have negative number of arguments");
560
561 // 64-bit last_java_sp is biased!
562 set_last_Java_frame(last_java_sp, noreg);
563 if (VerifyThread) mov(G2_thread, O0); // about to be smashed; pass early
564 save_thread(thread_cache);
565 // do the call
566 call(entry_point, relocInfo::runtime_call_type);
567 if (!VerifyThread)
568 delayed()->mov(G2_thread, O0); // pass thread as first argument
569 else
570 delayed()->nop(); // (thread already passed)
571 restore_thread(thread_cache);
572 reset_last_Java_frame();
573
574 // check for pending exceptions. use Gtemp as scratch register.
575 if (check_exceptions) {
576 check_and_forward_exception(Gtemp);
577 }
578
579 #ifdef ASSERT
580 set(badHeapWordVal, G3);
581 set(badHeapWordVal, G4);
582 set(badHeapWordVal, G5);
583 #endif
584
585 // get oop result if there is one and reset the value in the thread
586 if (oop_result->is_valid()) {
587 get_vm_result(oop_result);
588 }
589 }
590
591 void MacroAssembler::check_and_forward_exception(Register scratch_reg)
592 {
593 Label L;
594
595 check_and_handle_popframe(scratch_reg);
596 check_and_handle_earlyret(scratch_reg);
597
598 Address exception_addr(G2_thread, Thread::pending_exception_offset());
599 ld_ptr(exception_addr, scratch_reg);
600 br_null_short(scratch_reg, pt, L);
601 // we use O7 linkage so that forward_exception_entry has the issuing PC
602 call(StubRoutines::forward_exception_entry(), relocInfo::runtime_call_type);
603 delayed()->nop();
604 bind(L);
605 }
606
607
608 void MacroAssembler::check_and_handle_popframe(Register scratch_reg) {
609 }
610
611
612 void MacroAssembler::check_and_handle_earlyret(Register scratch_reg) {
613 }
614
615
616 void MacroAssembler::call_VM(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions) {
617 call_VM_base(oop_result, noreg, noreg, entry_point, number_of_arguments, check_exceptions);
618 }
619
620
621 void MacroAssembler::call_VM(Register oop_result, address entry_point, Register arg_1, bool check_exceptions) {
622 // O0 is reserved for the thread
623 mov(arg_1, O1);
624 call_VM(oop_result, entry_point, 1, check_exceptions);
625 }
626
627
628 void MacroAssembler::call_VM(Register oop_result, address entry_point, Register arg_1, Register arg_2, bool check_exceptions) {
629 // O0 is reserved for the thread
630 mov(arg_1, O1);
631 mov(arg_2, O2); assert(arg_2 != O1, "smashed argument");
632 call_VM(oop_result, entry_point, 2, check_exceptions);
633 }
634
635
636 void MacroAssembler::call_VM(Register oop_result, address entry_point, Register arg_1, Register arg_2, Register arg_3, bool check_exceptions) {
637 // O0 is reserved for the thread
638 mov(arg_1, O1);
639 mov(arg_2, O2); assert(arg_2 != O1, "smashed argument");
640 mov(arg_3, O3); assert(arg_3 != O1 && arg_3 != O2, "smashed argument");
641 call_VM(oop_result, entry_point, 3, check_exceptions);
642 }
643
644
645
646 // Note: The following call_VM overloadings are useful when a "save"
647 // has already been performed by a stub, and the last Java frame is
648 // the previous one. In that case, last_java_sp must be passed as FP
649 // instead of SP.
650
651
652 void MacroAssembler::call_VM(Register oop_result, Register last_java_sp, address entry_point, int number_of_arguments, bool check_exceptions) {
653 call_VM_base(oop_result, noreg, last_java_sp, entry_point, number_of_arguments, check_exceptions);
654 }
655
656
657 void MacroAssembler::call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, bool check_exceptions) {
658 // O0 is reserved for the thread
659 mov(arg_1, O1);
660 call_VM(oop_result, last_java_sp, entry_point, 1, check_exceptions);
661 }
662
663
664 void MacroAssembler::call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, bool check_exceptions) {
665 // O0 is reserved for the thread
666 mov(arg_1, O1);
667 mov(arg_2, O2); assert(arg_2 != O1, "smashed argument");
668 call_VM(oop_result, last_java_sp, entry_point, 2, check_exceptions);
669 }
670
671
672 void MacroAssembler::call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, bool check_exceptions) {
673 // O0 is reserved for the thread
674 mov(arg_1, O1);
675 mov(arg_2, O2); assert(arg_2 != O1, "smashed argument");
676 mov(arg_3, O3); assert(arg_3 != O1 && arg_3 != O2, "smashed argument");
677 call_VM(oop_result, last_java_sp, entry_point, 3, check_exceptions);
678 }
679
680
681
682 void MacroAssembler::call_VM_leaf_base(Register thread_cache, address entry_point, int number_of_arguments) {
683 assert_not_delayed();
684 save_thread(thread_cache);
685 // do the call
686 call(entry_point, relocInfo::runtime_call_type);
687 delayed()->nop();
688 restore_thread(thread_cache);
689 #ifdef ASSERT
690 set(badHeapWordVal, G3);
691 set(badHeapWordVal, G4);
692 set(badHeapWordVal, G5);
693 #endif
694 }
695
696
697 void MacroAssembler::call_VM_leaf(Register thread_cache, address entry_point, int number_of_arguments) {
698 call_VM_leaf_base(thread_cache, entry_point, number_of_arguments);
699 }
700
701
702 void MacroAssembler::call_VM_leaf(Register thread_cache, address entry_point, Register arg_1) {
703 mov(arg_1, O0);
704 call_VM_leaf(thread_cache, entry_point, 1);
705 }
706
707
708 void MacroAssembler::call_VM_leaf(Register thread_cache, address entry_point, Register arg_1, Register arg_2) {
709 mov(arg_1, O0);
710 mov(arg_2, O1); assert(arg_2 != O0, "smashed argument");
711 call_VM_leaf(thread_cache, entry_point, 2);
712 }
713
714
715 void MacroAssembler::call_VM_leaf(Register thread_cache, address entry_point, Register arg_1, Register arg_2, Register arg_3) {
716 mov(arg_1, O0);
717 mov(arg_2, O1); assert(arg_2 != O0, "smashed argument");
718 mov(arg_3, O2); assert(arg_3 != O0 && arg_3 != O1, "smashed argument");
719 call_VM_leaf(thread_cache, entry_point, 3);
720 }
721
722
723 void MacroAssembler::get_vm_result(Register oop_result) {
724 verify_thread();
725 Address vm_result_addr(G2_thread, JavaThread::vm_result_offset());
726 ld_ptr( vm_result_addr, oop_result);
727 st_ptr(G0, vm_result_addr);
728 verify_oop(oop_result);
729 }
730
731
732 void MacroAssembler::get_vm_result_2(Register metadata_result) {
733 verify_thread();
734 Address vm_result_addr_2(G2_thread, JavaThread::vm_result_2_offset());
735 ld_ptr(vm_result_addr_2, metadata_result);
736 st_ptr(G0, vm_result_addr_2);
737 }
738
739
740 // We require that C code which does not return a value in vm_result will
741 // leave it undisturbed.
742 void MacroAssembler::set_vm_result(Register oop_result) {
743 verify_thread();
744 Address vm_result_addr(G2_thread, JavaThread::vm_result_offset());
745 verify_oop(oop_result);
746
747 # ifdef ASSERT
748 // Check that we are not overwriting any other oop.
749 save_frame_and_mov(0, Lmethod, Lmethod); // Propagate Lmethod for -Xprof
750 ld_ptr(vm_result_addr, L0);
751 tst(L0);
752 restore();
753 breakpoint_trap(notZero, Assembler::ptr_cc);
754 // }
755 # endif
756
757 st_ptr(oop_result, vm_result_addr);
758 }
759
760
761 void MacroAssembler::ic_call(address entry, bool emit_delay) {
762 RelocationHolder rspec = virtual_call_Relocation::spec(pc());
763 patchable_set((intptr_t)Universe::non_oop_word(), G5_inline_cache_reg);
764 relocate(rspec);
765 call(entry, relocInfo::none);
766 if (emit_delay) {
767 delayed()->nop();
768 }
769 }
770
771
772 void MacroAssembler::card_table_write(jbyte* byte_map_base,
773 Register tmp, Register obj) {
774 #ifdef _LP64
775 srlx(obj, CardTableModRefBS::card_shift, obj);
776 #else
777 srl(obj, CardTableModRefBS::card_shift, obj);
778 #endif
779 assert(tmp != obj, "need separate temp reg");
780 set((address) byte_map_base, tmp);
781 stb(G0, tmp, obj);
782 }
783
784
785 void MacroAssembler::internal_sethi(const AddressLiteral& addrlit, Register d, bool ForceRelocatable) {
786 address save_pc;
787 int shiftcnt;
788 #ifdef _LP64
789 # ifdef CHECK_DELAY
790 assert_not_delayed((char*) "cannot put two instructions in delay slot");
791 # endif
792 v9_dep();
793 save_pc = pc();
794
795 int msb32 = (int) (addrlit.value() >> 32);
796 int lsb32 = (int) (addrlit.value());
797
798 if (msb32 == 0 && lsb32 >= 0) {
799 Assembler::sethi(lsb32, d, addrlit.rspec());
800 }
801 else if (msb32 == -1) {
802 Assembler::sethi(~lsb32, d, addrlit.rspec());
803 xor3(d, ~low10(~0), d);
804 }
805 else {
806 Assembler::sethi(msb32, d, addrlit.rspec()); // msb 22-bits
807 if (msb32 & 0x3ff) // Any bits?
808 or3(d, msb32 & 0x3ff, d); // msb 32-bits are now in lsb 32
809 if (lsb32 & 0xFFFFFC00) { // done?
810 if ((lsb32 >> 20) & 0xfff) { // Any bits set?
811 sllx(d, 12, d); // Make room for next 12 bits
812 or3(d, (lsb32 >> 20) & 0xfff, d); // Or in next 12
813 shiftcnt = 0; // We already shifted
814 }
815 else
816 shiftcnt = 12;
817 if ((lsb32 >> 10) & 0x3ff) {
818 sllx(d, shiftcnt + 10, d); // Make room for last 10 bits
819 or3(d, (lsb32 >> 10) & 0x3ff, d); // Or in next 10
820 shiftcnt = 0;
821 }
822 else
823 shiftcnt = 10;
824 sllx(d, shiftcnt + 10, d); // Shift leaving disp field 0'd
825 }
826 else
827 sllx(d, 32, d);
828 }
829 // Pad out the instruction sequence so it can be patched later.
830 if (ForceRelocatable || (addrlit.rtype() != relocInfo::none &&
831 addrlit.rtype() != relocInfo::runtime_call_type)) {
832 while (pc() < (save_pc + (7 * BytesPerInstWord)))
833 nop();
834 }
835 #else
836 Assembler::sethi(addrlit.value(), d, addrlit.rspec());
837 #endif
838 }
839
840
841 void MacroAssembler::sethi(const AddressLiteral& addrlit, Register d) {
842 internal_sethi(addrlit, d, false);
843 }
844
845
846 void MacroAssembler::patchable_sethi(const AddressLiteral& addrlit, Register d) {
847 internal_sethi(addrlit, d, true);
848 }
849
850
851 int MacroAssembler::insts_for_sethi(address a, bool worst_case) {
852 #ifdef _LP64
853 if (worst_case) return 7;
854 intptr_t iaddr = (intptr_t) a;
855 int msb32 = (int) (iaddr >> 32);
856 int lsb32 = (int) (iaddr);
857 int count;
858 if (msb32 == 0 && lsb32 >= 0)
859 count = 1;
860 else if (msb32 == -1)
861 count = 2;
862 else {
863 count = 2;
864 if (msb32 & 0x3ff)
865 count++;
866 if (lsb32 & 0xFFFFFC00 ) {
867 if ((lsb32 >> 20) & 0xfff) count += 2;
868 if ((lsb32 >> 10) & 0x3ff) count += 2;
869 }
870 }
871 return count;
872 #else
873 return 1;
874 #endif
875 }
876
877 int MacroAssembler::worst_case_insts_for_set() {
878 return insts_for_sethi(NULL, true) + 1;
879 }
880
881
882 // Keep in sync with MacroAssembler::insts_for_internal_set
883 void MacroAssembler::internal_set(const AddressLiteral& addrlit, Register d, bool ForceRelocatable) {
884 intptr_t value = addrlit.value();
885
886 if (!ForceRelocatable && addrlit.rspec().type() == relocInfo::none) {
887 // can optimize
888 if (-4096 <= value && value <= 4095) {
889 or3(G0, value, d); // setsw (this leaves upper 32 bits sign-extended)
890 return;
891 }
892 if (inv_hi22(hi22(value)) == value) {
893 sethi(addrlit, d);
894 return;
895 }
896 }
897 assert_not_delayed((char*) "cannot put two instructions in delay slot");
898 internal_sethi(addrlit, d, ForceRelocatable);
899 if (ForceRelocatable || addrlit.rspec().type() != relocInfo::none || addrlit.low10() != 0) {
900 add(d, addrlit.low10(), d, addrlit.rspec());
901 }
902 }
903
904 // Keep in sync with MacroAssembler::internal_set
905 int MacroAssembler::insts_for_internal_set(intptr_t value) {
906 // can optimize
907 if (-4096 <= value && value <= 4095) {
908 return 1;
909 }
910 if (inv_hi22(hi22(value)) == value) {
911 return insts_for_sethi((address) value);
912 }
913 int count = insts_for_sethi((address) value);
914 AddressLiteral al(value);
915 if (al.low10() != 0) {
916 count++;
917 }
918 return count;
919 }
920
921 void MacroAssembler::set(const AddressLiteral& al, Register d) {
922 internal_set(al, d, false);
923 }
924
925 void MacroAssembler::set(intptr_t value, Register d) {
926 AddressLiteral al(value);
927 internal_set(al, d, false);
928 }
929
930 void MacroAssembler::set(address addr, Register d, RelocationHolder const& rspec) {
931 AddressLiteral al(addr, rspec);
932 internal_set(al, d, false);
933 }
934
935 void MacroAssembler::patchable_set(const AddressLiteral& al, Register d) {
936 internal_set(al, d, true);
937 }
938
939 void MacroAssembler::patchable_set(intptr_t value, Register d) {
940 AddressLiteral al(value);
941 internal_set(al, d, true);
942 }
943
944
945 void MacroAssembler::set64(jlong value, Register d, Register tmp) {
946 assert_not_delayed();
947 v9_dep();
948
949 int hi = (int)(value >> 32);
950 int lo = (int)(value & ~0);
951 int bits_33to2 = (int)((value >> 2) & ~0);
952 // (Matcher::isSimpleConstant64 knows about the following optimizations.)
953 if (Assembler::is_simm13(lo) && value == lo) {
954 or3(G0, lo, d);
955 } else if (hi == 0) {
956 Assembler::sethi(lo, d); // hardware version zero-extends to upper 32
957 if (low10(lo) != 0)
958 or3(d, low10(lo), d);
959 }
960 else if ((hi >> 2) == 0) {
961 Assembler::sethi(bits_33to2, d); // hardware version zero-extends to upper 32
962 sllx(d, 2, d);
963 if (low12(lo) != 0)
964 or3(d, low12(lo), d);
965 }
966 else if (hi == -1) {
967 Assembler::sethi(~lo, d); // hardware version zero-extends to upper 32
968 xor3(d, low10(lo) ^ ~low10(~0), d);
969 }
970 else if (lo == 0) {
971 if (Assembler::is_simm13(hi)) {
972 or3(G0, hi, d);
973 } else {
974 Assembler::sethi(hi, d); // hardware version zero-extends to upper 32
975 if (low10(hi) != 0)
976 or3(d, low10(hi), d);
977 }
978 sllx(d, 32, d);
979 }
980 else {
981 Assembler::sethi(hi, tmp);
982 Assembler::sethi(lo, d); // macro assembler version sign-extends
983 if (low10(hi) != 0)
984 or3 (tmp, low10(hi), tmp);
985 if (low10(lo) != 0)
986 or3 ( d, low10(lo), d);
987 sllx(tmp, 32, tmp);
988 or3 (d, tmp, d);
989 }
990 }
991
992 int MacroAssembler::insts_for_set64(jlong value) {
993 v9_dep();
994
995 int hi = (int) (value >> 32);
996 int lo = (int) (value & ~0);
997 int count = 0;
998
999 // (Matcher::isSimpleConstant64 knows about the following optimizations.)
1000 if (Assembler::is_simm13(lo) && value == lo) {
1001 count++;
1002 } else if (hi == 0) {
1003 count++;
1004 if (low10(lo) != 0)
1005 count++;
1006 }
1007 else if (hi == -1) {
1008 count += 2;
1009 }
1010 else if (lo == 0) {
1011 if (Assembler::is_simm13(hi)) {
1012 count++;
1013 } else {
1014 count++;
1015 if (low10(hi) != 0)
1016 count++;
1017 }
1018 count++;
1019 }
1020 else {
1021 count += 2;
1022 if (low10(hi) != 0)
1023 count++;
1024 if (low10(lo) != 0)
1025 count++;
1026 count += 2;
1027 }
1028 return count;
1029 }
1030
1031 // compute size in bytes of sparc frame, given
1032 // number of extraWords
1033 int MacroAssembler::total_frame_size_in_bytes(int extraWords) {
1034
1035 int nWords = frame::memory_parameter_word_sp_offset;
1036
1037 nWords += extraWords;
1038
1039 if (nWords & 1) ++nWords; // round up to double-word
1040
1041 return nWords * BytesPerWord;
1042 }
1043
1044
1045 // save_frame: given number of "extra" words in frame,
1046 // issue approp. save instruction (p 200, v8 manual)
1047
1048 void MacroAssembler::save_frame(int extraWords) {
1049 int delta = -total_frame_size_in_bytes(extraWords);
1050 if (is_simm13(delta)) {
1051 save(SP, delta, SP);
1052 } else {
1053 set(delta, G3_scratch);
1054 save(SP, G3_scratch, SP);
1055 }
1056 }
1057
1058
1059 void MacroAssembler::save_frame_c1(int size_in_bytes) {
1060 if (is_simm13(-size_in_bytes)) {
1061 save(SP, -size_in_bytes, SP);
1062 } else {
1063 set(-size_in_bytes, G3_scratch);
1064 save(SP, G3_scratch, SP);
1065 }
1066 }
1067
1068
1069 void MacroAssembler::save_frame_and_mov(int extraWords,
1070 Register s1, Register d1,
1071 Register s2, Register d2) {
1072 assert_not_delayed();
1073
1074 // The trick here is to use precisely the same memory word
1075 // that trap handlers also use to save the register.
1076 // This word cannot be used for any other purpose, but
1077 // it works fine to save the register's value, whether or not
1078 // an interrupt flushes register windows at any given moment!
1079 Address s1_addr;
1080 if (s1->is_valid() && (s1->is_in() || s1->is_local())) {
1081 s1_addr = s1->address_in_saved_window();
1082 st_ptr(s1, s1_addr);
1083 }
1084
1085 Address s2_addr;
1086 if (s2->is_valid() && (s2->is_in() || s2->is_local())) {
1087 s2_addr = s2->address_in_saved_window();
1088 st_ptr(s2, s2_addr);
1089 }
1090
1091 save_frame(extraWords);
1092
1093 if (s1_addr.base() == SP) {
1094 ld_ptr(s1_addr.after_save(), d1);
1095 } else if (s1->is_valid()) {
1096 mov(s1->after_save(), d1);
1097 }
1098
1099 if (s2_addr.base() == SP) {
1100 ld_ptr(s2_addr.after_save(), d2);
1101 } else if (s2->is_valid()) {
1102 mov(s2->after_save(), d2);
1103 }
1104 }
1105
1106
1107 AddressLiteral MacroAssembler::allocate_metadata_address(Metadata* obj) {
1108 assert(oop_recorder() != NULL, "this assembler needs a Recorder");
1109 int index = oop_recorder()->allocate_metadata_index(obj);
1110 RelocationHolder rspec = metadata_Relocation::spec(index);
1111 return AddressLiteral((address)obj, rspec);
1112 }
1113
1114 AddressLiteral MacroAssembler::constant_metadata_address(Metadata* obj) {
1115 assert(oop_recorder() != NULL, "this assembler needs a Recorder");
1116 int index = oop_recorder()->find_index(obj);
1117 RelocationHolder rspec = metadata_Relocation::spec(index);
1118 return AddressLiteral((address)obj, rspec);
1119 }
1120
1121
1122 AddressLiteral MacroAssembler::constant_oop_address(jobject obj) {
1123 assert(oop_recorder() != NULL, "this assembler needs an OopRecorder");
1124 assert(Universe::heap()->is_in_reserved(JNIHandles::resolve(obj)), "not an oop");
1125 int oop_index = oop_recorder()->find_index(obj);
1126 return AddressLiteral(obj, oop_Relocation::spec(oop_index));
1127 }
1128
1129 void MacroAssembler::set_narrow_oop(jobject obj, Register d) {
1130 assert(oop_recorder() != NULL, "this assembler needs an OopRecorder");
1131 int oop_index = oop_recorder()->find_index(obj);
1132 RelocationHolder rspec = oop_Relocation::spec(oop_index);
1133
1134 assert_not_delayed();
1135 // Relocation with special format (see relocInfo_sparc.hpp).
1136 relocate(rspec, 1);
1137 // Assembler::sethi(0x3fffff, d);
1138 emit_int32( op(branch_op) | rd(d) | op2(sethi_op2) | hi22(0x3fffff) );
1139 // Don't add relocation for 'add'. Do patching during 'sethi' processing.
1140 add(d, 0x3ff, d);
1141
1142 }
1143
1144 void MacroAssembler::set_narrow_klass(Klass* k, Register d) {
1145 assert(oop_recorder() != NULL, "this assembler needs an OopRecorder");
1146 int klass_index = oop_recorder()->find_index(k);
1147 RelocationHolder rspec = metadata_Relocation::spec(klass_index);
1148 narrowOop encoded_k = Klass::encode_klass(k);
1149
1150 assert_not_delayed();
1151 // Relocation with special format (see relocInfo_sparc.hpp).
1152 relocate(rspec, 1);
1153 // Assembler::sethi(encoded_k, d);
1154 emit_int32( op(branch_op) | rd(d) | op2(sethi_op2) | hi22(encoded_k) );
1155 // Don't add relocation for 'add'. Do patching during 'sethi' processing.
1156 add(d, low10(encoded_k), d);
1157
1158 }
1159
1160 void MacroAssembler::align(int modulus) {
1161 while (offset() % modulus != 0) nop();
1162 }
1163
1164 void RegistersForDebugging::print(outputStream* s) {
1165 FlagSetting fs(Debugging, true);
1166 int j;
1167 for (j = 0; j < 8; ++j) {
1168 if (j != 6) { s->print("i%d = ", j); os::print_location(s, i[j]); }
1169 else { s->print( "fp = " ); os::print_location(s, i[j]); }
1170 }
1171 s->cr();
1172
1173 for (j = 0; j < 8; ++j) {
1174 s->print("l%d = ", j); os::print_location(s, l[j]);
1175 }
1176 s->cr();
1177
1178 for (j = 0; j < 8; ++j) {
1179 if (j != 6) { s->print("o%d = ", j); os::print_location(s, o[j]); }
1180 else { s->print( "sp = " ); os::print_location(s, o[j]); }
1181 }
1182 s->cr();
1183
1184 for (j = 0; j < 8; ++j) {
1185 s->print("g%d = ", j); os::print_location(s, g[j]);
1186 }
1187 s->cr();
1188
1189 // print out floats with compression
1190 for (j = 0; j < 32; ) {
1191 jfloat val = f[j];
1192 int last = j;
1193 for ( ; last+1 < 32; ++last ) {
1194 char b1[1024], b2[1024];
1195 sprintf(b1, "%f", val);
1196 sprintf(b2, "%f", f[last+1]);
1197 if (strcmp(b1, b2))
1198 break;
1199 }
1200 s->print("f%d", j);
1201 if ( j != last ) s->print(" - f%d", last);
1202 s->print(" = %f", val);
1203 s->fill_to(25);
1204 s->print_cr(" (0x%x)", *(int*)&val);
1205 j = last + 1;
1206 }
1207 s->cr();
1208
1209 // and doubles (evens only)
1210 for (j = 0; j < 32; ) {
1211 jdouble val = d[j];
1212 int last = j;
1213 for ( ; last+1 < 32; ++last ) {
1214 char b1[1024], b2[1024];
1215 sprintf(b1, "%f", val);
1216 sprintf(b2, "%f", d[last+1]);
1217 if (strcmp(b1, b2))
1218 break;
1219 }
1220 s->print("d%d", 2 * j);
1221 if ( j != last ) s->print(" - d%d", last);
1222 s->print(" = %f", val);
1223 s->fill_to(30);
1224 s->print("(0x%x)", *(int*)&val);
1225 s->fill_to(42);
1226 s->print_cr("(0x%x)", *(1 + (int*)&val));
1227 j = last + 1;
1228 }
1229 s->cr();
1230 }
1231
1232 void RegistersForDebugging::save_registers(MacroAssembler* a) {
1233 a->sub(FP, round_to(sizeof(RegistersForDebugging), sizeof(jdouble)) - STACK_BIAS, O0);
1234 a->flushw();
1235 int i;
1236 for (i = 0; i < 8; ++i) {
1237 a->ld_ptr(as_iRegister(i)->address_in_saved_window().after_save(), L1); a->st_ptr( L1, O0, i_offset(i));
1238 a->ld_ptr(as_lRegister(i)->address_in_saved_window().after_save(), L1); a->st_ptr( L1, O0, l_offset(i));
1239 a->st_ptr(as_oRegister(i)->after_save(), O0, o_offset(i));
1240 a->st_ptr(as_gRegister(i)->after_save(), O0, g_offset(i));
1241 }
1242 for (i = 0; i < 32; ++i) {
1243 a->stf(FloatRegisterImpl::S, as_FloatRegister(i), O0, f_offset(i));
1244 }
1245 for (i = 0; i < 64; i += 2) {
1246 a->stf(FloatRegisterImpl::D, as_FloatRegister(i), O0, d_offset(i));
1247 }
1248 }
1249
1250 void RegistersForDebugging::restore_registers(MacroAssembler* a, Register r) {
1251 for (int i = 1; i < 8; ++i) {
1252 a->ld_ptr(r, g_offset(i), as_gRegister(i));
1253 }
1254 for (int j = 0; j < 32; ++j) {
1255 a->ldf(FloatRegisterImpl::S, O0, f_offset(j), as_FloatRegister(j));
1256 }
1257 for (int k = 0; k < 64; k += 2) {
1258 a->ldf(FloatRegisterImpl::D, O0, d_offset(k), as_FloatRegister(k));
1259 }
1260 }
1261
1262
1263 // pushes double TOS element of FPU stack on CPU stack; pops from FPU stack
1264 void MacroAssembler::push_fTOS() {
1265 // %%%%%% need to implement this
1266 }
1267
1268 // pops double TOS element from CPU stack and pushes on FPU stack
1269 void MacroAssembler::pop_fTOS() {
1270 // %%%%%% need to implement this
1271 }
1272
1273 void MacroAssembler::empty_FPU_stack() {
1274 // %%%%%% need to implement this
1275 }
1276
1277 void MacroAssembler::_verify_oop(Register reg, const char* msg, const char * file, int line) {
1278 // plausibility check for oops
1279 if (!VerifyOops) return;
1280
1281 if (reg == G0) return; // always NULL, which is always an oop
1282
1283 BLOCK_COMMENT("verify_oop {");
1284 char buffer[64];
1285 #ifdef COMPILER1
1286 if (CommentedAssembly) {
1287 snprintf(buffer, sizeof(buffer), "verify_oop at %d", offset());
1288 block_comment(buffer);
1289 }
1290 #endif
1291
1292 const char* real_msg = NULL;
1293 {
1294 ResourceMark rm;
1295 stringStream ss;
1296 ss.print("%s at offset %d (%s:%d)", msg, offset(), file, line);
1297 real_msg = code_string(ss.as_string());
1298 }
1299
1300 // Call indirectly to solve generation ordering problem
1301 AddressLiteral a(StubRoutines::verify_oop_subroutine_entry_address());
1302
1303 // Make some space on stack above the current register window.
1304 // Enough to hold 8 64-bit registers.
1305 add(SP,-8*8,SP);
1306
1307 // Save some 64-bit registers; a normal 'save' chops the heads off
1308 // of 64-bit longs in the 32-bit build.
1309 stx(O0,SP,frame::register_save_words*wordSize+STACK_BIAS+0*8);
1310 stx(O1,SP,frame::register_save_words*wordSize+STACK_BIAS+1*8);
1311 mov(reg,O0); // Move arg into O0; arg might be in O7 which is about to be crushed
1312 stx(O7,SP,frame::register_save_words*wordSize+STACK_BIAS+7*8);
1313
1314 // Size of set() should stay the same
1315 patchable_set((intptr_t)real_msg, O1);
1316 // Load address to call to into O7
1317 load_ptr_contents(a, O7);
1318 // Register call to verify_oop_subroutine
1319 callr(O7, G0);
1320 delayed()->nop();
1321 // recover frame size
1322 add(SP, 8*8,SP);
1323 BLOCK_COMMENT("} verify_oop");
1324 }
1325
1326 void MacroAssembler::_verify_oop_addr(Address addr, const char* msg, const char * file, int line) {
1327 // plausibility check for oops
1328 if (!VerifyOops) return;
1329
1330 const char* real_msg = NULL;
1331 {
1332 ResourceMark rm;
1333 stringStream ss;
1334 ss.print("%s at SP+%d (%s:%d)", msg, addr.disp(), file, line);
1335 real_msg = code_string(ss.as_string());
1336 }
1337
1338 // Call indirectly to solve generation ordering problem
1339 AddressLiteral a(StubRoutines::verify_oop_subroutine_entry_address());
1340
1341 // Make some space on stack above the current register window.
1342 // Enough to hold 8 64-bit registers.
1343 add(SP,-8*8,SP);
1344
1345 // Save some 64-bit registers; a normal 'save' chops the heads off
1346 // of 64-bit longs in the 32-bit build.
1347 stx(O0,SP,frame::register_save_words*wordSize+STACK_BIAS+0*8);
1348 stx(O1,SP,frame::register_save_words*wordSize+STACK_BIAS+1*8);
1349 ld_ptr(addr.base(), addr.disp() + 8*8, O0); // Load arg into O0; arg might be in O7 which is about to be crushed
1350 stx(O7,SP,frame::register_save_words*wordSize+STACK_BIAS+7*8);
1351
1352 // Size of set() should stay the same
1353 patchable_set((intptr_t)real_msg, O1);
1354 // Load address to call to into O7
1355 load_ptr_contents(a, O7);
1356 // Register call to verify_oop_subroutine
1357 callr(O7, G0);
1358 delayed()->nop();
1359 // recover frame size
1360 add(SP, 8*8,SP);
1361 }
1362
1363 // side-door communication with signalHandler in os_solaris.cpp
1364 address MacroAssembler::_verify_oop_implicit_branch[3] = { NULL };
1365
1366 // This macro is expanded just once; it creates shared code. Contract:
1367 // receives an oop in O0. Must restore O0 & O7 from TLS. Must not smash ANY
1368 // registers, including flags. May not use a register 'save', as this blows
1369 // the high bits of the O-regs if they contain Long values. Acts as a 'leaf'
1370 // call.
1371 void MacroAssembler::verify_oop_subroutine() {
1372 // Leaf call; no frame.
1373 Label succeed, fail, null_or_fail;
1374
1375 // O0 and O7 were saved already (O0 in O0's TLS home, O7 in O5's TLS home).
1376 // O0 is now the oop to be checked. O7 is the return address.
1377 Register O0_obj = O0;
1378
1379 // Save some more registers for temps.
1380 stx(O2,SP,frame::register_save_words*wordSize+STACK_BIAS+2*8);
1381 stx(O3,SP,frame::register_save_words*wordSize+STACK_BIAS+3*8);
1382 stx(O4,SP,frame::register_save_words*wordSize+STACK_BIAS+4*8);
1383 stx(O5,SP,frame::register_save_words*wordSize+STACK_BIAS+5*8);
1384
1385 // Save flags
1386 Register O5_save_flags = O5;
1387 rdccr( O5_save_flags );
1388
1389 { // count number of verifies
1390 Register O2_adr = O2;
1391 Register O3_accum = O3;
1392 inc_counter(StubRoutines::verify_oop_count_addr(), O2_adr, O3_accum);
1393 }
1394
1395 Register O2_mask = O2;
1396 Register O3_bits = O3;
1397 Register O4_temp = O4;
1398
1399 // mark lower end of faulting range
1400 assert(_verify_oop_implicit_branch[0] == NULL, "set once");
1401 _verify_oop_implicit_branch[0] = pc();
1402
1403 // We can't check the mark oop because it could be in the process of
1404 // locking or unlocking while this is running.
1405 set(Universe::verify_oop_mask (), O2_mask);
1406 set(Universe::verify_oop_bits (), O3_bits);
1407
1408 // assert((obj & oop_mask) == oop_bits);
1409 and3(O0_obj, O2_mask, O4_temp);
1410 cmp_and_brx_short(O4_temp, O3_bits, notEqual, pn, null_or_fail);
1411
1412 if ((NULL_WORD & Universe::verify_oop_mask()) == Universe::verify_oop_bits()) {
1413 // the null_or_fail case is useless; must test for null separately
1414 br_null_short(O0_obj, pn, succeed);
1415 }
1416
1417 // Check the Klass* of this object for being in the right area of memory.
1418 // Cannot do the load in the delay above slot in case O0 is null
1419 load_klass(O0_obj, O0_obj);
1420 // assert((klass != NULL)
1421 br_null_short(O0_obj, pn, fail);
1422
1423 wrccr( O5_save_flags ); // Restore CCR's
1424
1425 // mark upper end of faulting range
1426 _verify_oop_implicit_branch[1] = pc();
1427
1428 //-----------------------
1429 // all tests pass
1430 bind(succeed);
1431
1432 // Restore prior 64-bit registers
1433 ldx(SP,frame::register_save_words*wordSize+STACK_BIAS+0*8,O0);
1434 ldx(SP,frame::register_save_words*wordSize+STACK_BIAS+1*8,O1);
1435 ldx(SP,frame::register_save_words*wordSize+STACK_BIAS+2*8,O2);
1436 ldx(SP,frame::register_save_words*wordSize+STACK_BIAS+3*8,O3);
1437 ldx(SP,frame::register_save_words*wordSize+STACK_BIAS+4*8,O4);
1438 ldx(SP,frame::register_save_words*wordSize+STACK_BIAS+5*8,O5);
1439
1440 retl(); // Leaf return; restore prior O7 in delay slot
1441 delayed()->ldx(SP,frame::register_save_words*wordSize+STACK_BIAS+7*8,O7);
1442
1443 //-----------------------
1444 bind(null_or_fail); // nulls are less common but OK
1445 br_null(O0_obj, false, pt, succeed);
1446 delayed()->wrccr( O5_save_flags ); // Restore CCR's
1447
1448 //-----------------------
1449 // report failure:
1450 bind(fail);
1451 _verify_oop_implicit_branch[2] = pc();
1452
1453 wrccr( O5_save_flags ); // Restore CCR's
1454
1455 save_frame(::round_to(sizeof(RegistersForDebugging) / BytesPerWord, 2));
1456
1457 // stop_subroutine expects message pointer in I1.
1458 mov(I1, O1);
1459
1460 // Restore prior 64-bit registers
1461 ldx(FP,frame::register_save_words*wordSize+STACK_BIAS+0*8,I0);
1462 ldx(FP,frame::register_save_words*wordSize+STACK_BIAS+1*8,I1);
1463 ldx(FP,frame::register_save_words*wordSize+STACK_BIAS+2*8,I2);
1464 ldx(FP,frame::register_save_words*wordSize+STACK_BIAS+3*8,I3);
1465 ldx(FP,frame::register_save_words*wordSize+STACK_BIAS+4*8,I4);
1466 ldx(FP,frame::register_save_words*wordSize+STACK_BIAS+5*8,I5);
1467
1468 // factor long stop-sequence into subroutine to save space
1469 assert(StubRoutines::Sparc::stop_subroutine_entry_address(), "hasn't been generated yet");
1470
1471 // call indirectly to solve generation ordering problem
1472 AddressLiteral al(StubRoutines::Sparc::stop_subroutine_entry_address());
1473 load_ptr_contents(al, O5);
1474 jmpl(O5, 0, O7);
1475 delayed()->nop();
1476 }
1477
1478
1479 void MacroAssembler::stop(const char* msg) {
1480 // save frame first to get O7 for return address
1481 // add one word to size in case struct is odd number of words long
1482 // It must be doubleword-aligned for storing doubles into it.
1483
1484 save_frame(::round_to(sizeof(RegistersForDebugging) / BytesPerWord, 2));
1485
1486 // stop_subroutine expects message pointer in I1.
1487 // Size of set() should stay the same
1488 patchable_set((intptr_t)msg, O1);
1489
1490 // factor long stop-sequence into subroutine to save space
1491 assert(StubRoutines::Sparc::stop_subroutine_entry_address(), "hasn't been generated yet");
1492
1493 // call indirectly to solve generation ordering problem
1494 AddressLiteral a(StubRoutines::Sparc::stop_subroutine_entry_address());
1495 load_ptr_contents(a, O5);
1496 jmpl(O5, 0, O7);
1497 delayed()->nop();
1498
1499 breakpoint_trap(); // make stop actually stop rather than writing
1500 // unnoticeable results in the output files.
1501
1502 // restore(); done in callee to save space!
1503 }
1504
1505
1506 void MacroAssembler::warn(const char* msg) {
1507 save_frame(::round_to(sizeof(RegistersForDebugging) / BytesPerWord, 2));
1508 RegistersForDebugging::save_registers(this);
1509 mov(O0, L0);
1510 // Size of set() should stay the same
1511 patchable_set((intptr_t)msg, O0);
1512 call( CAST_FROM_FN_PTR(address, warning) );
1513 delayed()->nop();
1514 // ret();
1515 // delayed()->restore();
1516 RegistersForDebugging::restore_registers(this, L0);
1517 restore();
1518 }
1519
1520
1521 void MacroAssembler::untested(const char* what) {
1522 // We must be able to turn interactive prompting off
1523 // in order to run automated test scripts on the VM
1524 // Use the flag ShowMessageBoxOnError
1525
1526 const char* b = NULL;
1527 {
1528 ResourceMark rm;
1529 stringStream ss;
1530 ss.print("untested: %s", what);
1531 b = code_string(ss.as_string());
1532 }
1533 if (ShowMessageBoxOnError) { STOP(b); }
1534 else { warn(b); }
1535 }
1536
1537
1538 void MacroAssembler::stop_subroutine() {
1539 RegistersForDebugging::save_registers(this);
1540
1541 // for the sake of the debugger, stick a PC on the current frame
1542 // (this assumes that the caller has performed an extra "save")
1543 mov(I7, L7);
1544 add(O7, -7 * BytesPerInt, I7);
1545
1546 save_frame(); // one more save to free up another O7 register
1547 mov(I0, O1); // addr of reg save area
1548
1549 // We expect pointer to message in I1. Caller must set it up in O1
1550 mov(I1, O0); // get msg
1551 call (CAST_FROM_FN_PTR(address, MacroAssembler::debug), relocInfo::runtime_call_type);
1552 delayed()->nop();
1553
1554 restore();
1555
1556 RegistersForDebugging::restore_registers(this, O0);
1557
1558 save_frame(0);
1559 call(CAST_FROM_FN_PTR(address,breakpoint));
1560 delayed()->nop();
1561 restore();
1562
1563 mov(L7, I7);
1564 retl();
1565 delayed()->restore(); // see stop above
1566 }
1567
1568
1569 void MacroAssembler::debug(char* msg, RegistersForDebugging* regs) {
1570 if ( ShowMessageBoxOnError ) {
1571 JavaThread* thread = JavaThread::current();
1572 JavaThreadState saved_state = thread->thread_state();
1573 thread->set_thread_state(_thread_in_vm);
1574 {
1575 // In order to get locks work, we need to fake a in_VM state
1576 ttyLocker ttyl;
1577 ::tty->print_cr("EXECUTION STOPPED: %s\n", msg);
1578 if (CountBytecodes || TraceBytecodes || StopInterpreterAt) {
1579 BytecodeCounter::print();
1580 }
1581 if (os::message_box(msg, "Execution stopped, print registers?"))
1582 regs->print(::tty);
1583 }
1584 BREAKPOINT;
1585 ThreadStateTransition::transition(JavaThread::current(), _thread_in_vm, saved_state);
1586 }
1587 else {
1588 ::tty->print_cr("=============== DEBUG MESSAGE: %s ================\n", msg);
1589 }
1590 assert(false, "DEBUG MESSAGE: %s", msg);
1591 }
1592
1593
1594 void MacroAssembler::calc_mem_param_words(Register Rparam_words, Register Rresult) {
1595 subcc( Rparam_words, Argument::n_register_parameters, Rresult); // how many mem words?
1596 Label no_extras;
1597 br( negative, true, pt, no_extras ); // if neg, clear reg
1598 delayed()->set(0, Rresult); // annuled, so only if taken
1599 bind( no_extras );
1600 }
1601
1602
1603 void MacroAssembler::calc_frame_size(Register Rextra_words, Register Rresult) {
1604 #ifdef _LP64
1605 add(Rextra_words, frame::memory_parameter_word_sp_offset, Rresult);
1606 #else
1607 add(Rextra_words, frame::memory_parameter_word_sp_offset + 1, Rresult);
1608 #endif
1609 bclr(1, Rresult);
1610 sll(Rresult, LogBytesPerWord, Rresult); // Rresult has total frame bytes
1611 }
1612
1613
1614 void MacroAssembler::calc_frame_size_and_save(Register Rextra_words, Register Rresult) {
1615 calc_frame_size(Rextra_words, Rresult);
1616 neg(Rresult);
1617 save(SP, Rresult, SP);
1618 }
1619
1620
1621 // ---------------------------------------------------------
1622 Assembler::RCondition cond2rcond(Assembler::Condition c) {
1623 switch (c) {
1624 /*case zero: */
1625 case Assembler::equal: return Assembler::rc_z;
1626 case Assembler::lessEqual: return Assembler::rc_lez;
1627 case Assembler::less: return Assembler::rc_lz;
1628 /*case notZero:*/
1629 case Assembler::notEqual: return Assembler::rc_nz;
1630 case Assembler::greater: return Assembler::rc_gz;
1631 case Assembler::greaterEqual: return Assembler::rc_gez;
1632 }
1633 ShouldNotReachHere();
1634 return Assembler::rc_z;
1635 }
1636
1637 // compares (32 bit) register with zero and branches. NOT FOR USE WITH 64-bit POINTERS
1638 void MacroAssembler::cmp_zero_and_br(Condition c, Register s1, Label& L, bool a, Predict p) {
1639 tst(s1);
1640 br (c, a, p, L);
1641 }
1642
1643 // Compares a pointer register with zero and branches on null.
1644 // Does a test & branch on 32-bit systems and a register-branch on 64-bit.
1645 void MacroAssembler::br_null( Register s1, bool a, Predict p, Label& L ) {
1646 assert_not_delayed();
1647 #ifdef _LP64
1648 bpr( rc_z, a, p, s1, L );
1649 #else
1650 tst(s1);
1651 br ( zero, a, p, L );
1652 #endif
1653 }
1654
1655 void MacroAssembler::br_notnull( Register s1, bool a, Predict p, Label& L ) {
1656 assert_not_delayed();
1657 #ifdef _LP64
1658 bpr( rc_nz, a, p, s1, L );
1659 #else
1660 tst(s1);
1661 br ( notZero, a, p, L );
1662 #endif
1663 }
1664
1665 // Compare registers and branch with nop in delay slot or cbcond without delay slot.
1666
1667 // Compare integer (32 bit) values (icc only).
1668 void MacroAssembler::cmp_and_br_short(Register s1, Register s2, Condition c,
1669 Predict p, Label& L) {
1670 assert_not_delayed();
1671 if (use_cbcond(L)) {
1672 Assembler::cbcond(c, icc, s1, s2, L);
1673 } else {
1674 cmp(s1, s2);
1675 br(c, false, p, L);
1676 delayed()->nop();
1677 }
1678 }
1679
1680 // Compare integer (32 bit) values (icc only).
1681 void MacroAssembler::cmp_and_br_short(Register s1, int simm13a, Condition c,
1682 Predict p, Label& L) {
1683 assert_not_delayed();
1684 if (is_simm(simm13a,5) && use_cbcond(L)) {
1685 Assembler::cbcond(c, icc, s1, simm13a, L);
1686 } else {
1687 cmp(s1, simm13a);
1688 br(c, false, p, L);
1689 delayed()->nop();
1690 }
1691 }
1692
1693 // Branch that tests xcc in LP64 and icc in !LP64
1694 void MacroAssembler::cmp_and_brx_short(Register s1, Register s2, Condition c,
1695 Predict p, Label& L) {
1696 assert_not_delayed();
1697 if (use_cbcond(L)) {
1698 Assembler::cbcond(c, ptr_cc, s1, s2, L);
1699 } else {
1700 cmp(s1, s2);
1701 brx(c, false, p, L);
1702 delayed()->nop();
1703 }
1704 }
1705
1706 // Branch that tests xcc in LP64 and icc in !LP64
1707 void MacroAssembler::cmp_and_brx_short(Register s1, int simm13a, Condition c,
1708 Predict p, Label& L) {
1709 assert_not_delayed();
1710 if (is_simm(simm13a,5) && use_cbcond(L)) {
1711 Assembler::cbcond(c, ptr_cc, s1, simm13a, L);
1712 } else {
1713 cmp(s1, simm13a);
1714 brx(c, false, p, L);
1715 delayed()->nop();
1716 }
1717 }
1718
1719 // Short branch version for compares a pointer with zero.
1720
1721 void MacroAssembler::br_null_short(Register s1, Predict p, Label& L) {
1722 assert_not_delayed();
1723 if (use_cbcond(L)) {
1724 Assembler::cbcond(zero, ptr_cc, s1, 0, L);
1725 return;
1726 }
1727 br_null(s1, false, p, L);
1728 delayed()->nop();
1729 }
1730
1731 void MacroAssembler::br_notnull_short(Register s1, Predict p, Label& L) {
1732 assert_not_delayed();
1733 if (use_cbcond(L)) {
1734 Assembler::cbcond(notZero, ptr_cc, s1, 0, L);
1735 return;
1736 }
1737 br_notnull(s1, false, p, L);
1738 delayed()->nop();
1739 }
1740
1741 // Unconditional short branch
1742 void MacroAssembler::ba_short(Label& L) {
1743 if (use_cbcond(L)) {
1744 Assembler::cbcond(equal, icc, G0, G0, L);
1745 return;
1746 }
1747 br(always, false, pt, L);
1748 delayed()->nop();
1749 }
1750
1751 // instruction sequences factored across compiler & interpreter
1752
1753
1754 void MacroAssembler::lcmp( Register Ra_hi, Register Ra_low,
1755 Register Rb_hi, Register Rb_low,
1756 Register Rresult) {
1757
1758 Label check_low_parts, done;
1759
1760 cmp(Ra_hi, Rb_hi ); // compare hi parts
1761 br(equal, true, pt, check_low_parts);
1762 delayed()->cmp(Ra_low, Rb_low); // test low parts
1763
1764 // And, with an unsigned comparison, it does not matter if the numbers
1765 // are negative or not.
1766 // E.g., -2 cmp -1: the low parts are 0xfffffffe and 0xffffffff.
1767 // The second one is bigger (unsignedly).
1768
1769 // Other notes: The first move in each triplet can be unconditional
1770 // (and therefore probably prefetchable).
1771 // And the equals case for the high part does not need testing,
1772 // since that triplet is reached only after finding the high halves differ.
1773
1774 mov(-1, Rresult);
1775 ba(done);
1776 delayed()->movcc(greater, false, icc, 1, Rresult);
1777
1778 bind(check_low_parts);
1779
1780 mov( -1, Rresult);
1781 movcc(equal, false, icc, 0, Rresult);
1782 movcc(greaterUnsigned, false, icc, 1, Rresult);
1783
1784 bind(done);
1785 }
1786
1787 void MacroAssembler::lneg( Register Rhi, Register Rlow ) {
1788 subcc( G0, Rlow, Rlow );
1789 subc( G0, Rhi, Rhi );
1790 }
1791
1792 void MacroAssembler::lshl( Register Rin_high, Register Rin_low,
1793 Register Rcount,
1794 Register Rout_high, Register Rout_low,
1795 Register Rtemp ) {
1796
1797
1798 Register Ralt_count = Rtemp;
1799 Register Rxfer_bits = Rtemp;
1800
1801 assert( Ralt_count != Rin_high
1802 && Ralt_count != Rin_low
1803 && Ralt_count != Rcount
1804 && Rxfer_bits != Rin_low
1805 && Rxfer_bits != Rin_high
1806 && Rxfer_bits != Rcount
1807 && Rxfer_bits != Rout_low
1808 && Rout_low != Rin_high,
1809 "register alias checks");
1810
1811 Label big_shift, done;
1812
1813 // This code can be optimized to use the 64 bit shifts in V9.
1814 // Here we use the 32 bit shifts.
1815
1816 and3( Rcount, 0x3f, Rcount); // take least significant 6 bits
1817 subcc(Rcount, 31, Ralt_count);
1818 br(greater, true, pn, big_shift);
1819 delayed()->dec(Ralt_count);
1820
1821 // shift < 32 bits, Ralt_count = Rcount-31
1822
1823 // We get the transfer bits by shifting right by 32-count the low
1824 // register. This is done by shifting right by 31-count and then by one
1825 // more to take care of the special (rare) case where count is zero
1826 // (shifting by 32 would not work).
1827
1828 neg(Ralt_count);
1829
1830 // The order of the next two instructions is critical in the case where
1831 // Rin and Rout are the same and should not be reversed.
1832
1833 srl(Rin_low, Ralt_count, Rxfer_bits); // shift right by 31-count
1834 if (Rcount != Rout_low) {
1835 sll(Rin_low, Rcount, Rout_low); // low half
1836 }
1837 sll(Rin_high, Rcount, Rout_high);
1838 if (Rcount == Rout_low) {
1839 sll(Rin_low, Rcount, Rout_low); // low half
1840 }
1841 srl(Rxfer_bits, 1, Rxfer_bits ); // shift right by one more
1842 ba(done);
1843 delayed()->or3(Rout_high, Rxfer_bits, Rout_high); // new hi value: or in shifted old hi part and xfer from low
1844
1845 // shift >= 32 bits, Ralt_count = Rcount-32
1846 bind(big_shift);
1847 sll(Rin_low, Ralt_count, Rout_high );
1848 clr(Rout_low);
1849
1850 bind(done);
1851 }
1852
1853
1854 void MacroAssembler::lshr( Register Rin_high, Register Rin_low,
1855 Register Rcount,
1856 Register Rout_high, Register Rout_low,
1857 Register Rtemp ) {
1858
1859 Register Ralt_count = Rtemp;
1860 Register Rxfer_bits = Rtemp;
1861
1862 assert( Ralt_count != Rin_high
1863 && Ralt_count != Rin_low
1864 && Ralt_count != Rcount
1865 && Rxfer_bits != Rin_low
1866 && Rxfer_bits != Rin_high
1867 && Rxfer_bits != Rcount
1868 && Rxfer_bits != Rout_high
1869 && Rout_high != Rin_low,
1870 "register alias checks");
1871
1872 Label big_shift, done;
1873
1874 // This code can be optimized to use the 64 bit shifts in V9.
1875 // Here we use the 32 bit shifts.
1876
1877 and3( Rcount, 0x3f, Rcount); // take least significant 6 bits
1878 subcc(Rcount, 31, Ralt_count);
1879 br(greater, true, pn, big_shift);
1880 delayed()->dec(Ralt_count);
1881
1882 // shift < 32 bits, Ralt_count = Rcount-31
1883
1884 // We get the transfer bits by shifting left by 32-count the high
1885 // register. This is done by shifting left by 31-count and then by one
1886 // more to take care of the special (rare) case where count is zero
1887 // (shifting by 32 would not work).
1888
1889 neg(Ralt_count);
1890 if (Rcount != Rout_low) {
1891 srl(Rin_low, Rcount, Rout_low);
1892 }
1893
1894 // The order of the next two instructions is critical in the case where
1895 // Rin and Rout are the same and should not be reversed.
1896
1897 sll(Rin_high, Ralt_count, Rxfer_bits); // shift left by 31-count
1898 sra(Rin_high, Rcount, Rout_high ); // high half
1899 sll(Rxfer_bits, 1, Rxfer_bits); // shift left by one more
1900 if (Rcount == Rout_low) {
1901 srl(Rin_low, Rcount, Rout_low);
1902 }
1903 ba(done);
1904 delayed()->or3(Rout_low, Rxfer_bits, Rout_low); // new low value: or shifted old low part and xfer from high
1905
1906 // shift >= 32 bits, Ralt_count = Rcount-32
1907 bind(big_shift);
1908
1909 sra(Rin_high, Ralt_count, Rout_low);
1910 sra(Rin_high, 31, Rout_high); // sign into hi
1911
1912 bind( done );
1913 }
1914
1915
1916
1917 void MacroAssembler::lushr( Register Rin_high, Register Rin_low,
1918 Register Rcount,
1919 Register Rout_high, Register Rout_low,
1920 Register Rtemp ) {
1921
1922 Register Ralt_count = Rtemp;
1923 Register Rxfer_bits = Rtemp;
1924
1925 assert( Ralt_count != Rin_high
1926 && Ralt_count != Rin_low
1927 && Ralt_count != Rcount
1928 && Rxfer_bits != Rin_low
1929 && Rxfer_bits != Rin_high
1930 && Rxfer_bits != Rcount
1931 && Rxfer_bits != Rout_high
1932 && Rout_high != Rin_low,
1933 "register alias checks");
1934
1935 Label big_shift, done;
1936
1937 // This code can be optimized to use the 64 bit shifts in V9.
1938 // Here we use the 32 bit shifts.
1939
1940 and3( Rcount, 0x3f, Rcount); // take least significant 6 bits
1941 subcc(Rcount, 31, Ralt_count);
1942 br(greater, true, pn, big_shift);
1943 delayed()->dec(Ralt_count);
1944
1945 // shift < 32 bits, Ralt_count = Rcount-31
1946
1947 // We get the transfer bits by shifting left by 32-count the high
1948 // register. This is done by shifting left by 31-count and then by one
1949 // more to take care of the special (rare) case where count is zero
1950 // (shifting by 32 would not work).
1951
1952 neg(Ralt_count);
1953 if (Rcount != Rout_low) {
1954 srl(Rin_low, Rcount, Rout_low);
1955 }
1956
1957 // The order of the next two instructions is critical in the case where
1958 // Rin and Rout are the same and should not be reversed.
1959
1960 sll(Rin_high, Ralt_count, Rxfer_bits); // shift left by 31-count
1961 srl(Rin_high, Rcount, Rout_high ); // high half
1962 sll(Rxfer_bits, 1, Rxfer_bits); // shift left by one more
1963 if (Rcount == Rout_low) {
1964 srl(Rin_low, Rcount, Rout_low);
1965 }
1966 ba(done);
1967 delayed()->or3(Rout_low, Rxfer_bits, Rout_low); // new low value: or shifted old low part and xfer from high
1968
1969 // shift >= 32 bits, Ralt_count = Rcount-32
1970 bind(big_shift);
1971
1972 srl(Rin_high, Ralt_count, Rout_low);
1973 clr(Rout_high);
1974
1975 bind( done );
1976 }
1977
1978 #ifdef _LP64
1979 void MacroAssembler::lcmp( Register Ra, Register Rb, Register Rresult) {
1980 cmp(Ra, Rb);
1981 mov(-1, Rresult);
1982 movcc(equal, false, xcc, 0, Rresult);
1983 movcc(greater, false, xcc, 1, Rresult);
1984 }
1985 #endif
1986
1987
1988 void MacroAssembler::load_sized_value(Address src, Register dst, size_t size_in_bytes, bool is_signed) {
1989 switch (size_in_bytes) {
1990 case 8: ld_long(src, dst); break;
1991 case 4: ld( src, dst); break;
1992 case 2: is_signed ? ldsh(src, dst) : lduh(src, dst); break;
1993 case 1: is_signed ? ldsb(src, dst) : ldub(src, dst); break;
1994 default: ShouldNotReachHere();
1995 }
1996 }
1997
1998 void MacroAssembler::store_sized_value(Register src, Address dst, size_t size_in_bytes) {
1999 switch (size_in_bytes) {
2000 case 8: st_long(src, dst); break;
2001 case 4: st( src, dst); break;
2002 case 2: sth( src, dst); break;
2003 case 1: stb( src, dst); break;
2004 default: ShouldNotReachHere();
2005 }
2006 }
2007
2008
2009 void MacroAssembler::float_cmp( bool is_float, int unordered_result,
2010 FloatRegister Fa, FloatRegister Fb,
2011 Register Rresult) {
2012 if (is_float) {
2013 fcmp(FloatRegisterImpl::S, fcc0, Fa, Fb);
2014 } else {
2015 fcmp(FloatRegisterImpl::D, fcc0, Fa, Fb);
2016 }
2017
2018 if (unordered_result == 1) {
2019 mov( -1, Rresult);
2020 movcc(f_equal, true, fcc0, 0, Rresult);
2021 movcc(f_unorderedOrGreater, true, fcc0, 1, Rresult);
2022 } else {
2023 mov( -1, Rresult);
2024 movcc(f_equal, true, fcc0, 0, Rresult);
2025 movcc(f_greater, true, fcc0, 1, Rresult);
2026 }
2027 }
2028
2029
2030 void MacroAssembler::save_all_globals_into_locals() {
2031 mov(G1,L1);
2032 mov(G2,L2);
2033 mov(G3,L3);
2034 mov(G4,L4);
2035 mov(G5,L5);
2036 mov(G6,L6);
2037 mov(G7,L7);
2038 }
2039
2040 void MacroAssembler::restore_globals_from_locals() {
2041 mov(L1,G1);
2042 mov(L2,G2);
2043 mov(L3,G3);
2044 mov(L4,G4);
2045 mov(L5,G5);
2046 mov(L6,G6);
2047 mov(L7,G7);
2048 }
2049
2050 RegisterOrConstant MacroAssembler::delayed_value_impl(intptr_t* delayed_value_addr,
2051 Register tmp,
2052 int offset) {
2053 intptr_t value = *delayed_value_addr;
2054 if (value != 0)
2055 return RegisterOrConstant(value + offset);
2056
2057 // load indirectly to solve generation ordering problem
2058 AddressLiteral a(delayed_value_addr);
2059 load_ptr_contents(a, tmp);
2060
2061 #ifdef ASSERT
2062 tst(tmp);
2063 breakpoint_trap(zero, xcc);
2064 #endif
2065
2066 if (offset != 0)
2067 add(tmp, offset, tmp);
2068
2069 return RegisterOrConstant(tmp);
2070 }
2071
2072
2073 RegisterOrConstant MacroAssembler::regcon_andn_ptr(RegisterOrConstant s1, RegisterOrConstant s2, RegisterOrConstant d, Register temp) {
2074 assert(d.register_or_noreg() != G0, "lost side effect");
2075 if ((s2.is_constant() && s2.as_constant() == 0) ||
2076 (s2.is_register() && s2.as_register() == G0)) {
2077 // Do nothing, just move value.
2078 if (s1.is_register()) {
2079 if (d.is_constant()) d = temp;
2080 mov(s1.as_register(), d.as_register());
2081 return d;
2082 } else {
2083 return s1;
2084 }
2085 }
2086
2087 if (s1.is_register()) {
2088 assert_different_registers(s1.as_register(), temp);
2089 if (d.is_constant()) d = temp;
2090 andn(s1.as_register(), ensure_simm13_or_reg(s2, temp), d.as_register());
2091 return d;
2092 } else {
2093 if (s2.is_register()) {
2094 assert_different_registers(s2.as_register(), temp);
2095 if (d.is_constant()) d = temp;
2096 set(s1.as_constant(), temp);
2097 andn(temp, s2.as_register(), d.as_register());
2098 return d;
2099 } else {
2100 intptr_t res = s1.as_constant() & ~s2.as_constant();
2101 return res;
2102 }
2103 }
2104 }
2105
2106 RegisterOrConstant MacroAssembler::regcon_inc_ptr(RegisterOrConstant s1, RegisterOrConstant s2, RegisterOrConstant d, Register temp) {
2107 assert(d.register_or_noreg() != G0, "lost side effect");
2108 if ((s2.is_constant() && s2.as_constant() == 0) ||
2109 (s2.is_register() && s2.as_register() == G0)) {
2110 // Do nothing, just move value.
2111 if (s1.is_register()) {
2112 if (d.is_constant()) d = temp;
2113 mov(s1.as_register(), d.as_register());
2114 return d;
2115 } else {
2116 return s1;
2117 }
2118 }
2119
2120 if (s1.is_register()) {
2121 assert_different_registers(s1.as_register(), temp);
2122 if (d.is_constant()) d = temp;
2123 add(s1.as_register(), ensure_simm13_or_reg(s2, temp), d.as_register());
2124 return d;
2125 } else {
2126 if (s2.is_register()) {
2127 assert_different_registers(s2.as_register(), temp);
2128 if (d.is_constant()) d = temp;
2129 add(s2.as_register(), ensure_simm13_or_reg(s1, temp), d.as_register());
2130 return d;
2131 } else {
2132 intptr_t res = s1.as_constant() + s2.as_constant();
2133 return res;
2134 }
2135 }
2136 }
2137
2138 RegisterOrConstant MacroAssembler::regcon_sll_ptr(RegisterOrConstant s1, RegisterOrConstant s2, RegisterOrConstant d, Register temp) {
2139 assert(d.register_or_noreg() != G0, "lost side effect");
2140 if (!is_simm13(s2.constant_or_zero()))
2141 s2 = (s2.as_constant() & 0xFF);
2142 if ((s2.is_constant() && s2.as_constant() == 0) ||
2143 (s2.is_register() && s2.as_register() == G0)) {
2144 // Do nothing, just move value.
2145 if (s1.is_register()) {
2146 if (d.is_constant()) d = temp;
2147 mov(s1.as_register(), d.as_register());
2148 return d;
2149 } else {
2150 return s1;
2151 }
2152 }
2153
2154 if (s1.is_register()) {
2155 assert_different_registers(s1.as_register(), temp);
2156 if (d.is_constant()) d = temp;
2157 sll_ptr(s1.as_register(), ensure_simm13_or_reg(s2, temp), d.as_register());
2158 return d;
2159 } else {
2160 if (s2.is_register()) {
2161 assert_different_registers(s2.as_register(), temp);
2162 if (d.is_constant()) d = temp;
2163 set(s1.as_constant(), temp);
2164 sll_ptr(temp, s2.as_register(), d.as_register());
2165 return d;
2166 } else {
2167 intptr_t res = s1.as_constant() << s2.as_constant();
2168 return res;
2169 }
2170 }
2171 }
2172
2173
2174 // Look up the method for a megamorphic invokeinterface call.
2175 // The target method is determined by <intf_klass, itable_index>.
2176 // The receiver klass is in recv_klass.
2177 // On success, the result will be in method_result, and execution falls through.
2178 // On failure, execution transfers to the given label.
2179 void MacroAssembler::lookup_interface_method(Register recv_klass,
2180 Register intf_klass,
2181 RegisterOrConstant itable_index,
2182 Register method_result,
2183 Register scan_temp,
2184 Register sethi_temp,
2185 Label& L_no_such_interface) {
2186 assert_different_registers(recv_klass, intf_klass, method_result, scan_temp);
2187 assert(itable_index.is_constant() || itable_index.as_register() == method_result,
2188 "caller must use same register for non-constant itable index as for method");
2189
2190 Label L_no_such_interface_restore;
2191 bool did_save = false;
2192 if (scan_temp == noreg || sethi_temp == noreg) {
2193 Register recv_2 = recv_klass->is_global() ? recv_klass : L0;
2194 Register intf_2 = intf_klass->is_global() ? intf_klass : L1;
2195 assert(method_result->is_global(), "must be able to return value");
2196 scan_temp = L2;
2197 sethi_temp = L3;
2198 save_frame_and_mov(0, recv_klass, recv_2, intf_klass, intf_2);
2199 recv_klass = recv_2;
2200 intf_klass = intf_2;
2201 did_save = true;
2202 }
2203
2204 // Compute start of first itableOffsetEntry (which is at the end of the vtable)
2205 int vtable_base = in_bytes(InstanceKlass::vtable_start_offset());
2206 int scan_step = itableOffsetEntry::size() * wordSize;
2207 int vte_size = vtableEntry::size_in_bytes();
2208
2209 lduw(recv_klass, in_bytes(InstanceKlass::vtable_length_offset()), scan_temp);
2210 // %%% We should store the aligned, prescaled offset in the klassoop.
2211 // Then the next several instructions would fold away.
2212
2213 int round_to_unit = ((HeapWordsPerLong > 1) ? BytesPerLong : 0);
2214 int itb_offset = vtable_base;
2215 if (round_to_unit != 0) {
2216 // hoist first instruction of round_to(scan_temp, BytesPerLong):
2217 itb_offset += round_to_unit - wordSize;
2218 }
2219 int itb_scale = exact_log2(vtableEntry::size_in_bytes());
2220 sll(scan_temp, itb_scale, scan_temp);
2221 add(scan_temp, itb_offset, scan_temp);
2222 if (round_to_unit != 0) {
2223 // Round up to align_object_offset boundary
2224 // see code for InstanceKlass::start_of_itable!
2225 // Was: round_to(scan_temp, BytesPerLong);
2226 // Hoisted: add(scan_temp, BytesPerLong-1, scan_temp);
2227 and3(scan_temp, -round_to_unit, scan_temp);
2228 }
2229 add(recv_klass, scan_temp, scan_temp);
2230
2231 // Adjust recv_klass by scaled itable_index, so we can free itable_index.
2232 RegisterOrConstant itable_offset = itable_index;
2233 itable_offset = regcon_sll_ptr(itable_index, exact_log2(itableMethodEntry::size() * wordSize), itable_offset);
2234 itable_offset = regcon_inc_ptr(itable_offset, itableMethodEntry::method_offset_in_bytes(), itable_offset);
2235 add(recv_klass, ensure_simm13_or_reg(itable_offset, sethi_temp), recv_klass);
2236
2237 // for (scan = klass->itable(); scan->interface() != NULL; scan += scan_step) {
2238 // if (scan->interface() == intf) {
2239 // result = (klass + scan->offset() + itable_index);
2240 // }
2241 // }
2242 Label L_search, L_found_method;
2243
2244 for (int peel = 1; peel >= 0; peel--) {
2245 // %%%% Could load both offset and interface in one ldx, if they were
2246 // in the opposite order. This would save a load.
2247 ld_ptr(scan_temp, itableOffsetEntry::interface_offset_in_bytes(), method_result);
2248
2249 // Check that this entry is non-null. A null entry means that
2250 // the receiver class doesn't implement the interface, and wasn't the
2251 // same as when the caller was compiled.
2252 bpr(Assembler::rc_z, false, Assembler::pn, method_result, did_save ? L_no_such_interface_restore : L_no_such_interface);
2253 delayed()->cmp(method_result, intf_klass);
2254
2255 if (peel) {
2256 brx(Assembler::equal, false, Assembler::pt, L_found_method);
2257 } else {
2258 brx(Assembler::notEqual, false, Assembler::pn, L_search);
2259 // (invert the test to fall through to found_method...)
2260 }
2261 delayed()->add(scan_temp, scan_step, scan_temp);
2262
2263 if (!peel) break;
2264
2265 bind(L_search);
2266 }
2267
2268 bind(L_found_method);
2269
2270 // Got a hit.
2271 int ito_offset = itableOffsetEntry::offset_offset_in_bytes();
2272 // scan_temp[-scan_step] points to the vtable offset we need
2273 ito_offset -= scan_step;
2274 lduw(scan_temp, ito_offset, scan_temp);
2275 ld_ptr(recv_klass, scan_temp, method_result);
2276
2277 if (did_save) {
2278 Label L_done;
2279 ba(L_done);
2280 delayed()->restore();
2281
2282 bind(L_no_such_interface_restore);
2283 ba(L_no_such_interface);
2284 delayed()->restore();
2285
2286 bind(L_done);
2287 }
2288 }
2289
2290
2291 // virtual method calling
2292 void MacroAssembler::lookup_virtual_method(Register recv_klass,
2293 RegisterOrConstant vtable_index,
2294 Register method_result) {
2295 assert_different_registers(recv_klass, method_result, vtable_index.register_or_noreg());
2296 Register sethi_temp = method_result;
2297 const int base = in_bytes(InstanceKlass::vtable_start_offset()) +
2298 // method pointer offset within the vtable entry:
2299 vtableEntry::method_offset_in_bytes();
2300 RegisterOrConstant vtable_offset = vtable_index;
2301 // Each of the following three lines potentially generates an instruction.
2302 // But the total number of address formation instructions will always be
2303 // at most two, and will often be zero. In any case, it will be optimal.
2304 // If vtable_index is a register, we will have (sll_ptr N,x; inc_ptr B,x; ld_ptr k,x).
2305 // If vtable_index is a constant, we will have at most (set B+X<<N,t; ld_ptr k,t).
2306 vtable_offset = regcon_sll_ptr(vtable_index, exact_log2(vtableEntry::size_in_bytes()), vtable_offset);
2307 vtable_offset = regcon_inc_ptr(vtable_offset, base, vtable_offset, sethi_temp);
2308 Address vtable_entry_addr(recv_klass, ensure_simm13_or_reg(vtable_offset, sethi_temp));
2309 ld_ptr(vtable_entry_addr, method_result);
2310 }
2311
2312
2313 void MacroAssembler::check_klass_subtype(Register sub_klass,
2314 Register super_klass,
2315 Register temp_reg,
2316 Register temp2_reg,
2317 Label& L_success) {
2318 Register sub_2 = sub_klass;
2319 Register sup_2 = super_klass;
2320 if (!sub_2->is_global()) sub_2 = L0;
2321 if (!sup_2->is_global()) sup_2 = L1;
2322 bool did_save = false;
2323 if (temp_reg == noreg || temp2_reg == noreg) {
2324 temp_reg = L2;
2325 temp2_reg = L3;
2326 save_frame_and_mov(0, sub_klass, sub_2, super_klass, sup_2);
2327 sub_klass = sub_2;
2328 super_klass = sup_2;
2329 did_save = true;
2330 }
2331 Label L_failure, L_pop_to_failure, L_pop_to_success;
2332 check_klass_subtype_fast_path(sub_klass, super_klass,
2333 temp_reg, temp2_reg,
2334 (did_save ? &L_pop_to_success : &L_success),
2335 (did_save ? &L_pop_to_failure : &L_failure), NULL);
2336
2337 if (!did_save)
2338 save_frame_and_mov(0, sub_klass, sub_2, super_klass, sup_2);
2339 check_klass_subtype_slow_path(sub_2, sup_2,
2340 L2, L3, L4, L5,
2341 NULL, &L_pop_to_failure);
2342
2343 // on success:
2344 bind(L_pop_to_success);
2345 restore();
2346 ba_short(L_success);
2347
2348 // on failure:
2349 bind(L_pop_to_failure);
2350 restore();
2351 bind(L_failure);
2352 }
2353
2354
2355 void MacroAssembler::check_klass_subtype_fast_path(Register sub_klass,
2356 Register super_klass,
2357 Register temp_reg,
2358 Register temp2_reg,
2359 Label* L_success,
2360 Label* L_failure,
2361 Label* L_slow_path,
2362 RegisterOrConstant super_check_offset) {
2363 int sc_offset = in_bytes(Klass::secondary_super_cache_offset());
2364 int sco_offset = in_bytes(Klass::super_check_offset_offset());
2365
2366 bool must_load_sco = (super_check_offset.constant_or_zero() == -1);
2367 bool need_slow_path = (must_load_sco ||
2368 super_check_offset.constant_or_zero() == sco_offset);
2369
2370 assert_different_registers(sub_klass, super_klass, temp_reg);
2371 if (super_check_offset.is_register()) {
2372 assert_different_registers(sub_klass, super_klass, temp_reg,
2373 super_check_offset.as_register());
2374 } else if (must_load_sco) {
2375 assert(temp2_reg != noreg, "supply either a temp or a register offset");
2376 }
2377
2378 Label L_fallthrough;
2379 int label_nulls = 0;
2380 if (L_success == NULL) { L_success = &L_fallthrough; label_nulls++; }
2381 if (L_failure == NULL) { L_failure = &L_fallthrough; label_nulls++; }
2382 if (L_slow_path == NULL) { L_slow_path = &L_fallthrough; label_nulls++; }
2383 assert(label_nulls <= 1 ||
2384 (L_slow_path == &L_fallthrough && label_nulls <= 2 && !need_slow_path),
2385 "at most one NULL in the batch, usually");
2386
2387 // If the pointers are equal, we are done (e.g., String[] elements).
2388 // This self-check enables sharing of secondary supertype arrays among
2389 // non-primary types such as array-of-interface. Otherwise, each such
2390 // type would need its own customized SSA.
2391 // We move this check to the front of the fast path because many
2392 // type checks are in fact trivially successful in this manner,
2393 // so we get a nicely predicted branch right at the start of the check.
2394 cmp(super_klass, sub_klass);
2395 brx(Assembler::equal, false, Assembler::pn, *L_success);
2396 delayed()->nop();
2397
2398 // Check the supertype display:
2399 if (must_load_sco) {
2400 // The super check offset is always positive...
2401 lduw(super_klass, sco_offset, temp2_reg);
2402 super_check_offset = RegisterOrConstant(temp2_reg);
2403 // super_check_offset is register.
2404 assert_different_registers(sub_klass, super_klass, temp_reg, super_check_offset.as_register());
2405 }
2406 ld_ptr(sub_klass, super_check_offset, temp_reg);
2407 cmp(super_klass, temp_reg);
2408
2409 // This check has worked decisively for primary supers.
2410 // Secondary supers are sought in the super_cache ('super_cache_addr').
2411 // (Secondary supers are interfaces and very deeply nested subtypes.)
2412 // This works in the same check above because of a tricky aliasing
2413 // between the super_cache and the primary super display elements.
2414 // (The 'super_check_addr' can address either, as the case requires.)
2415 // Note that the cache is updated below if it does not help us find
2416 // what we need immediately.
2417 // So if it was a primary super, we can just fail immediately.
2418 // Otherwise, it's the slow path for us (no success at this point).
2419
2420 // Hacked ba(), which may only be used just before L_fallthrough.
2421 #define FINAL_JUMP(label) \
2422 if (&(label) != &L_fallthrough) { \
2423 ba(label); delayed()->nop(); \
2424 }
2425
2426 if (super_check_offset.is_register()) {
2427 brx(Assembler::equal, false, Assembler::pn, *L_success);
2428 delayed()->cmp(super_check_offset.as_register(), sc_offset);
2429
2430 if (L_failure == &L_fallthrough) {
2431 brx(Assembler::equal, false, Assembler::pt, *L_slow_path);
2432 delayed()->nop();
2433 } else {
2434 brx(Assembler::notEqual, false, Assembler::pn, *L_failure);
2435 delayed()->nop();
2436 FINAL_JUMP(*L_slow_path);
2437 }
2438 } else if (super_check_offset.as_constant() == sc_offset) {
2439 // Need a slow path; fast failure is impossible.
2440 if (L_slow_path == &L_fallthrough) {
2441 brx(Assembler::equal, false, Assembler::pt, *L_success);
2442 delayed()->nop();
2443 } else {
2444 brx(Assembler::notEqual, false, Assembler::pn, *L_slow_path);
2445 delayed()->nop();
2446 FINAL_JUMP(*L_success);
2447 }
2448 } else {
2449 // No slow path; it's a fast decision.
2450 if (L_failure == &L_fallthrough) {
2451 brx(Assembler::equal, false, Assembler::pt, *L_success);
2452 delayed()->nop();
2453 } else {
2454 brx(Assembler::notEqual, false, Assembler::pn, *L_failure);
2455 delayed()->nop();
2456 FINAL_JUMP(*L_success);
2457 }
2458 }
2459
2460 bind(L_fallthrough);
2461
2462 #undef FINAL_JUMP
2463 }
2464
2465
2466 void MacroAssembler::check_klass_subtype_slow_path(Register sub_klass,
2467 Register super_klass,
2468 Register count_temp,
2469 Register scan_temp,
2470 Register scratch_reg,
2471 Register coop_reg,
2472 Label* L_success,
2473 Label* L_failure) {
2474 assert_different_registers(sub_klass, super_klass,
2475 count_temp, scan_temp, scratch_reg, coop_reg);
2476
2477 Label L_fallthrough, L_loop;
2478 int label_nulls = 0;
2479 if (L_success == NULL) { L_success = &L_fallthrough; label_nulls++; }
2480 if (L_failure == NULL) { L_failure = &L_fallthrough; label_nulls++; }
2481 assert(label_nulls <= 1, "at most one NULL in the batch");
2482
2483 // a couple of useful fields in sub_klass:
2484 int ss_offset = in_bytes(Klass::secondary_supers_offset());
2485 int sc_offset = in_bytes(Klass::secondary_super_cache_offset());
2486
2487 // Do a linear scan of the secondary super-klass chain.
2488 // This code is rarely used, so simplicity is a virtue here.
2489
2490 #ifndef PRODUCT
2491 int* pst_counter = &SharedRuntime::_partial_subtype_ctr;
2492 inc_counter((address) pst_counter, count_temp, scan_temp);
2493 #endif
2494
2495 // We will consult the secondary-super array.
2496 ld_ptr(sub_klass, ss_offset, scan_temp);
2497
2498 Register search_key = super_klass;
2499
2500 // Load the array length. (Positive movl does right thing on LP64.)
2501 lduw(scan_temp, Array<Klass*>::length_offset_in_bytes(), count_temp);
2502
2503 // Check for empty secondary super list
2504 tst(count_temp);
2505
2506 // In the array of super classes elements are pointer sized.
2507 int element_size = wordSize;
2508
2509 // Top of search loop
2510 bind(L_loop);
2511 br(Assembler::equal, false, Assembler::pn, *L_failure);
2512 delayed()->add(scan_temp, element_size, scan_temp);
2513
2514 // Skip the array header in all array accesses.
2515 int elem_offset = Array<Klass*>::base_offset_in_bytes();
2516 elem_offset -= element_size; // the scan pointer was pre-incremented also
2517
2518 // Load next super to check
2519 ld_ptr( scan_temp, elem_offset, scratch_reg );
2520
2521 // Look for Rsuper_klass on Rsub_klass's secondary super-class-overflow list
2522 cmp(scratch_reg, search_key);
2523
2524 // A miss means we are NOT a subtype and need to keep looping
2525 brx(Assembler::notEqual, false, Assembler::pn, L_loop);
2526 delayed()->deccc(count_temp); // decrement trip counter in delay slot
2527
2528 // Success. Cache the super we found and proceed in triumph.
2529 st_ptr(super_klass, sub_klass, sc_offset);
2530
2531 if (L_success != &L_fallthrough) {
2532 ba(*L_success);
2533 delayed()->nop();
2534 }
2535
2536 bind(L_fallthrough);
2537 }
2538
2539
2540 RegisterOrConstant MacroAssembler::argument_offset(RegisterOrConstant arg_slot,
2541 Register temp_reg,
2542 int extra_slot_offset) {
2543 // cf. TemplateTable::prepare_invoke(), if (load_receiver).
2544 int stackElementSize = Interpreter::stackElementSize;
2545 int offset = extra_slot_offset * stackElementSize;
2546 if (arg_slot.is_constant()) {
2547 offset += arg_slot.as_constant() * stackElementSize;
2548 return offset;
2549 } else {
2550 assert(temp_reg != noreg, "must specify");
2551 sll_ptr(arg_slot.as_register(), exact_log2(stackElementSize), temp_reg);
2552 if (offset != 0)
2553 add(temp_reg, offset, temp_reg);
2554 return temp_reg;
2555 }
2556 }
2557
2558
2559 Address MacroAssembler::argument_address(RegisterOrConstant arg_slot,
2560 Register temp_reg,
2561 int extra_slot_offset) {
2562 return Address(Gargs, argument_offset(arg_slot, temp_reg, extra_slot_offset));
2563 }
2564
2565
2566 void MacroAssembler::biased_locking_enter(Register obj_reg, Register mark_reg,
2567 Register temp_reg,
2568 Label& done, Label* slow_case,
2569 BiasedLockingCounters* counters) {
2570 assert(UseBiasedLocking, "why call this otherwise?");
2571
2572 if (PrintBiasedLockingStatistics) {
2573 assert_different_registers(obj_reg, mark_reg, temp_reg, O7);
2574 if (counters == NULL)
2575 counters = BiasedLocking::counters();
2576 }
2577
2578 Label cas_label;
2579
2580 // Biased locking
2581 // See whether the lock is currently biased toward our thread and
2582 // whether the epoch is still valid
2583 // Note that the runtime guarantees sufficient alignment of JavaThread
2584 // pointers to allow age to be placed into low bits
2585 assert(markOopDesc::age_shift == markOopDesc::lock_bits + markOopDesc::biased_lock_bits, "biased locking makes assumptions about bit layout");
2586 and3(mark_reg, markOopDesc::biased_lock_mask_in_place, temp_reg);
2587 cmp_and_brx_short(temp_reg, markOopDesc::biased_lock_pattern, Assembler::notEqual, Assembler::pn, cas_label);
2588
2589 load_klass(obj_reg, temp_reg);
2590 ld_ptr(Address(temp_reg, Klass::prototype_header_offset()), temp_reg);
2591 or3(G2_thread, temp_reg, temp_reg);
2592 xor3(mark_reg, temp_reg, temp_reg);
2593 andcc(temp_reg, ~((int) markOopDesc::age_mask_in_place), temp_reg);
2594 if (counters != NULL) {
2595 cond_inc(Assembler::equal, (address) counters->biased_lock_entry_count_addr(), mark_reg, temp_reg);
2596 // Reload mark_reg as we may need it later
2597 ld_ptr(Address(obj_reg, oopDesc::mark_offset_in_bytes()), mark_reg);
2598 }
2599 brx(Assembler::equal, true, Assembler::pt, done);
2600 delayed()->nop();
2601
2602 Label try_revoke_bias;
2603 Label try_rebias;
2604 Address mark_addr = Address(obj_reg, oopDesc::mark_offset_in_bytes());
2605 assert(mark_addr.disp() == 0, "cas must take a zero displacement");
2606
2607 // At this point we know that the header has the bias pattern and
2608 // that we are not the bias owner in the current epoch. We need to
2609 // figure out more details about the state of the header in order to
2610 // know what operations can be legally performed on the object's
2611 // header.
2612
2613 // If the low three bits in the xor result aren't clear, that means
2614 // the prototype header is no longer biased and we have to revoke
2615 // the bias on this object.
2616 btst(markOopDesc::biased_lock_mask_in_place, temp_reg);
2617 brx(Assembler::notZero, false, Assembler::pn, try_revoke_bias);
2618
2619 // Biasing is still enabled for this data type. See whether the
2620 // epoch of the current bias is still valid, meaning that the epoch
2621 // bits of the mark word are equal to the epoch bits of the
2622 // prototype header. (Note that the prototype header's epoch bits
2623 // only change at a safepoint.) If not, attempt to rebias the object
2624 // toward the current thread. Note that we must be absolutely sure
2625 // that the current epoch is invalid in order to do this because
2626 // otherwise the manipulations it performs on the mark word are
2627 // illegal.
2628 delayed()->btst(markOopDesc::epoch_mask_in_place, temp_reg);
2629 brx(Assembler::notZero, false, Assembler::pn, try_rebias);
2630
2631 // The epoch of the current bias is still valid but we know nothing
2632 // about the owner; it might be set or it might be clear. Try to
2633 // acquire the bias of the object using an atomic operation. If this
2634 // fails we will go in to the runtime to revoke the object's bias.
2635 // Note that we first construct the presumed unbiased header so we
2636 // don't accidentally blow away another thread's valid bias.
2637 delayed()->and3(mark_reg,
2638 markOopDesc::biased_lock_mask_in_place | markOopDesc::age_mask_in_place | markOopDesc::epoch_mask_in_place,
2639 mark_reg);
2640 or3(G2_thread, mark_reg, temp_reg);
2641 cas_ptr(mark_addr.base(), mark_reg, temp_reg);
2642 // If the biasing toward our thread failed, this means that
2643 // another thread succeeded in biasing it toward itself and we
2644 // need to revoke that bias. The revocation will occur in the
2645 // interpreter runtime in the slow case.
2646 cmp(mark_reg, temp_reg);
2647 if (counters != NULL) {
2648 cond_inc(Assembler::zero, (address) counters->anonymously_biased_lock_entry_count_addr(), mark_reg, temp_reg);
2649 }
2650 if (slow_case != NULL) {
2651 brx(Assembler::notEqual, true, Assembler::pn, *slow_case);
2652 delayed()->nop();
2653 }
2654 ba_short(done);
2655
2656 bind(try_rebias);
2657 // At this point we know the epoch has expired, meaning that the
2658 // current "bias owner", if any, is actually invalid. Under these
2659 // circumstances _only_, we are allowed to use the current header's
2660 // value as the comparison value when doing the cas to acquire the
2661 // bias in the current epoch. In other words, we allow transfer of
2662 // the bias from one thread to another directly in this situation.
2663 //
2664 // FIXME: due to a lack of registers we currently blow away the age
2665 // bits in this situation. Should attempt to preserve them.
2666 load_klass(obj_reg, temp_reg);
2667 ld_ptr(Address(temp_reg, Klass::prototype_header_offset()), temp_reg);
2668 or3(G2_thread, temp_reg, temp_reg);
2669 cas_ptr(mark_addr.base(), mark_reg, temp_reg);
2670 // If the biasing toward our thread failed, this means that
2671 // another thread succeeded in biasing it toward itself and we
2672 // need to revoke that bias. The revocation will occur in the
2673 // interpreter runtime in the slow case.
2674 cmp(mark_reg, temp_reg);
2675 if (counters != NULL) {
2676 cond_inc(Assembler::zero, (address) counters->rebiased_lock_entry_count_addr(), mark_reg, temp_reg);
2677 }
2678 if (slow_case != NULL) {
2679 brx(Assembler::notEqual, true, Assembler::pn, *slow_case);
2680 delayed()->nop();
2681 }
2682 ba_short(done);
2683
2684 bind(try_revoke_bias);
2685 // The prototype mark in the klass doesn't have the bias bit set any
2686 // more, indicating that objects of this data type are not supposed
2687 // to be biased any more. We are going to try to reset the mark of
2688 // this object to the prototype value and fall through to the
2689 // CAS-based locking scheme. Note that if our CAS fails, it means
2690 // that another thread raced us for the privilege of revoking the
2691 // bias of this particular object, so it's okay to continue in the
2692 // normal locking code.
2693 //
2694 // FIXME: due to a lack of registers we currently blow away the age
2695 // bits in this situation. Should attempt to preserve them.
2696 load_klass(obj_reg, temp_reg);
2697 ld_ptr(Address(temp_reg, Klass::prototype_header_offset()), temp_reg);
2698 cas_ptr(mark_addr.base(), mark_reg, temp_reg);
2699 // Fall through to the normal CAS-based lock, because no matter what
2700 // the result of the above CAS, some thread must have succeeded in
2701 // removing the bias bit from the object's header.
2702 if (counters != NULL) {
2703 cmp(mark_reg, temp_reg);
2704 cond_inc(Assembler::zero, (address) counters->revoked_lock_entry_count_addr(), mark_reg, temp_reg);
2705 }
2706
2707 bind(cas_label);
2708 }
2709
2710 void MacroAssembler::biased_locking_exit (Address mark_addr, Register temp_reg, Label& done,
2711 bool allow_delay_slot_filling) {
2712 // Check for biased locking unlock case, which is a no-op
2713 // Note: we do not have to check the thread ID for two reasons.
2714 // First, the interpreter checks for IllegalMonitorStateException at
2715 // a higher level. Second, if the bias was revoked while we held the
2716 // lock, the object could not be rebiased toward another thread, so
2717 // the bias bit would be clear.
2718 ld_ptr(mark_addr, temp_reg);
2719 and3(temp_reg, markOopDesc::biased_lock_mask_in_place, temp_reg);
2720 cmp(temp_reg, markOopDesc::biased_lock_pattern);
2721 brx(Assembler::equal, allow_delay_slot_filling, Assembler::pt, done);
2722 delayed();
2723 if (!allow_delay_slot_filling) {
2724 nop();
2725 }
2726 }
2727
2728
2729 // compiler_lock_object() and compiler_unlock_object() are direct transliterations
2730 // of i486.ad fast_lock() and fast_unlock(). See those methods for detailed comments.
2731 // The code could be tightened up considerably.
2732 //
2733 // box->dhw disposition - post-conditions at DONE_LABEL.
2734 // - Successful inflated lock: box->dhw != 0.
2735 // Any non-zero value suffices.
2736 // Consider G2_thread, rsp, boxReg, or markOopDesc::unused_mark()
2737 // - Successful Stack-lock: box->dhw == mark.
2738 // box->dhw must contain the displaced mark word value
2739 // - Failure -- icc.ZFlag == 0 and box->dhw is undefined.
2740 // The slow-path fast_enter() and slow_enter() operators
2741 // are responsible for setting box->dhw = NonZero (typically markOopDesc::unused_mark()).
2742 // - Biased: box->dhw is undefined
2743 //
2744 // SPARC refworkload performance - specifically jetstream and scimark - are
2745 // extremely sensitive to the size of the code emitted by compiler_lock_object
2746 // and compiler_unlock_object. Critically, the key factor is code size, not path
2747 // length. (Simply experiments to pad CLO with unexecuted NOPs demonstrte the
2748 // effect).
2749
2750
2751 void MacroAssembler::compiler_lock_object(Register Roop, Register Rmark,
2752 Register Rbox, Register Rscratch,
2753 BiasedLockingCounters* counters,
2754 bool try_bias) {
2755 Address mark_addr(Roop, oopDesc::mark_offset_in_bytes());
2756
2757 verify_oop(Roop);
2758 Label done ;
2759
2760 if (counters != NULL) {
2761 inc_counter((address) counters->total_entry_count_addr(), Rmark, Rscratch);
2762 }
2763
2764 if (EmitSync & 1) {
2765 mov(3, Rscratch);
2766 st_ptr(Rscratch, Rbox, BasicLock::displaced_header_offset_in_bytes());
2767 cmp(SP, G0);
2768 return ;
2769 }
2770
2771 if (EmitSync & 2) {
2772
2773 // Fetch object's markword
2774 ld_ptr(mark_addr, Rmark);
2775
2776 if (try_bias) {
2777 biased_locking_enter(Roop, Rmark, Rscratch, done, NULL, counters);
2778 }
2779
2780 // Save Rbox in Rscratch to be used for the cas operation
2781 mov(Rbox, Rscratch);
2782
2783 // set Rmark to markOop | markOopDesc::unlocked_value
2784 or3(Rmark, markOopDesc::unlocked_value, Rmark);
2785
2786 // Initialize the box. (Must happen before we update the object mark!)
2787 st_ptr(Rmark, Rbox, BasicLock::displaced_header_offset_in_bytes());
2788
2789 // compare object markOop with Rmark and if equal exchange Rscratch with object markOop
2790 assert(mark_addr.disp() == 0, "cas must take a zero displacement");
2791 cas_ptr(mark_addr.base(), Rmark, Rscratch);
2792
2793 // if compare/exchange succeeded we found an unlocked object and we now have locked it
2794 // hence we are done
2795 cmp(Rmark, Rscratch);
2796 #ifdef _LP64
2797 sub(Rscratch, STACK_BIAS, Rscratch);
2798 #endif
2799 brx(Assembler::equal, false, Assembler::pt, done);
2800 delayed()->sub(Rscratch, SP, Rscratch); //pull next instruction into delay slot
2801
2802 // we did not find an unlocked object so see if this is a recursive case
2803 // sub(Rscratch, SP, Rscratch);
2804 assert(os::vm_page_size() > 0xfff, "page size too small - change the constant");
2805 andcc(Rscratch, 0xfffff003, Rscratch);
2806 st_ptr(Rscratch, Rbox, BasicLock::displaced_header_offset_in_bytes());
2807 bind (done);
2808 return ;
2809 }
2810
2811 Label Egress ;
2812
2813 if (EmitSync & 256) {
2814 Label IsInflated ;
2815
2816 ld_ptr(mark_addr, Rmark); // fetch obj->mark
2817 // Triage: biased, stack-locked, neutral, inflated
2818 if (try_bias) {
2819 biased_locking_enter(Roop, Rmark, Rscratch, done, NULL, counters);
2820 // Invariant: if control reaches this point in the emitted stream
2821 // then Rmark has not been modified.
2822 }
2823
2824 // Store mark into displaced mark field in the on-stack basic-lock "box"
2825 // Critically, this must happen before the CAS
2826 // Maximize the ST-CAS distance to minimize the ST-before-CAS penalty.
2827 st_ptr(Rmark, Rbox, BasicLock::displaced_header_offset_in_bytes());
2828 andcc(Rmark, 2, G0);
2829 brx(Assembler::notZero, false, Assembler::pn, IsInflated);
2830 delayed()->
2831
2832 // Try stack-lock acquisition.
2833 // Beware: the 1st instruction is in a delay slot
2834 mov(Rbox, Rscratch);
2835 or3(Rmark, markOopDesc::unlocked_value, Rmark);
2836 assert(mark_addr.disp() == 0, "cas must take a zero displacement");
2837 cas_ptr(mark_addr.base(), Rmark, Rscratch);
2838 cmp(Rmark, Rscratch);
2839 brx(Assembler::equal, false, Assembler::pt, done);
2840 delayed()->sub(Rscratch, SP, Rscratch);
2841
2842 // Stack-lock attempt failed - check for recursive stack-lock.
2843 // See the comments below about how we might remove this case.
2844 #ifdef _LP64
2845 sub(Rscratch, STACK_BIAS, Rscratch);
2846 #endif
2847 assert(os::vm_page_size() > 0xfff, "page size too small - change the constant");
2848 andcc(Rscratch, 0xfffff003, Rscratch);
2849 br(Assembler::always, false, Assembler::pt, done);
2850 delayed()-> st_ptr(Rscratch, Rbox, BasicLock::displaced_header_offset_in_bytes());
2851
2852 bind(IsInflated);
2853 if (EmitSync & 64) {
2854 // If m->owner != null goto IsLocked
2855 // Pessimistic form: Test-and-CAS vs CAS
2856 // The optimistic form avoids RTS->RTO cache line upgrades.
2857 ld_ptr(Rmark, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner), Rscratch);
2858 andcc(Rscratch, Rscratch, G0);
2859 brx(Assembler::notZero, false, Assembler::pn, done);
2860 delayed()->nop();
2861 // m->owner == null : it's unlocked.
2862 }
2863
2864 // Try to CAS m->owner from null to Self
2865 // Invariant: if we acquire the lock then _recursions should be 0.
2866 add(Rmark, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner), Rmark);
2867 mov(G2_thread, Rscratch);
2868 cas_ptr(Rmark, G0, Rscratch);
2869 cmp(Rscratch, G0);
2870 // Intentional fall-through into done
2871 } else {
2872 // Aggressively avoid the Store-before-CAS penalty
2873 // Defer the store into box->dhw until after the CAS
2874 Label IsInflated, Recursive ;
2875
2876 // Anticipate CAS -- Avoid RTS->RTO upgrade
2877 // prefetch (mark_addr, Assembler::severalWritesAndPossiblyReads);
2878
2879 ld_ptr(mark_addr, Rmark); // fetch obj->mark
2880 // Triage: biased, stack-locked, neutral, inflated
2881
2882 if (try_bias) {
2883 biased_locking_enter(Roop, Rmark, Rscratch, done, NULL, counters);
2884 // Invariant: if control reaches this point in the emitted stream
2885 // then Rmark has not been modified.
2886 }
2887 andcc(Rmark, 2, G0);
2888 brx(Assembler::notZero, false, Assembler::pn, IsInflated);
2889 delayed()-> // Beware - dangling delay-slot
2890
2891 // Try stack-lock acquisition.
2892 // Transiently install BUSY (0) encoding in the mark word.
2893 // if the CAS of 0 into the mark was successful then we execute:
2894 // ST box->dhw = mark -- save fetched mark in on-stack basiclock box
2895 // ST obj->mark = box -- overwrite transient 0 value
2896 // This presumes TSO, of course.
2897
2898 mov(0, Rscratch);
2899 or3(Rmark, markOopDesc::unlocked_value, Rmark);
2900 assert(mark_addr.disp() == 0, "cas must take a zero displacement");
2901 cas_ptr(mark_addr.base(), Rmark, Rscratch);
2902 // prefetch (mark_addr, Assembler::severalWritesAndPossiblyReads);
2903 cmp(Rscratch, Rmark);
2904 brx(Assembler::notZero, false, Assembler::pn, Recursive);
2905 delayed()->st_ptr(Rmark, Rbox, BasicLock::displaced_header_offset_in_bytes());
2906 if (counters != NULL) {
2907 cond_inc(Assembler::equal, (address) counters->fast_path_entry_count_addr(), Rmark, Rscratch);
2908 }
2909 ba(done);
2910 delayed()->st_ptr(Rbox, mark_addr);
2911
2912 bind(Recursive);
2913 // Stack-lock attempt failed - check for recursive stack-lock.
2914 // Tests show that we can remove the recursive case with no impact
2915 // on refworkload 0.83. If we need to reduce the size of the code
2916 // emitted by compiler_lock_object() the recursive case is perfect
2917 // candidate.
2918 //
2919 // A more extreme idea is to always inflate on stack-lock recursion.
2920 // This lets us eliminate the recursive checks in compiler_lock_object
2921 // and compiler_unlock_object and the (box->dhw == 0) encoding.
2922 // A brief experiment - requiring changes to synchronizer.cpp, interpreter,
2923 // and showed a performance *increase*. In the same experiment I eliminated
2924 // the fast-path stack-lock code from the interpreter and always passed
2925 // control to the "slow" operators in synchronizer.cpp.
2926
2927 // RScratch contains the fetched obj->mark value from the failed CAS.
2928 #ifdef _LP64
2929 sub(Rscratch, STACK_BIAS, Rscratch);
2930 #endif
2931 sub(Rscratch, SP, Rscratch);
2932 assert(os::vm_page_size() > 0xfff, "page size too small - change the constant");
2933 andcc(Rscratch, 0xfffff003, Rscratch);
2934 if (counters != NULL) {
2935 // Accounting needs the Rscratch register
2936 st_ptr(Rscratch, Rbox, BasicLock::displaced_header_offset_in_bytes());
2937 cond_inc(Assembler::equal, (address) counters->fast_path_entry_count_addr(), Rmark, Rscratch);
2938 ba_short(done);
2939 } else {
2940 ba(done);
2941 delayed()->st_ptr(Rscratch, Rbox, BasicLock::displaced_header_offset_in_bytes());
2942 }
2943
2944 bind (IsInflated);
2945
2946 // Try to CAS m->owner from null to Self
2947 // Invariant: if we acquire the lock then _recursions should be 0.
2948 add(Rmark, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner), Rmark);
2949 mov(G2_thread, Rscratch);
2950 cas_ptr(Rmark, G0, Rscratch);
2951 andcc(Rscratch, Rscratch, G0); // set ICCs for done: icc.zf iff success
2952 // set icc.zf : 1=success 0=failure
2953 // ST box->displaced_header = NonZero.
2954 // Any non-zero value suffices:
2955 // markOopDesc::unused_mark(), G2_thread, RBox, RScratch, rsp, etc.
2956 st_ptr(Rbox, Rbox, BasicLock::displaced_header_offset_in_bytes());
2957 // Intentional fall-through into done
2958 }
2959
2960 bind (done);
2961 }
2962
2963 void MacroAssembler::compiler_unlock_object(Register Roop, Register Rmark,
2964 Register Rbox, Register Rscratch,
2965 bool try_bias) {
2966 Address mark_addr(Roop, oopDesc::mark_offset_in_bytes());
2967
2968 Label done ;
2969
2970 if (EmitSync & 4) {
2971 cmp(SP, G0);
2972 return ;
2973 }
2974
2975 if (EmitSync & 8) {
2976 if (try_bias) {
2977 biased_locking_exit(mark_addr, Rscratch, done);
2978 }
2979
2980 // Test first if it is a fast recursive unlock
2981 ld_ptr(Rbox, BasicLock::displaced_header_offset_in_bytes(), Rmark);
2982 br_null_short(Rmark, Assembler::pt, done);
2983
2984 // Check if it is still a light weight lock, this is is true if we see
2985 // the stack address of the basicLock in the markOop of the object
2986 assert(mark_addr.disp() == 0, "cas must take a zero displacement");
2987 cas_ptr(mark_addr.base(), Rbox, Rmark);
2988 ba(done);
2989 delayed()->cmp(Rbox, Rmark);
2990 bind(done);
2991 return ;
2992 }
2993
2994 // Beware ... If the aggregate size of the code emitted by CLO and CUO is
2995 // is too large performance rolls abruptly off a cliff.
2996 // This could be related to inlining policies, code cache management, or
2997 // I$ effects.
2998 Label LStacked ;
2999
3000 if (try_bias) {
3001 // TODO: eliminate redundant LDs of obj->mark
3002 biased_locking_exit(mark_addr, Rscratch, done);
3003 }
3004
3005 ld_ptr(Roop, oopDesc::mark_offset_in_bytes(), Rmark);
3006 ld_ptr(Rbox, BasicLock::displaced_header_offset_in_bytes(), Rscratch);
3007 andcc(Rscratch, Rscratch, G0);
3008 brx(Assembler::zero, false, Assembler::pn, done);
3009 delayed()->nop(); // consider: relocate fetch of mark, above, into this DS
3010 andcc(Rmark, 2, G0);
3011 brx(Assembler::zero, false, Assembler::pt, LStacked);
3012 delayed()->nop();
3013
3014 // It's inflated
3015 // Conceptually we need a #loadstore|#storestore "release" MEMBAR before
3016 // the ST of 0 into _owner which releases the lock. This prevents loads
3017 // and stores within the critical section from reordering (floating)
3018 // past the store that releases the lock. But TSO is a strong memory model
3019 // and that particular flavor of barrier is a noop, so we can safely elide it.
3020 // Note that we use 1-0 locking by default for the inflated case. We
3021 // close the resultant (and rare) race by having contended threads in
3022 // monitorenter periodically poll _owner.
3023
3024 if (EmitSync & 1024) {
3025 // Emit code to check that _owner == Self
3026 // We could fold the _owner test into subsequent code more efficiently
3027 // than using a stand-alone check, but since _owner checking is off by
3028 // default we don't bother. We also might consider predicating the
3029 // _owner==Self check on Xcheck:jni or running on a debug build.
3030 ld_ptr(Address(Rmark, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)), Rscratch);
3031 orcc(Rscratch, G0, G0);
3032 brx(Assembler::notZero, false, Assembler::pn, done);
3033 delayed()->nop();
3034 }
3035
3036 if (EmitSync & 512) {
3037 // classic lock release code absent 1-0 locking
3038 // m->Owner = null;
3039 // membar #storeload
3040 // if (m->cxq|m->EntryList) == null goto Success
3041 // if (m->succ != null) goto Success
3042 // if CAS (&m->Owner,0,Self) != 0 goto Success
3043 // goto SlowPath
3044 ld_ptr(Address(Rmark, OM_OFFSET_NO_MONITOR_VALUE_TAG(recursions)), Rbox);
3045 orcc(Rbox, G0, G0);
3046 brx(Assembler::notZero, false, Assembler::pn, done);
3047 delayed()->nop();
3048 st_ptr(G0, Address(Rmark, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
3049 if (os::is_MP()) { membar(StoreLoad); }
3050 ld_ptr(Address(Rmark, OM_OFFSET_NO_MONITOR_VALUE_TAG(EntryList)), Rscratch);
3051 ld_ptr(Address(Rmark, OM_OFFSET_NO_MONITOR_VALUE_TAG(cxq)), Rbox);
3052 orcc(Rbox, Rscratch, G0);
3053 brx(Assembler::zero, false, Assembler::pt, done);
3054 delayed()->
3055 ld_ptr(Address(Rmark, OM_OFFSET_NO_MONITOR_VALUE_TAG(succ)), Rscratch);
3056 andcc(Rscratch, Rscratch, G0);
3057 brx(Assembler::notZero, false, Assembler::pt, done);
3058 delayed()->andcc(G0, G0, G0);
3059 add(Rmark, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner), Rmark);
3060 mov(G2_thread, Rscratch);
3061 cas_ptr(Rmark, G0, Rscratch);
3062 cmp(Rscratch, G0);
3063 // invert icc.zf and goto done
3064 brx(Assembler::notZero, false, Assembler::pt, done);
3065 delayed()->cmp(G0, G0);
3066 br(Assembler::always, false, Assembler::pt, done);
3067 delayed()->cmp(G0, 1);
3068 } else {
3069 // 1-0 form : avoids CAS and MEMBAR in the common case
3070 // Do not bother to ratify that m->Owner == Self.
3071 ld_ptr(Address(Rmark, OM_OFFSET_NO_MONITOR_VALUE_TAG(recursions)), Rbox);
3072 orcc(Rbox, G0, G0);
3073 brx(Assembler::notZero, false, Assembler::pn, done);
3074 delayed()->
3075 ld_ptr(Address(Rmark, OM_OFFSET_NO_MONITOR_VALUE_TAG(EntryList)), Rscratch);
3076 ld_ptr(Address(Rmark, OM_OFFSET_NO_MONITOR_VALUE_TAG(cxq)), Rbox);
3077 orcc(Rbox, Rscratch, G0);
3078 if (EmitSync & 16384) {
3079 // As an optional optimization, if (EntryList|cxq) != null and _succ is null then
3080 // we should transfer control directly to the slow-path.
3081 // This test makes the reacquire operation below very infrequent.
3082 // The logic is equivalent to :
3083 // if (cxq|EntryList) == null : Owner=null; goto Success
3084 // if succ == null : goto SlowPath
3085 // Owner=null; membar #storeload
3086 // if succ != null : goto Success
3087 // if CAS(&Owner,null,Self) != null goto Success
3088 // goto SlowPath
3089 brx(Assembler::zero, true, Assembler::pt, done);
3090 delayed()->
3091 st_ptr(G0, Address(Rmark, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
3092 ld_ptr(Address(Rmark, OM_OFFSET_NO_MONITOR_VALUE_TAG(succ)), Rscratch);
3093 andcc(Rscratch, Rscratch, G0) ;
3094 brx(Assembler::zero, false, Assembler::pt, done);
3095 delayed()->orcc(G0, 1, G0);
3096 st_ptr(G0, Address(Rmark, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
3097 } else {
3098 brx(Assembler::zero, false, Assembler::pt, done);
3099 delayed()->
3100 st_ptr(G0, Address(Rmark, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
3101 }
3102 if (os::is_MP()) { membar(StoreLoad); }
3103 // Check that _succ is (or remains) non-zero
3104 ld_ptr(Address(Rmark, OM_OFFSET_NO_MONITOR_VALUE_TAG(succ)), Rscratch);
3105 andcc(Rscratch, Rscratch, G0);
3106 brx(Assembler::notZero, false, Assembler::pt, done);
3107 delayed()->andcc(G0, G0, G0);
3108 add(Rmark, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner), Rmark);
3109 mov(G2_thread, Rscratch);
3110 cas_ptr(Rmark, G0, Rscratch);
3111 cmp(Rscratch, G0);
3112 // invert icc.zf and goto done
3113 // A slightly better v8+/v9 idiom would be the following:
3114 // movrnz Rscratch,1,Rscratch
3115 // ba done
3116 // xorcc Rscratch,1,G0
3117 // In v8+ mode the idiom would be valid IFF Rscratch was a G or O register
3118 brx(Assembler::notZero, false, Assembler::pt, done);
3119 delayed()->cmp(G0, G0);
3120 br(Assembler::always, false, Assembler::pt, done);
3121 delayed()->cmp(G0, 1);
3122 }
3123
3124 bind (LStacked);
3125 // Consider: we could replace the expensive CAS in the exit
3126 // path with a simple ST of the displaced mark value fetched from
3127 // the on-stack basiclock box. That admits a race where a thread T2
3128 // in the slow lock path -- inflating with monitor M -- could race a
3129 // thread T1 in the fast unlock path, resulting in a missed wakeup for T2.
3130 // More precisely T1 in the stack-lock unlock path could "stomp" the
3131 // inflated mark value M installed by T2, resulting in an orphan
3132 // object monitor M and T2 becoming stranded. We can remedy that situation
3133 // by having T2 periodically poll the object's mark word using timed wait
3134 // operations. If T2 discovers that a stomp has occurred it vacates
3135 // the monitor M and wakes any other threads stranded on the now-orphan M.
3136 // In addition the monitor scavenger, which performs deflation,
3137 // would also need to check for orpan monitors and stranded threads.
3138 //
3139 // Finally, inflation is also used when T2 needs to assign a hashCode
3140 // to O and O is stack-locked by T1. The "stomp" race could cause
3141 // an assigned hashCode value to be lost. We can avoid that condition
3142 // and provide the necessary hashCode stability invariants by ensuring
3143 // that hashCode generation is idempotent between copying GCs.
3144 // For example we could compute the hashCode of an object O as
3145 // O's heap address XOR some high quality RNG value that is refreshed
3146 // at GC-time. The monitor scavenger would install the hashCode
3147 // found in any orphan monitors. Again, the mechanism admits a
3148 // lost-update "stomp" WAW race but detects and recovers as needed.
3149 //
3150 // A prototype implementation showed excellent results, although
3151 // the scavenger and timeout code was rather involved.
3152
3153 cas_ptr(mark_addr.base(), Rbox, Rscratch);
3154 cmp(Rbox, Rscratch);
3155 // Intentional fall through into done ...
3156
3157 bind(done);
3158 }
3159
3160
3161
3162 void MacroAssembler::print_CPU_state() {
3163 // %%%%% need to implement this
3164 }
3165
3166 void MacroAssembler::verify_FPU(int stack_depth, const char* s) {
3167 // %%%%% need to implement this
3168 }
3169
3170 void MacroAssembler::push_IU_state() {
3171 // %%%%% need to implement this
3172 }
3173
3174
3175 void MacroAssembler::pop_IU_state() {
3176 // %%%%% need to implement this
3177 }
3178
3179
3180 void MacroAssembler::push_FPU_state() {
3181 // %%%%% need to implement this
3182 }
3183
3184
3185 void MacroAssembler::pop_FPU_state() {
3186 // %%%%% need to implement this
3187 }
3188
3189
3190 void MacroAssembler::push_CPU_state() {
3191 // %%%%% need to implement this
3192 }
3193
3194
3195 void MacroAssembler::pop_CPU_state() {
3196 // %%%%% need to implement this
3197 }
3198
3199
3200
3201 void MacroAssembler::verify_tlab() {
3202 #ifdef ASSERT
3203 if (UseTLAB && VerifyOops) {
3204 Label next, next2, ok;
3205 Register t1 = L0;
3206 Register t2 = L1;
3207 Register t3 = L2;
3208
3209 save_frame(0);
3210 ld_ptr(G2_thread, in_bytes(JavaThread::tlab_top_offset()), t1);
3211 ld_ptr(G2_thread, in_bytes(JavaThread::tlab_start_offset()), t2);
3212 or3(t1, t2, t3);
3213 cmp_and_br_short(t1, t2, Assembler::greaterEqual, Assembler::pn, next);
3214 STOP("assert(top >= start)");
3215 should_not_reach_here();
3216
3217 bind(next);
3218 ld_ptr(G2_thread, in_bytes(JavaThread::tlab_top_offset()), t1);
3219 ld_ptr(G2_thread, in_bytes(JavaThread::tlab_end_offset()), t2);
3220 or3(t3, t2, t3);
3221 cmp_and_br_short(t1, t2, Assembler::lessEqual, Assembler::pn, next2);
3222 STOP("assert(top <= end)");
3223 should_not_reach_here();
3224
3225 bind(next2);
3226 and3(t3, MinObjAlignmentInBytesMask, t3);
3227 cmp_and_br_short(t3, 0, Assembler::lessEqual, Assembler::pn, ok);
3228 STOP("assert(aligned)");
3229 should_not_reach_here();
3230
3231 bind(ok);
3232 restore();
3233 }
3234 #endif
3235 }
3236
3237
3238 void MacroAssembler::eden_allocate(
3239 Register obj, // result: pointer to object after successful allocation
3240 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise
3241 int con_size_in_bytes, // object size in bytes if known at compile time
3242 Register t1, // temp register
3243 Register t2, // temp register
3244 Label& slow_case // continuation point if fast allocation fails
3245 ){
3246 // make sure arguments make sense
3247 assert_different_registers(obj, var_size_in_bytes, t1, t2);
3248 assert(0 <= con_size_in_bytes && Assembler::is_simm13(con_size_in_bytes), "illegal object size");
3249 assert((con_size_in_bytes & MinObjAlignmentInBytesMask) == 0, "object size is not multiple of alignment");
3250
3251 if (!Universe::heap()->supports_inline_contig_alloc()) {
3252 // No allocation in the shared eden.
3253 ba(slow_case);
3254 delayed()->nop();
3255 } else {
3256 // get eden boundaries
3257 // note: we need both top & top_addr!
3258 const Register top_addr = t1;
3259 const Register end = t2;
3260
3261 CollectedHeap* ch = Universe::heap();
3262 set((intx)ch->top_addr(), top_addr);
3263 intx delta = (intx)ch->end_addr() - (intx)ch->top_addr();
3264 ld_ptr(top_addr, delta, end);
3265 ld_ptr(top_addr, 0, obj);
3266
3267 // try to allocate
3268 Label retry;
3269 bind(retry);
3270 #ifdef ASSERT
3271 // make sure eden top is properly aligned
3272 {
3273 Label L;
3274 btst(MinObjAlignmentInBytesMask, obj);
3275 br(Assembler::zero, false, Assembler::pt, L);
3276 delayed()->nop();
3277 STOP("eden top is not properly aligned");
3278 bind(L);
3279 }
3280 #endif // ASSERT
3281 const Register free = end;
3282 sub(end, obj, free); // compute amount of free space
3283 if (var_size_in_bytes->is_valid()) {
3284 // size is unknown at compile time
3285 cmp(free, var_size_in_bytes);
3286 br(Assembler::lessUnsigned, false, Assembler::pn, slow_case); // if there is not enough space go the slow case
3287 delayed()->add(obj, var_size_in_bytes, end);
3288 } else {
3289 // size is known at compile time
3290 cmp(free, con_size_in_bytes);
3291 br(Assembler::lessUnsigned, false, Assembler::pn, slow_case); // if there is not enough space go the slow case
3292 delayed()->add(obj, con_size_in_bytes, end);
3293 }
3294 // Compare obj with the value at top_addr; if still equal, swap the value of
3295 // end with the value at top_addr. If not equal, read the value at top_addr
3296 // into end.
3297 cas_ptr(top_addr, obj, end);
3298 // if someone beat us on the allocation, try again, otherwise continue
3299 cmp(obj, end);
3300 brx(Assembler::notEqual, false, Assembler::pn, retry);
3301 delayed()->mov(end, obj); // nop if successfull since obj == end
3302
3303 #ifdef ASSERT
3304 // make sure eden top is properly aligned
3305 {
3306 Label L;
3307 const Register top_addr = t1;
3308
3309 set((intx)ch->top_addr(), top_addr);
3310 ld_ptr(top_addr, 0, top_addr);
3311 btst(MinObjAlignmentInBytesMask, top_addr);
3312 br(Assembler::zero, false, Assembler::pt, L);
3313 delayed()->nop();
3314 STOP("eden top is not properly aligned");
3315 bind(L);
3316 }
3317 #endif // ASSERT
3318 }
3319 }
3320
3321
3322 void MacroAssembler::tlab_allocate(
3323 Register obj, // result: pointer to object after successful allocation
3324 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise
3325 int con_size_in_bytes, // object size in bytes if known at compile time
3326 Register t1, // temp register
3327 Label& slow_case // continuation point if fast allocation fails
3328 ){
3329 // make sure arguments make sense
3330 assert_different_registers(obj, var_size_in_bytes, t1);
3331 assert(0 <= con_size_in_bytes && is_simm13(con_size_in_bytes), "illegal object size");
3332 assert((con_size_in_bytes & MinObjAlignmentInBytesMask) == 0, "object size is not multiple of alignment");
3333
3334 const Register free = t1;
3335
3336 verify_tlab();
3337
3338 ld_ptr(G2_thread, in_bytes(JavaThread::tlab_top_offset()), obj);
3339
3340 // calculate amount of free space
3341 ld_ptr(G2_thread, in_bytes(JavaThread::tlab_end_offset()), free);
3342 sub(free, obj, free);
3343
3344 Label done;
3345 if (var_size_in_bytes == noreg) {
3346 cmp(free, con_size_in_bytes);
3347 } else {
3348 cmp(free, var_size_in_bytes);
3349 }
3350 br(Assembler::less, false, Assembler::pn, slow_case);
3351 // calculate the new top pointer
3352 if (var_size_in_bytes == noreg) {
3353 delayed()->add(obj, con_size_in_bytes, free);
3354 } else {
3355 delayed()->add(obj, var_size_in_bytes, free);
3356 }
3357
3358 bind(done);
3359
3360 #ifdef ASSERT
3361 // make sure new free pointer is properly aligned
3362 {
3363 Label L;
3364 btst(MinObjAlignmentInBytesMask, free);
3365 br(Assembler::zero, false, Assembler::pt, L);
3366 delayed()->nop();
3367 STOP("updated TLAB free is not properly aligned");
3368 bind(L);
3369 }
3370 #endif // ASSERT
3371
3372 // update the tlab top pointer
3373 st_ptr(free, G2_thread, in_bytes(JavaThread::tlab_top_offset()));
3374 verify_tlab();
3375 }
3376
3377
3378 void MacroAssembler::tlab_refill(Label& retry, Label& try_eden, Label& slow_case) {
3379 Register top = O0;
3380 Register t1 = G1;
3381 Register t2 = G3;
3382 Register t3 = O1;
3383 assert_different_registers(top, t1, t2, t3, G4, G5 /* preserve G4 and G5 */);
3384 Label do_refill, discard_tlab;
3385
3386 if (!Universe::heap()->supports_inline_contig_alloc()) {
3387 // No allocation in the shared eden.
3388 ba(slow_case);
3389 delayed()->nop();
3390 }
3391
3392 ld_ptr(G2_thread, in_bytes(JavaThread::tlab_top_offset()), top);
3393 ld_ptr(G2_thread, in_bytes(JavaThread::tlab_end_offset()), t1);
3394 ld_ptr(G2_thread, in_bytes(JavaThread::tlab_refill_waste_limit_offset()), t2);
3395
3396 // calculate amount of free space
3397 sub(t1, top, t1);
3398 srl_ptr(t1, LogHeapWordSize, t1);
3399
3400 // Retain tlab and allocate object in shared space if
3401 // the amount free in the tlab is too large to discard.
3402 cmp(t1, t2);
3403
3404 brx(Assembler::lessEqual, false, Assembler::pt, discard_tlab);
3405 // increment waste limit to prevent getting stuck on this slow path
3406 if (Assembler::is_simm13(ThreadLocalAllocBuffer::refill_waste_limit_increment())) {
3407 delayed()->add(t2, ThreadLocalAllocBuffer::refill_waste_limit_increment(), t2);
3408 } else {
3409 delayed()->nop();
3410 // set64 does not use the temp register if the given constant is 32 bit. So
3411 // we can just use any register; using G0 results in ignoring of the upper 32 bit
3412 // of that value.
3413 set64(ThreadLocalAllocBuffer::refill_waste_limit_increment(), t3, G0);
3414 add(t2, t3, t2);
3415 }
3416
3417 st_ptr(t2, G2_thread, in_bytes(JavaThread::tlab_refill_waste_limit_offset()));
3418 if (TLABStats) {
3419 // increment number of slow_allocations
3420 ld(G2_thread, in_bytes(JavaThread::tlab_slow_allocations_offset()), t2);
3421 add(t2, 1, t2);
3422 stw(t2, G2_thread, in_bytes(JavaThread::tlab_slow_allocations_offset()));
3423 }
3424 ba(try_eden);
3425 delayed()->nop();
3426
3427 bind(discard_tlab);
3428 if (TLABStats) {
3429 // increment number of refills
3430 ld(G2_thread, in_bytes(JavaThread::tlab_number_of_refills_offset()), t2);
3431 add(t2, 1, t2);
3432 stw(t2, G2_thread, in_bytes(JavaThread::tlab_number_of_refills_offset()));
3433 // accumulate wastage
3434 ld(G2_thread, in_bytes(JavaThread::tlab_fast_refill_waste_offset()), t2);
3435 add(t2, t1, t2);
3436 stw(t2, G2_thread, in_bytes(JavaThread::tlab_fast_refill_waste_offset()));
3437 }
3438
3439 // if tlab is currently allocated (top or end != null) then
3440 // fill [top, end + alignment_reserve) with array object
3441 br_null_short(top, Assembler::pn, do_refill);
3442
3443 set((intptr_t)markOopDesc::prototype()->copy_set_hash(0x2), t2);
3444 st_ptr(t2, top, oopDesc::mark_offset_in_bytes()); // set up the mark word
3445 // set klass to intArrayKlass
3446 sub(t1, typeArrayOopDesc::header_size(T_INT), t1);
3447 add(t1, ThreadLocalAllocBuffer::alignment_reserve(), t1);
3448 sll_ptr(t1, log2_intptr(HeapWordSize/sizeof(jint)), t1);
3449 st(t1, top, arrayOopDesc::length_offset_in_bytes());
3450 set((intptr_t)Universe::intArrayKlassObj_addr(), t2);
3451 ld_ptr(t2, 0, t2);
3452 // store klass last. concurrent gcs assumes klass length is valid if
3453 // klass field is not null.
3454 store_klass(t2, top);
3455 verify_oop(top);
3456
3457 ld_ptr(G2_thread, in_bytes(JavaThread::tlab_start_offset()), t1);
3458 sub(top, t1, t1); // size of tlab's allocated portion
3459 incr_allocated_bytes(t1, t2, t3);
3460
3461 // refill the tlab with an eden allocation
3462 bind(do_refill);
3463 ld_ptr(G2_thread, in_bytes(JavaThread::tlab_size_offset()), t1);
3464 sll_ptr(t1, LogHeapWordSize, t1);
3465 // allocate new tlab, address returned in top
3466 eden_allocate(top, t1, 0, t2, t3, slow_case);
3467
3468 st_ptr(top, G2_thread, in_bytes(JavaThread::tlab_start_offset()));
3469 st_ptr(top, G2_thread, in_bytes(JavaThread::tlab_top_offset()));
3470 #ifdef ASSERT
3471 // check that tlab_size (t1) is still valid
3472 {
3473 Label ok;
3474 ld_ptr(G2_thread, in_bytes(JavaThread::tlab_size_offset()), t2);
3475 sll_ptr(t2, LogHeapWordSize, t2);
3476 cmp_and_br_short(t1, t2, Assembler::equal, Assembler::pt, ok);
3477 STOP("assert(t1 == tlab_size)");
3478 should_not_reach_here();
3479
3480 bind(ok);
3481 }
3482 #endif // ASSERT
3483 add(top, t1, top); // t1 is tlab_size
3484 sub(top, ThreadLocalAllocBuffer::alignment_reserve_in_bytes(), top);
3485 st_ptr(top, G2_thread, in_bytes(JavaThread::tlab_end_offset()));
3486 verify_tlab();
3487 ba(retry);
3488 delayed()->nop();
3489 }
3490
3491 void MacroAssembler::incr_allocated_bytes(RegisterOrConstant size_in_bytes,
3492 Register t1, Register t2) {
3493 // Bump total bytes allocated by this thread
3494 assert(t1->is_global(), "must be global reg"); // so all 64 bits are saved on a context switch
3495 assert_different_registers(size_in_bytes.register_or_noreg(), t1, t2);
3496 // v8 support has gone the way of the dodo
3497 ldx(G2_thread, in_bytes(JavaThread::allocated_bytes_offset()), t1);
3498 add(t1, ensure_simm13_or_reg(size_in_bytes, t2), t1);
3499 stx(t1, G2_thread, in_bytes(JavaThread::allocated_bytes_offset()));
3500 }
3501
3502 Assembler::Condition MacroAssembler::negate_condition(Assembler::Condition cond) {
3503 switch (cond) {
3504 // Note some conditions are synonyms for others
3505 case Assembler::never: return Assembler::always;
3506 case Assembler::zero: return Assembler::notZero;
3507 case Assembler::lessEqual: return Assembler::greater;
3508 case Assembler::less: return Assembler::greaterEqual;
3509 case Assembler::lessEqualUnsigned: return Assembler::greaterUnsigned;
3510 case Assembler::lessUnsigned: return Assembler::greaterEqualUnsigned;
3511 case Assembler::negative: return Assembler::positive;
3512 case Assembler::overflowSet: return Assembler::overflowClear;
3513 case Assembler::always: return Assembler::never;
3514 case Assembler::notZero: return Assembler::zero;
3515 case Assembler::greater: return Assembler::lessEqual;
3516 case Assembler::greaterEqual: return Assembler::less;
3517 case Assembler::greaterUnsigned: return Assembler::lessEqualUnsigned;
3518 case Assembler::greaterEqualUnsigned: return Assembler::lessUnsigned;
3519 case Assembler::positive: return Assembler::negative;
3520 case Assembler::overflowClear: return Assembler::overflowSet;
3521 }
3522
3523 ShouldNotReachHere(); return Assembler::overflowClear;
3524 }
3525
3526 void MacroAssembler::cond_inc(Assembler::Condition cond, address counter_ptr,
3527 Register Rtmp1, Register Rtmp2 /*, Register Rtmp3, Register Rtmp4 */) {
3528 Condition negated_cond = negate_condition(cond);
3529 Label L;
3530 brx(negated_cond, false, Assembler::pt, L);
3531 delayed()->nop();
3532 inc_counter(counter_ptr, Rtmp1, Rtmp2);
3533 bind(L);
3534 }
3535
3536 void MacroAssembler::inc_counter(address counter_addr, Register Rtmp1, Register Rtmp2) {
3537 AddressLiteral addrlit(counter_addr);
3538 sethi(addrlit, Rtmp1); // Move hi22 bits into temporary register.
3539 Address addr(Rtmp1, addrlit.low10()); // Build an address with low10 bits.
3540 ld(addr, Rtmp2);
3541 inc(Rtmp2);
3542 st(Rtmp2, addr);
3543 }
3544
3545 void MacroAssembler::inc_counter(int* counter_addr, Register Rtmp1, Register Rtmp2) {
3546 inc_counter((address) counter_addr, Rtmp1, Rtmp2);
3547 }
3548
3549 SkipIfEqual::SkipIfEqual(
3550 MacroAssembler* masm, Register temp, const bool* flag_addr,
3551 Assembler::Condition condition) {
3552 _masm = masm;
3553 AddressLiteral flag(flag_addr);
3554 _masm->sethi(flag, temp);
3555 _masm->ldub(temp, flag.low10(), temp);
3556 _masm->tst(temp);
3557 _masm->br(condition, false, Assembler::pt, _label);
3558 _masm->delayed()->nop();
3559 }
3560
3561 SkipIfEqual::~SkipIfEqual() {
3562 _masm->bind(_label);
3563 }
3564
3565
3566 // Writes to stack successive pages until offset reached to check for
3567 // stack overflow + shadow pages. This clobbers tsp and scratch.
3568 void MacroAssembler::bang_stack_size(Register Rsize, Register Rtsp,
3569 Register Rscratch) {
3570 // Use stack pointer in temp stack pointer
3571 mov(SP, Rtsp);
3572
3573 // Bang stack for total size given plus stack shadow page size.
3574 // Bang one page at a time because a large size can overflow yellow and
3575 // red zones (the bang will fail but stack overflow handling can't tell that
3576 // it was a stack overflow bang vs a regular segv).
3577 int offset = os::vm_page_size();
3578 Register Roffset = Rscratch;
3579
3580 Label loop;
3581 bind(loop);
3582 set((-offset)+STACK_BIAS, Rscratch);
3583 st(G0, Rtsp, Rscratch);
3584 set(offset, Roffset);
3585 sub(Rsize, Roffset, Rsize);
3586 cmp(Rsize, G0);
3587 br(Assembler::greater, false, Assembler::pn, loop);
3588 delayed()->sub(Rtsp, Roffset, Rtsp);
3589
3590 // Bang down shadow pages too.
3591 // At this point, (tmp-0) is the last address touched, so don't
3592 // touch it again. (It was touched as (tmp-pagesize) but then tmp
3593 // was post-decremented.) Skip this address by starting at i=1, and
3594 // touch a few more pages below. N.B. It is important to touch all
3595 // the way down to and including i=StackShadowPages.
3596 for (int i = 1; i < JavaThread::stack_shadow_zone_size() / os::vm_page_size(); i++) {
3597 set((-i*offset)+STACK_BIAS, Rscratch);
3598 st(G0, Rtsp, Rscratch);
3599 }
3600 }
3601
3602 void MacroAssembler::reserved_stack_check() {
3603 // testing if reserved zone needs to be enabled
3604 Label no_reserved_zone_enabling;
3605
3606 ld_ptr(G2_thread, JavaThread::reserved_stack_activation_offset(), G4_scratch);
3607 cmp_and_brx_short(SP, G4_scratch, Assembler::lessUnsigned, Assembler::pt, no_reserved_zone_enabling);
3608
3609 call_VM_leaf(L0, CAST_FROM_FN_PTR(address, SharedRuntime::enable_stack_reserved_zone), G2_thread);
3610
3611 AddressLiteral stub(StubRoutines::throw_delayed_StackOverflowError_entry());
3612 jump_to(stub, G4_scratch);
3613 delayed()->restore();
3614
3615 should_not_reach_here();
3616
3617 bind(no_reserved_zone_enabling);
3618 }
3619
3620 ///////////////////////////////////////////////////////////////////////////////////
3621 #if INCLUDE_ALL_GCS
3622
3623 static address satb_log_enqueue_with_frame = NULL;
3624 static u_char* satb_log_enqueue_with_frame_end = NULL;
3625
3626 static address satb_log_enqueue_frameless = NULL;
3627 static u_char* satb_log_enqueue_frameless_end = NULL;
3628
3629 static int EnqueueCodeSize = 128 DEBUG_ONLY( + 256); // Instructions?
3630
3631 static void generate_satb_log_enqueue(bool with_frame) {
3632 BufferBlob* bb = BufferBlob::create("enqueue_with_frame", EnqueueCodeSize);
3633 CodeBuffer buf(bb);
3634 MacroAssembler masm(&buf);
3635
3636 #define __ masm.
3637
3638 address start = __ pc();
3639 Register pre_val;
3640
3641 Label refill, restart;
3642 if (with_frame) {
3643 __ save_frame(0);
3644 pre_val = I0; // Was O0 before the save.
3645 } else {
3646 pre_val = O0;
3647 }
3648
3649 int satb_q_index_byte_offset =
3650 in_bytes(JavaThread::satb_mark_queue_offset() +
3651 SATBMarkQueue::byte_offset_of_index());
3652
3653 int satb_q_buf_byte_offset =
3654 in_bytes(JavaThread::satb_mark_queue_offset() +
3655 SATBMarkQueue::byte_offset_of_buf());
3656
3657 assert(in_bytes(SATBMarkQueue::byte_width_of_index()) == sizeof(intptr_t) &&
3658 in_bytes(SATBMarkQueue::byte_width_of_buf()) == sizeof(intptr_t),
3659 "check sizes in assembly below");
3660
3661 __ bind(restart);
3662
3663 // Load the index into the SATB buffer. SATBMarkQueue::_index is a size_t
3664 // so ld_ptr is appropriate.
3665 __ ld_ptr(G2_thread, satb_q_index_byte_offset, L0);
3666
3667 // index == 0?
3668 __ cmp_and_brx_short(L0, G0, Assembler::equal, Assembler::pn, refill);
3669
3670 __ ld_ptr(G2_thread, satb_q_buf_byte_offset, L1);
3671 __ sub(L0, oopSize, L0);
3672
3673 __ st_ptr(pre_val, L1, L0); // [_buf + index] := I0
3674 if (!with_frame) {
3675 // Use return-from-leaf
3676 __ retl();
3677 __ delayed()->st_ptr(L0, G2_thread, satb_q_index_byte_offset);
3678 } else {
3679 // Not delayed.
3680 __ st_ptr(L0, G2_thread, satb_q_index_byte_offset);
3681 }
3682 if (with_frame) {
3683 __ ret();
3684 __ delayed()->restore();
3685 }
3686 __ bind(refill);
3687
3688 address handle_zero =
3689 CAST_FROM_FN_PTR(address,
3690 &SATBMarkQueueSet::handle_zero_index_for_thread);
3691 // This should be rare enough that we can afford to save all the
3692 // scratch registers that the calling context might be using.
3693 __ mov(G1_scratch, L0);
3694 __ mov(G3_scratch, L1);
3695 __ mov(G4, L2);
3696 // We need the value of O0 above (for the write into the buffer), so we
3697 // save and restore it.
3698 __ mov(O0, L3);
3699 // Since the call will overwrite O7, we save and restore that, as well.
3700 __ mov(O7, L4);
3701 __ call_VM_leaf(L5, handle_zero, G2_thread);
3702 __ mov(L0, G1_scratch);
3703 __ mov(L1, G3_scratch);
3704 __ mov(L2, G4);
3705 __ mov(L3, O0);
3706 __ br(Assembler::always, /*annul*/false, Assembler::pt, restart);
3707 __ delayed()->mov(L4, O7);
3708
3709 if (with_frame) {
3710 satb_log_enqueue_with_frame = start;
3711 satb_log_enqueue_with_frame_end = __ pc();
3712 } else {
3713 satb_log_enqueue_frameless = start;
3714 satb_log_enqueue_frameless_end = __ pc();
3715 }
3716
3717 #undef __
3718 }
3719
3720 static inline void generate_satb_log_enqueue_if_necessary(bool with_frame) {
3721 if (with_frame) {
3722 if (satb_log_enqueue_with_frame == 0) {
3723 generate_satb_log_enqueue(with_frame);
3724 assert(satb_log_enqueue_with_frame != 0, "postcondition.");
3725 }
3726 } else {
3727 if (satb_log_enqueue_frameless == 0) {
3728 generate_satb_log_enqueue(with_frame);
3729 assert(satb_log_enqueue_frameless != 0, "postcondition.");
3730 }
3731 }
3732 }
3733
3734 void MacroAssembler::g1_write_barrier_pre(Register obj,
3735 Register index,
3736 int offset,
3737 Register pre_val,
3738 Register tmp,
3739 bool preserve_o_regs) {
3740 Label filtered;
3741
3742 if (obj == noreg) {
3743 // We are not loading the previous value so make
3744 // sure that we don't trash the value in pre_val
3745 // with the code below.
3746 assert_different_registers(pre_val, tmp);
3747 } else {
3748 // We will be loading the previous value
3749 // in this code so...
3750 assert(offset == 0 || index == noreg, "choose one");
3751 assert(pre_val == noreg, "check this code");
3752 }
3753
3754 // Is marking active?
3755 if (in_bytes(SATBMarkQueue::byte_width_of_active()) == 4) {
3756 ld(G2,
3757 in_bytes(JavaThread::satb_mark_queue_offset() +
3758 SATBMarkQueue::byte_offset_of_active()),
3759 tmp);
3760 } else {
3761 guarantee(in_bytes(SATBMarkQueue::byte_width_of_active()) == 1,
3762 "Assumption");
3763 ldsb(G2,
3764 in_bytes(JavaThread::satb_mark_queue_offset() +
3765 SATBMarkQueue::byte_offset_of_active()),
3766 tmp);
3767 }
3768
3769 // Is marking active?
3770 cmp_and_br_short(tmp, G0, Assembler::equal, Assembler::pt, filtered);
3771
3772 // Do we need to load the previous value?
3773 if (obj != noreg) {
3774 // Load the previous value...
3775 if (index == noreg) {
3776 if (Assembler::is_simm13(offset)) {
3777 load_heap_oop(obj, offset, tmp);
3778 } else {
3779 set(offset, tmp);
3780 load_heap_oop(obj, tmp, tmp);
3781 }
3782 } else {
3783 load_heap_oop(obj, index, tmp);
3784 }
3785 // Previous value has been loaded into tmp
3786 pre_val = tmp;
3787 }
3788
3789 assert(pre_val != noreg, "must have a real register");
3790
3791 // Is the previous value null?
3792 cmp_and_brx_short(pre_val, G0, Assembler::equal, Assembler::pt, filtered);
3793
3794 // OK, it's not filtered, so we'll need to call enqueue. In the normal
3795 // case, pre_val will be a scratch G-reg, but there are some cases in
3796 // which it's an O-reg. In the first case, do a normal call. In the
3797 // latter, do a save here and call the frameless version.
3798
3799 guarantee(pre_val->is_global() || pre_val->is_out(),
3800 "Or we need to think harder.");
3801
3802 if (pre_val->is_global() && !preserve_o_regs) {
3803 generate_satb_log_enqueue_if_necessary(true); // with frame
3804
3805 call(satb_log_enqueue_with_frame);
3806 delayed()->mov(pre_val, O0);
3807 } else {
3808 generate_satb_log_enqueue_if_necessary(false); // frameless
3809
3810 save_frame(0);
3811 call(satb_log_enqueue_frameless);
3812 delayed()->mov(pre_val->after_save(), O0);
3813 restore();
3814 }
3815
3816 bind(filtered);
3817 }
3818
3819 static address dirty_card_log_enqueue = 0;
3820 static u_char* dirty_card_log_enqueue_end = 0;
3821
3822 // This gets to assume that o0 contains the object address.
3823 static void generate_dirty_card_log_enqueue(jbyte* byte_map_base) {
3824 BufferBlob* bb = BufferBlob::create("dirty_card_enqueue", EnqueueCodeSize*2);
3825 CodeBuffer buf(bb);
3826 MacroAssembler masm(&buf);
3827 #define __ masm.
3828 address start = __ pc();
3829
3830 Label not_already_dirty, restart, refill, young_card;
3831
3832 #ifdef _LP64
3833 __ srlx(O0, CardTableModRefBS::card_shift, O0);
3834 #else
3835 __ srl(O0, CardTableModRefBS::card_shift, O0);
3836 #endif
3837 AddressLiteral addrlit(byte_map_base);
3838 __ set(addrlit, O1); // O1 := <card table base>
3839 __ ldub(O0, O1, O2); // O2 := [O0 + O1]
3840
3841 __ cmp_and_br_short(O2, G1SATBCardTableModRefBS::g1_young_card_val(), Assembler::equal, Assembler::pt, young_card);
3842
3843 __ membar(Assembler::Membar_mask_bits(Assembler::StoreLoad));
3844 __ ldub(O0, O1, O2); // O2 := [O0 + O1]
3845
3846 assert(CardTableModRefBS::dirty_card_val() == 0, "otherwise check this code");
3847 __ cmp_and_br_short(O2, G0, Assembler::notEqual, Assembler::pt, not_already_dirty);
3848
3849 __ bind(young_card);
3850 // We didn't take the branch, so we're already dirty: return.
3851 // Use return-from-leaf
3852 __ retl();
3853 __ delayed()->nop();
3854
3855 // Not dirty.
3856 __ bind(not_already_dirty);
3857
3858 // Get O0 + O1 into a reg by itself
3859 __ add(O0, O1, O3);
3860
3861 // First, dirty it.
3862 __ stb(G0, O3, G0); // [cardPtr] := 0 (i.e., dirty).
3863
3864 int dirty_card_q_index_byte_offset =
3865 in_bytes(JavaThread::dirty_card_queue_offset() +
3866 DirtyCardQueue::byte_offset_of_index());
3867 int dirty_card_q_buf_byte_offset =
3868 in_bytes(JavaThread::dirty_card_queue_offset() +
3869 DirtyCardQueue::byte_offset_of_buf());
3870 __ bind(restart);
3871
3872 // Load the index into the update buffer. DirtyCardQueue::_index is
3873 // a size_t so ld_ptr is appropriate here.
3874 __ ld_ptr(G2_thread, dirty_card_q_index_byte_offset, L0);
3875
3876 // index == 0?
3877 __ cmp_and_brx_short(L0, G0, Assembler::equal, Assembler::pn, refill);
3878
3879 __ ld_ptr(G2_thread, dirty_card_q_buf_byte_offset, L1);
3880 __ sub(L0, oopSize, L0);
3881
3882 __ st_ptr(O3, L1, L0); // [_buf + index] := I0
3883 // Use return-from-leaf
3884 __ retl();
3885 __ delayed()->st_ptr(L0, G2_thread, dirty_card_q_index_byte_offset);
3886
3887 __ bind(refill);
3888 address handle_zero =
3889 CAST_FROM_FN_PTR(address,
3890 &DirtyCardQueueSet::handle_zero_index_for_thread);
3891 // This should be rare enough that we can afford to save all the
3892 // scratch registers that the calling context might be using.
3893 __ mov(G1_scratch, L3);
3894 __ mov(G3_scratch, L5);
3895 // We need the value of O3 above (for the write into the buffer), so we
3896 // save and restore it.
3897 __ mov(O3, L6);
3898 // Since the call will overwrite O7, we save and restore that, as well.
3899 __ mov(O7, L4);
3900
3901 __ call_VM_leaf(L7_thread_cache, handle_zero, G2_thread);
3902 __ mov(L3, G1_scratch);
3903 __ mov(L5, G3_scratch);
3904 __ mov(L6, O3);
3905 __ br(Assembler::always, /*annul*/false, Assembler::pt, restart);
3906 __ delayed()->mov(L4, O7);
3907
3908 dirty_card_log_enqueue = start;
3909 dirty_card_log_enqueue_end = __ pc();
3910 // XXX Should have a guarantee here about not going off the end!
3911 // Does it already do so? Do an experiment...
3912
3913 #undef __
3914
3915 }
3916
3917 static inline void
3918 generate_dirty_card_log_enqueue_if_necessary(jbyte* byte_map_base) {
3919 if (dirty_card_log_enqueue == 0) {
3920 generate_dirty_card_log_enqueue(byte_map_base);
3921 assert(dirty_card_log_enqueue != 0, "postcondition.");
3922 }
3923 }
3924
3925
3926 void MacroAssembler::g1_write_barrier_post(Register store_addr, Register new_val, Register tmp) {
3927
3928 Label filtered;
3929 MacroAssembler* post_filter_masm = this;
3930
3931 if (new_val == G0) return;
3932
3933 G1SATBCardTableLoggingModRefBS* bs =
3934 barrier_set_cast<G1SATBCardTableLoggingModRefBS>(Universe::heap()->barrier_set());
3935
3936 if (G1RSBarrierRegionFilter) {
3937 xor3(store_addr, new_val, tmp);
3938 #ifdef _LP64
3939 srlx(tmp, HeapRegion::LogOfHRGrainBytes, tmp);
3940 #else
3941 srl(tmp, HeapRegion::LogOfHRGrainBytes, tmp);
3942 #endif
3943
3944 // XXX Should I predict this taken or not? Does it matter?
3945 cmp_and_brx_short(tmp, G0, Assembler::equal, Assembler::pt, filtered);
3946 }
3947
3948 // If the "store_addr" register is an "in" or "local" register, move it to
3949 // a scratch reg so we can pass it as an argument.
3950 bool use_scr = !(store_addr->is_global() || store_addr->is_out());
3951 // Pick a scratch register different from "tmp".
3952 Register scr = (tmp == G1_scratch ? G3_scratch : G1_scratch);
3953 // Make sure we use up the delay slot!
3954 if (use_scr) {
3955 post_filter_masm->mov(store_addr, scr);
3956 } else {
3957 post_filter_masm->nop();
3958 }
3959 generate_dirty_card_log_enqueue_if_necessary(bs->byte_map_base);
3960 save_frame(0);
3961 call(dirty_card_log_enqueue);
3962 if (use_scr) {
3963 delayed()->mov(scr, O0);
3964 } else {
3965 delayed()->mov(store_addr->after_save(), O0);
3966 }
3967 restore();
3968
3969 bind(filtered);
3970 }
3971
3972 #endif // INCLUDE_ALL_GCS
3973 ///////////////////////////////////////////////////////////////////////////////////
3974
3975 void MacroAssembler::card_write_barrier_post(Register store_addr, Register new_val, Register tmp) {
3976 // If we're writing constant NULL, we can skip the write barrier.
3977 if (new_val == G0) return;
3978 CardTableModRefBS* bs =
3979 barrier_set_cast<CardTableModRefBS>(Universe::heap()->barrier_set());
3980 assert(bs->kind() == BarrierSet::CardTableForRS ||
3981 bs->kind() == BarrierSet::CardTableExtension, "wrong barrier");
3982 card_table_write(bs->byte_map_base, tmp, store_addr);
3983 }
3984
3985 void MacroAssembler::load_klass(Register src_oop, Register klass) {
3986 // The number of bytes in this code is used by
3987 // MachCallDynamicJavaNode::ret_addr_offset()
3988 // if this changes, change that.
3989 if (UseCompressedClassPointers) {
3990 lduw(src_oop, oopDesc::klass_offset_in_bytes(), klass);
3991 decode_klass_not_null(klass);
3992 } else {
3993 ld_ptr(src_oop, oopDesc::klass_offset_in_bytes(), klass);
3994 }
3995 }
3996
3997 void MacroAssembler::store_klass(Register klass, Register dst_oop) {
3998 if (UseCompressedClassPointers) {
3999 assert(dst_oop != klass, "not enough registers");
4000 encode_klass_not_null(klass);
4001 st(klass, dst_oop, oopDesc::klass_offset_in_bytes());
4002 } else {
4003 st_ptr(klass, dst_oop, oopDesc::klass_offset_in_bytes());
4004 }
4005 }
4006
4007 void MacroAssembler::store_klass_gap(Register s, Register d) {
4008 if (UseCompressedClassPointers) {
4009 assert(s != d, "not enough registers");
4010 st(s, d, oopDesc::klass_gap_offset_in_bytes());
4011 }
4012 }
4013
4014 void MacroAssembler::load_heap_oop(const Address& s, Register d) {
4015 if (UseCompressedOops) {
4016 lduw(s, d);
4017 decode_heap_oop(d);
4018 } else {
4019 ld_ptr(s, d);
4020 }
4021 }
4022
4023 void MacroAssembler::load_heap_oop(Register s1, Register s2, Register d) {
4024 if (UseCompressedOops) {
4025 lduw(s1, s2, d);
4026 decode_heap_oop(d, d);
4027 } else {
4028 ld_ptr(s1, s2, d);
4029 }
4030 }
4031
4032 void MacroAssembler::load_heap_oop(Register s1, int simm13a, Register d) {
4033 if (UseCompressedOops) {
4034 lduw(s1, simm13a, d);
4035 decode_heap_oop(d, d);
4036 } else {
4037 ld_ptr(s1, simm13a, d);
4038 }
4039 }
4040
4041 void MacroAssembler::load_heap_oop(Register s1, RegisterOrConstant s2, Register d) {
4042 if (s2.is_constant()) load_heap_oop(s1, s2.as_constant(), d);
4043 else load_heap_oop(s1, s2.as_register(), d);
4044 }
4045
4046 void MacroAssembler::store_heap_oop(Register d, Register s1, Register s2) {
4047 if (UseCompressedOops) {
4048 assert(s1 != d && s2 != d, "not enough registers");
4049 encode_heap_oop(d);
4050 st(d, s1, s2);
4051 } else {
4052 st_ptr(d, s1, s2);
4053 }
4054 }
4055
4056 void MacroAssembler::store_heap_oop(Register d, Register s1, int simm13a) {
4057 if (UseCompressedOops) {
4058 assert(s1 != d, "not enough registers");
4059 encode_heap_oop(d);
4060 st(d, s1, simm13a);
4061 } else {
4062 st_ptr(d, s1, simm13a);
4063 }
4064 }
4065
4066 void MacroAssembler::store_heap_oop(Register d, const Address& a, int offset) {
4067 if (UseCompressedOops) {
4068 assert(a.base() != d, "not enough registers");
4069 encode_heap_oop(d);
4070 st(d, a, offset);
4071 } else {
4072 st_ptr(d, a, offset);
4073 }
4074 }
4075
4076
4077 void MacroAssembler::encode_heap_oop(Register src, Register dst) {
4078 assert (UseCompressedOops, "must be compressed");
4079 assert (Universe::heap() != NULL, "java heap should be initialized");
4080 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
4081 verify_oop(src);
4082 if (Universe::narrow_oop_base() == NULL) {
4083 srlx(src, LogMinObjAlignmentInBytes, dst);
4084 return;
4085 }
4086 Label done;
4087 if (src == dst) {
4088 // optimize for frequent case src == dst
4089 bpr(rc_nz, true, Assembler::pt, src, done);
4090 delayed() -> sub(src, G6_heapbase, dst); // annuled if not taken
4091 bind(done);
4092 srlx(src, LogMinObjAlignmentInBytes, dst);
4093 } else {
4094 bpr(rc_z, false, Assembler::pn, src, done);
4095 delayed() -> mov(G0, dst);
4096 // could be moved before branch, and annulate delay,
4097 // but may add some unneeded work decoding null
4098 sub(src, G6_heapbase, dst);
4099 srlx(dst, LogMinObjAlignmentInBytes, dst);
4100 bind(done);
4101 }
4102 }
4103
4104
4105 void MacroAssembler::encode_heap_oop_not_null(Register r) {
4106 assert (UseCompressedOops, "must be compressed");
4107 assert (Universe::heap() != NULL, "java heap should be initialized");
4108 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
4109 verify_oop(r);
4110 if (Universe::narrow_oop_base() != NULL)
4111 sub(r, G6_heapbase, r);
4112 srlx(r, LogMinObjAlignmentInBytes, r);
4113 }
4114
4115 void MacroAssembler::encode_heap_oop_not_null(Register src, Register dst) {
4116 assert (UseCompressedOops, "must be compressed");
4117 assert (Universe::heap() != NULL, "java heap should be initialized");
4118 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
4119 verify_oop(src);
4120 if (Universe::narrow_oop_base() == NULL) {
4121 srlx(src, LogMinObjAlignmentInBytes, dst);
4122 } else {
4123 sub(src, G6_heapbase, dst);
4124 srlx(dst, LogMinObjAlignmentInBytes, dst);
4125 }
4126 }
4127
4128 // Same algorithm as oops.inline.hpp decode_heap_oop.
4129 void MacroAssembler::decode_heap_oop(Register src, Register dst) {
4130 assert (UseCompressedOops, "must be compressed");
4131 assert (Universe::heap() != NULL, "java heap should be initialized");
4132 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
4133 sllx(src, LogMinObjAlignmentInBytes, dst);
4134 if (Universe::narrow_oop_base() != NULL) {
4135 Label done;
4136 bpr(rc_nz, true, Assembler::pt, dst, done);
4137 delayed() -> add(dst, G6_heapbase, dst); // annuled if not taken
4138 bind(done);
4139 }
4140 verify_oop(dst);
4141 }
4142
4143 void MacroAssembler::decode_heap_oop_not_null(Register r) {
4144 // Do not add assert code to this unless you change vtableStubs_sparc.cpp
4145 // pd_code_size_limit.
4146 // Also do not verify_oop as this is called by verify_oop.
4147 assert (UseCompressedOops, "must be compressed");
4148 assert (Universe::heap() != NULL, "java heap should be initialized");
4149 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
4150 sllx(r, LogMinObjAlignmentInBytes, r);
4151 if (Universe::narrow_oop_base() != NULL)
4152 add(r, G6_heapbase, r);
4153 }
4154
4155 void MacroAssembler::decode_heap_oop_not_null(Register src, Register dst) {
4156 // Do not add assert code to this unless you change vtableStubs_sparc.cpp
4157 // pd_code_size_limit.
4158 // Also do not verify_oop as this is called by verify_oop.
4159 assert (UseCompressedOops, "must be compressed");
4160 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
4161 sllx(src, LogMinObjAlignmentInBytes, dst);
4162 if (Universe::narrow_oop_base() != NULL)
4163 add(dst, G6_heapbase, dst);
4164 }
4165
4166 void MacroAssembler::encode_klass_not_null(Register r) {
4167 assert (UseCompressedClassPointers, "must be compressed");
4168 if (Universe::narrow_klass_base() != NULL) {
4169 assert(r != G6_heapbase, "bad register choice");
4170 set((intptr_t)Universe::narrow_klass_base(), G6_heapbase);
4171 sub(r, G6_heapbase, r);
4172 if (Universe::narrow_klass_shift() != 0) {
4173 assert (LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong");
4174 srlx(r, LogKlassAlignmentInBytes, r);
4175 }
4176 reinit_heapbase();
4177 } else {
4178 assert (LogKlassAlignmentInBytes == Universe::narrow_klass_shift() || Universe::narrow_klass_shift() == 0, "decode alg wrong");
4179 srlx(r, Universe::narrow_klass_shift(), r);
4180 }
4181 }
4182
4183 void MacroAssembler::encode_klass_not_null(Register src, Register dst) {
4184 if (src == dst) {
4185 encode_klass_not_null(src);
4186 } else {
4187 assert (UseCompressedClassPointers, "must be compressed");
4188 if (Universe::narrow_klass_base() != NULL) {
4189 set((intptr_t)Universe::narrow_klass_base(), dst);
4190 sub(src, dst, dst);
4191 if (Universe::narrow_klass_shift() != 0) {
4192 srlx(dst, LogKlassAlignmentInBytes, dst);
4193 }
4194 } else {
4195 // shift src into dst
4196 assert (LogKlassAlignmentInBytes == Universe::narrow_klass_shift() || Universe::narrow_klass_shift() == 0, "decode alg wrong");
4197 srlx(src, Universe::narrow_klass_shift(), dst);
4198 }
4199 }
4200 }
4201
4202 // Function instr_size_for_decode_klass_not_null() counts the instructions
4203 // generated by decode_klass_not_null() and reinit_heapbase(). Hence, if
4204 // the instructions they generate change, then this method needs to be updated.
4205 int MacroAssembler::instr_size_for_decode_klass_not_null() {
4206 assert (UseCompressedClassPointers, "only for compressed klass ptrs");
4207 int num_instrs = 1; // shift src,dst or add
4208 if (Universe::narrow_klass_base() != NULL) {
4209 // set + add + set
4210 num_instrs += insts_for_internal_set((intptr_t)Universe::narrow_klass_base()) +
4211 insts_for_internal_set((intptr_t)Universe::narrow_ptrs_base());
4212 if (Universe::narrow_klass_shift() != 0) {
4213 num_instrs += 1; // sllx
4214 }
4215 }
4216 return num_instrs * BytesPerInstWord;
4217 }
4218
4219 // !!! If the instructions that get generated here change then function
4220 // instr_size_for_decode_klass_not_null() needs to get updated.
4221 void MacroAssembler::decode_klass_not_null(Register r) {
4222 // Do not add assert code to this unless you change vtableStubs_sparc.cpp
4223 // pd_code_size_limit.
4224 assert (UseCompressedClassPointers, "must be compressed");
4225 if (Universe::narrow_klass_base() != NULL) {
4226 assert(r != G6_heapbase, "bad register choice");
4227 set((intptr_t)Universe::narrow_klass_base(), G6_heapbase);
4228 if (Universe::narrow_klass_shift() != 0)
4229 sllx(r, LogKlassAlignmentInBytes, r);
4230 add(r, G6_heapbase, r);
4231 reinit_heapbase();
4232 } else {
4233 assert (LogKlassAlignmentInBytes == Universe::narrow_klass_shift() || Universe::narrow_klass_shift() == 0, "decode alg wrong");
4234 sllx(r, Universe::narrow_klass_shift(), r);
4235 }
4236 }
4237
4238 void MacroAssembler::decode_klass_not_null(Register src, Register dst) {
4239 if (src == dst) {
4240 decode_klass_not_null(src);
4241 } else {
4242 // Do not add assert code to this unless you change vtableStubs_sparc.cpp
4243 // pd_code_size_limit.
4244 assert (UseCompressedClassPointers, "must be compressed");
4245 if (Universe::narrow_klass_base() != NULL) {
4246 if (Universe::narrow_klass_shift() != 0) {
4247 assert((src != G6_heapbase) && (dst != G6_heapbase), "bad register choice");
4248 set((intptr_t)Universe::narrow_klass_base(), G6_heapbase);
4249 sllx(src, LogKlassAlignmentInBytes, dst);
4250 add(dst, G6_heapbase, dst);
4251 reinit_heapbase();
4252 } else {
4253 set((intptr_t)Universe::narrow_klass_base(), dst);
4254 add(src, dst, dst);
4255 }
4256 } else {
4257 // shift/mov src into dst.
4258 assert (LogKlassAlignmentInBytes == Universe::narrow_klass_shift() || Universe::narrow_klass_shift() == 0, "decode alg wrong");
4259 sllx(src, Universe::narrow_klass_shift(), dst);
4260 }
4261 }
4262 }
4263
4264 void MacroAssembler::reinit_heapbase() {
4265 if (UseCompressedOops || UseCompressedClassPointers) {
4266 if (Universe::heap() != NULL) {
4267 set((intptr_t)Universe::narrow_ptrs_base(), G6_heapbase);
4268 } else {
4269 AddressLiteral base(Universe::narrow_ptrs_base_addr());
4270 load_ptr_contents(base, G6_heapbase);
4271 }
4272 }
4273 }
4274
4275 #ifdef COMPILER2
4276
4277 // Compress char[] to byte[] by compressing 16 bytes at once. Return 0 on failure.
4278 void MacroAssembler::string_compress_16(Register src, Register dst, Register cnt, Register result,
4279 Register tmp1, Register tmp2, Register tmp3, Register tmp4,
4280 FloatRegister ftmp1, FloatRegister ftmp2, FloatRegister ftmp3, Label& Ldone) {
4281 Label Lloop, Lslow;
4282 assert(UseVIS >= 3, "VIS3 is required");
4283 assert_different_registers(src, dst, cnt, tmp1, tmp2, tmp3, tmp4, result);
4284 assert_different_registers(ftmp1, ftmp2, ftmp3);
4285
4286 // Check if cnt >= 8 (= 16 bytes)
4287 cmp(cnt, 8);
4288 br(Assembler::less, false, Assembler::pn, Lslow);
4289 delayed()->mov(cnt, result); // copy count
4290
4291 // Check for 8-byte alignment of src and dst
4292 or3(src, dst, tmp1);
4293 andcc(tmp1, 7, G0);
4294 br(Assembler::notZero, false, Assembler::pn, Lslow);
4295 delayed()->nop();
4296
4297 // Set mask for bshuffle instruction
4298 Register mask = tmp4;
4299 set(0x13579bdf, mask);
4300 bmask(mask, G0, G0);
4301
4302 // Set mask to 0xff00 ff00 ff00 ff00 to check for non-latin1 characters
4303 Assembler::sethi(0xff00fc00, mask); // mask = 0x0000 0000 ff00 fc00
4304 add(mask, 0x300, mask); // mask = 0x0000 0000 ff00 ff00
4305 sllx(mask, 32, tmp1); // tmp1 = 0xff00 ff00 0000 0000
4306 or3(mask, tmp1, mask); // mask = 0xff00 ff00 ff00 ff00
4307
4308 // Load first 8 bytes
4309 ldx(src, 0, tmp1);
4310
4311 bind(Lloop);
4312 // Load next 8 bytes
4313 ldx(src, 8, tmp2);
4314
4315 // Check for non-latin1 character by testing if the most significant byte of a char is set.
4316 // Although we have to move the data between integer and floating point registers, this is
4317 // still faster than the corresponding VIS instructions (ford/fand/fcmpd).
4318 or3(tmp1, tmp2, tmp3);
4319 btst(tmp3, mask);
4320 // annul zeroing if branch is not taken to preserve original count
4321 brx(Assembler::notZero, true, Assembler::pn, Ldone);
4322 delayed()->mov(G0, result); // 0 - failed
4323
4324 // Move bytes into float register
4325 movxtod(tmp1, ftmp1);
4326 movxtod(tmp2, ftmp2);
4327
4328 // Compress by copying one byte per char from ftmp1 and ftmp2 to ftmp3
4329 bshuffle(ftmp1, ftmp2, ftmp3);
4330 stf(FloatRegisterImpl::D, ftmp3, dst, 0);
4331
4332 // Increment addresses and decrement count
4333 inc(src, 16);
4334 inc(dst, 8);
4335 dec(cnt, 8);
4336
4337 cmp(cnt, 8);
4338 // annul LDX if branch is not taken to prevent access past end of string
4339 br(Assembler::greaterEqual, true, Assembler::pt, Lloop);
4340 delayed()->ldx(src, 0, tmp1);
4341
4342 // Fallback to slow version
4343 bind(Lslow);
4344 }
4345
4346 // Compress char[] to byte[]. Return 0 on failure.
4347 void MacroAssembler::string_compress(Register src, Register dst, Register cnt, Register result, Register tmp, Label& Ldone) {
4348 Label Lloop;
4349 assert_different_registers(src, dst, cnt, tmp, result);
4350
4351 lduh(src, 0, tmp);
4352
4353 bind(Lloop);
4354 inc(src, sizeof(jchar));
4355 cmp(tmp, 0xff);
4356 // annul zeroing if branch is not taken to preserve original count
4357 br(Assembler::greater, true, Assembler::pn, Ldone); // don't check xcc
4358 delayed()->mov(G0, result); // 0 - failed
4359 deccc(cnt);
4360 stb(tmp, dst, 0);
4361 inc(dst);
4362 // annul LDUH if branch is not taken to prevent access past end of string
4363 br(Assembler::notZero, true, Assembler::pt, Lloop);
4364 delayed()->lduh(src, 0, tmp); // hoisted
4365 }
4366
4367 // Inflate byte[] to char[] by inflating 16 bytes at once.
4368 void MacroAssembler::string_inflate_16(Register src, Register dst, Register cnt, Register tmp,
4369 FloatRegister ftmp1, FloatRegister ftmp2, FloatRegister ftmp3, FloatRegister ftmp4, Label& Ldone) {
4370 Label Lloop, Lslow;
4371 assert(UseVIS >= 3, "VIS3 is required");
4372 assert_different_registers(src, dst, cnt, tmp);
4373 assert_different_registers(ftmp1, ftmp2, ftmp3, ftmp4);
4374
4375 // Check if cnt >= 8 (= 16 bytes)
4376 cmp(cnt, 8);
4377 br(Assembler::less, false, Assembler::pn, Lslow);
4378 delayed()->nop();
4379
4380 // Check for 8-byte alignment of src and dst
4381 or3(src, dst, tmp);
4382 andcc(tmp, 7, G0);
4383 br(Assembler::notZero, false, Assembler::pn, Lslow);
4384 // Initialize float register to zero
4385 FloatRegister zerof = ftmp4;
4386 delayed()->fzero(FloatRegisterImpl::D, zerof);
4387
4388 // Load first 8 bytes
4389 ldf(FloatRegisterImpl::D, src, 0, ftmp1);
4390
4391 bind(Lloop);
4392 inc(src, 8);
4393 dec(cnt, 8);
4394
4395 // Inflate the string by interleaving each byte from the source array
4396 // with a zero byte and storing the result in the destination array.
4397 fpmerge(zerof, ftmp1->successor(), ftmp2);
4398 stf(FloatRegisterImpl::D, ftmp2, dst, 8);
4399 fpmerge(zerof, ftmp1, ftmp3);
4400 stf(FloatRegisterImpl::D, ftmp3, dst, 0);
4401
4402 inc(dst, 16);
4403
4404 cmp(cnt, 8);
4405 // annul LDX if branch is not taken to prevent access past end of string
4406 br(Assembler::greaterEqual, true, Assembler::pt, Lloop);
4407 delayed()->ldf(FloatRegisterImpl::D, src, 0, ftmp1);
4408
4409 // Fallback to slow version
4410 bind(Lslow);
4411 }
4412
4413 // Inflate byte[] to char[].
4414 void MacroAssembler::string_inflate(Register src, Register dst, Register cnt, Register tmp, Label& Ldone) {
4415 Label Loop;
4416 assert_different_registers(src, dst, cnt, tmp);
4417
4418 ldub(src, 0, tmp);
4419 bind(Loop);
4420 inc(src);
4421 deccc(cnt);
4422 sth(tmp, dst, 0);
4423 inc(dst, sizeof(jchar));
4424 // annul LDUB if branch is not taken to prevent access past end of string
4425 br(Assembler::notZero, true, Assembler::pt, Loop);
4426 delayed()->ldub(src, 0, tmp); // hoisted
4427 }
4428
4429 void MacroAssembler::string_compare(Register str1, Register str2,
4430 Register cnt1, Register cnt2,
4431 Register tmp1, Register tmp2,
4432 Register result, int ae) {
4433 Label Ldone, Lloop;
4434 assert_different_registers(str1, str2, cnt1, cnt2, tmp1, result);
4435 int stride1, stride2;
4436
4437 // Note: Making use of the fact that compareTo(a, b) == -compareTo(b, a)
4438 // we interchange str1 and str2 in the UL case and negate the result.
4439 // Like this, str1 is always latin1 encoded, expect for the UU case.
4440
4441 if (ae == StrIntrinsicNode::LU || ae == StrIntrinsicNode::UL) {
4442 srl(cnt2, 1, cnt2);
4443 }
4444
4445 // See if the lengths are different, and calculate min in cnt1.
4446 // Save diff in case we need it for a tie-breaker.
4447 Label Lskip;
4448 Register diff = tmp1;
4449 subcc(cnt1, cnt2, diff);
4450 br(Assembler::greater, true, Assembler::pt, Lskip);
4451 // cnt2 is shorter, so use its count:
4452 delayed()->mov(cnt2, cnt1);
4453 bind(Lskip);
4454
4455 // Rename registers
4456 Register limit1 = cnt1;
4457 Register limit2 = limit1;
4458 Register chr1 = result;
4459 Register chr2 = cnt2;
4460 if (ae == StrIntrinsicNode::LU || ae == StrIntrinsicNode::UL) {
4461 // We need an additional register to keep track of two limits
4462 assert_different_registers(str1, str2, cnt1, cnt2, tmp1, tmp2, result);
4463 limit2 = tmp2;
4464 }
4465
4466 // Is the minimum length zero?
4467 cmp(limit1, (int)0); // use cast to resolve overloading ambiguity
4468 br(Assembler::equal, true, Assembler::pn, Ldone);
4469 // result is difference in lengths
4470 if (ae == StrIntrinsicNode::UU) {
4471 delayed()->sra(diff, 1, result); // Divide by 2 to get number of chars
4472 } else {
4473 delayed()->mov(diff, result);
4474 }
4475
4476 // Load first characters
4477 if (ae == StrIntrinsicNode::LL) {
4478 stride1 = stride2 = sizeof(jbyte);
4479 ldub(str1, 0, chr1);
4480 ldub(str2, 0, chr2);
4481 } else if (ae == StrIntrinsicNode::UU) {
4482 stride1 = stride2 = sizeof(jchar);
4483 lduh(str1, 0, chr1);
4484 lduh(str2, 0, chr2);
4485 } else {
4486 stride1 = sizeof(jbyte);
4487 stride2 = sizeof(jchar);
4488 ldub(str1, 0, chr1);
4489 lduh(str2, 0, chr2);
4490 }
4491
4492 // Compare first characters
4493 subcc(chr1, chr2, chr1);
4494 br(Assembler::notZero, false, Assembler::pt, Ldone);
4495 assert(chr1 == result, "result must be pre-placed");
4496 delayed()->nop();
4497
4498 // Check if the strings start at same location
4499 cmp(str1, str2);
4500 brx(Assembler::equal, true, Assembler::pn, Ldone);
4501 delayed()->mov(G0, result); // result is zero
4502
4503 // We have no guarantee that on 64 bit the higher half of limit is 0
4504 signx(limit1);
4505
4506 // Get limit
4507 if (ae == StrIntrinsicNode::LU || ae == StrIntrinsicNode::UL) {
4508 sll(limit1, 1, limit2);
4509 subcc(limit2, stride2, chr2);
4510 }
4511 subcc(limit1, stride1, chr1);
4512 br(Assembler::zero, true, Assembler::pn, Ldone);
4513 // result is difference in lengths
4514 if (ae == StrIntrinsicNode::UU) {
4515 delayed()->sra(diff, 1, result); // Divide by 2 to get number of chars
4516 } else {
4517 delayed()->mov(diff, result);
4518 }
4519
4520 // Shift str1 and str2 to the end of the arrays, negate limit
4521 add(str1, limit1, str1);
4522 add(str2, limit2, str2);
4523 neg(chr1, limit1); // limit1 = -(limit1-stride1)
4524 if (ae == StrIntrinsicNode::LU || ae == StrIntrinsicNode::UL) {
4525 neg(chr2, limit2); // limit2 = -(limit2-stride2)
4526 }
4527
4528 // Compare the rest of the characters
4529 if (ae == StrIntrinsicNode::UU) {
4530 lduh(str1, limit1, chr1);
4531 } else {
4532 ldub(str1, limit1, chr1);
4533 }
4534
4535 bind(Lloop);
4536 if (ae == StrIntrinsicNode::LL) {
4537 ldub(str2, limit2, chr2);
4538 } else {
4539 lduh(str2, limit2, chr2);
4540 }
4541
4542 subcc(chr1, chr2, chr1);
4543 br(Assembler::notZero, false, Assembler::pt, Ldone);
4544 assert(chr1 == result, "result must be pre-placed");
4545 delayed()->inccc(limit1, stride1);
4546 if (ae == StrIntrinsicNode::LU || ae == StrIntrinsicNode::UL) {
4547 inccc(limit2, stride2);
4548 }
4549
4550 // annul LDUB if branch is not taken to prevent access past end of string
4551 br(Assembler::notZero, true, Assembler::pt, Lloop);
4552 if (ae == StrIntrinsicNode::UU) {
4553 delayed()->lduh(str1, limit2, chr1);
4554 } else {
4555 delayed()->ldub(str1, limit1, chr1);
4556 }
4557
4558 // If strings are equal up to min length, return the length difference.
4559 if (ae == StrIntrinsicNode::UU) {
4560 // Divide by 2 to get number of chars
4561 sra(diff, 1, result);
4562 } else {
4563 mov(diff, result);
4564 }
4565
4566 // Otherwise, return the difference between the first mismatched chars.
4567 bind(Ldone);
4568 if(ae == StrIntrinsicNode::UL) {
4569 // Negate result (see note above)
4570 neg(result);
4571 }
4572 }
4573
4574 void MacroAssembler::array_equals(bool is_array_equ, Register ary1, Register ary2,
4575 Register limit, Register tmp, Register result, bool is_byte) {
4576 Label Ldone, Lvector, Lloop;
4577 assert_different_registers(ary1, ary2, limit, tmp, result);
4578
4579 int length_offset = arrayOopDesc::length_offset_in_bytes();
4580 int base_offset = arrayOopDesc::base_offset_in_bytes(is_byte ? T_BYTE : T_CHAR);
4581
4582 if (is_array_equ) {
4583 // return true if the same array
4584 cmp(ary1, ary2);
4585 brx(Assembler::equal, true, Assembler::pn, Ldone);
4586 delayed()->add(G0, 1, result); // equal
4587
4588 br_null(ary1, true, Assembler::pn, Ldone);
4589 delayed()->mov(G0, result); // not equal
4590
4591 br_null(ary2, true, Assembler::pn, Ldone);
4592 delayed()->mov(G0, result); // not equal
4593
4594 // load the lengths of arrays
4595 ld(Address(ary1, length_offset), limit);
4596 ld(Address(ary2, length_offset), tmp);
4597
4598 // return false if the two arrays are not equal length
4599 cmp(limit, tmp);
4600 br(Assembler::notEqual, true, Assembler::pn, Ldone);
4601 delayed()->mov(G0, result); // not equal
4602 }
4603
4604 cmp_zero_and_br(Assembler::zero, limit, Ldone, true, Assembler::pn);
4605 delayed()->add(G0, 1, result); // zero-length arrays are equal
4606
4607 if (is_array_equ) {
4608 // load array addresses
4609 add(ary1, base_offset, ary1);
4610 add(ary2, base_offset, ary2);
4611 } else {
4612 // We have no guarantee that on 64 bit the higher half of limit is 0
4613 signx(limit);
4614 }
4615
4616 if (is_byte) {
4617 Label Lskip;
4618 // check for trailing byte
4619 andcc(limit, 0x1, tmp);
4620 br(Assembler::zero, false, Assembler::pt, Lskip);
4621 delayed()->nop();
4622
4623 // compare the trailing byte
4624 sub(limit, sizeof(jbyte), limit);
4625 ldub(ary1, limit, result);
4626 ldub(ary2, limit, tmp);
4627 cmp(result, tmp);
4628 br(Assembler::notEqual, true, Assembler::pt, Ldone);
4629 delayed()->mov(G0, result); // not equal
4630
4631 // only one byte?
4632 cmp_zero_and_br(zero, limit, Ldone, true, Assembler::pn);
4633 delayed()->add(G0, 1, result); // zero-length arrays are equal
4634 bind(Lskip);
4635 } else if (is_array_equ) {
4636 // set byte count
4637 sll(limit, exact_log2(sizeof(jchar)), limit);
4638 }
4639
4640 // check for trailing character
4641 andcc(limit, 0x2, tmp);
4642 br(Assembler::zero, false, Assembler::pt, Lvector);
4643 delayed()->nop();
4644
4645 // compare the trailing char
4646 sub(limit, sizeof(jchar), limit);
4647 lduh(ary1, limit, result);
4648 lduh(ary2, limit, tmp);
4649 cmp(result, tmp);
4650 br(Assembler::notEqual, true, Assembler::pt, Ldone);
4651 delayed()->mov(G0, result); // not equal
4652
4653 // only one char?
4654 cmp_zero_and_br(zero, limit, Ldone, true, Assembler::pn);
4655 delayed()->add(G0, 1, result); // zero-length arrays are equal
4656
4657 // word by word compare, dont't need alignment check
4658 bind(Lvector);
4659 // Shift ary1 and ary2 to the end of the arrays, negate limit
4660 add(ary1, limit, ary1);
4661 add(ary2, limit, ary2);
4662 neg(limit, limit);
4663
4664 lduw(ary1, limit, result);
4665 bind(Lloop);
4666 lduw(ary2, limit, tmp);
4667 cmp(result, tmp);
4668 br(Assembler::notEqual, true, Assembler::pt, Ldone);
4669 delayed()->mov(G0, result); // not equal
4670 inccc(limit, 2*sizeof(jchar));
4671 // annul LDUW if branch is not taken to prevent access past end of array
4672 br(Assembler::notZero, true, Assembler::pt, Lloop);
4673 delayed()->lduw(ary1, limit, result); // hoisted
4674
4675 add(G0, 1, result); // equals
4676 bind(Ldone);
4677 }
4678
4679 #endif
4680
4681 // Use BIS for zeroing (count is in bytes).
4682 void MacroAssembler::bis_zeroing(Register to, Register count, Register temp, Label& Ldone) {
4683 assert(UseBlockZeroing && VM_Version::has_block_zeroing(), "only works with BIS zeroing");
4684 Register end = count;
4685 int cache_line_size = VM_Version::prefetch_data_size();
4686 // Minimum count when BIS zeroing can be used since
4687 // it needs membar which is expensive.
4688 int block_zero_size = MAX2(cache_line_size*3, (int)BlockZeroingLowLimit);
4689
4690 Label small_loop;
4691 // Check if count is negative (dead code) or zero.
4692 // Note, count uses 64bit in 64 bit VM.
4693 cmp_and_brx_short(count, 0, Assembler::lessEqual, Assembler::pn, Ldone);
4694
4695 // Use BIS zeroing only for big arrays since it requires membar.
4696 if (Assembler::is_simm13(block_zero_size)) { // < 4096
4697 cmp(count, block_zero_size);
4698 } else {
4699 set(block_zero_size, temp);
4700 cmp(count, temp);
4701 }
4702 br(Assembler::lessUnsigned, false, Assembler::pt, small_loop);
4703 delayed()->add(to, count, end);
4704
4705 // Note: size is >= three (32 bytes) cache lines.
4706
4707 // Clean the beginning of space up to next cache line.
4708 for (int offs = 0; offs < cache_line_size; offs += 8) {
4709 stx(G0, to, offs);
4710 }
4711
4712 // align to next cache line
4713 add(to, cache_line_size, to);
4714 and3(to, -cache_line_size, to);
4715
4716 // Note: size left >= two (32 bytes) cache lines.
4717
4718 // BIS should not be used to zero tail (64 bytes)
4719 // to avoid zeroing a header of the following object.
4720 sub(end, (cache_line_size*2)-8, end);
4721
4722 Label bis_loop;
4723 bind(bis_loop);
4724 stxa(G0, to, G0, Assembler::ASI_ST_BLKINIT_PRIMARY);
4725 add(to, cache_line_size, to);
4726 cmp_and_brx_short(to, end, Assembler::lessUnsigned, Assembler::pt, bis_loop);
4727
4728 // BIS needs membar.
4729 membar(Assembler::StoreLoad);
4730
4731 add(end, (cache_line_size*2)-8, end); // restore end
4732 cmp_and_brx_short(to, end, Assembler::greaterEqualUnsigned, Assembler::pn, Ldone);
4733
4734 // Clean the tail.
4735 bind(small_loop);
4736 stx(G0, to, 0);
4737 add(to, 8, to);
4738 cmp_and_brx_short(to, end, Assembler::lessUnsigned, Assembler::pt, small_loop);
4739 nop(); // Separate short branches
4740 }
4741
4742 /**
4743 * Update CRC-32[C] with a byte value according to constants in table
4744 *
4745 * @param [in,out]crc Register containing the crc.
4746 * @param [in]val Register containing the byte to fold into the CRC.
4747 * @param [in]table Register containing the table of crc constants.
4748 *
4749 * uint32_t crc;
4750 * val = crc_table[(val ^ crc) & 0xFF];
4751 * crc = val ^ (crc >> 8);
4752 */
4753 void MacroAssembler::update_byte_crc32(Register crc, Register val, Register table) {
4754 xor3(val, crc, val);
4755 and3(val, 0xFF, val);
4756 sllx(val, 2, val);
4757 lduw(table, val, val);
4758 srlx(crc, 8, crc);
4759 xor3(val, crc, crc);
4760 }
4761
4762 // Reverse byte order of lower 32 bits, assuming upper 32 bits all zeros
4763 void MacroAssembler::reverse_bytes_32(Register src, Register dst, Register tmp) {
4764 srlx(src, 24, dst);
4765
4766 sllx(src, 32+8, tmp);
4767 srlx(tmp, 32+24, tmp);
4768 sllx(tmp, 8, tmp);
4769 or3(dst, tmp, dst);
4770
4771 sllx(src, 32+16, tmp);
4772 srlx(tmp, 32+24, tmp);
4773 sllx(tmp, 16, tmp);
4774 or3(dst, tmp, dst);
4775
4776 sllx(src, 32+24, tmp);
4777 srlx(tmp, 32, tmp);
4778 or3(dst, tmp, dst);
4779 }
4780
4781 void MacroAssembler::movitof_revbytes(Register src, FloatRegister dst, Register tmp1, Register tmp2) {
4782 reverse_bytes_32(src, tmp1, tmp2);
4783 movxtod(tmp1, dst);
4784 }
4785
4786 void MacroAssembler::movftoi_revbytes(FloatRegister src, Register dst, Register tmp1, Register tmp2) {
4787 movdtox(src, tmp1);
4788 reverse_bytes_32(tmp1, dst, tmp2);
4789 }
4790
4791 void MacroAssembler::fold_128bit_crc32(Register xcrc_hi, Register xcrc_lo, Register xK_hi, Register xK_lo, Register xtmp_hi, Register xtmp_lo, Register buf, int offset) {
4792 xmulx(xcrc_hi, xK_hi, xtmp_lo);
4793 xmulxhi(xcrc_hi, xK_hi, xtmp_hi);
4794 xmulxhi(xcrc_lo, xK_lo, xcrc_hi);
4795 xmulx(xcrc_lo, xK_lo, xcrc_lo);
4796 xor3(xcrc_lo, xtmp_lo, xcrc_lo);
4797 xor3(xcrc_hi, xtmp_hi, xcrc_hi);
4798 ldxl(buf, G0, xtmp_lo);
4799 inc(buf, 8);
4800 ldxl(buf, G0, xtmp_hi);
4801 inc(buf, 8);
4802 xor3(xcrc_lo, xtmp_lo, xcrc_lo);
4803 xor3(xcrc_hi, xtmp_hi, xcrc_hi);
4804 }
4805
4806 void MacroAssembler::fold_128bit_crc32(Register xcrc_hi, Register xcrc_lo, Register xK_hi, Register xK_lo, Register xtmp_hi, Register xtmp_lo, Register xbuf_hi, Register xbuf_lo) {
4807 mov(xcrc_lo, xtmp_lo);
4808 mov(xcrc_hi, xtmp_hi);
4809 xmulx(xtmp_hi, xK_hi, xtmp_lo);
4810 xmulxhi(xtmp_hi, xK_hi, xtmp_hi);
4811 xmulxhi(xcrc_lo, xK_lo, xcrc_hi);
4812 xmulx(xcrc_lo, xK_lo, xcrc_lo);
4813 xor3(xcrc_lo, xbuf_lo, xcrc_lo);
4814 xor3(xcrc_hi, xbuf_hi, xcrc_hi);
4815 xor3(xcrc_lo, xtmp_lo, xcrc_lo);
4816 xor3(xcrc_hi, xtmp_hi, xcrc_hi);
4817 }
4818
4819 void MacroAssembler::fold_8bit_crc32(Register xcrc, Register table, Register xtmp, Register tmp) {
4820 and3(xcrc, 0xFF, tmp);
4821 sllx(tmp, 2, tmp);
4822 lduw(table, tmp, xtmp);
4823 srlx(xcrc, 8, xcrc);
4824 xor3(xtmp, xcrc, xcrc);
4825 }
4826
4827 void MacroAssembler::fold_8bit_crc32(Register crc, Register table, Register tmp) {
4828 and3(crc, 0xFF, tmp);
4829 srlx(crc, 8, crc);
4830 sllx(tmp, 2, tmp);
4831 lduw(table, tmp, tmp);
4832 xor3(tmp, crc, crc);
4833 }
4834
4835 #define CRC32_TMP_REG_NUM 18
4836
4837 #define CRC32_CONST_64 0x163cd6124
4838 #define CRC32_CONST_96 0x0ccaa009e
4839 #define CRC32_CONST_160 0x1751997d0
4840 #define CRC32_CONST_480 0x1c6e41596
4841 #define CRC32_CONST_544 0x154442bd4
4842
4843 void MacroAssembler::kernel_crc32(Register crc, Register buf, Register len, Register table) {
4844
4845 Label L_cleanup_loop, L_cleanup_check, L_align_loop, L_align_check;
4846 Label L_main_loop_prologue;
4847 Label L_fold_512b, L_fold_512b_loop, L_fold_128b;
4848 Label L_fold_tail, L_fold_tail_loop;
4849 Label L_8byte_fold_loop, L_8byte_fold_check;
4850
4851 const Register tmp[CRC32_TMP_REG_NUM] = {L0, L1, L2, L3, L4, L5, L6, G1, I0, I1, I2, I3, I4, I5, I7, O4, O5, G3};
4852
4853 Register const_64 = tmp[CRC32_TMP_REG_NUM-1];
4854 Register const_96 = tmp[CRC32_TMP_REG_NUM-1];
4855 Register const_160 = tmp[CRC32_TMP_REG_NUM-2];
4856 Register const_480 = tmp[CRC32_TMP_REG_NUM-1];
4857 Register const_544 = tmp[CRC32_TMP_REG_NUM-2];
4858
4859 set(ExternalAddress(StubRoutines::crc_table_addr()), table);
4860
4861 not1(crc); // ~c
4862 clruwu(crc); // clear upper 32 bits of crc
4863
4864 // Check if below cutoff, proceed directly to cleanup code
4865 mov(31, G4);
4866 cmp_and_br_short(len, G4, Assembler::lessEqualUnsigned, Assembler::pt, L_cleanup_check);
4867
4868 // Align buffer to 8 byte boundry
4869 mov(8, O5);
4870 and3(buf, 0x7, O4);
4871 sub(O5, O4, O5);
4872 and3(O5, 0x7, O5);
4873 sub(len, O5, len);
4874 ba(L_align_check);
4875 delayed()->nop();
4876
4877 // Alignment loop, table look up method for up to 7 bytes
4878 bind(L_align_loop);
4879 ldub(buf, 0, O4);
4880 inc(buf);
4881 dec(O5);
4882 xor3(O4, crc, O4);
4883 and3(O4, 0xFF, O4);
4884 sllx(O4, 2, O4);
4885 lduw(table, O4, O4);
4886 srlx(crc, 8, crc);
4887 xor3(O4, crc, crc);
4888 bind(L_align_check);
4889 nop();
4890 cmp_and_br_short(O5, 0, Assembler::notEqual, Assembler::pt, L_align_loop);
4891
4892 // Aligned on 64-bit (8-byte) boundry at this point
4893 // Check if still above cutoff (31-bytes)
4894 mov(31, G4);
4895 cmp_and_br_short(len, G4, Assembler::lessEqualUnsigned, Assembler::pt, L_cleanup_check);
4896 // At least 32 bytes left to process
4897
4898 // Free up registers by storing them to FP registers
4899 for (int i = 0; i < CRC32_TMP_REG_NUM; i++) {
4900 movxtod(tmp[i], as_FloatRegister(2*i));
4901 }
4902
4903 // Determine which loop to enter
4904 // Shared prologue
4905 ldxl(buf, G0, tmp[0]);
4906 inc(buf, 8);
4907 ldxl(buf, G0, tmp[1]);
4908 inc(buf, 8);
4909 xor3(tmp[0], crc, tmp[0]); // Fold CRC into first few bytes
4910 and3(crc, 0, crc); // Clear out the crc register
4911 // Main loop needs 128-bytes at least
4912 mov(128, G4);
4913 mov(64, tmp[2]);
4914 cmp_and_br_short(len, G4, Assembler::greaterEqualUnsigned, Assembler::pt, L_main_loop_prologue);
4915 // Less than 64 bytes
4916 nop();
4917 cmp_and_br_short(len, tmp[2], Assembler::lessUnsigned, Assembler::pt, L_fold_tail);
4918 // Between 64 and 127 bytes
4919 set64(CRC32_CONST_96, const_96, tmp[8]);
4920 set64(CRC32_CONST_160, const_160, tmp[9]);
4921 fold_128bit_crc32(tmp[1], tmp[0], const_96, const_160, tmp[2], tmp[3], buf, 0);
4922 fold_128bit_crc32(tmp[1], tmp[0], const_96, const_160, tmp[4], tmp[5], buf, 16);
4923 fold_128bit_crc32(tmp[1], tmp[0], const_96, const_160, tmp[6], tmp[7], buf, 32);
4924 dec(len, 48);
4925 ba(L_fold_tail);
4926 delayed()->nop();
4927
4928 bind(L_main_loop_prologue);
4929 for (int i = 2; i < 8; i++) {
4930 ldxl(buf, G0, tmp[i]);
4931 inc(buf, 8);
4932 }
4933
4934 // Fold total 512 bits of polynomial on each iteration,
4935 // 128 bits per each of 4 parallel streams
4936 set64(CRC32_CONST_480, const_480, tmp[8]);
4937 set64(CRC32_CONST_544, const_544, tmp[9]);
4938
4939 mov(128, G4);
4940 bind(L_fold_512b_loop);
4941 fold_128bit_crc32(tmp[1], tmp[0], const_480, const_544, tmp[9], tmp[8], buf, 0);
4942 fold_128bit_crc32(tmp[3], tmp[2], const_480, const_544, tmp[11], tmp[10], buf, 16);
4943 fold_128bit_crc32(tmp[5], tmp[4], const_480, const_544, tmp[13], tmp[12], buf, 32);
4944 fold_128bit_crc32(tmp[7], tmp[6], const_480, const_544, tmp[15], tmp[14], buf, 64);
4945 dec(len, 64);
4946 cmp_and_br_short(len, G4, Assembler::greaterEqualUnsigned, Assembler::pt, L_fold_512b_loop);
4947
4948 // Fold 512 bits to 128 bits
4949 bind(L_fold_512b);
4950 set64(CRC32_CONST_96, const_96, tmp[8]);
4951 set64(CRC32_CONST_160, const_160, tmp[9]);
4952
4953 fold_128bit_crc32(tmp[1], tmp[0], const_96, const_160, tmp[8], tmp[9], tmp[3], tmp[2]);
4954 fold_128bit_crc32(tmp[1], tmp[0], const_96, const_160, tmp[8], tmp[9], tmp[5], tmp[4]);
4955 fold_128bit_crc32(tmp[1], tmp[0], const_96, const_160, tmp[8], tmp[9], tmp[7], tmp[6]);
4956 dec(len, 48);
4957
4958 // Fold the rest of 128 bits data chunks
4959 bind(L_fold_tail);
4960 mov(32, G4);
4961 cmp_and_br_short(len, G4, Assembler::lessEqualUnsigned, Assembler::pt, L_fold_128b);
4962
4963 set64(CRC32_CONST_96, const_96, tmp[8]);
4964 set64(CRC32_CONST_160, const_160, tmp[9]);
4965
4966 bind(L_fold_tail_loop);
4967 fold_128bit_crc32(tmp[1], tmp[0], const_96, const_160, tmp[2], tmp[3], buf, 0);
4968 sub(len, 16, len);
4969 cmp_and_br_short(len, G4, Assembler::greaterEqualUnsigned, Assembler::pt, L_fold_tail_loop);
4970
4971 // Fold the 128 bits in tmps 0 - 1 into tmp 1
4972 bind(L_fold_128b);
4973
4974 set64(CRC32_CONST_64, const_64, tmp[4]);
4975
4976 xmulx(const_64, tmp[0], tmp[2]);
4977 xmulxhi(const_64, tmp[0], tmp[3]);
4978
4979 srl(tmp[2], G0, tmp[4]);
4980 xmulx(const_64, tmp[4], tmp[4]);
4981
4982 srlx(tmp[2], 32, tmp[2]);
4983 sllx(tmp[3], 32, tmp[3]);
4984 or3(tmp[2], tmp[3], tmp[2]);
4985
4986 xor3(tmp[4], tmp[1], tmp[4]);
4987 xor3(tmp[4], tmp[2], tmp[1]);
4988 dec(len, 8);
4989
4990 // Use table lookup for the 8 bytes left in tmp[1]
4991 dec(len, 8);
4992
4993 // 8 8-bit folds to compute 32-bit CRC.
4994 for (int j = 0; j < 4; j++) {
4995 fold_8bit_crc32(tmp[1], table, tmp[2], tmp[3]);
4996 }
4997 srl(tmp[1], G0, crc); // move 32 bits to general register
4998 for (int j = 0; j < 4; j++) {
4999 fold_8bit_crc32(crc, table, tmp[3]);
5000 }
5001
5002 bind(L_8byte_fold_check);
5003
5004 // Restore int registers saved in FP registers
5005 for (int i = 0; i < CRC32_TMP_REG_NUM; i++) {
5006 movdtox(as_FloatRegister(2*i), tmp[i]);
5007 }
5008
5009 ba(L_cleanup_check);
5010 delayed()->nop();
5011
5012 // Table look-up method for the remaining few bytes
5013 bind(L_cleanup_loop);
5014 ldub(buf, 0, O4);
5015 inc(buf);
5016 dec(len);
5017 xor3(O4, crc, O4);
5018 and3(O4, 0xFF, O4);
5019 sllx(O4, 2, O4);
5020 lduw(table, O4, O4);
5021 srlx(crc, 8, crc);
5022 xor3(O4, crc, crc);
5023 bind(L_cleanup_check);
5024 nop();
5025 cmp_and_br_short(len, 0, Assembler::greaterUnsigned, Assembler::pt, L_cleanup_loop);
5026
5027 not1(crc);
5028 }
5029