168 }
169 // Required boilerplate
170 virtual uint size_of() const { return sizeof(MachNode); }
171 virtual int Opcode() const; // Always equal to MachNode
172 virtual uint rule() const = 0; // Machine-specific opcode
173 // Number of inputs which come before the first operand.
174 // Generally at least 1, to skip the Control input
175 virtual uint oper_input_base() const { return 1; }
176
177 // Copy inputs and operands to new node of instruction.
178 // Called from cisc_version() and short_branch_version().
179 // !!!! The method's body is defined in ad_<arch>.cpp file.
180 void fill_new_machnode(MachNode *n, Compile* C) const;
181
182 // Return an equivalent instruction using memory for cisc_operand position
183 virtual MachNode *cisc_version(int offset, Compile* C);
184 // Modify this instruction's register mask to use stack version for cisc_operand
185 virtual void use_cisc_RegMask();
186
187 // Support for short branches
188 virtual MachNode *short_branch_version(Compile* C) { return NULL; }
189 bool may_be_short_branch() const { return (flags() & Flag_may_be_short_branch) != 0; }
190
191 // Avoid back to back some instructions on some CPUs.
192 bool avoid_back_to_back() const { return (flags() & Flag_avoid_back_to_back) != 0; }
193
194 // First index in _in[] corresponding to operand, or -1 if there is none
195 int operand_index(uint operand) const;
196
197 // Register class input is expected in
198 virtual const RegMask &in_RegMask(uint) const;
199
200 // cisc-spillable instructions redefine for use by in_RegMask
201 virtual const RegMask *cisc_RegMask() const { return NULL; }
202
203 // If this instruction is a 2-address instruction, then return the
204 // index of the input which must match the output. Not nessecary
205 // for instructions which bind the input and output register to the
206 // same singleton regiser (e.g., Intel IDIV which binds AX to be
207 // both an input and an output). It is nessecary when the input and
208 // output have choices - but they must use the same choice.
255 // This method is free to ignore stack slots if that helps.
256 #define TYPE_PTR_SENTINAL ((const TypePtr*)-1)
257 // Passing TYPE_PTR_SENTINAL as adr_type asks for computation of the adr_type if possible
258 const Node* get_base_and_disp(intptr_t &offset, const TypePtr* &adr_type) const;
259
260 // Helper for get_base_and_disp: find the base and index input nodes.
261 // Returns the MachOper as determined by memory_operand(), for use, if
262 // needed by the caller. If (MachOper *)-1 is returned, base and index
263 // are set to NodeSentinel. If (MachOper *) NULL is returned, base and
264 // index are set to NULL.
265 const MachOper* memory_inputs(Node* &base, Node* &index) const;
266
267 // Helper for memory_inputs: Which operand carries the necessary info?
268 // By default, returns NULL, which means there is no such operand.
269 // If it returns (MachOper*)-1, this means there are multiple memories.
270 virtual const MachOper* memory_operand() const { return NULL; }
271
272 // Call "get_base_and_disp" to decide which category of memory is used here.
273 virtual const class TypePtr *adr_type() const;
274
275 // Negate conditional branches. Error for non-branch Nodes
276 virtual void negate();
277
278 // Apply peephole rule(s) to this instruction
279 virtual MachNode *peephole( Block *block, int block_index, PhaseRegAlloc *ra_, int &deleted, Compile* C );
280
281 // Top-level ideal Opcode matched
282 virtual int ideal_Opcode() const { return Op_Node; }
283
284 // Set the branch inside jump MachNodes. Error for non-branch Nodes.
285 virtual void label_set( Label* label, uint block_num );
286
287 // Adds the label for the case
288 virtual void add_case_label( int switch_val, Label* blockLabel);
289
290 // Set the absolute address for methods
291 virtual void method_set( intptr_t addr );
292
293 // Should we clone rather than spill this instruction?
294 bool rematerialize() const;
295
296 // Get the pipeline info
297 static const Pipeline *pipeline_class();
298 virtual const Pipeline *pipeline() const;
299
300 #ifndef PRODUCT
301 virtual const char *Name() const = 0; // Machine-specific name
302 virtual void dump_spec(outputStream *st) const; // Print per-node info
303 void dump_format(PhaseRegAlloc *ra, outputStream *st) const; // access to virtual
304 #endif
305 };
306
497 }
498 virtual uint size_of() const { return sizeof(*this); }
499 void set_out_RegMask(const RegMask &out) { _out = &out; }
500 void set_in_RegMask(const RegMask &in) { _in = ∈ }
501 virtual const RegMask &out_RegMask() const { return *_out; }
502 virtual const RegMask &in_RegMask(uint) const { return *_in; }
503 virtual const class Type *bottom_type() const { return _type; }
504 virtual uint ideal_reg() const { return Matcher::base2reg[_type->base()]; }
505 virtual uint oper_input_base() const { return 1; }
506 uint implementation( CodeBuffer *cbuf, PhaseRegAlloc *ra_, bool do_size, outputStream* st ) const;
507
508 virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const;
509 virtual uint size(PhaseRegAlloc *ra_) const;
510
511 #ifndef PRODUCT
512 virtual const char *Name() const { return "MachSpillCopy"; }
513 virtual void format( PhaseRegAlloc *, outputStream *st ) const;
514 #endif
515 };
516
517 //------------------------------MachNullChkNode--------------------------------
518 // Machine-dependent null-pointer-check Node. Points a real MachNode that is
519 // also some kind of memory op. Turns the indicated MachNode into a
520 // conditional branch with good latency on the ptr-not-null path and awful
521 // latency on the pointer-is-null path.
522
523 class MachNullCheckNode : public MachIdealNode {
524 public:
525 const uint _vidx; // Index of memop being tested
526 MachNullCheckNode( Node *ctrl, Node *memop, uint vidx ) : MachIdealNode(), _vidx(vidx) {
527 init_class_id(Class_MachNullCheck);
528 init_flags(Flag_is_Branch);
529 add_req(ctrl);
530 add_req(memop);
531 }
532
533 virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const;
534 virtual void label_set(Label* label, uint block_num);
535 virtual bool pinned() const { return true; };
536 virtual void negate() { }
537 virtual const class Type *bottom_type() const { return TypeTuple::IFBOTH; }
538 virtual uint ideal_reg() const { return NotAMachineReg; }
539 virtual const RegMask &in_RegMask(uint) const;
540 virtual const RegMask &out_RegMask() const { return RegMask::Empty; }
541 #ifndef PRODUCT
542 virtual const char *Name() const { return "NullCheck"; }
543 virtual void format( PhaseRegAlloc *, outputStream *st ) const;
544 #endif
545 };
546
547 //------------------------------MachProjNode----------------------------------
548 // Machine-dependent Ideal projections (how is that for an oxymoron). Really
549 // just MachNodes made by the Ideal world that replicate simple projections
550 // but with machine-dependent input & output register masks. Generally
551 // produced as part of calling conventions. Normally I make MachNodes as part
552 // of the Matcher process, but the Matcher is ill suited to issues involving
553 // frame handling, so frame handling is all done in the Ideal world with
554 // occasional callbacks to the machine model for important info.
555 class MachProjNode : public ProjNode {
561 const uint _ideal_reg;
562 enum projType {
563 unmatched_proj = 0, // Projs for Control, I/O, memory not matched
564 fat_proj = 999 // Projs killing many regs, defined by _rout
565 };
566 virtual int Opcode() const;
567 virtual const Type *bottom_type() const;
568 virtual const TypePtr *adr_type() const;
569 virtual const RegMask &in_RegMask(uint) const { return RegMask::Empty; }
570 virtual const RegMask &out_RegMask() const { return _rout; }
571 virtual uint ideal_reg() const { return _ideal_reg; }
572 // Need size_of() for virtual ProjNode::clone()
573 virtual uint size_of() const { return sizeof(MachProjNode); }
574 #ifndef PRODUCT
575 virtual void dump_spec(outputStream *st) const;
576 #endif
577 };
578
579 //------------------------------MachIfNode-------------------------------------
580 // Machine-specific versions of IfNodes
581 class MachIfNode : public MachNode {
582 virtual uint size_of() const { return sizeof(*this); } // Size is bigger
583 public:
584 float _prob; // Probability branch goes either way
585 float _fcnt; // Frequency counter
586 MachIfNode() : MachNode() {
587 init_class_id(Class_MachIf);
588 }
589 #ifndef PRODUCT
590 virtual void dump_spec(outputStream *st) const;
591 #endif
592 };
593
594 //------------------------------MachGotoNode-----------------------------------
595 // Machine-specific versions of GotoNodes
596 class MachGotoNode : public MachNode {
597 public:
598 MachGotoNode() : MachNode() {
599 init_class_id(Class_MachGoto);
600 }
601 };
602
603 //------------------------------MachFastLockNode-------------------------------------
604 // Machine-specific versions of FastLockNodes
605 class MachFastLockNode : public MachNode {
606 virtual uint size_of() const { return sizeof(*this); } // Size is bigger
607 public:
608 BiasedLockingCounters* _counters;
609
610 MachFastLockNode() : MachNode() {}
611 };
612
613 //------------------------------MachReturnNode--------------------------------
614 // Machine-specific versions of subroutine returns
615 class MachReturnNode : public MachNode {
616 virtual uint size_of() const; // Size is bigger
617 public:
618 RegMask *_in_rms; // Input register masks, set during allocation
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168 }
169 // Required boilerplate
170 virtual uint size_of() const { return sizeof(MachNode); }
171 virtual int Opcode() const; // Always equal to MachNode
172 virtual uint rule() const = 0; // Machine-specific opcode
173 // Number of inputs which come before the first operand.
174 // Generally at least 1, to skip the Control input
175 virtual uint oper_input_base() const { return 1; }
176
177 // Copy inputs and operands to new node of instruction.
178 // Called from cisc_version() and short_branch_version().
179 // !!!! The method's body is defined in ad_<arch>.cpp file.
180 void fill_new_machnode(MachNode *n, Compile* C) const;
181
182 // Return an equivalent instruction using memory for cisc_operand position
183 virtual MachNode *cisc_version(int offset, Compile* C);
184 // Modify this instruction's register mask to use stack version for cisc_operand
185 virtual void use_cisc_RegMask();
186
187 // Support for short branches
188 bool may_be_short_branch() const { return (flags() & Flag_may_be_short_branch) != 0; }
189
190 // Avoid back to back some instructions on some CPUs.
191 bool avoid_back_to_back() const { return (flags() & Flag_avoid_back_to_back) != 0; }
192
193 // First index in _in[] corresponding to operand, or -1 if there is none
194 int operand_index(uint operand) const;
195
196 // Register class input is expected in
197 virtual const RegMask &in_RegMask(uint) const;
198
199 // cisc-spillable instructions redefine for use by in_RegMask
200 virtual const RegMask *cisc_RegMask() const { return NULL; }
201
202 // If this instruction is a 2-address instruction, then return the
203 // index of the input which must match the output. Not nessecary
204 // for instructions which bind the input and output register to the
205 // same singleton regiser (e.g., Intel IDIV which binds AX to be
206 // both an input and an output). It is nessecary when the input and
207 // output have choices - but they must use the same choice.
254 // This method is free to ignore stack slots if that helps.
255 #define TYPE_PTR_SENTINAL ((const TypePtr*)-1)
256 // Passing TYPE_PTR_SENTINAL as adr_type asks for computation of the adr_type if possible
257 const Node* get_base_and_disp(intptr_t &offset, const TypePtr* &adr_type) const;
258
259 // Helper for get_base_and_disp: find the base and index input nodes.
260 // Returns the MachOper as determined by memory_operand(), for use, if
261 // needed by the caller. If (MachOper *)-1 is returned, base and index
262 // are set to NodeSentinel. If (MachOper *) NULL is returned, base and
263 // index are set to NULL.
264 const MachOper* memory_inputs(Node* &base, Node* &index) const;
265
266 // Helper for memory_inputs: Which operand carries the necessary info?
267 // By default, returns NULL, which means there is no such operand.
268 // If it returns (MachOper*)-1, this means there are multiple memories.
269 virtual const MachOper* memory_operand() const { return NULL; }
270
271 // Call "get_base_and_disp" to decide which category of memory is used here.
272 virtual const class TypePtr *adr_type() const;
273
274 // Apply peephole rule(s) to this instruction
275 virtual MachNode *peephole( Block *block, int block_index, PhaseRegAlloc *ra_, int &deleted, Compile* C );
276
277 // Top-level ideal Opcode matched
278 virtual int ideal_Opcode() const { return Op_Node; }
279
280 // Adds the label for the case
281 virtual void add_case_label( int switch_val, Label* blockLabel);
282
283 // Set the absolute address for methods
284 virtual void method_set( intptr_t addr );
285
286 // Should we clone rather than spill this instruction?
287 bool rematerialize() const;
288
289 // Get the pipeline info
290 static const Pipeline *pipeline_class();
291 virtual const Pipeline *pipeline() const;
292
293 #ifndef PRODUCT
294 virtual const char *Name() const = 0; // Machine-specific name
295 virtual void dump_spec(outputStream *st) const; // Print per-node info
296 void dump_format(PhaseRegAlloc *ra, outputStream *st) const; // access to virtual
297 #endif
298 };
299
490 }
491 virtual uint size_of() const { return sizeof(*this); }
492 void set_out_RegMask(const RegMask &out) { _out = &out; }
493 void set_in_RegMask(const RegMask &in) { _in = ∈ }
494 virtual const RegMask &out_RegMask() const { return *_out; }
495 virtual const RegMask &in_RegMask(uint) const { return *_in; }
496 virtual const class Type *bottom_type() const { return _type; }
497 virtual uint ideal_reg() const { return Matcher::base2reg[_type->base()]; }
498 virtual uint oper_input_base() const { return 1; }
499 uint implementation( CodeBuffer *cbuf, PhaseRegAlloc *ra_, bool do_size, outputStream* st ) const;
500
501 virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const;
502 virtual uint size(PhaseRegAlloc *ra_) const;
503
504 #ifndef PRODUCT
505 virtual const char *Name() const { return "MachSpillCopy"; }
506 virtual void format( PhaseRegAlloc *, outputStream *st ) const;
507 #endif
508 };
509
510 //------------------------------MachBranchNode--------------------------------
511 // Abstract machine branch Node
512 class MachBranchNode : public MachIdealNode {
513 public:
514 MachBranchNode() : MachIdealNode() {
515 init_class_id(Class_MachBranch);
516 }
517 virtual void label_set(Label* label, uint block_num) = 0;
518 virtual void save_label(Label** label, uint* block_num) = 0;
519
520 // Support for short branches
521 virtual MachNode *short_branch_version(Compile* C) { return NULL; }
522
523 virtual bool pinned() const { return true; };
524 };
525
526 //------------------------------MachNullChkNode--------------------------------
527 // Machine-dependent null-pointer-check Node. Points a real MachNode that is
528 // also some kind of memory op. Turns the indicated MachNode into a
529 // conditional branch with good latency on the ptr-not-null path and awful
530 // latency on the pointer-is-null path.
531
532 class MachNullCheckNode : public MachBranchNode {
533 public:
534 const uint _vidx; // Index of memop being tested
535 MachNullCheckNode( Node *ctrl, Node *memop, uint vidx ) : MachBranchNode(), _vidx(vidx) {
536 init_class_id(Class_MachNullCheck);
537 add_req(ctrl);
538 add_req(memop);
539 }
540 virtual uint size_of() const { return sizeof(*this); }
541
542 virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const;
543 virtual void label_set(Label* label, uint block_num);
544 virtual void save_label(Label** label, uint* block_num);
545 virtual void negate() { }
546 virtual const class Type *bottom_type() const { return TypeTuple::IFBOTH; }
547 virtual uint ideal_reg() const { return NotAMachineReg; }
548 virtual const RegMask &in_RegMask(uint) const;
549 virtual const RegMask &out_RegMask() const { return RegMask::Empty; }
550 #ifndef PRODUCT
551 virtual const char *Name() const { return "NullCheck"; }
552 virtual void format( PhaseRegAlloc *, outputStream *st ) const;
553 #endif
554 };
555
556 //------------------------------MachProjNode----------------------------------
557 // Machine-dependent Ideal projections (how is that for an oxymoron). Really
558 // just MachNodes made by the Ideal world that replicate simple projections
559 // but with machine-dependent input & output register masks. Generally
560 // produced as part of calling conventions. Normally I make MachNodes as part
561 // of the Matcher process, but the Matcher is ill suited to issues involving
562 // frame handling, so frame handling is all done in the Ideal world with
563 // occasional callbacks to the machine model for important info.
564 class MachProjNode : public ProjNode {
570 const uint _ideal_reg;
571 enum projType {
572 unmatched_proj = 0, // Projs for Control, I/O, memory not matched
573 fat_proj = 999 // Projs killing many regs, defined by _rout
574 };
575 virtual int Opcode() const;
576 virtual const Type *bottom_type() const;
577 virtual const TypePtr *adr_type() const;
578 virtual const RegMask &in_RegMask(uint) const { return RegMask::Empty; }
579 virtual const RegMask &out_RegMask() const { return _rout; }
580 virtual uint ideal_reg() const { return _ideal_reg; }
581 // Need size_of() for virtual ProjNode::clone()
582 virtual uint size_of() const { return sizeof(MachProjNode); }
583 #ifndef PRODUCT
584 virtual void dump_spec(outputStream *st) const;
585 #endif
586 };
587
588 //------------------------------MachIfNode-------------------------------------
589 // Machine-specific versions of IfNodes
590 class MachIfNode : public MachBranchNode {
591 virtual uint size_of() const { return sizeof(*this); } // Size is bigger
592 public:
593 float _prob; // Probability branch goes either way
594 float _fcnt; // Frequency counter
595 MachIfNode() : MachBranchNode() {
596 init_class_id(Class_MachIf);
597 }
598 // Negate conditional branches.
599 virtual void negate() = 0;
600 #ifndef PRODUCT
601 virtual void dump_spec(outputStream *st) const;
602 #endif
603 };
604
605 //------------------------------MachGotoNode-----------------------------------
606 // Machine-specific versions of GotoNodes
607 class MachGotoNode : public MachBranchNode {
608 public:
609 MachGotoNode() : MachBranchNode() {
610 init_class_id(Class_MachGoto);
611 }
612 };
613
614 //------------------------------MachFastLockNode-------------------------------------
615 // Machine-specific versions of FastLockNodes
616 class MachFastLockNode : public MachNode {
617 virtual uint size_of() const { return sizeof(*this); } // Size is bigger
618 public:
619 BiasedLockingCounters* _counters;
620
621 MachFastLockNode() : MachNode() {}
622 };
623
624 //------------------------------MachReturnNode--------------------------------
625 // Machine-specific versions of subroutine returns
626 class MachReturnNode : public MachNode {
627 virtual uint size_of() const; // Size is bigger
628 public:
629 RegMask *_in_rms; // Input register masks, set during allocation
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