rev 56556 : 8232151: Minimal VM build broken after JDK-8232050
Reviewed-by: dholmes, clanger, redestad
1 /*
2 * Copyright (c) 2003, 2019, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #include "precompiled.hpp"
26 #ifndef _WINDOWS
27 #include "alloca.h"
28 #endif
29 #include "asm/macroAssembler.hpp"
30 #include "asm/macroAssembler.inline.hpp"
31 #include "code/debugInfoRec.hpp"
32 #include "code/icBuffer.hpp"
33 #include "code/nativeInst.hpp"
34 #include "code/vtableStubs.hpp"
35 #include "gc/shared/collectedHeap.hpp"
36 #include "gc/shared/gcLocker.hpp"
37 #include "gc/shared/barrierSet.hpp"
38 #include "gc/shared/barrierSetAssembler.hpp"
39 #include "interpreter/interpreter.hpp"
40 #include "logging/log.hpp"
41 #include "memory/resourceArea.hpp"
42 #include "memory/universe.hpp"
43 #include "oops/compiledICHolder.hpp"
44 #include "runtime/safepointMechanism.hpp"
45 #include "runtime/sharedRuntime.hpp"
46 #include "runtime/vframeArray.hpp"
47 #include "utilities/align.hpp"
48 #include "utilities/formatBuffer.hpp"
49 #include "vm_version_x86.hpp"
50 #include "vmreg_x86.inline.hpp"
51 #ifdef COMPILER1
52 #include "c1/c1_Runtime1.hpp"
53 #endif
54 #ifdef COMPILER2
55 #include "opto/runtime.hpp"
56 #endif
57 #if INCLUDE_JVMCI
58 #include "jvmci/jvmciJavaClasses.hpp"
59 #endif
60
61 #define __ masm->
62
63 const int StackAlignmentInSlots = StackAlignmentInBytes / VMRegImpl::stack_slot_size;
64
65 class SimpleRuntimeFrame {
66
67 public:
68
69 // Most of the runtime stubs have this simple frame layout.
70 // This class exists to make the layout shared in one place.
71 // Offsets are for compiler stack slots, which are jints.
72 enum layout {
73 // The frame sender code expects that rbp will be in the "natural" place and
74 // will override any oopMap setting for it. We must therefore force the layout
75 // so that it agrees with the frame sender code.
76 rbp_off = frame::arg_reg_save_area_bytes/BytesPerInt,
77 rbp_off2,
78 return_off, return_off2,
79 framesize
80 };
81 };
82
83 class RegisterSaver {
84 // Capture info about frame layout. Layout offsets are in jint
85 // units because compiler frame slots are jints.
86 #define XSAVE_AREA_BEGIN 160
87 #define XSAVE_AREA_YMM_BEGIN 576
88 #define XSAVE_AREA_ZMM_BEGIN 1152
89 #define XSAVE_AREA_UPPERBANK 1664
90 #define DEF_XMM_OFFS(regnum) xmm ## regnum ## _off = xmm_off + (regnum)*16/BytesPerInt, xmm ## regnum ## H_off
91 #define DEF_YMM_OFFS(regnum) ymm ## regnum ## _off = ymm_off + (regnum)*16/BytesPerInt, ymm ## regnum ## H_off
92 #define DEF_ZMM_OFFS(regnum) zmm ## regnum ## _off = zmm_off + (regnum-16)*64/BytesPerInt, zmm ## regnum ## H_off
93 enum layout {
94 fpu_state_off = frame::arg_reg_save_area_bytes/BytesPerInt, // fxsave save area
95 xmm_off = fpu_state_off + XSAVE_AREA_BEGIN/BytesPerInt, // offset in fxsave save area
96 DEF_XMM_OFFS(0),
97 DEF_XMM_OFFS(1),
98 // 2..15 are implied in range usage
99 ymm_off = xmm_off + (XSAVE_AREA_YMM_BEGIN - XSAVE_AREA_BEGIN)/BytesPerInt,
100 DEF_YMM_OFFS(0),
101 DEF_YMM_OFFS(1),
102 // 2..15 are implied in range usage
103 zmm_high = xmm_off + (XSAVE_AREA_ZMM_BEGIN - XSAVE_AREA_BEGIN)/BytesPerInt,
104 zmm_off = xmm_off + (XSAVE_AREA_UPPERBANK - XSAVE_AREA_BEGIN)/BytesPerInt,
105 DEF_ZMM_OFFS(16),
106 DEF_ZMM_OFFS(17),
107 // 18..31 are implied in range usage
108 fpu_state_end = fpu_state_off + ((FPUStateSizeInWords-1)*wordSize / BytesPerInt),
109 fpu_stateH_end,
110 r15_off, r15H_off,
111 r14_off, r14H_off,
112 r13_off, r13H_off,
113 r12_off, r12H_off,
114 r11_off, r11H_off,
115 r10_off, r10H_off,
116 r9_off, r9H_off,
117 r8_off, r8H_off,
118 rdi_off, rdiH_off,
119 rsi_off, rsiH_off,
120 ignore_off, ignoreH_off, // extra copy of rbp
121 rsp_off, rspH_off,
122 rbx_off, rbxH_off,
123 rdx_off, rdxH_off,
124 rcx_off, rcxH_off,
125 rax_off, raxH_off,
126 // 16-byte stack alignment fill word: see MacroAssembler::push/pop_IU_state
127 align_off, alignH_off,
128 flags_off, flagsH_off,
129 // The frame sender code expects that rbp will be in the "natural" place and
130 // will override any oopMap setting for it. We must therefore force the layout
131 // so that it agrees with the frame sender code.
132 rbp_off, rbpH_off, // copy of rbp we will restore
133 return_off, returnH_off, // slot for return address
134 reg_save_size // size in compiler stack slots
135 };
136
137 public:
138 static OopMap* save_live_registers(MacroAssembler* masm, int additional_frame_words, int* total_frame_words, bool save_vectors = false);
139 static void restore_live_registers(MacroAssembler* masm, bool restore_vectors = false);
140
141 // Offsets into the register save area
142 // Used by deoptimization when it is managing result register
143 // values on its own
144
145 static int rax_offset_in_bytes(void) { return BytesPerInt * rax_off; }
146 static int rdx_offset_in_bytes(void) { return BytesPerInt * rdx_off; }
147 static int rbx_offset_in_bytes(void) { return BytesPerInt * rbx_off; }
148 static int xmm0_offset_in_bytes(void) { return BytesPerInt * xmm0_off; }
149 static int return_offset_in_bytes(void) { return BytesPerInt * return_off; }
150
151 // During deoptimization only the result registers need to be restored,
152 // all the other values have already been extracted.
153 static void restore_result_registers(MacroAssembler* masm);
154 };
155
156 OopMap* RegisterSaver::save_live_registers(MacroAssembler* masm, int additional_frame_words, int* total_frame_words, bool save_vectors) {
157 int off = 0;
158 int num_xmm_regs = XMMRegisterImpl::number_of_registers;
159 if (UseAVX < 3) {
160 num_xmm_regs = num_xmm_regs/2;
161 }
162 #if COMPILER2_OR_JVMCI
163 if (save_vectors) {
164 assert(UseAVX > 0, "Vectors larger than 16 byte long are supported only with AVX");
165 assert(MaxVectorSize <= 64, "Only up to 64 byte long vectors are supported");
166 }
167 #else
168 assert(!save_vectors, "vectors are generated only by C2 and JVMCI");
169 #endif
170
171 // Always make the frame size 16-byte aligned, both vector and non vector stacks are always allocated
172 int frame_size_in_bytes = align_up(reg_save_size*BytesPerInt, num_xmm_regs);
173 // OopMap frame size is in compiler stack slots (jint's) not bytes or words
174 int frame_size_in_slots = frame_size_in_bytes / BytesPerInt;
175 // CodeBlob frame size is in words.
176 int frame_size_in_words = frame_size_in_bytes / wordSize;
177 *total_frame_words = frame_size_in_words;
178
179 // Save registers, fpu state, and flags.
180 // We assume caller has already pushed the return address onto the
181 // stack, so rsp is 8-byte aligned here.
182 // We push rpb twice in this sequence because we want the real rbp
183 // to be under the return like a normal enter.
184
185 __ enter(); // rsp becomes 16-byte aligned here
186 __ push_CPU_state(); // Push a multiple of 16 bytes
187
188 // push cpu state handles this on EVEX enabled targets
189 if (save_vectors) {
190 // Save upper half of YMM registers(0..15)
191 int base_addr = XSAVE_AREA_YMM_BEGIN;
192 for (int n = 0; n < 16; n++) {
193 __ vextractf128_high(Address(rsp, base_addr+n*16), as_XMMRegister(n));
194 }
195 if (VM_Version::supports_evex()) {
196 // Save upper half of ZMM registers(0..15)
197 base_addr = XSAVE_AREA_ZMM_BEGIN;
198 for (int n = 0; n < 16; n++) {
199 __ vextractf64x4_high(Address(rsp, base_addr+n*32), as_XMMRegister(n));
200 }
201 // Save full ZMM registers(16..num_xmm_regs)
202 base_addr = XSAVE_AREA_UPPERBANK;
203 off = 0;
204 int vector_len = Assembler::AVX_512bit;
205 for (int n = 16; n < num_xmm_regs; n++) {
206 __ evmovdqul(Address(rsp, base_addr+(off++*64)), as_XMMRegister(n), vector_len);
207 }
208 }
209 } else {
210 if (VM_Version::supports_evex()) {
211 // Save upper bank of ZMM registers(16..31) for double/float usage
212 int base_addr = XSAVE_AREA_UPPERBANK;
213 off = 0;
214 for (int n = 16; n < num_xmm_regs; n++) {
215 __ movsd(Address(rsp, base_addr+(off++*64)), as_XMMRegister(n));
216 }
217 }
218 }
219 __ vzeroupper();
220 if (frame::arg_reg_save_area_bytes != 0) {
221 // Allocate argument register save area
222 __ subptr(rsp, frame::arg_reg_save_area_bytes);
223 }
224
225 // Set an oopmap for the call site. This oopmap will map all
226 // oop-registers and debug-info registers as callee-saved. This
227 // will allow deoptimization at this safepoint to find all possible
228 // debug-info recordings, as well as let GC find all oops.
229
230 OopMapSet *oop_maps = new OopMapSet();
231 OopMap* map = new OopMap(frame_size_in_slots, 0);
232
233 #define STACK_OFFSET(x) VMRegImpl::stack2reg((x))
234
235 map->set_callee_saved(STACK_OFFSET( rax_off ), rax->as_VMReg());
236 map->set_callee_saved(STACK_OFFSET( rcx_off ), rcx->as_VMReg());
237 map->set_callee_saved(STACK_OFFSET( rdx_off ), rdx->as_VMReg());
238 map->set_callee_saved(STACK_OFFSET( rbx_off ), rbx->as_VMReg());
239 // rbp location is known implicitly by the frame sender code, needs no oopmap
240 // and the location where rbp was saved by is ignored
241 map->set_callee_saved(STACK_OFFSET( rsi_off ), rsi->as_VMReg());
242 map->set_callee_saved(STACK_OFFSET( rdi_off ), rdi->as_VMReg());
243 map->set_callee_saved(STACK_OFFSET( r8_off ), r8->as_VMReg());
244 map->set_callee_saved(STACK_OFFSET( r9_off ), r9->as_VMReg());
245 map->set_callee_saved(STACK_OFFSET( r10_off ), r10->as_VMReg());
246 map->set_callee_saved(STACK_OFFSET( r11_off ), r11->as_VMReg());
247 map->set_callee_saved(STACK_OFFSET( r12_off ), r12->as_VMReg());
248 map->set_callee_saved(STACK_OFFSET( r13_off ), r13->as_VMReg());
249 map->set_callee_saved(STACK_OFFSET( r14_off ), r14->as_VMReg());
250 map->set_callee_saved(STACK_OFFSET( r15_off ), r15->as_VMReg());
251 // For both AVX and EVEX we will use the legacy FXSAVE area for xmm0..xmm15,
252 // on EVEX enabled targets, we get it included in the xsave area
253 off = xmm0_off;
254 int delta = xmm1_off - off;
255 for (int n = 0; n < 16; n++) {
256 XMMRegister xmm_name = as_XMMRegister(n);
257 map->set_callee_saved(STACK_OFFSET(off), xmm_name->as_VMReg());
258 off += delta;
259 }
260 if(UseAVX > 2) {
261 // Obtain xmm16..xmm31 from the XSAVE area on EVEX enabled targets
262 off = zmm16_off;
263 delta = zmm17_off - off;
264 for (int n = 16; n < num_xmm_regs; n++) {
265 XMMRegister zmm_name = as_XMMRegister(n);
266 map->set_callee_saved(STACK_OFFSET(off), zmm_name->as_VMReg());
267 off += delta;
268 }
269 }
270
271 #if COMPILER2_OR_JVMCI
272 if (save_vectors) {
273 off = ymm0_off;
274 int delta = ymm1_off - off;
275 for (int n = 0; n < 16; n++) {
276 XMMRegister ymm_name = as_XMMRegister(n);
277 map->set_callee_saved(STACK_OFFSET(off), ymm_name->as_VMReg()->next(4));
278 off += delta;
279 }
280 }
281 #endif // COMPILER2_OR_JVMCI
282
283 // %%% These should all be a waste but we'll keep things as they were for now
284 if (true) {
285 map->set_callee_saved(STACK_OFFSET( raxH_off ), rax->as_VMReg()->next());
286 map->set_callee_saved(STACK_OFFSET( rcxH_off ), rcx->as_VMReg()->next());
287 map->set_callee_saved(STACK_OFFSET( rdxH_off ), rdx->as_VMReg()->next());
288 map->set_callee_saved(STACK_OFFSET( rbxH_off ), rbx->as_VMReg()->next());
289 // rbp location is known implicitly by the frame sender code, needs no oopmap
290 map->set_callee_saved(STACK_OFFSET( rsiH_off ), rsi->as_VMReg()->next());
291 map->set_callee_saved(STACK_OFFSET( rdiH_off ), rdi->as_VMReg()->next());
292 map->set_callee_saved(STACK_OFFSET( r8H_off ), r8->as_VMReg()->next());
293 map->set_callee_saved(STACK_OFFSET( r9H_off ), r9->as_VMReg()->next());
294 map->set_callee_saved(STACK_OFFSET( r10H_off ), r10->as_VMReg()->next());
295 map->set_callee_saved(STACK_OFFSET( r11H_off ), r11->as_VMReg()->next());
296 map->set_callee_saved(STACK_OFFSET( r12H_off ), r12->as_VMReg()->next());
297 map->set_callee_saved(STACK_OFFSET( r13H_off ), r13->as_VMReg()->next());
298 map->set_callee_saved(STACK_OFFSET( r14H_off ), r14->as_VMReg()->next());
299 map->set_callee_saved(STACK_OFFSET( r15H_off ), r15->as_VMReg()->next());
300 // For both AVX and EVEX we will use the legacy FXSAVE area for xmm0..xmm15,
301 // on EVEX enabled targets, we get it included in the xsave area
302 off = xmm0H_off;
303 delta = xmm1H_off - off;
304 for (int n = 0; n < 16; n++) {
305 XMMRegister xmm_name = as_XMMRegister(n);
306 map->set_callee_saved(STACK_OFFSET(off), xmm_name->as_VMReg()->next());
307 off += delta;
308 }
309 if (UseAVX > 2) {
310 // Obtain xmm16..xmm31 from the XSAVE area on EVEX enabled targets
311 off = zmm16H_off;
312 delta = zmm17H_off - off;
313 for (int n = 16; n < num_xmm_regs; n++) {
314 XMMRegister zmm_name = as_XMMRegister(n);
315 map->set_callee_saved(STACK_OFFSET(off), zmm_name->as_VMReg()->next());
316 off += delta;
317 }
318 }
319 }
320
321 return map;
322 }
323
324 void RegisterSaver::restore_live_registers(MacroAssembler* masm, bool restore_vectors) {
325 int num_xmm_regs = XMMRegisterImpl::number_of_registers;
326 if (UseAVX < 3) {
327 num_xmm_regs = num_xmm_regs/2;
328 }
329 if (frame::arg_reg_save_area_bytes != 0) {
330 // Pop arg register save area
331 __ addptr(rsp, frame::arg_reg_save_area_bytes);
332 }
333
334 #if COMPILER2_OR_JVMCI
335 if (restore_vectors) {
336 assert(UseAVX > 0, "Vectors larger than 16 byte long are supported only with AVX");
337 assert(MaxVectorSize <= 64, "Only up to 64 byte long vectors are supported");
338 }
339 #else
340 assert(!restore_vectors, "vectors are generated only by C2");
341 #endif
342
343 __ vzeroupper();
344
345 // On EVEX enabled targets everything is handled in pop fpu state
346 if (restore_vectors) {
347 // Restore upper half of YMM registers (0..15)
348 int base_addr = XSAVE_AREA_YMM_BEGIN;
349 for (int n = 0; n < 16; n++) {
350 __ vinsertf128_high(as_XMMRegister(n), Address(rsp, base_addr+n*16));
351 }
352 if (VM_Version::supports_evex()) {
353 // Restore upper half of ZMM registers (0..15)
354 base_addr = XSAVE_AREA_ZMM_BEGIN;
355 for (int n = 0; n < 16; n++) {
356 __ vinsertf64x4_high(as_XMMRegister(n), Address(rsp, base_addr+n*32));
357 }
358 // Restore full ZMM registers(16..num_xmm_regs)
359 base_addr = XSAVE_AREA_UPPERBANK;
360 int vector_len = Assembler::AVX_512bit;
361 int off = 0;
362 for (int n = 16; n < num_xmm_regs; n++) {
363 __ evmovdqul(as_XMMRegister(n), Address(rsp, base_addr+(off++*64)), vector_len);
364 }
365 }
366 } else {
367 if (VM_Version::supports_evex()) {
368 // Restore upper bank of ZMM registers(16..31) for double/float usage
369 int base_addr = XSAVE_AREA_UPPERBANK;
370 int off = 0;
371 for (int n = 16; n < num_xmm_regs; n++) {
372 __ movsd(as_XMMRegister(n), Address(rsp, base_addr+(off++*64)));
373 }
374 }
375 }
376
377 // Recover CPU state
378 __ pop_CPU_state();
379 // Get the rbp described implicitly by the calling convention (no oopMap)
380 __ pop(rbp);
381 }
382
383 void RegisterSaver::restore_result_registers(MacroAssembler* masm) {
384
385 // Just restore result register. Only used by deoptimization. By
386 // now any callee save register that needs to be restored to a c2
387 // caller of the deoptee has been extracted into the vframeArray
388 // and will be stuffed into the c2i adapter we create for later
389 // restoration so only result registers need to be restored here.
390
391 // Restore fp result register
392 __ movdbl(xmm0, Address(rsp, xmm0_offset_in_bytes()));
393 // Restore integer result register
394 __ movptr(rax, Address(rsp, rax_offset_in_bytes()));
395 __ movptr(rdx, Address(rsp, rdx_offset_in_bytes()));
396
397 // Pop all of the register save are off the stack except the return address
398 __ addptr(rsp, return_offset_in_bytes());
399 }
400
401 // Is vector's size (in bytes) bigger than a size saved by default?
402 // 16 bytes XMM registers are saved by default using fxsave/fxrstor instructions.
403 bool SharedRuntime::is_wide_vector(int size) {
404 return size > 16;
405 }
406
407 size_t SharedRuntime::trampoline_size() {
408 return 16;
409 }
410
411 void SharedRuntime::generate_trampoline(MacroAssembler *masm, address destination) {
412 __ jump(RuntimeAddress(destination));
413 }
414
415 // The java_calling_convention describes stack locations as ideal slots on
416 // a frame with no abi restrictions. Since we must observe abi restrictions
417 // (like the placement of the register window) the slots must be biased by
418 // the following value.
419 static int reg2offset_in(VMReg r) {
420 // Account for saved rbp and return address
421 // This should really be in_preserve_stack_slots
422 return (r->reg2stack() + 4) * VMRegImpl::stack_slot_size;
423 }
424
425 static int reg2offset_out(VMReg r) {
426 return (r->reg2stack() + SharedRuntime::out_preserve_stack_slots()) * VMRegImpl::stack_slot_size;
427 }
428
429 // ---------------------------------------------------------------------------
430 // Read the array of BasicTypes from a signature, and compute where the
431 // arguments should go. Values in the VMRegPair regs array refer to 4-byte
432 // quantities. Values less than VMRegImpl::stack0 are registers, those above
433 // refer to 4-byte stack slots. All stack slots are based off of the stack pointer
434 // as framesizes are fixed.
435 // VMRegImpl::stack0 refers to the first slot 0(sp).
436 // and VMRegImpl::stack0+1 refers to the memory word 4-byes higher. Register
437 // up to RegisterImpl::number_of_registers) are the 64-bit
438 // integer registers.
439
440 // Note: the INPUTS in sig_bt are in units of Java argument words, which are
441 // either 32-bit or 64-bit depending on the build. The OUTPUTS are in 32-bit
442 // units regardless of build. Of course for i486 there is no 64 bit build
443
444 // The Java calling convention is a "shifted" version of the C ABI.
445 // By skipping the first C ABI register we can call non-static jni methods
446 // with small numbers of arguments without having to shuffle the arguments
447 // at all. Since we control the java ABI we ought to at least get some
448 // advantage out of it.
449
450 int SharedRuntime::java_calling_convention(const BasicType *sig_bt,
451 VMRegPair *regs,
452 int total_args_passed,
453 int is_outgoing) {
454
455 // Create the mapping between argument positions and
456 // registers.
457 static const Register INT_ArgReg[Argument::n_int_register_parameters_j] = {
458 j_rarg0, j_rarg1, j_rarg2, j_rarg3, j_rarg4, j_rarg5
459 };
460 static const XMMRegister FP_ArgReg[Argument::n_float_register_parameters_j] = {
461 j_farg0, j_farg1, j_farg2, j_farg3,
462 j_farg4, j_farg5, j_farg6, j_farg7
463 };
464
465
466 uint int_args = 0;
467 uint fp_args = 0;
468 uint stk_args = 0; // inc by 2 each time
469
470 for (int i = 0; i < total_args_passed; i++) {
471 switch (sig_bt[i]) {
472 case T_BOOLEAN:
473 case T_CHAR:
474 case T_BYTE:
475 case T_SHORT:
476 case T_INT:
477 if (int_args < Argument::n_int_register_parameters_j) {
478 regs[i].set1(INT_ArgReg[int_args++]->as_VMReg());
479 } else {
480 regs[i].set1(VMRegImpl::stack2reg(stk_args));
481 stk_args += 2;
482 }
483 break;
484 case T_VOID:
485 // halves of T_LONG or T_DOUBLE
486 assert(i != 0 && (sig_bt[i - 1] == T_LONG || sig_bt[i - 1] == T_DOUBLE), "expecting half");
487 regs[i].set_bad();
488 break;
489 case T_LONG:
490 assert((i + 1) < total_args_passed && sig_bt[i + 1] == T_VOID, "expecting half");
491 // fall through
492 case T_OBJECT:
493 case T_ARRAY:
494 case T_ADDRESS:
495 if (int_args < Argument::n_int_register_parameters_j) {
496 regs[i].set2(INT_ArgReg[int_args++]->as_VMReg());
497 } else {
498 regs[i].set2(VMRegImpl::stack2reg(stk_args));
499 stk_args += 2;
500 }
501 break;
502 case T_FLOAT:
503 if (fp_args < Argument::n_float_register_parameters_j) {
504 regs[i].set1(FP_ArgReg[fp_args++]->as_VMReg());
505 } else {
506 regs[i].set1(VMRegImpl::stack2reg(stk_args));
507 stk_args += 2;
508 }
509 break;
510 case T_DOUBLE:
511 assert((i + 1) < total_args_passed && sig_bt[i + 1] == T_VOID, "expecting half");
512 if (fp_args < Argument::n_float_register_parameters_j) {
513 regs[i].set2(FP_ArgReg[fp_args++]->as_VMReg());
514 } else {
515 regs[i].set2(VMRegImpl::stack2reg(stk_args));
516 stk_args += 2;
517 }
518 break;
519 default:
520 ShouldNotReachHere();
521 break;
522 }
523 }
524
525 return align_up(stk_args, 2);
526 }
527
528 // Patch the callers callsite with entry to compiled code if it exists.
529 static void patch_callers_callsite(MacroAssembler *masm) {
530 Label L;
531 __ cmpptr(Address(rbx, in_bytes(Method::code_offset())), (int32_t)NULL_WORD);
532 __ jcc(Assembler::equal, L);
533
534 // Save the current stack pointer
535 __ mov(r13, rsp);
536 // Schedule the branch target address early.
537 // Call into the VM to patch the caller, then jump to compiled callee
538 // rax isn't live so capture return address while we easily can
539 __ movptr(rax, Address(rsp, 0));
540
541 // align stack so push_CPU_state doesn't fault
542 __ andptr(rsp, -(StackAlignmentInBytes));
543 __ push_CPU_state();
544 __ vzeroupper();
545 // VM needs caller's callsite
546 // VM needs target method
547 // This needs to be a long call since we will relocate this adapter to
548 // the codeBuffer and it may not reach
549
550 // Allocate argument register save area
551 if (frame::arg_reg_save_area_bytes != 0) {
552 __ subptr(rsp, frame::arg_reg_save_area_bytes);
553 }
554 __ mov(c_rarg0, rbx);
555 __ mov(c_rarg1, rax);
556 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, SharedRuntime::fixup_callers_callsite)));
557
558 // De-allocate argument register save area
559 if (frame::arg_reg_save_area_bytes != 0) {
560 __ addptr(rsp, frame::arg_reg_save_area_bytes);
561 }
562
563 __ vzeroupper();
564 __ pop_CPU_state();
565 // restore sp
566 __ mov(rsp, r13);
567 __ bind(L);
568 }
569
570
571 static void gen_c2i_adapter(MacroAssembler *masm,
572 int total_args_passed,
573 int comp_args_on_stack,
574 const BasicType *sig_bt,
575 const VMRegPair *regs,
576 Label& skip_fixup) {
577 // Before we get into the guts of the C2I adapter, see if we should be here
578 // at all. We've come from compiled code and are attempting to jump to the
579 // interpreter, which means the caller made a static call to get here
580 // (vcalls always get a compiled target if there is one). Check for a
581 // compiled target. If there is one, we need to patch the caller's call.
582 patch_callers_callsite(masm);
583
584 __ bind(skip_fixup);
585
586 // Since all args are passed on the stack, total_args_passed *
587 // Interpreter::stackElementSize is the space we need. Plus 1 because
588 // we also account for the return address location since
589 // we store it first rather than hold it in rax across all the shuffling
590
591 int extraspace = (total_args_passed * Interpreter::stackElementSize) + wordSize;
592
593 // stack is aligned, keep it that way
594 extraspace = align_up(extraspace, 2*wordSize);
595
596 // Get return address
597 __ pop(rax);
598
599 // set senderSP value
600 __ mov(r13, rsp);
601
602 __ subptr(rsp, extraspace);
603
604 // Store the return address in the expected location
605 __ movptr(Address(rsp, 0), rax);
606
607 // Now write the args into the outgoing interpreter space
608 for (int i = 0; i < total_args_passed; i++) {
609 if (sig_bt[i] == T_VOID) {
610 assert(i > 0 && (sig_bt[i-1] == T_LONG || sig_bt[i-1] == T_DOUBLE), "missing half");
611 continue;
612 }
613
614 // offset to start parameters
615 int st_off = (total_args_passed - i) * Interpreter::stackElementSize;
616 int next_off = st_off - Interpreter::stackElementSize;
617
618 // Say 4 args:
619 // i st_off
620 // 0 32 T_LONG
621 // 1 24 T_VOID
622 // 2 16 T_OBJECT
623 // 3 8 T_BOOL
624 // - 0 return address
625 //
626 // However to make thing extra confusing. Because we can fit a long/double in
627 // a single slot on a 64 bt vm and it would be silly to break them up, the interpreter
628 // leaves one slot empty and only stores to a single slot. In this case the
629 // slot that is occupied is the T_VOID slot. See I said it was confusing.
630
631 VMReg r_1 = regs[i].first();
632 VMReg r_2 = regs[i].second();
633 if (!r_1->is_valid()) {
634 assert(!r_2->is_valid(), "");
635 continue;
636 }
637 if (r_1->is_stack()) {
638 // memory to memory use rax
639 int ld_off = r_1->reg2stack() * VMRegImpl::stack_slot_size + extraspace;
640 if (!r_2->is_valid()) {
641 // sign extend??
642 __ movl(rax, Address(rsp, ld_off));
643 __ movptr(Address(rsp, st_off), rax);
644
645 } else {
646
647 __ movq(rax, Address(rsp, ld_off));
648
649 // Two VMREgs|OptoRegs can be T_OBJECT, T_ADDRESS, T_DOUBLE, T_LONG
650 // T_DOUBLE and T_LONG use two slots in the interpreter
651 if ( sig_bt[i] == T_LONG || sig_bt[i] == T_DOUBLE) {
652 // ld_off == LSW, ld_off+wordSize == MSW
653 // st_off == MSW, next_off == LSW
654 __ movq(Address(rsp, next_off), rax);
655 #ifdef ASSERT
656 // Overwrite the unused slot with known junk
657 __ mov64(rax, CONST64(0xdeadffffdeadaaaa));
658 __ movptr(Address(rsp, st_off), rax);
659 #endif /* ASSERT */
660 } else {
661 __ movq(Address(rsp, st_off), rax);
662 }
663 }
664 } else if (r_1->is_Register()) {
665 Register r = r_1->as_Register();
666 if (!r_2->is_valid()) {
667 // must be only an int (or less ) so move only 32bits to slot
668 // why not sign extend??
669 __ movl(Address(rsp, st_off), r);
670 } else {
671 // Two VMREgs|OptoRegs can be T_OBJECT, T_ADDRESS, T_DOUBLE, T_LONG
672 // T_DOUBLE and T_LONG use two slots in the interpreter
673 if ( sig_bt[i] == T_LONG || sig_bt[i] == T_DOUBLE) {
674 // long/double in gpr
675 #ifdef ASSERT
676 // Overwrite the unused slot with known junk
677 __ mov64(rax, CONST64(0xdeadffffdeadaaab));
678 __ movptr(Address(rsp, st_off), rax);
679 #endif /* ASSERT */
680 __ movq(Address(rsp, next_off), r);
681 } else {
682 __ movptr(Address(rsp, st_off), r);
683 }
684 }
685 } else {
686 assert(r_1->is_XMMRegister(), "");
687 if (!r_2->is_valid()) {
688 // only a float use just part of the slot
689 __ movflt(Address(rsp, st_off), r_1->as_XMMRegister());
690 } else {
691 #ifdef ASSERT
692 // Overwrite the unused slot with known junk
693 __ mov64(rax, CONST64(0xdeadffffdeadaaac));
694 __ movptr(Address(rsp, st_off), rax);
695 #endif /* ASSERT */
696 __ movdbl(Address(rsp, next_off), r_1->as_XMMRegister());
697 }
698 }
699 }
700
701 // Schedule the branch target address early.
702 __ movptr(rcx, Address(rbx, in_bytes(Method::interpreter_entry_offset())));
703 __ jmp(rcx);
704 }
705
706 static void range_check(MacroAssembler* masm, Register pc_reg, Register temp_reg,
707 address code_start, address code_end,
708 Label& L_ok) {
709 Label L_fail;
710 __ lea(temp_reg, ExternalAddress(code_start));
711 __ cmpptr(pc_reg, temp_reg);
712 __ jcc(Assembler::belowEqual, L_fail);
713 __ lea(temp_reg, ExternalAddress(code_end));
714 __ cmpptr(pc_reg, temp_reg);
715 __ jcc(Assembler::below, L_ok);
716 __ bind(L_fail);
717 }
718
719 void SharedRuntime::gen_i2c_adapter(MacroAssembler *masm,
720 int total_args_passed,
721 int comp_args_on_stack,
722 const BasicType *sig_bt,
723 const VMRegPair *regs) {
724
725 // Note: r13 contains the senderSP on entry. We must preserve it since
726 // we may do a i2c -> c2i transition if we lose a race where compiled
727 // code goes non-entrant while we get args ready.
728 // In addition we use r13 to locate all the interpreter args as
729 // we must align the stack to 16 bytes on an i2c entry else we
730 // lose alignment we expect in all compiled code and register
731 // save code can segv when fxsave instructions find improperly
732 // aligned stack pointer.
733
734 // Adapters can be frameless because they do not require the caller
735 // to perform additional cleanup work, such as correcting the stack pointer.
736 // An i2c adapter is frameless because the *caller* frame, which is interpreted,
737 // routinely repairs its own stack pointer (from interpreter_frame_last_sp),
738 // even if a callee has modified the stack pointer.
739 // A c2i adapter is frameless because the *callee* frame, which is interpreted,
740 // routinely repairs its caller's stack pointer (from sender_sp, which is set
741 // up via the senderSP register).
742 // In other words, if *either* the caller or callee is interpreted, we can
743 // get the stack pointer repaired after a call.
744 // This is why c2i and i2c adapters cannot be indefinitely composed.
745 // In particular, if a c2i adapter were to somehow call an i2c adapter,
746 // both caller and callee would be compiled methods, and neither would
747 // clean up the stack pointer changes performed by the two adapters.
748 // If this happens, control eventually transfers back to the compiled
749 // caller, but with an uncorrected stack, causing delayed havoc.
750
751 // Pick up the return address
752 __ movptr(rax, Address(rsp, 0));
753
754 if (VerifyAdapterCalls &&
755 (Interpreter::code() != NULL || StubRoutines::code1() != NULL)) {
756 // So, let's test for cascading c2i/i2c adapters right now.
757 // assert(Interpreter::contains($return_addr) ||
758 // StubRoutines::contains($return_addr),
759 // "i2c adapter must return to an interpreter frame");
760 __ block_comment("verify_i2c { ");
761 Label L_ok;
762 if (Interpreter::code() != NULL)
763 range_check(masm, rax, r11,
764 Interpreter::code()->code_start(), Interpreter::code()->code_end(),
765 L_ok);
766 if (StubRoutines::code1() != NULL)
767 range_check(masm, rax, r11,
768 StubRoutines::code1()->code_begin(), StubRoutines::code1()->code_end(),
769 L_ok);
770 if (StubRoutines::code2() != NULL)
771 range_check(masm, rax, r11,
772 StubRoutines::code2()->code_begin(), StubRoutines::code2()->code_end(),
773 L_ok);
774 const char* msg = "i2c adapter must return to an interpreter frame";
775 __ block_comment(msg);
776 __ stop(msg);
777 __ bind(L_ok);
778 __ block_comment("} verify_i2ce ");
779 }
780
781 // Must preserve original SP for loading incoming arguments because
782 // we need to align the outgoing SP for compiled code.
783 __ movptr(r11, rsp);
784
785 // Cut-out for having no stack args. Since up to 2 int/oop args are passed
786 // in registers, we will occasionally have no stack args.
787 int comp_words_on_stack = 0;
788 if (comp_args_on_stack) {
789 // Sig words on the stack are greater-than VMRegImpl::stack0. Those in
790 // registers are below. By subtracting stack0, we either get a negative
791 // number (all values in registers) or the maximum stack slot accessed.
792
793 // Convert 4-byte c2 stack slots to words.
794 comp_words_on_stack = align_up(comp_args_on_stack*VMRegImpl::stack_slot_size, wordSize)>>LogBytesPerWord;
795 // Round up to miminum stack alignment, in wordSize
796 comp_words_on_stack = align_up(comp_words_on_stack, 2);
797 __ subptr(rsp, comp_words_on_stack * wordSize);
798 }
799
800
801 // Ensure compiled code always sees stack at proper alignment
802 __ andptr(rsp, -16);
803
804 // push the return address and misalign the stack that youngest frame always sees
805 // as far as the placement of the call instruction
806 __ push(rax);
807
808 // Put saved SP in another register
809 const Register saved_sp = rax;
810 __ movptr(saved_sp, r11);
811
812 // Will jump to the compiled code just as if compiled code was doing it.
813 // Pre-load the register-jump target early, to schedule it better.
814 __ movptr(r11, Address(rbx, in_bytes(Method::from_compiled_offset())));
815
816 #if INCLUDE_JVMCI
817 if (EnableJVMCI || UseAOT) {
818 // check if this call should be routed towards a specific entry point
819 __ cmpptr(Address(r15_thread, in_bytes(JavaThread::jvmci_alternate_call_target_offset())), 0);
820 Label no_alternative_target;
821 __ jcc(Assembler::equal, no_alternative_target);
822 __ movptr(r11, Address(r15_thread, in_bytes(JavaThread::jvmci_alternate_call_target_offset())));
823 __ movptr(Address(r15_thread, in_bytes(JavaThread::jvmci_alternate_call_target_offset())), 0);
824 __ bind(no_alternative_target);
825 }
826 #endif // INCLUDE_JVMCI
827
828 // Now generate the shuffle code. Pick up all register args and move the
829 // rest through the floating point stack top.
830 for (int i = 0; i < total_args_passed; i++) {
831 if (sig_bt[i] == T_VOID) {
832 // Longs and doubles are passed in native word order, but misaligned
833 // in the 32-bit build.
834 assert(i > 0 && (sig_bt[i-1] == T_LONG || sig_bt[i-1] == T_DOUBLE), "missing half");
835 continue;
836 }
837
838 // Pick up 0, 1 or 2 words from SP+offset.
839
840 assert(!regs[i].second()->is_valid() || regs[i].first()->next() == regs[i].second(),
841 "scrambled load targets?");
842 // Load in argument order going down.
843 int ld_off = (total_args_passed - i)*Interpreter::stackElementSize;
844 // Point to interpreter value (vs. tag)
845 int next_off = ld_off - Interpreter::stackElementSize;
846 //
847 //
848 //
849 VMReg r_1 = regs[i].first();
850 VMReg r_2 = regs[i].second();
851 if (!r_1->is_valid()) {
852 assert(!r_2->is_valid(), "");
853 continue;
854 }
855 if (r_1->is_stack()) {
856 // Convert stack slot to an SP offset (+ wordSize to account for return address )
857 int st_off = regs[i].first()->reg2stack()*VMRegImpl::stack_slot_size + wordSize;
858
859 // We can use r13 as a temp here because compiled code doesn't need r13 as an input
860 // and if we end up going thru a c2i because of a miss a reasonable value of r13
861 // will be generated.
862 if (!r_2->is_valid()) {
863 // sign extend???
864 __ movl(r13, Address(saved_sp, ld_off));
865 __ movptr(Address(rsp, st_off), r13);
866 } else {
867 //
868 // We are using two optoregs. This can be either T_OBJECT, T_ADDRESS, T_LONG, or T_DOUBLE
869 // the interpreter allocates two slots but only uses one for thr T_LONG or T_DOUBLE case
870 // So we must adjust where to pick up the data to match the interpreter.
871 //
872 // Interpreter local[n] == MSW, local[n+1] == LSW however locals
873 // are accessed as negative so LSW is at LOW address
874
875 // ld_off is MSW so get LSW
876 const int offset = (sig_bt[i]==T_LONG||sig_bt[i]==T_DOUBLE)?
877 next_off : ld_off;
878 __ movq(r13, Address(saved_sp, offset));
879 // st_off is LSW (i.e. reg.first())
880 __ movq(Address(rsp, st_off), r13);
881 }
882 } else if (r_1->is_Register()) { // Register argument
883 Register r = r_1->as_Register();
884 assert(r != rax, "must be different");
885 if (r_2->is_valid()) {
886 //
887 // We are using two VMRegs. This can be either T_OBJECT, T_ADDRESS, T_LONG, or T_DOUBLE
888 // the interpreter allocates two slots but only uses one for thr T_LONG or T_DOUBLE case
889 // So we must adjust where to pick up the data to match the interpreter.
890
891 const int offset = (sig_bt[i]==T_LONG||sig_bt[i]==T_DOUBLE)?
892 next_off : ld_off;
893
894 // this can be a misaligned move
895 __ movq(r, Address(saved_sp, offset));
896 } else {
897 // sign extend and use a full word?
898 __ movl(r, Address(saved_sp, ld_off));
899 }
900 } else {
901 if (!r_2->is_valid()) {
902 __ movflt(r_1->as_XMMRegister(), Address(saved_sp, ld_off));
903 } else {
904 __ movdbl(r_1->as_XMMRegister(), Address(saved_sp, next_off));
905 }
906 }
907 }
908
909 // 6243940 We might end up in handle_wrong_method if
910 // the callee is deoptimized as we race thru here. If that
911 // happens we don't want to take a safepoint because the
912 // caller frame will look interpreted and arguments are now
913 // "compiled" so it is much better to make this transition
914 // invisible to the stack walking code. Unfortunately if
915 // we try and find the callee by normal means a safepoint
916 // is possible. So we stash the desired callee in the thread
917 // and the vm will find there should this case occur.
918
919 __ movptr(Address(r15_thread, JavaThread::callee_target_offset()), rbx);
920
921 // put Method* where a c2i would expect should we end up there
922 // only needed becaus eof c2 resolve stubs return Method* as a result in
923 // rax
924 __ mov(rax, rbx);
925 __ jmp(r11);
926 }
927
928 // ---------------------------------------------------------------
929 AdapterHandlerEntry* SharedRuntime::generate_i2c2i_adapters(MacroAssembler *masm,
930 int total_args_passed,
931 int comp_args_on_stack,
932 const BasicType *sig_bt,
933 const VMRegPair *regs,
934 AdapterFingerPrint* fingerprint) {
935 address i2c_entry = __ pc();
936
937 gen_i2c_adapter(masm, total_args_passed, comp_args_on_stack, sig_bt, regs);
938
939 // -------------------------------------------------------------------------
940 // Generate a C2I adapter. On entry we know rbx holds the Method* during calls
941 // to the interpreter. The args start out packed in the compiled layout. They
942 // need to be unpacked into the interpreter layout. This will almost always
943 // require some stack space. We grow the current (compiled) stack, then repack
944 // the args. We finally end in a jump to the generic interpreter entry point.
945 // On exit from the interpreter, the interpreter will restore our SP (lest the
946 // compiled code, which relys solely on SP and not RBP, get sick).
947
948 address c2i_unverified_entry = __ pc();
949 Label skip_fixup;
950 Label ok;
951
952 Register holder = rax;
953 Register receiver = j_rarg0;
954 Register temp = rbx;
955
956 {
957 __ load_klass(temp, receiver);
958 __ cmpptr(temp, Address(holder, CompiledICHolder::holder_klass_offset()));
959 __ movptr(rbx, Address(holder, CompiledICHolder::holder_metadata_offset()));
960 __ jcc(Assembler::equal, ok);
961 __ jump(RuntimeAddress(SharedRuntime::get_ic_miss_stub()));
962
963 __ bind(ok);
964 // Method might have been compiled since the call site was patched to
965 // interpreted if that is the case treat it as a miss so we can get
966 // the call site corrected.
967 __ cmpptr(Address(rbx, in_bytes(Method::code_offset())), (int32_t)NULL_WORD);
968 __ jcc(Assembler::equal, skip_fixup);
969 __ jump(RuntimeAddress(SharedRuntime::get_ic_miss_stub()));
970 }
971
972 address c2i_entry = __ pc();
973
974 // Class initialization barrier for static methods
975 address c2i_no_clinit_check_entry = NULL;
976 if (VM_Version::supports_fast_class_init_checks()) {
977 Label L_skip_barrier;
978 Register method = rbx;
979
980 { // Bypass the barrier for non-static methods
981 Register flags = rscratch1;
982 __ movl(flags, Address(method, Method::access_flags_offset()));
983 __ testl(flags, JVM_ACC_STATIC);
984 __ jcc(Assembler::zero, L_skip_barrier); // non-static
985 }
986
987 Register klass = rscratch1;
988 __ load_method_holder(klass, method);
989 __ clinit_barrier(klass, r15_thread, &L_skip_barrier /*L_fast_path*/);
990
991 __ jump(RuntimeAddress(SharedRuntime::get_handle_wrong_method_stub())); // slow path
992
993 __ bind(L_skip_barrier);
994 c2i_no_clinit_check_entry = __ pc();
995 }
996
997 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
998 bs->c2i_entry_barrier(masm);
999
1000 gen_c2i_adapter(masm, total_args_passed, comp_args_on_stack, sig_bt, regs, skip_fixup);
1001
1002 __ flush();
1003 return AdapterHandlerLibrary::new_entry(fingerprint, i2c_entry, c2i_entry, c2i_unverified_entry, c2i_no_clinit_check_entry);
1004 }
1005
1006 int SharedRuntime::c_calling_convention(const BasicType *sig_bt,
1007 VMRegPair *regs,
1008 VMRegPair *regs2,
1009 int total_args_passed) {
1010 assert(regs2 == NULL, "not needed on x86");
1011 // We return the amount of VMRegImpl stack slots we need to reserve for all
1012 // the arguments NOT counting out_preserve_stack_slots.
1013
1014 // NOTE: These arrays will have to change when c1 is ported
1015 #ifdef _WIN64
1016 static const Register INT_ArgReg[Argument::n_int_register_parameters_c] = {
1017 c_rarg0, c_rarg1, c_rarg2, c_rarg3
1018 };
1019 static const XMMRegister FP_ArgReg[Argument::n_float_register_parameters_c] = {
1020 c_farg0, c_farg1, c_farg2, c_farg3
1021 };
1022 #else
1023 static const Register INT_ArgReg[Argument::n_int_register_parameters_c] = {
1024 c_rarg0, c_rarg1, c_rarg2, c_rarg3, c_rarg4, c_rarg5
1025 };
1026 static const XMMRegister FP_ArgReg[Argument::n_float_register_parameters_c] = {
1027 c_farg0, c_farg1, c_farg2, c_farg3,
1028 c_farg4, c_farg5, c_farg6, c_farg7
1029 };
1030 #endif // _WIN64
1031
1032
1033 uint int_args = 0;
1034 uint fp_args = 0;
1035 uint stk_args = 0; // inc by 2 each time
1036
1037 for (int i = 0; i < total_args_passed; i++) {
1038 switch (sig_bt[i]) {
1039 case T_BOOLEAN:
1040 case T_CHAR:
1041 case T_BYTE:
1042 case T_SHORT:
1043 case T_INT:
1044 if (int_args < Argument::n_int_register_parameters_c) {
1045 regs[i].set1(INT_ArgReg[int_args++]->as_VMReg());
1046 #ifdef _WIN64
1047 fp_args++;
1048 // Allocate slots for callee to stuff register args the stack.
1049 stk_args += 2;
1050 #endif
1051 } else {
1052 regs[i].set1(VMRegImpl::stack2reg(stk_args));
1053 stk_args += 2;
1054 }
1055 break;
1056 case T_LONG:
1057 assert((i + 1) < total_args_passed && sig_bt[i + 1] == T_VOID, "expecting half");
1058 // fall through
1059 case T_OBJECT:
1060 case T_ARRAY:
1061 case T_ADDRESS:
1062 case T_METADATA:
1063 if (int_args < Argument::n_int_register_parameters_c) {
1064 regs[i].set2(INT_ArgReg[int_args++]->as_VMReg());
1065 #ifdef _WIN64
1066 fp_args++;
1067 stk_args += 2;
1068 #endif
1069 } else {
1070 regs[i].set2(VMRegImpl::stack2reg(stk_args));
1071 stk_args += 2;
1072 }
1073 break;
1074 case T_FLOAT:
1075 if (fp_args < Argument::n_float_register_parameters_c) {
1076 regs[i].set1(FP_ArgReg[fp_args++]->as_VMReg());
1077 #ifdef _WIN64
1078 int_args++;
1079 // Allocate slots for callee to stuff register args the stack.
1080 stk_args += 2;
1081 #endif
1082 } else {
1083 regs[i].set1(VMRegImpl::stack2reg(stk_args));
1084 stk_args += 2;
1085 }
1086 break;
1087 case T_DOUBLE:
1088 assert((i + 1) < total_args_passed && sig_bt[i + 1] == T_VOID, "expecting half");
1089 if (fp_args < Argument::n_float_register_parameters_c) {
1090 regs[i].set2(FP_ArgReg[fp_args++]->as_VMReg());
1091 #ifdef _WIN64
1092 int_args++;
1093 // Allocate slots for callee to stuff register args the stack.
1094 stk_args += 2;
1095 #endif
1096 } else {
1097 regs[i].set2(VMRegImpl::stack2reg(stk_args));
1098 stk_args += 2;
1099 }
1100 break;
1101 case T_VOID: // Halves of longs and doubles
1102 assert(i != 0 && (sig_bt[i - 1] == T_LONG || sig_bt[i - 1] == T_DOUBLE), "expecting half");
1103 regs[i].set_bad();
1104 break;
1105 default:
1106 ShouldNotReachHere();
1107 break;
1108 }
1109 }
1110 #ifdef _WIN64
1111 // windows abi requires that we always allocate enough stack space
1112 // for 4 64bit registers to be stored down.
1113 if (stk_args < 8) {
1114 stk_args = 8;
1115 }
1116 #endif // _WIN64
1117
1118 return stk_args;
1119 }
1120
1121 // On 64 bit we will store integer like items to the stack as
1122 // 64 bits items (sparc abi) even though java would only store
1123 // 32bits for a parameter. On 32bit it will simply be 32 bits
1124 // So this routine will do 32->32 on 32bit and 32->64 on 64bit
1125 static void move32_64(MacroAssembler* masm, VMRegPair src, VMRegPair dst) {
1126 if (src.first()->is_stack()) {
1127 if (dst.first()->is_stack()) {
1128 // stack to stack
1129 __ movslq(rax, Address(rbp, reg2offset_in(src.first())));
1130 __ movq(Address(rsp, reg2offset_out(dst.first())), rax);
1131 } else {
1132 // stack to reg
1133 __ movslq(dst.first()->as_Register(), Address(rbp, reg2offset_in(src.first())));
1134 }
1135 } else if (dst.first()->is_stack()) {
1136 // reg to stack
1137 // Do we really have to sign extend???
1138 // __ movslq(src.first()->as_Register(), src.first()->as_Register());
1139 __ movq(Address(rsp, reg2offset_out(dst.first())), src.first()->as_Register());
1140 } else {
1141 // Do we really have to sign extend???
1142 // __ movslq(dst.first()->as_Register(), src.first()->as_Register());
1143 if (dst.first() != src.first()) {
1144 __ movq(dst.first()->as_Register(), src.first()->as_Register());
1145 }
1146 }
1147 }
1148
1149 static void move_ptr(MacroAssembler* masm, VMRegPair src, VMRegPair dst) {
1150 if (src.first()->is_stack()) {
1151 if (dst.first()->is_stack()) {
1152 // stack to stack
1153 __ movq(rax, Address(rbp, reg2offset_in(src.first())));
1154 __ movq(Address(rsp, reg2offset_out(dst.first())), rax);
1155 } else {
1156 // stack to reg
1157 __ movq(dst.first()->as_Register(), Address(rbp, reg2offset_in(src.first())));
1158 }
1159 } else if (dst.first()->is_stack()) {
1160 // reg to stack
1161 __ movq(Address(rsp, reg2offset_out(dst.first())), src.first()->as_Register());
1162 } else {
1163 if (dst.first() != src.first()) {
1164 __ movq(dst.first()->as_Register(), src.first()->as_Register());
1165 }
1166 }
1167 }
1168
1169 // An oop arg. Must pass a handle not the oop itself
1170 static void object_move(MacroAssembler* masm,
1171 OopMap* map,
1172 int oop_handle_offset,
1173 int framesize_in_slots,
1174 VMRegPair src,
1175 VMRegPair dst,
1176 bool is_receiver,
1177 int* receiver_offset) {
1178
1179 // must pass a handle. First figure out the location we use as a handle
1180
1181 Register rHandle = dst.first()->is_stack() ? rax : dst.first()->as_Register();
1182
1183 // See if oop is NULL if it is we need no handle
1184
1185 if (src.first()->is_stack()) {
1186
1187 // Oop is already on the stack as an argument
1188 int offset_in_older_frame = src.first()->reg2stack() + SharedRuntime::out_preserve_stack_slots();
1189 map->set_oop(VMRegImpl::stack2reg(offset_in_older_frame + framesize_in_slots));
1190 if (is_receiver) {
1191 *receiver_offset = (offset_in_older_frame + framesize_in_slots) * VMRegImpl::stack_slot_size;
1192 }
1193
1194 __ cmpptr(Address(rbp, reg2offset_in(src.first())), (int32_t)NULL_WORD);
1195 __ lea(rHandle, Address(rbp, reg2offset_in(src.first())));
1196 // conditionally move a NULL
1197 __ cmovptr(Assembler::equal, rHandle, Address(rbp, reg2offset_in(src.first())));
1198 } else {
1199
1200 // Oop is in an a register we must store it to the space we reserve
1201 // on the stack for oop_handles and pass a handle if oop is non-NULL
1202
1203 const Register rOop = src.first()->as_Register();
1204 int oop_slot;
1205 if (rOop == j_rarg0)
1206 oop_slot = 0;
1207 else if (rOop == j_rarg1)
1208 oop_slot = 1;
1209 else if (rOop == j_rarg2)
1210 oop_slot = 2;
1211 else if (rOop == j_rarg3)
1212 oop_slot = 3;
1213 else if (rOop == j_rarg4)
1214 oop_slot = 4;
1215 else {
1216 assert(rOop == j_rarg5, "wrong register");
1217 oop_slot = 5;
1218 }
1219
1220 oop_slot = oop_slot * VMRegImpl::slots_per_word + oop_handle_offset;
1221 int offset = oop_slot*VMRegImpl::stack_slot_size;
1222
1223 map->set_oop(VMRegImpl::stack2reg(oop_slot));
1224 // Store oop in handle area, may be NULL
1225 __ movptr(Address(rsp, offset), rOop);
1226 if (is_receiver) {
1227 *receiver_offset = offset;
1228 }
1229
1230 __ cmpptr(rOop, (int32_t)NULL_WORD);
1231 __ lea(rHandle, Address(rsp, offset));
1232 // conditionally move a NULL from the handle area where it was just stored
1233 __ cmovptr(Assembler::equal, rHandle, Address(rsp, offset));
1234 }
1235
1236 // If arg is on the stack then place it otherwise it is already in correct reg.
1237 if (dst.first()->is_stack()) {
1238 __ movptr(Address(rsp, reg2offset_out(dst.first())), rHandle);
1239 }
1240 }
1241
1242 // A float arg may have to do float reg int reg conversion
1243 static void float_move(MacroAssembler* masm, VMRegPair src, VMRegPair dst) {
1244 assert(!src.second()->is_valid() && !dst.second()->is_valid(), "bad float_move");
1245
1246 // The calling conventions assures us that each VMregpair is either
1247 // all really one physical register or adjacent stack slots.
1248 // This greatly simplifies the cases here compared to sparc.
1249
1250 if (src.first()->is_stack()) {
1251 if (dst.first()->is_stack()) {
1252 __ movl(rax, Address(rbp, reg2offset_in(src.first())));
1253 __ movptr(Address(rsp, reg2offset_out(dst.first())), rax);
1254 } else {
1255 // stack to reg
1256 assert(dst.first()->is_XMMRegister(), "only expect xmm registers as parameters");
1257 __ movflt(dst.first()->as_XMMRegister(), Address(rbp, reg2offset_in(src.first())));
1258 }
1259 } else if (dst.first()->is_stack()) {
1260 // reg to stack
1261 assert(src.first()->is_XMMRegister(), "only expect xmm registers as parameters");
1262 __ movflt(Address(rsp, reg2offset_out(dst.first())), src.first()->as_XMMRegister());
1263 } else {
1264 // reg to reg
1265 // In theory these overlap but the ordering is such that this is likely a nop
1266 if ( src.first() != dst.first()) {
1267 __ movdbl(dst.first()->as_XMMRegister(), src.first()->as_XMMRegister());
1268 }
1269 }
1270 }
1271
1272 // A long move
1273 static void long_move(MacroAssembler* masm, VMRegPair src, VMRegPair dst) {
1274
1275 // The calling conventions assures us that each VMregpair is either
1276 // all really one physical register or adjacent stack slots.
1277 // This greatly simplifies the cases here compared to sparc.
1278
1279 if (src.is_single_phys_reg() ) {
1280 if (dst.is_single_phys_reg()) {
1281 if (dst.first() != src.first()) {
1282 __ mov(dst.first()->as_Register(), src.first()->as_Register());
1283 }
1284 } else {
1285 assert(dst.is_single_reg(), "not a stack pair");
1286 __ movq(Address(rsp, reg2offset_out(dst.first())), src.first()->as_Register());
1287 }
1288 } else if (dst.is_single_phys_reg()) {
1289 assert(src.is_single_reg(), "not a stack pair");
1290 __ movq(dst.first()->as_Register(), Address(rbp, reg2offset_out(src.first())));
1291 } else {
1292 assert(src.is_single_reg() && dst.is_single_reg(), "not stack pairs");
1293 __ movq(rax, Address(rbp, reg2offset_in(src.first())));
1294 __ movq(Address(rsp, reg2offset_out(dst.first())), rax);
1295 }
1296 }
1297
1298 // A double move
1299 static void double_move(MacroAssembler* masm, VMRegPair src, VMRegPair dst) {
1300
1301 // The calling conventions assures us that each VMregpair is either
1302 // all really one physical register or adjacent stack slots.
1303 // This greatly simplifies the cases here compared to sparc.
1304
1305 if (src.is_single_phys_reg() ) {
1306 if (dst.is_single_phys_reg()) {
1307 // In theory these overlap but the ordering is such that this is likely a nop
1308 if ( src.first() != dst.first()) {
1309 __ movdbl(dst.first()->as_XMMRegister(), src.first()->as_XMMRegister());
1310 }
1311 } else {
1312 assert(dst.is_single_reg(), "not a stack pair");
1313 __ movdbl(Address(rsp, reg2offset_out(dst.first())), src.first()->as_XMMRegister());
1314 }
1315 } else if (dst.is_single_phys_reg()) {
1316 assert(src.is_single_reg(), "not a stack pair");
1317 __ movdbl(dst.first()->as_XMMRegister(), Address(rbp, reg2offset_out(src.first())));
1318 } else {
1319 assert(src.is_single_reg() && dst.is_single_reg(), "not stack pairs");
1320 __ movq(rax, Address(rbp, reg2offset_in(src.first())));
1321 __ movq(Address(rsp, reg2offset_out(dst.first())), rax);
1322 }
1323 }
1324
1325
1326 void SharedRuntime::save_native_result(MacroAssembler *masm, BasicType ret_type, int frame_slots) {
1327 // We always ignore the frame_slots arg and just use the space just below frame pointer
1328 // which by this time is free to use
1329 switch (ret_type) {
1330 case T_FLOAT:
1331 __ movflt(Address(rbp, -wordSize), xmm0);
1332 break;
1333 case T_DOUBLE:
1334 __ movdbl(Address(rbp, -wordSize), xmm0);
1335 break;
1336 case T_VOID: break;
1337 default: {
1338 __ movptr(Address(rbp, -wordSize), rax);
1339 }
1340 }
1341 }
1342
1343 void SharedRuntime::restore_native_result(MacroAssembler *masm, BasicType ret_type, int frame_slots) {
1344 // We always ignore the frame_slots arg and just use the space just below frame pointer
1345 // which by this time is free to use
1346 switch (ret_type) {
1347 case T_FLOAT:
1348 __ movflt(xmm0, Address(rbp, -wordSize));
1349 break;
1350 case T_DOUBLE:
1351 __ movdbl(xmm0, Address(rbp, -wordSize));
1352 break;
1353 case T_VOID: break;
1354 default: {
1355 __ movptr(rax, Address(rbp, -wordSize));
1356 }
1357 }
1358 }
1359
1360 static void save_args(MacroAssembler *masm, int arg_count, int first_arg, VMRegPair *args) {
1361 for ( int i = first_arg ; i < arg_count ; i++ ) {
1362 if (args[i].first()->is_Register()) {
1363 __ push(args[i].first()->as_Register());
1364 } else if (args[i].first()->is_XMMRegister()) {
1365 __ subptr(rsp, 2*wordSize);
1366 __ movdbl(Address(rsp, 0), args[i].first()->as_XMMRegister());
1367 }
1368 }
1369 }
1370
1371 static void restore_args(MacroAssembler *masm, int arg_count, int first_arg, VMRegPair *args) {
1372 for ( int i = arg_count - 1 ; i >= first_arg ; i-- ) {
1373 if (args[i].first()->is_Register()) {
1374 __ pop(args[i].first()->as_Register());
1375 } else if (args[i].first()->is_XMMRegister()) {
1376 __ movdbl(args[i].first()->as_XMMRegister(), Address(rsp, 0));
1377 __ addptr(rsp, 2*wordSize);
1378 }
1379 }
1380 }
1381
1382
1383 static void save_or_restore_arguments(MacroAssembler* masm,
1384 const int stack_slots,
1385 const int total_in_args,
1386 const int arg_save_area,
1387 OopMap* map,
1388 VMRegPair* in_regs,
1389 BasicType* in_sig_bt) {
1390 // if map is non-NULL then the code should store the values,
1391 // otherwise it should load them.
1392 int slot = arg_save_area;
1393 // Save down double word first
1394 for ( int i = 0; i < total_in_args; i++) {
1395 if (in_regs[i].first()->is_XMMRegister() && in_sig_bt[i] == T_DOUBLE) {
1396 int offset = slot * VMRegImpl::stack_slot_size;
1397 slot += VMRegImpl::slots_per_word;
1398 assert(slot <= stack_slots, "overflow");
1399 if (map != NULL) {
1400 __ movdbl(Address(rsp, offset), in_regs[i].first()->as_XMMRegister());
1401 } else {
1402 __ movdbl(in_regs[i].first()->as_XMMRegister(), Address(rsp, offset));
1403 }
1404 }
1405 if (in_regs[i].first()->is_Register() &&
1406 (in_sig_bt[i] == T_LONG || in_sig_bt[i] == T_ARRAY)) {
1407 int offset = slot * VMRegImpl::stack_slot_size;
1408 if (map != NULL) {
1409 __ movq(Address(rsp, offset), in_regs[i].first()->as_Register());
1410 if (in_sig_bt[i] == T_ARRAY) {
1411 map->set_oop(VMRegImpl::stack2reg(slot));;
1412 }
1413 } else {
1414 __ movq(in_regs[i].first()->as_Register(), Address(rsp, offset));
1415 }
1416 slot += VMRegImpl::slots_per_word;
1417 }
1418 }
1419 // Save or restore single word registers
1420 for ( int i = 0; i < total_in_args; i++) {
1421 if (in_regs[i].first()->is_Register()) {
1422 int offset = slot * VMRegImpl::stack_slot_size;
1423 slot++;
1424 assert(slot <= stack_slots, "overflow");
1425
1426 // Value is in an input register pass we must flush it to the stack
1427 const Register reg = in_regs[i].first()->as_Register();
1428 switch (in_sig_bt[i]) {
1429 case T_BOOLEAN:
1430 case T_CHAR:
1431 case T_BYTE:
1432 case T_SHORT:
1433 case T_INT:
1434 if (map != NULL) {
1435 __ movl(Address(rsp, offset), reg);
1436 } else {
1437 __ movl(reg, Address(rsp, offset));
1438 }
1439 break;
1440 case T_ARRAY:
1441 case T_LONG:
1442 // handled above
1443 break;
1444 case T_OBJECT:
1445 default: ShouldNotReachHere();
1446 }
1447 } else if (in_regs[i].first()->is_XMMRegister()) {
1448 if (in_sig_bt[i] == T_FLOAT) {
1449 int offset = slot * VMRegImpl::stack_slot_size;
1450 slot++;
1451 assert(slot <= stack_slots, "overflow");
1452 if (map != NULL) {
1453 __ movflt(Address(rsp, offset), in_regs[i].first()->as_XMMRegister());
1454 } else {
1455 __ movflt(in_regs[i].first()->as_XMMRegister(), Address(rsp, offset));
1456 }
1457 }
1458 } else if (in_regs[i].first()->is_stack()) {
1459 if (in_sig_bt[i] == T_ARRAY && map != NULL) {
1460 int offset_in_older_frame = in_regs[i].first()->reg2stack() + SharedRuntime::out_preserve_stack_slots();
1461 map->set_oop(VMRegImpl::stack2reg(offset_in_older_frame + stack_slots));
1462 }
1463 }
1464 }
1465 }
1466
1467 // Pin object, return pinned object or null in rax
1468 static void gen_pin_object(MacroAssembler* masm,
1469 VMRegPair reg) {
1470 __ block_comment("gen_pin_object {");
1471
1472 // rax always contains oop, either incoming or
1473 // pinned.
1474 Register tmp_reg = rax;
1475
1476 Label is_null;
1477 VMRegPair tmp;
1478 VMRegPair in_reg = reg;
1479
1480 tmp.set_ptr(tmp_reg->as_VMReg());
1481 if (reg.first()->is_stack()) {
1482 // Load the arg up from the stack
1483 move_ptr(masm, reg, tmp);
1484 reg = tmp;
1485 } else {
1486 __ movptr(rax, reg.first()->as_Register());
1487 }
1488 __ testptr(reg.first()->as_Register(), reg.first()->as_Register());
1489 __ jccb(Assembler::equal, is_null);
1490
1491 if (reg.first()->as_Register() != c_rarg1) {
1492 __ movptr(c_rarg1, reg.first()->as_Register());
1493 }
1494
1495 __ call_VM_leaf(
1496 CAST_FROM_FN_PTR(address, SharedRuntime::pin_object),
1497 r15_thread, c_rarg1);
1498
1499 __ bind(is_null);
1500 __ block_comment("} gen_pin_object");
1501 }
1502
1503 // Unpin object
1504 static void gen_unpin_object(MacroAssembler* masm,
1505 VMRegPair reg) {
1506 __ block_comment("gen_unpin_object {");
1507 Label is_null;
1508
1509 if (reg.first()->is_stack()) {
1510 __ movptr(c_rarg1, Address(rbp, reg2offset_in(reg.first())));
1511 } else if (reg.first()->as_Register() != c_rarg1) {
1512 __ movptr(c_rarg1, reg.first()->as_Register());
1513 }
1514
1515 __ testptr(c_rarg1, c_rarg1);
1516 __ jccb(Assembler::equal, is_null);
1517
1518 __ call_VM_leaf(
1519 CAST_FROM_FN_PTR(address, SharedRuntime::unpin_object),
1520 r15_thread, c_rarg1);
1521
1522 __ bind(is_null);
1523 __ block_comment("} gen_unpin_object");
1524 }
1525
1526 // Check GCLocker::needs_gc and enter the runtime if it's true. This
1527 // keeps a new JNI critical region from starting until a GC has been
1528 // forced. Save down any oops in registers and describe them in an
1529 // OopMap.
1530 static void check_needs_gc_for_critical_native(MacroAssembler* masm,
1531 int stack_slots,
1532 int total_c_args,
1533 int total_in_args,
1534 int arg_save_area,
1535 OopMapSet* oop_maps,
1536 VMRegPair* in_regs,
1537 BasicType* in_sig_bt) {
1538 __ block_comment("check GCLocker::needs_gc");
1539 Label cont;
1540 __ cmp8(ExternalAddress((address)GCLocker::needs_gc_address()), false);
1541 __ jcc(Assembler::equal, cont);
1542
1543 // Save down any incoming oops and call into the runtime to halt for a GC
1544
1545 OopMap* map = new OopMap(stack_slots * 2, 0 /* arg_slots*/);
1546 save_or_restore_arguments(masm, stack_slots, total_in_args,
1547 arg_save_area, map, in_regs, in_sig_bt);
1548
1549 address the_pc = __ pc();
1550 oop_maps->add_gc_map( __ offset(), map);
1551 __ set_last_Java_frame(rsp, noreg, the_pc);
1552
1553 __ block_comment("block_for_jni_critical");
1554 __ movptr(c_rarg0, r15_thread);
1555 __ mov(r12, rsp); // remember sp
1556 __ subptr(rsp, frame::arg_reg_save_area_bytes); // windows
1557 __ andptr(rsp, -16); // align stack as required by ABI
1558 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, SharedRuntime::block_for_jni_critical)));
1559 __ mov(rsp, r12); // restore sp
1560 __ reinit_heapbase();
1561
1562 __ reset_last_Java_frame(false);
1563
1564 save_or_restore_arguments(masm, stack_slots, total_in_args,
1565 arg_save_area, NULL, in_regs, in_sig_bt);
1566 __ bind(cont);
1567 #ifdef ASSERT
1568 if (StressCriticalJNINatives) {
1569 // Stress register saving
1570 OopMap* map = new OopMap(stack_slots * 2, 0 /* arg_slots*/);
1571 save_or_restore_arguments(masm, stack_slots, total_in_args,
1572 arg_save_area, map, in_regs, in_sig_bt);
1573 // Destroy argument registers
1574 for (int i = 0; i < total_in_args - 1; i++) {
1575 if (in_regs[i].first()->is_Register()) {
1576 const Register reg = in_regs[i].first()->as_Register();
1577 __ xorptr(reg, reg);
1578 } else if (in_regs[i].first()->is_XMMRegister()) {
1579 __ xorpd(in_regs[i].first()->as_XMMRegister(), in_regs[i].first()->as_XMMRegister());
1580 } else if (in_regs[i].first()->is_FloatRegister()) {
1581 ShouldNotReachHere();
1582 } else if (in_regs[i].first()->is_stack()) {
1583 // Nothing to do
1584 } else {
1585 ShouldNotReachHere();
1586 }
1587 if (in_sig_bt[i] == T_LONG || in_sig_bt[i] == T_DOUBLE) {
1588 i++;
1589 }
1590 }
1591
1592 save_or_restore_arguments(masm, stack_slots, total_in_args,
1593 arg_save_area, NULL, in_regs, in_sig_bt);
1594 }
1595 #endif
1596 }
1597
1598 // Unpack an array argument into a pointer to the body and the length
1599 // if the array is non-null, otherwise pass 0 for both.
1600 static void unpack_array_argument(MacroAssembler* masm, VMRegPair reg, BasicType in_elem_type, VMRegPair body_arg, VMRegPair length_arg) {
1601 Register tmp_reg = rax;
1602 assert(!body_arg.first()->is_Register() || body_arg.first()->as_Register() != tmp_reg,
1603 "possible collision");
1604 assert(!length_arg.first()->is_Register() || length_arg.first()->as_Register() != tmp_reg,
1605 "possible collision");
1606
1607 __ block_comment("unpack_array_argument {");
1608
1609 // Pass the length, ptr pair
1610 Label is_null, done;
1611 VMRegPair tmp;
1612 tmp.set_ptr(tmp_reg->as_VMReg());
1613 if (reg.first()->is_stack()) {
1614 // Load the arg up from the stack
1615 move_ptr(masm, reg, tmp);
1616 reg = tmp;
1617 }
1618 __ testptr(reg.first()->as_Register(), reg.first()->as_Register());
1619 __ jccb(Assembler::equal, is_null);
1620 __ lea(tmp_reg, Address(reg.first()->as_Register(), arrayOopDesc::base_offset_in_bytes(in_elem_type)));
1621 move_ptr(masm, tmp, body_arg);
1622 // load the length relative to the body.
1623 __ movl(tmp_reg, Address(tmp_reg, arrayOopDesc::length_offset_in_bytes() -
1624 arrayOopDesc::base_offset_in_bytes(in_elem_type)));
1625 move32_64(masm, tmp, length_arg);
1626 __ jmpb(done);
1627 __ bind(is_null);
1628 // Pass zeros
1629 __ xorptr(tmp_reg, tmp_reg);
1630 move_ptr(masm, tmp, body_arg);
1631 move32_64(masm, tmp, length_arg);
1632 __ bind(done);
1633
1634 __ block_comment("} unpack_array_argument");
1635 }
1636
1637
1638 // Different signatures may require very different orders for the move
1639 // to avoid clobbering other arguments. There's no simple way to
1640 // order them safely. Compute a safe order for issuing stores and
1641 // break any cycles in those stores. This code is fairly general but
1642 // it's not necessary on the other platforms so we keep it in the
1643 // platform dependent code instead of moving it into a shared file.
1644 // (See bugs 7013347 & 7145024.)
1645 // Note that this code is specific to LP64.
1646 class ComputeMoveOrder: public StackObj {
1647 class MoveOperation: public ResourceObj {
1648 friend class ComputeMoveOrder;
1649 private:
1650 VMRegPair _src;
1651 VMRegPair _dst;
1652 int _src_index;
1653 int _dst_index;
1654 bool _processed;
1655 MoveOperation* _next;
1656 MoveOperation* _prev;
1657
1658 static int get_id(VMRegPair r) {
1659 return r.first()->value();
1660 }
1661
1662 public:
1663 MoveOperation(int src_index, VMRegPair src, int dst_index, VMRegPair dst):
1664 _src(src)
1665 , _dst(dst)
1666 , _src_index(src_index)
1667 , _dst_index(dst_index)
1668 , _processed(false)
1669 , _next(NULL)
1670 , _prev(NULL) {
1671 }
1672
1673 VMRegPair src() const { return _src; }
1674 int src_id() const { return get_id(src()); }
1675 int src_index() const { return _src_index; }
1676 VMRegPair dst() const { return _dst; }
1677 void set_dst(int i, VMRegPair dst) { _dst_index = i, _dst = dst; }
1678 int dst_index() const { return _dst_index; }
1679 int dst_id() const { return get_id(dst()); }
1680 MoveOperation* next() const { return _next; }
1681 MoveOperation* prev() const { return _prev; }
1682 void set_processed() { _processed = true; }
1683 bool is_processed() const { return _processed; }
1684
1685 // insert
1686 void break_cycle(VMRegPair temp_register) {
1687 // create a new store following the last store
1688 // to move from the temp_register to the original
1689 MoveOperation* new_store = new MoveOperation(-1, temp_register, dst_index(), dst());
1690
1691 // break the cycle of links and insert new_store at the end
1692 // break the reverse link.
1693 MoveOperation* p = prev();
1694 assert(p->next() == this, "must be");
1695 _prev = NULL;
1696 p->_next = new_store;
1697 new_store->_prev = p;
1698
1699 // change the original store to save it's value in the temp.
1700 set_dst(-1, temp_register);
1701 }
1702
1703 void link(GrowableArray<MoveOperation*>& killer) {
1704 // link this store in front the store that it depends on
1705 MoveOperation* n = killer.at_grow(src_id(), NULL);
1706 if (n != NULL) {
1707 assert(_next == NULL && n->_prev == NULL, "shouldn't have been set yet");
1708 _next = n;
1709 n->_prev = this;
1710 }
1711 }
1712 };
1713
1714 private:
1715 GrowableArray<MoveOperation*> edges;
1716
1717 public:
1718 ComputeMoveOrder(int total_in_args, VMRegPair* in_regs, int total_c_args, VMRegPair* out_regs,
1719 BasicType* in_sig_bt, GrowableArray<int>& arg_order, VMRegPair tmp_vmreg) {
1720 // Move operations where the dest is the stack can all be
1721 // scheduled first since they can't interfere with the other moves.
1722 for (int i = total_in_args - 1, c_arg = total_c_args - 1; i >= 0; i--, c_arg--) {
1723 if (in_sig_bt[i] == T_ARRAY) {
1724 c_arg--;
1725 if (out_regs[c_arg].first()->is_stack() &&
1726 out_regs[c_arg + 1].first()->is_stack()) {
1727 arg_order.push(i);
1728 arg_order.push(c_arg);
1729 } else {
1730 if (out_regs[c_arg].first()->is_stack() ||
1731 in_regs[i].first() == out_regs[c_arg].first()) {
1732 add_edge(i, in_regs[i].first(), c_arg, out_regs[c_arg + 1]);
1733 } else {
1734 add_edge(i, in_regs[i].first(), c_arg, out_regs[c_arg]);
1735 }
1736 }
1737 } else if (in_sig_bt[i] == T_VOID) {
1738 arg_order.push(i);
1739 arg_order.push(c_arg);
1740 } else {
1741 if (out_regs[c_arg].first()->is_stack() ||
1742 in_regs[i].first() == out_regs[c_arg].first()) {
1743 arg_order.push(i);
1744 arg_order.push(c_arg);
1745 } else {
1746 add_edge(i, in_regs[i].first(), c_arg, out_regs[c_arg]);
1747 }
1748 }
1749 }
1750 // Break any cycles in the register moves and emit the in the
1751 // proper order.
1752 GrowableArray<MoveOperation*>* stores = get_store_order(tmp_vmreg);
1753 for (int i = 0; i < stores->length(); i++) {
1754 arg_order.push(stores->at(i)->src_index());
1755 arg_order.push(stores->at(i)->dst_index());
1756 }
1757 }
1758
1759 // Collected all the move operations
1760 void add_edge(int src_index, VMRegPair src, int dst_index, VMRegPair dst) {
1761 if (src.first() == dst.first()) return;
1762 edges.append(new MoveOperation(src_index, src, dst_index, dst));
1763 }
1764
1765 // Walk the edges breaking cycles between moves. The result list
1766 // can be walked in order to produce the proper set of loads
1767 GrowableArray<MoveOperation*>* get_store_order(VMRegPair temp_register) {
1768 // Record which moves kill which values
1769 GrowableArray<MoveOperation*> killer;
1770 for (int i = 0; i < edges.length(); i++) {
1771 MoveOperation* s = edges.at(i);
1772 assert(killer.at_grow(s->dst_id(), NULL) == NULL, "only one killer");
1773 killer.at_put_grow(s->dst_id(), s, NULL);
1774 }
1775 assert(killer.at_grow(MoveOperation::get_id(temp_register), NULL) == NULL,
1776 "make sure temp isn't in the registers that are killed");
1777
1778 // create links between loads and stores
1779 for (int i = 0; i < edges.length(); i++) {
1780 edges.at(i)->link(killer);
1781 }
1782
1783 // at this point, all the move operations are chained together
1784 // in a doubly linked list. Processing it backwards finds
1785 // the beginning of the chain, forwards finds the end. If there's
1786 // a cycle it can be broken at any point, so pick an edge and walk
1787 // backward until the list ends or we end where we started.
1788 GrowableArray<MoveOperation*>* stores = new GrowableArray<MoveOperation*>();
1789 for (int e = 0; e < edges.length(); e++) {
1790 MoveOperation* s = edges.at(e);
1791 if (!s->is_processed()) {
1792 MoveOperation* start = s;
1793 // search for the beginning of the chain or cycle
1794 while (start->prev() != NULL && start->prev() != s) {
1795 start = start->prev();
1796 }
1797 if (start->prev() == s) {
1798 start->break_cycle(temp_register);
1799 }
1800 // walk the chain forward inserting to store list
1801 while (start != NULL) {
1802 stores->append(start);
1803 start->set_processed();
1804 start = start->next();
1805 }
1806 }
1807 }
1808 return stores;
1809 }
1810 };
1811
1812 static void verify_oop_args(MacroAssembler* masm,
1813 const methodHandle& method,
1814 const BasicType* sig_bt,
1815 const VMRegPair* regs) {
1816 Register temp_reg = rbx; // not part of any compiled calling seq
1817 if (VerifyOops) {
1818 for (int i = 0; i < method->size_of_parameters(); i++) {
1819 if (is_reference_type(sig_bt[i])) {
1820 VMReg r = regs[i].first();
1821 assert(r->is_valid(), "bad oop arg");
1822 if (r->is_stack()) {
1823 __ movptr(temp_reg, Address(rsp, r->reg2stack() * VMRegImpl::stack_slot_size + wordSize));
1824 __ verify_oop(temp_reg);
1825 } else {
1826 __ verify_oop(r->as_Register());
1827 }
1828 }
1829 }
1830 }
1831 }
1832
1833 static void gen_special_dispatch(MacroAssembler* masm,
1834 const methodHandle& method,
1835 const BasicType* sig_bt,
1836 const VMRegPair* regs) {
1837 verify_oop_args(masm, method, sig_bt, regs);
1838 vmIntrinsics::ID iid = method->intrinsic_id();
1839
1840 // Now write the args into the outgoing interpreter space
1841 bool has_receiver = false;
1842 Register receiver_reg = noreg;
1843 int member_arg_pos = -1;
1844 Register member_reg = noreg;
1845 int ref_kind = MethodHandles::signature_polymorphic_intrinsic_ref_kind(iid);
1846 if (ref_kind != 0) {
1847 member_arg_pos = method->size_of_parameters() - 1; // trailing MemberName argument
1848 member_reg = rbx; // known to be free at this point
1849 has_receiver = MethodHandles::ref_kind_has_receiver(ref_kind);
1850 } else if (iid == vmIntrinsics::_invokeBasic) {
1851 has_receiver = true;
1852 } else {
1853 fatal("unexpected intrinsic id %d", iid);
1854 }
1855
1856 if (member_reg != noreg) {
1857 // Load the member_arg into register, if necessary.
1858 SharedRuntime::check_member_name_argument_is_last_argument(method, sig_bt, regs);
1859 VMReg r = regs[member_arg_pos].first();
1860 if (r->is_stack()) {
1861 __ movptr(member_reg, Address(rsp, r->reg2stack() * VMRegImpl::stack_slot_size + wordSize));
1862 } else {
1863 // no data motion is needed
1864 member_reg = r->as_Register();
1865 }
1866 }
1867
1868 if (has_receiver) {
1869 // Make sure the receiver is loaded into a register.
1870 assert(method->size_of_parameters() > 0, "oob");
1871 assert(sig_bt[0] == T_OBJECT, "receiver argument must be an object");
1872 VMReg r = regs[0].first();
1873 assert(r->is_valid(), "bad receiver arg");
1874 if (r->is_stack()) {
1875 // Porting note: This assumes that compiled calling conventions always
1876 // pass the receiver oop in a register. If this is not true on some
1877 // platform, pick a temp and load the receiver from stack.
1878 fatal("receiver always in a register");
1879 receiver_reg = j_rarg0; // known to be free at this point
1880 __ movptr(receiver_reg, Address(rsp, r->reg2stack() * VMRegImpl::stack_slot_size + wordSize));
1881 } else {
1882 // no data motion is needed
1883 receiver_reg = r->as_Register();
1884 }
1885 }
1886
1887 // Figure out which address we are really jumping to:
1888 MethodHandles::generate_method_handle_dispatch(masm, iid,
1889 receiver_reg, member_reg, /*for_compiler_entry:*/ true);
1890 }
1891
1892 // ---------------------------------------------------------------------------
1893 // Generate a native wrapper for a given method. The method takes arguments
1894 // in the Java compiled code convention, marshals them to the native
1895 // convention (handlizes oops, etc), transitions to native, makes the call,
1896 // returns to java state (possibly blocking), unhandlizes any result and
1897 // returns.
1898 //
1899 // Critical native functions are a shorthand for the use of
1900 // GetPrimtiveArrayCritical and disallow the use of any other JNI
1901 // functions. The wrapper is expected to unpack the arguments before
1902 // passing them to the callee and perform checks before and after the
1903 // native call to ensure that they GCLocker
1904 // lock_critical/unlock_critical semantics are followed. Some other
1905 // parts of JNI setup are skipped like the tear down of the JNI handle
1906 // block and the check for pending exceptions it's impossible for them
1907 // to be thrown.
1908 //
1909 // They are roughly structured like this:
1910 // if (GCLocker::needs_gc())
1911 // SharedRuntime::block_for_jni_critical();
1912 // tranistion to thread_in_native
1913 // unpack arrray arguments and call native entry point
1914 // check for safepoint in progress
1915 // check if any thread suspend flags are set
1916 // call into JVM and possible unlock the JNI critical
1917 // if a GC was suppressed while in the critical native.
1918 // transition back to thread_in_Java
1919 // return to caller
1920 //
1921 nmethod* SharedRuntime::generate_native_wrapper(MacroAssembler* masm,
1922 const methodHandle& method,
1923 int compile_id,
1924 BasicType* in_sig_bt,
1925 VMRegPair* in_regs,
1926 BasicType ret_type,
1927 address critical_entry) {
1928 if (method->is_method_handle_intrinsic()) {
1929 vmIntrinsics::ID iid = method->intrinsic_id();
1930 intptr_t start = (intptr_t)__ pc();
1931 int vep_offset = ((intptr_t)__ pc()) - start;
1932 gen_special_dispatch(masm,
1933 method,
1934 in_sig_bt,
1935 in_regs);
1936 int frame_complete = ((intptr_t)__ pc()) - start; // not complete, period
1937 __ flush();
1938 int stack_slots = SharedRuntime::out_preserve_stack_slots(); // no out slots at all, actually
1939 return nmethod::new_native_nmethod(method,
1940 compile_id,
1941 masm->code(),
1942 vep_offset,
1943 frame_complete,
1944 stack_slots / VMRegImpl::slots_per_word,
1945 in_ByteSize(-1),
1946 in_ByteSize(-1),
1947 (OopMapSet*)NULL);
1948 }
1949 bool is_critical_native = true;
1950 address native_func = critical_entry;
1951 if (native_func == NULL) {
1952 native_func = method->native_function();
1953 is_critical_native = false;
1954 }
1955 assert(native_func != NULL, "must have function");
1956
1957 // An OopMap for lock (and class if static)
1958 OopMapSet *oop_maps = new OopMapSet();
1959 intptr_t start = (intptr_t)__ pc();
1960
1961 // We have received a description of where all the java arg are located
1962 // on entry to the wrapper. We need to convert these args to where
1963 // the jni function will expect them. To figure out where they go
1964 // we convert the java signature to a C signature by inserting
1965 // the hidden arguments as arg[0] and possibly arg[1] (static method)
1966
1967 const int total_in_args = method->size_of_parameters();
1968 int total_c_args = total_in_args;
1969 if (!is_critical_native) {
1970 total_c_args += 1;
1971 if (method->is_static()) {
1972 total_c_args++;
1973 }
1974 } else {
1975 for (int i = 0; i < total_in_args; i++) {
1976 if (in_sig_bt[i] == T_ARRAY) {
1977 total_c_args++;
1978 }
1979 }
1980 }
1981
1982 BasicType* out_sig_bt = NEW_RESOURCE_ARRAY(BasicType, total_c_args);
1983 VMRegPair* out_regs = NEW_RESOURCE_ARRAY(VMRegPair, total_c_args);
1984 BasicType* in_elem_bt = NULL;
1985
1986 int argc = 0;
1987 if (!is_critical_native) {
1988 out_sig_bt[argc++] = T_ADDRESS;
1989 if (method->is_static()) {
1990 out_sig_bt[argc++] = T_OBJECT;
1991 }
1992
1993 for (int i = 0; i < total_in_args ; i++ ) {
1994 out_sig_bt[argc++] = in_sig_bt[i];
1995 }
1996 } else {
1997 in_elem_bt = NEW_RESOURCE_ARRAY(BasicType, total_in_args);
1998 SignatureStream ss(method->signature());
1999 for (int i = 0; i < total_in_args ; i++ ) {
2000 if (in_sig_bt[i] == T_ARRAY) {
2001 // Arrays are passed as int, elem* pair
2002 out_sig_bt[argc++] = T_INT;
2003 out_sig_bt[argc++] = T_ADDRESS;
2004 Symbol* atype = ss.as_symbol();
2005 const char* at = atype->as_C_string();
2006 if (strlen(at) == 2) {
2007 assert(at[0] == '[', "must be");
2008 switch (at[1]) {
2009 case 'B': in_elem_bt[i] = T_BYTE; break;
2010 case 'C': in_elem_bt[i] = T_CHAR; break;
2011 case 'D': in_elem_bt[i] = T_DOUBLE; break;
2012 case 'F': in_elem_bt[i] = T_FLOAT; break;
2013 case 'I': in_elem_bt[i] = T_INT; break;
2014 case 'J': in_elem_bt[i] = T_LONG; break;
2015 case 'S': in_elem_bt[i] = T_SHORT; break;
2016 case 'Z': in_elem_bt[i] = T_BOOLEAN; break;
2017 default: ShouldNotReachHere();
2018 }
2019 }
2020 } else {
2021 out_sig_bt[argc++] = in_sig_bt[i];
2022 in_elem_bt[i] = T_VOID;
2023 }
2024 if (in_sig_bt[i] != T_VOID) {
2025 assert(in_sig_bt[i] == ss.type(), "must match");
2026 ss.next();
2027 }
2028 }
2029 }
2030
2031 // Now figure out where the args must be stored and how much stack space
2032 // they require.
2033 int out_arg_slots;
2034 out_arg_slots = c_calling_convention(out_sig_bt, out_regs, NULL, total_c_args);
2035
2036 // Compute framesize for the wrapper. We need to handlize all oops in
2037 // incoming registers
2038
2039 // Calculate the total number of stack slots we will need.
2040
2041 // First count the abi requirement plus all of the outgoing args
2042 int stack_slots = SharedRuntime::out_preserve_stack_slots() + out_arg_slots;
2043
2044 // Now the space for the inbound oop handle area
2045 int total_save_slots = 6 * VMRegImpl::slots_per_word; // 6 arguments passed in registers
2046 if (is_critical_native) {
2047 // Critical natives may have to call out so they need a save area
2048 // for register arguments.
2049 int double_slots = 0;
2050 int single_slots = 0;
2051 for ( int i = 0; i < total_in_args; i++) {
2052 if (in_regs[i].first()->is_Register()) {
2053 const Register reg = in_regs[i].first()->as_Register();
2054 switch (in_sig_bt[i]) {
2055 case T_BOOLEAN:
2056 case T_BYTE:
2057 case T_SHORT:
2058 case T_CHAR:
2059 case T_INT: single_slots++; break;
2060 case T_ARRAY: // specific to LP64 (7145024)
2061 case T_LONG: double_slots++; break;
2062 default: ShouldNotReachHere();
2063 }
2064 } else if (in_regs[i].first()->is_XMMRegister()) {
2065 switch (in_sig_bt[i]) {
2066 case T_FLOAT: single_slots++; break;
2067 case T_DOUBLE: double_slots++; break;
2068 default: ShouldNotReachHere();
2069 }
2070 } else if (in_regs[i].first()->is_FloatRegister()) {
2071 ShouldNotReachHere();
2072 }
2073 }
2074 total_save_slots = double_slots * 2 + single_slots;
2075 // align the save area
2076 if (double_slots != 0) {
2077 stack_slots = align_up(stack_slots, 2);
2078 }
2079 }
2080
2081 int oop_handle_offset = stack_slots;
2082 stack_slots += total_save_slots;
2083
2084 // Now any space we need for handlizing a klass if static method
2085
2086 int klass_slot_offset = 0;
2087 int klass_offset = -1;
2088 int lock_slot_offset = 0;
2089 bool is_static = false;
2090
2091 if (method->is_static()) {
2092 klass_slot_offset = stack_slots;
2093 stack_slots += VMRegImpl::slots_per_word;
2094 klass_offset = klass_slot_offset * VMRegImpl::stack_slot_size;
2095 is_static = true;
2096 }
2097
2098 // Plus a lock if needed
2099
2100 if (method->is_synchronized()) {
2101 lock_slot_offset = stack_slots;
2102 stack_slots += VMRegImpl::slots_per_word;
2103 }
2104
2105 // Now a place (+2) to save return values or temp during shuffling
2106 // + 4 for return address (which we own) and saved rbp
2107 stack_slots += 6;
2108
2109 // Ok The space we have allocated will look like:
2110 //
2111 //
2112 // FP-> | |
2113 // |---------------------|
2114 // | 2 slots for moves |
2115 // |---------------------|
2116 // | lock box (if sync) |
2117 // |---------------------| <- lock_slot_offset
2118 // | klass (if static) |
2119 // |---------------------| <- klass_slot_offset
2120 // | oopHandle area |
2121 // |---------------------| <- oop_handle_offset (6 java arg registers)
2122 // | outbound memory |
2123 // | based arguments |
2124 // | |
2125 // |---------------------|
2126 // | |
2127 // SP-> | out_preserved_slots |
2128 //
2129 //
2130
2131
2132 // Now compute actual number of stack words we need rounding to make
2133 // stack properly aligned.
2134 stack_slots = align_up(stack_slots, StackAlignmentInSlots);
2135
2136 int stack_size = stack_slots * VMRegImpl::stack_slot_size;
2137
2138 // First thing make an ic check to see if we should even be here
2139
2140 // We are free to use all registers as temps without saving them and
2141 // restoring them except rbp. rbp is the only callee save register
2142 // as far as the interpreter and the compiler(s) are concerned.
2143
2144
2145 const Register ic_reg = rax;
2146 const Register receiver = j_rarg0;
2147
2148 Label hit;
2149 Label exception_pending;
2150
2151 assert_different_registers(ic_reg, receiver, rscratch1);
2152 __ verify_oop(receiver);
2153 __ load_klass(rscratch1, receiver);
2154 __ cmpq(ic_reg, rscratch1);
2155 __ jcc(Assembler::equal, hit);
2156
2157 __ jump(RuntimeAddress(SharedRuntime::get_ic_miss_stub()));
2158
2159 // Verified entry point must be aligned
2160 __ align(8);
2161
2162 __ bind(hit);
2163
2164 int vep_offset = ((intptr_t)__ pc()) - start;
2165
2166 if (VM_Version::supports_fast_class_init_checks() && method->needs_clinit_barrier()) {
2167 Label L_skip_barrier;
2168 Register klass = r10;
2169 __ mov_metadata(klass, method->method_holder()); // InstanceKlass*
2170 __ clinit_barrier(klass, r15_thread, &L_skip_barrier /*L_fast_path*/);
2171
2172 __ jump(RuntimeAddress(SharedRuntime::get_handle_wrong_method_stub())); // slow path
2173
2174 __ bind(L_skip_barrier);
2175 }
2176
2177 #ifdef COMPILER1
2178 // For Object.hashCode, System.identityHashCode try to pull hashCode from object header if available.
2179 if ((InlineObjectHash && method->intrinsic_id() == vmIntrinsics::_hashCode) || (method->intrinsic_id() == vmIntrinsics::_identityHashCode)) {
2180 inline_check_hashcode_from_object_header(masm, method, j_rarg0 /*obj_reg*/, rax /*result*/);
2181 }
2182 #endif // COMPILER1
2183
2184 // The instruction at the verified entry point must be 5 bytes or longer
2185 // because it can be patched on the fly by make_non_entrant. The stack bang
2186 // instruction fits that requirement.
2187
2188 // Generate stack overflow check
2189
2190 if (UseStackBanging) {
2191 __ bang_stack_with_offset((int)JavaThread::stack_shadow_zone_size());
2192 } else {
2193 // need a 5 byte instruction to allow MT safe patching to non-entrant
2194 __ fat_nop();
2195 }
2196
2197 // Generate a new frame for the wrapper.
2198 __ enter();
2199 // -2 because return address is already present and so is saved rbp
2200 __ subptr(rsp, stack_size - 2*wordSize);
2201
2202 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
2203 bs->nmethod_entry_barrier(masm);
2204
2205 // Frame is now completed as far as size and linkage.
2206 int frame_complete = ((intptr_t)__ pc()) - start;
2207
2208 if (UseRTMLocking) {
2209 // Abort RTM transaction before calling JNI
2210 // because critical section will be large and will be
2211 // aborted anyway. Also nmethod could be deoptimized.
2212 __ xabort(0);
2213 }
2214
2215 #ifdef ASSERT
2216 {
2217 Label L;
2218 __ mov(rax, rsp);
2219 __ andptr(rax, -16); // must be 16 byte boundary (see amd64 ABI)
2220 __ cmpptr(rax, rsp);
2221 __ jcc(Assembler::equal, L);
2222 __ stop("improperly aligned stack");
2223 __ bind(L);
2224 }
2225 #endif /* ASSERT */
2226
2227
2228 // We use r14 as the oop handle for the receiver/klass
2229 // It is callee save so it survives the call to native
2230
2231 const Register oop_handle_reg = r14;
2232
2233 if (is_critical_native && !Universe::heap()->supports_object_pinning()) {
2234 check_needs_gc_for_critical_native(masm, stack_slots, total_c_args, total_in_args,
2235 oop_handle_offset, oop_maps, in_regs, in_sig_bt);
2236 }
2237
2238 //
2239 // We immediately shuffle the arguments so that any vm call we have to
2240 // make from here on out (sync slow path, jvmti, etc.) we will have
2241 // captured the oops from our caller and have a valid oopMap for
2242 // them.
2243
2244 // -----------------
2245 // The Grand Shuffle
2246
2247 // The Java calling convention is either equal (linux) or denser (win64) than the
2248 // c calling convention. However the because of the jni_env argument the c calling
2249 // convention always has at least one more (and two for static) arguments than Java.
2250 // Therefore if we move the args from java -> c backwards then we will never have
2251 // a register->register conflict and we don't have to build a dependency graph
2252 // and figure out how to break any cycles.
2253 //
2254
2255 // Record esp-based slot for receiver on stack for non-static methods
2256 int receiver_offset = -1;
2257
2258 // This is a trick. We double the stack slots so we can claim
2259 // the oops in the caller's frame. Since we are sure to have
2260 // more args than the caller doubling is enough to make
2261 // sure we can capture all the incoming oop args from the
2262 // caller.
2263 //
2264 OopMap* map = new OopMap(stack_slots * 2, 0 /* arg_slots*/);
2265
2266 // Mark location of rbp (someday)
2267 // map->set_callee_saved(VMRegImpl::stack2reg( stack_slots - 2), stack_slots * 2, 0, vmreg(rbp));
2268
2269 // Use eax, ebx as temporaries during any memory-memory moves we have to do
2270 // All inbound args are referenced based on rbp and all outbound args via rsp.
2271
2272
2273 #ifdef ASSERT
2274 bool reg_destroyed[RegisterImpl::number_of_registers];
2275 bool freg_destroyed[XMMRegisterImpl::number_of_registers];
2276 for ( int r = 0 ; r < RegisterImpl::number_of_registers ; r++ ) {
2277 reg_destroyed[r] = false;
2278 }
2279 for ( int f = 0 ; f < XMMRegisterImpl::number_of_registers ; f++ ) {
2280 freg_destroyed[f] = false;
2281 }
2282
2283 #endif /* ASSERT */
2284
2285 // This may iterate in two different directions depending on the
2286 // kind of native it is. The reason is that for regular JNI natives
2287 // the incoming and outgoing registers are offset upwards and for
2288 // critical natives they are offset down.
2289 GrowableArray<int> arg_order(2 * total_in_args);
2290 // Inbound arguments that need to be pinned for critical natives
2291 GrowableArray<int> pinned_args(total_in_args);
2292 // Current stack slot for storing register based array argument
2293 int pinned_slot = oop_handle_offset;
2294
2295 VMRegPair tmp_vmreg;
2296 tmp_vmreg.set2(rbx->as_VMReg());
2297
2298 if (!is_critical_native) {
2299 for (int i = total_in_args - 1, c_arg = total_c_args - 1; i >= 0; i--, c_arg--) {
2300 arg_order.push(i);
2301 arg_order.push(c_arg);
2302 }
2303 } else {
2304 // Compute a valid move order, using tmp_vmreg to break any cycles
2305 ComputeMoveOrder cmo(total_in_args, in_regs, total_c_args, out_regs, in_sig_bt, arg_order, tmp_vmreg);
2306 }
2307
2308 int temploc = -1;
2309 for (int ai = 0; ai < arg_order.length(); ai += 2) {
2310 int i = arg_order.at(ai);
2311 int c_arg = arg_order.at(ai + 1);
2312 __ block_comment(err_msg("move %d -> %d", i, c_arg));
2313 if (c_arg == -1) {
2314 assert(is_critical_native, "should only be required for critical natives");
2315 // This arg needs to be moved to a temporary
2316 __ mov(tmp_vmreg.first()->as_Register(), in_regs[i].first()->as_Register());
2317 in_regs[i] = tmp_vmreg;
2318 temploc = i;
2319 continue;
2320 } else if (i == -1) {
2321 assert(is_critical_native, "should only be required for critical natives");
2322 // Read from the temporary location
2323 assert(temploc != -1, "must be valid");
2324 i = temploc;
2325 temploc = -1;
2326 }
2327 #ifdef ASSERT
2328 if (in_regs[i].first()->is_Register()) {
2329 assert(!reg_destroyed[in_regs[i].first()->as_Register()->encoding()], "destroyed reg!");
2330 } else if (in_regs[i].first()->is_XMMRegister()) {
2331 assert(!freg_destroyed[in_regs[i].first()->as_XMMRegister()->encoding()], "destroyed reg!");
2332 }
2333 if (out_regs[c_arg].first()->is_Register()) {
2334 reg_destroyed[out_regs[c_arg].first()->as_Register()->encoding()] = true;
2335 } else if (out_regs[c_arg].first()->is_XMMRegister()) {
2336 freg_destroyed[out_regs[c_arg].first()->as_XMMRegister()->encoding()] = true;
2337 }
2338 #endif /* ASSERT */
2339 switch (in_sig_bt[i]) {
2340 case T_ARRAY:
2341 if (is_critical_native) {
2342 // pin before unpack
2343 if (Universe::heap()->supports_object_pinning()) {
2344 save_args(masm, total_c_args, 0, out_regs);
2345 gen_pin_object(masm, in_regs[i]);
2346 pinned_args.append(i);
2347 restore_args(masm, total_c_args, 0, out_regs);
2348
2349 // rax has pinned array
2350 VMRegPair result_reg;
2351 result_reg.set_ptr(rax->as_VMReg());
2352 move_ptr(masm, result_reg, in_regs[i]);
2353 if (!in_regs[i].first()->is_stack()) {
2354 assert(pinned_slot <= stack_slots, "overflow");
2355 move_ptr(masm, result_reg, VMRegImpl::stack2reg(pinned_slot));
2356 pinned_slot += VMRegImpl::slots_per_word;
2357 }
2358 }
2359 unpack_array_argument(masm, in_regs[i], in_elem_bt[i], out_regs[c_arg + 1], out_regs[c_arg]);
2360 c_arg++;
2361 #ifdef ASSERT
2362 if (out_regs[c_arg].first()->is_Register()) {
2363 reg_destroyed[out_regs[c_arg].first()->as_Register()->encoding()] = true;
2364 } else if (out_regs[c_arg].first()->is_XMMRegister()) {
2365 freg_destroyed[out_regs[c_arg].first()->as_XMMRegister()->encoding()] = true;
2366 }
2367 #endif
2368 break;
2369 }
2370 case T_OBJECT:
2371 assert(!is_critical_native, "no oop arguments");
2372 object_move(masm, map, oop_handle_offset, stack_slots, in_regs[i], out_regs[c_arg],
2373 ((i == 0) && (!is_static)),
2374 &receiver_offset);
2375 break;
2376 case T_VOID:
2377 break;
2378
2379 case T_FLOAT:
2380 float_move(masm, in_regs[i], out_regs[c_arg]);
2381 break;
2382
2383 case T_DOUBLE:
2384 assert( i + 1 < total_in_args &&
2385 in_sig_bt[i + 1] == T_VOID &&
2386 out_sig_bt[c_arg+1] == T_VOID, "bad arg list");
2387 double_move(masm, in_regs[i], out_regs[c_arg]);
2388 break;
2389
2390 case T_LONG :
2391 long_move(masm, in_regs[i], out_regs[c_arg]);
2392 break;
2393
2394 case T_ADDRESS: assert(false, "found T_ADDRESS in java args");
2395
2396 default:
2397 move32_64(masm, in_regs[i], out_regs[c_arg]);
2398 }
2399 }
2400
2401 int c_arg;
2402
2403 // Pre-load a static method's oop into r14. Used both by locking code and
2404 // the normal JNI call code.
2405 if (!is_critical_native) {
2406 // point c_arg at the first arg that is already loaded in case we
2407 // need to spill before we call out
2408 c_arg = total_c_args - total_in_args;
2409
2410 if (method->is_static()) {
2411
2412 // load oop into a register
2413 __ movoop(oop_handle_reg, JNIHandles::make_local(method->method_holder()->java_mirror()));
2414
2415 // Now handlize the static class mirror it's known not-null.
2416 __ movptr(Address(rsp, klass_offset), oop_handle_reg);
2417 map->set_oop(VMRegImpl::stack2reg(klass_slot_offset));
2418
2419 // Now get the handle
2420 __ lea(oop_handle_reg, Address(rsp, klass_offset));
2421 // store the klass handle as second argument
2422 __ movptr(c_rarg1, oop_handle_reg);
2423 // and protect the arg if we must spill
2424 c_arg--;
2425 }
2426 } else {
2427 // For JNI critical methods we need to save all registers in save_args.
2428 c_arg = 0;
2429 }
2430
2431 // Change state to native (we save the return address in the thread, since it might not
2432 // be pushed on the stack when we do a a stack traversal). It is enough that the pc()
2433 // points into the right code segment. It does not have to be the correct return pc.
2434 // We use the same pc/oopMap repeatedly when we call out
2435
2436 intptr_t the_pc = (intptr_t) __ pc();
2437 oop_maps->add_gc_map(the_pc - start, map);
2438
2439 __ set_last_Java_frame(rsp, noreg, (address)the_pc);
2440
2441
2442 // We have all of the arguments setup at this point. We must not touch any register
2443 // argument registers at this point (what if we save/restore them there are no oop?
2444
2445 {
2446 SkipIfEqual skip(masm, &DTraceMethodProbes, false);
2447 // protect the args we've loaded
2448 save_args(masm, total_c_args, c_arg, out_regs);
2449 __ mov_metadata(c_rarg1, method());
2450 __ call_VM_leaf(
2451 CAST_FROM_FN_PTR(address, SharedRuntime::dtrace_method_entry),
2452 r15_thread, c_rarg1);
2453 restore_args(masm, total_c_args, c_arg, out_regs);
2454 }
2455
2456 // RedefineClasses() tracing support for obsolete method entry
2457 if (log_is_enabled(Trace, redefine, class, obsolete)) {
2458 // protect the args we've loaded
2459 save_args(masm, total_c_args, c_arg, out_regs);
2460 __ mov_metadata(c_rarg1, method());
2461 __ call_VM_leaf(
2462 CAST_FROM_FN_PTR(address, SharedRuntime::rc_trace_method_entry),
2463 r15_thread, c_rarg1);
2464 restore_args(masm, total_c_args, c_arg, out_regs);
2465 }
2466
2467 // Lock a synchronized method
2468
2469 // Register definitions used by locking and unlocking
2470
2471 const Register swap_reg = rax; // Must use rax for cmpxchg instruction
2472 const Register obj_reg = rbx; // Will contain the oop
2473 const Register lock_reg = r13; // Address of compiler lock object (BasicLock)
2474 const Register old_hdr = r13; // value of old header at unlock time
2475
2476 Label slow_path_lock;
2477 Label lock_done;
2478
2479 if (method->is_synchronized()) {
2480 assert(!is_critical_native, "unhandled");
2481
2482
2483 const int mark_word_offset = BasicLock::displaced_header_offset_in_bytes();
2484
2485 // Get the handle (the 2nd argument)
2486 __ mov(oop_handle_reg, c_rarg1);
2487
2488 // Get address of the box
2489
2490 __ lea(lock_reg, Address(rsp, lock_slot_offset * VMRegImpl::stack_slot_size));
2491
2492 // Load the oop from the handle
2493 __ movptr(obj_reg, Address(oop_handle_reg, 0));
2494
2495 __ resolve(IS_NOT_NULL, obj_reg);
2496 if (UseBiasedLocking) {
2497 __ biased_locking_enter(lock_reg, obj_reg, swap_reg, rscratch1, false, lock_done, &slow_path_lock);
2498 }
2499
2500 // Load immediate 1 into swap_reg %rax
2501 __ movl(swap_reg, 1);
2502
2503 // Load (object->mark() | 1) into swap_reg %rax
2504 __ orptr(swap_reg, Address(obj_reg, oopDesc::mark_offset_in_bytes()));
2505
2506 // Save (object->mark() | 1) into BasicLock's displaced header
2507 __ movptr(Address(lock_reg, mark_word_offset), swap_reg);
2508
2509 // src -> dest iff dest == rax else rax <- dest
2510 __ lock();
2511 __ cmpxchgptr(lock_reg, Address(obj_reg, oopDesc::mark_offset_in_bytes()));
2512 __ jcc(Assembler::equal, lock_done);
2513
2514 // Hmm should this move to the slow path code area???
2515
2516 // Test if the oopMark is an obvious stack pointer, i.e.,
2517 // 1) (mark & 3) == 0, and
2518 // 2) rsp <= mark < mark + os::pagesize()
2519 // These 3 tests can be done by evaluating the following
2520 // expression: ((mark - rsp) & (3 - os::vm_page_size())),
2521 // assuming both stack pointer and pagesize have their
2522 // least significant 2 bits clear.
2523 // NOTE: the oopMark is in swap_reg %rax as the result of cmpxchg
2524
2525 __ subptr(swap_reg, rsp);
2526 __ andptr(swap_reg, 3 - os::vm_page_size());
2527
2528 // Save the test result, for recursive case, the result is zero
2529 __ movptr(Address(lock_reg, mark_word_offset), swap_reg);
2530 __ jcc(Assembler::notEqual, slow_path_lock);
2531
2532 // Slow path will re-enter here
2533
2534 __ bind(lock_done);
2535 }
2536
2537
2538 // Finally just about ready to make the JNI call
2539
2540
2541 // get JNIEnv* which is first argument to native
2542 if (!is_critical_native) {
2543 __ lea(c_rarg0, Address(r15_thread, in_bytes(JavaThread::jni_environment_offset())));
2544 }
2545
2546 // Now set thread in native
2547 __ movl(Address(r15_thread, JavaThread::thread_state_offset()), _thread_in_native);
2548
2549 __ call(RuntimeAddress(native_func));
2550
2551 // Verify or restore cpu control state after JNI call
2552 __ restore_cpu_control_state_after_jni();
2553
2554 // Unpack native results.
2555 switch (ret_type) {
2556 case T_BOOLEAN: __ c2bool(rax); break;
2557 case T_CHAR : __ movzwl(rax, rax); break;
2558 case T_BYTE : __ sign_extend_byte (rax); break;
2559 case T_SHORT : __ sign_extend_short(rax); break;
2560 case T_INT : /* nothing to do */ break;
2561 case T_DOUBLE :
2562 case T_FLOAT :
2563 // Result is in xmm0 we'll save as needed
2564 break;
2565 case T_ARRAY: // Really a handle
2566 case T_OBJECT: // Really a handle
2567 break; // can't de-handlize until after safepoint check
2568 case T_VOID: break;
2569 case T_LONG: break;
2570 default : ShouldNotReachHere();
2571 }
2572
2573 // unpin pinned arguments
2574 pinned_slot = oop_handle_offset;
2575 if (pinned_args.length() > 0) {
2576 // save return value that may be overwritten otherwise.
2577 save_native_result(masm, ret_type, stack_slots);
2578 for (int index = 0; index < pinned_args.length(); index ++) {
2579 int i = pinned_args.at(index);
2580 assert(pinned_slot <= stack_slots, "overflow");
2581 if (!in_regs[i].first()->is_stack()) {
2582 int offset = pinned_slot * VMRegImpl::stack_slot_size;
2583 __ movq(in_regs[i].first()->as_Register(), Address(rsp, offset));
2584 pinned_slot += VMRegImpl::slots_per_word;
2585 }
2586 gen_unpin_object(masm, in_regs[i]);
2587 }
2588 restore_native_result(masm, ret_type, stack_slots);
2589 }
2590
2591 // Switch thread to "native transition" state before reading the synchronization state.
2592 // This additional state is necessary because reading and testing the synchronization
2593 // state is not atomic w.r.t. GC, as this scenario demonstrates:
2594 // Java thread A, in _thread_in_native state, loads _not_synchronized and is preempted.
2595 // VM thread changes sync state to synchronizing and suspends threads for GC.
2596 // Thread A is resumed to finish this native method, but doesn't block here since it
2597 // didn't see any synchronization is progress, and escapes.
2598 __ movl(Address(r15_thread, JavaThread::thread_state_offset()), _thread_in_native_trans);
2599
2600 // Force this write out before the read below
2601 __ membar(Assembler::Membar_mask_bits(
2602 Assembler::LoadLoad | Assembler::LoadStore |
2603 Assembler::StoreLoad | Assembler::StoreStore));
2604
2605 Label after_transition;
2606
2607 // check for safepoint operation in progress and/or pending suspend requests
2608 {
2609 Label Continue;
2610 Label slow_path;
2611
2612 __ safepoint_poll(slow_path, r15_thread, rscratch1);
2613
2614 __ cmpl(Address(r15_thread, JavaThread::suspend_flags_offset()), 0);
2615 __ jcc(Assembler::equal, Continue);
2616 __ bind(slow_path);
2617
2618 // Don't use call_VM as it will see a possible pending exception and forward it
2619 // and never return here preventing us from clearing _last_native_pc down below.
2620 // Also can't use call_VM_leaf either as it will check to see if rsi & rdi are
2621 // preserved and correspond to the bcp/locals pointers. So we do a runtime call
2622 // by hand.
2623 //
2624 __ vzeroupper();
2625 save_native_result(masm, ret_type, stack_slots);
2626 __ mov(c_rarg0, r15_thread);
2627 __ mov(r12, rsp); // remember sp
2628 __ subptr(rsp, frame::arg_reg_save_area_bytes); // windows
2629 __ andptr(rsp, -16); // align stack as required by ABI
2630 if (!is_critical_native) {
2631 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, JavaThread::check_special_condition_for_native_trans)));
2632 } else {
2633 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, JavaThread::check_special_condition_for_native_trans_and_transition)));
2634 }
2635 __ mov(rsp, r12); // restore sp
2636 __ reinit_heapbase();
2637 // Restore any method result value
2638 restore_native_result(masm, ret_type, stack_slots);
2639
2640 if (is_critical_native) {
2641 // The call above performed the transition to thread_in_Java so
2642 // skip the transition logic below.
2643 __ jmpb(after_transition);
2644 }
2645
2646 __ bind(Continue);
2647 }
2648
2649 // change thread state
2650 __ movl(Address(r15_thread, JavaThread::thread_state_offset()), _thread_in_Java);
2651 __ bind(after_transition);
2652
2653 Label reguard;
2654 Label reguard_done;
2655 __ cmpl(Address(r15_thread, JavaThread::stack_guard_state_offset()), JavaThread::stack_guard_yellow_reserved_disabled);
2656 __ jcc(Assembler::equal, reguard);
2657 __ bind(reguard_done);
2658
2659 // native result if any is live
2660
2661 // Unlock
2662 Label unlock_done;
2663 Label slow_path_unlock;
2664 if (method->is_synchronized()) {
2665
2666 // Get locked oop from the handle we passed to jni
2667 __ movptr(obj_reg, Address(oop_handle_reg, 0));
2668 __ resolve(IS_NOT_NULL, obj_reg);
2669
2670 Label done;
2671
2672 if (UseBiasedLocking) {
2673 __ biased_locking_exit(obj_reg, old_hdr, done);
2674 }
2675
2676 // Simple recursive lock?
2677
2678 __ cmpptr(Address(rsp, lock_slot_offset * VMRegImpl::stack_slot_size), (int32_t)NULL_WORD);
2679 __ jcc(Assembler::equal, done);
2680
2681 // Must save rax if if it is live now because cmpxchg must use it
2682 if (ret_type != T_FLOAT && ret_type != T_DOUBLE && ret_type != T_VOID) {
2683 save_native_result(masm, ret_type, stack_slots);
2684 }
2685
2686
2687 // get address of the stack lock
2688 __ lea(rax, Address(rsp, lock_slot_offset * VMRegImpl::stack_slot_size));
2689 // get old displaced header
2690 __ movptr(old_hdr, Address(rax, 0));
2691
2692 // Atomic swap old header if oop still contains the stack lock
2693 __ lock();
2694 __ cmpxchgptr(old_hdr, Address(obj_reg, oopDesc::mark_offset_in_bytes()));
2695 __ jcc(Assembler::notEqual, slow_path_unlock);
2696
2697 // slow path re-enters here
2698 __ bind(unlock_done);
2699 if (ret_type != T_FLOAT && ret_type != T_DOUBLE && ret_type != T_VOID) {
2700 restore_native_result(masm, ret_type, stack_slots);
2701 }
2702
2703 __ bind(done);
2704
2705 }
2706 {
2707 SkipIfEqual skip(masm, &DTraceMethodProbes, false);
2708 save_native_result(masm, ret_type, stack_slots);
2709 __ mov_metadata(c_rarg1, method());
2710 __ call_VM_leaf(
2711 CAST_FROM_FN_PTR(address, SharedRuntime::dtrace_method_exit),
2712 r15_thread, c_rarg1);
2713 restore_native_result(masm, ret_type, stack_slots);
2714 }
2715
2716 __ reset_last_Java_frame(false);
2717
2718 // Unbox oop result, e.g. JNIHandles::resolve value.
2719 if (is_reference_type(ret_type)) {
2720 __ resolve_jobject(rax /* value */,
2721 r15_thread /* thread */,
2722 rcx /* tmp */);
2723 }
2724
2725 if (CheckJNICalls) {
2726 // clear_pending_jni_exception_check
2727 __ movptr(Address(r15_thread, JavaThread::pending_jni_exception_check_fn_offset()), NULL_WORD);
2728 }
2729
2730 if (!is_critical_native) {
2731 // reset handle block
2732 __ movptr(rcx, Address(r15_thread, JavaThread::active_handles_offset()));
2733 __ movl(Address(rcx, JNIHandleBlock::top_offset_in_bytes()), (int32_t)NULL_WORD);
2734 }
2735
2736 // pop our frame
2737
2738 __ leave();
2739
2740 if (!is_critical_native) {
2741 // Any exception pending?
2742 __ cmpptr(Address(r15_thread, in_bytes(Thread::pending_exception_offset())), (int32_t)NULL_WORD);
2743 __ jcc(Assembler::notEqual, exception_pending);
2744 }
2745
2746 // Return
2747
2748 __ ret(0);
2749
2750 // Unexpected paths are out of line and go here
2751
2752 if (!is_critical_native) {
2753 // forward the exception
2754 __ bind(exception_pending);
2755
2756 // and forward the exception
2757 __ jump(RuntimeAddress(StubRoutines::forward_exception_entry()));
2758 }
2759
2760 // Slow path locking & unlocking
2761 if (method->is_synchronized()) {
2762
2763 // BEGIN Slow path lock
2764 __ bind(slow_path_lock);
2765
2766 // has last_Java_frame setup. No exceptions so do vanilla call not call_VM
2767 // args are (oop obj, BasicLock* lock, JavaThread* thread)
2768
2769 // protect the args we've loaded
2770 save_args(masm, total_c_args, c_arg, out_regs);
2771
2772 __ mov(c_rarg0, obj_reg);
2773 __ mov(c_rarg1, lock_reg);
2774 __ mov(c_rarg2, r15_thread);
2775
2776 // Not a leaf but we have last_Java_frame setup as we want
2777 __ call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::complete_monitor_locking_C), 3);
2778 restore_args(masm, total_c_args, c_arg, out_regs);
2779
2780 #ifdef ASSERT
2781 { Label L;
2782 __ cmpptr(Address(r15_thread, in_bytes(Thread::pending_exception_offset())), (int32_t)NULL_WORD);
2783 __ jcc(Assembler::equal, L);
2784 __ stop("no pending exception allowed on exit from monitorenter");
2785 __ bind(L);
2786 }
2787 #endif
2788 __ jmp(lock_done);
2789
2790 // END Slow path lock
2791
2792 // BEGIN Slow path unlock
2793 __ bind(slow_path_unlock);
2794
2795 // If we haven't already saved the native result we must save it now as xmm registers
2796 // are still exposed.
2797 __ vzeroupper();
2798 if (ret_type == T_FLOAT || ret_type == T_DOUBLE ) {
2799 save_native_result(masm, ret_type, stack_slots);
2800 }
2801
2802 __ lea(c_rarg1, Address(rsp, lock_slot_offset * VMRegImpl::stack_slot_size));
2803
2804 __ mov(c_rarg0, obj_reg);
2805 __ mov(c_rarg2, r15_thread);
2806 __ mov(r12, rsp); // remember sp
2807 __ subptr(rsp, frame::arg_reg_save_area_bytes); // windows
2808 __ andptr(rsp, -16); // align stack as required by ABI
2809
2810 // Save pending exception around call to VM (which contains an EXCEPTION_MARK)
2811 // NOTE that obj_reg == rbx currently
2812 __ movptr(rbx, Address(r15_thread, in_bytes(Thread::pending_exception_offset())));
2813 __ movptr(Address(r15_thread, in_bytes(Thread::pending_exception_offset())), (int32_t)NULL_WORD);
2814
2815 // args are (oop obj, BasicLock* lock, JavaThread* thread)
2816 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, SharedRuntime::complete_monitor_unlocking_C)));
2817 __ mov(rsp, r12); // restore sp
2818 __ reinit_heapbase();
2819 #ifdef ASSERT
2820 {
2821 Label L;
2822 __ cmpptr(Address(r15_thread, in_bytes(Thread::pending_exception_offset())), (int)NULL_WORD);
2823 __ jcc(Assembler::equal, L);
2824 __ stop("no pending exception allowed on exit complete_monitor_unlocking_C");
2825 __ bind(L);
2826 }
2827 #endif /* ASSERT */
2828
2829 __ movptr(Address(r15_thread, in_bytes(Thread::pending_exception_offset())), rbx);
2830
2831 if (ret_type == T_FLOAT || ret_type == T_DOUBLE ) {
2832 restore_native_result(masm, ret_type, stack_slots);
2833 }
2834 __ jmp(unlock_done);
2835
2836 // END Slow path unlock
2837
2838 } // synchronized
2839
2840 // SLOW PATH Reguard the stack if needed
2841
2842 __ bind(reguard);
2843 __ vzeroupper();
2844 save_native_result(masm, ret_type, stack_slots);
2845 __ mov(r12, rsp); // remember sp
2846 __ subptr(rsp, frame::arg_reg_save_area_bytes); // windows
2847 __ andptr(rsp, -16); // align stack as required by ABI
2848 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, SharedRuntime::reguard_yellow_pages)));
2849 __ mov(rsp, r12); // restore sp
2850 __ reinit_heapbase();
2851 restore_native_result(masm, ret_type, stack_slots);
2852 // and continue
2853 __ jmp(reguard_done);
2854
2855
2856
2857 __ flush();
2858
2859 nmethod *nm = nmethod::new_native_nmethod(method,
2860 compile_id,
2861 masm->code(),
2862 vep_offset,
2863 frame_complete,
2864 stack_slots / VMRegImpl::slots_per_word,
2865 (is_static ? in_ByteSize(klass_offset) : in_ByteSize(receiver_offset)),
2866 in_ByteSize(lock_slot_offset*VMRegImpl::stack_slot_size),
2867 oop_maps);
2868
2869 if (is_critical_native) {
2870 nm->set_lazy_critical_native(true);
2871 }
2872
2873 return nm;
2874
2875 }
2876
2877 // this function returns the adjust size (in number of words) to a c2i adapter
2878 // activation for use during deoptimization
2879 int Deoptimization::last_frame_adjust(int callee_parameters, int callee_locals ) {
2880 return (callee_locals - callee_parameters) * Interpreter::stackElementWords;
2881 }
2882
2883
2884 uint SharedRuntime::out_preserve_stack_slots() {
2885 return 0;
2886 }
2887
2888 //------------------------------generate_deopt_blob----------------------------
2889 void SharedRuntime::generate_deopt_blob() {
2890 // Allocate space for the code
2891 ResourceMark rm;
2892 // Setup code generation tools
2893 int pad = 0;
2894 #if INCLUDE_JVMCI
2895 if (EnableJVMCI || UseAOT) {
2896 pad += 512; // Increase the buffer size when compiling for JVMCI
2897 }
2898 #endif
2899 CodeBuffer buffer("deopt_blob", 2048+pad, 1024);
2900 MacroAssembler* masm = new MacroAssembler(&buffer);
2901 int frame_size_in_words;
2902 OopMap* map = NULL;
2903 OopMapSet *oop_maps = new OopMapSet();
2904
2905 // -------------
2906 // This code enters when returning to a de-optimized nmethod. A return
2907 // address has been pushed on the the stack, and return values are in
2908 // registers.
2909 // If we are doing a normal deopt then we were called from the patched
2910 // nmethod from the point we returned to the nmethod. So the return
2911 // address on the stack is wrong by NativeCall::instruction_size
2912 // We will adjust the value so it looks like we have the original return
2913 // address on the stack (like when we eagerly deoptimized).
2914 // In the case of an exception pending when deoptimizing, we enter
2915 // with a return address on the stack that points after the call we patched
2916 // into the exception handler. We have the following register state from,
2917 // e.g., the forward exception stub (see stubGenerator_x86_64.cpp).
2918 // rax: exception oop
2919 // rbx: exception handler
2920 // rdx: throwing pc
2921 // So in this case we simply jam rdx into the useless return address and
2922 // the stack looks just like we want.
2923 //
2924 // At this point we need to de-opt. We save the argument return
2925 // registers. We call the first C routine, fetch_unroll_info(). This
2926 // routine captures the return values and returns a structure which
2927 // describes the current frame size and the sizes of all replacement frames.
2928 // The current frame is compiled code and may contain many inlined
2929 // functions, each with their own JVM state. We pop the current frame, then
2930 // push all the new frames. Then we call the C routine unpack_frames() to
2931 // populate these frames. Finally unpack_frames() returns us the new target
2932 // address. Notice that callee-save registers are BLOWN here; they have
2933 // already been captured in the vframeArray at the time the return PC was
2934 // patched.
2935 address start = __ pc();
2936 Label cont;
2937
2938 // Prolog for non exception case!
2939
2940 // Save everything in sight.
2941 map = RegisterSaver::save_live_registers(masm, 0, &frame_size_in_words);
2942
2943 // Normal deoptimization. Save exec mode for unpack_frames.
2944 __ movl(r14, Deoptimization::Unpack_deopt); // callee-saved
2945 __ jmp(cont);
2946
2947 int reexecute_offset = __ pc() - start;
2948 #if INCLUDE_JVMCI && !defined(COMPILER1)
2949 if (EnableJVMCI && UseJVMCICompiler) {
2950 // JVMCI does not use this kind of deoptimization
2951 __ should_not_reach_here();
2952 }
2953 #endif
2954
2955 // Reexecute case
2956 // return address is the pc describes what bci to do re-execute at
2957
2958 // No need to update map as each call to save_live_registers will produce identical oopmap
2959 (void) RegisterSaver::save_live_registers(masm, 0, &frame_size_in_words);
2960
2961 __ movl(r14, Deoptimization::Unpack_reexecute); // callee-saved
2962 __ jmp(cont);
2963
2964 #if INCLUDE_JVMCI
2965 Label after_fetch_unroll_info_call;
2966 int implicit_exception_uncommon_trap_offset = 0;
2967 int uncommon_trap_offset = 0;
2968
2969 if (EnableJVMCI || UseAOT) {
2970 implicit_exception_uncommon_trap_offset = __ pc() - start;
2971
2972 __ pushptr(Address(r15_thread, in_bytes(JavaThread::jvmci_implicit_exception_pc_offset())));
2973 __ movptr(Address(r15_thread, in_bytes(JavaThread::jvmci_implicit_exception_pc_offset())), (int32_t)NULL_WORD);
2974
2975 uncommon_trap_offset = __ pc() - start;
2976
2977 // Save everything in sight.
2978 RegisterSaver::save_live_registers(masm, 0, &frame_size_in_words);
2979 // fetch_unroll_info needs to call last_java_frame()
2980 __ set_last_Java_frame(noreg, noreg, NULL);
2981
2982 __ movl(c_rarg1, Address(r15_thread, in_bytes(JavaThread::pending_deoptimization_offset())));
2983 __ movl(Address(r15_thread, in_bytes(JavaThread::pending_deoptimization_offset())), -1);
2984
2985 __ movl(r14, (int32_t)Deoptimization::Unpack_reexecute);
2986 __ mov(c_rarg0, r15_thread);
2987 __ movl(c_rarg2, r14); // exec mode
2988 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, Deoptimization::uncommon_trap)));
2989 oop_maps->add_gc_map( __ pc()-start, map->deep_copy());
2990
2991 __ reset_last_Java_frame(false);
2992
2993 __ jmp(after_fetch_unroll_info_call);
2994 } // EnableJVMCI
2995 #endif // INCLUDE_JVMCI
2996
2997 int exception_offset = __ pc() - start;
2998
2999 // Prolog for exception case
3000
3001 // all registers are dead at this entry point, except for rax, and
3002 // rdx which contain the exception oop and exception pc
3003 // respectively. Set them in TLS and fall thru to the
3004 // unpack_with_exception_in_tls entry point.
3005
3006 __ movptr(Address(r15_thread, JavaThread::exception_pc_offset()), rdx);
3007 __ movptr(Address(r15_thread, JavaThread::exception_oop_offset()), rax);
3008
3009 int exception_in_tls_offset = __ pc() - start;
3010
3011 // new implementation because exception oop is now passed in JavaThread
3012
3013 // Prolog for exception case
3014 // All registers must be preserved because they might be used by LinearScan
3015 // Exceptiop oop and throwing PC are passed in JavaThread
3016 // tos: stack at point of call to method that threw the exception (i.e. only
3017 // args are on the stack, no return address)
3018
3019 // make room on stack for the return address
3020 // It will be patched later with the throwing pc. The correct value is not
3021 // available now because loading it from memory would destroy registers.
3022 __ push(0);
3023
3024 // Save everything in sight.
3025 map = RegisterSaver::save_live_registers(masm, 0, &frame_size_in_words);
3026
3027 // Now it is safe to overwrite any register
3028
3029 // Deopt during an exception. Save exec mode for unpack_frames.
3030 __ movl(r14, Deoptimization::Unpack_exception); // callee-saved
3031
3032 // load throwing pc from JavaThread and patch it as the return address
3033 // of the current frame. Then clear the field in JavaThread
3034
3035 __ movptr(rdx, Address(r15_thread, JavaThread::exception_pc_offset()));
3036 __ movptr(Address(rbp, wordSize), rdx);
3037 __ movptr(Address(r15_thread, JavaThread::exception_pc_offset()), (int32_t)NULL_WORD);
3038
3039 #ifdef ASSERT
3040 // verify that there is really an exception oop in JavaThread
3041 __ movptr(rax, Address(r15_thread, JavaThread::exception_oop_offset()));
3042 __ verify_oop(rax);
3043
3044 // verify that there is no pending exception
3045 Label no_pending_exception;
3046 __ movptr(rax, Address(r15_thread, Thread::pending_exception_offset()));
3047 __ testptr(rax, rax);
3048 __ jcc(Assembler::zero, no_pending_exception);
3049 __ stop("must not have pending exception here");
3050 __ bind(no_pending_exception);
3051 #endif
3052
3053 __ bind(cont);
3054
3055 // Call C code. Need thread and this frame, but NOT official VM entry
3056 // crud. We cannot block on this call, no GC can happen.
3057 //
3058 // UnrollBlock* fetch_unroll_info(JavaThread* thread)
3059
3060 // fetch_unroll_info needs to call last_java_frame().
3061
3062 __ set_last_Java_frame(noreg, noreg, NULL);
3063 #ifdef ASSERT
3064 { Label L;
3065 __ cmpptr(Address(r15_thread,
3066 JavaThread::last_Java_fp_offset()),
3067 (int32_t)0);
3068 __ jcc(Assembler::equal, L);
3069 __ stop("SharedRuntime::generate_deopt_blob: last_Java_fp not cleared");
3070 __ bind(L);
3071 }
3072 #endif // ASSERT
3073 __ mov(c_rarg0, r15_thread);
3074 __ movl(c_rarg1, r14); // exec_mode
3075 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, Deoptimization::fetch_unroll_info)));
3076
3077 // Need to have an oopmap that tells fetch_unroll_info where to
3078 // find any register it might need.
3079 oop_maps->add_gc_map(__ pc() - start, map);
3080
3081 __ reset_last_Java_frame(false);
3082
3083 #if INCLUDE_JVMCI
3084 if (EnableJVMCI || UseAOT) {
3085 __ bind(after_fetch_unroll_info_call);
3086 }
3087 #endif
3088
3089 // Load UnrollBlock* into rdi
3090 __ mov(rdi, rax);
3091
3092 __ movl(r14, Address(rdi, Deoptimization::UnrollBlock::unpack_kind_offset_in_bytes()));
3093 Label noException;
3094 __ cmpl(r14, Deoptimization::Unpack_exception); // Was exception pending?
3095 __ jcc(Assembler::notEqual, noException);
3096 __ movptr(rax, Address(r15_thread, JavaThread::exception_oop_offset()));
3097 // QQQ this is useless it was NULL above
3098 __ movptr(rdx, Address(r15_thread, JavaThread::exception_pc_offset()));
3099 __ movptr(Address(r15_thread, JavaThread::exception_oop_offset()), (int32_t)NULL_WORD);
3100 __ movptr(Address(r15_thread, JavaThread::exception_pc_offset()), (int32_t)NULL_WORD);
3101
3102 __ verify_oop(rax);
3103
3104 // Overwrite the result registers with the exception results.
3105 __ movptr(Address(rsp, RegisterSaver::rax_offset_in_bytes()), rax);
3106 // I think this is useless
3107 __ movptr(Address(rsp, RegisterSaver::rdx_offset_in_bytes()), rdx);
3108
3109 __ bind(noException);
3110
3111 // Only register save data is on the stack.
3112 // Now restore the result registers. Everything else is either dead
3113 // or captured in the vframeArray.
3114 RegisterSaver::restore_result_registers(masm);
3115
3116 // All of the register save area has been popped of the stack. Only the
3117 // return address remains.
3118
3119 // Pop all the frames we must move/replace.
3120 //
3121 // Frame picture (youngest to oldest)
3122 // 1: self-frame (no frame link)
3123 // 2: deopting frame (no frame link)
3124 // 3: caller of deopting frame (could be compiled/interpreted).
3125 //
3126 // Note: by leaving the return address of self-frame on the stack
3127 // and using the size of frame 2 to adjust the stack
3128 // when we are done the return to frame 3 will still be on the stack.
3129
3130 // Pop deoptimized frame
3131 __ movl(rcx, Address(rdi, Deoptimization::UnrollBlock::size_of_deoptimized_frame_offset_in_bytes()));
3132 __ addptr(rsp, rcx);
3133
3134 // rsp should be pointing at the return address to the caller (3)
3135
3136 // Pick up the initial fp we should save
3137 // restore rbp before stack bang because if stack overflow is thrown it needs to be pushed (and preserved)
3138 __ movptr(rbp, Address(rdi, Deoptimization::UnrollBlock::initial_info_offset_in_bytes()));
3139
3140 #ifdef ASSERT
3141 // Compilers generate code that bang the stack by as much as the
3142 // interpreter would need. So this stack banging should never
3143 // trigger a fault. Verify that it does not on non product builds.
3144 if (UseStackBanging) {
3145 __ movl(rbx, Address(rdi, Deoptimization::UnrollBlock::total_frame_sizes_offset_in_bytes()));
3146 __ bang_stack_size(rbx, rcx);
3147 }
3148 #endif
3149
3150 // Load address of array of frame pcs into rcx
3151 __ movptr(rcx, Address(rdi, Deoptimization::UnrollBlock::frame_pcs_offset_in_bytes()));
3152
3153 // Trash the old pc
3154 __ addptr(rsp, wordSize);
3155
3156 // Load address of array of frame sizes into rsi
3157 __ movptr(rsi, Address(rdi, Deoptimization::UnrollBlock::frame_sizes_offset_in_bytes()));
3158
3159 // Load counter into rdx
3160 __ movl(rdx, Address(rdi, Deoptimization::UnrollBlock::number_of_frames_offset_in_bytes()));
3161
3162 // Now adjust the caller's stack to make up for the extra locals
3163 // but record the original sp so that we can save it in the skeletal interpreter
3164 // frame and the stack walking of interpreter_sender will get the unextended sp
3165 // value and not the "real" sp value.
3166
3167 const Register sender_sp = r8;
3168
3169 __ mov(sender_sp, rsp);
3170 __ movl(rbx, Address(rdi,
3171 Deoptimization::UnrollBlock::
3172 caller_adjustment_offset_in_bytes()));
3173 __ subptr(rsp, rbx);
3174
3175 // Push interpreter frames in a loop
3176 Label loop;
3177 __ bind(loop);
3178 __ movptr(rbx, Address(rsi, 0)); // Load frame size
3179 __ subptr(rbx, 2*wordSize); // We'll push pc and ebp by hand
3180 __ pushptr(Address(rcx, 0)); // Save return address
3181 __ enter(); // Save old & set new ebp
3182 __ subptr(rsp, rbx); // Prolog
3183 // This value is corrected by layout_activation_impl
3184 __ movptr(Address(rbp, frame::interpreter_frame_last_sp_offset * wordSize), (int32_t)NULL_WORD );
3185 __ movptr(Address(rbp, frame::interpreter_frame_sender_sp_offset * wordSize), sender_sp); // Make it walkable
3186 __ mov(sender_sp, rsp); // Pass sender_sp to next frame
3187 __ addptr(rsi, wordSize); // Bump array pointer (sizes)
3188 __ addptr(rcx, wordSize); // Bump array pointer (pcs)
3189 __ decrementl(rdx); // Decrement counter
3190 __ jcc(Assembler::notZero, loop);
3191 __ pushptr(Address(rcx, 0)); // Save final return address
3192
3193 // Re-push self-frame
3194 __ enter(); // Save old & set new ebp
3195
3196 // Allocate a full sized register save area.
3197 // Return address and rbp are in place, so we allocate two less words.
3198 __ subptr(rsp, (frame_size_in_words - 2) * wordSize);
3199
3200 // Restore frame locals after moving the frame
3201 __ movdbl(Address(rsp, RegisterSaver::xmm0_offset_in_bytes()), xmm0);
3202 __ movptr(Address(rsp, RegisterSaver::rax_offset_in_bytes()), rax);
3203
3204 // Call C code. Need thread but NOT official VM entry
3205 // crud. We cannot block on this call, no GC can happen. Call should
3206 // restore return values to their stack-slots with the new SP.
3207 //
3208 // void Deoptimization::unpack_frames(JavaThread* thread, int exec_mode)
3209
3210 // Use rbp because the frames look interpreted now
3211 // Save "the_pc" since it cannot easily be retrieved using the last_java_SP after we aligned SP.
3212 // Don't need the precise return PC here, just precise enough to point into this code blob.
3213 address the_pc = __ pc();
3214 __ set_last_Java_frame(noreg, rbp, the_pc);
3215
3216 __ andptr(rsp, -(StackAlignmentInBytes)); // Fix stack alignment as required by ABI
3217 __ mov(c_rarg0, r15_thread);
3218 __ movl(c_rarg1, r14); // second arg: exec_mode
3219 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, Deoptimization::unpack_frames)));
3220 // Revert SP alignment after call since we're going to do some SP relative addressing below
3221 __ movptr(rsp, Address(r15_thread, JavaThread::last_Java_sp_offset()));
3222
3223 // Set an oopmap for the call site
3224 // Use the same PC we used for the last java frame
3225 oop_maps->add_gc_map(the_pc - start,
3226 new OopMap( frame_size_in_words, 0 ));
3227
3228 // Clear fp AND pc
3229 __ reset_last_Java_frame(true);
3230
3231 // Collect return values
3232 __ movdbl(xmm0, Address(rsp, RegisterSaver::xmm0_offset_in_bytes()));
3233 __ movptr(rax, Address(rsp, RegisterSaver::rax_offset_in_bytes()));
3234 // I think this is useless (throwing pc?)
3235 __ movptr(rdx, Address(rsp, RegisterSaver::rdx_offset_in_bytes()));
3236
3237 // Pop self-frame.
3238 __ leave(); // Epilog
3239
3240 // Jump to interpreter
3241 __ ret(0);
3242
3243 // Make sure all code is generated
3244 masm->flush();
3245
3246 _deopt_blob = DeoptimizationBlob::create(&buffer, oop_maps, 0, exception_offset, reexecute_offset, frame_size_in_words);
3247 _deopt_blob->set_unpack_with_exception_in_tls_offset(exception_in_tls_offset);
3248 #if INCLUDE_JVMCI
3249 if (EnableJVMCI || UseAOT) {
3250 _deopt_blob->set_uncommon_trap_offset(uncommon_trap_offset);
3251 _deopt_blob->set_implicit_exception_uncommon_trap_offset(implicit_exception_uncommon_trap_offset);
3252 }
3253 #endif
3254 }
3255
3256 #ifdef COMPILER2
3257 //------------------------------generate_uncommon_trap_blob--------------------
3258 void SharedRuntime::generate_uncommon_trap_blob() {
3259 // Allocate space for the code
3260 ResourceMark rm;
3261 // Setup code generation tools
3262 CodeBuffer buffer("uncommon_trap_blob", 2048, 1024);
3263 MacroAssembler* masm = new MacroAssembler(&buffer);
3264
3265 assert(SimpleRuntimeFrame::framesize % 4 == 0, "sp not 16-byte aligned");
3266
3267 address start = __ pc();
3268
3269 if (UseRTMLocking) {
3270 // Abort RTM transaction before possible nmethod deoptimization.
3271 __ xabort(0);
3272 }
3273
3274 // Push self-frame. We get here with a return address on the
3275 // stack, so rsp is 8-byte aligned until we allocate our frame.
3276 __ subptr(rsp, SimpleRuntimeFrame::return_off << LogBytesPerInt); // Epilog!
3277
3278 // No callee saved registers. rbp is assumed implicitly saved
3279 __ movptr(Address(rsp, SimpleRuntimeFrame::rbp_off << LogBytesPerInt), rbp);
3280
3281 // compiler left unloaded_class_index in j_rarg0 move to where the
3282 // runtime expects it.
3283 __ movl(c_rarg1, j_rarg0);
3284
3285 __ set_last_Java_frame(noreg, noreg, NULL);
3286
3287 // Call C code. Need thread but NOT official VM entry
3288 // crud. We cannot block on this call, no GC can happen. Call should
3289 // capture callee-saved registers as well as return values.
3290 // Thread is in rdi already.
3291 //
3292 // UnrollBlock* uncommon_trap(JavaThread* thread, jint unloaded_class_index);
3293
3294 __ mov(c_rarg0, r15_thread);
3295 __ movl(c_rarg2, Deoptimization::Unpack_uncommon_trap);
3296 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, Deoptimization::uncommon_trap)));
3297
3298 // Set an oopmap for the call site
3299 OopMapSet* oop_maps = new OopMapSet();
3300 OopMap* map = new OopMap(SimpleRuntimeFrame::framesize, 0);
3301
3302 // location of rbp is known implicitly by the frame sender code
3303
3304 oop_maps->add_gc_map(__ pc() - start, map);
3305
3306 __ reset_last_Java_frame(false);
3307
3308 // Load UnrollBlock* into rdi
3309 __ mov(rdi, rax);
3310
3311 #ifdef ASSERT
3312 { Label L;
3313 __ cmpptr(Address(rdi, Deoptimization::UnrollBlock::unpack_kind_offset_in_bytes()),
3314 (int32_t)Deoptimization::Unpack_uncommon_trap);
3315 __ jcc(Assembler::equal, L);
3316 __ stop("SharedRuntime::generate_deopt_blob: expected Unpack_uncommon_trap");
3317 __ bind(L);
3318 }
3319 #endif
3320
3321 // Pop all the frames we must move/replace.
3322 //
3323 // Frame picture (youngest to oldest)
3324 // 1: self-frame (no frame link)
3325 // 2: deopting frame (no frame link)
3326 // 3: caller of deopting frame (could be compiled/interpreted).
3327
3328 // Pop self-frame. We have no frame, and must rely only on rax and rsp.
3329 __ addptr(rsp, (SimpleRuntimeFrame::framesize - 2) << LogBytesPerInt); // Epilog!
3330
3331 // Pop deoptimized frame (int)
3332 __ movl(rcx, Address(rdi,
3333 Deoptimization::UnrollBlock::
3334 size_of_deoptimized_frame_offset_in_bytes()));
3335 __ addptr(rsp, rcx);
3336
3337 // rsp should be pointing at the return address to the caller (3)
3338
3339 // Pick up the initial fp we should save
3340 // restore rbp before stack bang because if stack overflow is thrown it needs to be pushed (and preserved)
3341 __ movptr(rbp, Address(rdi, Deoptimization::UnrollBlock::initial_info_offset_in_bytes()));
3342
3343 #ifdef ASSERT
3344 // Compilers generate code that bang the stack by as much as the
3345 // interpreter would need. So this stack banging should never
3346 // trigger a fault. Verify that it does not on non product builds.
3347 if (UseStackBanging) {
3348 __ movl(rbx, Address(rdi ,Deoptimization::UnrollBlock::total_frame_sizes_offset_in_bytes()));
3349 __ bang_stack_size(rbx, rcx);
3350 }
3351 #endif
3352
3353 // Load address of array of frame pcs into rcx (address*)
3354 __ movptr(rcx, Address(rdi, Deoptimization::UnrollBlock::frame_pcs_offset_in_bytes()));
3355
3356 // Trash the return pc
3357 __ addptr(rsp, wordSize);
3358
3359 // Load address of array of frame sizes into rsi (intptr_t*)
3360 __ movptr(rsi, Address(rdi, Deoptimization::UnrollBlock:: frame_sizes_offset_in_bytes()));
3361
3362 // Counter
3363 __ movl(rdx, Address(rdi, Deoptimization::UnrollBlock:: number_of_frames_offset_in_bytes())); // (int)
3364
3365 // Now adjust the caller's stack to make up for the extra locals but
3366 // record the original sp so that we can save it in the skeletal
3367 // interpreter frame and the stack walking of interpreter_sender
3368 // will get the unextended sp value and not the "real" sp value.
3369
3370 const Register sender_sp = r8;
3371
3372 __ mov(sender_sp, rsp);
3373 __ movl(rbx, Address(rdi, Deoptimization::UnrollBlock:: caller_adjustment_offset_in_bytes())); // (int)
3374 __ subptr(rsp, rbx);
3375
3376 // Push interpreter frames in a loop
3377 Label loop;
3378 __ bind(loop);
3379 __ movptr(rbx, Address(rsi, 0)); // Load frame size
3380 __ subptr(rbx, 2 * wordSize); // We'll push pc and rbp by hand
3381 __ pushptr(Address(rcx, 0)); // Save return address
3382 __ enter(); // Save old & set new rbp
3383 __ subptr(rsp, rbx); // Prolog
3384 __ movptr(Address(rbp, frame::interpreter_frame_sender_sp_offset * wordSize),
3385 sender_sp); // Make it walkable
3386 // This value is corrected by layout_activation_impl
3387 __ movptr(Address(rbp, frame::interpreter_frame_last_sp_offset * wordSize), (int32_t)NULL_WORD );
3388 __ mov(sender_sp, rsp); // Pass sender_sp to next frame
3389 __ addptr(rsi, wordSize); // Bump array pointer (sizes)
3390 __ addptr(rcx, wordSize); // Bump array pointer (pcs)
3391 __ decrementl(rdx); // Decrement counter
3392 __ jcc(Assembler::notZero, loop);
3393 __ pushptr(Address(rcx, 0)); // Save final return address
3394
3395 // Re-push self-frame
3396 __ enter(); // Save old & set new rbp
3397 __ subptr(rsp, (SimpleRuntimeFrame::framesize - 4) << LogBytesPerInt);
3398 // Prolog
3399
3400 // Use rbp because the frames look interpreted now
3401 // Save "the_pc" since it cannot easily be retrieved using the last_java_SP after we aligned SP.
3402 // Don't need the precise return PC here, just precise enough to point into this code blob.
3403 address the_pc = __ pc();
3404 __ set_last_Java_frame(noreg, rbp, the_pc);
3405
3406 // Call C code. Need thread but NOT official VM entry
3407 // crud. We cannot block on this call, no GC can happen. Call should
3408 // restore return values to their stack-slots with the new SP.
3409 // Thread is in rdi already.
3410 //
3411 // BasicType unpack_frames(JavaThread* thread, int exec_mode);
3412
3413 __ andptr(rsp, -(StackAlignmentInBytes)); // Align SP as required by ABI
3414 __ mov(c_rarg0, r15_thread);
3415 __ movl(c_rarg1, Deoptimization::Unpack_uncommon_trap);
3416 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, Deoptimization::unpack_frames)));
3417
3418 // Set an oopmap for the call site
3419 // Use the same PC we used for the last java frame
3420 oop_maps->add_gc_map(the_pc - start, new OopMap(SimpleRuntimeFrame::framesize, 0));
3421
3422 // Clear fp AND pc
3423 __ reset_last_Java_frame(true);
3424
3425 // Pop self-frame.
3426 __ leave(); // Epilog
3427
3428 // Jump to interpreter
3429 __ ret(0);
3430
3431 // Make sure all code is generated
3432 masm->flush();
3433
3434 _uncommon_trap_blob = UncommonTrapBlob::create(&buffer, oop_maps,
3435 SimpleRuntimeFrame::framesize >> 1);
3436 }
3437 #endif // COMPILER2
3438
3439
3440 //------------------------------generate_handler_blob------
3441 //
3442 // Generate a special Compile2Runtime blob that saves all registers,
3443 // and setup oopmap.
3444 //
3445 SafepointBlob* SharedRuntime::generate_handler_blob(address call_ptr, int poll_type) {
3446 assert(StubRoutines::forward_exception_entry() != NULL,
3447 "must be generated before");
3448
3449 ResourceMark rm;
3450 OopMapSet *oop_maps = new OopMapSet();
3451 OopMap* map;
3452
3453 // Allocate space for the code. Setup code generation tools.
3454 CodeBuffer buffer("handler_blob", 2048, 1024);
3455 MacroAssembler* masm = new MacroAssembler(&buffer);
3456
3457 address start = __ pc();
3458 address call_pc = NULL;
3459 int frame_size_in_words;
3460 bool cause_return = (poll_type == POLL_AT_RETURN);
3461 bool save_vectors = (poll_type == POLL_AT_VECTOR_LOOP);
3462
3463 if (UseRTMLocking) {
3464 // Abort RTM transaction before calling runtime
3465 // because critical section will be large and will be
3466 // aborted anyway. Also nmethod could be deoptimized.
3467 __ xabort(0);
3468 }
3469
3470 // Make room for return address (or push it again)
3471 if (!cause_return) {
3472 __ push(rbx);
3473 }
3474
3475 // Save registers, fpu state, and flags
3476 map = RegisterSaver::save_live_registers(masm, 0, &frame_size_in_words, save_vectors);
3477
3478 // The following is basically a call_VM. However, we need the precise
3479 // address of the call in order to generate an oopmap. Hence, we do all the
3480 // work outselves.
3481
3482 __ set_last_Java_frame(noreg, noreg, NULL);
3483
3484 // The return address must always be correct so that frame constructor never
3485 // sees an invalid pc.
3486
3487 if (!cause_return) {
3488 // Get the return pc saved by the signal handler and stash it in its appropriate place on the stack.
3489 // Additionally, rbx is a callee saved register and we can look at it later to determine
3490 // if someone changed the return address for us!
3491 __ movptr(rbx, Address(r15_thread, JavaThread::saved_exception_pc_offset()));
3492 __ movptr(Address(rbp, wordSize), rbx);
3493 }
3494
3495 // Do the call
3496 __ mov(c_rarg0, r15_thread);
3497 __ call(RuntimeAddress(call_ptr));
3498
3499 // Set an oopmap for the call site. This oopmap will map all
3500 // oop-registers and debug-info registers as callee-saved. This
3501 // will allow deoptimization at this safepoint to find all possible
3502 // debug-info recordings, as well as let GC find all oops.
3503
3504 oop_maps->add_gc_map( __ pc() - start, map);
3505
3506 Label noException;
3507
3508 __ reset_last_Java_frame(false);
3509
3510 __ cmpptr(Address(r15_thread, Thread::pending_exception_offset()), (int32_t)NULL_WORD);
3511 __ jcc(Assembler::equal, noException);
3512
3513 // Exception pending
3514
3515 RegisterSaver::restore_live_registers(masm, save_vectors);
3516
3517 __ jump(RuntimeAddress(StubRoutines::forward_exception_entry()));
3518
3519 // No exception case
3520 __ bind(noException);
3521
3522 Label no_adjust;
3523 #ifdef ASSERT
3524 Label bail;
3525 #endif
3526 if (SafepointMechanism::uses_thread_local_poll() && !cause_return) {
3527 Label no_prefix, not_special;
3528
3529 // If our stashed return pc was modified by the runtime we avoid touching it
3530 __ cmpptr(rbx, Address(rbp, wordSize));
3531 __ jccb(Assembler::notEqual, no_adjust);
3532
3533 // Skip over the poll instruction.
3534 // See NativeInstruction::is_safepoint_poll()
3535 // Possible encodings:
3536 // 85 00 test %eax,(%rax)
3537 // 85 01 test %eax,(%rcx)
3538 // 85 02 test %eax,(%rdx)
3539 // 85 03 test %eax,(%rbx)
3540 // 85 06 test %eax,(%rsi)
3541 // 85 07 test %eax,(%rdi)
3542 //
3543 // 41 85 00 test %eax,(%r8)
3544 // 41 85 01 test %eax,(%r9)
3545 // 41 85 02 test %eax,(%r10)
3546 // 41 85 03 test %eax,(%r11)
3547 // 41 85 06 test %eax,(%r14)
3548 // 41 85 07 test %eax,(%r15)
3549 //
3550 // 85 04 24 test %eax,(%rsp)
3551 // 41 85 04 24 test %eax,(%r12)
3552 // 85 45 00 test %eax,0x0(%rbp)
3553 // 41 85 45 00 test %eax,0x0(%r13)
3554
3555 __ cmpb(Address(rbx, 0), NativeTstRegMem::instruction_rex_b_prefix);
3556 __ jcc(Assembler::notEqual, no_prefix);
3557 __ addptr(rbx, 1);
3558 __ bind(no_prefix);
3559 #ifdef ASSERT
3560 __ movptr(rax, rbx); // remember where 0x85 should be, for verification below
3561 #endif
3562 // r12/r13/rsp/rbp base encoding takes 3 bytes with the following register values:
3563 // r12/rsp 0x04
3564 // r13/rbp 0x05
3565 __ movzbq(rcx, Address(rbx, 1));
3566 __ andptr(rcx, 0x07); // looking for 0x04 .. 0x05
3567 __ subptr(rcx, 4); // looking for 0x00 .. 0x01
3568 __ cmpptr(rcx, 1);
3569 __ jcc(Assembler::above, not_special);
3570 __ addptr(rbx, 1);
3571 __ bind(not_special);
3572 #ifdef ASSERT
3573 // Verify the correct encoding of the poll we're about to skip.
3574 __ cmpb(Address(rax, 0), NativeTstRegMem::instruction_code_memXregl);
3575 __ jcc(Assembler::notEqual, bail);
3576 // Mask out the modrm bits
3577 __ testb(Address(rax, 1), NativeTstRegMem::modrm_mask);
3578 // rax encodes to 0, so if the bits are nonzero it's incorrect
3579 __ jcc(Assembler::notZero, bail);
3580 #endif
3581 // Adjust return pc forward to step over the safepoint poll instruction
3582 __ addptr(rbx, 2);
3583 __ movptr(Address(rbp, wordSize), rbx);
3584 }
3585
3586 __ bind(no_adjust);
3587 // Normal exit, restore registers and exit.
3588 RegisterSaver::restore_live_registers(masm, save_vectors);
3589 __ ret(0);
3590
3591 #ifdef ASSERT
3592 __ bind(bail);
3593 __ stop("Attempting to adjust pc to skip safepoint poll but the return point is not what we expected");
3594 #endif
3595
3596 // Make sure all code is generated
3597 masm->flush();
3598
3599 // Fill-out other meta info
3600 return SafepointBlob::create(&buffer, oop_maps, frame_size_in_words);
3601 }
3602
3603 //
3604 // generate_resolve_blob - call resolution (static/virtual/opt-virtual/ic-miss
3605 //
3606 // Generate a stub that calls into vm to find out the proper destination
3607 // of a java call. All the argument registers are live at this point
3608 // but since this is generic code we don't know what they are and the caller
3609 // must do any gc of the args.
3610 //
3611 RuntimeStub* SharedRuntime::generate_resolve_blob(address destination, const char* name) {
3612 assert (StubRoutines::forward_exception_entry() != NULL, "must be generated before");
3613
3614 // allocate space for the code
3615 ResourceMark rm;
3616
3617 CodeBuffer buffer(name, 1000, 512);
3618 MacroAssembler* masm = new MacroAssembler(&buffer);
3619
3620 int frame_size_in_words;
3621
3622 OopMapSet *oop_maps = new OopMapSet();
3623 OopMap* map = NULL;
3624
3625 int start = __ offset();
3626
3627 map = RegisterSaver::save_live_registers(masm, 0, &frame_size_in_words);
3628
3629 int frame_complete = __ offset();
3630
3631 __ set_last_Java_frame(noreg, noreg, NULL);
3632
3633 __ mov(c_rarg0, r15_thread);
3634
3635 __ call(RuntimeAddress(destination));
3636
3637
3638 // Set an oopmap for the call site.
3639 // We need this not only for callee-saved registers, but also for volatile
3640 // registers that the compiler might be keeping live across a safepoint.
3641
3642 oop_maps->add_gc_map( __ offset() - start, map);
3643
3644 // rax contains the address we are going to jump to assuming no exception got installed
3645
3646 // clear last_Java_sp
3647 __ reset_last_Java_frame(false);
3648 // check for pending exceptions
3649 Label pending;
3650 __ cmpptr(Address(r15_thread, Thread::pending_exception_offset()), (int32_t)NULL_WORD);
3651 __ jcc(Assembler::notEqual, pending);
3652
3653 // get the returned Method*
3654 __ get_vm_result_2(rbx, r15_thread);
3655 __ movptr(Address(rsp, RegisterSaver::rbx_offset_in_bytes()), rbx);
3656
3657 __ movptr(Address(rsp, RegisterSaver::rax_offset_in_bytes()), rax);
3658
3659 RegisterSaver::restore_live_registers(masm);
3660
3661 // We are back the the original state on entry and ready to go.
3662
3663 __ jmp(rax);
3664
3665 // Pending exception after the safepoint
3666
3667 __ bind(pending);
3668
3669 RegisterSaver::restore_live_registers(masm);
3670
3671 // exception pending => remove activation and forward to exception handler
3672
3673 __ movptr(Address(r15_thread, JavaThread::vm_result_offset()), (int)NULL_WORD);
3674
3675 __ movptr(rax, Address(r15_thread, Thread::pending_exception_offset()));
3676 __ jump(RuntimeAddress(StubRoutines::forward_exception_entry()));
3677
3678 // -------------
3679 // make sure all code is generated
3680 masm->flush();
3681
3682 // return the blob
3683 // frame_size_words or bytes??
3684 return RuntimeStub::new_runtime_stub(name, &buffer, frame_complete, frame_size_in_words, oop_maps, true);
3685 }
3686
3687
3688 //------------------------------Montgomery multiplication------------------------
3689 //
3690
3691 #ifndef _WINDOWS
3692
3693 #define ASM_SUBTRACT
3694
3695 #ifdef ASM_SUBTRACT
3696 // Subtract 0:b from carry:a. Return carry.
3697 static unsigned long
3698 sub(unsigned long a[], unsigned long b[], unsigned long carry, long len) {
3699 long i = 0, cnt = len;
3700 unsigned long tmp;
3701 asm volatile("clc; "
3702 "0: ; "
3703 "mov (%[b], %[i], 8), %[tmp]; "
3704 "sbb %[tmp], (%[a], %[i], 8); "
3705 "inc %[i]; dec %[cnt]; "
3706 "jne 0b; "
3707 "mov %[carry], %[tmp]; sbb $0, %[tmp]; "
3708 : [i]"+r"(i), [cnt]"+r"(cnt), [tmp]"=&r"(tmp)
3709 : [a]"r"(a), [b]"r"(b), [carry]"r"(carry)
3710 : "memory");
3711 return tmp;
3712 }
3713 #else // ASM_SUBTRACT
3714 typedef int __attribute__((mode(TI))) int128;
3715
3716 // Subtract 0:b from carry:a. Return carry.
3717 static unsigned long
3718 sub(unsigned long a[], unsigned long b[], unsigned long carry, int len) {
3719 int128 tmp = 0;
3720 int i;
3721 for (i = 0; i < len; i++) {
3722 tmp += a[i];
3723 tmp -= b[i];
3724 a[i] = tmp;
3725 tmp >>= 64;
3726 assert(-1 <= tmp && tmp <= 0, "invariant");
3727 }
3728 return tmp + carry;
3729 }
3730 #endif // ! ASM_SUBTRACT
3731
3732 // Multiply (unsigned) Long A by Long B, accumulating the double-
3733 // length result into the accumulator formed of T0, T1, and T2.
3734 #define MACC(A, B, T0, T1, T2) \
3735 do { \
3736 unsigned long hi, lo; \
3737 __asm__ ("mul %5; add %%rax, %2; adc %%rdx, %3; adc $0, %4" \
3738 : "=&d"(hi), "=a"(lo), "+r"(T0), "+r"(T1), "+g"(T2) \
3739 : "r"(A), "a"(B) : "cc"); \
3740 } while(0)
3741
3742 // As above, but add twice the double-length result into the
3743 // accumulator.
3744 #define MACC2(A, B, T0, T1, T2) \
3745 do { \
3746 unsigned long hi, lo; \
3747 __asm__ ("mul %5; add %%rax, %2; adc %%rdx, %3; adc $0, %4; " \
3748 "add %%rax, %2; adc %%rdx, %3; adc $0, %4" \
3749 : "=&d"(hi), "=a"(lo), "+r"(T0), "+r"(T1), "+g"(T2) \
3750 : "r"(A), "a"(B) : "cc"); \
3751 } while(0)
3752
3753 // Fast Montgomery multiplication. The derivation of the algorithm is
3754 // in A Cryptographic Library for the Motorola DSP56000,
3755 // Dusse and Kaliski, Proc. EUROCRYPT 90, pp. 230-237.
3756
3757 static void __attribute__((noinline))
3758 montgomery_multiply(unsigned long a[], unsigned long b[], unsigned long n[],
3759 unsigned long m[], unsigned long inv, int len) {
3760 unsigned long t0 = 0, t1 = 0, t2 = 0; // Triple-precision accumulator
3761 int i;
3762
3763 assert(inv * n[0] == -1UL, "broken inverse in Montgomery multiply");
3764
3765 for (i = 0; i < len; i++) {
3766 int j;
3767 for (j = 0; j < i; j++) {
3768 MACC(a[j], b[i-j], t0, t1, t2);
3769 MACC(m[j], n[i-j], t0, t1, t2);
3770 }
3771 MACC(a[i], b[0], t0, t1, t2);
3772 m[i] = t0 * inv;
3773 MACC(m[i], n[0], t0, t1, t2);
3774
3775 assert(t0 == 0, "broken Montgomery multiply");
3776
3777 t0 = t1; t1 = t2; t2 = 0;
3778 }
3779
3780 for (i = len; i < 2*len; i++) {
3781 int j;
3782 for (j = i-len+1; j < len; j++) {
3783 MACC(a[j], b[i-j], t0, t1, t2);
3784 MACC(m[j], n[i-j], t0, t1, t2);
3785 }
3786 m[i-len] = t0;
3787 t0 = t1; t1 = t2; t2 = 0;
3788 }
3789
3790 while (t0)
3791 t0 = sub(m, n, t0, len);
3792 }
3793
3794 // Fast Montgomery squaring. This uses asymptotically 25% fewer
3795 // multiplies so it should be up to 25% faster than Montgomery
3796 // multiplication. However, its loop control is more complex and it
3797 // may actually run slower on some machines.
3798
3799 static void __attribute__((noinline))
3800 montgomery_square(unsigned long a[], unsigned long n[],
3801 unsigned long m[], unsigned long inv, int len) {
3802 unsigned long t0 = 0, t1 = 0, t2 = 0; // Triple-precision accumulator
3803 int i;
3804
3805 assert(inv * n[0] == -1UL, "broken inverse in Montgomery multiply");
3806
3807 for (i = 0; i < len; i++) {
3808 int j;
3809 int end = (i+1)/2;
3810 for (j = 0; j < end; j++) {
3811 MACC2(a[j], a[i-j], t0, t1, t2);
3812 MACC(m[j], n[i-j], t0, t1, t2);
3813 }
3814 if ((i & 1) == 0) {
3815 MACC(a[j], a[j], t0, t1, t2);
3816 }
3817 for (; j < i; j++) {
3818 MACC(m[j], n[i-j], t0, t1, t2);
3819 }
3820 m[i] = t0 * inv;
3821 MACC(m[i], n[0], t0, t1, t2);
3822
3823 assert(t0 == 0, "broken Montgomery square");
3824
3825 t0 = t1; t1 = t2; t2 = 0;
3826 }
3827
3828 for (i = len; i < 2*len; i++) {
3829 int start = i-len+1;
3830 int end = start + (len - start)/2;
3831 int j;
3832 for (j = start; j < end; j++) {
3833 MACC2(a[j], a[i-j], t0, t1, t2);
3834 MACC(m[j], n[i-j], t0, t1, t2);
3835 }
3836 if ((i & 1) == 0) {
3837 MACC(a[j], a[j], t0, t1, t2);
3838 }
3839 for (; j < len; j++) {
3840 MACC(m[j], n[i-j], t0, t1, t2);
3841 }
3842 m[i-len] = t0;
3843 t0 = t1; t1 = t2; t2 = 0;
3844 }
3845
3846 while (t0)
3847 t0 = sub(m, n, t0, len);
3848 }
3849
3850 // Swap words in a longword.
3851 static unsigned long swap(unsigned long x) {
3852 return (x << 32) | (x >> 32);
3853 }
3854
3855 // Copy len longwords from s to d, word-swapping as we go. The
3856 // destination array is reversed.
3857 static void reverse_words(unsigned long *s, unsigned long *d, int len) {
3858 d += len;
3859 while(len-- > 0) {
3860 d--;
3861 *d = swap(*s);
3862 s++;
3863 }
3864 }
3865
3866 // The threshold at which squaring is advantageous was determined
3867 // experimentally on an i7-3930K (Ivy Bridge) CPU @ 3.5GHz.
3868 #define MONTGOMERY_SQUARING_THRESHOLD 64
3869
3870 void SharedRuntime::montgomery_multiply(jint *a_ints, jint *b_ints, jint *n_ints,
3871 jint len, jlong inv,
3872 jint *m_ints) {
3873 assert(len % 2 == 0, "array length in montgomery_multiply must be even");
3874 int longwords = len/2;
3875
3876 // Make very sure we don't use so much space that the stack might
3877 // overflow. 512 jints corresponds to an 16384-bit integer and
3878 // will use here a total of 8k bytes of stack space.
3879 int total_allocation = longwords * sizeof (unsigned long) * 4;
3880 guarantee(total_allocation <= 8192, "must be");
3881 unsigned long *scratch = (unsigned long *)alloca(total_allocation);
3882
3883 // Local scratch arrays
3884 unsigned long
3885 *a = scratch + 0 * longwords,
3886 *b = scratch + 1 * longwords,
3887 *n = scratch + 2 * longwords,
3888 *m = scratch + 3 * longwords;
3889
3890 reverse_words((unsigned long *)a_ints, a, longwords);
3891 reverse_words((unsigned long *)b_ints, b, longwords);
3892 reverse_words((unsigned long *)n_ints, n, longwords);
3893
3894 ::montgomery_multiply(a, b, n, m, (unsigned long)inv, longwords);
3895
3896 reverse_words(m, (unsigned long *)m_ints, longwords);
3897 }
3898
3899 void SharedRuntime::montgomery_square(jint *a_ints, jint *n_ints,
3900 jint len, jlong inv,
3901 jint *m_ints) {
3902 assert(len % 2 == 0, "array length in montgomery_square must be even");
3903 int longwords = len/2;
3904
3905 // Make very sure we don't use so much space that the stack might
3906 // overflow. 512 jints corresponds to an 16384-bit integer and
3907 // will use here a total of 6k bytes of stack space.
3908 int total_allocation = longwords * sizeof (unsigned long) * 3;
3909 guarantee(total_allocation <= 8192, "must be");
3910 unsigned long *scratch = (unsigned long *)alloca(total_allocation);
3911
3912 // Local scratch arrays
3913 unsigned long
3914 *a = scratch + 0 * longwords,
3915 *n = scratch + 1 * longwords,
3916 *m = scratch + 2 * longwords;
3917
3918 reverse_words((unsigned long *)a_ints, a, longwords);
3919 reverse_words((unsigned long *)n_ints, n, longwords);
3920
3921 if (len >= MONTGOMERY_SQUARING_THRESHOLD) {
3922 ::montgomery_square(a, n, m, (unsigned long)inv, longwords);
3923 } else {
3924 ::montgomery_multiply(a, a, n, m, (unsigned long)inv, longwords);
3925 }
3926
3927 reverse_words(m, (unsigned long *)m_ints, longwords);
3928 }
3929
3930 #endif // WINDOWS
3931
3932 #ifdef COMPILER2
3933 // This is here instead of runtime_x86_64.cpp because it uses SimpleRuntimeFrame
3934 //
3935 //------------------------------generate_exception_blob---------------------------
3936 // creates exception blob at the end
3937 // Using exception blob, this code is jumped from a compiled method.
3938 // (see emit_exception_handler in x86_64.ad file)
3939 //
3940 // Given an exception pc at a call we call into the runtime for the
3941 // handler in this method. This handler might merely restore state
3942 // (i.e. callee save registers) unwind the frame and jump to the
3943 // exception handler for the nmethod if there is no Java level handler
3944 // for the nmethod.
3945 //
3946 // This code is entered with a jmp.
3947 //
3948 // Arguments:
3949 // rax: exception oop
3950 // rdx: exception pc
3951 //
3952 // Results:
3953 // rax: exception oop
3954 // rdx: exception pc in caller or ???
3955 // destination: exception handler of caller
3956 //
3957 // Note: the exception pc MUST be at a call (precise debug information)
3958 // Registers rax, rdx, rcx, rsi, rdi, r8-r11 are not callee saved.
3959 //
3960
3961 void OptoRuntime::generate_exception_blob() {
3962 assert(!OptoRuntime::is_callee_saved_register(RDX_num), "");
3963 assert(!OptoRuntime::is_callee_saved_register(RAX_num), "");
3964 assert(!OptoRuntime::is_callee_saved_register(RCX_num), "");
3965
3966 assert(SimpleRuntimeFrame::framesize % 4 == 0, "sp not 16-byte aligned");
3967
3968 // Allocate space for the code
3969 ResourceMark rm;
3970 // Setup code generation tools
3971 CodeBuffer buffer("exception_blob", 2048, 1024);
3972 MacroAssembler* masm = new MacroAssembler(&buffer);
3973
3974
3975 address start = __ pc();
3976
3977 // Exception pc is 'return address' for stack walker
3978 __ push(rdx);
3979 __ subptr(rsp, SimpleRuntimeFrame::return_off << LogBytesPerInt); // Prolog
3980
3981 // Save callee-saved registers. See x86_64.ad.
3982
3983 // rbp is an implicitly saved callee saved register (i.e., the calling
3984 // convention will save/restore it in the prolog/epilog). Other than that
3985 // there are no callee save registers now that adapter frames are gone.
3986
3987 __ movptr(Address(rsp, SimpleRuntimeFrame::rbp_off << LogBytesPerInt), rbp);
3988
3989 // Store exception in Thread object. We cannot pass any arguments to the
3990 // handle_exception call, since we do not want to make any assumption
3991 // about the size of the frame where the exception happened in.
3992 // c_rarg0 is either rdi (Linux) or rcx (Windows).
3993 __ movptr(Address(r15_thread, JavaThread::exception_oop_offset()),rax);
3994 __ movptr(Address(r15_thread, JavaThread::exception_pc_offset()), rdx);
3995
3996 // This call does all the hard work. It checks if an exception handler
3997 // exists in the method.
3998 // If so, it returns the handler address.
3999 // If not, it prepares for stack-unwinding, restoring the callee-save
4000 // registers of the frame being removed.
4001 //
4002 // address OptoRuntime::handle_exception_C(JavaThread* thread)
4003
4004 // At a method handle call, the stack may not be properly aligned
4005 // when returning with an exception.
4006 address the_pc = __ pc();
4007 __ set_last_Java_frame(noreg, noreg, the_pc);
4008 __ mov(c_rarg0, r15_thread);
4009 __ andptr(rsp, -(StackAlignmentInBytes)); // Align stack
4010 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, OptoRuntime::handle_exception_C)));
4011
4012 // Set an oopmap for the call site. This oopmap will only be used if we
4013 // are unwinding the stack. Hence, all locations will be dead.
4014 // Callee-saved registers will be the same as the frame above (i.e.,
4015 // handle_exception_stub), since they were restored when we got the
4016 // exception.
4017
4018 OopMapSet* oop_maps = new OopMapSet();
4019
4020 oop_maps->add_gc_map(the_pc - start, new OopMap(SimpleRuntimeFrame::framesize, 0));
4021
4022 __ reset_last_Java_frame(false);
4023
4024 // Restore callee-saved registers
4025
4026 // rbp is an implicitly saved callee-saved register (i.e., the calling
4027 // convention will save restore it in prolog/epilog) Other than that
4028 // there are no callee save registers now that adapter frames are gone.
4029
4030 __ movptr(rbp, Address(rsp, SimpleRuntimeFrame::rbp_off << LogBytesPerInt));
4031
4032 __ addptr(rsp, SimpleRuntimeFrame::return_off << LogBytesPerInt); // Epilog
4033 __ pop(rdx); // No need for exception pc anymore
4034
4035 // rax: exception handler
4036
4037 // We have a handler in rax (could be deopt blob).
4038 __ mov(r8, rax);
4039
4040 // Get the exception oop
4041 __ movptr(rax, Address(r15_thread, JavaThread::exception_oop_offset()));
4042 // Get the exception pc in case we are deoptimized
4043 __ movptr(rdx, Address(r15_thread, JavaThread::exception_pc_offset()));
4044 #ifdef ASSERT
4045 __ movptr(Address(r15_thread, JavaThread::exception_handler_pc_offset()), (int)NULL_WORD);
4046 __ movptr(Address(r15_thread, JavaThread::exception_pc_offset()), (int)NULL_WORD);
4047 #endif
4048 // Clear the exception oop so GC no longer processes it as a root.
4049 __ movptr(Address(r15_thread, JavaThread::exception_oop_offset()), (int)NULL_WORD);
4050
4051 // rax: exception oop
4052 // r8: exception handler
4053 // rdx: exception pc
4054 // Jump to handler
4055
4056 __ jmp(r8);
4057
4058 // Make sure all code is generated
4059 masm->flush();
4060
4061 // Set exception blob
4062 _exception_blob = ExceptionBlob::create(&buffer, oop_maps, SimpleRuntimeFrame::framesize >> 1);
4063 }
4064 #endif // COMPILER2
--- EOF ---