1 /* 2 * Copyright (c) 2000, 2018, Oracle and/or its affiliates. All rights reserved. 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 4 * 5 * This code is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License version 2 only, as 7 * published by the Free Software Foundation. 8 * 9 * This code is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 12 * version 2 for more details (a copy is included in the LICENSE file that 13 * accompanied this code). 14 * 15 * You should have received a copy of the GNU General Public License version 16 * 2 along with this work; if not, write to the Free Software Foundation, 17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 18 * 19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA 20 * or visit www.oracle.com if you need additional information or have any 21 * questions. 22 * 23 */ 24 25 #include "precompiled.hpp" 26 #include "asm/macroAssembler.hpp" 27 #include "asm/macroAssembler.inline.hpp" 28 #include "c1/c1_Compilation.hpp" 29 #include "c1/c1_LIRAssembler.hpp" 30 #include "c1/c1_MacroAssembler.hpp" 31 #include "c1/c1_Runtime1.hpp" 32 #include "c1/c1_ValueStack.hpp" 33 #include "ci/ciArrayKlass.hpp" 34 #include "ci/ciInstance.hpp" 35 #include "gc/shared/barrierSet.hpp" 36 #include "gc/shared/cardTableBarrierSet.hpp" 37 #include "gc/shared/collectedHeap.hpp" 38 #include "nativeInst_x86.hpp" 39 #include "oops/objArrayKlass.hpp" 40 #include "runtime/frame.inline.hpp" 41 #include "runtime/safepointMechanism.hpp" 42 #include "runtime/sharedRuntime.hpp" 43 #include "vmreg_x86.inline.hpp" 44 45 46 // These masks are used to provide 128-bit aligned bitmasks to the XMM 47 // instructions, to allow sign-masking or sign-bit flipping. They allow 48 // fast versions of NegF/NegD and AbsF/AbsD. 49 50 // Note: 'double' and 'long long' have 32-bits alignment on x86. 51 static jlong* double_quadword(jlong *adr, jlong lo, jlong hi) { 52 // Use the expression (adr)&(~0xF) to provide 128-bits aligned address 53 // of 128-bits operands for SSE instructions. 54 jlong *operand = (jlong*)(((intptr_t)adr) & ((intptr_t)(~0xF))); 55 // Store the value to a 128-bits operand. 56 operand[0] = lo; 57 operand[1] = hi; 58 return operand; 59 } 60 61 // Buffer for 128-bits masks used by SSE instructions. 62 static jlong fp_signmask_pool[(4+1)*2]; // 4*128bits(data) + 128bits(alignment) 63 64 // Static initialization during VM startup. 65 static jlong *float_signmask_pool = double_quadword(&fp_signmask_pool[1*2], CONST64(0x7FFFFFFF7FFFFFFF), CONST64(0x7FFFFFFF7FFFFFFF)); 66 static jlong *double_signmask_pool = double_quadword(&fp_signmask_pool[2*2], CONST64(0x7FFFFFFFFFFFFFFF), CONST64(0x7FFFFFFFFFFFFFFF)); 67 static jlong *float_signflip_pool = double_quadword(&fp_signmask_pool[3*2], (jlong)UCONST64(0x8000000080000000), (jlong)UCONST64(0x8000000080000000)); 68 static jlong *double_signflip_pool = double_quadword(&fp_signmask_pool[4*2], (jlong)UCONST64(0x8000000000000000), (jlong)UCONST64(0x8000000000000000)); 69 70 71 NEEDS_CLEANUP // remove this definitions ? 72 const Register IC_Klass = rax; // where the IC klass is cached 73 const Register SYNC_header = rax; // synchronization header 74 const Register SHIFT_count = rcx; // where count for shift operations must be 75 76 #define __ _masm-> 77 78 79 static void select_different_registers(Register preserve, 80 Register extra, 81 Register &tmp1, 82 Register &tmp2) { 83 if (tmp1 == preserve) { 84 assert_different_registers(tmp1, tmp2, extra); 85 tmp1 = extra; 86 } else if (tmp2 == preserve) { 87 assert_different_registers(tmp1, tmp2, extra); 88 tmp2 = extra; 89 } 90 assert_different_registers(preserve, tmp1, tmp2); 91 } 92 93 94 95 static void select_different_registers(Register preserve, 96 Register extra, 97 Register &tmp1, 98 Register &tmp2, 99 Register &tmp3) { 100 if (tmp1 == preserve) { 101 assert_different_registers(tmp1, tmp2, tmp3, extra); 102 tmp1 = extra; 103 } else if (tmp2 == preserve) { 104 assert_different_registers(tmp1, tmp2, tmp3, extra); 105 tmp2 = extra; 106 } else if (tmp3 == preserve) { 107 assert_different_registers(tmp1, tmp2, tmp3, extra); 108 tmp3 = extra; 109 } 110 assert_different_registers(preserve, tmp1, tmp2, tmp3); 111 } 112 113 114 115 bool LIR_Assembler::is_small_constant(LIR_Opr opr) { 116 if (opr->is_constant()) { 117 LIR_Const* constant = opr->as_constant_ptr(); 118 switch (constant->type()) { 119 case T_INT: { 120 return true; 121 } 122 123 default: 124 return false; 125 } 126 } 127 return false; 128 } 129 130 131 LIR_Opr LIR_Assembler::receiverOpr() { 132 return FrameMap::receiver_opr; 133 } 134 135 LIR_Opr LIR_Assembler::osrBufferPointer() { 136 return FrameMap::as_pointer_opr(receiverOpr()->as_register()); 137 } 138 139 //--------------fpu register translations----------------------- 140 141 142 address LIR_Assembler::float_constant(float f) { 143 address const_addr = __ float_constant(f); 144 if (const_addr == NULL) { 145 bailout("const section overflow"); 146 return __ code()->consts()->start(); 147 } else { 148 return const_addr; 149 } 150 } 151 152 153 address LIR_Assembler::double_constant(double d) { 154 address const_addr = __ double_constant(d); 155 if (const_addr == NULL) { 156 bailout("const section overflow"); 157 return __ code()->consts()->start(); 158 } else { 159 return const_addr; 160 } 161 } 162 163 164 void LIR_Assembler::set_24bit_FPU() { 165 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24())); 166 } 167 168 void LIR_Assembler::reset_FPU() { 169 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std())); 170 } 171 172 void LIR_Assembler::fpop() { 173 __ fpop(); 174 } 175 176 void LIR_Assembler::fxch(int i) { 177 __ fxch(i); 178 } 179 180 void LIR_Assembler::fld(int i) { 181 __ fld_s(i); 182 } 183 184 void LIR_Assembler::ffree(int i) { 185 __ ffree(i); 186 } 187 188 void LIR_Assembler::breakpoint() { 189 __ int3(); 190 } 191 192 void LIR_Assembler::push(LIR_Opr opr) { 193 if (opr->is_single_cpu()) { 194 __ push_reg(opr->as_register()); 195 } else if (opr->is_double_cpu()) { 196 NOT_LP64(__ push_reg(opr->as_register_hi())); 197 __ push_reg(opr->as_register_lo()); 198 } else if (opr->is_stack()) { 199 __ push_addr(frame_map()->address_for_slot(opr->single_stack_ix())); 200 } else if (opr->is_constant()) { 201 LIR_Const* const_opr = opr->as_constant_ptr(); 202 if (const_opr->type() == T_OBJECT || const_opr->type() == T_VALUETYPE) { 203 __ push_oop(const_opr->as_jobject()); 204 } else if (const_opr->type() == T_INT) { 205 __ push_jint(const_opr->as_jint()); 206 } else { 207 ShouldNotReachHere(); 208 } 209 210 } else { 211 ShouldNotReachHere(); 212 } 213 } 214 215 void LIR_Assembler::pop(LIR_Opr opr) { 216 if (opr->is_single_cpu()) { 217 __ pop_reg(opr->as_register()); 218 } else { 219 ShouldNotReachHere(); 220 } 221 } 222 223 bool LIR_Assembler::is_literal_address(LIR_Address* addr) { 224 return addr->base()->is_illegal() && addr->index()->is_illegal(); 225 } 226 227 //------------------------------------------- 228 229 Address LIR_Assembler::as_Address(LIR_Address* addr) { 230 return as_Address(addr, rscratch1); 231 } 232 233 Address LIR_Assembler::as_Address(LIR_Address* addr, Register tmp) { 234 if (addr->base()->is_illegal()) { 235 assert(addr->index()->is_illegal(), "must be illegal too"); 236 AddressLiteral laddr((address)addr->disp(), relocInfo::none); 237 if (! __ reachable(laddr)) { 238 __ movptr(tmp, laddr.addr()); 239 Address res(tmp, 0); 240 return res; 241 } else { 242 return __ as_Address(laddr); 243 } 244 } 245 246 Register base = addr->base()->as_pointer_register(); 247 248 if (addr->index()->is_illegal()) { 249 return Address( base, addr->disp()); 250 } else if (addr->index()->is_cpu_register()) { 251 Register index = addr->index()->as_pointer_register(); 252 return Address(base, index, (Address::ScaleFactor) addr->scale(), addr->disp()); 253 } else if (addr->index()->is_constant()) { 254 intptr_t addr_offset = (addr->index()->as_constant_ptr()->as_jint() << addr->scale()) + addr->disp(); 255 assert(Assembler::is_simm32(addr_offset), "must be"); 256 257 return Address(base, addr_offset); 258 } else { 259 Unimplemented(); 260 return Address(); 261 } 262 } 263 264 265 Address LIR_Assembler::as_Address_hi(LIR_Address* addr) { 266 Address base = as_Address(addr); 267 return Address(base._base, base._index, base._scale, base._disp + BytesPerWord); 268 } 269 270 271 Address LIR_Assembler::as_Address_lo(LIR_Address* addr) { 272 return as_Address(addr); 273 } 274 275 276 void LIR_Assembler::osr_entry() { 277 offsets()->set_value(CodeOffsets::OSR_Entry, code_offset()); 278 BlockBegin* osr_entry = compilation()->hir()->osr_entry(); 279 ValueStack* entry_state = osr_entry->state(); 280 int number_of_locks = entry_state->locks_size(); 281 282 // we jump here if osr happens with the interpreter 283 // state set up to continue at the beginning of the 284 // loop that triggered osr - in particular, we have 285 // the following registers setup: 286 // 287 // rcx: osr buffer 288 // 289 290 // build frame 291 ciMethod* m = compilation()->method(); 292 __ build_frame(initial_frame_size_in_bytes(), bang_size_in_bytes()); 293 294 // OSR buffer is 295 // 296 // locals[nlocals-1..0] 297 // monitors[0..number_of_locks] 298 // 299 // locals is a direct copy of the interpreter frame so in the osr buffer 300 // so first slot in the local array is the last local from the interpreter 301 // and last slot is local[0] (receiver) from the interpreter 302 // 303 // Similarly with locks. The first lock slot in the osr buffer is the nth lock 304 // from the interpreter frame, the nth lock slot in the osr buffer is 0th lock 305 // in the interpreter frame (the method lock if a sync method) 306 307 // Initialize monitors in the compiled activation. 308 // rcx: pointer to osr buffer 309 // 310 // All other registers are dead at this point and the locals will be 311 // copied into place by code emitted in the IR. 312 313 Register OSR_buf = osrBufferPointer()->as_pointer_register(); 314 { assert(frame::interpreter_frame_monitor_size() == BasicObjectLock::size(), "adjust code below"); 315 int monitor_offset = BytesPerWord * method()->max_locals() + 316 (BasicObjectLock::size() * BytesPerWord) * (number_of_locks - 1); 317 // SharedRuntime::OSR_migration_begin() packs BasicObjectLocks in 318 // the OSR buffer using 2 word entries: first the lock and then 319 // the oop. 320 for (int i = 0; i < number_of_locks; i++) { 321 int slot_offset = monitor_offset - ((i * 2) * BytesPerWord); 322 #ifdef ASSERT 323 // verify the interpreter's monitor has a non-null object 324 { 325 Label L; 326 __ cmpptr(Address(OSR_buf, slot_offset + 1*BytesPerWord), (int32_t)NULL_WORD); 327 __ jcc(Assembler::notZero, L); 328 __ stop("locked object is NULL"); 329 __ bind(L); 330 } 331 #endif 332 __ movptr(rbx, Address(OSR_buf, slot_offset + 0)); 333 __ movptr(frame_map()->address_for_monitor_lock(i), rbx); 334 __ movptr(rbx, Address(OSR_buf, slot_offset + 1*BytesPerWord)); 335 __ movptr(frame_map()->address_for_monitor_object(i), rbx); 336 } 337 } 338 } 339 340 341 // inline cache check; done before the frame is built. 342 int LIR_Assembler::check_icache() { 343 Register receiver = FrameMap::receiver_opr->as_register(); 344 Register ic_klass = IC_Klass; 345 const int ic_cmp_size = LP64_ONLY(10) NOT_LP64(9); 346 const bool do_post_padding = VerifyOops || UseCompressedClassPointers; 347 if (!do_post_padding) { 348 // insert some nops so that the verified entry point is aligned on CodeEntryAlignment 349 __ align(CodeEntryAlignment, __ offset() + ic_cmp_size); 350 } 351 int offset = __ offset(); 352 __ inline_cache_check(receiver, IC_Klass); 353 assert(__ offset() % CodeEntryAlignment == 0 || do_post_padding, "alignment must be correct"); 354 if (do_post_padding) { 355 // force alignment after the cache check. 356 // It's been verified to be aligned if !VerifyOops 357 __ align(CodeEntryAlignment); 358 } 359 return offset; 360 } 361 362 363 void LIR_Assembler::jobject2reg_with_patching(Register reg, CodeEmitInfo* info) { 364 jobject o = NULL; 365 PatchingStub* patch = new PatchingStub(_masm, patching_id(info)); 366 __ movoop(reg, o); 367 patching_epilog(patch, lir_patch_normal, reg, info); 368 } 369 370 void LIR_Assembler::klass2reg_with_patching(Register reg, CodeEmitInfo* info) { 371 Metadata* o = NULL; 372 PatchingStub* patch = new PatchingStub(_masm, PatchingStub::load_klass_id); 373 __ mov_metadata(reg, o); 374 patching_epilog(patch, lir_patch_normal, reg, info); 375 } 376 377 // This specifies the rsp decrement needed to build the frame 378 int LIR_Assembler::initial_frame_size_in_bytes() const { 379 // if rounding, must let FrameMap know! 380 381 // The frame_map records size in slots (32bit word) 382 383 // subtract two words to account for return address and link 384 return (frame_map()->framesize() - (2*VMRegImpl::slots_per_word)) * VMRegImpl::stack_slot_size; 385 } 386 387 388 int LIR_Assembler::emit_exception_handler() { 389 // if the last instruction is a call (typically to do a throw which 390 // is coming at the end after block reordering) the return address 391 // must still point into the code area in order to avoid assertion 392 // failures when searching for the corresponding bci => add a nop 393 // (was bug 5/14/1999 - gri) 394 __ nop(); 395 396 // generate code for exception handler 397 address handler_base = __ start_a_stub(exception_handler_size()); 398 if (handler_base == NULL) { 399 // not enough space left for the handler 400 bailout("exception handler overflow"); 401 return -1; 402 } 403 404 int offset = code_offset(); 405 406 // the exception oop and pc are in rax, and rdx 407 // no other registers need to be preserved, so invalidate them 408 __ invalidate_registers(false, true, true, false, true, true); 409 410 // check that there is really an exception 411 __ verify_not_null_oop(rax); 412 413 // search an exception handler (rax: exception oop, rdx: throwing pc) 414 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::handle_exception_from_callee_id))); 415 __ should_not_reach_here(); 416 guarantee(code_offset() - offset <= exception_handler_size(), "overflow"); 417 __ end_a_stub(); 418 419 return offset; 420 } 421 422 423 // Emit the code to remove the frame from the stack in the exception 424 // unwind path. 425 int LIR_Assembler::emit_unwind_handler() { 426 #ifndef PRODUCT 427 if (CommentedAssembly) { 428 _masm->block_comment("Unwind handler"); 429 } 430 #endif 431 432 int offset = code_offset(); 433 434 // Fetch the exception from TLS and clear out exception related thread state 435 Register thread = NOT_LP64(rsi) LP64_ONLY(r15_thread); 436 NOT_LP64(__ get_thread(rsi)); 437 __ movptr(rax, Address(thread, JavaThread::exception_oop_offset())); 438 __ movptr(Address(thread, JavaThread::exception_oop_offset()), (intptr_t)NULL_WORD); 439 __ movptr(Address(thread, JavaThread::exception_pc_offset()), (intptr_t)NULL_WORD); 440 441 __ bind(_unwind_handler_entry); 442 __ verify_not_null_oop(rax); 443 if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) { 444 __ mov(rbx, rax); // Preserve the exception (rbx is always callee-saved) 445 } 446 447 // Preform needed unlocking 448 MonitorExitStub* stub = NULL; 449 if (method()->is_synchronized()) { 450 monitor_address(0, FrameMap::rax_opr); 451 stub = new MonitorExitStub(FrameMap::rax_opr, true, 0); 452 __ unlock_object(rdi, rsi, rax, *stub->entry()); 453 __ bind(*stub->continuation()); 454 } 455 456 if (compilation()->env()->dtrace_method_probes()) { 457 #ifdef _LP64 458 __ mov(rdi, r15_thread); 459 __ mov_metadata(rsi, method()->constant_encoding()); 460 #else 461 __ get_thread(rax); 462 __ movptr(Address(rsp, 0), rax); 463 __ mov_metadata(Address(rsp, sizeof(void*)), method()->constant_encoding()); 464 #endif 465 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, SharedRuntime::dtrace_method_exit))); 466 } 467 468 if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) { 469 __ mov(rax, rbx); // Restore the exception 470 } 471 472 // remove the activation and dispatch to the unwind handler 473 __ remove_frame(initial_frame_size_in_bytes()); 474 __ jump(RuntimeAddress(Runtime1::entry_for(Runtime1::unwind_exception_id))); 475 476 // Emit the slow path assembly 477 if (stub != NULL) { 478 stub->emit_code(this); 479 } 480 481 return offset; 482 } 483 484 485 int LIR_Assembler::emit_deopt_handler() { 486 // if the last instruction is a call (typically to do a throw which 487 // is coming at the end after block reordering) the return address 488 // must still point into the code area in order to avoid assertion 489 // failures when searching for the corresponding bci => add a nop 490 // (was bug 5/14/1999 - gri) 491 __ nop(); 492 493 // generate code for exception handler 494 address handler_base = __ start_a_stub(deopt_handler_size()); 495 if (handler_base == NULL) { 496 // not enough space left for the handler 497 bailout("deopt handler overflow"); 498 return -1; 499 } 500 501 int offset = code_offset(); 502 InternalAddress here(__ pc()); 503 504 __ pushptr(here.addr()); 505 __ jump(RuntimeAddress(SharedRuntime::deopt_blob()->unpack())); 506 guarantee(code_offset() - offset <= deopt_handler_size(), "overflow"); 507 __ end_a_stub(); 508 509 return offset; 510 } 511 512 513 void LIR_Assembler::return_op(LIR_Opr result) { 514 assert(result->is_illegal() || !result->is_single_cpu() || result->as_register() == rax, "word returns are in rax,"); 515 if (!result->is_illegal() && result->is_float_kind() && !result->is_xmm_register()) { 516 assert(result->fpu() == 0, "result must already be on TOS"); 517 } 518 519 // Pop the stack before the safepoint code 520 __ remove_frame(initial_frame_size_in_bytes()); 521 522 if (StackReservedPages > 0 && compilation()->has_reserved_stack_access()) { 523 __ reserved_stack_check(); 524 } 525 526 bool result_is_oop = result->is_valid() ? result->is_oop() : false; 527 528 // Note: we do not need to round double result; float result has the right precision 529 // the poll sets the condition code, but no data registers 530 531 if (SafepointMechanism::uses_thread_local_poll()) { 532 #ifdef _LP64 533 const Register poll_addr = rscratch1; 534 __ movptr(poll_addr, Address(r15_thread, Thread::polling_page_offset())); 535 #else 536 const Register poll_addr = rbx; 537 assert(FrameMap::is_caller_save_register(poll_addr), "will overwrite"); 538 __ get_thread(poll_addr); 539 __ movptr(poll_addr, Address(poll_addr, Thread::polling_page_offset())); 540 #endif 541 __ relocate(relocInfo::poll_return_type); 542 __ testl(rax, Address(poll_addr, 0)); 543 } else { 544 AddressLiteral polling_page(os::get_polling_page(), relocInfo::poll_return_type); 545 546 if (Assembler::is_polling_page_far()) { 547 __ lea(rscratch1, polling_page); 548 __ relocate(relocInfo::poll_return_type); 549 __ testl(rax, Address(rscratch1, 0)); 550 } else { 551 __ testl(rax, polling_page); 552 } 553 } 554 __ ret(0); 555 } 556 557 558 int LIR_Assembler::safepoint_poll(LIR_Opr tmp, CodeEmitInfo* info) { 559 guarantee(info != NULL, "Shouldn't be NULL"); 560 int offset = __ offset(); 561 if (SafepointMechanism::uses_thread_local_poll()) { 562 #ifdef _LP64 563 const Register poll_addr = rscratch1; 564 __ movptr(poll_addr, Address(r15_thread, Thread::polling_page_offset())); 565 #else 566 assert(tmp->is_cpu_register(), "needed"); 567 const Register poll_addr = tmp->as_register(); 568 __ get_thread(poll_addr); 569 __ movptr(poll_addr, Address(poll_addr, in_bytes(Thread::polling_page_offset()))); 570 #endif 571 add_debug_info_for_branch(info); 572 __ relocate(relocInfo::poll_type); 573 address pre_pc = __ pc(); 574 __ testl(rax, Address(poll_addr, 0)); 575 address post_pc = __ pc(); 576 guarantee(pointer_delta(post_pc, pre_pc, 1) == 2 LP64_ONLY(+1), "must be exact length"); 577 } else { 578 AddressLiteral polling_page(os::get_polling_page(), relocInfo::poll_type); 579 if (Assembler::is_polling_page_far()) { 580 __ lea(rscratch1, polling_page); 581 offset = __ offset(); 582 add_debug_info_for_branch(info); 583 __ relocate(relocInfo::poll_type); 584 __ testl(rax, Address(rscratch1, 0)); 585 } else { 586 add_debug_info_for_branch(info); 587 __ testl(rax, polling_page); 588 } 589 } 590 return offset; 591 } 592 593 594 void LIR_Assembler::move_regs(Register from_reg, Register to_reg) { 595 if (from_reg != to_reg) __ mov(to_reg, from_reg); 596 } 597 598 void LIR_Assembler::swap_reg(Register a, Register b) { 599 __ xchgptr(a, b); 600 } 601 602 603 void LIR_Assembler::const2reg(LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) { 604 assert(src->is_constant(), "should not call otherwise"); 605 assert(dest->is_register(), "should not call otherwise"); 606 LIR_Const* c = src->as_constant_ptr(); 607 608 switch (c->type()) { 609 case T_INT: { 610 assert(patch_code == lir_patch_none, "no patching handled here"); 611 __ movl(dest->as_register(), c->as_jint()); 612 break; 613 } 614 615 case T_ADDRESS: { 616 assert(patch_code == lir_patch_none, "no patching handled here"); 617 __ movptr(dest->as_register(), c->as_jint()); 618 break; 619 } 620 621 case T_LONG: { 622 assert(patch_code == lir_patch_none, "no patching handled here"); 623 #ifdef _LP64 624 __ movptr(dest->as_register_lo(), (intptr_t)c->as_jlong()); 625 #else 626 __ movptr(dest->as_register_lo(), c->as_jint_lo()); 627 __ movptr(dest->as_register_hi(), c->as_jint_hi()); 628 #endif // _LP64 629 break; 630 } 631 632 case T_VALUETYPE: // Fall through 633 case T_OBJECT: { 634 if (patch_code != lir_patch_none) { 635 jobject2reg_with_patching(dest->as_register(), info); 636 } else { 637 __ movoop(dest->as_register(), c->as_jobject()); 638 } 639 break; 640 } 641 642 case T_METADATA: { 643 if (patch_code != lir_patch_none) { 644 klass2reg_with_patching(dest->as_register(), info); 645 } else { 646 __ mov_metadata(dest->as_register(), c->as_metadata()); 647 } 648 break; 649 } 650 651 case T_FLOAT: { 652 if (dest->is_single_xmm()) { 653 if (LP64_ONLY(UseAVX <= 2 &&) c->is_zero_float()) { 654 __ xorps(dest->as_xmm_float_reg(), dest->as_xmm_float_reg()); 655 } else { 656 __ movflt(dest->as_xmm_float_reg(), 657 InternalAddress(float_constant(c->as_jfloat()))); 658 } 659 } else { 660 assert(dest->is_single_fpu(), "must be"); 661 assert(dest->fpu_regnr() == 0, "dest must be TOS"); 662 if (c->is_zero_float()) { 663 __ fldz(); 664 } else if (c->is_one_float()) { 665 __ fld1(); 666 } else { 667 __ fld_s (InternalAddress(float_constant(c->as_jfloat()))); 668 } 669 } 670 break; 671 } 672 673 case T_DOUBLE: { 674 if (dest->is_double_xmm()) { 675 if (LP64_ONLY(UseAVX <= 2 &&) c->is_zero_double()) { 676 __ xorpd(dest->as_xmm_double_reg(), dest->as_xmm_double_reg()); 677 } else { 678 __ movdbl(dest->as_xmm_double_reg(), 679 InternalAddress(double_constant(c->as_jdouble()))); 680 } 681 } else { 682 assert(dest->is_double_fpu(), "must be"); 683 assert(dest->fpu_regnrLo() == 0, "dest must be TOS"); 684 if (c->is_zero_double()) { 685 __ fldz(); 686 } else if (c->is_one_double()) { 687 __ fld1(); 688 } else { 689 __ fld_d (InternalAddress(double_constant(c->as_jdouble()))); 690 } 691 } 692 break; 693 } 694 695 default: 696 ShouldNotReachHere(); 697 } 698 } 699 700 void LIR_Assembler::const2stack(LIR_Opr src, LIR_Opr dest) { 701 assert(src->is_constant(), "should not call otherwise"); 702 assert(dest->is_stack(), "should not call otherwise"); 703 LIR_Const* c = src->as_constant_ptr(); 704 705 switch (c->type()) { 706 case T_INT: // fall through 707 case T_FLOAT: 708 __ movl(frame_map()->address_for_slot(dest->single_stack_ix()), c->as_jint_bits()); 709 break; 710 711 case T_ADDRESS: 712 __ movptr(frame_map()->address_for_slot(dest->single_stack_ix()), c->as_jint_bits()); 713 break; 714 715 case T_VALUETYPE: // Fall through 716 case T_OBJECT: 717 __ movoop(frame_map()->address_for_slot(dest->single_stack_ix()), c->as_jobject()); 718 break; 719 720 case T_LONG: // fall through 721 case T_DOUBLE: 722 #ifdef _LP64 723 __ movptr(frame_map()->address_for_slot(dest->double_stack_ix(), 724 lo_word_offset_in_bytes), (intptr_t)c->as_jlong_bits()); 725 #else 726 __ movptr(frame_map()->address_for_slot(dest->double_stack_ix(), 727 lo_word_offset_in_bytes), c->as_jint_lo_bits()); 728 __ movptr(frame_map()->address_for_slot(dest->double_stack_ix(), 729 hi_word_offset_in_bytes), c->as_jint_hi_bits()); 730 #endif // _LP64 731 break; 732 733 default: 734 ShouldNotReachHere(); 735 } 736 } 737 738 void LIR_Assembler::const2mem(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info, bool wide) { 739 assert(src->is_constant(), "should not call otherwise"); 740 assert(dest->is_address(), "should not call otherwise"); 741 LIR_Const* c = src->as_constant_ptr(); 742 LIR_Address* addr = dest->as_address_ptr(); 743 744 int null_check_here = code_offset(); 745 switch (type) { 746 case T_INT: // fall through 747 case T_FLOAT: 748 __ movl(as_Address(addr), c->as_jint_bits()); 749 break; 750 751 case T_ADDRESS: 752 __ movptr(as_Address(addr), c->as_jint_bits()); 753 break; 754 755 case T_VALUETYPE: // fall through 756 case T_OBJECT: // fall through 757 case T_ARRAY: 758 if (c->as_jobject() == NULL) { 759 if (UseCompressedOops && !wide) { 760 __ movl(as_Address(addr), (int32_t)NULL_WORD); 761 } else { 762 #ifdef _LP64 763 __ xorptr(rscratch1, rscratch1); 764 null_check_here = code_offset(); 765 __ movptr(as_Address(addr), rscratch1); 766 #else 767 __ movptr(as_Address(addr), NULL_WORD); 768 #endif 769 } 770 } else { 771 if (is_literal_address(addr)) { 772 ShouldNotReachHere(); 773 __ movoop(as_Address(addr, noreg), c->as_jobject()); 774 } else { 775 #ifdef _LP64 776 __ movoop(rscratch1, c->as_jobject()); 777 if (UseCompressedOops && !wide) { 778 __ encode_heap_oop(rscratch1); 779 null_check_here = code_offset(); 780 __ movl(as_Address_lo(addr), rscratch1); 781 } else { 782 null_check_here = code_offset(); 783 __ movptr(as_Address_lo(addr), rscratch1); 784 } 785 #else 786 __ movoop(as_Address(addr), c->as_jobject()); 787 #endif 788 } 789 } 790 break; 791 792 case T_LONG: // fall through 793 case T_DOUBLE: 794 #ifdef _LP64 795 if (is_literal_address(addr)) { 796 ShouldNotReachHere(); 797 __ movptr(as_Address(addr, r15_thread), (intptr_t)c->as_jlong_bits()); 798 } else { 799 __ movptr(r10, (intptr_t)c->as_jlong_bits()); 800 null_check_here = code_offset(); 801 __ movptr(as_Address_lo(addr), r10); 802 } 803 #else 804 // Always reachable in 32bit so this doesn't produce useless move literal 805 __ movptr(as_Address_hi(addr), c->as_jint_hi_bits()); 806 __ movptr(as_Address_lo(addr), c->as_jint_lo_bits()); 807 #endif // _LP64 808 break; 809 810 case T_BOOLEAN: // fall through 811 case T_BYTE: 812 __ movb(as_Address(addr), c->as_jint() & 0xFF); 813 break; 814 815 case T_CHAR: // fall through 816 case T_SHORT: 817 __ movw(as_Address(addr), c->as_jint() & 0xFFFF); 818 break; 819 820 default: 821 ShouldNotReachHere(); 822 }; 823 824 if (info != NULL) { 825 add_debug_info_for_null_check(null_check_here, info); 826 } 827 } 828 829 830 void LIR_Assembler::reg2reg(LIR_Opr src, LIR_Opr dest) { 831 assert(src->is_register(), "should not call otherwise"); 832 assert(dest->is_register(), "should not call otherwise"); 833 834 // move between cpu-registers 835 if (dest->is_single_cpu()) { 836 #ifdef _LP64 837 if (src->type() == T_LONG) { 838 // Can do LONG -> OBJECT 839 move_regs(src->as_register_lo(), dest->as_register()); 840 return; 841 } 842 #endif 843 assert(src->is_single_cpu(), "must match"); 844 if (src->type() == T_OBJECT || src->type() == T_VALUETYPE) { 845 __ verify_oop(src->as_register()); 846 } 847 move_regs(src->as_register(), dest->as_register()); 848 849 } else if (dest->is_double_cpu()) { 850 #ifdef _LP64 851 if (src->type() == T_OBJECT || src->type() == T_ARRAY || src->type() == T_VALUETYPE) { 852 // Surprising to me but we can see move of a long to t_object 853 __ verify_oop(src->as_register()); 854 move_regs(src->as_register(), dest->as_register_lo()); 855 return; 856 } 857 #endif 858 assert(src->is_double_cpu(), "must match"); 859 Register f_lo = src->as_register_lo(); 860 Register f_hi = src->as_register_hi(); 861 Register t_lo = dest->as_register_lo(); 862 Register t_hi = dest->as_register_hi(); 863 #ifdef _LP64 864 assert(f_hi == f_lo, "must be same"); 865 assert(t_hi == t_lo, "must be same"); 866 move_regs(f_lo, t_lo); 867 #else 868 assert(f_lo != f_hi && t_lo != t_hi, "invalid register allocation"); 869 870 871 if (f_lo == t_hi && f_hi == t_lo) { 872 swap_reg(f_lo, f_hi); 873 } else if (f_hi == t_lo) { 874 assert(f_lo != t_hi, "overwriting register"); 875 move_regs(f_hi, t_hi); 876 move_regs(f_lo, t_lo); 877 } else { 878 assert(f_hi != t_lo, "overwriting register"); 879 move_regs(f_lo, t_lo); 880 move_regs(f_hi, t_hi); 881 } 882 #endif // LP64 883 884 // special moves from fpu-register to xmm-register 885 // necessary for method results 886 } else if (src->is_single_xmm() && !dest->is_single_xmm()) { 887 __ movflt(Address(rsp, 0), src->as_xmm_float_reg()); 888 __ fld_s(Address(rsp, 0)); 889 } else if (src->is_double_xmm() && !dest->is_double_xmm()) { 890 __ movdbl(Address(rsp, 0), src->as_xmm_double_reg()); 891 __ fld_d(Address(rsp, 0)); 892 } else if (dest->is_single_xmm() && !src->is_single_xmm()) { 893 __ fstp_s(Address(rsp, 0)); 894 __ movflt(dest->as_xmm_float_reg(), Address(rsp, 0)); 895 } else if (dest->is_double_xmm() && !src->is_double_xmm()) { 896 __ fstp_d(Address(rsp, 0)); 897 __ movdbl(dest->as_xmm_double_reg(), Address(rsp, 0)); 898 899 // move between xmm-registers 900 } else if (dest->is_single_xmm()) { 901 assert(src->is_single_xmm(), "must match"); 902 __ movflt(dest->as_xmm_float_reg(), src->as_xmm_float_reg()); 903 } else if (dest->is_double_xmm()) { 904 assert(src->is_double_xmm(), "must match"); 905 __ movdbl(dest->as_xmm_double_reg(), src->as_xmm_double_reg()); 906 907 // move between fpu-registers (no instruction necessary because of fpu-stack) 908 } else if (dest->is_single_fpu() || dest->is_double_fpu()) { 909 assert(src->is_single_fpu() || src->is_double_fpu(), "must match"); 910 assert(src->fpu() == dest->fpu(), "currently should be nothing to do"); 911 } else { 912 ShouldNotReachHere(); 913 } 914 } 915 916 void LIR_Assembler::reg2stack(LIR_Opr src, LIR_Opr dest, BasicType type, bool pop_fpu_stack) { 917 assert(src->is_register(), "should not call otherwise"); 918 assert(dest->is_stack(), "should not call otherwise"); 919 920 if (src->is_single_cpu()) { 921 Address dst = frame_map()->address_for_slot(dest->single_stack_ix()); 922 if (type == T_OBJECT || type == T_ARRAY || type == T_VALUETYPE) { 923 __ verify_oop(src->as_register()); 924 __ movptr (dst, src->as_register()); 925 } else if (type == T_METADATA) { 926 __ movptr (dst, src->as_register()); 927 } else { 928 __ movl (dst, src->as_register()); 929 } 930 931 } else if (src->is_double_cpu()) { 932 Address dstLO = frame_map()->address_for_slot(dest->double_stack_ix(), lo_word_offset_in_bytes); 933 Address dstHI = frame_map()->address_for_slot(dest->double_stack_ix(), hi_word_offset_in_bytes); 934 __ movptr (dstLO, src->as_register_lo()); 935 NOT_LP64(__ movptr (dstHI, src->as_register_hi())); 936 937 } else if (src->is_single_xmm()) { 938 Address dst_addr = frame_map()->address_for_slot(dest->single_stack_ix()); 939 __ movflt(dst_addr, src->as_xmm_float_reg()); 940 941 } else if (src->is_double_xmm()) { 942 Address dst_addr = frame_map()->address_for_slot(dest->double_stack_ix()); 943 __ movdbl(dst_addr, src->as_xmm_double_reg()); 944 945 } else if (src->is_single_fpu()) { 946 assert(src->fpu_regnr() == 0, "argument must be on TOS"); 947 Address dst_addr = frame_map()->address_for_slot(dest->single_stack_ix()); 948 if (pop_fpu_stack) __ fstp_s (dst_addr); 949 else __ fst_s (dst_addr); 950 951 } else if (src->is_double_fpu()) { 952 assert(src->fpu_regnrLo() == 0, "argument must be on TOS"); 953 Address dst_addr = frame_map()->address_for_slot(dest->double_stack_ix()); 954 if (pop_fpu_stack) __ fstp_d (dst_addr); 955 else __ fst_d (dst_addr); 956 957 } else { 958 ShouldNotReachHere(); 959 } 960 } 961 962 963 void LIR_Assembler::reg2mem(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool pop_fpu_stack, bool wide, bool /* unaligned */) { 964 LIR_Address* to_addr = dest->as_address_ptr(); 965 PatchingStub* patch = NULL; 966 Register compressed_src = rscratch1; 967 968 if (type == T_ARRAY || type == T_OBJECT || type == T_VALUETYPE) { 969 __ verify_oop(src->as_register()); 970 #ifdef _LP64 971 if (UseCompressedOops && !wide) { 972 __ movptr(compressed_src, src->as_register()); 973 __ encode_heap_oop(compressed_src); 974 if (patch_code != lir_patch_none) { 975 info->oop_map()->set_narrowoop(compressed_src->as_VMReg()); 976 } 977 } 978 #endif 979 } 980 981 if (patch_code != lir_patch_none) { 982 patch = new PatchingStub(_masm, PatchingStub::access_field_id); 983 Address toa = as_Address(to_addr); 984 assert(toa.disp() != 0, "must have"); 985 } 986 987 int null_check_here = code_offset(); 988 switch (type) { 989 case T_FLOAT: { 990 if (src->is_single_xmm()) { 991 __ movflt(as_Address(to_addr), src->as_xmm_float_reg()); 992 } else { 993 assert(src->is_single_fpu(), "must be"); 994 assert(src->fpu_regnr() == 0, "argument must be on TOS"); 995 if (pop_fpu_stack) __ fstp_s(as_Address(to_addr)); 996 else __ fst_s (as_Address(to_addr)); 997 } 998 break; 999 } 1000 1001 case T_DOUBLE: { 1002 if (src->is_double_xmm()) { 1003 __ movdbl(as_Address(to_addr), src->as_xmm_double_reg()); 1004 } else { 1005 assert(src->is_double_fpu(), "must be"); 1006 assert(src->fpu_regnrLo() == 0, "argument must be on TOS"); 1007 if (pop_fpu_stack) __ fstp_d(as_Address(to_addr)); 1008 else __ fst_d (as_Address(to_addr)); 1009 } 1010 break; 1011 } 1012 1013 case T_VALUETYPE: // fall through 1014 case T_ARRAY: // fall through 1015 case T_OBJECT: // fall through 1016 if (UseCompressedOops && !wide) { 1017 __ movl(as_Address(to_addr), compressed_src); 1018 } else { 1019 __ movptr(as_Address(to_addr), src->as_register()); 1020 } 1021 break; 1022 case T_METADATA: 1023 // We get here to store a method pointer to the stack to pass to 1024 // a dtrace runtime call. This can't work on 64 bit with 1025 // compressed klass ptrs: T_METADATA can be a compressed klass 1026 // ptr or a 64 bit method pointer. 1027 LP64_ONLY(ShouldNotReachHere()); 1028 __ movptr(as_Address(to_addr), src->as_register()); 1029 break; 1030 case T_ADDRESS: 1031 __ movptr(as_Address(to_addr), src->as_register()); 1032 break; 1033 case T_INT: 1034 __ movl(as_Address(to_addr), src->as_register()); 1035 break; 1036 1037 case T_LONG: { 1038 Register from_lo = src->as_register_lo(); 1039 Register from_hi = src->as_register_hi(); 1040 #ifdef _LP64 1041 __ movptr(as_Address_lo(to_addr), from_lo); 1042 #else 1043 Register base = to_addr->base()->as_register(); 1044 Register index = noreg; 1045 if (to_addr->index()->is_register()) { 1046 index = to_addr->index()->as_register(); 1047 } 1048 if (base == from_lo || index == from_lo) { 1049 assert(base != from_hi, "can't be"); 1050 assert(index == noreg || (index != base && index != from_hi), "can't handle this"); 1051 __ movl(as_Address_hi(to_addr), from_hi); 1052 if (patch != NULL) { 1053 patching_epilog(patch, lir_patch_high, base, info); 1054 patch = new PatchingStub(_masm, PatchingStub::access_field_id); 1055 patch_code = lir_patch_low; 1056 } 1057 __ movl(as_Address_lo(to_addr), from_lo); 1058 } else { 1059 assert(index == noreg || (index != base && index != from_lo), "can't handle this"); 1060 __ movl(as_Address_lo(to_addr), from_lo); 1061 if (patch != NULL) { 1062 patching_epilog(patch, lir_patch_low, base, info); 1063 patch = new PatchingStub(_masm, PatchingStub::access_field_id); 1064 patch_code = lir_patch_high; 1065 } 1066 __ movl(as_Address_hi(to_addr), from_hi); 1067 } 1068 #endif // _LP64 1069 break; 1070 } 1071 1072 case T_BYTE: // fall through 1073 case T_BOOLEAN: { 1074 Register src_reg = src->as_register(); 1075 Address dst_addr = as_Address(to_addr); 1076 assert(VM_Version::is_P6() || src_reg->has_byte_register(), "must use byte registers if not P6"); 1077 __ movb(dst_addr, src_reg); 1078 break; 1079 } 1080 1081 case T_CHAR: // fall through 1082 case T_SHORT: 1083 __ movw(as_Address(to_addr), src->as_register()); 1084 break; 1085 1086 default: 1087 ShouldNotReachHere(); 1088 } 1089 if (info != NULL) { 1090 add_debug_info_for_null_check(null_check_here, info); 1091 } 1092 1093 if (patch_code != lir_patch_none) { 1094 patching_epilog(patch, patch_code, to_addr->base()->as_register(), info); 1095 } 1096 } 1097 1098 1099 void LIR_Assembler::stack2reg(LIR_Opr src, LIR_Opr dest, BasicType type) { 1100 assert(src->is_stack(), "should not call otherwise"); 1101 assert(dest->is_register(), "should not call otherwise"); 1102 1103 if (dest->is_single_cpu()) { 1104 if (type == T_ARRAY || type == T_OBJECT || type == T_VALUETYPE) { 1105 __ movptr(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix())); 1106 __ verify_oop(dest->as_register()); 1107 } else if (type == T_METADATA) { 1108 __ movptr(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix())); 1109 } else { 1110 __ movl(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix())); 1111 } 1112 1113 } else if (dest->is_double_cpu()) { 1114 Address src_addr_LO = frame_map()->address_for_slot(src->double_stack_ix(), lo_word_offset_in_bytes); 1115 Address src_addr_HI = frame_map()->address_for_slot(src->double_stack_ix(), hi_word_offset_in_bytes); 1116 __ movptr(dest->as_register_lo(), src_addr_LO); 1117 NOT_LP64(__ movptr(dest->as_register_hi(), src_addr_HI)); 1118 1119 } else if (dest->is_single_xmm()) { 1120 Address src_addr = frame_map()->address_for_slot(src->single_stack_ix()); 1121 __ movflt(dest->as_xmm_float_reg(), src_addr); 1122 1123 } else if (dest->is_double_xmm()) { 1124 Address src_addr = frame_map()->address_for_slot(src->double_stack_ix()); 1125 __ movdbl(dest->as_xmm_double_reg(), src_addr); 1126 1127 } else if (dest->is_single_fpu()) { 1128 assert(dest->fpu_regnr() == 0, "dest must be TOS"); 1129 Address src_addr = frame_map()->address_for_slot(src->single_stack_ix()); 1130 __ fld_s(src_addr); 1131 1132 } else if (dest->is_double_fpu()) { 1133 assert(dest->fpu_regnrLo() == 0, "dest must be TOS"); 1134 Address src_addr = frame_map()->address_for_slot(src->double_stack_ix()); 1135 __ fld_d(src_addr); 1136 1137 } else { 1138 ShouldNotReachHere(); 1139 } 1140 } 1141 1142 1143 void LIR_Assembler::stack2stack(LIR_Opr src, LIR_Opr dest, BasicType type) { 1144 if (src->is_single_stack()) { 1145 if (type == T_OBJECT || type == T_ARRAY || type == T_VALUETYPE) { 1146 __ pushptr(frame_map()->address_for_slot(src ->single_stack_ix())); 1147 __ popptr (frame_map()->address_for_slot(dest->single_stack_ix())); 1148 } else { 1149 #ifndef _LP64 1150 __ pushl(frame_map()->address_for_slot(src ->single_stack_ix())); 1151 __ popl (frame_map()->address_for_slot(dest->single_stack_ix())); 1152 #else 1153 //no pushl on 64bits 1154 __ movl(rscratch1, frame_map()->address_for_slot(src ->single_stack_ix())); 1155 __ movl(frame_map()->address_for_slot(dest->single_stack_ix()), rscratch1); 1156 #endif 1157 } 1158 1159 } else if (src->is_double_stack()) { 1160 #ifdef _LP64 1161 __ pushptr(frame_map()->address_for_slot(src ->double_stack_ix())); 1162 __ popptr (frame_map()->address_for_slot(dest->double_stack_ix())); 1163 #else 1164 __ pushl(frame_map()->address_for_slot(src ->double_stack_ix(), 0)); 1165 // push and pop the part at src + wordSize, adding wordSize for the previous push 1166 __ pushl(frame_map()->address_for_slot(src ->double_stack_ix(), 2 * wordSize)); 1167 __ popl (frame_map()->address_for_slot(dest->double_stack_ix(), 2 * wordSize)); 1168 __ popl (frame_map()->address_for_slot(dest->double_stack_ix(), 0)); 1169 #endif // _LP64 1170 1171 } else { 1172 ShouldNotReachHere(); 1173 } 1174 } 1175 1176 1177 void LIR_Assembler::mem2reg(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool wide, bool /* unaligned */) { 1178 assert(src->is_address(), "should not call otherwise"); 1179 assert(dest->is_register(), "should not call otherwise"); 1180 1181 LIR_Address* addr = src->as_address_ptr(); 1182 Address from_addr = as_Address(addr); 1183 1184 if (addr->base()->type() == T_OBJECT || addr->base()->type() == T_VALUETYPE) { 1185 __ verify_oop(addr->base()->as_pointer_register()); 1186 } 1187 1188 switch (type) { 1189 case T_BOOLEAN: // fall through 1190 case T_BYTE: // fall through 1191 case T_CHAR: // fall through 1192 case T_SHORT: 1193 if (!VM_Version::is_P6() && !from_addr.uses(dest->as_register())) { 1194 // on pre P6 processors we may get partial register stalls 1195 // so blow away the value of to_rinfo before loading a 1196 // partial word into it. Do it here so that it precedes 1197 // the potential patch point below. 1198 __ xorptr(dest->as_register(), dest->as_register()); 1199 } 1200 break; 1201 default: 1202 break; 1203 } 1204 1205 PatchingStub* patch = NULL; 1206 if (patch_code != lir_patch_none) { 1207 patch = new PatchingStub(_masm, PatchingStub::access_field_id); 1208 assert(from_addr.disp() != 0, "must have"); 1209 } 1210 if (info != NULL) { 1211 add_debug_info_for_null_check_here(info); 1212 } 1213 1214 switch (type) { 1215 case T_FLOAT: { 1216 if (dest->is_single_xmm()) { 1217 __ movflt(dest->as_xmm_float_reg(), from_addr); 1218 } else { 1219 assert(dest->is_single_fpu(), "must be"); 1220 assert(dest->fpu_regnr() == 0, "dest must be TOS"); 1221 __ fld_s(from_addr); 1222 } 1223 break; 1224 } 1225 1226 case T_DOUBLE: { 1227 if (dest->is_double_xmm()) { 1228 __ movdbl(dest->as_xmm_double_reg(), from_addr); 1229 } else { 1230 assert(dest->is_double_fpu(), "must be"); 1231 assert(dest->fpu_regnrLo() == 0, "dest must be TOS"); 1232 __ fld_d(from_addr); 1233 } 1234 break; 1235 } 1236 1237 case T_VALUETYPE: // fall through 1238 case T_OBJECT: // fall through 1239 case T_ARRAY: // fall through 1240 if (UseCompressedOops && !wide) { 1241 __ movl(dest->as_register(), from_addr); 1242 } else { 1243 __ movptr(dest->as_register(), from_addr); 1244 } 1245 break; 1246 1247 case T_ADDRESS: 1248 if (UseCompressedClassPointers && addr->disp() == oopDesc::klass_offset_in_bytes()) { 1249 __ movl(dest->as_register(), from_addr); 1250 } else { 1251 __ movptr(dest->as_register(), from_addr); 1252 } 1253 break; 1254 case T_INT: 1255 __ movl(dest->as_register(), from_addr); 1256 break; 1257 1258 case T_LONG: { 1259 Register to_lo = dest->as_register_lo(); 1260 Register to_hi = dest->as_register_hi(); 1261 #ifdef _LP64 1262 __ movptr(to_lo, as_Address_lo(addr)); 1263 #else 1264 Register base = addr->base()->as_register(); 1265 Register index = noreg; 1266 if (addr->index()->is_register()) { 1267 index = addr->index()->as_register(); 1268 } 1269 if ((base == to_lo && index == to_hi) || 1270 (base == to_hi && index == to_lo)) { 1271 // addresses with 2 registers are only formed as a result of 1272 // array access so this code will never have to deal with 1273 // patches or null checks. 1274 assert(info == NULL && patch == NULL, "must be"); 1275 __ lea(to_hi, as_Address(addr)); 1276 __ movl(to_lo, Address(to_hi, 0)); 1277 __ movl(to_hi, Address(to_hi, BytesPerWord)); 1278 } else if (base == to_lo || index == to_lo) { 1279 assert(base != to_hi, "can't be"); 1280 assert(index == noreg || (index != base && index != to_hi), "can't handle this"); 1281 __ movl(to_hi, as_Address_hi(addr)); 1282 if (patch != NULL) { 1283 patching_epilog(patch, lir_patch_high, base, info); 1284 patch = new PatchingStub(_masm, PatchingStub::access_field_id); 1285 patch_code = lir_patch_low; 1286 } 1287 __ movl(to_lo, as_Address_lo(addr)); 1288 } else { 1289 assert(index == noreg || (index != base && index != to_lo), "can't handle this"); 1290 __ movl(to_lo, as_Address_lo(addr)); 1291 if (patch != NULL) { 1292 patching_epilog(patch, lir_patch_low, base, info); 1293 patch = new PatchingStub(_masm, PatchingStub::access_field_id); 1294 patch_code = lir_patch_high; 1295 } 1296 __ movl(to_hi, as_Address_hi(addr)); 1297 } 1298 #endif // _LP64 1299 break; 1300 } 1301 1302 case T_BOOLEAN: // fall through 1303 case T_BYTE: { 1304 Register dest_reg = dest->as_register(); 1305 assert(VM_Version::is_P6() || dest_reg->has_byte_register(), "must use byte registers if not P6"); 1306 if (VM_Version::is_P6() || from_addr.uses(dest_reg)) { 1307 __ movsbl(dest_reg, from_addr); 1308 } else { 1309 __ movb(dest_reg, from_addr); 1310 __ shll(dest_reg, 24); 1311 __ sarl(dest_reg, 24); 1312 } 1313 break; 1314 } 1315 1316 case T_CHAR: { 1317 Register dest_reg = dest->as_register(); 1318 assert(VM_Version::is_P6() || dest_reg->has_byte_register(), "must use byte registers if not P6"); 1319 if (VM_Version::is_P6() || from_addr.uses(dest_reg)) { 1320 __ movzwl(dest_reg, from_addr); 1321 } else { 1322 __ movw(dest_reg, from_addr); 1323 } 1324 break; 1325 } 1326 1327 case T_SHORT: { 1328 Register dest_reg = dest->as_register(); 1329 if (VM_Version::is_P6() || from_addr.uses(dest_reg)) { 1330 __ movswl(dest_reg, from_addr); 1331 } else { 1332 __ movw(dest_reg, from_addr); 1333 __ shll(dest_reg, 16); 1334 __ sarl(dest_reg, 16); 1335 } 1336 break; 1337 } 1338 1339 default: 1340 ShouldNotReachHere(); 1341 } 1342 1343 if (patch != NULL) { 1344 patching_epilog(patch, patch_code, addr->base()->as_register(), info); 1345 } 1346 1347 if (type == T_ARRAY || type == T_OBJECT || type == T_VALUETYPE) { 1348 #ifdef _LP64 1349 if (UseCompressedOops && !wide) { 1350 __ decode_heap_oop(dest->as_register()); 1351 } 1352 #endif 1353 1354 // Load barrier has not yet been applied, so ZGC can't verify the oop here 1355 if (!UseZGC) { 1356 __ verify_oop(dest->as_register()); 1357 } 1358 } else if (type == T_ADDRESS && addr->disp() == oopDesc::klass_offset_in_bytes()) { 1359 #ifdef _LP64 1360 if (UseCompressedClassPointers) { 1361 __ decode_klass_not_null(dest->as_register()); 1362 } 1363 #endif 1364 } 1365 } 1366 1367 1368 NEEDS_CLEANUP; // This could be static? 1369 Address::ScaleFactor LIR_Assembler::array_element_size(BasicType type) const { 1370 int elem_size = type2aelembytes(type); 1371 switch (elem_size) { 1372 case 1: return Address::times_1; 1373 case 2: return Address::times_2; 1374 case 4: return Address::times_4; 1375 case 8: return Address::times_8; 1376 } 1377 ShouldNotReachHere(); 1378 return Address::no_scale; 1379 } 1380 1381 1382 void LIR_Assembler::emit_op3(LIR_Op3* op) { 1383 switch (op->code()) { 1384 case lir_idiv: 1385 case lir_irem: 1386 arithmetic_idiv(op->code(), 1387 op->in_opr1(), 1388 op->in_opr2(), 1389 op->in_opr3(), 1390 op->result_opr(), 1391 op->info()); 1392 break; 1393 case lir_fmad: 1394 __ fmad(op->result_opr()->as_xmm_double_reg(), 1395 op->in_opr1()->as_xmm_double_reg(), 1396 op->in_opr2()->as_xmm_double_reg(), 1397 op->in_opr3()->as_xmm_double_reg()); 1398 break; 1399 case lir_fmaf: 1400 __ fmaf(op->result_opr()->as_xmm_float_reg(), 1401 op->in_opr1()->as_xmm_float_reg(), 1402 op->in_opr2()->as_xmm_float_reg(), 1403 op->in_opr3()->as_xmm_float_reg()); 1404 break; 1405 default: ShouldNotReachHere(); break; 1406 } 1407 } 1408 1409 void LIR_Assembler::emit_opBranch(LIR_OpBranch* op) { 1410 #ifdef ASSERT 1411 assert(op->block() == NULL || op->block()->label() == op->label(), "wrong label"); 1412 if (op->block() != NULL) _branch_target_blocks.append(op->block()); 1413 if (op->ublock() != NULL) _branch_target_blocks.append(op->ublock()); 1414 #endif 1415 1416 if (op->cond() == lir_cond_always) { 1417 if (op->info() != NULL) add_debug_info_for_branch(op->info()); 1418 __ jmp (*(op->label())); 1419 } else { 1420 Assembler::Condition acond = Assembler::zero; 1421 if (op->code() == lir_cond_float_branch) { 1422 assert(op->ublock() != NULL, "must have unordered successor"); 1423 __ jcc(Assembler::parity, *(op->ublock()->label())); 1424 switch(op->cond()) { 1425 case lir_cond_equal: acond = Assembler::equal; break; 1426 case lir_cond_notEqual: acond = Assembler::notEqual; break; 1427 case lir_cond_less: acond = Assembler::below; break; 1428 case lir_cond_lessEqual: acond = Assembler::belowEqual; break; 1429 case lir_cond_greaterEqual: acond = Assembler::aboveEqual; break; 1430 case lir_cond_greater: acond = Assembler::above; break; 1431 default: ShouldNotReachHere(); 1432 } 1433 } else { 1434 switch (op->cond()) { 1435 case lir_cond_equal: acond = Assembler::equal; break; 1436 case lir_cond_notEqual: acond = Assembler::notEqual; break; 1437 case lir_cond_less: acond = Assembler::less; break; 1438 case lir_cond_lessEqual: acond = Assembler::lessEqual; break; 1439 case lir_cond_greaterEqual: acond = Assembler::greaterEqual;break; 1440 case lir_cond_greater: acond = Assembler::greater; break; 1441 case lir_cond_belowEqual: acond = Assembler::belowEqual; break; 1442 case lir_cond_aboveEqual: acond = Assembler::aboveEqual; break; 1443 default: ShouldNotReachHere(); 1444 } 1445 } 1446 __ jcc(acond,*(op->label())); 1447 } 1448 } 1449 1450 void LIR_Assembler::emit_opConvert(LIR_OpConvert* op) { 1451 LIR_Opr src = op->in_opr(); 1452 LIR_Opr dest = op->result_opr(); 1453 1454 switch (op->bytecode()) { 1455 case Bytecodes::_i2l: 1456 #ifdef _LP64 1457 __ movl2ptr(dest->as_register_lo(), src->as_register()); 1458 #else 1459 move_regs(src->as_register(), dest->as_register_lo()); 1460 move_regs(src->as_register(), dest->as_register_hi()); 1461 __ sarl(dest->as_register_hi(), 31); 1462 #endif // LP64 1463 break; 1464 1465 case Bytecodes::_l2i: 1466 #ifdef _LP64 1467 __ movl(dest->as_register(), src->as_register_lo()); 1468 #else 1469 move_regs(src->as_register_lo(), dest->as_register()); 1470 #endif 1471 break; 1472 1473 case Bytecodes::_i2b: 1474 move_regs(src->as_register(), dest->as_register()); 1475 __ sign_extend_byte(dest->as_register()); 1476 break; 1477 1478 case Bytecodes::_i2c: 1479 move_regs(src->as_register(), dest->as_register()); 1480 __ andl(dest->as_register(), 0xFFFF); 1481 break; 1482 1483 case Bytecodes::_i2s: 1484 move_regs(src->as_register(), dest->as_register()); 1485 __ sign_extend_short(dest->as_register()); 1486 break; 1487 1488 1489 case Bytecodes::_f2d: 1490 case Bytecodes::_d2f: 1491 if (dest->is_single_xmm()) { 1492 __ cvtsd2ss(dest->as_xmm_float_reg(), src->as_xmm_double_reg()); 1493 } else if (dest->is_double_xmm()) { 1494 __ cvtss2sd(dest->as_xmm_double_reg(), src->as_xmm_float_reg()); 1495 } else { 1496 assert(src->fpu() == dest->fpu(), "register must be equal"); 1497 // do nothing (float result is rounded later through spilling) 1498 } 1499 break; 1500 1501 case Bytecodes::_i2f: 1502 case Bytecodes::_i2d: 1503 if (dest->is_single_xmm()) { 1504 __ cvtsi2ssl(dest->as_xmm_float_reg(), src->as_register()); 1505 } else if (dest->is_double_xmm()) { 1506 __ cvtsi2sdl(dest->as_xmm_double_reg(), src->as_register()); 1507 } else { 1508 assert(dest->fpu() == 0, "result must be on TOS"); 1509 __ movl(Address(rsp, 0), src->as_register()); 1510 __ fild_s(Address(rsp, 0)); 1511 } 1512 break; 1513 1514 case Bytecodes::_f2i: 1515 case Bytecodes::_d2i: 1516 if (src->is_single_xmm()) { 1517 __ cvttss2sil(dest->as_register(), src->as_xmm_float_reg()); 1518 } else if (src->is_double_xmm()) { 1519 __ cvttsd2sil(dest->as_register(), src->as_xmm_double_reg()); 1520 } else { 1521 assert(src->fpu() == 0, "input must be on TOS"); 1522 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_trunc())); 1523 __ fist_s(Address(rsp, 0)); 1524 __ movl(dest->as_register(), Address(rsp, 0)); 1525 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std())); 1526 } 1527 1528 // IA32 conversion instructions do not match JLS for overflow, underflow and NaN -> fixup in stub 1529 assert(op->stub() != NULL, "stub required"); 1530 __ cmpl(dest->as_register(), 0x80000000); 1531 __ jcc(Assembler::equal, *op->stub()->entry()); 1532 __ bind(*op->stub()->continuation()); 1533 break; 1534 1535 case Bytecodes::_l2f: 1536 case Bytecodes::_l2d: 1537 assert(!dest->is_xmm_register(), "result in xmm register not supported (no SSE instruction present)"); 1538 assert(dest->fpu() == 0, "result must be on TOS"); 1539 1540 __ movptr(Address(rsp, 0), src->as_register_lo()); 1541 NOT_LP64(__ movl(Address(rsp, BytesPerWord), src->as_register_hi())); 1542 __ fild_d(Address(rsp, 0)); 1543 // float result is rounded later through spilling 1544 break; 1545 1546 case Bytecodes::_f2l: 1547 case Bytecodes::_d2l: 1548 assert(!src->is_xmm_register(), "input in xmm register not supported (no SSE instruction present)"); 1549 assert(src->fpu() == 0, "input must be on TOS"); 1550 assert(dest == FrameMap::long0_opr, "runtime stub places result in these registers"); 1551 1552 // instruction sequence too long to inline it here 1553 { 1554 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::fpu2long_stub_id))); 1555 } 1556 break; 1557 1558 default: ShouldNotReachHere(); 1559 } 1560 } 1561 1562 void LIR_Assembler::emit_alloc_obj(LIR_OpAllocObj* op) { 1563 if (op->init_check()) { 1564 add_debug_info_for_null_check_here(op->stub()->info()); 1565 __ cmpb(Address(op->klass()->as_register(), 1566 InstanceKlass::init_state_offset()), 1567 InstanceKlass::fully_initialized); 1568 __ jcc(Assembler::notEqual, *op->stub()->entry()); 1569 } 1570 __ allocate_object(op->obj()->as_register(), 1571 op->tmp1()->as_register(), 1572 op->tmp2()->as_register(), 1573 op->header_size(), 1574 op->object_size(), 1575 op->klass()->as_register(), 1576 *op->stub()->entry()); 1577 __ bind(*op->stub()->continuation()); 1578 } 1579 1580 void LIR_Assembler::emit_alloc_array(LIR_OpAllocArray* op) { 1581 Register len = op->len()->as_register(); 1582 LP64_ONLY( __ movslq(len, len); ) 1583 1584 if (UseSlowPath || op->type() == T_VALUETYPE || 1585 (!UseFastNewObjectArray && (op->type() == T_OBJECT || op->type() == T_ARRAY)) || 1586 (!UseFastNewTypeArray && (op->type() != T_OBJECT && op->type() != T_ARRAY))) { 1587 __ jmp(*op->stub()->entry()); 1588 } else { 1589 Register tmp1 = op->tmp1()->as_register(); 1590 Register tmp2 = op->tmp2()->as_register(); 1591 Register tmp3 = op->tmp3()->as_register(); 1592 if (len == tmp1) { 1593 tmp1 = tmp3; 1594 } else if (len == tmp2) { 1595 tmp2 = tmp3; 1596 } else if (len == tmp3) { 1597 // everything is ok 1598 } else { 1599 __ mov(tmp3, len); 1600 } 1601 __ allocate_array(op->obj()->as_register(), 1602 len, 1603 tmp1, 1604 tmp2, 1605 arrayOopDesc::header_size(op->type()), 1606 array_element_size(op->type()), 1607 op->klass()->as_register(), 1608 *op->stub()->entry()); 1609 } 1610 __ bind(*op->stub()->continuation()); 1611 } 1612 1613 void LIR_Assembler::type_profile_helper(Register mdo, 1614 ciMethodData *md, ciProfileData *data, 1615 Register recv, Label* update_done) { 1616 for (uint i = 0; i < ReceiverTypeData::row_limit(); i++) { 1617 Label next_test; 1618 // See if the receiver is receiver[n]. 1619 __ cmpptr(recv, Address(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i)))); 1620 __ jccb(Assembler::notEqual, next_test); 1621 Address data_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i))); 1622 __ addptr(data_addr, DataLayout::counter_increment); 1623 __ jmp(*update_done); 1624 __ bind(next_test); 1625 } 1626 1627 // Didn't find receiver; find next empty slot and fill it in 1628 for (uint i = 0; i < ReceiverTypeData::row_limit(); i++) { 1629 Label next_test; 1630 Address recv_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i))); 1631 __ cmpptr(recv_addr, (intptr_t)NULL_WORD); 1632 __ jccb(Assembler::notEqual, next_test); 1633 __ movptr(recv_addr, recv); 1634 __ movptr(Address(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i))), DataLayout::counter_increment); 1635 __ jmp(*update_done); 1636 __ bind(next_test); 1637 } 1638 } 1639 1640 void LIR_Assembler::emit_typecheck_helper(LIR_OpTypeCheck *op, Label* success, Label* failure, Label* obj_is_null) { 1641 // we always need a stub for the failure case. 1642 CodeStub* stub = op->stub(); 1643 Register obj = op->object()->as_register(); 1644 Register k_RInfo = op->tmp1()->as_register(); 1645 Register klass_RInfo = op->tmp2()->as_register(); 1646 Register dst = op->result_opr()->as_register(); 1647 ciKlass* k = op->klass(); 1648 Register Rtmp1 = noreg; 1649 1650 // check if it needs to be profiled 1651 ciMethodData* md = NULL; 1652 ciProfileData* data = NULL; 1653 1654 if (op->should_profile()) { 1655 ciMethod* method = op->profiled_method(); 1656 assert(method != NULL, "Should have method"); 1657 int bci = op->profiled_bci(); 1658 md = method->method_data_or_null(); 1659 assert(md != NULL, "Sanity"); 1660 data = md->bci_to_data(bci); 1661 assert(data != NULL, "need data for type check"); 1662 assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check"); 1663 } 1664 Label profile_cast_success, profile_cast_failure; 1665 Label *success_target = op->should_profile() ? &profile_cast_success : success; 1666 Label *failure_target = op->should_profile() ? &profile_cast_failure : failure; 1667 1668 if (obj == k_RInfo) { 1669 k_RInfo = dst; 1670 } else if (obj == klass_RInfo) { 1671 klass_RInfo = dst; 1672 } 1673 if (k->is_loaded() && !UseCompressedClassPointers) { 1674 select_different_registers(obj, dst, k_RInfo, klass_RInfo); 1675 } else { 1676 Rtmp1 = op->tmp3()->as_register(); 1677 select_different_registers(obj, dst, k_RInfo, klass_RInfo, Rtmp1); 1678 } 1679 1680 assert_different_registers(obj, k_RInfo, klass_RInfo); 1681 1682 if (op->need_null_check()) { 1683 __ cmpptr(obj, (int32_t)NULL_WORD); 1684 if (op->should_profile()) { 1685 Label not_null; 1686 __ jccb(Assembler::notEqual, not_null); 1687 // Object is null; update MDO and exit 1688 Register mdo = klass_RInfo; 1689 __ mov_metadata(mdo, md->constant_encoding()); 1690 Address data_addr(mdo, md->byte_offset_of_slot(data, DataLayout::flags_offset())); 1691 int header_bits = BitData::null_seen_byte_constant(); 1692 __ orb(data_addr, header_bits); 1693 __ jmp(*obj_is_null); 1694 __ bind(not_null); 1695 } else { 1696 __ jcc(Assembler::equal, *obj_is_null); 1697 } 1698 } 1699 1700 if (!k->is_loaded()) { 1701 klass2reg_with_patching(k_RInfo, op->info_for_patch()); 1702 } else { 1703 #ifdef _LP64 1704 __ mov_metadata(k_RInfo, k->constant_encoding()); 1705 #endif // _LP64 1706 } 1707 __ verify_oop(obj); 1708 1709 if (op->fast_check()) { 1710 // get object class 1711 // not a safepoint as obj null check happens earlier 1712 #ifdef _LP64 1713 if (UseCompressedClassPointers) { 1714 __ load_klass(Rtmp1, obj); 1715 __ cmpptr(k_RInfo, Rtmp1); 1716 } else { 1717 __ cmpptr(k_RInfo, Address(obj, oopDesc::klass_offset_in_bytes())); 1718 } 1719 #else 1720 if (k->is_loaded()) { 1721 __ cmpklass(Address(obj, oopDesc::klass_offset_in_bytes()), k->constant_encoding()); 1722 } else { 1723 __ cmpptr(k_RInfo, Address(obj, oopDesc::klass_offset_in_bytes())); 1724 } 1725 #endif 1726 __ jcc(Assembler::notEqual, *failure_target); 1727 // successful cast, fall through to profile or jump 1728 } else { 1729 // get object class 1730 // not a safepoint as obj null check happens earlier 1731 __ load_klass(klass_RInfo, obj); 1732 if (k->is_loaded()) { 1733 // See if we get an immediate positive hit 1734 #ifdef _LP64 1735 __ cmpptr(k_RInfo, Address(klass_RInfo, k->super_check_offset())); 1736 #else 1737 __ cmpklass(Address(klass_RInfo, k->super_check_offset()), k->constant_encoding()); 1738 #endif // _LP64 1739 if ((juint)in_bytes(Klass::secondary_super_cache_offset()) != k->super_check_offset()) { 1740 __ jcc(Assembler::notEqual, *failure_target); 1741 // successful cast, fall through to profile or jump 1742 } else { 1743 // See if we get an immediate positive hit 1744 __ jcc(Assembler::equal, *success_target); 1745 // check for self 1746 #ifdef _LP64 1747 __ cmpptr(klass_RInfo, k_RInfo); 1748 #else 1749 __ cmpklass(klass_RInfo, k->constant_encoding()); 1750 #endif // _LP64 1751 __ jcc(Assembler::equal, *success_target); 1752 1753 __ push(klass_RInfo); 1754 #ifdef _LP64 1755 __ push(k_RInfo); 1756 #else 1757 __ pushklass(k->constant_encoding()); 1758 #endif // _LP64 1759 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id))); 1760 __ pop(klass_RInfo); 1761 __ pop(klass_RInfo); 1762 // result is a boolean 1763 __ cmpl(klass_RInfo, 0); 1764 __ jcc(Assembler::equal, *failure_target); 1765 // successful cast, fall through to profile or jump 1766 } 1767 } else { 1768 // perform the fast part of the checking logic 1769 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, success_target, failure_target, NULL); 1770 // call out-of-line instance of __ check_klass_subtype_slow_path(...): 1771 __ push(klass_RInfo); 1772 __ push(k_RInfo); 1773 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id))); 1774 __ pop(klass_RInfo); 1775 __ pop(k_RInfo); 1776 // result is a boolean 1777 __ cmpl(k_RInfo, 0); 1778 __ jcc(Assembler::equal, *failure_target); 1779 // successful cast, fall through to profile or jump 1780 } 1781 } 1782 if (op->should_profile()) { 1783 Register mdo = klass_RInfo, recv = k_RInfo; 1784 __ bind(profile_cast_success); 1785 __ mov_metadata(mdo, md->constant_encoding()); 1786 __ load_klass(recv, obj); 1787 type_profile_helper(mdo, md, data, recv, success); 1788 __ jmp(*success); 1789 1790 __ bind(profile_cast_failure); 1791 __ mov_metadata(mdo, md->constant_encoding()); 1792 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset())); 1793 __ subptr(counter_addr, DataLayout::counter_increment); 1794 __ jmp(*failure); 1795 } 1796 __ jmp(*success); 1797 } 1798 1799 1800 void LIR_Assembler::emit_opTypeCheck(LIR_OpTypeCheck* op) { 1801 LIR_Code code = op->code(); 1802 if (code == lir_store_check) { 1803 Register value = op->object()->as_register(); 1804 Register array = op->array()->as_register(); 1805 Register k_RInfo = op->tmp1()->as_register(); 1806 Register klass_RInfo = op->tmp2()->as_register(); 1807 Register Rtmp1 = op->tmp3()->as_register(); 1808 1809 CodeStub* stub = op->stub(); 1810 1811 // check if it needs to be profiled 1812 ciMethodData* md = NULL; 1813 ciProfileData* data = NULL; 1814 1815 if (op->should_profile()) { 1816 ciMethod* method = op->profiled_method(); 1817 assert(method != NULL, "Should have method"); 1818 int bci = op->profiled_bci(); 1819 md = method->method_data_or_null(); 1820 assert(md != NULL, "Sanity"); 1821 data = md->bci_to_data(bci); 1822 assert(data != NULL, "need data for type check"); 1823 assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check"); 1824 } 1825 Label profile_cast_success, profile_cast_failure, done; 1826 Label *success_target = op->should_profile() ? &profile_cast_success : &done; 1827 Label *failure_target = op->should_profile() ? &profile_cast_failure : stub->entry(); 1828 1829 __ cmpptr(value, (int32_t)NULL_WORD); 1830 if (op->should_profile()) { 1831 Label not_null; 1832 __ jccb(Assembler::notEqual, not_null); 1833 // Object is null; update MDO and exit 1834 Register mdo = klass_RInfo; 1835 __ mov_metadata(mdo, md->constant_encoding()); 1836 Address data_addr(mdo, md->byte_offset_of_slot(data, DataLayout::flags_offset())); 1837 int header_bits = BitData::null_seen_byte_constant(); 1838 __ orb(data_addr, header_bits); 1839 __ jmp(done); 1840 __ bind(not_null); 1841 } else { 1842 __ jcc(Assembler::equal, done); 1843 } 1844 1845 add_debug_info_for_null_check_here(op->info_for_exception()); 1846 __ load_klass(k_RInfo, array); 1847 __ load_klass(klass_RInfo, value); 1848 1849 // get instance klass (it's already uncompressed) 1850 __ movptr(k_RInfo, Address(k_RInfo, ObjArrayKlass::element_klass_offset())); 1851 // perform the fast part of the checking logic 1852 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, success_target, failure_target, NULL); 1853 // call out-of-line instance of __ check_klass_subtype_slow_path(...): 1854 __ push(klass_RInfo); 1855 __ push(k_RInfo); 1856 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id))); 1857 __ pop(klass_RInfo); 1858 __ pop(k_RInfo); 1859 // result is a boolean 1860 __ cmpl(k_RInfo, 0); 1861 __ jcc(Assembler::equal, *failure_target); 1862 // fall through to the success case 1863 1864 if (op->should_profile()) { 1865 Register mdo = klass_RInfo, recv = k_RInfo; 1866 __ bind(profile_cast_success); 1867 __ mov_metadata(mdo, md->constant_encoding()); 1868 __ load_klass(recv, value); 1869 type_profile_helper(mdo, md, data, recv, &done); 1870 __ jmpb(done); 1871 1872 __ bind(profile_cast_failure); 1873 __ mov_metadata(mdo, md->constant_encoding()); 1874 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset())); 1875 __ subptr(counter_addr, DataLayout::counter_increment); 1876 __ jmp(*stub->entry()); 1877 } 1878 1879 __ bind(done); 1880 } else 1881 if (code == lir_checkcast) { 1882 Register obj = op->object()->as_register(); 1883 Register dst = op->result_opr()->as_register(); 1884 Label success; 1885 emit_typecheck_helper(op, &success, op->stub()->entry(), &success); 1886 __ bind(success); 1887 if (dst != obj) { 1888 __ mov(dst, obj); 1889 } 1890 } else 1891 if (code == lir_instanceof) { 1892 Register obj = op->object()->as_register(); 1893 Register dst = op->result_opr()->as_register(); 1894 Label success, failure, done; 1895 emit_typecheck_helper(op, &success, &failure, &failure); 1896 __ bind(failure); 1897 __ xorptr(dst, dst); 1898 __ jmpb(done); 1899 __ bind(success); 1900 __ movptr(dst, 1); 1901 __ bind(done); 1902 } else { 1903 ShouldNotReachHere(); 1904 } 1905 1906 } 1907 1908 1909 void LIR_Assembler::emit_compare_and_swap(LIR_OpCompareAndSwap* op) { 1910 if (LP64_ONLY(false &&) op->code() == lir_cas_long && VM_Version::supports_cx8()) { 1911 assert(op->cmp_value()->as_register_lo() == rax, "wrong register"); 1912 assert(op->cmp_value()->as_register_hi() == rdx, "wrong register"); 1913 assert(op->new_value()->as_register_lo() == rbx, "wrong register"); 1914 assert(op->new_value()->as_register_hi() == rcx, "wrong register"); 1915 Register addr = op->addr()->as_register(); 1916 __ lock(); 1917 NOT_LP64(__ cmpxchg8(Address(addr, 0))); 1918 1919 } else if (op->code() == lir_cas_int || op->code() == lir_cas_obj ) { 1920 NOT_LP64(assert(op->addr()->is_single_cpu(), "must be single");) 1921 Register addr = (op->addr()->is_single_cpu() ? op->addr()->as_register() : op->addr()->as_register_lo()); 1922 Register newval = op->new_value()->as_register(); 1923 Register cmpval = op->cmp_value()->as_register(); 1924 assert(cmpval == rax, "wrong register"); 1925 assert(newval != NULL, "new val must be register"); 1926 assert(cmpval != newval, "cmp and new values must be in different registers"); 1927 assert(cmpval != addr, "cmp and addr must be in different registers"); 1928 assert(newval != addr, "new value and addr must be in different registers"); 1929 1930 if ( op->code() == lir_cas_obj) { 1931 #ifdef _LP64 1932 if (UseCompressedOops) { 1933 __ encode_heap_oop(cmpval); 1934 __ mov(rscratch1, newval); 1935 __ encode_heap_oop(rscratch1); 1936 __ lock(); 1937 // cmpval (rax) is implicitly used by this instruction 1938 __ cmpxchgl(rscratch1, Address(addr, 0)); 1939 } else 1940 #endif 1941 { 1942 __ lock(); 1943 __ cmpxchgptr(newval, Address(addr, 0)); 1944 } 1945 } else { 1946 assert(op->code() == lir_cas_int, "lir_cas_int expected"); 1947 __ lock(); 1948 __ cmpxchgl(newval, Address(addr, 0)); 1949 } 1950 #ifdef _LP64 1951 } else if (op->code() == lir_cas_long) { 1952 Register addr = (op->addr()->is_single_cpu() ? op->addr()->as_register() : op->addr()->as_register_lo()); 1953 Register newval = op->new_value()->as_register_lo(); 1954 Register cmpval = op->cmp_value()->as_register_lo(); 1955 assert(cmpval == rax, "wrong register"); 1956 assert(newval != NULL, "new val must be register"); 1957 assert(cmpval != newval, "cmp and new values must be in different registers"); 1958 assert(cmpval != addr, "cmp and addr must be in different registers"); 1959 assert(newval != addr, "new value and addr must be in different registers"); 1960 __ lock(); 1961 __ cmpxchgq(newval, Address(addr, 0)); 1962 #endif // _LP64 1963 } else { 1964 Unimplemented(); 1965 } 1966 } 1967 1968 void LIR_Assembler::cmove(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Opr result, BasicType type) { 1969 Assembler::Condition acond, ncond; 1970 switch (condition) { 1971 case lir_cond_equal: acond = Assembler::equal; ncond = Assembler::notEqual; break; 1972 case lir_cond_notEqual: acond = Assembler::notEqual; ncond = Assembler::equal; break; 1973 case lir_cond_less: acond = Assembler::less; ncond = Assembler::greaterEqual; break; 1974 case lir_cond_lessEqual: acond = Assembler::lessEqual; ncond = Assembler::greater; break; 1975 case lir_cond_greaterEqual: acond = Assembler::greaterEqual; ncond = Assembler::less; break; 1976 case lir_cond_greater: acond = Assembler::greater; ncond = Assembler::lessEqual; break; 1977 case lir_cond_belowEqual: acond = Assembler::belowEqual; ncond = Assembler::above; break; 1978 case lir_cond_aboveEqual: acond = Assembler::aboveEqual; ncond = Assembler::below; break; 1979 default: acond = Assembler::equal; ncond = Assembler::notEqual; 1980 ShouldNotReachHere(); 1981 } 1982 1983 if (opr1->is_cpu_register()) { 1984 reg2reg(opr1, result); 1985 } else if (opr1->is_stack()) { 1986 stack2reg(opr1, result, result->type()); 1987 } else if (opr1->is_constant()) { 1988 const2reg(opr1, result, lir_patch_none, NULL); 1989 } else { 1990 ShouldNotReachHere(); 1991 } 1992 1993 if (VM_Version::supports_cmov() && !opr2->is_constant()) { 1994 // optimized version that does not require a branch 1995 if (opr2->is_single_cpu()) { 1996 assert(opr2->cpu_regnr() != result->cpu_regnr(), "opr2 already overwritten by previous move"); 1997 __ cmov(ncond, result->as_register(), opr2->as_register()); 1998 } else if (opr2->is_double_cpu()) { 1999 assert(opr2->cpu_regnrLo() != result->cpu_regnrLo() && opr2->cpu_regnrLo() != result->cpu_regnrHi(), "opr2 already overwritten by previous move"); 2000 assert(opr2->cpu_regnrHi() != result->cpu_regnrLo() && opr2->cpu_regnrHi() != result->cpu_regnrHi(), "opr2 already overwritten by previous move"); 2001 __ cmovptr(ncond, result->as_register_lo(), opr2->as_register_lo()); 2002 NOT_LP64(__ cmovptr(ncond, result->as_register_hi(), opr2->as_register_hi());) 2003 } else if (opr2->is_single_stack()) { 2004 __ cmovl(ncond, result->as_register(), frame_map()->address_for_slot(opr2->single_stack_ix())); 2005 } else if (opr2->is_double_stack()) { 2006 __ cmovptr(ncond, result->as_register_lo(), frame_map()->address_for_slot(opr2->double_stack_ix(), lo_word_offset_in_bytes)); 2007 NOT_LP64(__ cmovptr(ncond, result->as_register_hi(), frame_map()->address_for_slot(opr2->double_stack_ix(), hi_word_offset_in_bytes));) 2008 } else { 2009 ShouldNotReachHere(); 2010 } 2011 2012 } else { 2013 Label skip; 2014 __ jcc (acond, skip); 2015 if (opr2->is_cpu_register()) { 2016 reg2reg(opr2, result); 2017 } else if (opr2->is_stack()) { 2018 stack2reg(opr2, result, result->type()); 2019 } else if (opr2->is_constant()) { 2020 const2reg(opr2, result, lir_patch_none, NULL); 2021 } else { 2022 ShouldNotReachHere(); 2023 } 2024 __ bind(skip); 2025 } 2026 } 2027 2028 2029 void LIR_Assembler::arith_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest, CodeEmitInfo* info, bool pop_fpu_stack) { 2030 assert(info == NULL, "should never be used, idiv/irem and ldiv/lrem not handled by this method"); 2031 2032 if (left->is_single_cpu()) { 2033 assert(left == dest, "left and dest must be equal"); 2034 Register lreg = left->as_register(); 2035 2036 if (right->is_single_cpu()) { 2037 // cpu register - cpu register 2038 Register rreg = right->as_register(); 2039 switch (code) { 2040 case lir_add: __ addl (lreg, rreg); break; 2041 case lir_sub: __ subl (lreg, rreg); break; 2042 case lir_mul: __ imull(lreg, rreg); break; 2043 default: ShouldNotReachHere(); 2044 } 2045 2046 } else if (right->is_stack()) { 2047 // cpu register - stack 2048 Address raddr = frame_map()->address_for_slot(right->single_stack_ix()); 2049 switch (code) { 2050 case lir_add: __ addl(lreg, raddr); break; 2051 case lir_sub: __ subl(lreg, raddr); break; 2052 default: ShouldNotReachHere(); 2053 } 2054 2055 } else if (right->is_constant()) { 2056 // cpu register - constant 2057 jint c = right->as_constant_ptr()->as_jint(); 2058 switch (code) { 2059 case lir_add: { 2060 __ incrementl(lreg, c); 2061 break; 2062 } 2063 case lir_sub: { 2064 __ decrementl(lreg, c); 2065 break; 2066 } 2067 default: ShouldNotReachHere(); 2068 } 2069 2070 } else { 2071 ShouldNotReachHere(); 2072 } 2073 2074 } else if (left->is_double_cpu()) { 2075 assert(left == dest, "left and dest must be equal"); 2076 Register lreg_lo = left->as_register_lo(); 2077 Register lreg_hi = left->as_register_hi(); 2078 2079 if (right->is_double_cpu()) { 2080 // cpu register - cpu register 2081 Register rreg_lo = right->as_register_lo(); 2082 Register rreg_hi = right->as_register_hi(); 2083 NOT_LP64(assert_different_registers(lreg_lo, lreg_hi, rreg_lo, rreg_hi)); 2084 LP64_ONLY(assert_different_registers(lreg_lo, rreg_lo)); 2085 switch (code) { 2086 case lir_add: 2087 __ addptr(lreg_lo, rreg_lo); 2088 NOT_LP64(__ adcl(lreg_hi, rreg_hi)); 2089 break; 2090 case lir_sub: 2091 __ subptr(lreg_lo, rreg_lo); 2092 NOT_LP64(__ sbbl(lreg_hi, rreg_hi)); 2093 break; 2094 case lir_mul: 2095 #ifdef _LP64 2096 __ imulq(lreg_lo, rreg_lo); 2097 #else 2098 assert(lreg_lo == rax && lreg_hi == rdx, "must be"); 2099 __ imull(lreg_hi, rreg_lo); 2100 __ imull(rreg_hi, lreg_lo); 2101 __ addl (rreg_hi, lreg_hi); 2102 __ mull (rreg_lo); 2103 __ addl (lreg_hi, rreg_hi); 2104 #endif // _LP64 2105 break; 2106 default: 2107 ShouldNotReachHere(); 2108 } 2109 2110 } else if (right->is_constant()) { 2111 // cpu register - constant 2112 #ifdef _LP64 2113 jlong c = right->as_constant_ptr()->as_jlong_bits(); 2114 __ movptr(r10, (intptr_t) c); 2115 switch (code) { 2116 case lir_add: 2117 __ addptr(lreg_lo, r10); 2118 break; 2119 case lir_sub: 2120 __ subptr(lreg_lo, r10); 2121 break; 2122 default: 2123 ShouldNotReachHere(); 2124 } 2125 #else 2126 jint c_lo = right->as_constant_ptr()->as_jint_lo(); 2127 jint c_hi = right->as_constant_ptr()->as_jint_hi(); 2128 switch (code) { 2129 case lir_add: 2130 __ addptr(lreg_lo, c_lo); 2131 __ adcl(lreg_hi, c_hi); 2132 break; 2133 case lir_sub: 2134 __ subptr(lreg_lo, c_lo); 2135 __ sbbl(lreg_hi, c_hi); 2136 break; 2137 default: 2138 ShouldNotReachHere(); 2139 } 2140 #endif // _LP64 2141 2142 } else { 2143 ShouldNotReachHere(); 2144 } 2145 2146 } else if (left->is_single_xmm()) { 2147 assert(left == dest, "left and dest must be equal"); 2148 XMMRegister lreg = left->as_xmm_float_reg(); 2149 2150 if (right->is_single_xmm()) { 2151 XMMRegister rreg = right->as_xmm_float_reg(); 2152 switch (code) { 2153 case lir_add: __ addss(lreg, rreg); break; 2154 case lir_sub: __ subss(lreg, rreg); break; 2155 case lir_mul_strictfp: // fall through 2156 case lir_mul: __ mulss(lreg, rreg); break; 2157 case lir_div_strictfp: // fall through 2158 case lir_div: __ divss(lreg, rreg); break; 2159 default: ShouldNotReachHere(); 2160 } 2161 } else { 2162 Address raddr; 2163 if (right->is_single_stack()) { 2164 raddr = frame_map()->address_for_slot(right->single_stack_ix()); 2165 } else if (right->is_constant()) { 2166 // hack for now 2167 raddr = __ as_Address(InternalAddress(float_constant(right->as_jfloat()))); 2168 } else { 2169 ShouldNotReachHere(); 2170 } 2171 switch (code) { 2172 case lir_add: __ addss(lreg, raddr); break; 2173 case lir_sub: __ subss(lreg, raddr); break; 2174 case lir_mul_strictfp: // fall through 2175 case lir_mul: __ mulss(lreg, raddr); break; 2176 case lir_div_strictfp: // fall through 2177 case lir_div: __ divss(lreg, raddr); break; 2178 default: ShouldNotReachHere(); 2179 } 2180 } 2181 2182 } else if (left->is_double_xmm()) { 2183 assert(left == dest, "left and dest must be equal"); 2184 2185 XMMRegister lreg = left->as_xmm_double_reg(); 2186 if (right->is_double_xmm()) { 2187 XMMRegister rreg = right->as_xmm_double_reg(); 2188 switch (code) { 2189 case lir_add: __ addsd(lreg, rreg); break; 2190 case lir_sub: __ subsd(lreg, rreg); break; 2191 case lir_mul_strictfp: // fall through 2192 case lir_mul: __ mulsd(lreg, rreg); break; 2193 case lir_div_strictfp: // fall through 2194 case lir_div: __ divsd(lreg, rreg); break; 2195 default: ShouldNotReachHere(); 2196 } 2197 } else { 2198 Address raddr; 2199 if (right->is_double_stack()) { 2200 raddr = frame_map()->address_for_slot(right->double_stack_ix()); 2201 } else if (right->is_constant()) { 2202 // hack for now 2203 raddr = __ as_Address(InternalAddress(double_constant(right->as_jdouble()))); 2204 } else { 2205 ShouldNotReachHere(); 2206 } 2207 switch (code) { 2208 case lir_add: __ addsd(lreg, raddr); break; 2209 case lir_sub: __ subsd(lreg, raddr); break; 2210 case lir_mul_strictfp: // fall through 2211 case lir_mul: __ mulsd(lreg, raddr); break; 2212 case lir_div_strictfp: // fall through 2213 case lir_div: __ divsd(lreg, raddr); break; 2214 default: ShouldNotReachHere(); 2215 } 2216 } 2217 2218 } else if (left->is_single_fpu()) { 2219 assert(dest->is_single_fpu(), "fpu stack allocation required"); 2220 2221 if (right->is_single_fpu()) { 2222 arith_fpu_implementation(code, left->fpu_regnr(), right->fpu_regnr(), dest->fpu_regnr(), pop_fpu_stack); 2223 2224 } else { 2225 assert(left->fpu_regnr() == 0, "left must be on TOS"); 2226 assert(dest->fpu_regnr() == 0, "dest must be on TOS"); 2227 2228 Address raddr; 2229 if (right->is_single_stack()) { 2230 raddr = frame_map()->address_for_slot(right->single_stack_ix()); 2231 } else if (right->is_constant()) { 2232 address const_addr = float_constant(right->as_jfloat()); 2233 assert(const_addr != NULL, "incorrect float/double constant maintainance"); 2234 // hack for now 2235 raddr = __ as_Address(InternalAddress(const_addr)); 2236 } else { 2237 ShouldNotReachHere(); 2238 } 2239 2240 switch (code) { 2241 case lir_add: __ fadd_s(raddr); break; 2242 case lir_sub: __ fsub_s(raddr); break; 2243 case lir_mul_strictfp: // fall through 2244 case lir_mul: __ fmul_s(raddr); break; 2245 case lir_div_strictfp: // fall through 2246 case lir_div: __ fdiv_s(raddr); break; 2247 default: ShouldNotReachHere(); 2248 } 2249 } 2250 2251 } else if (left->is_double_fpu()) { 2252 assert(dest->is_double_fpu(), "fpu stack allocation required"); 2253 2254 if (code == lir_mul_strictfp || code == lir_div_strictfp) { 2255 // Double values require special handling for strictfp mul/div on x86 2256 __ fld_x(ExternalAddress(StubRoutines::addr_fpu_subnormal_bias1())); 2257 __ fmulp(left->fpu_regnrLo() + 1); 2258 } 2259 2260 if (right->is_double_fpu()) { 2261 arith_fpu_implementation(code, left->fpu_regnrLo(), right->fpu_regnrLo(), dest->fpu_regnrLo(), pop_fpu_stack); 2262 2263 } else { 2264 assert(left->fpu_regnrLo() == 0, "left must be on TOS"); 2265 assert(dest->fpu_regnrLo() == 0, "dest must be on TOS"); 2266 2267 Address raddr; 2268 if (right->is_double_stack()) { 2269 raddr = frame_map()->address_for_slot(right->double_stack_ix()); 2270 } else if (right->is_constant()) { 2271 // hack for now 2272 raddr = __ as_Address(InternalAddress(double_constant(right->as_jdouble()))); 2273 } else { 2274 ShouldNotReachHere(); 2275 } 2276 2277 switch (code) { 2278 case lir_add: __ fadd_d(raddr); break; 2279 case lir_sub: __ fsub_d(raddr); break; 2280 case lir_mul_strictfp: // fall through 2281 case lir_mul: __ fmul_d(raddr); break; 2282 case lir_div_strictfp: // fall through 2283 case lir_div: __ fdiv_d(raddr); break; 2284 default: ShouldNotReachHere(); 2285 } 2286 } 2287 2288 if (code == lir_mul_strictfp || code == lir_div_strictfp) { 2289 // Double values require special handling for strictfp mul/div on x86 2290 __ fld_x(ExternalAddress(StubRoutines::addr_fpu_subnormal_bias2())); 2291 __ fmulp(dest->fpu_regnrLo() + 1); 2292 } 2293 2294 } else if (left->is_single_stack() || left->is_address()) { 2295 assert(left == dest, "left and dest must be equal"); 2296 2297 Address laddr; 2298 if (left->is_single_stack()) { 2299 laddr = frame_map()->address_for_slot(left->single_stack_ix()); 2300 } else if (left->is_address()) { 2301 laddr = as_Address(left->as_address_ptr()); 2302 } else { 2303 ShouldNotReachHere(); 2304 } 2305 2306 if (right->is_single_cpu()) { 2307 Register rreg = right->as_register(); 2308 switch (code) { 2309 case lir_add: __ addl(laddr, rreg); break; 2310 case lir_sub: __ subl(laddr, rreg); break; 2311 default: ShouldNotReachHere(); 2312 } 2313 } else if (right->is_constant()) { 2314 jint c = right->as_constant_ptr()->as_jint(); 2315 switch (code) { 2316 case lir_add: { 2317 __ incrementl(laddr, c); 2318 break; 2319 } 2320 case lir_sub: { 2321 __ decrementl(laddr, c); 2322 break; 2323 } 2324 default: ShouldNotReachHere(); 2325 } 2326 } else { 2327 ShouldNotReachHere(); 2328 } 2329 2330 } else { 2331 ShouldNotReachHere(); 2332 } 2333 } 2334 2335 void LIR_Assembler::arith_fpu_implementation(LIR_Code code, int left_index, int right_index, int dest_index, bool pop_fpu_stack) { 2336 assert(pop_fpu_stack || (left_index == dest_index || right_index == dest_index), "invalid LIR"); 2337 assert(!pop_fpu_stack || (left_index - 1 == dest_index || right_index - 1 == dest_index), "invalid LIR"); 2338 assert(left_index == 0 || right_index == 0, "either must be on top of stack"); 2339 2340 bool left_is_tos = (left_index == 0); 2341 bool dest_is_tos = (dest_index == 0); 2342 int non_tos_index = (left_is_tos ? right_index : left_index); 2343 2344 switch (code) { 2345 case lir_add: 2346 if (pop_fpu_stack) __ faddp(non_tos_index); 2347 else if (dest_is_tos) __ fadd (non_tos_index); 2348 else __ fadda(non_tos_index); 2349 break; 2350 2351 case lir_sub: 2352 if (left_is_tos) { 2353 if (pop_fpu_stack) __ fsubrp(non_tos_index); 2354 else if (dest_is_tos) __ fsub (non_tos_index); 2355 else __ fsubra(non_tos_index); 2356 } else { 2357 if (pop_fpu_stack) __ fsubp (non_tos_index); 2358 else if (dest_is_tos) __ fsubr (non_tos_index); 2359 else __ fsuba (non_tos_index); 2360 } 2361 break; 2362 2363 case lir_mul_strictfp: // fall through 2364 case lir_mul: 2365 if (pop_fpu_stack) __ fmulp(non_tos_index); 2366 else if (dest_is_tos) __ fmul (non_tos_index); 2367 else __ fmula(non_tos_index); 2368 break; 2369 2370 case lir_div_strictfp: // fall through 2371 case lir_div: 2372 if (left_is_tos) { 2373 if (pop_fpu_stack) __ fdivrp(non_tos_index); 2374 else if (dest_is_tos) __ fdiv (non_tos_index); 2375 else __ fdivra(non_tos_index); 2376 } else { 2377 if (pop_fpu_stack) __ fdivp (non_tos_index); 2378 else if (dest_is_tos) __ fdivr (non_tos_index); 2379 else __ fdiva (non_tos_index); 2380 } 2381 break; 2382 2383 case lir_rem: 2384 assert(left_is_tos && dest_is_tos && right_index == 1, "must be guaranteed by FPU stack allocation"); 2385 __ fremr(noreg); 2386 break; 2387 2388 default: 2389 ShouldNotReachHere(); 2390 } 2391 } 2392 2393 2394 void LIR_Assembler::intrinsic_op(LIR_Code code, LIR_Opr value, LIR_Opr tmp, LIR_Opr dest, LIR_Op* op) { 2395 if (value->is_double_xmm()) { 2396 switch(code) { 2397 case lir_abs : 2398 { 2399 #ifdef _LP64 2400 if (UseAVX > 2 && !VM_Version::supports_avx512vl()) { 2401 assert(tmp->is_valid(), "need temporary"); 2402 __ vpandn(dest->as_xmm_double_reg(), tmp->as_xmm_double_reg(), value->as_xmm_double_reg(), 2); 2403 } else 2404 #endif 2405 { 2406 if (dest->as_xmm_double_reg() != value->as_xmm_double_reg()) { 2407 __ movdbl(dest->as_xmm_double_reg(), value->as_xmm_double_reg()); 2408 } 2409 assert(!tmp->is_valid(), "do not need temporary"); 2410 __ andpd(dest->as_xmm_double_reg(), 2411 ExternalAddress((address)double_signmask_pool)); 2412 } 2413 } 2414 break; 2415 2416 case lir_sqrt: __ sqrtsd(dest->as_xmm_double_reg(), value->as_xmm_double_reg()); break; 2417 // all other intrinsics are not available in the SSE instruction set, so FPU is used 2418 default : ShouldNotReachHere(); 2419 } 2420 2421 } else if (value->is_double_fpu()) { 2422 assert(value->fpu_regnrLo() == 0 && dest->fpu_regnrLo() == 0, "both must be on TOS"); 2423 switch(code) { 2424 case lir_abs : __ fabs() ; break; 2425 case lir_sqrt : __ fsqrt(); break; 2426 default : ShouldNotReachHere(); 2427 } 2428 } else { 2429 Unimplemented(); 2430 } 2431 } 2432 2433 void LIR_Assembler::logic_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst) { 2434 // assert(left->destroys_register(), "check"); 2435 if (left->is_single_cpu()) { 2436 Register reg = left->as_register(); 2437 if (right->is_constant()) { 2438 int val = right->as_constant_ptr()->as_jint(); 2439 switch (code) { 2440 case lir_logic_and: __ andl (reg, val); break; 2441 case lir_logic_or: __ orl (reg, val); break; 2442 case lir_logic_xor: __ xorl (reg, val); break; 2443 default: ShouldNotReachHere(); 2444 } 2445 } else if (right->is_stack()) { 2446 // added support for stack operands 2447 Address raddr = frame_map()->address_for_slot(right->single_stack_ix()); 2448 switch (code) { 2449 case lir_logic_and: __ andl (reg, raddr); break; 2450 case lir_logic_or: __ orl (reg, raddr); break; 2451 case lir_logic_xor: __ xorl (reg, raddr); break; 2452 default: ShouldNotReachHere(); 2453 } 2454 } else { 2455 Register rright = right->as_register(); 2456 switch (code) { 2457 case lir_logic_and: __ andptr (reg, rright); break; 2458 case lir_logic_or : __ orptr (reg, rright); break; 2459 case lir_logic_xor: __ xorptr (reg, rright); break; 2460 default: ShouldNotReachHere(); 2461 } 2462 } 2463 move_regs(reg, dst->as_register()); 2464 } else { 2465 Register l_lo = left->as_register_lo(); 2466 Register l_hi = left->as_register_hi(); 2467 if (right->is_constant()) { 2468 #ifdef _LP64 2469 __ mov64(rscratch1, right->as_constant_ptr()->as_jlong()); 2470 switch (code) { 2471 case lir_logic_and: 2472 __ andq(l_lo, rscratch1); 2473 break; 2474 case lir_logic_or: 2475 __ orq(l_lo, rscratch1); 2476 break; 2477 case lir_logic_xor: 2478 __ xorq(l_lo, rscratch1); 2479 break; 2480 default: ShouldNotReachHere(); 2481 } 2482 #else 2483 int r_lo = right->as_constant_ptr()->as_jint_lo(); 2484 int r_hi = right->as_constant_ptr()->as_jint_hi(); 2485 switch (code) { 2486 case lir_logic_and: 2487 __ andl(l_lo, r_lo); 2488 __ andl(l_hi, r_hi); 2489 break; 2490 case lir_logic_or: 2491 __ orl(l_lo, r_lo); 2492 __ orl(l_hi, r_hi); 2493 break; 2494 case lir_logic_xor: 2495 __ xorl(l_lo, r_lo); 2496 __ xorl(l_hi, r_hi); 2497 break; 2498 default: ShouldNotReachHere(); 2499 } 2500 #endif // _LP64 2501 } else { 2502 #ifdef _LP64 2503 Register r_lo; 2504 if (right->type() == T_OBJECT || right->type() == T_ARRAY || right->type() == T_VALUETYPE) { 2505 r_lo = right->as_register(); 2506 } else { 2507 r_lo = right->as_register_lo(); 2508 } 2509 #else 2510 Register r_lo = right->as_register_lo(); 2511 Register r_hi = right->as_register_hi(); 2512 assert(l_lo != r_hi, "overwriting registers"); 2513 #endif 2514 switch (code) { 2515 case lir_logic_and: 2516 __ andptr(l_lo, r_lo); 2517 NOT_LP64(__ andptr(l_hi, r_hi);) 2518 break; 2519 case lir_logic_or: 2520 __ orptr(l_lo, r_lo); 2521 NOT_LP64(__ orptr(l_hi, r_hi);) 2522 break; 2523 case lir_logic_xor: 2524 __ xorptr(l_lo, r_lo); 2525 NOT_LP64(__ xorptr(l_hi, r_hi);) 2526 break; 2527 default: ShouldNotReachHere(); 2528 } 2529 } 2530 2531 Register dst_lo = dst->as_register_lo(); 2532 Register dst_hi = dst->as_register_hi(); 2533 2534 #ifdef _LP64 2535 move_regs(l_lo, dst_lo); 2536 #else 2537 if (dst_lo == l_hi) { 2538 assert(dst_hi != l_lo, "overwriting registers"); 2539 move_regs(l_hi, dst_hi); 2540 move_regs(l_lo, dst_lo); 2541 } else { 2542 assert(dst_lo != l_hi, "overwriting registers"); 2543 move_regs(l_lo, dst_lo); 2544 move_regs(l_hi, dst_hi); 2545 } 2546 #endif // _LP64 2547 } 2548 } 2549 2550 2551 // we assume that rax, and rdx can be overwritten 2552 void LIR_Assembler::arithmetic_idiv(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr temp, LIR_Opr result, CodeEmitInfo* info) { 2553 2554 assert(left->is_single_cpu(), "left must be register"); 2555 assert(right->is_single_cpu() || right->is_constant(), "right must be register or constant"); 2556 assert(result->is_single_cpu(), "result must be register"); 2557 2558 // assert(left->destroys_register(), "check"); 2559 // assert(right->destroys_register(), "check"); 2560 2561 Register lreg = left->as_register(); 2562 Register dreg = result->as_register(); 2563 2564 if (right->is_constant()) { 2565 jint divisor = right->as_constant_ptr()->as_jint(); 2566 assert(divisor > 0 && is_power_of_2(divisor), "must be"); 2567 if (code == lir_idiv) { 2568 assert(lreg == rax, "must be rax,"); 2569 assert(temp->as_register() == rdx, "tmp register must be rdx"); 2570 __ cdql(); // sign extend into rdx:rax 2571 if (divisor == 2) { 2572 __ subl(lreg, rdx); 2573 } else { 2574 __ andl(rdx, divisor - 1); 2575 __ addl(lreg, rdx); 2576 } 2577 __ sarl(lreg, log2_jint(divisor)); 2578 move_regs(lreg, dreg); 2579 } else if (code == lir_irem) { 2580 Label done; 2581 __ mov(dreg, lreg); 2582 __ andl(dreg, 0x80000000 | (divisor - 1)); 2583 __ jcc(Assembler::positive, done); 2584 __ decrement(dreg); 2585 __ orl(dreg, ~(divisor - 1)); 2586 __ increment(dreg); 2587 __ bind(done); 2588 } else { 2589 ShouldNotReachHere(); 2590 } 2591 } else { 2592 Register rreg = right->as_register(); 2593 assert(lreg == rax, "left register must be rax,"); 2594 assert(rreg != rdx, "right register must not be rdx"); 2595 assert(temp->as_register() == rdx, "tmp register must be rdx"); 2596 2597 move_regs(lreg, rax); 2598 2599 int idivl_offset = __ corrected_idivl(rreg); 2600 if (ImplicitDiv0Checks) { 2601 add_debug_info_for_div0(idivl_offset, info); 2602 } 2603 if (code == lir_irem) { 2604 move_regs(rdx, dreg); // result is in rdx 2605 } else { 2606 move_regs(rax, dreg); 2607 } 2608 } 2609 } 2610 2611 2612 void LIR_Assembler::comp_op(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Op2* op) { 2613 if (opr1->is_single_cpu()) { 2614 Register reg1 = opr1->as_register(); 2615 if (opr2->is_single_cpu()) { 2616 // cpu register - cpu register 2617 if (opr1->type() == T_OBJECT || opr1->type() == T_ARRAY || opr1->type() == T_VALUETYPE) { 2618 __ cmpoop(reg1, opr2->as_register()); 2619 } else { 2620 assert(opr2->type() != T_OBJECT && opr2->type() != T_ARRAY && opr2->type() != T_VALUETYPE, "cmp int, oop?"); 2621 __ cmpl(reg1, opr2->as_register()); 2622 } 2623 } else if (opr2->is_stack()) { 2624 // cpu register - stack 2625 if (opr1->type() == T_OBJECT || opr1->type() == T_ARRAY || opr1->type() == T_VALUETYPE) { 2626 __ cmpoop(reg1, frame_map()->address_for_slot(opr2->single_stack_ix())); 2627 } else { 2628 __ cmpl(reg1, frame_map()->address_for_slot(opr2->single_stack_ix())); 2629 } 2630 } else if (opr2->is_constant()) { 2631 // cpu register - constant 2632 LIR_Const* c = opr2->as_constant_ptr(); 2633 if (c->type() == T_INT) { 2634 __ cmpl(reg1, c->as_jint()); 2635 } else if (c->type() == T_OBJECT || c->type() == T_ARRAY || c->type() == T_VALUETYPE) { 2636 // In 64bit oops are single register 2637 jobject o = c->as_jobject(); 2638 if (o == NULL) { 2639 __ cmpptr(reg1, (int32_t)NULL_WORD); 2640 } else { 2641 __ cmpoop(reg1, o); 2642 } 2643 } else { 2644 fatal("unexpected type: %s", basictype_to_str(c->type())); 2645 } 2646 // cpu register - address 2647 } else if (opr2->is_address()) { 2648 if (op->info() != NULL) { 2649 add_debug_info_for_null_check_here(op->info()); 2650 } 2651 __ cmpl(reg1, as_Address(opr2->as_address_ptr())); 2652 } else { 2653 ShouldNotReachHere(); 2654 } 2655 2656 } else if(opr1->is_double_cpu()) { 2657 Register xlo = opr1->as_register_lo(); 2658 Register xhi = opr1->as_register_hi(); 2659 if (opr2->is_double_cpu()) { 2660 #ifdef _LP64 2661 __ cmpptr(xlo, opr2->as_register_lo()); 2662 #else 2663 // cpu register - cpu register 2664 Register ylo = opr2->as_register_lo(); 2665 Register yhi = opr2->as_register_hi(); 2666 __ subl(xlo, ylo); 2667 __ sbbl(xhi, yhi); 2668 if (condition == lir_cond_equal || condition == lir_cond_notEqual) { 2669 __ orl(xhi, xlo); 2670 } 2671 #endif // _LP64 2672 } else if (opr2->is_constant()) { 2673 // cpu register - constant 0 2674 assert(opr2->as_jlong() == (jlong)0, "only handles zero"); 2675 #ifdef _LP64 2676 __ cmpptr(xlo, (int32_t)opr2->as_jlong()); 2677 #else 2678 assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "only handles equals case"); 2679 __ orl(xhi, xlo); 2680 #endif // _LP64 2681 } else { 2682 ShouldNotReachHere(); 2683 } 2684 2685 } else if (opr1->is_single_xmm()) { 2686 XMMRegister reg1 = opr1->as_xmm_float_reg(); 2687 if (opr2->is_single_xmm()) { 2688 // xmm register - xmm register 2689 __ ucomiss(reg1, opr2->as_xmm_float_reg()); 2690 } else if (opr2->is_stack()) { 2691 // xmm register - stack 2692 __ ucomiss(reg1, frame_map()->address_for_slot(opr2->single_stack_ix())); 2693 } else if (opr2->is_constant()) { 2694 // xmm register - constant 2695 __ ucomiss(reg1, InternalAddress(float_constant(opr2->as_jfloat()))); 2696 } else if (opr2->is_address()) { 2697 // xmm register - address 2698 if (op->info() != NULL) { 2699 add_debug_info_for_null_check_here(op->info()); 2700 } 2701 __ ucomiss(reg1, as_Address(opr2->as_address_ptr())); 2702 } else { 2703 ShouldNotReachHere(); 2704 } 2705 2706 } else if (opr1->is_double_xmm()) { 2707 XMMRegister reg1 = opr1->as_xmm_double_reg(); 2708 if (opr2->is_double_xmm()) { 2709 // xmm register - xmm register 2710 __ ucomisd(reg1, opr2->as_xmm_double_reg()); 2711 } else if (opr2->is_stack()) { 2712 // xmm register - stack 2713 __ ucomisd(reg1, frame_map()->address_for_slot(opr2->double_stack_ix())); 2714 } else if (opr2->is_constant()) { 2715 // xmm register - constant 2716 __ ucomisd(reg1, InternalAddress(double_constant(opr2->as_jdouble()))); 2717 } else if (opr2->is_address()) { 2718 // xmm register - address 2719 if (op->info() != NULL) { 2720 add_debug_info_for_null_check_here(op->info()); 2721 } 2722 __ ucomisd(reg1, as_Address(opr2->pointer()->as_address())); 2723 } else { 2724 ShouldNotReachHere(); 2725 } 2726 2727 } else if(opr1->is_single_fpu() || opr1->is_double_fpu()) { 2728 assert(opr1->is_fpu_register() && opr1->fpu() == 0, "currently left-hand side must be on TOS (relax this restriction)"); 2729 assert(opr2->is_fpu_register(), "both must be registers"); 2730 __ fcmp(noreg, opr2->fpu(), op->fpu_pop_count() > 0, op->fpu_pop_count() > 1); 2731 2732 } else if (opr1->is_address() && opr2->is_constant()) { 2733 LIR_Const* c = opr2->as_constant_ptr(); 2734 #ifdef _LP64 2735 if (c->type() == T_OBJECT || c->type() == T_ARRAY || c->type() == T_VALUETYPE) { 2736 assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "need to reverse"); 2737 __ movoop(rscratch1, c->as_jobject()); 2738 } 2739 #endif // LP64 2740 if (op->info() != NULL) { 2741 add_debug_info_for_null_check_here(op->info()); 2742 } 2743 // special case: address - constant 2744 LIR_Address* addr = opr1->as_address_ptr(); 2745 if (c->type() == T_INT) { 2746 __ cmpl(as_Address(addr), c->as_jint()); 2747 } else if (c->type() == T_OBJECT || c->type() == T_ARRAY || c->type() == T_VALUETYPE) { 2748 #ifdef _LP64 2749 // %%% Make this explode if addr isn't reachable until we figure out a 2750 // better strategy by giving noreg as the temp for as_Address 2751 __ cmpoop(rscratch1, as_Address(addr, noreg)); 2752 #else 2753 __ cmpoop(as_Address(addr), c->as_jobject()); 2754 #endif // _LP64 2755 } else { 2756 ShouldNotReachHere(); 2757 } 2758 2759 } else { 2760 ShouldNotReachHere(); 2761 } 2762 } 2763 2764 void LIR_Assembler::comp_fl2i(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst, LIR_Op2* op) { 2765 if (code == lir_cmp_fd2i || code == lir_ucmp_fd2i) { 2766 if (left->is_single_xmm()) { 2767 assert(right->is_single_xmm(), "must match"); 2768 __ cmpss2int(left->as_xmm_float_reg(), right->as_xmm_float_reg(), dst->as_register(), code == lir_ucmp_fd2i); 2769 } else if (left->is_double_xmm()) { 2770 assert(right->is_double_xmm(), "must match"); 2771 __ cmpsd2int(left->as_xmm_double_reg(), right->as_xmm_double_reg(), dst->as_register(), code == lir_ucmp_fd2i); 2772 2773 } else { 2774 assert(left->is_single_fpu() || left->is_double_fpu(), "must be"); 2775 assert(right->is_single_fpu() || right->is_double_fpu(), "must match"); 2776 2777 assert(left->fpu() == 0, "left must be on TOS"); 2778 __ fcmp2int(dst->as_register(), code == lir_ucmp_fd2i, right->fpu(), 2779 op->fpu_pop_count() > 0, op->fpu_pop_count() > 1); 2780 } 2781 } else { 2782 assert(code == lir_cmp_l2i, "check"); 2783 #ifdef _LP64 2784 Label done; 2785 Register dest = dst->as_register(); 2786 __ cmpptr(left->as_register_lo(), right->as_register_lo()); 2787 __ movl(dest, -1); 2788 __ jccb(Assembler::less, done); 2789 __ set_byte_if_not_zero(dest); 2790 __ movzbl(dest, dest); 2791 __ bind(done); 2792 #else 2793 __ lcmp2int(left->as_register_hi(), 2794 left->as_register_lo(), 2795 right->as_register_hi(), 2796 right->as_register_lo()); 2797 move_regs(left->as_register_hi(), dst->as_register()); 2798 #endif // _LP64 2799 } 2800 } 2801 2802 2803 void LIR_Assembler::align_call(LIR_Code code) { 2804 // make sure that the displacement word of the call ends up word aligned 2805 int offset = __ offset(); 2806 switch (code) { 2807 case lir_static_call: 2808 case lir_optvirtual_call: 2809 case lir_dynamic_call: 2810 offset += NativeCall::displacement_offset; 2811 break; 2812 case lir_icvirtual_call: 2813 offset += NativeCall::displacement_offset + NativeMovConstReg::instruction_size; 2814 break; 2815 case lir_virtual_call: // currently, sparc-specific for niagara 2816 default: ShouldNotReachHere(); 2817 } 2818 __ align(BytesPerWord, offset); 2819 } 2820 2821 2822 void LIR_Assembler::call(LIR_OpJavaCall* op, relocInfo::relocType rtype) { 2823 assert((__ offset() + NativeCall::displacement_offset) % BytesPerWord == 0, 2824 "must be aligned"); 2825 __ call(AddressLiteral(op->addr(), rtype)); 2826 add_call_info(code_offset(), op->info()); 2827 } 2828 2829 2830 void LIR_Assembler::ic_call(LIR_OpJavaCall* op) { 2831 __ ic_call(op->addr()); 2832 add_call_info(code_offset(), op->info()); 2833 assert((__ offset() - NativeCall::instruction_size + NativeCall::displacement_offset) % BytesPerWord == 0, 2834 "must be aligned"); 2835 } 2836 2837 2838 /* Currently, vtable-dispatch is only enabled for sparc platforms */ 2839 void LIR_Assembler::vtable_call(LIR_OpJavaCall* op) { 2840 ShouldNotReachHere(); 2841 } 2842 2843 2844 void LIR_Assembler::emit_static_call_stub() { 2845 address call_pc = __ pc(); 2846 address stub = __ start_a_stub(call_stub_size()); 2847 if (stub == NULL) { 2848 bailout("static call stub overflow"); 2849 return; 2850 } 2851 2852 int start = __ offset(); 2853 2854 // make sure that the displacement word of the call ends up word aligned 2855 __ align(BytesPerWord, __ offset() + NativeMovConstReg::instruction_size + NativeCall::displacement_offset); 2856 __ relocate(static_stub_Relocation::spec(call_pc, false /* is_aot */)); 2857 __ mov_metadata(rbx, (Metadata*)NULL); 2858 // must be set to -1 at code generation time 2859 assert(((__ offset() + 1) % BytesPerWord) == 0, "must be aligned"); 2860 // On 64bit this will die since it will take a movq & jmp, must be only a jmp 2861 __ jump(RuntimeAddress(__ pc())); 2862 2863 if (UseAOT) { 2864 // Trampoline to aot code 2865 __ relocate(static_stub_Relocation::spec(call_pc, true /* is_aot */)); 2866 #ifdef _LP64 2867 __ mov64(rax, CONST64(0)); // address is zapped till fixup time. 2868 #else 2869 __ movl(rax, 0xdeadffff); // address is zapped till fixup time. 2870 #endif 2871 __ jmp(rax); 2872 } 2873 assert(__ offset() - start <= call_stub_size(), "stub too big"); 2874 __ end_a_stub(); 2875 } 2876 2877 2878 void LIR_Assembler::throw_op(LIR_Opr exceptionPC, LIR_Opr exceptionOop, CodeEmitInfo* info) { 2879 assert(exceptionOop->as_register() == rax, "must match"); 2880 assert(exceptionPC->as_register() == rdx, "must match"); 2881 2882 // exception object is not added to oop map by LinearScan 2883 // (LinearScan assumes that no oops are in fixed registers) 2884 info->add_register_oop(exceptionOop); 2885 Runtime1::StubID unwind_id; 2886 2887 // get current pc information 2888 // pc is only needed if the method has an exception handler, the unwind code does not need it. 2889 int pc_for_athrow_offset = __ offset(); 2890 InternalAddress pc_for_athrow(__ pc()); 2891 __ lea(exceptionPC->as_register(), pc_for_athrow); 2892 add_call_info(pc_for_athrow_offset, info); // for exception handler 2893 2894 __ verify_not_null_oop(rax); 2895 // search an exception handler (rax: exception oop, rdx: throwing pc) 2896 if (compilation()->has_fpu_code()) { 2897 unwind_id = Runtime1::handle_exception_id; 2898 } else { 2899 unwind_id = Runtime1::handle_exception_nofpu_id; 2900 } 2901 __ call(RuntimeAddress(Runtime1::entry_for(unwind_id))); 2902 2903 // enough room for two byte trap 2904 __ nop(); 2905 } 2906 2907 2908 void LIR_Assembler::unwind_op(LIR_Opr exceptionOop) { 2909 assert(exceptionOop->as_register() == rax, "must match"); 2910 2911 __ jmp(_unwind_handler_entry); 2912 } 2913 2914 2915 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, LIR_Opr count, LIR_Opr dest, LIR_Opr tmp) { 2916 2917 // optimized version for linear scan: 2918 // * count must be already in ECX (guaranteed by LinearScan) 2919 // * left and dest must be equal 2920 // * tmp must be unused 2921 assert(count->as_register() == SHIFT_count, "count must be in ECX"); 2922 assert(left == dest, "left and dest must be equal"); 2923 assert(tmp->is_illegal(), "wasting a register if tmp is allocated"); 2924 2925 if (left->is_single_cpu()) { 2926 Register value = left->as_register(); 2927 assert(value != SHIFT_count, "left cannot be ECX"); 2928 2929 switch (code) { 2930 case lir_shl: __ shll(value); break; 2931 case lir_shr: __ sarl(value); break; 2932 case lir_ushr: __ shrl(value); break; 2933 default: ShouldNotReachHere(); 2934 } 2935 } else if (left->is_double_cpu()) { 2936 Register lo = left->as_register_lo(); 2937 Register hi = left->as_register_hi(); 2938 assert(lo != SHIFT_count && hi != SHIFT_count, "left cannot be ECX"); 2939 #ifdef _LP64 2940 switch (code) { 2941 case lir_shl: __ shlptr(lo); break; 2942 case lir_shr: __ sarptr(lo); break; 2943 case lir_ushr: __ shrptr(lo); break; 2944 default: ShouldNotReachHere(); 2945 } 2946 #else 2947 2948 switch (code) { 2949 case lir_shl: __ lshl(hi, lo); break; 2950 case lir_shr: __ lshr(hi, lo, true); break; 2951 case lir_ushr: __ lshr(hi, lo, false); break; 2952 default: ShouldNotReachHere(); 2953 } 2954 #endif // LP64 2955 } else { 2956 ShouldNotReachHere(); 2957 } 2958 } 2959 2960 2961 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, jint count, LIR_Opr dest) { 2962 if (dest->is_single_cpu()) { 2963 // first move left into dest so that left is not destroyed by the shift 2964 Register value = dest->as_register(); 2965 count = count & 0x1F; // Java spec 2966 2967 move_regs(left->as_register(), value); 2968 switch (code) { 2969 case lir_shl: __ shll(value, count); break; 2970 case lir_shr: __ sarl(value, count); break; 2971 case lir_ushr: __ shrl(value, count); break; 2972 default: ShouldNotReachHere(); 2973 } 2974 } else if (dest->is_double_cpu()) { 2975 #ifndef _LP64 2976 Unimplemented(); 2977 #else 2978 // first move left into dest so that left is not destroyed by the shift 2979 Register value = dest->as_register_lo(); 2980 count = count & 0x1F; // Java spec 2981 2982 move_regs(left->as_register_lo(), value); 2983 switch (code) { 2984 case lir_shl: __ shlptr(value, count); break; 2985 case lir_shr: __ sarptr(value, count); break; 2986 case lir_ushr: __ shrptr(value, count); break; 2987 default: ShouldNotReachHere(); 2988 } 2989 #endif // _LP64 2990 } else { 2991 ShouldNotReachHere(); 2992 } 2993 } 2994 2995 2996 void LIR_Assembler::store_parameter(Register r, int offset_from_rsp_in_words) { 2997 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp"); 2998 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord; 2999 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset"); 3000 __ movptr (Address(rsp, offset_from_rsp_in_bytes), r); 3001 } 3002 3003 3004 void LIR_Assembler::store_parameter(jint c, int offset_from_rsp_in_words) { 3005 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp"); 3006 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord; 3007 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset"); 3008 __ movptr (Address(rsp, offset_from_rsp_in_bytes), c); 3009 } 3010 3011 3012 void LIR_Assembler::store_parameter(jobject o, int offset_from_rsp_in_words) { 3013 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp"); 3014 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord; 3015 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset"); 3016 __ movoop (Address(rsp, offset_from_rsp_in_bytes), o); 3017 } 3018 3019 3020 void LIR_Assembler::store_parameter(Metadata* m, int offset_from_rsp_in_words) { 3021 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp"); 3022 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord; 3023 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset"); 3024 __ mov_metadata(Address(rsp, offset_from_rsp_in_bytes), m); 3025 } 3026 3027 3028 // This code replaces a call to arraycopy; no exception may 3029 // be thrown in this code, they must be thrown in the System.arraycopy 3030 // activation frame; we could save some checks if this would not be the case 3031 void LIR_Assembler::emit_arraycopy(LIR_OpArrayCopy* op) { 3032 ciArrayKlass* default_type = op->expected_type(); 3033 Register src = op->src()->as_register(); 3034 Register dst = op->dst()->as_register(); 3035 Register src_pos = op->src_pos()->as_register(); 3036 Register dst_pos = op->dst_pos()->as_register(); 3037 Register length = op->length()->as_register(); 3038 Register tmp = op->tmp()->as_register(); 3039 3040 __ resolve(ACCESS_READ, src); 3041 __ resolve(ACCESS_WRITE, dst); 3042 3043 CodeStub* stub = op->stub(); 3044 int flags = op->flags(); 3045 BasicType basic_type = default_type != NULL ? default_type->element_type()->basic_type() : T_ILLEGAL; 3046 if (basic_type == T_ARRAY) basic_type = T_OBJECT; 3047 3048 // if we don't know anything, just go through the generic arraycopy 3049 if (default_type == NULL) { 3050 // save outgoing arguments on stack in case call to System.arraycopy is needed 3051 // HACK ALERT. This code used to push the parameters in a hardwired fashion 3052 // for interpreter calling conventions. Now we have to do it in new style conventions. 3053 // For the moment until C1 gets the new register allocator I just force all the 3054 // args to the right place (except the register args) and then on the back side 3055 // reload the register args properly if we go slow path. Yuck 3056 3057 // These are proper for the calling convention 3058 store_parameter(length, 2); 3059 store_parameter(dst_pos, 1); 3060 store_parameter(dst, 0); 3061 3062 // these are just temporary placements until we need to reload 3063 store_parameter(src_pos, 3); 3064 store_parameter(src, 4); 3065 NOT_LP64(assert(src == rcx && src_pos == rdx, "mismatch in calling convention");) 3066 3067 address copyfunc_addr = StubRoutines::generic_arraycopy(); 3068 assert(copyfunc_addr != NULL, "generic arraycopy stub required"); 3069 3070 // pass arguments: may push as this is not a safepoint; SP must be fix at each safepoint 3071 #ifdef _LP64 3072 // The arguments are in java calling convention so we can trivially shift them to C 3073 // convention 3074 assert_different_registers(c_rarg0, j_rarg1, j_rarg2, j_rarg3, j_rarg4); 3075 __ mov(c_rarg0, j_rarg0); 3076 assert_different_registers(c_rarg1, j_rarg2, j_rarg3, j_rarg4); 3077 __ mov(c_rarg1, j_rarg1); 3078 assert_different_registers(c_rarg2, j_rarg3, j_rarg4); 3079 __ mov(c_rarg2, j_rarg2); 3080 assert_different_registers(c_rarg3, j_rarg4); 3081 __ mov(c_rarg3, j_rarg3); 3082 #ifdef _WIN64 3083 // Allocate abi space for args but be sure to keep stack aligned 3084 __ subptr(rsp, 6*wordSize); 3085 store_parameter(j_rarg4, 4); 3086 #ifndef PRODUCT 3087 if (PrintC1Statistics) { 3088 __ incrementl(ExternalAddress((address)&Runtime1::_generic_arraycopystub_cnt)); 3089 } 3090 #endif 3091 __ call(RuntimeAddress(copyfunc_addr)); 3092 __ addptr(rsp, 6*wordSize); 3093 #else 3094 __ mov(c_rarg4, j_rarg4); 3095 #ifndef PRODUCT 3096 if (PrintC1Statistics) { 3097 __ incrementl(ExternalAddress((address)&Runtime1::_generic_arraycopystub_cnt)); 3098 } 3099 #endif 3100 __ call(RuntimeAddress(copyfunc_addr)); 3101 #endif // _WIN64 3102 #else 3103 __ push(length); 3104 __ push(dst_pos); 3105 __ push(dst); 3106 __ push(src_pos); 3107 __ push(src); 3108 3109 #ifndef PRODUCT 3110 if (PrintC1Statistics) { 3111 __ incrementl(ExternalAddress((address)&Runtime1::_generic_arraycopystub_cnt)); 3112 } 3113 #endif 3114 __ call_VM_leaf(copyfunc_addr, 5); // removes pushed parameter from the stack 3115 3116 #endif // _LP64 3117 3118 __ cmpl(rax, 0); 3119 __ jcc(Assembler::equal, *stub->continuation()); 3120 3121 __ mov(tmp, rax); 3122 __ xorl(tmp, -1); 3123 3124 // Reload values from the stack so they are where the stub 3125 // expects them. 3126 __ movptr (dst, Address(rsp, 0*BytesPerWord)); 3127 __ movptr (dst_pos, Address(rsp, 1*BytesPerWord)); 3128 __ movptr (length, Address(rsp, 2*BytesPerWord)); 3129 __ movptr (src_pos, Address(rsp, 3*BytesPerWord)); 3130 __ movptr (src, Address(rsp, 4*BytesPerWord)); 3131 3132 __ subl(length, tmp); 3133 __ addl(src_pos, tmp); 3134 __ addl(dst_pos, tmp); 3135 __ jmp(*stub->entry()); 3136 3137 __ bind(*stub->continuation()); 3138 return; 3139 } 3140 3141 assert(default_type != NULL && default_type->is_array_klass() && default_type->is_loaded(), "must be true at this point"); 3142 3143 int elem_size = type2aelembytes(basic_type); 3144 Address::ScaleFactor scale; 3145 3146 switch (elem_size) { 3147 case 1 : 3148 scale = Address::times_1; 3149 break; 3150 case 2 : 3151 scale = Address::times_2; 3152 break; 3153 case 4 : 3154 scale = Address::times_4; 3155 break; 3156 case 8 : 3157 scale = Address::times_8; 3158 break; 3159 default: 3160 scale = Address::no_scale; 3161 ShouldNotReachHere(); 3162 } 3163 3164 Address src_length_addr = Address(src, arrayOopDesc::length_offset_in_bytes()); 3165 Address dst_length_addr = Address(dst, arrayOopDesc::length_offset_in_bytes()); 3166 Address src_klass_addr = Address(src, oopDesc::klass_offset_in_bytes()); 3167 Address dst_klass_addr = Address(dst, oopDesc::klass_offset_in_bytes()); 3168 3169 // length and pos's are all sign extended at this point on 64bit 3170 3171 // test for NULL 3172 if (flags & LIR_OpArrayCopy::src_null_check) { 3173 __ testptr(src, src); 3174 __ jcc(Assembler::zero, *stub->entry()); 3175 } 3176 if (flags & LIR_OpArrayCopy::dst_null_check) { 3177 __ testptr(dst, dst); 3178 __ jcc(Assembler::zero, *stub->entry()); 3179 } 3180 3181 // If the compiler was not able to prove that exact type of the source or the destination 3182 // of the arraycopy is an array type, check at runtime if the source or the destination is 3183 // an instance type. 3184 if (flags & LIR_OpArrayCopy::type_check) { 3185 if (!(flags & LIR_OpArrayCopy::dst_objarray)) { 3186 __ load_klass(tmp, dst); 3187 __ cmpl(Address(tmp, in_bytes(Klass::layout_helper_offset())), Klass::_lh_neutral_value); 3188 __ jcc(Assembler::greaterEqual, *stub->entry()); 3189 } 3190 3191 if (!(flags & LIR_OpArrayCopy::src_objarray)) { 3192 __ load_klass(tmp, src); 3193 __ cmpl(Address(tmp, in_bytes(Klass::layout_helper_offset())), Klass::_lh_neutral_value); 3194 __ jcc(Assembler::greaterEqual, *stub->entry()); 3195 } 3196 } 3197 3198 // check if negative 3199 if (flags & LIR_OpArrayCopy::src_pos_positive_check) { 3200 __ testl(src_pos, src_pos); 3201 __ jcc(Assembler::less, *stub->entry()); 3202 } 3203 if (flags & LIR_OpArrayCopy::dst_pos_positive_check) { 3204 __ testl(dst_pos, dst_pos); 3205 __ jcc(Assembler::less, *stub->entry()); 3206 } 3207 3208 if (flags & LIR_OpArrayCopy::src_range_check) { 3209 __ lea(tmp, Address(src_pos, length, Address::times_1, 0)); 3210 __ cmpl(tmp, src_length_addr); 3211 __ jcc(Assembler::above, *stub->entry()); 3212 } 3213 if (flags & LIR_OpArrayCopy::dst_range_check) { 3214 __ lea(tmp, Address(dst_pos, length, Address::times_1, 0)); 3215 __ cmpl(tmp, dst_length_addr); 3216 __ jcc(Assembler::above, *stub->entry()); 3217 } 3218 3219 if (flags & LIR_OpArrayCopy::length_positive_check) { 3220 __ testl(length, length); 3221 __ jcc(Assembler::less, *stub->entry()); 3222 } 3223 3224 #ifdef _LP64 3225 __ movl2ptr(src_pos, src_pos); //higher 32bits must be null 3226 __ movl2ptr(dst_pos, dst_pos); //higher 32bits must be null 3227 #endif 3228 3229 if (flags & LIR_OpArrayCopy::type_check) { 3230 // We don't know the array types are compatible 3231 if (basic_type != T_OBJECT) { 3232 // Simple test for basic type arrays 3233 if (UseCompressedClassPointers) { 3234 __ movl(tmp, src_klass_addr); 3235 __ cmpl(tmp, dst_klass_addr); 3236 } else { 3237 __ movptr(tmp, src_klass_addr); 3238 __ cmpptr(tmp, dst_klass_addr); 3239 } 3240 __ jcc(Assembler::notEqual, *stub->entry()); 3241 } else { 3242 // For object arrays, if src is a sub class of dst then we can 3243 // safely do the copy. 3244 Label cont, slow; 3245 3246 __ push(src); 3247 __ push(dst); 3248 3249 __ load_klass(src, src); 3250 __ load_klass(dst, dst); 3251 3252 __ check_klass_subtype_fast_path(src, dst, tmp, &cont, &slow, NULL); 3253 3254 __ push(src); 3255 __ push(dst); 3256 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id))); 3257 __ pop(dst); 3258 __ pop(src); 3259 3260 __ cmpl(src, 0); 3261 __ jcc(Assembler::notEqual, cont); 3262 3263 __ bind(slow); 3264 __ pop(dst); 3265 __ pop(src); 3266 3267 address copyfunc_addr = StubRoutines::checkcast_arraycopy(); 3268 if (copyfunc_addr != NULL) { // use stub if available 3269 // src is not a sub class of dst so we have to do a 3270 // per-element check. 3271 3272 int mask = LIR_OpArrayCopy::src_objarray|LIR_OpArrayCopy::dst_objarray; 3273 if ((flags & mask) != mask) { 3274 // Check that at least both of them object arrays. 3275 assert(flags & mask, "one of the two should be known to be an object array"); 3276 3277 if (!(flags & LIR_OpArrayCopy::src_objarray)) { 3278 __ load_klass(tmp, src); 3279 } else if (!(flags & LIR_OpArrayCopy::dst_objarray)) { 3280 __ load_klass(tmp, dst); 3281 } 3282 int lh_offset = in_bytes(Klass::layout_helper_offset()); 3283 Address klass_lh_addr(tmp, lh_offset); 3284 jint objArray_lh = Klass::array_layout_helper(T_OBJECT); 3285 __ cmpl(klass_lh_addr, objArray_lh); 3286 __ jcc(Assembler::notEqual, *stub->entry()); 3287 } 3288 3289 // Spill because stubs can use any register they like and it's 3290 // easier to restore just those that we care about. 3291 store_parameter(dst, 0); 3292 store_parameter(dst_pos, 1); 3293 store_parameter(length, 2); 3294 store_parameter(src_pos, 3); 3295 store_parameter(src, 4); 3296 3297 #ifndef _LP64 3298 __ movptr(tmp, dst_klass_addr); 3299 __ movptr(tmp, Address(tmp, ObjArrayKlass::element_klass_offset())); 3300 __ push(tmp); 3301 __ movl(tmp, Address(tmp, Klass::super_check_offset_offset())); 3302 __ push(tmp); 3303 __ push(length); 3304 __ lea(tmp, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type))); 3305 __ push(tmp); 3306 __ lea(tmp, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type))); 3307 __ push(tmp); 3308 3309 __ call_VM_leaf(copyfunc_addr, 5); 3310 #else 3311 __ movl2ptr(length, length); //higher 32bits must be null 3312 3313 __ lea(c_rarg0, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type))); 3314 assert_different_registers(c_rarg0, dst, dst_pos, length); 3315 __ lea(c_rarg1, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type))); 3316 assert_different_registers(c_rarg1, dst, length); 3317 3318 __ mov(c_rarg2, length); 3319 assert_different_registers(c_rarg2, dst); 3320 3321 #ifdef _WIN64 3322 // Allocate abi space for args but be sure to keep stack aligned 3323 __ subptr(rsp, 6*wordSize); 3324 __ load_klass(c_rarg3, dst); 3325 __ movptr(c_rarg3, Address(c_rarg3, ObjArrayKlass::element_klass_offset())); 3326 store_parameter(c_rarg3, 4); 3327 __ movl(c_rarg3, Address(c_rarg3, Klass::super_check_offset_offset())); 3328 __ call(RuntimeAddress(copyfunc_addr)); 3329 __ addptr(rsp, 6*wordSize); 3330 #else 3331 __ load_klass(c_rarg4, dst); 3332 __ movptr(c_rarg4, Address(c_rarg4, ObjArrayKlass::element_klass_offset())); 3333 __ movl(c_rarg3, Address(c_rarg4, Klass::super_check_offset_offset())); 3334 __ call(RuntimeAddress(copyfunc_addr)); 3335 #endif 3336 3337 #endif 3338 3339 #ifndef PRODUCT 3340 if (PrintC1Statistics) { 3341 Label failed; 3342 __ testl(rax, rax); 3343 __ jcc(Assembler::notZero, failed); 3344 __ incrementl(ExternalAddress((address)&Runtime1::_arraycopy_checkcast_cnt)); 3345 __ bind(failed); 3346 } 3347 #endif 3348 3349 __ testl(rax, rax); 3350 __ jcc(Assembler::zero, *stub->continuation()); 3351 3352 #ifndef PRODUCT 3353 if (PrintC1Statistics) { 3354 __ incrementl(ExternalAddress((address)&Runtime1::_arraycopy_checkcast_attempt_cnt)); 3355 } 3356 #endif 3357 3358 __ mov(tmp, rax); 3359 3360 __ xorl(tmp, -1); 3361 3362 // Restore previously spilled arguments 3363 __ movptr (dst, Address(rsp, 0*BytesPerWord)); 3364 __ movptr (dst_pos, Address(rsp, 1*BytesPerWord)); 3365 __ movptr (length, Address(rsp, 2*BytesPerWord)); 3366 __ movptr (src_pos, Address(rsp, 3*BytesPerWord)); 3367 __ movptr (src, Address(rsp, 4*BytesPerWord)); 3368 3369 3370 __ subl(length, tmp); 3371 __ addl(src_pos, tmp); 3372 __ addl(dst_pos, tmp); 3373 } 3374 3375 __ jmp(*stub->entry()); 3376 3377 __ bind(cont); 3378 __ pop(dst); 3379 __ pop(src); 3380 } 3381 } 3382 3383 #ifdef ASSERT 3384 if (basic_type != T_OBJECT || !(flags & LIR_OpArrayCopy::type_check)) { 3385 // Sanity check the known type with the incoming class. For the 3386 // primitive case the types must match exactly with src.klass and 3387 // dst.klass each exactly matching the default type. For the 3388 // object array case, if no type check is needed then either the 3389 // dst type is exactly the expected type and the src type is a 3390 // subtype which we can't check or src is the same array as dst 3391 // but not necessarily exactly of type default_type. 3392 Label known_ok, halt; 3393 __ mov_metadata(tmp, default_type->constant_encoding()); 3394 #ifdef _LP64 3395 if (UseCompressedClassPointers) { 3396 __ encode_klass_not_null(tmp); 3397 } 3398 #endif 3399 3400 if (basic_type != T_OBJECT) { 3401 3402 if (UseCompressedClassPointers) __ cmpl(tmp, dst_klass_addr); 3403 else __ cmpptr(tmp, dst_klass_addr); 3404 __ jcc(Assembler::notEqual, halt); 3405 if (UseCompressedClassPointers) __ cmpl(tmp, src_klass_addr); 3406 else __ cmpptr(tmp, src_klass_addr); 3407 __ jcc(Assembler::equal, known_ok); 3408 } else { 3409 if (UseCompressedClassPointers) __ cmpl(tmp, dst_klass_addr); 3410 else __ cmpptr(tmp, dst_klass_addr); 3411 __ jcc(Assembler::equal, known_ok); 3412 __ cmpptr(src, dst); 3413 __ jcc(Assembler::equal, known_ok); 3414 } 3415 __ bind(halt); 3416 __ stop("incorrect type information in arraycopy"); 3417 __ bind(known_ok); 3418 } 3419 #endif 3420 3421 #ifndef PRODUCT 3422 if (PrintC1Statistics) { 3423 __ incrementl(ExternalAddress(Runtime1::arraycopy_count_address(basic_type))); 3424 } 3425 #endif 3426 3427 #ifdef _LP64 3428 assert_different_registers(c_rarg0, dst, dst_pos, length); 3429 __ lea(c_rarg0, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type))); 3430 assert_different_registers(c_rarg1, length); 3431 __ lea(c_rarg1, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type))); 3432 __ mov(c_rarg2, length); 3433 3434 #else 3435 __ lea(tmp, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type))); 3436 store_parameter(tmp, 0); 3437 __ lea(tmp, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type))); 3438 store_parameter(tmp, 1); 3439 store_parameter(length, 2); 3440 #endif // _LP64 3441 3442 bool disjoint = (flags & LIR_OpArrayCopy::overlapping) == 0; 3443 bool aligned = (flags & LIR_OpArrayCopy::unaligned) == 0; 3444 const char *name; 3445 address entry = StubRoutines::select_arraycopy_function(basic_type, aligned, disjoint, name, false); 3446 __ call_VM_leaf(entry, 0); 3447 3448 __ bind(*stub->continuation()); 3449 } 3450 3451 void LIR_Assembler::emit_updatecrc32(LIR_OpUpdateCRC32* op) { 3452 assert(op->crc()->is_single_cpu(), "crc must be register"); 3453 assert(op->val()->is_single_cpu(), "byte value must be register"); 3454 assert(op->result_opr()->is_single_cpu(), "result must be register"); 3455 Register crc = op->crc()->as_register(); 3456 Register val = op->val()->as_register(); 3457 Register res = op->result_opr()->as_register(); 3458 3459 assert_different_registers(val, crc, res); 3460 3461 __ lea(res, ExternalAddress(StubRoutines::crc_table_addr())); 3462 __ notl(crc); // ~crc 3463 __ update_byte_crc32(crc, val, res); 3464 __ notl(crc); // ~crc 3465 __ mov(res, crc); 3466 } 3467 3468 void LIR_Assembler::emit_lock(LIR_OpLock* op) { 3469 Register obj = op->obj_opr()->as_register(); // may not be an oop 3470 Register hdr = op->hdr_opr()->as_register(); 3471 Register lock = op->lock_opr()->as_register(); 3472 if (!UseFastLocking) { 3473 __ jmp(*op->stub()->entry()); 3474 } else if (op->code() == lir_lock) { 3475 Register scratch = noreg; 3476 if (UseBiasedLocking) { 3477 scratch = op->scratch_opr()->as_register(); 3478 } 3479 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header"); 3480 __ resolve(ACCESS_READ | ACCESS_WRITE, obj); 3481 // add debug info for NullPointerException only if one is possible 3482 int null_check_offset = __ lock_object(hdr, obj, lock, scratch, *op->stub()->entry()); 3483 if (op->info() != NULL) { 3484 add_debug_info_for_null_check(null_check_offset, op->info()); 3485 } 3486 // done 3487 } else if (op->code() == lir_unlock) { 3488 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header"); 3489 __ unlock_object(hdr, obj, lock, *op->stub()->entry()); 3490 } else { 3491 Unimplemented(); 3492 } 3493 __ bind(*op->stub()->continuation()); 3494 } 3495 3496 3497 void LIR_Assembler::emit_profile_call(LIR_OpProfileCall* op) { 3498 ciMethod* method = op->profiled_method(); 3499 int bci = op->profiled_bci(); 3500 ciMethod* callee = op->profiled_callee(); 3501 3502 // Update counter for all call types 3503 ciMethodData* md = method->method_data_or_null(); 3504 assert(md != NULL, "Sanity"); 3505 ciProfileData* data = md->bci_to_data(bci); 3506 assert(data != NULL && data->is_CounterData(), "need CounterData for calls"); 3507 assert(op->mdo()->is_single_cpu(), "mdo must be allocated"); 3508 Register mdo = op->mdo()->as_register(); 3509 __ mov_metadata(mdo, md->constant_encoding()); 3510 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset())); 3511 // Perform additional virtual call profiling for invokevirtual and 3512 // invokeinterface bytecodes 3513 if (op->should_profile_receiver_type()) { 3514 assert(op->recv()->is_single_cpu(), "recv must be allocated"); 3515 Register recv = op->recv()->as_register(); 3516 assert_different_registers(mdo, recv); 3517 assert(data->is_VirtualCallData(), "need VirtualCallData for virtual calls"); 3518 ciKlass* known_klass = op->known_holder(); 3519 if (C1OptimizeVirtualCallProfiling && known_klass != NULL) { 3520 // We know the type that will be seen at this call site; we can 3521 // statically update the MethodData* rather than needing to do 3522 // dynamic tests on the receiver type 3523 3524 // NOTE: we should probably put a lock around this search to 3525 // avoid collisions by concurrent compilations 3526 ciVirtualCallData* vc_data = (ciVirtualCallData*) data; 3527 uint i; 3528 for (i = 0; i < VirtualCallData::row_limit(); i++) { 3529 ciKlass* receiver = vc_data->receiver(i); 3530 if (known_klass->equals(receiver)) { 3531 Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i))); 3532 __ addptr(data_addr, DataLayout::counter_increment); 3533 return; 3534 } 3535 } 3536 3537 // Receiver type not found in profile data; select an empty slot 3538 3539 // Note that this is less efficient than it should be because it 3540 // always does a write to the receiver part of the 3541 // VirtualCallData rather than just the first time 3542 for (i = 0; i < VirtualCallData::row_limit(); i++) { 3543 ciKlass* receiver = vc_data->receiver(i); 3544 if (receiver == NULL) { 3545 Address recv_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_offset(i))); 3546 __ mov_metadata(recv_addr, known_klass->constant_encoding()); 3547 Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i))); 3548 __ addptr(data_addr, DataLayout::counter_increment); 3549 return; 3550 } 3551 } 3552 } else { 3553 __ load_klass(recv, recv); 3554 Label update_done; 3555 type_profile_helper(mdo, md, data, recv, &update_done); 3556 // Receiver did not match any saved receiver and there is no empty row for it. 3557 // Increment total counter to indicate polymorphic case. 3558 __ addptr(counter_addr, DataLayout::counter_increment); 3559 3560 __ bind(update_done); 3561 } 3562 } else { 3563 // Static call 3564 __ addptr(counter_addr, DataLayout::counter_increment); 3565 } 3566 } 3567 3568 void LIR_Assembler::emit_profile_type(LIR_OpProfileType* op) { 3569 Register obj = op->obj()->as_register(); 3570 Register tmp = op->tmp()->as_pointer_register(); 3571 Address mdo_addr = as_Address(op->mdp()->as_address_ptr()); 3572 ciKlass* exact_klass = op->exact_klass(); 3573 intptr_t current_klass = op->current_klass(); 3574 bool not_null = op->not_null(); 3575 bool no_conflict = op->no_conflict(); 3576 3577 Label update, next, none; 3578 3579 bool do_null = !not_null; 3580 bool exact_klass_set = exact_klass != NULL && ciTypeEntries::valid_ciklass(current_klass) == exact_klass; 3581 bool do_update = !TypeEntries::is_type_unknown(current_klass) && !exact_klass_set; 3582 3583 assert(do_null || do_update, "why are we here?"); 3584 assert(!TypeEntries::was_null_seen(current_klass) || do_update, "why are we here?"); 3585 3586 __ verify_oop(obj); 3587 3588 if (tmp != obj) { 3589 __ mov(tmp, obj); 3590 } 3591 if (do_null) { 3592 __ testptr(tmp, tmp); 3593 __ jccb(Assembler::notZero, update); 3594 if (!TypeEntries::was_null_seen(current_klass)) { 3595 __ orptr(mdo_addr, TypeEntries::null_seen); 3596 } 3597 if (do_update) { 3598 #ifndef ASSERT 3599 __ jmpb(next); 3600 } 3601 #else 3602 __ jmp(next); 3603 } 3604 } else { 3605 __ testptr(tmp, tmp); 3606 __ jcc(Assembler::notZero, update); 3607 __ stop("unexpect null obj"); 3608 #endif 3609 } 3610 3611 __ bind(update); 3612 3613 if (do_update) { 3614 #ifdef ASSERT 3615 if (exact_klass != NULL) { 3616 Label ok; 3617 __ load_klass(tmp, tmp); 3618 __ push(tmp); 3619 __ mov_metadata(tmp, exact_klass->constant_encoding()); 3620 __ cmpptr(tmp, Address(rsp, 0)); 3621 __ jcc(Assembler::equal, ok); 3622 __ stop("exact klass and actual klass differ"); 3623 __ bind(ok); 3624 __ pop(tmp); 3625 } 3626 #endif 3627 if (!no_conflict) { 3628 if (exact_klass == NULL || TypeEntries::is_type_none(current_klass)) { 3629 if (exact_klass != NULL) { 3630 __ mov_metadata(tmp, exact_klass->constant_encoding()); 3631 } else { 3632 __ load_klass(tmp, tmp); 3633 } 3634 3635 __ xorptr(tmp, mdo_addr); 3636 __ testptr(tmp, TypeEntries::type_klass_mask); 3637 // klass seen before, nothing to do. The unknown bit may have been 3638 // set already but no need to check. 3639 __ jccb(Assembler::zero, next); 3640 3641 __ testptr(tmp, TypeEntries::type_unknown); 3642 __ jccb(Assembler::notZero, next); // already unknown. Nothing to do anymore. 3643 3644 if (TypeEntries::is_type_none(current_klass)) { 3645 __ cmpptr(mdo_addr, 0); 3646 __ jccb(Assembler::equal, none); 3647 __ cmpptr(mdo_addr, TypeEntries::null_seen); 3648 __ jccb(Assembler::equal, none); 3649 // There is a chance that the checks above (re-reading profiling 3650 // data from memory) fail if another thread has just set the 3651 // profiling to this obj's klass 3652 __ xorptr(tmp, mdo_addr); 3653 __ testptr(tmp, TypeEntries::type_klass_mask); 3654 __ jccb(Assembler::zero, next); 3655 } 3656 } else { 3657 assert(ciTypeEntries::valid_ciklass(current_klass) != NULL && 3658 ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "conflict only"); 3659 3660 __ movptr(tmp, mdo_addr); 3661 __ testptr(tmp, TypeEntries::type_unknown); 3662 __ jccb(Assembler::notZero, next); // already unknown. Nothing to do anymore. 3663 } 3664 3665 // different than before. Cannot keep accurate profile. 3666 __ orptr(mdo_addr, TypeEntries::type_unknown); 3667 3668 if (TypeEntries::is_type_none(current_klass)) { 3669 __ jmpb(next); 3670 3671 __ bind(none); 3672 // first time here. Set profile type. 3673 __ movptr(mdo_addr, tmp); 3674 } 3675 } else { 3676 // There's a single possible klass at this profile point 3677 assert(exact_klass != NULL, "should be"); 3678 if (TypeEntries::is_type_none(current_klass)) { 3679 __ mov_metadata(tmp, exact_klass->constant_encoding()); 3680 __ xorptr(tmp, mdo_addr); 3681 __ testptr(tmp, TypeEntries::type_klass_mask); 3682 #ifdef ASSERT 3683 __ jcc(Assembler::zero, next); 3684 3685 { 3686 Label ok; 3687 __ push(tmp); 3688 __ cmpptr(mdo_addr, 0); 3689 __ jcc(Assembler::equal, ok); 3690 __ cmpptr(mdo_addr, TypeEntries::null_seen); 3691 __ jcc(Assembler::equal, ok); 3692 // may have been set by another thread 3693 __ mov_metadata(tmp, exact_klass->constant_encoding()); 3694 __ xorptr(tmp, mdo_addr); 3695 __ testptr(tmp, TypeEntries::type_mask); 3696 __ jcc(Assembler::zero, ok); 3697 3698 __ stop("unexpected profiling mismatch"); 3699 __ bind(ok); 3700 __ pop(tmp); 3701 } 3702 #else 3703 __ jccb(Assembler::zero, next); 3704 #endif 3705 // first time here. Set profile type. 3706 __ movptr(mdo_addr, tmp); 3707 } else { 3708 assert(ciTypeEntries::valid_ciklass(current_klass) != NULL && 3709 ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "inconsistent"); 3710 3711 __ movptr(tmp, mdo_addr); 3712 __ testptr(tmp, TypeEntries::type_unknown); 3713 __ jccb(Assembler::notZero, next); // already unknown. Nothing to do anymore. 3714 3715 __ orptr(mdo_addr, TypeEntries::type_unknown); 3716 } 3717 } 3718 3719 __ bind(next); 3720 } 3721 } 3722 3723 void LIR_Assembler::emit_delay(LIR_OpDelay*) { 3724 Unimplemented(); 3725 } 3726 3727 3728 void LIR_Assembler::monitor_address(int monitor_no, LIR_Opr dst) { 3729 __ lea(dst->as_register(), frame_map()->address_for_monitor_lock(monitor_no)); 3730 } 3731 3732 3733 void LIR_Assembler::align_backward_branch_target() { 3734 __ align(BytesPerWord); 3735 } 3736 3737 3738 void LIR_Assembler::negate(LIR_Opr left, LIR_Opr dest, LIR_Opr tmp) { 3739 if (left->is_single_cpu()) { 3740 __ negl(left->as_register()); 3741 move_regs(left->as_register(), dest->as_register()); 3742 3743 } else if (left->is_double_cpu()) { 3744 Register lo = left->as_register_lo(); 3745 #ifdef _LP64 3746 Register dst = dest->as_register_lo(); 3747 __ movptr(dst, lo); 3748 __ negptr(dst); 3749 #else 3750 Register hi = left->as_register_hi(); 3751 __ lneg(hi, lo); 3752 if (dest->as_register_lo() == hi) { 3753 assert(dest->as_register_hi() != lo, "destroying register"); 3754 move_regs(hi, dest->as_register_hi()); 3755 move_regs(lo, dest->as_register_lo()); 3756 } else { 3757 move_regs(lo, dest->as_register_lo()); 3758 move_regs(hi, dest->as_register_hi()); 3759 } 3760 #endif // _LP64 3761 3762 } else if (dest->is_single_xmm()) { 3763 #ifdef _LP64 3764 if (UseAVX > 2 && !VM_Version::supports_avx512vl()) { 3765 assert(tmp->is_valid(), "need temporary"); 3766 assert_different_registers(left->as_xmm_float_reg(), tmp->as_xmm_float_reg()); 3767 __ vpxor(dest->as_xmm_float_reg(), tmp->as_xmm_float_reg(), left->as_xmm_float_reg(), 2); 3768 } 3769 else 3770 #endif 3771 { 3772 assert(!tmp->is_valid(), "do not need temporary"); 3773 if (left->as_xmm_float_reg() != dest->as_xmm_float_reg()) { 3774 __ movflt(dest->as_xmm_float_reg(), left->as_xmm_float_reg()); 3775 } 3776 __ xorps(dest->as_xmm_float_reg(), 3777 ExternalAddress((address)float_signflip_pool)); 3778 } 3779 } else if (dest->is_double_xmm()) { 3780 #ifdef _LP64 3781 if (UseAVX > 2 && !VM_Version::supports_avx512vl()) { 3782 assert(tmp->is_valid(), "need temporary"); 3783 assert_different_registers(left->as_xmm_double_reg(), tmp->as_xmm_double_reg()); 3784 __ vpxor(dest->as_xmm_double_reg(), tmp->as_xmm_double_reg(), left->as_xmm_double_reg(), 2); 3785 } 3786 else 3787 #endif 3788 { 3789 assert(!tmp->is_valid(), "do not need temporary"); 3790 if (left->as_xmm_double_reg() != dest->as_xmm_double_reg()) { 3791 __ movdbl(dest->as_xmm_double_reg(), left->as_xmm_double_reg()); 3792 } 3793 __ xorpd(dest->as_xmm_double_reg(), 3794 ExternalAddress((address)double_signflip_pool)); 3795 } 3796 } else if (left->is_single_fpu() || left->is_double_fpu()) { 3797 assert(left->fpu() == 0, "arg must be on TOS"); 3798 assert(dest->fpu() == 0, "dest must be TOS"); 3799 __ fchs(); 3800 3801 } else { 3802 ShouldNotReachHere(); 3803 } 3804 } 3805 3806 3807 void LIR_Assembler::leal(LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) { 3808 assert(src->is_address(), "must be an address"); 3809 assert(dest->is_register(), "must be a register"); 3810 3811 PatchingStub* patch = NULL; 3812 if (patch_code != lir_patch_none) { 3813 patch = new PatchingStub(_masm, PatchingStub::access_field_id); 3814 } 3815 3816 Register reg = dest->as_pointer_register(); 3817 LIR_Address* addr = src->as_address_ptr(); 3818 __ lea(reg, as_Address(addr)); 3819 3820 if (patch != NULL) { 3821 patching_epilog(patch, patch_code, addr->base()->as_register(), info); 3822 } 3823 } 3824 3825 3826 3827 void LIR_Assembler::rt_call(LIR_Opr result, address dest, const LIR_OprList* args, LIR_Opr tmp, CodeEmitInfo* info) { 3828 assert(!tmp->is_valid(), "don't need temporary"); 3829 __ call(RuntimeAddress(dest)); 3830 if (info != NULL) { 3831 add_call_info_here(info); 3832 } 3833 } 3834 3835 3836 void LIR_Assembler::volatile_move_op(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info) { 3837 assert(type == T_LONG, "only for volatile long fields"); 3838 3839 if (info != NULL) { 3840 add_debug_info_for_null_check_here(info); 3841 } 3842 3843 if (src->is_double_xmm()) { 3844 if (dest->is_double_cpu()) { 3845 #ifdef _LP64 3846 __ movdq(dest->as_register_lo(), src->as_xmm_double_reg()); 3847 #else 3848 __ movdl(dest->as_register_lo(), src->as_xmm_double_reg()); 3849 __ psrlq(src->as_xmm_double_reg(), 32); 3850 __ movdl(dest->as_register_hi(), src->as_xmm_double_reg()); 3851 #endif // _LP64 3852 } else if (dest->is_double_stack()) { 3853 __ movdbl(frame_map()->address_for_slot(dest->double_stack_ix()), src->as_xmm_double_reg()); 3854 } else if (dest->is_address()) { 3855 __ movdbl(as_Address(dest->as_address_ptr()), src->as_xmm_double_reg()); 3856 } else { 3857 ShouldNotReachHere(); 3858 } 3859 3860 } else if (dest->is_double_xmm()) { 3861 if (src->is_double_stack()) { 3862 __ movdbl(dest->as_xmm_double_reg(), frame_map()->address_for_slot(src->double_stack_ix())); 3863 } else if (src->is_address()) { 3864 __ movdbl(dest->as_xmm_double_reg(), as_Address(src->as_address_ptr())); 3865 } else { 3866 ShouldNotReachHere(); 3867 } 3868 3869 } else if (src->is_double_fpu()) { 3870 assert(src->fpu_regnrLo() == 0, "must be TOS"); 3871 if (dest->is_double_stack()) { 3872 __ fistp_d(frame_map()->address_for_slot(dest->double_stack_ix())); 3873 } else if (dest->is_address()) { 3874 __ fistp_d(as_Address(dest->as_address_ptr())); 3875 } else { 3876 ShouldNotReachHere(); 3877 } 3878 3879 } else if (dest->is_double_fpu()) { 3880 assert(dest->fpu_regnrLo() == 0, "must be TOS"); 3881 if (src->is_double_stack()) { 3882 __ fild_d(frame_map()->address_for_slot(src->double_stack_ix())); 3883 } else if (src->is_address()) { 3884 __ fild_d(as_Address(src->as_address_ptr())); 3885 } else { 3886 ShouldNotReachHere(); 3887 } 3888 } else { 3889 ShouldNotReachHere(); 3890 } 3891 } 3892 3893 #ifdef ASSERT 3894 // emit run-time assertion 3895 void LIR_Assembler::emit_assert(LIR_OpAssert* op) { 3896 assert(op->code() == lir_assert, "must be"); 3897 3898 if (op->in_opr1()->is_valid()) { 3899 assert(op->in_opr2()->is_valid(), "both operands must be valid"); 3900 comp_op(op->condition(), op->in_opr1(), op->in_opr2(), op); 3901 } else { 3902 assert(op->in_opr2()->is_illegal(), "both operands must be illegal"); 3903 assert(op->condition() == lir_cond_always, "no other conditions allowed"); 3904 } 3905 3906 Label ok; 3907 if (op->condition() != lir_cond_always) { 3908 Assembler::Condition acond = Assembler::zero; 3909 switch (op->condition()) { 3910 case lir_cond_equal: acond = Assembler::equal; break; 3911 case lir_cond_notEqual: acond = Assembler::notEqual; break; 3912 case lir_cond_less: acond = Assembler::less; break; 3913 case lir_cond_lessEqual: acond = Assembler::lessEqual; break; 3914 case lir_cond_greaterEqual: acond = Assembler::greaterEqual;break; 3915 case lir_cond_greater: acond = Assembler::greater; break; 3916 case lir_cond_belowEqual: acond = Assembler::belowEqual; break; 3917 case lir_cond_aboveEqual: acond = Assembler::aboveEqual; break; 3918 default: ShouldNotReachHere(); 3919 } 3920 __ jcc(acond, ok); 3921 } 3922 if (op->halt()) { 3923 const char* str = __ code_string(op->msg()); 3924 __ stop(str); 3925 } else { 3926 breakpoint(); 3927 } 3928 __ bind(ok); 3929 } 3930 #endif 3931 3932 void LIR_Assembler::membar() { 3933 // QQQ sparc TSO uses this, 3934 __ membar( Assembler::Membar_mask_bits(Assembler::StoreLoad)); 3935 } 3936 3937 void LIR_Assembler::membar_acquire() { 3938 // No x86 machines currently require load fences 3939 } 3940 3941 void LIR_Assembler::membar_release() { 3942 // No x86 machines currently require store fences 3943 } 3944 3945 void LIR_Assembler::membar_loadload() { 3946 // no-op 3947 //__ membar(Assembler::Membar_mask_bits(Assembler::loadload)); 3948 } 3949 3950 void LIR_Assembler::membar_storestore() { 3951 // no-op 3952 //__ membar(Assembler::Membar_mask_bits(Assembler::storestore)); 3953 } 3954 3955 void LIR_Assembler::membar_loadstore() { 3956 // no-op 3957 //__ membar(Assembler::Membar_mask_bits(Assembler::loadstore)); 3958 } 3959 3960 void LIR_Assembler::membar_storeload() { 3961 __ membar(Assembler::Membar_mask_bits(Assembler::StoreLoad)); 3962 } 3963 3964 void LIR_Assembler::on_spin_wait() { 3965 __ pause (); 3966 } 3967 3968 void LIR_Assembler::get_thread(LIR_Opr result_reg) { 3969 assert(result_reg->is_register(), "check"); 3970 #ifdef _LP64 3971 // __ get_thread(result_reg->as_register_lo()); 3972 __ mov(result_reg->as_register(), r15_thread); 3973 #else 3974 __ get_thread(result_reg->as_register()); 3975 #endif // _LP64 3976 } 3977 3978 3979 void LIR_Assembler::peephole(LIR_List*) { 3980 // do nothing for now 3981 } 3982 3983 void LIR_Assembler::atomic_op(LIR_Code code, LIR_Opr src, LIR_Opr data, LIR_Opr dest, LIR_Opr tmp) { 3984 assert(data == dest, "xchg/xadd uses only 2 operands"); 3985 3986 if (data->type() == T_INT) { 3987 if (code == lir_xadd) { 3988 __ lock(); 3989 __ xaddl(as_Address(src->as_address_ptr()), data->as_register()); 3990 } else { 3991 __ xchgl(data->as_register(), as_Address(src->as_address_ptr())); 3992 } 3993 } else if (data->is_oop()) { 3994 assert (code == lir_xchg, "xadd for oops"); 3995 Register obj = data->as_register(); 3996 #ifdef _LP64 3997 if (UseCompressedOops) { 3998 __ encode_heap_oop(obj); 3999 __ xchgl(obj, as_Address(src->as_address_ptr())); 4000 __ decode_heap_oop(obj); 4001 } else { 4002 __ xchgptr(obj, as_Address(src->as_address_ptr())); 4003 } 4004 #else 4005 __ xchgl(obj, as_Address(src->as_address_ptr())); 4006 #endif 4007 } else if (data->type() == T_LONG) { 4008 #ifdef _LP64 4009 assert(data->as_register_lo() == data->as_register_hi(), "should be a single register"); 4010 if (code == lir_xadd) { 4011 __ lock(); 4012 __ xaddq(as_Address(src->as_address_ptr()), data->as_register_lo()); 4013 } else { 4014 __ xchgq(data->as_register_lo(), as_Address(src->as_address_ptr())); 4015 } 4016 #else 4017 ShouldNotReachHere(); 4018 #endif 4019 } else { 4020 ShouldNotReachHere(); 4021 } 4022 } 4023 4024 #undef __