< prev index next >

src/hotspot/cpu/ppc/ppc.ad

Print this page 
rev 50668 : PPC64: Add support for HW random number generator

Add support to use a hardware random number generator through new 'darn'
instruction introduced with POWER9 processor. That change introduces a new
JCA provider (called HWTRNG) with the proper methods to be intrinsified and
that are used, in the end, by generateSeed() and nextBytes() methods in
SecureRandom class when the HWTPRNG provider is selected. It also paves the
way to use a HW TRNG for other architectures that support it.
14562     // TODO: PPC port $archOpcode(ppc64Opcode_mcrf);
14563     __ brnop1();
14564   %}
14565   ins_pipe(pipe_class_default);
14566 %}
14567 
14568 instruct brNop2() %{
14569   ins_cost(0);
14570 
14571   ins_is_nop(true);
14572 
14573   format %{ "brNop2" %}
14574   size(4);
14575   ins_encode %{
14576     // TODO: PPC port $archOpcode(ppc64Opcode_mcrf);
14577     __ brnop2();
14578   %}
14579   ins_pipe(pipe_class_default);
14580 %}
14581 









14582 //----------PEEPHOLE RULES-----------------------------------------------------
14583 // These must follow all instruction definitions as they use the names
14584 // defined in the instructions definitions.
14585 //
14586 // peepmatch ( root_instr_name [preceeding_instruction]* );
14587 //
14588 // peepconstraint %{
14589 // (instruction_number.operand_name relational_op instruction_number.operand_name
14590 //  [, ...] );
14591 // // instruction numbers are zero-based using left to right order in peepmatch
14592 //
14593 // peepreplace ( instr_name ( [instruction_number.operand_name]* ) );
14594 // // provide an instruction_number.operand_name for each operand that appears
14595 // // in the replacement instruction's match rule
14596 //
14597 // ---------VM FLAGS---------------------------------------------------------
14598 //
14599 // All peephole optimizations can be turned off using -XX:-OptoPeephole
14600 //
14601 // Each peephole rule is given an identifying number starting with zero and




14562     // TODO: PPC port $archOpcode(ppc64Opcode_mcrf);
14563     __ brnop1();
14564   %}
14565   ins_pipe(pipe_class_default);
14566 %}
14567 
14568 instruct brNop2() %{
14569   ins_cost(0);
14570 
14571   ins_is_nop(true);
14572 
14573   format %{ "brNop2" %}
14574   size(4);
14575   ins_encode %{
14576     // TODO: PPC port $archOpcode(ppc64Opcode_mcrf);
14577     __ brnop2();
14578   %}
14579   ins_pipe(pipe_class_default);
14580 %}
14581 
14582 instruct randL(iRegLdst dst) %{
14583   match(Set dst (RandL));
14584   format %{ "DARN $dst\t# long" %}
14585   ins_encode %{
14586     __ darn($dst$$Register);
14587   %}
14588   ins_pipe(pipe_class_default);
14589 %}
14590 
14591 //----------PEEPHOLE RULES-----------------------------------------------------
14592 // These must follow all instruction definitions as they use the names
14593 // defined in the instructions definitions.
14594 //
14595 // peepmatch ( root_instr_name [preceeding_instruction]* );
14596 //
14597 // peepconstraint %{
14598 // (instruction_number.operand_name relational_op instruction_number.operand_name
14599 //  [, ...] );
14600 // // instruction numbers are zero-based using left to right order in peepmatch
14601 //
14602 // peepreplace ( instr_name ( [instruction_number.operand_name]* ) );
14603 // // provide an instruction_number.operand_name for each operand that appears
14604 // // in the replacement instruction's match rule
14605 //
14606 // ---------VM FLAGS---------------------------------------------------------
14607 //
14608 // All peephole optimizations can be turned off using -XX:-OptoPeephole
14609 //
14610 // Each peephole rule is given an identifying number starting with zero and







< prev index next >