1 /*
2 * Copyright (c) 1997, 2020, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #include "precompiled.hpp"
26 #include "jvm.h"
27 #include "asm/macroAssembler.hpp"
28 #include "asm/macroAssembler.inline.hpp"
29 #include "logging/log.hpp"
30 #include "logging/logStream.hpp"
31 #include "memory/resourceArea.hpp"
32 #include "runtime/java.hpp"
33 #include "runtime/os.hpp"
34 #include "runtime/stubCodeGenerator.hpp"
35 #include "runtime/vm_version.hpp"
36 #include "utilities/powerOfTwo.hpp"
37 #include "utilities/virtualizationSupport.hpp"
38
39 #include OS_HEADER_INLINE(os)
40
41 int VM_Version::_cpu;
42 int VM_Version::_model;
43 int VM_Version::_stepping;
44 bool VM_Version::_has_intel_jcc_erratum;
45 VM_Version::CpuidInfo VM_Version::_cpuid_info = { 0, };
46
47 // Address of instruction which causes SEGV
48 address VM_Version::_cpuinfo_segv_addr = 0;
49 // Address of instruction after the one which causes SEGV
50 address VM_Version::_cpuinfo_cont_addr = 0;
51
52 static BufferBlob* stub_blob;
53 static const int stub_size = 2000;
54
55 extern "C" {
56 typedef void (*get_cpu_info_stub_t)(void*);
57 typedef void (*detect_virt_stub_t)(uint32_t, uint32_t*);
58 }
59 static get_cpu_info_stub_t get_cpu_info_stub = NULL;
60 static detect_virt_stub_t detect_virt_stub = NULL;
61
62
63 class VM_Version_StubGenerator: public StubCodeGenerator {
64 public:
65
66 VM_Version_StubGenerator(CodeBuffer *c) : StubCodeGenerator(c) {}
67
68 address generate_get_cpu_info() {
69 // Flags to test CPU type.
70 const uint32_t HS_EFL_AC = 0x40000;
71 const uint32_t HS_EFL_ID = 0x200000;
72 // Values for when we don't have a CPUID instruction.
73 const int CPU_FAMILY_SHIFT = 8;
74 const uint32_t CPU_FAMILY_386 = (3 << CPU_FAMILY_SHIFT);
75 const uint32_t CPU_FAMILY_486 = (4 << CPU_FAMILY_SHIFT);
76 bool use_evex = FLAG_IS_DEFAULT(UseAVX) || (UseAVX > 2);
77
78 Label detect_486, cpu486, detect_586, std_cpuid1, std_cpuid4;
79 Label sef_cpuid, ext_cpuid, ext_cpuid1, ext_cpuid5, ext_cpuid7, ext_cpuid8, done, wrapup;
80 Label legacy_setup, save_restore_except, legacy_save_restore, start_simd_check;
81
82 StubCodeMark mark(this, "VM_Version", "get_cpu_info_stub");
83 # define __ _masm->
84
85 address start = __ pc();
86
87 //
88 // void get_cpu_info(VM_Version::CpuidInfo* cpuid_info);
89 //
90 // LP64: rcx and rdx are first and second argument registers on windows
91
92 __ push(rbp);
93 #ifdef _LP64
94 __ mov(rbp, c_rarg0); // cpuid_info address
95 #else
96 __ movptr(rbp, Address(rsp, 8)); // cpuid_info address
97 #endif
98 __ push(rbx);
99 __ push(rsi);
100 __ pushf(); // preserve rbx, and flags
101 __ pop(rax);
102 __ push(rax);
103 __ mov(rcx, rax);
104 //
105 // if we are unable to change the AC flag, we have a 386
106 //
107 __ xorl(rax, HS_EFL_AC);
108 __ push(rax);
109 __ popf();
110 __ pushf();
111 __ pop(rax);
112 __ cmpptr(rax, rcx);
113 __ jccb(Assembler::notEqual, detect_486);
114
115 __ movl(rax, CPU_FAMILY_386);
116 __ movl(Address(rbp, in_bytes(VM_Version::std_cpuid1_offset())), rax);
117 __ jmp(done);
118
119 //
120 // If we are unable to change the ID flag, we have a 486 which does
121 // not support the "cpuid" instruction.
122 //
123 __ bind(detect_486);
124 __ mov(rax, rcx);
125 __ xorl(rax, HS_EFL_ID);
126 __ push(rax);
127 __ popf();
128 __ pushf();
129 __ pop(rax);
130 __ cmpptr(rcx, rax);
131 __ jccb(Assembler::notEqual, detect_586);
132
133 __ bind(cpu486);
134 __ movl(rax, CPU_FAMILY_486);
135 __ movl(Address(rbp, in_bytes(VM_Version::std_cpuid1_offset())), rax);
136 __ jmp(done);
137
138 //
139 // At this point, we have a chip which supports the "cpuid" instruction
140 //
141 __ bind(detect_586);
142 __ xorl(rax, rax);
143 __ cpuid();
144 __ orl(rax, rax);
145 __ jcc(Assembler::equal, cpu486); // if cpuid doesn't support an input
146 // value of at least 1, we give up and
147 // assume a 486
148 __ lea(rsi, Address(rbp, in_bytes(VM_Version::std_cpuid0_offset())));
149 __ movl(Address(rsi, 0), rax);
150 __ movl(Address(rsi, 4), rbx);
151 __ movl(Address(rsi, 8), rcx);
152 __ movl(Address(rsi,12), rdx);
153
154 __ cmpl(rax, 0xa); // Is cpuid(0xB) supported?
155 __ jccb(Assembler::belowEqual, std_cpuid4);
156
157 //
158 // cpuid(0xB) Processor Topology
159 //
160 __ movl(rax, 0xb);
161 __ xorl(rcx, rcx); // Threads level
162 __ cpuid();
163
164 __ lea(rsi, Address(rbp, in_bytes(VM_Version::tpl_cpuidB0_offset())));
165 __ movl(Address(rsi, 0), rax);
166 __ movl(Address(rsi, 4), rbx);
167 __ movl(Address(rsi, 8), rcx);
168 __ movl(Address(rsi,12), rdx);
169
170 __ movl(rax, 0xb);
171 __ movl(rcx, 1); // Cores level
172 __ cpuid();
173 __ push(rax);
174 __ andl(rax, 0x1f); // Determine if valid topology level
175 __ orl(rax, rbx); // eax[4:0] | ebx[0:15] == 0 indicates invalid level
176 __ andl(rax, 0xffff);
177 __ pop(rax);
178 __ jccb(Assembler::equal, std_cpuid4);
179
180 __ lea(rsi, Address(rbp, in_bytes(VM_Version::tpl_cpuidB1_offset())));
181 __ movl(Address(rsi, 0), rax);
182 __ movl(Address(rsi, 4), rbx);
183 __ movl(Address(rsi, 8), rcx);
184 __ movl(Address(rsi,12), rdx);
185
186 __ movl(rax, 0xb);
187 __ movl(rcx, 2); // Packages level
188 __ cpuid();
189 __ push(rax);
190 __ andl(rax, 0x1f); // Determine if valid topology level
191 __ orl(rax, rbx); // eax[4:0] | ebx[0:15] == 0 indicates invalid level
192 __ andl(rax, 0xffff);
193 __ pop(rax);
194 __ jccb(Assembler::equal, std_cpuid4);
195
196 __ lea(rsi, Address(rbp, in_bytes(VM_Version::tpl_cpuidB2_offset())));
197 __ movl(Address(rsi, 0), rax);
198 __ movl(Address(rsi, 4), rbx);
199 __ movl(Address(rsi, 8), rcx);
200 __ movl(Address(rsi,12), rdx);
201
202 //
203 // cpuid(0x4) Deterministic cache params
204 //
205 __ bind(std_cpuid4);
206 __ movl(rax, 4);
207 __ cmpl(rax, Address(rbp, in_bytes(VM_Version::std_cpuid0_offset()))); // Is cpuid(0x4) supported?
208 __ jccb(Assembler::greater, std_cpuid1);
209
210 __ xorl(rcx, rcx); // L1 cache
211 __ cpuid();
212 __ push(rax);
213 __ andl(rax, 0x1f); // Determine if valid cache parameters used
214 __ orl(rax, rax); // eax[4:0] == 0 indicates invalid cache
215 __ pop(rax);
216 __ jccb(Assembler::equal, std_cpuid1);
217
218 __ lea(rsi, Address(rbp, in_bytes(VM_Version::dcp_cpuid4_offset())));
219 __ movl(Address(rsi, 0), rax);
220 __ movl(Address(rsi, 4), rbx);
221 __ movl(Address(rsi, 8), rcx);
222 __ movl(Address(rsi,12), rdx);
223
224 //
225 // Standard cpuid(0x1)
226 //
227 __ bind(std_cpuid1);
228 __ movl(rax, 1);
229 __ cpuid();
230 __ lea(rsi, Address(rbp, in_bytes(VM_Version::std_cpuid1_offset())));
231 __ movl(Address(rsi, 0), rax);
232 __ movl(Address(rsi, 4), rbx);
233 __ movl(Address(rsi, 8), rcx);
234 __ movl(Address(rsi,12), rdx);
235
236 //
237 // Check if OS has enabled XGETBV instruction to access XCR0
238 // (OSXSAVE feature flag) and CPU supports AVX
239 //
240 __ andl(rcx, 0x18000000); // cpuid1 bits osxsave | avx
241 __ cmpl(rcx, 0x18000000);
242 __ jccb(Assembler::notEqual, sef_cpuid); // jump if AVX is not supported
243
244 //
245 // XCR0, XFEATURE_ENABLED_MASK register
246 //
247 __ xorl(rcx, rcx); // zero for XCR0 register
248 __ xgetbv();
249 __ lea(rsi, Address(rbp, in_bytes(VM_Version::xem_xcr0_offset())));
250 __ movl(Address(rsi, 0), rax);
251 __ movl(Address(rsi, 4), rdx);
252
253 //
254 // cpuid(0x7) Structured Extended Features
255 //
256 __ bind(sef_cpuid);
257 __ movl(rax, 7);
258 __ cmpl(rax, Address(rbp, in_bytes(VM_Version::std_cpuid0_offset()))); // Is cpuid(0x7) supported?
259 __ jccb(Assembler::greater, ext_cpuid);
260
261 __ xorl(rcx, rcx);
262 __ cpuid();
263 __ lea(rsi, Address(rbp, in_bytes(VM_Version::sef_cpuid7_offset())));
264 __ movl(Address(rsi, 0), rax);
265 __ movl(Address(rsi, 4), rbx);
266 __ movl(Address(rsi, 8), rcx);
267 __ movl(Address(rsi, 12), rdx);
268
269 //
270 // Extended cpuid(0x80000000)
271 //
272 __ bind(ext_cpuid);
273 __ movl(rax, 0x80000000);
274 __ cpuid();
275 __ cmpl(rax, 0x80000000); // Is cpuid(0x80000001) supported?
276 __ jcc(Assembler::belowEqual, done);
277 __ cmpl(rax, 0x80000004); // Is cpuid(0x80000005) supported?
278 __ jcc(Assembler::belowEqual, ext_cpuid1);
279 __ cmpl(rax, 0x80000006); // Is cpuid(0x80000007) supported?
280 __ jccb(Assembler::belowEqual, ext_cpuid5);
281 __ cmpl(rax, 0x80000007); // Is cpuid(0x80000008) supported?
282 __ jccb(Assembler::belowEqual, ext_cpuid7);
283 __ cmpl(rax, 0x80000008); // Is cpuid(0x80000009 and above) supported?
284 __ jccb(Assembler::belowEqual, ext_cpuid8);
285 __ cmpl(rax, 0x8000001E); // Is cpuid(0x8000001E) supported?
286 __ jccb(Assembler::below, ext_cpuid8);
287 //
288 // Extended cpuid(0x8000001E)
289 //
290 __ movl(rax, 0x8000001E);
291 __ cpuid();
292 __ lea(rsi, Address(rbp, in_bytes(VM_Version::ext_cpuid1E_offset())));
293 __ movl(Address(rsi, 0), rax);
294 __ movl(Address(rsi, 4), rbx);
295 __ movl(Address(rsi, 8), rcx);
296 __ movl(Address(rsi,12), rdx);
297
298 //
299 // Extended cpuid(0x80000008)
300 //
301 __ bind(ext_cpuid8);
302 __ movl(rax, 0x80000008);
303 __ cpuid();
304 __ lea(rsi, Address(rbp, in_bytes(VM_Version::ext_cpuid8_offset())));
305 __ movl(Address(rsi, 0), rax);
306 __ movl(Address(rsi, 4), rbx);
307 __ movl(Address(rsi, 8), rcx);
308 __ movl(Address(rsi,12), rdx);
309
310 //
311 // Extended cpuid(0x80000007)
312 //
313 __ bind(ext_cpuid7);
314 __ movl(rax, 0x80000007);
315 __ cpuid();
316 __ lea(rsi, Address(rbp, in_bytes(VM_Version::ext_cpuid7_offset())));
317 __ movl(Address(rsi, 0), rax);
318 __ movl(Address(rsi, 4), rbx);
319 __ movl(Address(rsi, 8), rcx);
320 __ movl(Address(rsi,12), rdx);
321
322 //
323 // Extended cpuid(0x80000005)
324 //
325 __ bind(ext_cpuid5);
326 __ movl(rax, 0x80000005);
327 __ cpuid();
328 __ lea(rsi, Address(rbp, in_bytes(VM_Version::ext_cpuid5_offset())));
329 __ movl(Address(rsi, 0), rax);
330 __ movl(Address(rsi, 4), rbx);
331 __ movl(Address(rsi, 8), rcx);
332 __ movl(Address(rsi,12), rdx);
333
334 //
335 // Extended cpuid(0x80000001)
336 //
337 __ bind(ext_cpuid1);
338 __ movl(rax, 0x80000001);
339 __ cpuid();
340 __ lea(rsi, Address(rbp, in_bytes(VM_Version::ext_cpuid1_offset())));
341 __ movl(Address(rsi, 0), rax);
342 __ movl(Address(rsi, 4), rbx);
343 __ movl(Address(rsi, 8), rcx);
344 __ movl(Address(rsi,12), rdx);
345
346 //
347 // Check if OS has enabled XGETBV instruction to access XCR0
348 // (OSXSAVE feature flag) and CPU supports AVX
349 //
350 __ lea(rsi, Address(rbp, in_bytes(VM_Version::std_cpuid1_offset())));
351 __ movl(rcx, 0x18000000); // cpuid1 bits osxsave | avx
352 __ andl(rcx, Address(rsi, 8)); // cpuid1 bits osxsave | avx
353 __ cmpl(rcx, 0x18000000);
354 __ jccb(Assembler::notEqual, done); // jump if AVX is not supported
355
356 __ movl(rax, 0x6);
357 __ andl(rax, Address(rbp, in_bytes(VM_Version::xem_xcr0_offset()))); // xcr0 bits sse | ymm
358 __ cmpl(rax, 0x6);
359 __ jccb(Assembler::equal, start_simd_check); // return if AVX is not supported
360
361 // we need to bridge farther than imm8, so we use this island as a thunk
362 __ bind(done);
363 __ jmp(wrapup);
364
365 __ bind(start_simd_check);
366 //
367 // Some OSs have a bug when upper 128/256bits of YMM/ZMM
368 // registers are not restored after a signal processing.
369 // Generate SEGV here (reference through NULL)
370 // and check upper YMM/ZMM bits after it.
371 //
372 intx saved_useavx = UseAVX;
373 intx saved_usesse = UseSSE;
374
375 // If UseAVX is unitialized or is set by the user to include EVEX
376 if (use_evex) {
377 // check _cpuid_info.sef_cpuid7_ebx.bits.avx512f
378 __ lea(rsi, Address(rbp, in_bytes(VM_Version::sef_cpuid7_offset())));
379 __ movl(rax, 0x10000);
380 __ andl(rax, Address(rsi, 4)); // xcr0 bits sse | ymm
381 __ cmpl(rax, 0x10000);
382 __ jccb(Assembler::notEqual, legacy_setup); // jump if EVEX is not supported
383 // check _cpuid_info.xem_xcr0_eax.bits.opmask
384 // check _cpuid_info.xem_xcr0_eax.bits.zmm512
385 // check _cpuid_info.xem_xcr0_eax.bits.zmm32
386 __ movl(rax, 0xE0);
387 __ andl(rax, Address(rbp, in_bytes(VM_Version::xem_xcr0_offset()))); // xcr0 bits sse | ymm
388 __ cmpl(rax, 0xE0);
389 __ jccb(Assembler::notEqual, legacy_setup); // jump if EVEX is not supported
390
391 if (FLAG_IS_DEFAULT(UseAVX)) {
392 __ lea(rsi, Address(rbp, in_bytes(VM_Version::std_cpuid1_offset())));
393 __ movl(rax, Address(rsi, 0));
394 __ cmpl(rax, 0x50654); // If it is Skylake
395 __ jcc(Assembler::equal, legacy_setup);
396 }
397 // EVEX setup: run in lowest evex mode
398 VM_Version::set_evex_cpuFeatures(); // Enable temporary to pass asserts
399 UseAVX = 3;
400 UseSSE = 2;
401 #ifdef _WINDOWS
402 // xmm5-xmm15 are not preserved by caller on windows
403 // https://msdn.microsoft.com/en-us/library/9z1stfyw.aspx
404 __ subptr(rsp, 64);
405 __ evmovdqul(Address(rsp, 0), xmm7, Assembler::AVX_512bit);
406 #ifdef _LP64
407 __ subptr(rsp, 64);
408 __ evmovdqul(Address(rsp, 0), xmm8, Assembler::AVX_512bit);
409 __ subptr(rsp, 64);
410 __ evmovdqul(Address(rsp, 0), xmm31, Assembler::AVX_512bit);
411 #endif // _LP64
412 #endif // _WINDOWS
413
414 // load value into all 64 bytes of zmm7 register
415 __ movl(rcx, VM_Version::ymm_test_value());
416 __ movdl(xmm0, rcx);
417 __ vpbroadcastd(xmm0, xmm0, Assembler::AVX_512bit);
418 __ evmovdqul(xmm7, xmm0, Assembler::AVX_512bit);
419 #ifdef _LP64
420 __ evmovdqul(xmm8, xmm0, Assembler::AVX_512bit);
421 __ evmovdqul(xmm31, xmm0, Assembler::AVX_512bit);
422 #endif
423 VM_Version::clean_cpuFeatures();
424 __ jmp(save_restore_except);
425 }
426
427 __ bind(legacy_setup);
428 // AVX setup
429 VM_Version::set_avx_cpuFeatures(); // Enable temporary to pass asserts
430 UseAVX = 1;
431 UseSSE = 2;
432 #ifdef _WINDOWS
433 __ subptr(rsp, 32);
434 __ vmovdqu(Address(rsp, 0), xmm7);
435 #ifdef _LP64
436 __ subptr(rsp, 32);
437 __ vmovdqu(Address(rsp, 0), xmm8);
438 __ subptr(rsp, 32);
439 __ vmovdqu(Address(rsp, 0), xmm15);
440 #endif // _LP64
441 #endif // _WINDOWS
442
443 // load value into all 32 bytes of ymm7 register
444 __ movl(rcx, VM_Version::ymm_test_value());
445
446 __ movdl(xmm0, rcx);
447 __ pshufd(xmm0, xmm0, 0x00);
448 __ vinsertf128_high(xmm0, xmm0);
449 __ vmovdqu(xmm7, xmm0);
450 #ifdef _LP64
451 __ vmovdqu(xmm8, xmm0);
452 __ vmovdqu(xmm15, xmm0);
453 #endif
454 VM_Version::clean_cpuFeatures();
455
456 __ bind(save_restore_except);
457 __ xorl(rsi, rsi);
458 VM_Version::set_cpuinfo_segv_addr(__ pc());
459 // Generate SEGV
460 __ movl(rax, Address(rsi, 0));
461
462 VM_Version::set_cpuinfo_cont_addr(__ pc());
463 // Returns here after signal. Save xmm0 to check it later.
464
465 // If UseAVX is unitialized or is set by the user to include EVEX
466 if (use_evex) {
467 // check _cpuid_info.sef_cpuid7_ebx.bits.avx512f
468 __ lea(rsi, Address(rbp, in_bytes(VM_Version::sef_cpuid7_offset())));
469 __ movl(rax, 0x10000);
470 __ andl(rax, Address(rsi, 4));
471 __ cmpl(rax, 0x10000);
472 __ jcc(Assembler::notEqual, legacy_save_restore);
473 // check _cpuid_info.xem_xcr0_eax.bits.opmask
474 // check _cpuid_info.xem_xcr0_eax.bits.zmm512
475 // check _cpuid_info.xem_xcr0_eax.bits.zmm32
476 __ movl(rax, 0xE0);
477 __ andl(rax, Address(rbp, in_bytes(VM_Version::xem_xcr0_offset()))); // xcr0 bits sse | ymm
478 __ cmpl(rax, 0xE0);
479 __ jcc(Assembler::notEqual, legacy_save_restore);
480
481 if (FLAG_IS_DEFAULT(UseAVX)) {
482 __ lea(rsi, Address(rbp, in_bytes(VM_Version::std_cpuid1_offset())));
483 __ movl(rax, Address(rsi, 0));
484 __ cmpl(rax, 0x50654); // If it is Skylake
485 __ jcc(Assembler::equal, legacy_save_restore);
486 }
487 // EVEX check: run in lowest evex mode
488 VM_Version::set_evex_cpuFeatures(); // Enable temporary to pass asserts
489 UseAVX = 3;
490 UseSSE = 2;
491 __ lea(rsi, Address(rbp, in_bytes(VM_Version::zmm_save_offset())));
492 __ evmovdqul(Address(rsi, 0), xmm0, Assembler::AVX_512bit);
493 __ evmovdqul(Address(rsi, 64), xmm7, Assembler::AVX_512bit);
494 #ifdef _LP64
495 __ evmovdqul(Address(rsi, 128), xmm8, Assembler::AVX_512bit);
496 __ evmovdqul(Address(rsi, 192), xmm31, Assembler::AVX_512bit);
497 #endif
498
499 #ifdef _WINDOWS
500 #ifdef _LP64
501 __ evmovdqul(xmm31, Address(rsp, 0), Assembler::AVX_512bit);
502 __ addptr(rsp, 64);
503 __ evmovdqul(xmm8, Address(rsp, 0), Assembler::AVX_512bit);
504 __ addptr(rsp, 64);
505 #endif // _LP64
506 __ evmovdqul(xmm7, Address(rsp, 0), Assembler::AVX_512bit);
507 __ addptr(rsp, 64);
508 #endif // _WINDOWS
509 generate_vzeroupper(wrapup);
510 VM_Version::clean_cpuFeatures();
511 UseAVX = saved_useavx;
512 UseSSE = saved_usesse;
513 __ jmp(wrapup);
514 }
515
516 __ bind(legacy_save_restore);
517 // AVX check
518 VM_Version::set_avx_cpuFeatures(); // Enable temporary to pass asserts
519 UseAVX = 1;
520 UseSSE = 2;
521 __ lea(rsi, Address(rbp, in_bytes(VM_Version::ymm_save_offset())));
522 __ vmovdqu(Address(rsi, 0), xmm0);
523 __ vmovdqu(Address(rsi, 32), xmm7);
524 #ifdef _LP64
525 __ vmovdqu(Address(rsi, 64), xmm8);
526 __ vmovdqu(Address(rsi, 96), xmm15);
527 #endif
528
529 #ifdef _WINDOWS
530 #ifdef _LP64
531 __ vmovdqu(xmm15, Address(rsp, 0));
532 __ addptr(rsp, 32);
533 __ vmovdqu(xmm8, Address(rsp, 0));
534 __ addptr(rsp, 32);
535 #endif // _LP64
536 __ vmovdqu(xmm7, Address(rsp, 0));
537 __ addptr(rsp, 32);
538 #endif // _WINDOWS
539 generate_vzeroupper(wrapup);
540 VM_Version::clean_cpuFeatures();
541 UseAVX = saved_useavx;
542 UseSSE = saved_usesse;
543
544 __ bind(wrapup);
545 __ popf();
546 __ pop(rsi);
547 __ pop(rbx);
548 __ pop(rbp);
549 __ ret(0);
550
551 # undef __
552
553 return start;
554 };
555 void generate_vzeroupper(Label& L_wrapup) {
556 # define __ _masm->
557 __ lea(rsi, Address(rbp, in_bytes(VM_Version::std_cpuid0_offset())));
558 __ cmpl(Address(rsi, 4), 0x756e6547); // 'uneG'
559 __ jcc(Assembler::notEqual, L_wrapup);
560 __ movl(rcx, 0x0FFF0FF0);
561 __ lea(rsi, Address(rbp, in_bytes(VM_Version::std_cpuid1_offset())));
562 __ andl(rcx, Address(rsi, 0));
563 __ cmpl(rcx, 0x00050670); // If it is Xeon Phi 3200/5200/7200
564 __ jcc(Assembler::equal, L_wrapup);
565 __ cmpl(rcx, 0x00080650); // If it is Future Xeon Phi
566 __ jcc(Assembler::equal, L_wrapup);
567 // vzeroupper() will use a pre-computed instruction sequence that we
568 // can't compute until after we've determined CPU capabilities. Use
569 // uncached variant here directly to be able to bootstrap correctly
570 __ vzeroupper_uncached();
571 # undef __
572 }
573 address generate_detect_virt() {
574 StubCodeMark mark(this, "VM_Version", "detect_virt_stub");
575 # define __ _masm->
576
577 address start = __ pc();
578
579 // Evacuate callee-saved registers
580 __ push(rbp);
581 __ push(rbx);
582 __ push(rsi); // for Windows
583
584 #ifdef _LP64
585 __ mov(rax, c_rarg0); // CPUID leaf
586 __ mov(rsi, c_rarg1); // register array address (eax, ebx, ecx, edx)
587 #else
588 __ movptr(rax, Address(rsp, 16)); // CPUID leaf
589 __ movptr(rsi, Address(rsp, 20)); // register array address
590 #endif
591
592 __ cpuid();
593
594 // Store result to register array
595 __ movl(Address(rsi, 0), rax);
596 __ movl(Address(rsi, 4), rbx);
597 __ movl(Address(rsi, 8), rcx);
598 __ movl(Address(rsi, 12), rdx);
599
600 // Epilogue
601 __ pop(rsi);
602 __ pop(rbx);
603 __ pop(rbp);
604 __ ret(0);
605
606 # undef __
607
608 return start;
609 };
610 };
611
612 void VM_Version::get_processor_features() {
613
614 _cpu = 4; // 486 by default
615 _model = 0;
616 _stepping = 0;
617 _features = 0;
618 _logical_processors_per_package = 1;
619 // i486 internal cache is both I&D and has a 16-byte line size
620 _L1_data_cache_line_size = 16;
621
622 // Get raw processor info
623
624 get_cpu_info_stub(&_cpuid_info);
625
626 assert_is_initialized();
627 _cpu = extended_cpu_family();
628 _model = extended_cpu_model();
629 _stepping = cpu_stepping();
630
631 if (cpu_family() > 4) { // it supports CPUID
632 _features = feature_flags();
633 // Logical processors are only available on P4s and above,
634 // and only if hyperthreading is available.
635 _logical_processors_per_package = logical_processor_count();
636 _L1_data_cache_line_size = L1_line_size();
637 }
638
639 _supports_cx8 = supports_cmpxchg8();
640 // xchg and xadd instructions
641 _supports_atomic_getset4 = true;
642 _supports_atomic_getadd4 = true;
643 LP64_ONLY(_supports_atomic_getset8 = true);
644 LP64_ONLY(_supports_atomic_getadd8 = true);
645
646 #ifdef _LP64
647 // OS should support SSE for x64 and hardware should support at least SSE2.
648 if (!VM_Version::supports_sse2()) {
649 vm_exit_during_initialization("Unknown x64 processor: SSE2 not supported");
650 }
651 // in 64 bit the use of SSE2 is the minimum
652 if (UseSSE < 2) UseSSE = 2;
653 #endif
654
655 #ifdef AMD64
656 // flush_icache_stub have to be generated first.
657 // That is why Icache line size is hard coded in ICache class,
658 // see icache_x86.hpp. It is also the reason why we can't use
659 // clflush instruction in 32-bit VM since it could be running
660 // on CPU which does not support it.
661 //
662 // The only thing we can do is to verify that flushed
663 // ICache::line_size has correct value.
664 guarantee(_cpuid_info.std_cpuid1_edx.bits.clflush != 0, "clflush is not supported");
665 // clflush_size is size in quadwords (8 bytes).
666 guarantee(_cpuid_info.std_cpuid1_ebx.bits.clflush_size == 8, "such clflush size is not supported");
667 #endif
668
669 #ifdef _LP64
670 // assigning this field effectively enables Unsafe.writebackMemory()
671 // by initing UnsafeConstant.DATA_CACHE_LINE_FLUSH_SIZE to non-zero
672 // that is only implemented on x86_64 and only if the OS plays ball
673 if (os::supports_map_sync()) {
674 // publish data cache line flush size to generic field, otherwise
675 // let if default to zero thereby disabling writeback
676 _data_cache_line_flush_size = _cpuid_info.std_cpuid1_ebx.bits.clflush_size * 8;
677 }
678 #endif
679 // If the OS doesn't support SSE, we can't use this feature even if the HW does
680 if (!os::supports_sse())
681 _features &= ~(CPU_SSE|CPU_SSE2|CPU_SSE3|CPU_SSSE3|CPU_SSE4A|CPU_SSE4_1|CPU_SSE4_2);
682
683 if (UseSSE < 4) {
684 _features &= ~CPU_SSE4_1;
685 _features &= ~CPU_SSE4_2;
686 }
687
688 if (UseSSE < 3) {
689 _features &= ~CPU_SSE3;
690 _features &= ~CPU_SSSE3;
691 _features &= ~CPU_SSE4A;
692 }
693
694 if (UseSSE < 2)
695 _features &= ~CPU_SSE2;
696
697 if (UseSSE < 1)
698 _features &= ~CPU_SSE;
699
700 //since AVX instructions is slower than SSE in some ZX cpus, force USEAVX=0.
701 if (is_zx() && ((cpu_family() == 6) || (cpu_family() == 7))) {
702 UseAVX = 0;
703 }
704
705 // first try initial setting and detect what we can support
706 int use_avx_limit = 0;
707 if (UseAVX > 0) {
708 if (UseAVX > 2 && supports_evex()) {
709 use_avx_limit = 3;
710 } else if (UseAVX > 1 && supports_avx2()) {
711 use_avx_limit = 2;
712 } else if (UseAVX > 0 && supports_avx()) {
713 use_avx_limit = 1;
714 } else {
715 use_avx_limit = 0;
716 }
717 }
718 if (FLAG_IS_DEFAULT(UseAVX)) {
719 // Don't use AVX-512 on older Skylakes unless explicitly requested.
720 if (use_avx_limit > 2 && is_intel_skylake() && _stepping < 5) {
721 FLAG_SET_DEFAULT(UseAVX, 2);
722 } else {
723 FLAG_SET_DEFAULT(UseAVX, use_avx_limit);
724 }
725 }
726 if (UseAVX > use_avx_limit) {
727 warning("UseAVX=%d is not supported on this CPU, setting it to UseAVX=%d", (int) UseAVX, use_avx_limit);
728 FLAG_SET_DEFAULT(UseAVX, use_avx_limit);
729 } else if (UseAVX < 0) {
730 warning("UseAVX=%d is not valid, setting it to UseAVX=0", (int) UseAVX);
731 FLAG_SET_DEFAULT(UseAVX, 0);
732 }
733
734 if (UseAVX < 3) {
735 _features &= ~CPU_AVX512F;
736 _features &= ~CPU_AVX512DQ;
737 _features &= ~CPU_AVX512CD;
738 _features &= ~CPU_AVX512BW;
739 _features &= ~CPU_AVX512VL;
740 _features &= ~CPU_AVX512_VPOPCNTDQ;
741 _features &= ~CPU_AVX512_VPCLMULQDQ;
742 _features &= ~CPU_AVX512_VAES;
743 _features &= ~CPU_AVX512_VNNI;
744 _features &= ~CPU_AVX512_VBMI;
745 _features &= ~CPU_AVX512_VBMI2;
746 }
747
748 if (UseAVX < 2)
749 _features &= ~CPU_AVX2;
750
751 if (UseAVX < 1) {
752 _features &= ~CPU_AVX;
753 _features &= ~CPU_VZEROUPPER;
754 }
755
756 if (logical_processors_per_package() == 1) {
757 // HT processor could be installed on a system which doesn't support HT.
758 _features &= ~CPU_HT;
759 }
760
761 if (is_intel()) { // Intel cpus specific settings
762 if (is_knights_family()) {
763 _features &= ~CPU_VZEROUPPER;
764 }
765 }
766
767 if (FLAG_IS_DEFAULT(IntelJccErratumMitigation)) {
768 _has_intel_jcc_erratum = compute_has_intel_jcc_erratum();
769 } else {
770 _has_intel_jcc_erratum = IntelJccErratumMitigation;
771 }
772
773 char buf[512];
774 int res = jio_snprintf(buf, sizeof(buf),
775 "(%u cores per cpu, %u threads per core) family %d model %d stepping %d microcode 0x%x"
776 "%s%s%s%s%s%s%s%s%s%s" "%s%s%s%s%s%s%s%s%s%s" "%s%s%s%s%s%s%s%s%s%s" "%s%s%s%s%s%s%s%s%s%s" "%s%s%s%s%s%s",
777
778 cores_per_cpu(), threads_per_core(),
779 cpu_family(), _model, _stepping, os::cpu_microcode_revision(),
780
781 (supports_cmov() ? ", cmov" : ""),
782 (supports_cmpxchg8() ? ", cx8" : ""),
783 (supports_fxsr() ? ", fxsr" : ""),
784 (supports_mmx() ? ", mmx" : ""),
785 (supports_sse() ? ", sse" : ""),
786 (supports_sse2() ? ", sse2" : ""),
787 (supports_sse3() ? ", sse3" : ""),
788 (supports_ssse3()? ", ssse3": ""),
789 (supports_sse4_1() ? ", sse4.1" : ""),
790 (supports_sse4_2() ? ", sse4.2" : ""),
791
792 (supports_popcnt() ? ", popcnt" : ""),
793 (supports_vzeroupper() ? ", vzeroupper" : ""),
794 (supports_avx() ? ", avx" : ""),
795 (supports_avx2() ? ", avx2" : ""),
796 (supports_aes() ? ", aes" : ""),
797 (supports_clmul() ? ", clmul" : ""),
798 (supports_erms() ? ", erms" : ""),
799 (supports_rtm() ? ", rtm" : ""),
800 (supports_3dnow_prefetch() ? ", 3dnowpref" : ""),
801 (supports_lzcnt() ? ", lzcnt": ""),
802
803 (supports_sse4a() ? ", sse4a": ""),
804 (supports_ht() ? ", ht": ""),
805 (supports_tsc() ? ", tsc": ""),
806 (supports_tscinv_bit() ? ", tscinvbit": ""),
807 (supports_tscinv() ? ", tscinv": ""),
808 (supports_bmi1() ? ", bmi1" : ""),
809 (supports_bmi2() ? ", bmi2" : ""),
810 (supports_adx() ? ", adx" : ""),
811 (supports_evex() ? ", avx512f" : ""),
812 (supports_avx512dq() ? ", avx512dq" : ""),
813
814 (supports_avx512pf() ? ", avx512pf" : ""),
815 (supports_avx512er() ? ", avx512er" : ""),
816 (supports_avx512cd() ? ", avx512cd" : ""),
817 (supports_avx512bw() ? ", avx512bw" : ""),
818 (supports_avx512vl() ? ", avx512vl" : ""),
819 (supports_avx512_vpopcntdq() ? ", avx512_vpopcntdq" : ""),
820 (supports_avx512_vpclmulqdq() ? ", avx512_vpclmulqdq" : ""),
821 (supports_avx512_vbmi() ? ", avx512_vbmi" : ""),
822 (supports_avx512_vbmi2() ? ", avx512_vbmi2" : ""),
823 (supports_avx512_vaes() ? ", avx512_vaes" : ""),
824
825 (supports_avx512_vnni() ? ", avx512_vnni" : ""),
826 (supports_sha() ? ", sha" : ""),
827 (supports_fma() ? ", fma" : ""),
828 (supports_clflush() ? ", clflush" : ""),
829 (supports_clflushopt() ? ", clflushopt" : ""),
830 (supports_clwb() ? ", clwb" : ""));
831
832 assert(res > 0, "not enough temporary space allocated"); // increase 'buf' size
833
834 _features_string = os::strdup(buf);
835
836 // UseSSE is set to the smaller of what hardware supports and what
837 // the command line requires. I.e., you cannot set UseSSE to 2 on
838 // older Pentiums which do not support it.
839 int use_sse_limit = 0;
840 if (UseSSE > 0) {
841 if (UseSSE > 3 && supports_sse4_1()) {
842 use_sse_limit = 4;
843 } else if (UseSSE > 2 && supports_sse3()) {
844 use_sse_limit = 3;
845 } else if (UseSSE > 1 && supports_sse2()) {
846 use_sse_limit = 2;
847 } else if (UseSSE > 0 && supports_sse()) {
848 use_sse_limit = 1;
849 } else {
850 use_sse_limit = 0;
851 }
852 }
853 if (FLAG_IS_DEFAULT(UseSSE)) {
854 FLAG_SET_DEFAULT(UseSSE, use_sse_limit);
855 } else if (UseSSE > use_sse_limit) {
856 warning("UseSSE=%d is not supported on this CPU, setting it to UseSSE=%d", (int) UseSSE, use_sse_limit);
857 FLAG_SET_DEFAULT(UseSSE, use_sse_limit);
858 } else if (UseSSE < 0) {
859 warning("UseSSE=%d is not valid, setting it to UseSSE=0", (int) UseSSE);
860 FLAG_SET_DEFAULT(UseSSE, 0);
861 }
862
863 // Use AES instructions if available.
864 if (supports_aes()) {
865 if (FLAG_IS_DEFAULT(UseAES)) {
866 FLAG_SET_DEFAULT(UseAES, true);
867 }
868 if (!UseAES) {
869 if (UseAESIntrinsics && !FLAG_IS_DEFAULT(UseAESIntrinsics)) {
870 warning("AES intrinsics require UseAES flag to be enabled. Intrinsics will be disabled.");
871 }
872 FLAG_SET_DEFAULT(UseAESIntrinsics, false);
873 } else {
874 if (UseSSE > 2) {
875 if (FLAG_IS_DEFAULT(UseAESIntrinsics)) {
876 FLAG_SET_DEFAULT(UseAESIntrinsics, true);
877 }
878 } else {
879 // The AES intrinsic stubs require AES instruction support (of course)
880 // but also require sse3 mode or higher for instructions it use.
881 if (UseAESIntrinsics && !FLAG_IS_DEFAULT(UseAESIntrinsics)) {
882 warning("X86 AES intrinsics require SSE3 instructions or higher. Intrinsics will be disabled.");
883 }
884 FLAG_SET_DEFAULT(UseAESIntrinsics, false);
885 }
886
887 // --AES-CTR begins--
888 if (!UseAESIntrinsics) {
889 if (UseAESCTRIntrinsics && !FLAG_IS_DEFAULT(UseAESCTRIntrinsics)) {
890 warning("AES-CTR intrinsics require UseAESIntrinsics flag to be enabled. Intrinsics will be disabled.");
891 FLAG_SET_DEFAULT(UseAESCTRIntrinsics, false);
892 }
893 } else {
894 if (supports_sse4_1()) {
895 if (FLAG_IS_DEFAULT(UseAESCTRIntrinsics)) {
896 FLAG_SET_DEFAULT(UseAESCTRIntrinsics, true);
897 }
898 } else {
899 // The AES-CTR intrinsic stubs require AES instruction support (of course)
900 // but also require sse4.1 mode or higher for instructions it use.
901 if (UseAESCTRIntrinsics && !FLAG_IS_DEFAULT(UseAESCTRIntrinsics)) {
902 warning("X86 AES-CTR intrinsics require SSE4.1 instructions or higher. Intrinsics will be disabled.");
903 }
904 FLAG_SET_DEFAULT(UseAESCTRIntrinsics, false);
905 }
906 }
907 // --AES-CTR ends--
908 }
909 } else if (UseAES || UseAESIntrinsics || UseAESCTRIntrinsics) {
910 if (UseAES && !FLAG_IS_DEFAULT(UseAES)) {
911 warning("AES instructions are not available on this CPU");
912 FLAG_SET_DEFAULT(UseAES, false);
913 }
914 if (UseAESIntrinsics && !FLAG_IS_DEFAULT(UseAESIntrinsics)) {
915 warning("AES intrinsics are not available on this CPU");
916 FLAG_SET_DEFAULT(UseAESIntrinsics, false);
917 }
918 if (UseAESCTRIntrinsics && !FLAG_IS_DEFAULT(UseAESCTRIntrinsics)) {
919 warning("AES-CTR intrinsics are not available on this CPU");
920 FLAG_SET_DEFAULT(UseAESCTRIntrinsics, false);
921 }
922 }
923
924 // Use CLMUL instructions if available.
925 if (supports_clmul()) {
926 if (FLAG_IS_DEFAULT(UseCLMUL)) {
927 UseCLMUL = true;
928 }
929 } else if (UseCLMUL) {
930 if (!FLAG_IS_DEFAULT(UseCLMUL))
931 warning("CLMUL instructions not available on this CPU (AVX may also be required)");
932 FLAG_SET_DEFAULT(UseCLMUL, false);
933 }
934
935 if (UseCLMUL && (UseSSE > 2)) {
936 if (FLAG_IS_DEFAULT(UseCRC32Intrinsics)) {
937 UseCRC32Intrinsics = true;
938 }
939 } else if (UseCRC32Intrinsics) {
940 if (!FLAG_IS_DEFAULT(UseCRC32Intrinsics))
941 warning("CRC32 Intrinsics requires CLMUL instructions (not available on this CPU)");
942 FLAG_SET_DEFAULT(UseCRC32Intrinsics, false);
943 }
944
945 if (supports_sse4_2() && supports_clmul()) {
946 if (FLAG_IS_DEFAULT(UseCRC32CIntrinsics)) {
947 UseCRC32CIntrinsics = true;
948 }
949 } else if (UseCRC32CIntrinsics) {
950 if (!FLAG_IS_DEFAULT(UseCRC32CIntrinsics)) {
951 warning("CRC32C intrinsics are not available on this CPU");
952 }
953 FLAG_SET_DEFAULT(UseCRC32CIntrinsics, false);
954 }
955
956 // GHASH/GCM intrinsics
957 if (UseCLMUL && (UseSSE > 2)) {
958 if (FLAG_IS_DEFAULT(UseGHASHIntrinsics)) {
959 UseGHASHIntrinsics = true;
960 }
961 } else if (UseGHASHIntrinsics) {
962 if (!FLAG_IS_DEFAULT(UseGHASHIntrinsics))
963 warning("GHASH intrinsic requires CLMUL and SSE2 instructions on this CPU");
964 FLAG_SET_DEFAULT(UseGHASHIntrinsics, false);
965 }
966
967 // Base64 Intrinsics (Check the condition for which the intrinsic will be active)
968 if ((UseAVX > 2) && supports_avx512vl() && supports_avx512bw()) {
969 if (FLAG_IS_DEFAULT(UseBASE64Intrinsics)) {
970 UseBASE64Intrinsics = true;
971 }
972 } else if (UseBASE64Intrinsics) {
973 if (!FLAG_IS_DEFAULT(UseBASE64Intrinsics))
974 warning("Base64 intrinsic requires EVEX instructions on this CPU");
975 FLAG_SET_DEFAULT(UseBASE64Intrinsics, false);
976 }
977
978 if (supports_fma() && UseSSE >= 2) { // Check UseSSE since FMA code uses SSE instructions
979 if (FLAG_IS_DEFAULT(UseFMA)) {
980 UseFMA = true;
981 }
982 } else if (UseFMA) {
983 warning("FMA instructions are not available on this CPU");
984 FLAG_SET_DEFAULT(UseFMA, false);
985 }
986
987 if (FLAG_IS_DEFAULT(UseMD5Intrinsics)) {
988 UseMD5Intrinsics = true;
989 }
990
991 if (supports_sha() LP64_ONLY(|| supports_avx2() && supports_bmi2())) {
992 if (FLAG_IS_DEFAULT(UseSHA)) {
993 UseSHA = true;
994 }
995 } else if (UseSHA) {
996 warning("SHA instructions are not available on this CPU");
997 FLAG_SET_DEFAULT(UseSHA, false);
998 }
999
1000 if (supports_sha() && supports_sse4_1() && UseSHA) {
1001 if (FLAG_IS_DEFAULT(UseSHA1Intrinsics)) {
1002 FLAG_SET_DEFAULT(UseSHA1Intrinsics, true);
1003 }
1004 } else if (UseSHA1Intrinsics) {
1005 warning("Intrinsics for SHA-1 crypto hash functions not available on this CPU.");
1006 FLAG_SET_DEFAULT(UseSHA1Intrinsics, false);
1007 }
1008
1009 if (supports_sse4_1() && UseSHA) {
1010 if (FLAG_IS_DEFAULT(UseSHA256Intrinsics)) {
1011 FLAG_SET_DEFAULT(UseSHA256Intrinsics, true);
1012 }
1013 } else if (UseSHA256Intrinsics) {
1014 warning("Intrinsics for SHA-224 and SHA-256 crypto hash functions not available on this CPU.");
1015 FLAG_SET_DEFAULT(UseSHA256Intrinsics, false);
1016 }
1017
1018 #ifdef _LP64
1019 // These are only supported on 64-bit
1020 if (UseSHA && supports_avx2() && supports_bmi2()) {
1021 if (FLAG_IS_DEFAULT(UseSHA512Intrinsics)) {
1022 FLAG_SET_DEFAULT(UseSHA512Intrinsics, true);
1023 }
1024 } else
1025 #endif
1026 if (UseSHA512Intrinsics) {
1027 warning("Intrinsics for SHA-384 and SHA-512 crypto hash functions not available on this CPU.");
1028 FLAG_SET_DEFAULT(UseSHA512Intrinsics, false);
1029 }
1030
1031 if (!(UseSHA1Intrinsics || UseSHA256Intrinsics || UseSHA512Intrinsics)) {
1032 FLAG_SET_DEFAULT(UseSHA, false);
1033 }
1034
1035 if (UseAdler32Intrinsics) {
1036 warning("Adler32Intrinsics not available on this CPU.");
1037 FLAG_SET_DEFAULT(UseAdler32Intrinsics, false);
1038 }
1039
1040 if (!supports_rtm() && UseRTMLocking) {
1041 // Can't continue because UseRTMLocking affects UseBiasedLocking flag
1042 // setting during arguments processing. See use_biased_locking().
1043 // VM_Version_init() is executed after UseBiasedLocking is used
1044 // in Thread::allocate().
1045 vm_exit_during_initialization("RTM instructions are not available on this CPU");
1046 }
1047
1048 #if INCLUDE_RTM_OPT
1049 if (UseRTMLocking) {
1050 if (is_client_compilation_mode_vm()) {
1051 // Only C2 does RTM locking optimization.
1052 // Can't continue because UseRTMLocking affects UseBiasedLocking flag
1053 // setting during arguments processing. See use_biased_locking().
1054 vm_exit_during_initialization("RTM locking optimization is not supported in this VM");
1055 }
1056 if (is_intel_family_core()) {
1057 if ((_model == CPU_MODEL_HASWELL_E3) ||
1058 (_model == CPU_MODEL_HASWELL_E7 && _stepping < 3) ||
1059 (_model == CPU_MODEL_BROADWELL && _stepping < 4)) {
1060 // currently a collision between SKL and HSW_E3
1061 if (!UnlockExperimentalVMOptions && UseAVX < 3) {
1062 vm_exit_during_initialization("UseRTMLocking is only available as experimental option on this "
1063 "platform. It must be enabled via -XX:+UnlockExperimentalVMOptions flag.");
1064 } else {
1065 warning("UseRTMLocking is only available as experimental option on this platform.");
1066 }
1067 }
1068 }
1069 if (!FLAG_IS_CMDLINE(UseRTMLocking)) {
1070 // RTM locking should be used only for applications with
1071 // high lock contention. For now we do not use it by default.
1072 vm_exit_during_initialization("UseRTMLocking flag should be only set on command line");
1073 }
1074 } else { // !UseRTMLocking
1075 if (UseRTMForStackLocks) {
1076 if (!FLAG_IS_DEFAULT(UseRTMForStackLocks)) {
1077 warning("UseRTMForStackLocks flag should be off when UseRTMLocking flag is off");
1078 }
1079 FLAG_SET_DEFAULT(UseRTMForStackLocks, false);
1080 }
1081 if (UseRTMDeopt) {
1082 FLAG_SET_DEFAULT(UseRTMDeopt, false);
1083 }
1084 if (PrintPreciseRTMLockingStatistics) {
1085 FLAG_SET_DEFAULT(PrintPreciseRTMLockingStatistics, false);
1086 }
1087 }
1088 #else
1089 if (UseRTMLocking) {
1090 // Only C2 does RTM locking optimization.
1091 // Can't continue because UseRTMLocking affects UseBiasedLocking flag
1092 // setting during arguments processing. See use_biased_locking().
1093 vm_exit_during_initialization("RTM locking optimization is not supported in this VM");
1094 }
1095 #endif
1096
1097 #ifdef COMPILER2
1098 if (UseFPUForSpilling) {
1099 if (UseSSE < 2) {
1100 // Only supported with SSE2+
1101 FLAG_SET_DEFAULT(UseFPUForSpilling, false);
1102 }
1103 }
1104 #endif
1105
1106 #if COMPILER2_OR_JVMCI
1107 int max_vector_size = 0;
1108 if (UseSSE < 2) {
1109 // Vectors (in XMM) are only supported with SSE2+
1110 // SSE is always 2 on x64.
1111 max_vector_size = 0;
1112 } else if (UseAVX == 0 || !os_supports_avx_vectors()) {
1113 // 16 byte vectors (in XMM) are supported with SSE2+
1114 max_vector_size = 16;
1115 } else if (UseAVX == 1 || UseAVX == 2) {
1116 // 32 bytes vectors (in YMM) are only supported with AVX+
1117 max_vector_size = 32;
1118 } else if (UseAVX > 2) {
1119 // 64 bytes vectors (in ZMM) are only supported with AVX 3
1120 max_vector_size = 64;
1121 }
1122
1123 #ifdef _LP64
1124 int min_vector_size = 4; // We require MaxVectorSize to be at least 4 on 64bit
1125 #else
1126 int min_vector_size = 0;
1127 #endif
1128
1129 if (!FLAG_IS_DEFAULT(MaxVectorSize)) {
1130 if (MaxVectorSize < min_vector_size) {
1131 warning("MaxVectorSize must be at least %i on this platform", min_vector_size);
1132 FLAG_SET_DEFAULT(MaxVectorSize, min_vector_size);
1133 }
1134 if (MaxVectorSize > max_vector_size) {
1135 warning("MaxVectorSize must be at most %i on this platform", max_vector_size);
1136 FLAG_SET_DEFAULT(MaxVectorSize, max_vector_size);
1137 }
1138 if (!is_power_of_2(MaxVectorSize)) {
1139 warning("MaxVectorSize must be a power of 2, setting to default: %i", max_vector_size);
1140 FLAG_SET_DEFAULT(MaxVectorSize, max_vector_size);
1141 }
1142 } else {
1143 // If default, use highest supported configuration
1144 FLAG_SET_DEFAULT(MaxVectorSize, max_vector_size);
1145 }
1146
1147 #if defined(COMPILER2) && defined(ASSERT)
1148 if (MaxVectorSize > 0) {
1149 if (supports_avx() && PrintMiscellaneous && Verbose && TraceNewVectors) {
1150 tty->print_cr("State of YMM registers after signal handle:");
1151 int nreg = 2 LP64_ONLY(+2);
1152 const char* ymm_name[4] = {"0", "7", "8", "15"};
1153 for (int i = 0; i < nreg; i++) {
1154 tty->print("YMM%s:", ymm_name[i]);
1155 for (int j = 7; j >=0; j--) {
1156 tty->print(" %x", _cpuid_info.ymm_save[i*8 + j]);
1157 }
1158 tty->cr();
1159 }
1160 }
1161 }
1162 #endif // COMPILER2 && ASSERT
1163
1164 if (!FLAG_IS_DEFAULT(AVX3Threshold)) {
1165 if (!is_power_of_2(AVX3Threshold)) {
1166 warning("AVX3Threshold must be a power of 2");
1167 FLAG_SET_DEFAULT(AVX3Threshold, 4096);
1168 }
1169 }
1170
1171 #ifdef _LP64
1172 if (FLAG_IS_DEFAULT(UseMultiplyToLenIntrinsic)) {
1173 UseMultiplyToLenIntrinsic = true;
1174 }
1175 if (FLAG_IS_DEFAULT(UseSquareToLenIntrinsic)) {
1176 UseSquareToLenIntrinsic = true;
1177 }
1178 if (FLAG_IS_DEFAULT(UseMulAddIntrinsic)) {
1179 UseMulAddIntrinsic = true;
1180 }
1181 if (FLAG_IS_DEFAULT(UseMontgomeryMultiplyIntrinsic)) {
1182 UseMontgomeryMultiplyIntrinsic = true;
1183 }
1184 if (FLAG_IS_DEFAULT(UseMontgomerySquareIntrinsic)) {
1185 UseMontgomerySquareIntrinsic = true;
1186 }
1187 #else
1188 if (UseMultiplyToLenIntrinsic) {
1189 if (!FLAG_IS_DEFAULT(UseMultiplyToLenIntrinsic)) {
1190 warning("multiplyToLen intrinsic is not available in 32-bit VM");
1191 }
1192 FLAG_SET_DEFAULT(UseMultiplyToLenIntrinsic, false);
1193 }
1194 if (UseMontgomeryMultiplyIntrinsic) {
1195 if (!FLAG_IS_DEFAULT(UseMontgomeryMultiplyIntrinsic)) {
1196 warning("montgomeryMultiply intrinsic is not available in 32-bit VM");
1197 }
1198 FLAG_SET_DEFAULT(UseMontgomeryMultiplyIntrinsic, false);
1199 }
1200 if (UseMontgomerySquareIntrinsic) {
1201 if (!FLAG_IS_DEFAULT(UseMontgomerySquareIntrinsic)) {
1202 warning("montgomerySquare intrinsic is not available in 32-bit VM");
1203 }
1204 FLAG_SET_DEFAULT(UseMontgomerySquareIntrinsic, false);
1205 }
1206 if (UseSquareToLenIntrinsic) {
1207 if (!FLAG_IS_DEFAULT(UseSquareToLenIntrinsic)) {
1208 warning("squareToLen intrinsic is not available in 32-bit VM");
1209 }
1210 FLAG_SET_DEFAULT(UseSquareToLenIntrinsic, false);
1211 }
1212 if (UseMulAddIntrinsic) {
1213 if (!FLAG_IS_DEFAULT(UseMulAddIntrinsic)) {
1214 warning("mulAdd intrinsic is not available in 32-bit VM");
1215 }
1216 FLAG_SET_DEFAULT(UseMulAddIntrinsic, false);
1217 }
1218 #endif // _LP64
1219 #endif // COMPILER2_OR_JVMCI
1220
1221 // On new cpus instructions which update whole XMM register should be used
1222 // to prevent partial register stall due to dependencies on high half.
1223 //
1224 // UseXmmLoadAndClearUpper == true --> movsd(xmm, mem)
1225 // UseXmmLoadAndClearUpper == false --> movlpd(xmm, mem)
1226 // UseXmmRegToRegMoveAll == true --> movaps(xmm, xmm), movapd(xmm, xmm).
1227 // UseXmmRegToRegMoveAll == false --> movss(xmm, xmm), movsd(xmm, xmm).
1228
1229
1230 if (is_zx()) { // ZX cpus specific settings
1231 if (FLAG_IS_DEFAULT(UseStoreImmI16)) {
1232 UseStoreImmI16 = false; // don't use it on ZX cpus
1233 }
1234 if ((cpu_family() == 6) || (cpu_family() == 7)) {
1235 if (FLAG_IS_DEFAULT(UseAddressNop)) {
1236 // Use it on all ZX cpus
1237 UseAddressNop = true;
1238 }
1239 }
1240 if (FLAG_IS_DEFAULT(UseXmmLoadAndClearUpper)) {
1241 UseXmmLoadAndClearUpper = true; // use movsd on all ZX cpus
1242 }
1243 if (FLAG_IS_DEFAULT(UseXmmRegToRegMoveAll)) {
1244 if (supports_sse3()) {
1245 UseXmmRegToRegMoveAll = true; // use movaps, movapd on new ZX cpus
1246 } else {
1247 UseXmmRegToRegMoveAll = false;
1248 }
1249 }
1250 if (((cpu_family() == 6) || (cpu_family() == 7)) && supports_sse3()) { // new ZX cpus
1251 #ifdef COMPILER2
1252 if (FLAG_IS_DEFAULT(MaxLoopPad)) {
1253 // For new ZX cpus do the next optimization:
1254 // don't align the beginning of a loop if there are enough instructions
1255 // left (NumberOfLoopInstrToAlign defined in c2_globals.hpp)
1256 // in current fetch line (OptoLoopAlignment) or the padding
1257 // is big (> MaxLoopPad).
1258 // Set MaxLoopPad to 11 for new ZX cpus to reduce number of
1259 // generated NOP instructions. 11 is the largest size of one
1260 // address NOP instruction '0F 1F' (see Assembler::nop(i)).
1261 MaxLoopPad = 11;
1262 }
1263 #endif // COMPILER2
1264 if (FLAG_IS_DEFAULT(UseXMMForArrayCopy)) {
1265 UseXMMForArrayCopy = true; // use SSE2 movq on new ZX cpus
1266 }
1267 if (supports_sse4_2()) { // new ZX cpus
1268 if (FLAG_IS_DEFAULT(UseUnalignedLoadStores)) {
1269 UseUnalignedLoadStores = true; // use movdqu on newest ZX cpus
1270 }
1271 }
1272 if (supports_sse4_2()) {
1273 if (FLAG_IS_DEFAULT(UseSSE42Intrinsics)) {
1274 FLAG_SET_DEFAULT(UseSSE42Intrinsics, true);
1275 }
1276 } else {
1277 if (UseSSE42Intrinsics && !FLAG_IS_DEFAULT(UseAESIntrinsics)) {
1278 warning("SSE4.2 intrinsics require SSE4.2 instructions or higher. Intrinsics will be disabled.");
1279 }
1280 FLAG_SET_DEFAULT(UseSSE42Intrinsics, false);
1281 }
1282 }
1283
1284 if (FLAG_IS_DEFAULT(AllocatePrefetchInstr) && supports_3dnow_prefetch()) {
1285 FLAG_SET_DEFAULT(AllocatePrefetchInstr, 3);
1286 }
1287 }
1288
1289 if (is_amd_family()) { // AMD cpus specific settings
1290 if (supports_sse2() && FLAG_IS_DEFAULT(UseAddressNop)) {
1291 // Use it on new AMD cpus starting from Opteron.
1292 UseAddressNop = true;
1293 }
1294 if (supports_sse2() && FLAG_IS_DEFAULT(UseNewLongLShift)) {
1295 // Use it on new AMD cpus starting from Opteron.
1296 UseNewLongLShift = true;
1297 }
1298 if (FLAG_IS_DEFAULT(UseXmmLoadAndClearUpper)) {
1299 if (supports_sse4a()) {
1300 UseXmmLoadAndClearUpper = true; // use movsd only on '10h' Opteron
1301 } else {
1302 UseXmmLoadAndClearUpper = false;
1303 }
1304 }
1305 if (FLAG_IS_DEFAULT(UseXmmRegToRegMoveAll)) {
1306 if (supports_sse4a()) {
1307 UseXmmRegToRegMoveAll = true; // use movaps, movapd only on '10h'
1308 } else {
1309 UseXmmRegToRegMoveAll = false;
1310 }
1311 }
1312 if (FLAG_IS_DEFAULT(UseXmmI2F)) {
1313 if (supports_sse4a()) {
1314 UseXmmI2F = true;
1315 } else {
1316 UseXmmI2F = false;
1317 }
1318 }
1319 if (FLAG_IS_DEFAULT(UseXmmI2D)) {
1320 if (supports_sse4a()) {
1321 UseXmmI2D = true;
1322 } else {
1323 UseXmmI2D = false;
1324 }
1325 }
1326 if (supports_sse4_2()) {
1327 if (FLAG_IS_DEFAULT(UseSSE42Intrinsics)) {
1328 FLAG_SET_DEFAULT(UseSSE42Intrinsics, true);
1329 }
1330 } else {
1331 if (UseSSE42Intrinsics && !FLAG_IS_DEFAULT(UseAESIntrinsics)) {
1332 warning("SSE4.2 intrinsics require SSE4.2 instructions or higher. Intrinsics will be disabled.");
1333 }
1334 FLAG_SET_DEFAULT(UseSSE42Intrinsics, false);
1335 }
1336
1337 // some defaults for AMD family 15h
1338 if (cpu_family() == 0x15) {
1339 // On family 15h processors default is no sw prefetch
1340 if (FLAG_IS_DEFAULT(AllocatePrefetchStyle)) {
1341 FLAG_SET_DEFAULT(AllocatePrefetchStyle, 0);
1342 }
1343 // Also, if some other prefetch style is specified, default instruction type is PREFETCHW
1344 if (FLAG_IS_DEFAULT(AllocatePrefetchInstr)) {
1345 FLAG_SET_DEFAULT(AllocatePrefetchInstr, 3);
1346 }
1347 // On family 15h processors use XMM and UnalignedLoadStores for Array Copy
1348 if (supports_sse2() && FLAG_IS_DEFAULT(UseXMMForArrayCopy)) {
1349 FLAG_SET_DEFAULT(UseXMMForArrayCopy, true);
1350 }
1351 if (supports_sse2() && FLAG_IS_DEFAULT(UseUnalignedLoadStores)) {
1352 FLAG_SET_DEFAULT(UseUnalignedLoadStores, true);
1353 }
1354 }
1355
1356 #ifdef COMPILER2
1357 if (cpu_family() < 0x17 && MaxVectorSize > 16) {
1358 // Limit vectors size to 16 bytes on AMD cpus < 17h.
1359 FLAG_SET_DEFAULT(MaxVectorSize, 16);
1360 }
1361 #endif // COMPILER2
1362
1363 // Some defaults for AMD family 17h || Hygon family 18h
1364 if (cpu_family() == 0x17 || cpu_family() == 0x18) {
1365 // On family 17h processors use XMM and UnalignedLoadStores for Array Copy
1366 if (supports_sse2() && FLAG_IS_DEFAULT(UseXMMForArrayCopy)) {
1367 FLAG_SET_DEFAULT(UseXMMForArrayCopy, true);
1368 }
1369 if (supports_sse2() && FLAG_IS_DEFAULT(UseUnalignedLoadStores)) {
1370 FLAG_SET_DEFAULT(UseUnalignedLoadStores, true);
1371 }
1372 #ifdef COMPILER2
1373 if (supports_sse4_2() && FLAG_IS_DEFAULT(UseFPUForSpilling)) {
1374 FLAG_SET_DEFAULT(UseFPUForSpilling, true);
1375 }
1376 #endif
1377 }
1378 }
1379
1380 if (is_intel()) { // Intel cpus specific settings
1381 if (FLAG_IS_DEFAULT(UseStoreImmI16)) {
1382 UseStoreImmI16 = false; // don't use it on Intel cpus
1383 }
1384 if (cpu_family() == 6 || cpu_family() == 15) {
1385 if (FLAG_IS_DEFAULT(UseAddressNop)) {
1386 // Use it on all Intel cpus starting from PentiumPro
1387 UseAddressNop = true;
1388 }
1389 }
1390 if (FLAG_IS_DEFAULT(UseXmmLoadAndClearUpper)) {
1391 UseXmmLoadAndClearUpper = true; // use movsd on all Intel cpus
1392 }
1393 if (FLAG_IS_DEFAULT(UseXmmRegToRegMoveAll)) {
1394 if (supports_sse3()) {
1395 UseXmmRegToRegMoveAll = true; // use movaps, movapd on new Intel cpus
1396 } else {
1397 UseXmmRegToRegMoveAll = false;
1398 }
1399 }
1400 if (cpu_family() == 6 && supports_sse3()) { // New Intel cpus
1401 #ifdef COMPILER2
1402 if (FLAG_IS_DEFAULT(MaxLoopPad)) {
1403 // For new Intel cpus do the next optimization:
1404 // don't align the beginning of a loop if there are enough instructions
1405 // left (NumberOfLoopInstrToAlign defined in c2_globals.hpp)
1406 // in current fetch line (OptoLoopAlignment) or the padding
1407 // is big (> MaxLoopPad).
1408 // Set MaxLoopPad to 11 for new Intel cpus to reduce number of
1409 // generated NOP instructions. 11 is the largest size of one
1410 // address NOP instruction '0F 1F' (see Assembler::nop(i)).
1411 MaxLoopPad = 11;
1412 }
1413 #endif // COMPILER2
1414 if (FLAG_IS_DEFAULT(UseXMMForArrayCopy)) {
1415 UseXMMForArrayCopy = true; // use SSE2 movq on new Intel cpus
1416 }
1417 if ((supports_sse4_2() && supports_ht()) || supports_avx()) { // Newest Intel cpus
1418 if (FLAG_IS_DEFAULT(UseUnalignedLoadStores)) {
1419 UseUnalignedLoadStores = true; // use movdqu on newest Intel cpus
1420 }
1421 }
1422 if (supports_sse4_2()) {
1423 if (FLAG_IS_DEFAULT(UseSSE42Intrinsics)) {
1424 FLAG_SET_DEFAULT(UseSSE42Intrinsics, true);
1425 }
1426 } else {
1427 if (UseSSE42Intrinsics && !FLAG_IS_DEFAULT(UseAESIntrinsics)) {
1428 warning("SSE4.2 intrinsics require SSE4.2 instructions or higher. Intrinsics will be disabled.");
1429 }
1430 FLAG_SET_DEFAULT(UseSSE42Intrinsics, false);
1431 }
1432 }
1433 if (is_atom_family() || is_knights_family()) {
1434 #ifdef COMPILER2
1435 if (FLAG_IS_DEFAULT(OptoScheduling)) {
1436 OptoScheduling = true;
1437 }
1438 #endif
1439 if (supports_sse4_2()) { // Silvermont
1440 if (FLAG_IS_DEFAULT(UseUnalignedLoadStores)) {
1441 UseUnalignedLoadStores = true; // use movdqu on newest Intel cpus
1442 }
1443 }
1444 if (FLAG_IS_DEFAULT(UseIncDec)) {
1445 FLAG_SET_DEFAULT(UseIncDec, false);
1446 }
1447 }
1448 if (FLAG_IS_DEFAULT(AllocatePrefetchInstr) && supports_3dnow_prefetch()) {
1449 FLAG_SET_DEFAULT(AllocatePrefetchInstr, 3);
1450 }
1451 }
1452
1453 #ifdef _LP64
1454 if (UseSSE42Intrinsics) {
1455 if (FLAG_IS_DEFAULT(UseVectorizedMismatchIntrinsic)) {
1456 UseVectorizedMismatchIntrinsic = true;
1457 }
1458 } else if (UseVectorizedMismatchIntrinsic) {
1459 if (!FLAG_IS_DEFAULT(UseVectorizedMismatchIntrinsic))
1460 warning("vectorizedMismatch intrinsics are not available on this CPU");
1461 FLAG_SET_DEFAULT(UseVectorizedMismatchIntrinsic, false);
1462 }
1463 #else
1464 if (UseVectorizedMismatchIntrinsic) {
1465 if (!FLAG_IS_DEFAULT(UseVectorizedMismatchIntrinsic)) {
1466 warning("vectorizedMismatch intrinsic is not available in 32-bit VM");
1467 }
1468 FLAG_SET_DEFAULT(UseVectorizedMismatchIntrinsic, false);
1469 }
1470 #endif // _LP64
1471
1472 // Use count leading zeros count instruction if available.
1473 if (supports_lzcnt()) {
1474 if (FLAG_IS_DEFAULT(UseCountLeadingZerosInstruction)) {
1475 UseCountLeadingZerosInstruction = true;
1476 }
1477 } else if (UseCountLeadingZerosInstruction) {
1478 warning("lzcnt instruction is not available on this CPU");
1479 FLAG_SET_DEFAULT(UseCountLeadingZerosInstruction, false);
1480 }
1481
1482 // Use count trailing zeros instruction if available
1483 if (supports_bmi1()) {
1484 // tzcnt does not require VEX prefix
1485 if (FLAG_IS_DEFAULT(UseCountTrailingZerosInstruction)) {
1486 if (!UseBMI1Instructions && !FLAG_IS_DEFAULT(UseBMI1Instructions)) {
1487 // Don't use tzcnt if BMI1 is switched off on command line.
1488 UseCountTrailingZerosInstruction = false;
1489 } else {
1490 UseCountTrailingZerosInstruction = true;
1491 }
1492 }
1493 } else if (UseCountTrailingZerosInstruction) {
1494 warning("tzcnt instruction is not available on this CPU");
1495 FLAG_SET_DEFAULT(UseCountTrailingZerosInstruction, false);
1496 }
1497
1498 // BMI instructions (except tzcnt) use an encoding with VEX prefix.
1499 // VEX prefix is generated only when AVX > 0.
1500 if (supports_bmi1() && supports_avx()) {
1501 if (FLAG_IS_DEFAULT(UseBMI1Instructions)) {
1502 UseBMI1Instructions = true;
1503 }
1504 } else if (UseBMI1Instructions) {
1505 warning("BMI1 instructions are not available on this CPU (AVX is also required)");
1506 FLAG_SET_DEFAULT(UseBMI1Instructions, false);
1507 }
1508
1509 if (supports_bmi2() && supports_avx()) {
1510 if (FLAG_IS_DEFAULT(UseBMI2Instructions)) {
1511 UseBMI2Instructions = true;
1512 }
1513 } else if (UseBMI2Instructions) {
1514 warning("BMI2 instructions are not available on this CPU (AVX is also required)");
1515 FLAG_SET_DEFAULT(UseBMI2Instructions, false);
1516 }
1517
1518 // Use population count instruction if available.
1519 if (supports_popcnt()) {
1520 if (FLAG_IS_DEFAULT(UsePopCountInstruction)) {
1521 UsePopCountInstruction = true;
1522 }
1523 } else if (UsePopCountInstruction) {
1524 warning("POPCNT instruction is not available on this CPU");
1525 FLAG_SET_DEFAULT(UsePopCountInstruction, false);
1526 }
1527
1528 // Use fast-string operations if available.
1529 if (supports_erms()) {
1530 if (FLAG_IS_DEFAULT(UseFastStosb)) {
1531 UseFastStosb = true;
1532 }
1533 } else if (UseFastStosb) {
1534 warning("fast-string operations are not available on this CPU");
1535 FLAG_SET_DEFAULT(UseFastStosb, false);
1536 }
1537
1538 // Use XMM/YMM MOVDQU instruction for Object Initialization
1539 if (!UseFastStosb && UseSSE >= 2 && UseUnalignedLoadStores) {
1540 if (FLAG_IS_DEFAULT(UseXMMForObjInit)) {
1541 UseXMMForObjInit = true;
1542 }
1543 } else if (UseXMMForObjInit) {
1544 warning("UseXMMForObjInit requires SSE2 and unaligned load/stores. Feature is switched off.");
1545 FLAG_SET_DEFAULT(UseXMMForObjInit, false);
1546 }
1547
1548 #ifdef COMPILER2
1549 if (FLAG_IS_DEFAULT(AlignVector)) {
1550 // Modern processors allow misaligned memory operations for vectors.
1551 AlignVector = !UseUnalignedLoadStores;
1552 }
1553 if (FLAG_IS_DEFAULT(OptimizeFill)) {
1554 // 8247307: On x86, the auto-vectorized loop array fill code shows
1555 // better performance than the array fill stubs. We should reenable
1556 // this after the x86 stubs get improved.
1557 OptimizeFill = false;
1558 }
1559 #endif // COMPILER2
1560
1561 if (FLAG_IS_DEFAULT(AllocatePrefetchInstr)) {
1562 if (AllocatePrefetchInstr == 3 && !supports_3dnow_prefetch()) {
1563 FLAG_SET_DEFAULT(AllocatePrefetchInstr, 0);
1564 } else if (!supports_sse() && supports_3dnow_prefetch()) {
1565 FLAG_SET_DEFAULT(AllocatePrefetchInstr, 3);
1566 }
1567 }
1568
1569 // Allocation prefetch settings
1570 intx cache_line_size = prefetch_data_size();
1571 if (FLAG_IS_DEFAULT(AllocatePrefetchStepSize) &&
1572 (cache_line_size > AllocatePrefetchStepSize)) {
1573 FLAG_SET_DEFAULT(AllocatePrefetchStepSize, cache_line_size);
1574 }
1575
1576 if ((AllocatePrefetchDistance == 0) && (AllocatePrefetchStyle != 0)) {
1577 assert(!FLAG_IS_DEFAULT(AllocatePrefetchDistance), "default value should not be 0");
1578 if (!FLAG_IS_DEFAULT(AllocatePrefetchStyle)) {
1579 warning("AllocatePrefetchDistance is set to 0 which disable prefetching. Ignoring AllocatePrefetchStyle flag.");
1580 }
1581 FLAG_SET_DEFAULT(AllocatePrefetchStyle, 0);
1582 }
1583
1584 if (FLAG_IS_DEFAULT(AllocatePrefetchDistance)) {
1585 bool use_watermark_prefetch = (AllocatePrefetchStyle == 2);
1586 FLAG_SET_DEFAULT(AllocatePrefetchDistance, allocate_prefetch_distance(use_watermark_prefetch));
1587 }
1588
1589 if (is_intel() && cpu_family() == 6 && supports_sse3()) {
1590 if (FLAG_IS_DEFAULT(AllocatePrefetchLines) &&
1591 supports_sse4_2() && supports_ht()) { // Nehalem based cpus
1592 FLAG_SET_DEFAULT(AllocatePrefetchLines, 4);
1593 }
1594 #ifdef COMPILER2
1595 if (FLAG_IS_DEFAULT(UseFPUForSpilling) && supports_sse4_2()) {
1596 FLAG_SET_DEFAULT(UseFPUForSpilling, true);
1597 }
1598 #endif
1599 }
1600
1601 if (is_zx() && ((cpu_family() == 6) || (cpu_family() == 7)) && supports_sse4_2()) {
1602 #ifdef COMPILER2
1603 if (FLAG_IS_DEFAULT(UseFPUForSpilling)) {
1604 FLAG_SET_DEFAULT(UseFPUForSpilling, true);
1605 }
1606 #endif
1607 }
1608
1609 #ifdef _LP64
1610 // Prefetch settings
1611
1612 // Prefetch interval for gc copy/scan == 9 dcache lines. Derived from
1613 // 50-warehouse specjbb runs on a 2-way 1.8ghz opteron using a 4gb heap.
1614 // Tested intervals from 128 to 2048 in increments of 64 == one cache line.
1615 // 256 bytes (4 dcache lines) was the nearest runner-up to 576.
1616
1617 // gc copy/scan is disabled if prefetchw isn't supported, because
1618 // Prefetch::write emits an inlined prefetchw on Linux.
1619 // Do not use the 3dnow prefetchw instruction. It isn't supported on em64t.
1620 // The used prefetcht0 instruction works for both amd64 and em64t.
1621
1622 if (FLAG_IS_DEFAULT(PrefetchCopyIntervalInBytes)) {
1623 FLAG_SET_DEFAULT(PrefetchCopyIntervalInBytes, 576);
1624 }
1625 if (FLAG_IS_DEFAULT(PrefetchScanIntervalInBytes)) {
1626 FLAG_SET_DEFAULT(PrefetchScanIntervalInBytes, 576);
1627 }
1628 if (FLAG_IS_DEFAULT(PrefetchFieldsAhead)) {
1629 FLAG_SET_DEFAULT(PrefetchFieldsAhead, 1);
1630 }
1631 #endif
1632
1633 if (FLAG_IS_DEFAULT(ContendedPaddingWidth) &&
1634 (cache_line_size > ContendedPaddingWidth))
1635 ContendedPaddingWidth = cache_line_size;
1636
1637 // This machine allows unaligned memory accesses
1638 if (FLAG_IS_DEFAULT(UseUnalignedAccesses)) {
1639 FLAG_SET_DEFAULT(UseUnalignedAccesses, true);
1640 }
1641
1642 #ifndef PRODUCT
1643 if (log_is_enabled(Info, os, cpu)) {
1644 LogStream ls(Log(os, cpu)::info());
1645 outputStream* log = &ls;
1646 log->print_cr("Logical CPUs per core: %u",
1647 logical_processors_per_package());
1648 log->print_cr("L1 data cache line size: %u", L1_data_cache_line_size());
1649 log->print("UseSSE=%d", (int) UseSSE);
1650 if (UseAVX > 0) {
1651 log->print(" UseAVX=%d", (int) UseAVX);
1652 }
1653 if (UseAES) {
1654 log->print(" UseAES=1");
1655 }
1656 #ifdef COMPILER2
1657 if (MaxVectorSize > 0) {
1658 log->print(" MaxVectorSize=%d", (int) MaxVectorSize);
1659 }
1660 #endif
1661 log->cr();
1662 log->print("Allocation");
1663 if (AllocatePrefetchStyle <= 0 || (UseSSE == 0 && !supports_3dnow_prefetch())) {
1664 log->print_cr(": no prefetching");
1665 } else {
1666 log->print(" prefetching: ");
1667 if (UseSSE == 0 && supports_3dnow_prefetch()) {
1668 log->print("PREFETCHW");
1669 } else if (UseSSE >= 1) {
1670 if (AllocatePrefetchInstr == 0) {
1671 log->print("PREFETCHNTA");
1672 } else if (AllocatePrefetchInstr == 1) {
1673 log->print("PREFETCHT0");
1674 } else if (AllocatePrefetchInstr == 2) {
1675 log->print("PREFETCHT2");
1676 } else if (AllocatePrefetchInstr == 3) {
1677 log->print("PREFETCHW");
1678 }
1679 }
1680 if (AllocatePrefetchLines > 1) {
1681 log->print_cr(" at distance %d, %d lines of %d bytes", (int) AllocatePrefetchDistance, (int) AllocatePrefetchLines, (int) AllocatePrefetchStepSize);
1682 } else {
1683 log->print_cr(" at distance %d, one line of %d bytes", (int) AllocatePrefetchDistance, (int) AllocatePrefetchStepSize);
1684 }
1685 }
1686
1687 if (PrefetchCopyIntervalInBytes > 0) {
1688 log->print_cr("PrefetchCopyIntervalInBytes %d", (int) PrefetchCopyIntervalInBytes);
1689 }
1690 if (PrefetchScanIntervalInBytes > 0) {
1691 log->print_cr("PrefetchScanIntervalInBytes %d", (int) PrefetchScanIntervalInBytes);
1692 }
1693 if (PrefetchFieldsAhead > 0) {
1694 log->print_cr("PrefetchFieldsAhead %d", (int) PrefetchFieldsAhead);
1695 }
1696 if (ContendedPaddingWidth > 0) {
1697 log->print_cr("ContendedPaddingWidth %d", (int) ContendedPaddingWidth);
1698 }
1699 }
1700 #endif // !PRODUCT
1701 }
1702
1703 void VM_Version::print_platform_virtualization_info(outputStream* st) {
1704 VirtualizationType vrt = VM_Version::get_detected_virtualization();
1705 if (vrt == XenHVM) {
1706 st->print_cr("Xen hardware-assisted virtualization detected");
1707 } else if (vrt == KVM) {
1708 st->print_cr("KVM virtualization detected");
1709 } else if (vrt == VMWare) {
1710 st->print_cr("VMWare virtualization detected");
1711 VirtualizationSupport::print_virtualization_info(st);
1712 } else if (vrt == HyperV) {
1713 st->print_cr("Hyper-V virtualization detected");
1714 } else if (vrt == HyperVRole) {
1715 st->print_cr("Hyper-V role detected");
1716 }
1717 }
1718
1719 bool VM_Version::use_biased_locking() {
1720 #if INCLUDE_RTM_OPT
1721 // RTM locking is most useful when there is high lock contention and
1722 // low data contention. With high lock contention the lock is usually
1723 // inflated and biased locking is not suitable for that case.
1724 // RTM locking code requires that biased locking is off.
1725 // Note: we can't switch off UseBiasedLocking in get_processor_features()
1726 // because it is used by Thread::allocate() which is called before
1727 // VM_Version::initialize().
1728 if (UseRTMLocking && UseBiasedLocking) {
1729 if (FLAG_IS_DEFAULT(UseBiasedLocking)) {
1730 FLAG_SET_DEFAULT(UseBiasedLocking, false);
1731 } else {
1732 warning("Biased locking is not supported with RTM locking; ignoring UseBiasedLocking flag." );
1733 UseBiasedLocking = false;
1734 }
1735 }
1736 #endif
1737 return UseBiasedLocking;
1738 }
1739
1740 bool VM_Version::compute_has_intel_jcc_erratum() {
1741 if (!is_intel_family_core()) {
1742 // Only Intel CPUs are affected.
1743 return false;
1744 }
1745 // The following table of affected CPUs is based on the following document released by Intel:
1746 // https://www.intel.com/content/dam/support/us/en/documents/processors/mitigations-jump-conditional-code-erratum.pdf
1747 switch (_model) {
1748 case 0x8E:
1749 // 06_8EH | 9 | 8th Generation Intel® Core™ Processor Family based on microarchitecture code name Amber Lake Y
1750 // 06_8EH | 9 | 7th Generation Intel® Core™ Processor Family based on microarchitecture code name Kaby Lake U
1751 // 06_8EH | 9 | 7th Generation Intel® Core™ Processor Family based on microarchitecture code name Kaby Lake U 23e
1752 // 06_8EH | 9 | 7th Generation Intel® Core™ Processor Family based on microarchitecture code name Kaby Lake Y
1753 // 06_8EH | A | 8th Generation Intel® Core™ Processor Family based on microarchitecture code name Coffee Lake U43e
1754 // 06_8EH | B | 8th Generation Intel® Core™ Processors based on microarchitecture code name Whiskey Lake U
1755 // 06_8EH | C | 8th Generation Intel® Core™ Processor Family based on microarchitecture code name Amber Lake Y
1756 // 06_8EH | C | 10th Generation Intel® Core™ Processor Family based on microarchitecture code name Comet Lake U42
1757 // 06_8EH | C | 8th Generation Intel® Core™ Processors based on microarchitecture code name Whiskey Lake U
1758 return _stepping == 0x9 || _stepping == 0xA || _stepping == 0xB || _stepping == 0xC;
1759 case 0x4E:
1760 // 06_4E | 3 | 6th Generation Intel® Core™ Processors based on microarchitecture code name Skylake U
1761 // 06_4E | 3 | 6th Generation Intel® Core™ Processor Family based on microarchitecture code name Skylake U23e
1762 // 06_4E | 3 | 6th Generation Intel® Core™ Processors based on microarchitecture code name Skylake Y
1763 return _stepping == 0x3;
1764 case 0x55:
1765 // 06_55H | 4 | Intel® Xeon® Processor D Family based on microarchitecture code name Skylake D, Bakerville
1766 // 06_55H | 4 | Intel® Xeon® Scalable Processors based on microarchitecture code name Skylake Server
1767 // 06_55H | 4 | Intel® Xeon® Processor W Family based on microarchitecture code name Skylake W
1768 // 06_55H | 4 | Intel® Core™ X-series Processors based on microarchitecture code name Skylake X
1769 // 06_55H | 4 | Intel® Xeon® Processor E3 v5 Family based on microarchitecture code name Skylake Xeon E3
1770 // 06_55 | 7 | 2nd Generation Intel® Xeon® Scalable Processors based on microarchitecture code name Cascade Lake (server)
1771 return _stepping == 0x4 || _stepping == 0x7;
1772 case 0x5E:
1773 // 06_5E | 3 | 6th Generation Intel® Core™ Processor Family based on microarchitecture code name Skylake H
1774 // 06_5E | 3 | 6th Generation Intel® Core™ Processor Family based on microarchitecture code name Skylake S
1775 return _stepping == 0x3;
1776 case 0x9E:
1777 // 06_9EH | 9 | 8th Generation Intel® Core™ Processor Family based on microarchitecture code name Kaby Lake G
1778 // 06_9EH | 9 | 7th Generation Intel® Core™ Processor Family based on microarchitecture code name Kaby Lake H
1779 // 06_9EH | 9 | 7th Generation Intel® Core™ Processor Family based on microarchitecture code name Kaby Lake S
1780 // 06_9EH | 9 | Intel® Core™ X-series Processors based on microarchitecture code name Kaby Lake X
1781 // 06_9EH | 9 | Intel® Xeon® Processor E3 v6 Family Kaby Lake Xeon E3
1782 // 06_9EH | A | 8th Generation Intel® Core™ Processor Family based on microarchitecture code name Coffee Lake H
1783 // 06_9EH | A | 8th Generation Intel® Core™ Processor Family based on microarchitecture code name Coffee Lake S
1784 // 06_9EH | A | 8th Generation Intel® Core™ Processor Family based on microarchitecture code name Coffee Lake S (6+2) x/KBP
1785 // 06_9EH | A | Intel® Xeon® Processor E Family based on microarchitecture code name Coffee Lake S (6+2)
1786 // 06_9EH | A | Intel® Xeon® Processor E Family based on microarchitecture code name Coffee Lake S (4+2)
1787 // 06_9EH | B | 8th Generation Intel® Core™ Processor Family based on microarchitecture code name Coffee Lake S (4+2)
1788 // 06_9EH | B | Intel® Celeron® Processor G Series based on microarchitecture code name Coffee Lake S (4+2)
1789 // 06_9EH | D | 9th Generation Intel® Core™ Processor Family based on microarchitecturecode name Coffee Lake H (8+2)
1790 // 06_9EH | D | 9th Generation Intel® Core™ Processor Family based on microarchitecture code name Coffee Lake S (8+2)
1791 return _stepping == 0x9 || _stepping == 0xA || _stepping == 0xB || _stepping == 0xD;
1792 case 0xA6:
1793 // 06_A6H | 0 | 10th Generation Intel® Core™ Processor Family based on microarchitecture code name Comet Lake U62
1794 return _stepping == 0x0;
1795 case 0xAE:
1796 // 06_AEH | A | 8th Generation Intel® Core™ Processor Family based on microarchitecture code name Kaby Lake Refresh U (4+2)
1797 return _stepping == 0xA;
1798 default:
1799 // If we are running on another intel machine not recognized in the table, we are okay.
1800 return false;
1801 }
1802 }
1803
1804 // On Xen, the cpuid instruction returns
1805 // eax / registers[0]: Version of Xen
1806 // ebx / registers[1]: chars 'XenV'
1807 // ecx / registers[2]: chars 'MMXe'
1808 // edx / registers[3]: chars 'nVMM'
1809 //
1810 // On KVM / VMWare / MS Hyper-V, the cpuid instruction returns
1811 // ebx / registers[1]: chars 'KVMK' / 'VMwa' / 'Micr'
1812 // ecx / registers[2]: chars 'VMKV' / 'reVM' / 'osof'
1813 // edx / registers[3]: chars 'M' / 'ware' / 't Hv'
1814 //
1815 // more information :
1816 // https://kb.vmware.com/s/article/1009458
1817 //
1818 void VM_Version::check_virtualizations() {
1819 uint32_t registers[4] = {0};
1820 char signature[13] = {0};
1821
1822 // Xen cpuid leaves can be found 0x100 aligned boundary starting
1823 // from 0x40000000 until 0x40010000.
1824 // https://lists.linuxfoundation.org/pipermail/virtualization/2012-May/019974.html
1825 for (int leaf = 0x40000000; leaf < 0x40010000; leaf += 0x100) {
1826 detect_virt_stub(leaf, registers);
1827 memcpy(signature, ®isters[1], 12);
1828
1829 if (strncmp("VMwareVMware", signature, 12) == 0) {
1830 Abstract_VM_Version::_detected_virtualization = VMWare;
1831 // check for extended metrics from guestlib
1832 VirtualizationSupport::initialize();
1833 } else if (strncmp("Microsoft Hv", signature, 12) == 0) {
1834 Abstract_VM_Version::_detected_virtualization = HyperV;
1835 #ifdef _WINDOWS
1836 // CPUID leaf 0x40000007 is available to the root partition only.
1837 // See Hypervisor Top Level Functional Specification section 2.4.8 for more details.
1838 // https://github.com/MicrosoftDocs/Virtualization-Documentation/raw/master/tlfs/Hypervisor%20Top%20Level%20Functional%20Specification%20v6.0b.pdf
1839 detect_virt_stub(0x40000007, registers);
1840 if ((registers[0] != 0x0) ||
1841 (registers[1] != 0x0) ||
1842 (registers[2] != 0x0) ||
1843 (registers[3] != 0x0)) {
1844 Abstract_VM_Version::_detected_virtualization = HyperVRole;
1845 }
1846 #endif
1847 } else if (strncmp("KVMKVMKVM", signature, 9) == 0) {
1848 Abstract_VM_Version::_detected_virtualization = KVM;
1849 } else if (strncmp("XenVMMXenVMM", signature, 12) == 0) {
1850 Abstract_VM_Version::_detected_virtualization = XenHVM;
1851 }
1852 }
1853 }
1854
1855 void VM_Version::initialize() {
1856 ResourceMark rm;
1857 // Making this stub must be FIRST use of assembler
1858 stub_blob = BufferBlob::create("VM_Version stub", stub_size);
1859 if (stub_blob == NULL) {
1860 vm_exit_during_initialization("Unable to allocate stub for VM_Version");
1861 }
1862 CodeBuffer c(stub_blob);
1863 VM_Version_StubGenerator g(&c);
1864
1865 get_cpu_info_stub = CAST_TO_FN_PTR(get_cpu_info_stub_t,
1866 g.generate_get_cpu_info());
1867 detect_virt_stub = CAST_TO_FN_PTR(detect_virt_stub_t,
1868 g.generate_detect_virt());
1869
1870 get_processor_features();
1871
1872 LP64_ONLY(Assembler::precompute_instructions();)
1873
1874 if (VM_Version::supports_hv()) { // Supports hypervisor
1875 check_virtualizations();
1876 }
1877 }