1 /*
2 * Copyright (c) 1997, 2020, Oracle and/or its affiliates. All rights reserved.
3 * Copyright (c) 2012, 2020 SAP SE. All rights reserved.
4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
5 *
6 * This code is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 only, as
8 * published by the Free Software Foundation.
9 *
10 * This code is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * version 2 for more details (a copy is included in the LICENSE file that
14 * accompanied this code).
15 *
16 * You should have received a copy of the GNU General Public License version
17 * 2 along with this work; if not, write to the Free Software Foundation,
18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 * or visit www.oracle.com if you need additional information or have any
22 * questions.
23 *
24 */
25
26 #include "precompiled.hpp"
27 #include "jvm.h"
28 #include "asm/assembler.inline.hpp"
29 #include "asm/macroAssembler.inline.hpp"
30 #include "compiler/disassembler.hpp"
31 #include "memory/resourceArea.hpp"
32 #include "runtime/java.hpp"
33 #include "runtime/os.hpp"
34 #include "runtime/stubCodeGenerator.hpp"
35 #include "runtime/vm_version.hpp"
36 #include "utilities/align.hpp"
37 #include "utilities/defaultStream.hpp"
38 #include "utilities/globalDefinitions.hpp"
39 #include "utilities/powerOfTwo.hpp"
40
41 #include <sys/sysinfo.h>
42 #if defined(_AIX)
43 #include <libperfstat.h>
44 #endif
45
46 #if defined(LINUX) && defined(VM_LITTLE_ENDIAN)
47 #include <sys/auxv.h>
48
49 #ifndef PPC_FEATURE2_HTM_NOSC
50 #define PPC_FEATURE2_HTM_NOSC (1 << 24)
51 #endif
52 #endif
53
54 bool VM_Version::_is_determine_features_test_running = false;
55 uint64_t VM_Version::_dscr_val = 0;
56
57 #define MSG(flag) \
58 if (flag && !FLAG_IS_DEFAULT(flag)) \
59 jio_fprintf(defaultStream::error_stream(), \
60 "warning: -XX:+" #flag " requires -XX:+UseSIGTRAP\n" \
61 " -XX:+" #flag " will be disabled!\n");
62
63 void VM_Version::initialize() {
64
65 // Test which instructions are supported and measure cache line size.
66 determine_features();
67
68 // If PowerArchitecturePPC64 hasn't been specified explicitly determine from features.
69 if (FLAG_IS_DEFAULT(PowerArchitecturePPC64)) {
70 if (VM_Version::has_brw()) {
71 FLAG_SET_ERGO(PowerArchitecturePPC64, 10);
72 } else if (VM_Version::has_darn()) {
73 FLAG_SET_ERGO(PowerArchitecturePPC64, 9);
74 } else if (VM_Version::has_lqarx()) {
75 FLAG_SET_ERGO(PowerArchitecturePPC64, 8);
76 } else if (VM_Version::has_popcntw()) {
77 FLAG_SET_ERGO(PowerArchitecturePPC64, 7);
78 } else if (VM_Version::has_cmpb()) {
79 FLAG_SET_ERGO(PowerArchitecturePPC64, 6);
80 } else if (VM_Version::has_popcntb()) {
81 FLAG_SET_ERGO(PowerArchitecturePPC64, 5);
82 } else {
83 FLAG_SET_ERGO(PowerArchitecturePPC64, 0);
84 }
85 }
86
87 bool PowerArchitecturePPC64_ok = false;
88 switch (PowerArchitecturePPC64) {
89 case 10: if (!VM_Version::has_brw() ) break;
90 case 9: if (!VM_Version::has_darn() ) break;
91 case 8: if (!VM_Version::has_lqarx() ) break;
92 case 7: if (!VM_Version::has_popcntw()) break;
93 case 6: if (!VM_Version::has_cmpb() ) break;
94 case 5: if (!VM_Version::has_popcntb()) break;
95 case 0: PowerArchitecturePPC64_ok = true; break;
96 default: break;
97 }
98 guarantee(PowerArchitecturePPC64_ok, "PowerArchitecturePPC64 cannot be set to "
99 UINTX_FORMAT " on this machine", PowerArchitecturePPC64);
100
101 // Power 8: Configure Data Stream Control Register.
102 if (PowerArchitecturePPC64 >= 8 && has_mfdscr()) {
103 config_dscr();
104 }
105
106 if (!UseSIGTRAP) {
107 MSG(TrapBasedICMissChecks);
108 MSG(TrapBasedNullChecks);
109 FLAG_SET_ERGO(TrapBasedNullChecks, false);
110 FLAG_SET_ERGO(TrapBasedICMissChecks, false);
111 }
112
113 #ifdef COMPILER2
114 if (!UseSIGTRAP) {
115 MSG(TrapBasedRangeChecks);
116 FLAG_SET_ERGO(TrapBasedRangeChecks, false);
117 }
118
119 // On Power6 test for section size.
120 if (PowerArchitecturePPC64 == 6) {
121 determine_section_size();
122 // TODO: PPC port } else {
123 // TODO: PPC port PdScheduling::power6SectorSize = 0x20;
124 }
125
126 if (PowerArchitecturePPC64 >= 8) {
127 if (FLAG_IS_DEFAULT(SuperwordUseVSX)) {
128 FLAG_SET_ERGO(SuperwordUseVSX, true);
129 }
130 } else {
131 if (SuperwordUseVSX) {
132 warning("SuperwordUseVSX specified, but needs at least Power8.");
133 FLAG_SET_DEFAULT(SuperwordUseVSX, false);
134 }
135 }
136 MaxVectorSize = SuperwordUseVSX ? 16 : 8;
137
138 if (PowerArchitecturePPC64 >= 9) {
139 if (FLAG_IS_DEFAULT(UseCountTrailingZerosInstructionsPPC64)) {
140 FLAG_SET_ERGO(UseCountTrailingZerosInstructionsPPC64, true);
141 }
142 if (FLAG_IS_DEFAULT(UseCharacterCompareIntrinsics)) {
143 FLAG_SET_ERGO(UseCharacterCompareIntrinsics, true);
144 }
145 if (FLAG_IS_DEFAULT(UseVectorByteReverseInstructionsPPC64)) {
146 FLAG_SET_ERGO(UseVectorByteReverseInstructionsPPC64, true);
147 }
148 } else {
149 if (UseCountTrailingZerosInstructionsPPC64) {
150 warning("UseCountTrailingZerosInstructionsPPC64 specified, but needs at least Power9.");
151 FLAG_SET_DEFAULT(UseCountTrailingZerosInstructionsPPC64, false);
152 }
153 if (UseCharacterCompareIntrinsics) {
154 warning("UseCharacterCompareIntrinsics specified, but needs at least Power9.");
155 FLAG_SET_DEFAULT(UseCharacterCompareIntrinsics, false);
156 }
157 if (UseVectorByteReverseInstructionsPPC64) {
158 warning("UseVectorByteReverseInstructionsPPC64 specified, but needs at least Power9.");
159 FLAG_SET_DEFAULT(UseVectorByteReverseInstructionsPPC64, false);
160 }
161 }
162
163 if (PowerArchitecturePPC64 >= 10) {
164 if (FLAG_IS_DEFAULT(UseByteReverseInstructions)) {
165 FLAG_SET_ERGO(UseByteReverseInstructions, true);
166 }
167 } else {
168 if (UseByteReverseInstructions) {
169 warning("UseByteReverseInstructions specified, but needs at least Power10.");
170 FLAG_SET_DEFAULT(UseByteReverseInstructions, false);
171 }
172 }
173 #endif
174
175 // Create and print feature-string.
176 char buf[(num_features+1) * 16]; // Max 16 chars per feature.
177 jio_snprintf(buf, sizeof(buf),
178 "ppc64%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s",
179 (has_fsqrt() ? " fsqrt" : ""),
180 (has_isel() ? " isel" : ""),
181 (has_lxarxeh() ? " lxarxeh" : ""),
182 (has_cmpb() ? " cmpb" : ""),
183 (has_popcntb() ? " popcntb" : ""),
184 (has_popcntw() ? " popcntw" : ""),
185 (has_fcfids() ? " fcfids" : ""),
186 (has_vand() ? " vand" : ""),
187 (has_lqarx() ? " lqarx" : ""),
188 (has_vcipher() ? " aes" : ""),
189 (has_vpmsumb() ? " vpmsumb" : ""),
190 (has_mfdscr() ? " mfdscr" : ""),
191 (has_vsx() ? " vsx" : ""),
192 (has_ldbrx() ? " ldbrx" : ""),
193 (has_stdbrx() ? " stdbrx" : ""),
194 (has_vshasig() ? " sha" : ""),
195 (has_tm() ? " rtm" : ""),
196 (has_darn() ? " darn" : ""),
197 (has_brw() ? " brw" : "")
198 // Make sure number of %s matches num_features!
199 );
200 _features_string = os::strdup(buf);
201 if (Verbose) {
202 print_features();
203 }
204
205 // PPC64 supports 8-byte compare-exchange operations (see Atomic::cmpxchg)
206 // and 'atomic long memory ops' (see Unsafe_GetLongVolatile).
207 _supports_cx8 = true;
208
209 // Used by C1.
210 _supports_atomic_getset4 = true;
211 _supports_atomic_getadd4 = true;
212 _supports_atomic_getset8 = true;
213 _supports_atomic_getadd8 = true;
214
215 intx cache_line_size = L1_data_cache_line_size();
216
217 if (PowerArchitecturePPC64 >= 9) {
218 if (os::supports_map_sync() == true) {
219 _data_cache_line_flush_size = cache_line_size;
220 }
221 }
222
223 if (FLAG_IS_DEFAULT(AllocatePrefetchStyle)) AllocatePrefetchStyle = 1;
224
225 if (cache_line_size > AllocatePrefetchStepSize) AllocatePrefetchStepSize = cache_line_size;
226 // PPC processors have an automatic prefetch engine.
227 if (FLAG_IS_DEFAULT(AllocatePrefetchLines)) AllocatePrefetchLines = 1;
228 if (AllocatePrefetchDistance < 0) AllocatePrefetchDistance = 3 * cache_line_size;
229
230 assert(AllocatePrefetchLines > 0, "invalid value");
231 if (AllocatePrefetchLines < 1) { // Set valid value in product VM.
232 AllocatePrefetchLines = 1; // Conservative value.
233 }
234
235 if (AllocatePrefetchStyle == 3 && AllocatePrefetchDistance < cache_line_size) {
236 AllocatePrefetchStyle = 1; // Fall back if inappropriate.
237 }
238
239 assert(AllocatePrefetchStyle >= 0, "AllocatePrefetchStyle should be positive");
240
241 if (FLAG_IS_DEFAULT(ContendedPaddingWidth) && (cache_line_size > ContendedPaddingWidth)) {
242 ContendedPaddingWidth = cache_line_size;
243 }
244
245 // If running on Power8 or newer hardware, the implementation uses the available vector instructions.
246 // In all other cases, the implementation uses only generally available instructions.
247 if (!UseCRC32Intrinsics) {
248 if (FLAG_IS_DEFAULT(UseCRC32Intrinsics)) {
249 FLAG_SET_DEFAULT(UseCRC32Intrinsics, true);
250 }
251 }
252
253 // Implementation does not use any of the vector instructions available with Power8.
254 // Their exploitation is still pending (aka "work in progress").
255 if (!UseCRC32CIntrinsics) {
256 if (FLAG_IS_DEFAULT(UseCRC32CIntrinsics)) {
257 FLAG_SET_DEFAULT(UseCRC32CIntrinsics, true);
258 }
259 }
260
261 // TODO: Provide implementation.
262 if (UseAdler32Intrinsics) {
263 warning("Adler32Intrinsics not available on this CPU.");
264 FLAG_SET_DEFAULT(UseAdler32Intrinsics, false);
265 }
266
267 // The AES intrinsic stubs require AES instruction support.
268 if (has_vcipher()) {
269 if (FLAG_IS_DEFAULT(UseAES)) {
270 UseAES = true;
271 }
272 } else if (UseAES) {
273 if (!FLAG_IS_DEFAULT(UseAES))
274 warning("AES instructions are not available on this CPU");
275 FLAG_SET_DEFAULT(UseAES, false);
276 }
277
278 if (UseAES && has_vcipher()) {
279 if (FLAG_IS_DEFAULT(UseAESIntrinsics)) {
280 UseAESIntrinsics = true;
281 }
282 } else if (UseAESIntrinsics) {
283 if (!FLAG_IS_DEFAULT(UseAESIntrinsics))
284 warning("AES intrinsics are not available on this CPU");
285 FLAG_SET_DEFAULT(UseAESIntrinsics, false);
286 }
287
288 if (UseAESCTRIntrinsics) {
289 warning("AES/CTR intrinsics are not available on this CPU");
290 FLAG_SET_DEFAULT(UseAESCTRIntrinsics, false);
291 }
292
293 if (UseGHASHIntrinsics) {
294 warning("GHASH intrinsics are not available on this CPU");
295 FLAG_SET_DEFAULT(UseGHASHIntrinsics, false);
296 }
297
298 if (FLAG_IS_DEFAULT(UseFMA)) {
299 FLAG_SET_DEFAULT(UseFMA, true);
300 }
301
302 if (UseMD5Intrinsics) {
303 warning("MD5 intrinsics are not available on this CPU");
304 FLAG_SET_DEFAULT(UseMD5Intrinsics, false);
305 }
306
307 if (has_vshasig()) {
308 if (FLAG_IS_DEFAULT(UseSHA)) {
309 UseSHA = true;
310 }
311 } else if (UseSHA) {
312 if (!FLAG_IS_DEFAULT(UseSHA))
313 warning("SHA instructions are not available on this CPU");
314 FLAG_SET_DEFAULT(UseSHA, false);
315 }
316
317 if (UseSHA1Intrinsics) {
318 warning("Intrinsics for SHA-1 crypto hash functions not available on this CPU.");
319 FLAG_SET_DEFAULT(UseSHA1Intrinsics, false);
320 }
321
322 if (UseSHA && has_vshasig()) {
323 if (FLAG_IS_DEFAULT(UseSHA256Intrinsics)) {
324 FLAG_SET_DEFAULT(UseSHA256Intrinsics, true);
325 }
326 } else if (UseSHA256Intrinsics) {
327 warning("Intrinsics for SHA-224 and SHA-256 crypto hash functions not available on this CPU.");
328 FLAG_SET_DEFAULT(UseSHA256Intrinsics, false);
329 }
330
331 if (UseSHA && has_vshasig()) {
332 if (FLAG_IS_DEFAULT(UseSHA512Intrinsics)) {
333 FLAG_SET_DEFAULT(UseSHA512Intrinsics, true);
334 }
335 } else if (UseSHA512Intrinsics) {
336 warning("Intrinsics for SHA-384 and SHA-512 crypto hash functions not available on this CPU.");
337 FLAG_SET_DEFAULT(UseSHA512Intrinsics, false);
338 }
339
340 if (UseSHA3Intrinsics) {
341 warning("Intrinsics for SHA3-224, SHA3-256, SHA3-384 and SHA3-512 crypto hash functions not available on this CPU.");
342 FLAG_SET_DEFAULT(UseSHA3Intrinsics, false);
343 }
344
345 if (!(UseSHA1Intrinsics || UseSHA256Intrinsics || UseSHA512Intrinsics)) {
346 FLAG_SET_DEFAULT(UseSHA, false);
347 }
348
349 #ifdef COMPILER2
350 if (FLAG_IS_DEFAULT(UseSquareToLenIntrinsic)) {
351 UseSquareToLenIntrinsic = true;
352 }
353 if (FLAG_IS_DEFAULT(UseMulAddIntrinsic)) {
354 UseMulAddIntrinsic = true;
355 }
356 if (FLAG_IS_DEFAULT(UseMultiplyToLenIntrinsic)) {
357 UseMultiplyToLenIntrinsic = true;
358 }
359 if (FLAG_IS_DEFAULT(UseMontgomeryMultiplyIntrinsic)) {
360 UseMontgomeryMultiplyIntrinsic = true;
361 }
362 if (FLAG_IS_DEFAULT(UseMontgomerySquareIntrinsic)) {
363 UseMontgomerySquareIntrinsic = true;
364 }
365 #endif
366
367 if (UseVectorizedMismatchIntrinsic) {
368 warning("UseVectorizedMismatchIntrinsic specified, but not available on this CPU.");
369 FLAG_SET_DEFAULT(UseVectorizedMismatchIntrinsic, false);
370 }
371
372
373 // Adjust RTM (Restricted Transactional Memory) flags.
374 if (UseRTMLocking) {
375 // If CPU or OS do not support TM:
376 // Can't continue because UseRTMLocking affects UseBiasedLocking flag
377 // setting during arguments processing. See use_biased_locking().
378 // VM_Version_init() is executed after UseBiasedLocking is used
379 // in Thread::allocate().
380 if (PowerArchitecturePPC64 < 8) {
381 vm_exit_during_initialization("RTM instructions are not available on this CPU.");
382 }
383
384 if (!has_tm()) {
385 vm_exit_during_initialization("RTM is not supported on this OS version.");
386 }
387 }
388
389 if (UseRTMLocking) {
390 #if INCLUDE_RTM_OPT
391 if (!FLAG_IS_CMDLINE(UseRTMLocking)) {
392 // RTM locking should be used only for applications with
393 // high lock contention. For now we do not use it by default.
394 vm_exit_during_initialization("UseRTMLocking flag should be only set on command line");
395 }
396 #else
397 // Only C2 does RTM locking optimization.
398 // Can't continue because UseRTMLocking affects UseBiasedLocking flag
399 // setting during arguments processing. See use_biased_locking().
400 vm_exit_during_initialization("RTM locking optimization is not supported in this VM");
401 #endif
402 } else { // !UseRTMLocking
403 if (UseRTMForStackLocks) {
404 if (!FLAG_IS_DEFAULT(UseRTMForStackLocks)) {
405 warning("UseRTMForStackLocks flag should be off when UseRTMLocking flag is off");
406 }
407 FLAG_SET_DEFAULT(UseRTMForStackLocks, false);
408 }
409 if (UseRTMDeopt) {
410 FLAG_SET_DEFAULT(UseRTMDeopt, false);
411 }
412 #ifdef COMPILER2
413 if (PrintPreciseRTMLockingStatistics) {
414 FLAG_SET_DEFAULT(PrintPreciseRTMLockingStatistics, false);
415 }
416 #endif
417 }
418
419 // This machine allows unaligned memory accesses
420 if (FLAG_IS_DEFAULT(UseUnalignedAccesses)) {
421 FLAG_SET_DEFAULT(UseUnalignedAccesses, true);
422 }
423
424 check_virtualizations();
425 }
426
427 void VM_Version::check_virtualizations() {
428 #if defined(_AIX)
429 int rc = 0;
430 perfstat_partition_total_t pinfo;
431 rc = perfstat_partition_total(NULL, &pinfo, sizeof(perfstat_partition_total_t), 1);
432 if (rc == 1) {
433 Abstract_VM_Version::_detected_virtualization = PowerVM;
434 }
435 #else
436 const char* info_file = "/proc/ppc64/lparcfg";
437 // system_type=...qemu indicates PowerKVM
438 // e.g. system_type=IBM pSeries (emulated by qemu)
439 char line[500];
440 FILE* fp = fopen(info_file, "r");
441 if (fp == NULL) {
442 return;
443 }
444 const char* system_type="system_type="; // in case this line contains qemu, it is KVM
445 const char* num_lpars="NumLpars="; // in case of non-KVM : if this line is found it is PowerVM
446 bool num_lpars_found = false;
447
448 while (fgets(line, sizeof(line), fp) != NULL) {
449 if (strncmp(line, system_type, strlen(system_type)) == 0) {
450 if (strstr(line, "qemu") != 0) {
451 Abstract_VM_Version::_detected_virtualization = PowerKVM;
452 fclose(fp);
453 return;
454 }
455 }
456 if (strncmp(line, num_lpars, strlen(num_lpars)) == 0) {
457 num_lpars_found = true;
458 }
459 }
460 if (num_lpars_found) {
461 Abstract_VM_Version::_detected_virtualization = PowerVM;
462 } else {
463 Abstract_VM_Version::_detected_virtualization = PowerFullPartitionMode;
464 }
465 fclose(fp);
466 #endif
467 }
468
469 void VM_Version::print_platform_virtualization_info(outputStream* st) {
470 #if defined(_AIX)
471 // more info about perfstat API see
472 // https://www.ibm.com/support/knowledgecenter/en/ssw_aix_72/com.ibm.aix.prftools/idprftools_perfstat_glob_partition.htm
473 int rc = 0;
474 perfstat_partition_total_t pinfo;
475 memset(&pinfo, 0, sizeof(perfstat_partition_total_t));
476 rc = perfstat_partition_total(NULL, &pinfo, sizeof(perfstat_partition_total_t), 1);
477 if (rc != 1) {
478 return;
479 } else {
480 st->print_cr("Virtualization type : PowerVM");
481 }
482 // CPU information
483 perfstat_cpu_total_t cpuinfo;
484 memset(&cpuinfo, 0, sizeof(perfstat_cpu_total_t));
485 rc = perfstat_cpu_total(NULL, &cpuinfo, sizeof(perfstat_cpu_total_t), 1);
486 if (rc != 1) {
487 return;
488 }
489
490 st->print_cr("Processor description : %s", cpuinfo.description);
491 st->print_cr("Processor speed : %llu Hz", cpuinfo.processorHZ);
492
493 st->print_cr("LPAR partition name : %s", pinfo.name);
494 st->print_cr("LPAR partition number : %u", pinfo.lpar_id);
495 st->print_cr("LPAR partition type : %s", pinfo.type.b.shared_enabled ? "shared" : "dedicated");
496 st->print_cr("LPAR mode : %s", pinfo.type.b.donate_enabled ? "donating" : pinfo.type.b.capped ? "capped" : "uncapped");
497 st->print_cr("LPAR partition group ID : %u", pinfo.group_id);
498 st->print_cr("LPAR shared pool ID : %u", pinfo.pool_id);
499
500 st->print_cr("AMS (active memory sharing) : %s", pinfo.type.b.ams_capable ? "capable" : "not capable");
501 st->print_cr("AMS (active memory sharing) : %s", pinfo.type.b.ams_enabled ? "on" : "off");
502 st->print_cr("AME (active memory expansion) : %s", pinfo.type.b.ame_enabled ? "on" : "off");
503
504 if (pinfo.type.b.ame_enabled) {
505 st->print_cr("AME true memory in bytes : %llu", pinfo.true_memory);
506 st->print_cr("AME expanded memory in bytes : %llu", pinfo.expanded_memory);
507 }
508
509 st->print_cr("SMT : %s", pinfo.type.b.smt_capable ? "capable" : "not capable");
510 st->print_cr("SMT : %s", pinfo.type.b.smt_enabled ? "on" : "off");
511 int ocpus = pinfo.online_cpus > 0 ? pinfo.online_cpus : 1;
512 st->print_cr("LPAR threads : %d", cpuinfo.ncpus/ocpus);
513 st->print_cr("LPAR online virtual cpus : %d", pinfo.online_cpus);
514 st->print_cr("LPAR logical cpus : %d", cpuinfo.ncpus);
515 st->print_cr("LPAR maximum virtual cpus : %u", pinfo.max_cpus);
516 st->print_cr("LPAR minimum virtual cpus : %u", pinfo.min_cpus);
517 st->print_cr("LPAR entitled capacity : %4.2f", (double) (pinfo.entitled_proc_capacity/100.0));
518 st->print_cr("LPAR online memory : %llu MB", pinfo.online_memory);
519 st->print_cr("LPAR maximum memory : %llu MB", pinfo.max_memory);
520 st->print_cr("LPAR minimum memory : %llu MB", pinfo.min_memory);
521 #else
522 const char* info_file = "/proc/ppc64/lparcfg";
523 const char* kw[] = { "system_type=", // qemu indicates PowerKVM
524 "partition_entitled_capacity=", // entitled processor capacity percentage
525 "partition_max_entitled_capacity=",
526 "capacity_weight=", // partition CPU weight
527 "partition_active_processors=",
528 "partition_potential_processors=",
529 "entitled_proc_capacity_available=",
530 "capped=", // 0 - uncapped, 1 - vcpus capped at entitled processor capacity percentage
531 "shared_processor_mode=", // (non)dedicated partition
532 "system_potential_processors=",
533 "pool=", // CPU-pool number
534 "pool_capacity=",
535 "NumLpars=", // on non-KVM machines, NumLpars is not found for full partition mode machines
536 NULL };
537 if (!print_matching_lines_from_file(info_file, st, kw)) {
538 st->print_cr(" <%s Not Available>", info_file);
539 }
540 #endif
541 }
542
543 bool VM_Version::use_biased_locking() {
544 #if INCLUDE_RTM_OPT
545 // RTM locking is most useful when there is high lock contention and
546 // low data contention. With high lock contention the lock is usually
547 // inflated and biased locking is not suitable for that case.
548 // RTM locking code requires that biased locking is off.
549 // Note: we can't switch off UseBiasedLocking in get_processor_features()
550 // because it is used by Thread::allocate() which is called before
551 // VM_Version::initialize().
552 if (UseRTMLocking && UseBiasedLocking) {
553 if (FLAG_IS_DEFAULT(UseBiasedLocking)) {
554 FLAG_SET_DEFAULT(UseBiasedLocking, false);
555 } else {
556 warning("Biased locking is not supported with RTM locking; ignoring UseBiasedLocking flag." );
557 UseBiasedLocking = false;
558 }
559 }
560 #endif
561 return UseBiasedLocking;
562 }
563
564 void VM_Version::print_features() {
565 tty->print_cr("Version: %s L1_data_cache_line_size=%d", features_string(), L1_data_cache_line_size());
566
567 if (Verbose) {
568 if (ContendedPaddingWidth > 0) {
569 tty->cr();
570 tty->print_cr("ContendedPaddingWidth " INTX_FORMAT, ContendedPaddingWidth);
571 }
572 }
573 }
574
575 #ifdef COMPILER2
576 // Determine section size on power6: If section size is 8 instructions,
577 // there should be a difference between the two testloops of ~15 %. If
578 // no difference is detected the section is assumed to be 32 instructions.
579 void VM_Version::determine_section_size() {
580
581 int unroll = 80;
582
583 const int code_size = (2* unroll * 32 + 100)*BytesPerInstWord;
584
585 // Allocate space for the code.
586 ResourceMark rm;
587 CodeBuffer cb("detect_section_size", code_size, 0);
588 MacroAssembler* a = new MacroAssembler(&cb);
589
590 uint32_t *code = (uint32_t *)a->pc();
591 // Emit code.
592 void (*test1)() = (void(*)())(void *)a->function_entry();
593
594 Label l1;
595
596 a->li(R4, 1);
597 a->sldi(R4, R4, 28);
598 a->b(l1);
599 a->align(CodeEntryAlignment);
600
601 a->bind(l1);
602
603 for (int i = 0; i < unroll; i++) {
604 // Schleife 1
605 // ------- sector 0 ------------
606 // ;; 0
607 a->nop(); // 1
608 a->fpnop0(); // 2
609 a->fpnop1(); // 3
610 a->addi(R4,R4, -1); // 4
611
612 // ;; 1
613 a->nop(); // 5
614 a->fmr(F6, F6); // 6
615 a->fmr(F7, F7); // 7
616 a->endgroup(); // 8
617 // ------- sector 8 ------------
618
619 // ;; 2
620 a->nop(); // 9
621 a->nop(); // 10
622 a->fmr(F8, F8); // 11
623 a->fmr(F9, F9); // 12
624
625 // ;; 3
626 a->nop(); // 13
627 a->fmr(F10, F10); // 14
628 a->fmr(F11, F11); // 15
629 a->endgroup(); // 16
630 // -------- sector 16 -------------
631
632 // ;; 4
633 a->nop(); // 17
634 a->nop(); // 18
635 a->fmr(F15, F15); // 19
636 a->fmr(F16, F16); // 20
637
638 // ;; 5
639 a->nop(); // 21
640 a->fmr(F17, F17); // 22
641 a->fmr(F18, F18); // 23
642 a->endgroup(); // 24
643 // ------- sector 24 ------------
644
645 // ;; 6
646 a->nop(); // 25
647 a->nop(); // 26
648 a->fmr(F19, F19); // 27
649 a->fmr(F20, F20); // 28
650
651 // ;; 7
652 a->nop(); // 29
653 a->fmr(F21, F21); // 30
654 a->fmr(F22, F22); // 31
655 a->brnop0(); // 32
656
657 // ------- sector 32 ------------
658 }
659
660 // ;; 8
661 a->cmpdi(CCR0, R4, unroll); // 33
662 a->bge(CCR0, l1); // 34
663 a->blr();
664
665 // Emit code.
666 void (*test2)() = (void(*)())(void *)a->function_entry();
667 // uint32_t *code = (uint32_t *)a->pc();
668
669 Label l2;
670
671 a->li(R4, 1);
672 a->sldi(R4, R4, 28);
673 a->b(l2);
674 a->align(CodeEntryAlignment);
675
676 a->bind(l2);
677
678 for (int i = 0; i < unroll; i++) {
679 // Schleife 2
680 // ------- sector 0 ------------
681 // ;; 0
682 a->brnop0(); // 1
683 a->nop(); // 2
684 //a->cmpdi(CCR0, R4, unroll);
685 a->fpnop0(); // 3
686 a->fpnop1(); // 4
687 a->addi(R4,R4, -1); // 5
688
689 // ;; 1
690
691 a->nop(); // 6
692 a->fmr(F6, F6); // 7
693 a->fmr(F7, F7); // 8
694 // ------- sector 8 ---------------
695
696 // ;; 2
697 a->endgroup(); // 9
698
699 // ;; 3
700 a->nop(); // 10
701 a->nop(); // 11
702 a->fmr(F8, F8); // 12
703
704 // ;; 4
705 a->fmr(F9, F9); // 13
706 a->nop(); // 14
707 a->fmr(F10, F10); // 15
708
709 // ;; 5
710 a->fmr(F11, F11); // 16
711 // -------- sector 16 -------------
712
713 // ;; 6
714 a->endgroup(); // 17
715
716 // ;; 7
717 a->nop(); // 18
718 a->nop(); // 19
719 a->fmr(F15, F15); // 20
720
721 // ;; 8
722 a->fmr(F16, F16); // 21
723 a->nop(); // 22
724 a->fmr(F17, F17); // 23
725
726 // ;; 9
727 a->fmr(F18, F18); // 24
728 // -------- sector 24 -------------
729
730 // ;; 10
731 a->endgroup(); // 25
732
733 // ;; 11
734 a->nop(); // 26
735 a->nop(); // 27
736 a->fmr(F19, F19); // 28
737
738 // ;; 12
739 a->fmr(F20, F20); // 29
740 a->nop(); // 30
741 a->fmr(F21, F21); // 31
742
743 // ;; 13
744 a->fmr(F22, F22); // 32
745 }
746
747 // -------- sector 32 -------------
748 // ;; 14
749 a->cmpdi(CCR0, R4, unroll); // 33
750 a->bge(CCR0, l2); // 34
751
752 a->blr();
753 uint32_t *code_end = (uint32_t *)a->pc();
754 a->flush();
755
756 cb.insts()->set_end((u_char*)code_end);
757
758 double loop1_seconds,loop2_seconds, rel_diff;
759 uint64_t start1, stop1;
760
761 start1 = os::current_thread_cpu_time(false);
762 (*test1)();
763 stop1 = os::current_thread_cpu_time(false);
764 loop1_seconds = (stop1- start1) / (1000 *1000 *1000.0);
765
766
767 start1 = os::current_thread_cpu_time(false);
768 (*test2)();
769 stop1 = os::current_thread_cpu_time(false);
770
771 loop2_seconds = (stop1 - start1) / (1000 *1000 *1000.0);
772
773 rel_diff = (loop2_seconds - loop1_seconds) / loop1_seconds *100;
774
775 if (PrintAssembly || PrintStubCode) {
776 ttyLocker ttyl;
777 tty->print_cr("Decoding section size detection stub at " INTPTR_FORMAT " before execution:", p2i(code));
778 // Use existing decode function. This enables the [MachCode] format which is needed to DecodeErrorFile.
779 Disassembler::decode(&cb, (u_char*)code, (u_char*)code_end, tty);
780 tty->print_cr("Time loop1 :%f", loop1_seconds);
781 tty->print_cr("Time loop2 :%f", loop2_seconds);
782 tty->print_cr("(time2 - time1) / time1 = %f %%", rel_diff);
783
784 if (rel_diff > 12.0) {
785 tty->print_cr("Section Size 8 Instructions");
786 } else{
787 tty->print_cr("Section Size 32 Instructions or Power5");
788 }
789 }
790
791 #if 0 // TODO: PPC port
792 // Set sector size (if not set explicitly).
793 if (FLAG_IS_DEFAULT(Power6SectorSize128PPC64)) {
794 if (rel_diff > 12.0) {
795 PdScheduling::power6SectorSize = 0x20;
796 } else {
797 PdScheduling::power6SectorSize = 0x80;
798 }
799 } else if (Power6SectorSize128PPC64) {
800 PdScheduling::power6SectorSize = 0x80;
801 } else {
802 PdScheduling::power6SectorSize = 0x20;
803 }
804 #endif
805 if (UsePower6SchedulerPPC64) Unimplemented();
806 }
807 #endif // COMPILER2
808
809 void VM_Version::determine_features() {
810 #if defined(ABI_ELFv2)
811 // 1 InstWord per call for the blr instruction.
812 const int code_size = (num_features+1+2*1)*BytesPerInstWord;
813 #else
814 // 7 InstWords for each call (function descriptor + blr instruction).
815 const int code_size = (num_features+1+2*7)*BytesPerInstWord;
816 #endif
817 int features = 0;
818
819 // create test area
820 enum { BUFFER_SIZE = 2*4*K }; // Needs to be >=2* max cache line size (cache line size can't exceed min page size).
821 char test_area[BUFFER_SIZE];
822 char *mid_of_test_area = &test_area[BUFFER_SIZE>>1];
823
824 // Allocate space for the code.
825 ResourceMark rm;
826 CodeBuffer cb("detect_cpu_features", code_size, 0);
827 MacroAssembler* a = new MacroAssembler(&cb);
828
829 // Must be set to true so we can generate the test code.
830 _features = VM_Version::all_features_m;
831
832 // Emit code.
833 void (*test)(address addr, uint64_t offset)=(void(*)(address addr, uint64_t offset))(void *)a->function_entry();
834 uint32_t *code = (uint32_t *)a->pc();
835 // Don't use R0 in ldarx.
836 // Keep R3_ARG1 unmodified, it contains &field (see below).
837 // Keep R4_ARG2 unmodified, it contains offset = 0 (see below).
838 a->fsqrt(F3, F4); // code[0] -> fsqrt_m
839 a->fsqrts(F3, F4); // code[1] -> fsqrts_m
840 a->isel(R7, R5, R6, 0); // code[2] -> isel_m
841 a->ldarx_unchecked(R7, R3_ARG1, R4_ARG2, 1); // code[3] -> lxarx_m
842 a->cmpb(R7, R5, R6); // code[4] -> cmpb
843 a->popcntb(R7, R5); // code[5] -> popcntb
844 a->popcntw(R7, R5); // code[6] -> popcntw
845 a->fcfids(F3, F4); // code[7] -> fcfids
846 a->vand(VR0, VR0, VR0); // code[8] -> vand
847 // arg0 of lqarx must be an even register, (arg1 + arg2) must be a multiple of 16
848 a->lqarx_unchecked(R6, R3_ARG1, R4_ARG2, 1); // code[9] -> lqarx_m
849 a->vcipher(VR0, VR1, VR2); // code[10] -> vcipher
850 a->vpmsumb(VR0, VR1, VR2); // code[11] -> vpmsumb
851 a->mfdscr(R0); // code[12] -> mfdscr
852 a->lxvd2x(VSR0, R3_ARG1); // code[13] -> vsx
853 a->ldbrx(R7, R3_ARG1, R4_ARG2); // code[14] -> ldbrx
854 a->stdbrx(R7, R3_ARG1, R4_ARG2); // code[15] -> stdbrx
855 a->vshasigmaw(VR0, VR1, 1, 0xF); // code[16] -> vshasig
856 // rtm is determined by OS
857 a->darn(R7); // code[17] -> darn
858 a->brw(R5, R6); // code[18] -> brw
859 a->blr();
860
861 // Emit function to set one cache line to zero. Emit function descriptor and get pointer to it.
862 void (*zero_cacheline_func_ptr)(char*) = (void(*)(char*))(void *)a->function_entry();
863 a->dcbz(R3_ARG1); // R3_ARG1 = addr
864 a->blr();
865
866 uint32_t *code_end = (uint32_t *)a->pc();
867 a->flush();
868 _features = VM_Version::unknown_m;
869
870 // Print the detection code.
871 if (PrintAssembly) {
872 ttyLocker ttyl;
873 tty->print_cr("Decoding cpu-feature detection stub at " INTPTR_FORMAT " before execution:", p2i(code));
874 Disassembler::decode((u_char*)code, (u_char*)code_end, tty);
875 }
876
877 // Measure cache line size.
878 memset(test_area, 0xFF, BUFFER_SIZE); // Fill test area with 0xFF.
879 (*zero_cacheline_func_ptr)(mid_of_test_area); // Call function which executes dcbz to the middle.
880 int count = 0; // count zeroed bytes
881 for (int i = 0; i < BUFFER_SIZE; i++) if (test_area[i] == 0) count++;
882 guarantee(is_power_of_2(count), "cache line size needs to be a power of 2");
883 _L1_data_cache_line_size = count;
884
885 // Execute code. Illegal instructions will be replaced by 0 in the signal handler.
886 VM_Version::_is_determine_features_test_running = true;
887 // We must align the first argument to 16 bytes because of the lqarx check.
888 (*test)(align_up((address)mid_of_test_area, 16), 0);
889 VM_Version::_is_determine_features_test_running = false;
890
891 // determine which instructions are legal.
892 int feature_cntr = 0;
893 if (code[feature_cntr++]) features |= fsqrt_m;
894 if (code[feature_cntr++]) features |= fsqrts_m;
895 if (code[feature_cntr++]) features |= isel_m;
896 if (code[feature_cntr++]) features |= lxarxeh_m;
897 if (code[feature_cntr++]) features |= cmpb_m;
898 if (code[feature_cntr++]) features |= popcntb_m;
899 if (code[feature_cntr++]) features |= popcntw_m;
900 if (code[feature_cntr++]) features |= fcfids_m;
901 if (code[feature_cntr++]) features |= vand_m;
902 if (code[feature_cntr++]) features |= lqarx_m;
903 if (code[feature_cntr++]) features |= vcipher_m;
904 if (code[feature_cntr++]) features |= vpmsumb_m;
905 if (code[feature_cntr++]) features |= mfdscr_m;
906 if (code[feature_cntr++]) features |= vsx_m;
907 if (code[feature_cntr++]) features |= ldbrx_m;
908 if (code[feature_cntr++]) features |= stdbrx_m;
909 if (code[feature_cntr++]) features |= vshasig_m;
910 // feature rtm_m is determined by OS
911 if (code[feature_cntr++]) features |= darn_m;
912 if (code[feature_cntr++]) features |= brw_m;
913
914 // Print the detection code.
915 if (PrintAssembly) {
916 ttyLocker ttyl;
917 tty->print_cr("Decoding cpu-feature detection stub at " INTPTR_FORMAT " after execution:", p2i(code));
918 Disassembler::decode((u_char*)code, (u_char*)code_end, tty);
919 }
920
921 _features = features;
922
923 #ifdef AIX
924 // To enable it on AIX it's necessary POWER8 or above and at least AIX 7.2.
925 // Actually, this is supported since AIX 7.1.. Unfortunately, this first
926 // contained bugs, so that it can only be enabled after AIX 7.1.3.30.
927 // The Java property os.version, which is used in RTM tests to decide
928 // whether the feature is available, only knows major and minor versions.
929 // We don't want to change this property, as user code might depend on it.
930 // So the tests can not check on subversion 3.30, and we only enable RTM
931 // with AIX 7.2.
932 if (has_lqarx()) { // POWER8 or above
933 if (os::Aix::os_version() >= 0x07020000) { // At least AIX 7.2.
934 _features |= rtm_m;
935 }
936 }
937 #endif
938 #if defined(LINUX) && defined(VM_LITTLE_ENDIAN)
939 unsigned long auxv = getauxval(AT_HWCAP2);
940
941 if (auxv & PPC_FEATURE2_HTM_NOSC) {
942 if (auxv & PPC_FEATURE2_HAS_HTM) {
943 // TM on POWER8 and POWER9 in compat mode (VM) is supported by the JVM.
944 // TM on POWER9 DD2.1 NV (baremetal) is not supported by the JVM (TM on
945 // POWER9 DD2.1 NV has a few issues that need a couple of firmware
946 // and kernel workarounds, so there is a new mode only supported
947 // on non-virtualized P9 machines called HTM with no Suspend Mode).
948 // TM on POWER9 D2.2+ NV is not supported at all by Linux.
949 _features |= rtm_m;
950 }
951 }
952 #endif
953 }
954
955 // Power 8: Configure Data Stream Control Register.
956 void VM_Version::config_dscr() {
957 // 7 InstWords for each call (function descriptor + blr instruction).
958 const int code_size = (2+2*7)*BytesPerInstWord;
959
960 // Allocate space for the code.
961 ResourceMark rm;
962 CodeBuffer cb("config_dscr", code_size, 0);
963 MacroAssembler* a = new MacroAssembler(&cb);
964
965 // Emit code.
966 uint64_t (*get_dscr)() = (uint64_t(*)())(void *)a->function_entry();
967 uint32_t *code = (uint32_t *)a->pc();
968 a->mfdscr(R3);
969 a->blr();
970
971 void (*set_dscr)(long) = (void(*)(long))(void *)a->function_entry();
972 a->mtdscr(R3);
973 a->blr();
974
975 uint32_t *code_end = (uint32_t *)a->pc();
976 a->flush();
977
978 // Print the detection code.
979 if (PrintAssembly) {
980 ttyLocker ttyl;
981 tty->print_cr("Decoding dscr configuration stub at " INTPTR_FORMAT " before execution:", p2i(code));
982 Disassembler::decode((u_char*)code, (u_char*)code_end, tty);
983 }
984
985 // Apply the configuration if needed.
986 _dscr_val = (*get_dscr)();
987 if (Verbose) {
988 tty->print_cr("dscr value was 0x%lx" , _dscr_val);
989 }
990 bool change_requested = false;
991 if (DSCR_PPC64 != (uintx)-1) {
992 _dscr_val = DSCR_PPC64;
993 change_requested = true;
994 }
995 if (DSCR_DPFD_PPC64 <= 7) {
996 uint64_t mask = 0x7;
997 if ((_dscr_val & mask) != DSCR_DPFD_PPC64) {
998 _dscr_val = (_dscr_val & ~mask) | (DSCR_DPFD_PPC64);
999 change_requested = true;
1000 }
1001 }
1002 if (DSCR_URG_PPC64 <= 7) {
1003 uint64_t mask = 0x7 << 6;
1004 if ((_dscr_val & mask) != DSCR_DPFD_PPC64 << 6) {
1005 _dscr_val = (_dscr_val & ~mask) | (DSCR_URG_PPC64 << 6);
1006 change_requested = true;
1007 }
1008 }
1009 if (change_requested) {
1010 (*set_dscr)(_dscr_val);
1011 if (Verbose) {
1012 tty->print_cr("dscr was set to 0x%lx" , (*get_dscr)());
1013 }
1014 }
1015 }
1016
1017 static uint64_t saved_features = 0;
1018
1019 void VM_Version::allow_all() {
1020 saved_features = _features;
1021 _features = all_features_m;
1022 }
1023
1024 void VM_Version::revert() {
1025 _features = saved_features;
1026 }