1 /*
2 * Copyright (c) 1997, 2020, Oracle and/or its affiliates. All rights reserved.
3 * Copyright (c) 2012, 2020 SAP SE. All rights reserved.
4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
5 *
6 * This code is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 only, as
8 * published by the Free Software Foundation.
9 *
10 * This code is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * version 2 for more details (a copy is included in the LICENSE file that
14 * accompanied this code).
15 *
16 * You should have received a copy of the GNU General Public License version
17 * 2 along with this work; if not, write to the Free Software Foundation,
18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 * or visit www.oracle.com if you need additional information or have any
22 * questions.
23 *
24 */
25
26 #include "precompiled.hpp"
27 #include "jvm.h"
28 #include "asm/assembler.inline.hpp"
29 #include "asm/macroAssembler.inline.hpp"
30 #include "compiler/disassembler.hpp"
31 #include "memory/resourceArea.hpp"
32 #include "runtime/java.hpp"
33 #include "runtime/os.hpp"
34 #include "runtime/stubCodeGenerator.hpp"
35 #include "runtime/vm_version.hpp"
36 #include "utilities/align.hpp"
37 #include "utilities/defaultStream.hpp"
38 #include "utilities/globalDefinitions.hpp"
39 #include "utilities/powerOfTwo.hpp"
40
41 #include <sys/sysinfo.h>
42 #if defined(_AIX)
43 #include <libperfstat.h>
44 #endif
45
46 #if defined(LINUX) && defined(VM_LITTLE_ENDIAN)
47 #include <sys/auxv.h>
48
49 #ifndef PPC_FEATURE2_HTM_NOSC
50 #define PPC_FEATURE2_HTM_NOSC (1 << 24)
51 #endif
52 #endif
53
54 bool VM_Version::_is_determine_features_test_running = false;
55 uint64_t VM_Version::_dscr_val = 0;
56
57 #define MSG(flag) \
58 if (flag && !FLAG_IS_DEFAULT(flag)) \
59 jio_fprintf(defaultStream::error_stream(), \
60 "warning: -XX:+" #flag " requires -XX:+UseSIGTRAP\n" \
61 " -XX:+" #flag " will be disabled!\n");
62
63 void VM_Version::initialize() {
64
65 // Test which instructions are supported and measure cache line size.
66 determine_features();
67
68 // If PowerArchitecturePPC64 hasn't been specified explicitly determine from features.
69 if (FLAG_IS_DEFAULT(PowerArchitecturePPC64)) {
70 if (VM_Version::has_brw()) {
71 FLAG_SET_ERGO(PowerArchitecturePPC64, 10);
72 } else if (VM_Version::has_darn()) {
73 FLAG_SET_ERGO(PowerArchitecturePPC64, 9);
74 } else if (VM_Version::has_lqarx()) {
75 FLAG_SET_ERGO(PowerArchitecturePPC64, 8);
76 } else if (VM_Version::has_popcntw()) {
77 FLAG_SET_ERGO(PowerArchitecturePPC64, 7);
78 } else if (VM_Version::has_cmpb()) {
79 FLAG_SET_ERGO(PowerArchitecturePPC64, 6);
80 } else if (VM_Version::has_popcntb()) {
81 FLAG_SET_ERGO(PowerArchitecturePPC64, 5);
82 } else {
83 FLAG_SET_ERGO(PowerArchitecturePPC64, 0);
84 }
85 }
86
87 bool PowerArchitecturePPC64_ok = false;
88 switch (PowerArchitecturePPC64) {
89 case 10: if (!VM_Version::has_brw() ) break;
90 case 9: if (!VM_Version::has_darn() ) break;
91 case 8: if (!VM_Version::has_lqarx() ) break;
92 case 7: if (!VM_Version::has_popcntw()) break;
93 case 6: if (!VM_Version::has_cmpb() ) break;
94 case 5: if (!VM_Version::has_popcntb()) break;
95 case 0: PowerArchitecturePPC64_ok = true; break;
96 default: break;
97 }
98 guarantee(PowerArchitecturePPC64_ok, "PowerArchitecturePPC64 cannot be set to "
99 UINTX_FORMAT " on this machine", PowerArchitecturePPC64);
100
101 // Power 8: Configure Data Stream Control Register.
102 if (PowerArchitecturePPC64 >= 8 && has_mfdscr()) {
103 config_dscr();
104 }
105
106 if (!UseSIGTRAP) {
107 MSG(TrapBasedICMissChecks);
108 MSG(TrapBasedNullChecks);
109 FLAG_SET_ERGO(TrapBasedNullChecks, false);
110 FLAG_SET_ERGO(TrapBasedICMissChecks, false);
111 }
112
113 #ifdef COMPILER2
114 if (!UseSIGTRAP) {
115 MSG(TrapBasedRangeChecks);
116 FLAG_SET_ERGO(TrapBasedRangeChecks, false);
117 }
118
119 // On Power6 test for section size.
120 if (PowerArchitecturePPC64 == 6) {
121 determine_section_size();
122 // TODO: PPC port } else {
123 // TODO: PPC port PdScheduling::power6SectorSize = 0x20;
124 }
125
126 if (PowerArchitecturePPC64 >= 8) {
127 if (FLAG_IS_DEFAULT(SuperwordUseVSX)) {
128 FLAG_SET_ERGO(SuperwordUseVSX, true);
129 }
130 } else {
131 if (SuperwordUseVSX) {
132 warning("SuperwordUseVSX specified, but needs at least Power8.");
133 FLAG_SET_DEFAULT(SuperwordUseVSX, false);
134 }
135 }
136 MaxVectorSize = SuperwordUseVSX ? 16 : 8;
137
138 if (PowerArchitecturePPC64 >= 9) {
139 if (FLAG_IS_DEFAULT(UseCountTrailingZerosInstructionsPPC64)) {
140 FLAG_SET_ERGO(UseCountTrailingZerosInstructionsPPC64, true);
141 }
142 if (FLAG_IS_DEFAULT(UseCharacterCompareIntrinsics)) {
143 FLAG_SET_ERGO(UseCharacterCompareIntrinsics, true);
144 }
145 if (FLAG_IS_DEFAULT(UseVectorByteReverseInstructionsPPC64)) {
146 FLAG_SET_ERGO(UseVectorByteReverseInstructionsPPC64, true);
147 }
148 } else {
149 if (UseCountTrailingZerosInstructionsPPC64) {
150 warning("UseCountTrailingZerosInstructionsPPC64 specified, but needs at least Power9.");
151 FLAG_SET_DEFAULT(UseCountTrailingZerosInstructionsPPC64, false);
152 }
153 if (UseCharacterCompareIntrinsics) {
154 warning("UseCharacterCompareIntrinsics specified, but needs at least Power9.");
155 FLAG_SET_DEFAULT(UseCharacterCompareIntrinsics, false);
156 }
157 if (UseVectorByteReverseInstructionsPPC64) {
158 warning("UseVectorByteReverseInstructionsPPC64 specified, but needs at least Power9.");
159 FLAG_SET_DEFAULT(UseVectorByteReverseInstructionsPPC64, false);
160 }
161 }
162
163 if (PowerArchitecturePPC64 >= 10) {
164 if (FLAG_IS_DEFAULT(UseByteReverseInstructions)) {
165 FLAG_SET_ERGO(UseByteReverseInstructions, true);
166 }
167 } else {
168 if (UseByteReverseInstructions) {
169 warning("UseByteReverseInstructions specified, but needs at least Power10.");
170 FLAG_SET_DEFAULT(UseByteReverseInstructions, false);
171 }
172 }
173 #endif
174
175 // Create and print feature-string.
176 char buf[(num_features+1) * 16]; // Max 16 chars per feature.
177 jio_snprintf(buf, sizeof(buf),
178 "ppc64%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s",
179 (has_fsqrt() ? " fsqrt" : ""),
180 (has_isel() ? " isel" : ""),
181 (has_lxarxeh() ? " lxarxeh" : ""),
182 (has_cmpb() ? " cmpb" : ""),
183 (has_popcntb() ? " popcntb" : ""),
184 (has_popcntw() ? " popcntw" : ""),
185 (has_fcfids() ? " fcfids" : ""),
186 (has_vand() ? " vand" : ""),
187 (has_lqarx() ? " lqarx" : ""),
188 (has_vcipher() ? " aes" : ""),
189 (has_vpmsumb() ? " vpmsumb" : ""),
190 (has_mfdscr() ? " mfdscr" : ""),
191 (has_vsx() ? " vsx" : ""),
192 (has_ldbrx() ? " ldbrx" : ""),
193 (has_stdbrx() ? " stdbrx" : ""),
194 (has_vshasig() ? " sha" : ""),
195 (has_tm() ? " rtm" : ""),
196 (has_darn() ? " darn" : ""),
197 (has_brw() ? " brw" : "")
198 // Make sure number of %s matches num_features!
199 );
200 _features_string = os::strdup(buf);
201 if (Verbose) {
202 print_features();
203 }
204
205 // PPC64 supports 8-byte compare-exchange operations (see Atomic::cmpxchg)
206 // and 'atomic long memory ops' (see Unsafe_GetLongVolatile).
207 _supports_cx8 = true;
208
209 // Used by C1.
210 _supports_atomic_getset4 = true;
211 _supports_atomic_getadd4 = true;
212 _supports_atomic_getset8 = true;
213 _supports_atomic_getadd8 = true;
214
215 intx cache_line_size = L1_data_cache_line_size();
216
217 if (PowerArchitecturePPC64 >= 9) {
218 if (os::supports_map_sync() == true) {
219 _data_cache_line_flush_size = cache_line_size;
220 }
221 }
222
223 if (FLAG_IS_DEFAULT(AllocatePrefetchStyle)) AllocatePrefetchStyle = 1;
224
225 if (cache_line_size > AllocatePrefetchStepSize) AllocatePrefetchStepSize = cache_line_size;
226 // PPC processors have an automatic prefetch engine.
227 if (FLAG_IS_DEFAULT(AllocatePrefetchLines)) AllocatePrefetchLines = 1;
228 if (AllocatePrefetchDistance < 0) AllocatePrefetchDistance = 3 * cache_line_size;
229
230 assert(AllocatePrefetchLines > 0, "invalid value");
231 if (AllocatePrefetchLines < 1) { // Set valid value in product VM.
232 AllocatePrefetchLines = 1; // Conservative value.
233 }
234
235 if (AllocatePrefetchStyle == 3 && AllocatePrefetchDistance < cache_line_size) {
236 AllocatePrefetchStyle = 1; // Fall back if inappropriate.
237 }
238
239 assert(AllocatePrefetchStyle >= 0, "AllocatePrefetchStyle should be positive");
240
241 if (FLAG_IS_DEFAULT(ContendedPaddingWidth) && (cache_line_size > ContendedPaddingWidth)) {
242 ContendedPaddingWidth = cache_line_size;
243 }
244
245 // If running on Power8 or newer hardware, the implementation uses the available vector instructions.
246 // In all other cases, the implementation uses only generally available instructions.
247 if (!UseCRC32Intrinsics) {
248 if (FLAG_IS_DEFAULT(UseCRC32Intrinsics)) {
249 FLAG_SET_DEFAULT(UseCRC32Intrinsics, true);
250 }
251 }
252
253 // Implementation does not use any of the vector instructions available with Power8.
254 // Their exploitation is still pending (aka "work in progress").
255 if (!UseCRC32CIntrinsics) {
256 if (FLAG_IS_DEFAULT(UseCRC32CIntrinsics)) {
257 FLAG_SET_DEFAULT(UseCRC32CIntrinsics, true);
258 }
259 }
260
261 // TODO: Provide implementation.
262 if (UseAdler32Intrinsics) {
263 warning("Adler32Intrinsics not available on this CPU.");
264 FLAG_SET_DEFAULT(UseAdler32Intrinsics, false);
265 }
266
267 // The AES intrinsic stubs require AES instruction support.
268 if (has_vcipher()) {
269 if (FLAG_IS_DEFAULT(UseAES)) {
270 UseAES = true;
271 }
272 } else if (UseAES) {
273 if (!FLAG_IS_DEFAULT(UseAES))
274 warning("AES instructions are not available on this CPU");
275 FLAG_SET_DEFAULT(UseAES, false);
276 }
277
278 if (UseAES && has_vcipher()) {
279 if (FLAG_IS_DEFAULT(UseAESIntrinsics)) {
280 UseAESIntrinsics = true;
281 }
282 } else if (UseAESIntrinsics) {
283 if (!FLAG_IS_DEFAULT(UseAESIntrinsics))
284 warning("AES intrinsics are not available on this CPU");
285 FLAG_SET_DEFAULT(UseAESIntrinsics, false);
286 }
287
288 if (UseAESCTRIntrinsics) {
289 warning("AES/CTR intrinsics are not available on this CPU");
290 FLAG_SET_DEFAULT(UseAESCTRIntrinsics, false);
291 }
292
293 if (UseGHASHIntrinsics) {
294 warning("GHASH intrinsics are not available on this CPU");
295 FLAG_SET_DEFAULT(UseGHASHIntrinsics, false);
296 }
297
298 if (FLAG_IS_DEFAULT(UseFMA)) {
299 FLAG_SET_DEFAULT(UseFMA, true);
300 }
301
302 if (UseMD5Intrinsics) {
303 warning("MD5 intrinsics are not available on this CPU");
304 FLAG_SET_DEFAULT(UseMD5Intrinsics, false);
305 }
306
307 if (has_vshasig()) {
308 if (FLAG_IS_DEFAULT(UseSHA)) {
309 UseSHA = true;
310 }
311 } else if (UseSHA) {
312 if (!FLAG_IS_DEFAULT(UseSHA))
313 warning("SHA instructions are not available on this CPU");
314 FLAG_SET_DEFAULT(UseSHA, false);
315 }
316
317 if (UseSHA1Intrinsics) {
318 warning("Intrinsics for SHA-1 crypto hash functions not available on this CPU.");
319 FLAG_SET_DEFAULT(UseSHA1Intrinsics, false);
320 }
321
322 if (UseSHA && has_vshasig()) {
323 if (FLAG_IS_DEFAULT(UseSHA256Intrinsics)) {
324 FLAG_SET_DEFAULT(UseSHA256Intrinsics, true);
325 }
326 } else if (UseSHA256Intrinsics) {
327 warning("Intrinsics for SHA-224 and SHA-256 crypto hash functions not available on this CPU.");
328 FLAG_SET_DEFAULT(UseSHA256Intrinsics, false);
329 }
330
331 if (UseSHA && has_vshasig()) {
332 if (FLAG_IS_DEFAULT(UseSHA512Intrinsics)) {
333 FLAG_SET_DEFAULT(UseSHA512Intrinsics, true);
334 }
335 } else if (UseSHA512Intrinsics) {
336 warning("Intrinsics for SHA-384 and SHA-512 crypto hash functions not available on this CPU.");
337 FLAG_SET_DEFAULT(UseSHA512Intrinsics, false);
338 }
339
340 if (!(UseSHA1Intrinsics || UseSHA256Intrinsics || UseSHA512Intrinsics)) {
341 FLAG_SET_DEFAULT(UseSHA, false);
342 }
343
344 #ifdef COMPILER2
345 if (FLAG_IS_DEFAULT(UseSquareToLenIntrinsic)) {
346 UseSquareToLenIntrinsic = true;
347 }
348 if (FLAG_IS_DEFAULT(UseMulAddIntrinsic)) {
349 UseMulAddIntrinsic = true;
350 }
351 if (FLAG_IS_DEFAULT(UseMultiplyToLenIntrinsic)) {
352 UseMultiplyToLenIntrinsic = true;
353 }
354 if (FLAG_IS_DEFAULT(UseMontgomeryMultiplyIntrinsic)) {
355 UseMontgomeryMultiplyIntrinsic = true;
356 }
357 if (FLAG_IS_DEFAULT(UseMontgomerySquareIntrinsic)) {
358 UseMontgomerySquareIntrinsic = true;
359 }
360 #endif
361
362 if (UseVectorizedMismatchIntrinsic) {
363 warning("UseVectorizedMismatchIntrinsic specified, but not available on this CPU.");
364 FLAG_SET_DEFAULT(UseVectorizedMismatchIntrinsic, false);
365 }
366
367
368 // Adjust RTM (Restricted Transactional Memory) flags.
369 if (UseRTMLocking) {
370 // If CPU or OS do not support TM:
371 // Can't continue because UseRTMLocking affects UseBiasedLocking flag
372 // setting during arguments processing. See use_biased_locking().
373 // VM_Version_init() is executed after UseBiasedLocking is used
374 // in Thread::allocate().
375 if (PowerArchitecturePPC64 < 8) {
376 vm_exit_during_initialization("RTM instructions are not available on this CPU.");
377 }
378
379 if (!has_tm()) {
380 vm_exit_during_initialization("RTM is not supported on this OS version.");
381 }
382 }
383
384 if (UseRTMLocking) {
385 #if INCLUDE_RTM_OPT
386 if (!FLAG_IS_CMDLINE(UseRTMLocking)) {
387 // RTM locking should be used only for applications with
388 // high lock contention. For now we do not use it by default.
389 vm_exit_during_initialization("UseRTMLocking flag should be only set on command line");
390 }
391 #else
392 // Only C2 does RTM locking optimization.
393 // Can't continue because UseRTMLocking affects UseBiasedLocking flag
394 // setting during arguments processing. See use_biased_locking().
395 vm_exit_during_initialization("RTM locking optimization is not supported in this VM");
396 #endif
397 } else { // !UseRTMLocking
398 if (UseRTMForStackLocks) {
399 if (!FLAG_IS_DEFAULT(UseRTMForStackLocks)) {
400 warning("UseRTMForStackLocks flag should be off when UseRTMLocking flag is off");
401 }
402 FLAG_SET_DEFAULT(UseRTMForStackLocks, false);
403 }
404 if (UseRTMDeopt) {
405 FLAG_SET_DEFAULT(UseRTMDeopt, false);
406 }
407 #ifdef COMPILER2
408 if (PrintPreciseRTMLockingStatistics) {
409 FLAG_SET_DEFAULT(PrintPreciseRTMLockingStatistics, false);
410 }
411 #endif
412 }
413
414 // This machine allows unaligned memory accesses
415 if (FLAG_IS_DEFAULT(UseUnalignedAccesses)) {
416 FLAG_SET_DEFAULT(UseUnalignedAccesses, true);
417 }
418
419 check_virtualizations();
420 }
421
422 void VM_Version::check_virtualizations() {
423 #if defined(_AIX)
424 int rc = 0;
425 perfstat_partition_total_t pinfo;
426 rc = perfstat_partition_total(NULL, &pinfo, sizeof(perfstat_partition_total_t), 1);
427 if (rc == 1) {
428 Abstract_VM_Version::_detected_virtualization = PowerVM;
429 }
430 #else
431 const char* info_file = "/proc/ppc64/lparcfg";
432 // system_type=...qemu indicates PowerKVM
433 // e.g. system_type=IBM pSeries (emulated by qemu)
434 char line[500];
435 FILE* fp = fopen(info_file, "r");
436 if (fp == NULL) {
437 return;
438 }
439 const char* system_type="system_type="; // in case this line contains qemu, it is KVM
440 const char* num_lpars="NumLpars="; // in case of non-KVM : if this line is found it is PowerVM
441 bool num_lpars_found = false;
442
443 while (fgets(line, sizeof(line), fp) != NULL) {
444 if (strncmp(line, system_type, strlen(system_type)) == 0) {
445 if (strstr(line, "qemu") != 0) {
446 Abstract_VM_Version::_detected_virtualization = PowerKVM;
447 fclose(fp);
448 return;
449 }
450 }
451 if (strncmp(line, num_lpars, strlen(num_lpars)) == 0) {
452 num_lpars_found = true;
453 }
454 }
455 if (num_lpars_found) {
456 Abstract_VM_Version::_detected_virtualization = PowerVM;
457 } else {
458 Abstract_VM_Version::_detected_virtualization = PowerFullPartitionMode;
459 }
460 fclose(fp);
461 #endif
462 }
463
464 void VM_Version::print_platform_virtualization_info(outputStream* st) {
465 #if defined(_AIX)
466 // more info about perfstat API see
467 // https://www.ibm.com/support/knowledgecenter/en/ssw_aix_72/com.ibm.aix.prftools/idprftools_perfstat_glob_partition.htm
468 int rc = 0;
469 perfstat_partition_total_t pinfo;
470 memset(&pinfo, 0, sizeof(perfstat_partition_total_t));
471 rc = perfstat_partition_total(NULL, &pinfo, sizeof(perfstat_partition_total_t), 1);
472 if (rc != 1) {
473 return;
474 } else {
475 st->print_cr("Virtualization type : PowerVM");
476 }
477 // CPU information
478 perfstat_cpu_total_t cpuinfo;
479 memset(&cpuinfo, 0, sizeof(perfstat_cpu_total_t));
480 rc = perfstat_cpu_total(NULL, &cpuinfo, sizeof(perfstat_cpu_total_t), 1);
481 if (rc != 1) {
482 return;
483 }
484
485 st->print_cr("Processor description : %s", cpuinfo.description);
486 st->print_cr("Processor speed : %llu Hz", cpuinfo.processorHZ);
487
488 st->print_cr("LPAR partition name : %s", pinfo.name);
489 st->print_cr("LPAR partition number : %u", pinfo.lpar_id);
490 st->print_cr("LPAR partition type : %s", pinfo.type.b.shared_enabled ? "shared" : "dedicated");
491 st->print_cr("LPAR mode : %s", pinfo.type.b.donate_enabled ? "donating" : pinfo.type.b.capped ? "capped" : "uncapped");
492 st->print_cr("LPAR partition group ID : %u", pinfo.group_id);
493 st->print_cr("LPAR shared pool ID : %u", pinfo.pool_id);
494
495 st->print_cr("AMS (active memory sharing) : %s", pinfo.type.b.ams_capable ? "capable" : "not capable");
496 st->print_cr("AMS (active memory sharing) : %s", pinfo.type.b.ams_enabled ? "on" : "off");
497 st->print_cr("AME (active memory expansion) : %s", pinfo.type.b.ame_enabled ? "on" : "off");
498
499 if (pinfo.type.b.ame_enabled) {
500 st->print_cr("AME true memory in bytes : %llu", pinfo.true_memory);
501 st->print_cr("AME expanded memory in bytes : %llu", pinfo.expanded_memory);
502 }
503
504 st->print_cr("SMT : %s", pinfo.type.b.smt_capable ? "capable" : "not capable");
505 st->print_cr("SMT : %s", pinfo.type.b.smt_enabled ? "on" : "off");
506 int ocpus = pinfo.online_cpus > 0 ? pinfo.online_cpus : 1;
507 st->print_cr("LPAR threads : %d", cpuinfo.ncpus/ocpus);
508 st->print_cr("LPAR online virtual cpus : %d", pinfo.online_cpus);
509 st->print_cr("LPAR logical cpus : %d", cpuinfo.ncpus);
510 st->print_cr("LPAR maximum virtual cpus : %u", pinfo.max_cpus);
511 st->print_cr("LPAR minimum virtual cpus : %u", pinfo.min_cpus);
512 st->print_cr("LPAR entitled capacity : %4.2f", (double) (pinfo.entitled_proc_capacity/100.0));
513 st->print_cr("LPAR online memory : %llu MB", pinfo.online_memory);
514 st->print_cr("LPAR maximum memory : %llu MB", pinfo.max_memory);
515 st->print_cr("LPAR minimum memory : %llu MB", pinfo.min_memory);
516 #else
517 const char* info_file = "/proc/ppc64/lparcfg";
518 const char* kw[] = { "system_type=", // qemu indicates PowerKVM
519 "partition_entitled_capacity=", // entitled processor capacity percentage
520 "partition_max_entitled_capacity=",
521 "capacity_weight=", // partition CPU weight
522 "partition_active_processors=",
523 "partition_potential_processors=",
524 "entitled_proc_capacity_available=",
525 "capped=", // 0 - uncapped, 1 - vcpus capped at entitled processor capacity percentage
526 "shared_processor_mode=", // (non)dedicated partition
527 "system_potential_processors=",
528 "pool=", // CPU-pool number
529 "pool_capacity=",
530 "NumLpars=", // on non-KVM machines, NumLpars is not found for full partition mode machines
531 NULL };
532 if (!print_matching_lines_from_file(info_file, st, kw)) {
533 st->print_cr(" <%s Not Available>", info_file);
534 }
535 #endif
536 }
537
538 bool VM_Version::use_biased_locking() {
539 #if INCLUDE_RTM_OPT
540 // RTM locking is most useful when there is high lock contention and
541 // low data contention. With high lock contention the lock is usually
542 // inflated and biased locking is not suitable for that case.
543 // RTM locking code requires that biased locking is off.
544 // Note: we can't switch off UseBiasedLocking in get_processor_features()
545 // because it is used by Thread::allocate() which is called before
546 // VM_Version::initialize().
547 if (UseRTMLocking && UseBiasedLocking) {
548 if (FLAG_IS_DEFAULT(UseBiasedLocking)) {
549 FLAG_SET_DEFAULT(UseBiasedLocking, false);
550 } else {
551 warning("Biased locking is not supported with RTM locking; ignoring UseBiasedLocking flag." );
552 UseBiasedLocking = false;
553 }
554 }
555 #endif
556 return UseBiasedLocking;
557 }
558
559 void VM_Version::print_features() {
560 tty->print_cr("Version: %s L1_data_cache_line_size=%d", features_string(), L1_data_cache_line_size());
561
562 if (Verbose) {
563 if (ContendedPaddingWidth > 0) {
564 tty->cr();
565 tty->print_cr("ContendedPaddingWidth " INTX_FORMAT, ContendedPaddingWidth);
566 }
567 }
568 }
569
570 #ifdef COMPILER2
571 // Determine section size on power6: If section size is 8 instructions,
572 // there should be a difference between the two testloops of ~15 %. If
573 // no difference is detected the section is assumed to be 32 instructions.
574 void VM_Version::determine_section_size() {
575
576 int unroll = 80;
577
578 const int code_size = (2* unroll * 32 + 100)*BytesPerInstWord;
579
580 // Allocate space for the code.
581 ResourceMark rm;
582 CodeBuffer cb("detect_section_size", code_size, 0);
583 MacroAssembler* a = new MacroAssembler(&cb);
584
585 uint32_t *code = (uint32_t *)a->pc();
586 // Emit code.
587 void (*test1)() = (void(*)())(void *)a->function_entry();
588
589 Label l1;
590
591 a->li(R4, 1);
592 a->sldi(R4, R4, 28);
593 a->b(l1);
594 a->align(CodeEntryAlignment);
595
596 a->bind(l1);
597
598 for (int i = 0; i < unroll; i++) {
599 // Schleife 1
600 // ------- sector 0 ------------
601 // ;; 0
602 a->nop(); // 1
603 a->fpnop0(); // 2
604 a->fpnop1(); // 3
605 a->addi(R4,R4, -1); // 4
606
607 // ;; 1
608 a->nop(); // 5
609 a->fmr(F6, F6); // 6
610 a->fmr(F7, F7); // 7
611 a->endgroup(); // 8
612 // ------- sector 8 ------------
613
614 // ;; 2
615 a->nop(); // 9
616 a->nop(); // 10
617 a->fmr(F8, F8); // 11
618 a->fmr(F9, F9); // 12
619
620 // ;; 3
621 a->nop(); // 13
622 a->fmr(F10, F10); // 14
623 a->fmr(F11, F11); // 15
624 a->endgroup(); // 16
625 // -------- sector 16 -------------
626
627 // ;; 4
628 a->nop(); // 17
629 a->nop(); // 18
630 a->fmr(F15, F15); // 19
631 a->fmr(F16, F16); // 20
632
633 // ;; 5
634 a->nop(); // 21
635 a->fmr(F17, F17); // 22
636 a->fmr(F18, F18); // 23
637 a->endgroup(); // 24
638 // ------- sector 24 ------------
639
640 // ;; 6
641 a->nop(); // 25
642 a->nop(); // 26
643 a->fmr(F19, F19); // 27
644 a->fmr(F20, F20); // 28
645
646 // ;; 7
647 a->nop(); // 29
648 a->fmr(F21, F21); // 30
649 a->fmr(F22, F22); // 31
650 a->brnop0(); // 32
651
652 // ------- sector 32 ------------
653 }
654
655 // ;; 8
656 a->cmpdi(CCR0, R4, unroll); // 33
657 a->bge(CCR0, l1); // 34
658 a->blr();
659
660 // Emit code.
661 void (*test2)() = (void(*)())(void *)a->function_entry();
662 // uint32_t *code = (uint32_t *)a->pc();
663
664 Label l2;
665
666 a->li(R4, 1);
667 a->sldi(R4, R4, 28);
668 a->b(l2);
669 a->align(CodeEntryAlignment);
670
671 a->bind(l2);
672
673 for (int i = 0; i < unroll; i++) {
674 // Schleife 2
675 // ------- sector 0 ------------
676 // ;; 0
677 a->brnop0(); // 1
678 a->nop(); // 2
679 //a->cmpdi(CCR0, R4, unroll);
680 a->fpnop0(); // 3
681 a->fpnop1(); // 4
682 a->addi(R4,R4, -1); // 5
683
684 // ;; 1
685
686 a->nop(); // 6
687 a->fmr(F6, F6); // 7
688 a->fmr(F7, F7); // 8
689 // ------- sector 8 ---------------
690
691 // ;; 2
692 a->endgroup(); // 9
693
694 // ;; 3
695 a->nop(); // 10
696 a->nop(); // 11
697 a->fmr(F8, F8); // 12
698
699 // ;; 4
700 a->fmr(F9, F9); // 13
701 a->nop(); // 14
702 a->fmr(F10, F10); // 15
703
704 // ;; 5
705 a->fmr(F11, F11); // 16
706 // -------- sector 16 -------------
707
708 // ;; 6
709 a->endgroup(); // 17
710
711 // ;; 7
712 a->nop(); // 18
713 a->nop(); // 19
714 a->fmr(F15, F15); // 20
715
716 // ;; 8
717 a->fmr(F16, F16); // 21
718 a->nop(); // 22
719 a->fmr(F17, F17); // 23
720
721 // ;; 9
722 a->fmr(F18, F18); // 24
723 // -------- sector 24 -------------
724
725 // ;; 10
726 a->endgroup(); // 25
727
728 // ;; 11
729 a->nop(); // 26
730 a->nop(); // 27
731 a->fmr(F19, F19); // 28
732
733 // ;; 12
734 a->fmr(F20, F20); // 29
735 a->nop(); // 30
736 a->fmr(F21, F21); // 31
737
738 // ;; 13
739 a->fmr(F22, F22); // 32
740 }
741
742 // -------- sector 32 -------------
743 // ;; 14
744 a->cmpdi(CCR0, R4, unroll); // 33
745 a->bge(CCR0, l2); // 34
746
747 a->blr();
748 uint32_t *code_end = (uint32_t *)a->pc();
749 a->flush();
750
751 cb.insts()->set_end((u_char*)code_end);
752
753 double loop1_seconds,loop2_seconds, rel_diff;
754 uint64_t start1, stop1;
755
756 start1 = os::current_thread_cpu_time(false);
757 (*test1)();
758 stop1 = os::current_thread_cpu_time(false);
759 loop1_seconds = (stop1- start1) / (1000 *1000 *1000.0);
760
761
762 start1 = os::current_thread_cpu_time(false);
763 (*test2)();
764 stop1 = os::current_thread_cpu_time(false);
765
766 loop2_seconds = (stop1 - start1) / (1000 *1000 *1000.0);
767
768 rel_diff = (loop2_seconds - loop1_seconds) / loop1_seconds *100;
769
770 if (PrintAssembly || PrintStubCode) {
771 ttyLocker ttyl;
772 tty->print_cr("Decoding section size detection stub at " INTPTR_FORMAT " before execution:", p2i(code));
773 // Use existing decode function. This enables the [MachCode] format which is needed to DecodeErrorFile.
774 Disassembler::decode(&cb, (u_char*)code, (u_char*)code_end, tty);
775 tty->print_cr("Time loop1 :%f", loop1_seconds);
776 tty->print_cr("Time loop2 :%f", loop2_seconds);
777 tty->print_cr("(time2 - time1) / time1 = %f %%", rel_diff);
778
779 if (rel_diff > 12.0) {
780 tty->print_cr("Section Size 8 Instructions");
781 } else{
782 tty->print_cr("Section Size 32 Instructions or Power5");
783 }
784 }
785
786 #if 0 // TODO: PPC port
787 // Set sector size (if not set explicitly).
788 if (FLAG_IS_DEFAULT(Power6SectorSize128PPC64)) {
789 if (rel_diff > 12.0) {
790 PdScheduling::power6SectorSize = 0x20;
791 } else {
792 PdScheduling::power6SectorSize = 0x80;
793 }
794 } else if (Power6SectorSize128PPC64) {
795 PdScheduling::power6SectorSize = 0x80;
796 } else {
797 PdScheduling::power6SectorSize = 0x20;
798 }
799 #endif
800 if (UsePower6SchedulerPPC64) Unimplemented();
801 }
802 #endif // COMPILER2
803
804 void VM_Version::determine_features() {
805 #if defined(ABI_ELFv2)
806 // 1 InstWord per call for the blr instruction.
807 const int code_size = (num_features+1+2*1)*BytesPerInstWord;
808 #else
809 // 7 InstWords for each call (function descriptor + blr instruction).
810 const int code_size = (num_features+1+2*7)*BytesPerInstWord;
811 #endif
812 int features = 0;
813
814 // create test area
815 enum { BUFFER_SIZE = 2*4*K }; // Needs to be >=2* max cache line size (cache line size can't exceed min page size).
816 char test_area[BUFFER_SIZE];
817 char *mid_of_test_area = &test_area[BUFFER_SIZE>>1];
818
819 // Allocate space for the code.
820 ResourceMark rm;
821 CodeBuffer cb("detect_cpu_features", code_size, 0);
822 MacroAssembler* a = new MacroAssembler(&cb);
823
824 // Must be set to true so we can generate the test code.
825 _features = VM_Version::all_features_m;
826
827 // Emit code.
828 void (*test)(address addr, uint64_t offset)=(void(*)(address addr, uint64_t offset))(void *)a->function_entry();
829 uint32_t *code = (uint32_t *)a->pc();
830 // Don't use R0 in ldarx.
831 // Keep R3_ARG1 unmodified, it contains &field (see below).
832 // Keep R4_ARG2 unmodified, it contains offset = 0 (see below).
833 a->fsqrt(F3, F4); // code[0] -> fsqrt_m
834 a->fsqrts(F3, F4); // code[1] -> fsqrts_m
835 a->isel(R7, R5, R6, 0); // code[2] -> isel_m
836 a->ldarx_unchecked(R7, R3_ARG1, R4_ARG2, 1); // code[3] -> lxarx_m
837 a->cmpb(R7, R5, R6); // code[4] -> cmpb
838 a->popcntb(R7, R5); // code[5] -> popcntb
839 a->popcntw(R7, R5); // code[6] -> popcntw
840 a->fcfids(F3, F4); // code[7] -> fcfids
841 a->vand(VR0, VR0, VR0); // code[8] -> vand
842 // arg0 of lqarx must be an even register, (arg1 + arg2) must be a multiple of 16
843 a->lqarx_unchecked(R6, R3_ARG1, R4_ARG2, 1); // code[9] -> lqarx_m
844 a->vcipher(VR0, VR1, VR2); // code[10] -> vcipher
845 a->vpmsumb(VR0, VR1, VR2); // code[11] -> vpmsumb
846 a->mfdscr(R0); // code[12] -> mfdscr
847 a->lxvd2x(VSR0, R3_ARG1); // code[13] -> vsx
848 a->ldbrx(R7, R3_ARG1, R4_ARG2); // code[14] -> ldbrx
849 a->stdbrx(R7, R3_ARG1, R4_ARG2); // code[15] -> stdbrx
850 a->vshasigmaw(VR0, VR1, 1, 0xF); // code[16] -> vshasig
851 // rtm is determined by OS
852 a->darn(R7); // code[17] -> darn
853 a->brw(R5, R6); // code[18] -> brw
854 a->blr();
855
856 // Emit function to set one cache line to zero. Emit function descriptor and get pointer to it.
857 void (*zero_cacheline_func_ptr)(char*) = (void(*)(char*))(void *)a->function_entry();
858 a->dcbz(R3_ARG1); // R3_ARG1 = addr
859 a->blr();
860
861 uint32_t *code_end = (uint32_t *)a->pc();
862 a->flush();
863 _features = VM_Version::unknown_m;
864
865 // Print the detection code.
866 if (PrintAssembly) {
867 ttyLocker ttyl;
868 tty->print_cr("Decoding cpu-feature detection stub at " INTPTR_FORMAT " before execution:", p2i(code));
869 Disassembler::decode((u_char*)code, (u_char*)code_end, tty);
870 }
871
872 // Measure cache line size.
873 memset(test_area, 0xFF, BUFFER_SIZE); // Fill test area with 0xFF.
874 (*zero_cacheline_func_ptr)(mid_of_test_area); // Call function which executes dcbz to the middle.
875 int count = 0; // count zeroed bytes
876 for (int i = 0; i < BUFFER_SIZE; i++) if (test_area[i] == 0) count++;
877 guarantee(is_power_of_2(count), "cache line size needs to be a power of 2");
878 _L1_data_cache_line_size = count;
879
880 // Execute code. Illegal instructions will be replaced by 0 in the signal handler.
881 VM_Version::_is_determine_features_test_running = true;
882 // We must align the first argument to 16 bytes because of the lqarx check.
883 (*test)(align_up((address)mid_of_test_area, 16), 0);
884 VM_Version::_is_determine_features_test_running = false;
885
886 // determine which instructions are legal.
887 int feature_cntr = 0;
888 if (code[feature_cntr++]) features |= fsqrt_m;
889 if (code[feature_cntr++]) features |= fsqrts_m;
890 if (code[feature_cntr++]) features |= isel_m;
891 if (code[feature_cntr++]) features |= lxarxeh_m;
892 if (code[feature_cntr++]) features |= cmpb_m;
893 if (code[feature_cntr++]) features |= popcntb_m;
894 if (code[feature_cntr++]) features |= popcntw_m;
895 if (code[feature_cntr++]) features |= fcfids_m;
896 if (code[feature_cntr++]) features |= vand_m;
897 if (code[feature_cntr++]) features |= lqarx_m;
898 if (code[feature_cntr++]) features |= vcipher_m;
899 if (code[feature_cntr++]) features |= vpmsumb_m;
900 if (code[feature_cntr++]) features |= mfdscr_m;
901 if (code[feature_cntr++]) features |= vsx_m;
902 if (code[feature_cntr++]) features |= ldbrx_m;
903 if (code[feature_cntr++]) features |= stdbrx_m;
904 if (code[feature_cntr++]) features |= vshasig_m;
905 // feature rtm_m is determined by OS
906 if (code[feature_cntr++]) features |= darn_m;
907 if (code[feature_cntr++]) features |= brw_m;
908
909 // Print the detection code.
910 if (PrintAssembly) {
911 ttyLocker ttyl;
912 tty->print_cr("Decoding cpu-feature detection stub at " INTPTR_FORMAT " after execution:", p2i(code));
913 Disassembler::decode((u_char*)code, (u_char*)code_end, tty);
914 }
915
916 _features = features;
917
918 #ifdef AIX
919 // To enable it on AIX it's necessary POWER8 or above and at least AIX 7.2.
920 // Actually, this is supported since AIX 7.1.. Unfortunately, this first
921 // contained bugs, so that it can only be enabled after AIX 7.1.3.30.
922 // The Java property os.version, which is used in RTM tests to decide
923 // whether the feature is available, only knows major and minor versions.
924 // We don't want to change this property, as user code might depend on it.
925 // So the tests can not check on subversion 3.30, and we only enable RTM
926 // with AIX 7.2.
927 if (has_lqarx()) { // POWER8 or above
928 if (os::Aix::os_version() >= 0x07020000) { // At least AIX 7.2.
929 _features |= rtm_m;
930 }
931 }
932 #endif
933 #if defined(LINUX) && defined(VM_LITTLE_ENDIAN)
934 unsigned long auxv = getauxval(AT_HWCAP2);
935
936 if (auxv & PPC_FEATURE2_HTM_NOSC) {
937 if (auxv & PPC_FEATURE2_HAS_HTM) {
938 // TM on POWER8 and POWER9 in compat mode (VM) is supported by the JVM.
939 // TM on POWER9 DD2.1 NV (baremetal) is not supported by the JVM (TM on
940 // POWER9 DD2.1 NV has a few issues that need a couple of firmware
941 // and kernel workarounds, so there is a new mode only supported
942 // on non-virtualized P9 machines called HTM with no Suspend Mode).
943 // TM on POWER9 D2.2+ NV is not supported at all by Linux.
944 _features |= rtm_m;
945 }
946 }
947 #endif
948 }
949
950 // Power 8: Configure Data Stream Control Register.
951 void VM_Version::config_dscr() {
952 // 7 InstWords for each call (function descriptor + blr instruction).
953 const int code_size = (2+2*7)*BytesPerInstWord;
954
955 // Allocate space for the code.
956 ResourceMark rm;
957 CodeBuffer cb("config_dscr", code_size, 0);
958 MacroAssembler* a = new MacroAssembler(&cb);
959
960 // Emit code.
961 uint64_t (*get_dscr)() = (uint64_t(*)())(void *)a->function_entry();
962 uint32_t *code = (uint32_t *)a->pc();
963 a->mfdscr(R3);
964 a->blr();
965
966 void (*set_dscr)(long) = (void(*)(long))(void *)a->function_entry();
967 a->mtdscr(R3);
968 a->blr();
969
970 uint32_t *code_end = (uint32_t *)a->pc();
971 a->flush();
972
973 // Print the detection code.
974 if (PrintAssembly) {
975 ttyLocker ttyl;
976 tty->print_cr("Decoding dscr configuration stub at " INTPTR_FORMAT " before execution:", p2i(code));
977 Disassembler::decode((u_char*)code, (u_char*)code_end, tty);
978 }
979
980 // Apply the configuration if needed.
981 _dscr_val = (*get_dscr)();
982 if (Verbose) {
983 tty->print_cr("dscr value was 0x%lx" , _dscr_val);
984 }
985 bool change_requested = false;
986 if (DSCR_PPC64 != (uintx)-1) {
987 _dscr_val = DSCR_PPC64;
988 change_requested = true;
989 }
990 if (DSCR_DPFD_PPC64 <= 7) {
991 uint64_t mask = 0x7;
992 if ((_dscr_val & mask) != DSCR_DPFD_PPC64) {
993 _dscr_val = (_dscr_val & ~mask) | (DSCR_DPFD_PPC64);
994 change_requested = true;
995 }
996 }
997 if (DSCR_URG_PPC64 <= 7) {
998 uint64_t mask = 0x7 << 6;
999 if ((_dscr_val & mask) != DSCR_DPFD_PPC64 << 6) {
1000 _dscr_val = (_dscr_val & ~mask) | (DSCR_URG_PPC64 << 6);
1001 change_requested = true;
1002 }
1003 }
1004 if (change_requested) {
1005 (*set_dscr)(_dscr_val);
1006 if (Verbose) {
1007 tty->print_cr("dscr was set to 0x%lx" , (*get_dscr)());
1008 }
1009 }
1010 }
1011
1012 static uint64_t saved_features = 0;
1013
1014 void VM_Version::allow_all() {
1015 saved_features = _features;
1016 _features = all_features_m;
1017 }
1018
1019 void VM_Version::revert() {
1020 _features = saved_features;
1021 }