1 /*
2 * Copyright (c) 1997, 2020, Oracle and/or its affiliates. All rights reserved.
3 * Copyright (c) 2015, 2020, Red Hat Inc. All rights reserved.
4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
5 *
6 * This code is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 only, as
8 * published by the Free Software Foundation.
9 *
10 * This code is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * version 2 for more details (a copy is included in the LICENSE file that
14 * accompanied this code).
15 *
16 * You should have received a copy of the GNU General Public License version
17 * 2 along with this work; if not, write to the Free Software Foundation,
18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 * or visit www.oracle.com if you need additional information or have any
22 * questions.
23 *
24 */
25
26 #include "precompiled.hpp"
27 #include "asm/macroAssembler.hpp"
28 #include "asm/macroAssembler.inline.hpp"
29 #include "memory/resourceArea.hpp"
30 #include "runtime/arguments.hpp"
31 #include "runtime/java.hpp"
32 #include "runtime/os.hpp"
33 #include "runtime/stubCodeGenerator.hpp"
34 #include "runtime/vm_version.hpp"
35 #include "utilities/macros.hpp"
36
37 #include OS_HEADER_INLINE(os)
38
39 #include <sys/auxv.h>
40 #include <asm/hwcap.h>
41
42 #ifndef HWCAP_AES
43 #define HWCAP_AES (1<<3)
44 #endif
45
46 #ifndef HWCAP_PMULL
47 #define HWCAP_PMULL (1<<4)
48 #endif
49
50 #ifndef HWCAP_SHA1
51 #define HWCAP_SHA1 (1<<5)
52 #endif
53
54 #ifndef HWCAP_SHA2
55 #define HWCAP_SHA2 (1<<6)
56 #endif
57
58 #ifndef HWCAP_CRC32
59 #define HWCAP_CRC32 (1<<7)
60 #endif
61
62 #ifndef HWCAP_ATOMICS
63 #define HWCAP_ATOMICS (1<<8)
64 #endif
65
66 #ifndef HWCAP_SHA512
67 #define HWCAP_SHA512 (1 << 21)
68 #endif
69
70 #ifndef HWCAP_SHA3
71 #define HWCAP_SHA3 (1 << 17)
72 #endif
73
74 int VM_Version::_cpu;
75 int VM_Version::_model;
76 int VM_Version::_model2;
77 int VM_Version::_variant;
78 int VM_Version::_revision;
79 int VM_Version::_stepping;
80 bool VM_Version::_dcpop;
81 VM_Version::PsrInfo VM_Version::_psr_info = { 0, };
82
83 static BufferBlob* stub_blob;
84 static const int stub_size = 550;
85
86 extern "C" {
87 typedef void (*getPsrInfo_stub_t)(void*);
88 }
89 static getPsrInfo_stub_t getPsrInfo_stub = NULL;
90
91
92 class VM_Version_StubGenerator: public StubCodeGenerator {
93 public:
94
95 VM_Version_StubGenerator(CodeBuffer *c) : StubCodeGenerator(c) {}
96
97 address generate_getPsrInfo() {
98 StubCodeMark mark(this, "VM_Version", "getPsrInfo_stub");
99 # define __ _masm->
100 address start = __ pc();
101
102 // void getPsrInfo(VM_Version::PsrInfo* psr_info);
103
104 address entry = __ pc();
105
106 __ enter();
107
108 __ get_dczid_el0(rscratch1);
109 __ strw(rscratch1, Address(c_rarg0, in_bytes(VM_Version::dczid_el0_offset())));
110
111 __ get_ctr_el0(rscratch1);
112 __ strw(rscratch1, Address(c_rarg0, in_bytes(VM_Version::ctr_el0_offset())));
113
114 __ leave();
115 __ ret(lr);
116
117 # undef __
118
119 return start;
120 }
121 };
122
123
124 void VM_Version::get_processor_features() {
125 _supports_cx8 = true;
126 _supports_atomic_getset4 = true;
127 _supports_atomic_getadd4 = true;
128 _supports_atomic_getset8 = true;
129 _supports_atomic_getadd8 = true;
130
131 getPsrInfo_stub(&_psr_info);
132
133 int dcache_line = VM_Version::dcache_line_size();
134
135 // Limit AllocatePrefetchDistance so that it does not exceed the
136 // constraint in AllocatePrefetchDistanceConstraintFunc.
137 if (FLAG_IS_DEFAULT(AllocatePrefetchDistance))
138 FLAG_SET_DEFAULT(AllocatePrefetchDistance, MIN2(512, 3*dcache_line));
139
140 if (FLAG_IS_DEFAULT(AllocatePrefetchStepSize))
141 FLAG_SET_DEFAULT(AllocatePrefetchStepSize, dcache_line);
142 if (FLAG_IS_DEFAULT(PrefetchScanIntervalInBytes))
143 FLAG_SET_DEFAULT(PrefetchScanIntervalInBytes, 3*dcache_line);
144 if (FLAG_IS_DEFAULT(PrefetchCopyIntervalInBytes))
145 FLAG_SET_DEFAULT(PrefetchCopyIntervalInBytes, 3*dcache_line);
146 if (FLAG_IS_DEFAULT(SoftwarePrefetchHintDistance))
147 FLAG_SET_DEFAULT(SoftwarePrefetchHintDistance, 3*dcache_line);
148
149 if (PrefetchCopyIntervalInBytes != -1 &&
150 ((PrefetchCopyIntervalInBytes & 7) || (PrefetchCopyIntervalInBytes >= 32768))) {
151 warning("PrefetchCopyIntervalInBytes must be -1, or a multiple of 8 and < 32768");
152 PrefetchCopyIntervalInBytes &= ~7;
153 if (PrefetchCopyIntervalInBytes >= 32768)
154 PrefetchCopyIntervalInBytes = 32760;
155 }
156
157 if (AllocatePrefetchDistance !=-1 && (AllocatePrefetchDistance & 7)) {
158 warning("AllocatePrefetchDistance must be multiple of 8");
159 AllocatePrefetchDistance &= ~7;
160 }
161
162 if (AllocatePrefetchStepSize & 7) {
163 warning("AllocatePrefetchStepSize must be multiple of 8");
164 AllocatePrefetchStepSize &= ~7;
165 }
166
167 if (SoftwarePrefetchHintDistance != -1 &&
168 (SoftwarePrefetchHintDistance & 7)) {
169 warning("SoftwarePrefetchHintDistance must be -1, or a multiple of 8");
170 SoftwarePrefetchHintDistance &= ~7;
171 }
172
173 uint64_t auxv = getauxval(AT_HWCAP);
174
175 char buf[512];
176
177 _features = auxv;
178
179 int cpu_lines = 0;
180 if (FILE *f = fopen("/proc/cpuinfo", "r")) {
181 // need a large buffer as the flags line may include lots of text
182 char buf[1024], *p;
183 while (fgets(buf, sizeof (buf), f) != NULL) {
184 if ((p = strchr(buf, ':')) != NULL) {
185 long v = strtol(p+1, NULL, 0);
186 if (strncmp(buf, "CPU implementer", sizeof "CPU implementer" - 1) == 0) {
187 _cpu = v;
188 cpu_lines++;
189 } else if (strncmp(buf, "CPU variant", sizeof "CPU variant" - 1) == 0) {
190 _variant = v;
191 } else if (strncmp(buf, "CPU part", sizeof "CPU part" - 1) == 0) {
192 if (_model != v) _model2 = _model;
193 _model = v;
194 } else if (strncmp(buf, "CPU revision", sizeof "CPU revision" - 1) == 0) {
195 _revision = v;
196 } else if (strncmp(buf, "flags", sizeof("flags") - 1) == 0) {
197 if (strstr(p+1, "dcpop")) {
198 _dcpop = true;
199 }
200 }
201 }
202 }
203 fclose(f);
204 }
205
206 if (os::supports_map_sync()) {
207 // if dcpop is available publish data cache line flush size via
208 // generic field, otherwise let if default to zero thereby
209 // disabling writeback
210 if (_dcpop) {
211 _data_cache_line_flush_size = dcache_line;
212 }
213 }
214
215 // Enable vendor specific features
216
217 // Ampere eMAG
218 if (_cpu == CPU_AMCC && (_model == 0) && (_variant == 0x3)) {
219 if (FLAG_IS_DEFAULT(AvoidUnalignedAccesses)) {
220 FLAG_SET_DEFAULT(AvoidUnalignedAccesses, true);
221 }
222 if (FLAG_IS_DEFAULT(UseSIMDForMemoryOps)) {
223 FLAG_SET_DEFAULT(UseSIMDForMemoryOps, true);
224 }
225 if (FLAG_IS_DEFAULT(UseSIMDForArrayEquals)) {
226 FLAG_SET_DEFAULT(UseSIMDForArrayEquals, !(_revision == 1 || _revision == 2));
227 }
228 }
229
230 // ThunderX
231 if (_cpu == CPU_CAVIUM && (_model == 0xA1)) {
232 guarantee(_variant != 0, "Pre-release hardware no longer supported.");
233 if (FLAG_IS_DEFAULT(AvoidUnalignedAccesses)) {
234 FLAG_SET_DEFAULT(AvoidUnalignedAccesses, true);
235 }
236 if (FLAG_IS_DEFAULT(UseSIMDForMemoryOps)) {
237 FLAG_SET_DEFAULT(UseSIMDForMemoryOps, (_variant > 0));
238 }
239 if (FLAG_IS_DEFAULT(UseSIMDForArrayEquals)) {
240 FLAG_SET_DEFAULT(UseSIMDForArrayEquals, false);
241 }
242 }
243
244 // ThunderX2
245 if ((_cpu == CPU_CAVIUM && (_model == 0xAF)) ||
246 (_cpu == CPU_BROADCOM && (_model == 0x516))) {
247 if (FLAG_IS_DEFAULT(AvoidUnalignedAccesses)) {
248 FLAG_SET_DEFAULT(AvoidUnalignedAccesses, true);
249 }
250 if (FLAG_IS_DEFAULT(UseSIMDForMemoryOps)) {
251 FLAG_SET_DEFAULT(UseSIMDForMemoryOps, true);
252 }
253 }
254
255 // HiSilicon TSV110
256 if (_cpu == CPU_HISILICON && _model == 0xd01) {
257 if (FLAG_IS_DEFAULT(AvoidUnalignedAccesses)) {
258 FLAG_SET_DEFAULT(AvoidUnalignedAccesses, true);
259 }
260 if (FLAG_IS_DEFAULT(UseSIMDForMemoryOps)) {
261 FLAG_SET_DEFAULT(UseSIMDForMemoryOps, true);
262 }
263 }
264
265 // Cortex A53
266 if (_cpu == CPU_ARM && (_model == 0xd03 || _model2 == 0xd03)) {
267 _features |= CPU_A53MAC;
268 if (FLAG_IS_DEFAULT(UseSIMDForArrayEquals)) {
269 FLAG_SET_DEFAULT(UseSIMDForArrayEquals, false);
270 }
271 }
272
273 // Cortex A73
274 if (_cpu == CPU_ARM && (_model == 0xd09 || _model2 == 0xd09)) {
275 if (FLAG_IS_DEFAULT(SoftwarePrefetchHintDistance)) {
276 FLAG_SET_DEFAULT(SoftwarePrefetchHintDistance, -1);
277 }
278 // A73 is faster with short-and-easy-for-speculative-execution-loop
279 if (FLAG_IS_DEFAULT(UseSimpleArrayEquals)) {
280 FLAG_SET_DEFAULT(UseSimpleArrayEquals, true);
281 }
282 }
283
284 if (_cpu == CPU_ARM && (_model == 0xd07 || _model2 == 0xd07)) _features |= CPU_STXR_PREFETCH;
285 // If an olde style /proc/cpuinfo (cpu_lines == 1) then if _model is an A57 (0xd07)
286 // we assume the worst and assume we could be on a big little system and have
287 // undisclosed A53 cores which we could be swapped to at any stage
288 if (_cpu == CPU_ARM && cpu_lines == 1 && _model == 0xd07) _features |= CPU_A53MAC;
289
290 sprintf(buf, "0x%02x:0x%x:0x%03x:%d", _cpu, _variant, _model, _revision);
291 if (_model2) sprintf(buf+strlen(buf), "(0x%03x)", _model2);
292 if (auxv & HWCAP_ASIMD) strcat(buf, ", simd");
293 if (auxv & HWCAP_CRC32) strcat(buf, ", crc");
294 if (auxv & HWCAP_AES) strcat(buf, ", aes");
295 if (auxv & HWCAP_SHA1) strcat(buf, ", sha1");
296 if (auxv & HWCAP_SHA2) strcat(buf, ", sha256");
297 if (auxv & HWCAP_SHA512) strcat(buf, ", sha512");
298 if (auxv & HWCAP_SHA3) strcat(buf, ", sha3");
299 if (auxv & HWCAP_ATOMICS) strcat(buf, ", lse");
300
301 _features_string = os::strdup(buf);
302
303 if (FLAG_IS_DEFAULT(UseCRC32)) {
304 UseCRC32 = (auxv & HWCAP_CRC32) != 0;
305 }
306
307 if (UseCRC32 && (auxv & HWCAP_CRC32) == 0) {
308 warning("UseCRC32 specified, but not supported on this CPU");
309 FLAG_SET_DEFAULT(UseCRC32, false);
310 }
311
312 if (FLAG_IS_DEFAULT(UseAdler32Intrinsics)) {
313 FLAG_SET_DEFAULT(UseAdler32Intrinsics, true);
314 }
315
316 if (UseVectorizedMismatchIntrinsic) {
317 warning("UseVectorizedMismatchIntrinsic specified, but not available on this CPU.");
318 FLAG_SET_DEFAULT(UseVectorizedMismatchIntrinsic, false);
319 }
320
321 if (auxv & HWCAP_ATOMICS) {
322 if (FLAG_IS_DEFAULT(UseLSE))
323 FLAG_SET_DEFAULT(UseLSE, true);
324 } else {
325 if (UseLSE) {
326 warning("UseLSE specified, but not supported on this CPU");
327 FLAG_SET_DEFAULT(UseLSE, false);
328 }
329 }
330
331 if (auxv & HWCAP_AES) {
332 UseAES = UseAES || FLAG_IS_DEFAULT(UseAES);
333 UseAESIntrinsics =
334 UseAESIntrinsics || (UseAES && FLAG_IS_DEFAULT(UseAESIntrinsics));
335 if (UseAESIntrinsics && !UseAES) {
336 warning("UseAESIntrinsics enabled, but UseAES not, enabling");
337 UseAES = true;
338 }
339 } else {
340 if (UseAES) {
341 warning("AES instructions are not available on this CPU");
342 FLAG_SET_DEFAULT(UseAES, false);
343 }
344 if (UseAESIntrinsics) {
345 warning("AES intrinsics are not available on this CPU");
346 FLAG_SET_DEFAULT(UseAESIntrinsics, false);
347 }
348 }
349
350 if (UseAESCTRIntrinsics) {
351 warning("AES/CTR intrinsics are not available on this CPU");
352 FLAG_SET_DEFAULT(UseAESCTRIntrinsics, false);
353 }
354
355 if (FLAG_IS_DEFAULT(UseCRC32Intrinsics)) {
356 UseCRC32Intrinsics = true;
357 }
358
359 if (auxv & HWCAP_CRC32) {
360 if (FLAG_IS_DEFAULT(UseCRC32CIntrinsics)) {
361 FLAG_SET_DEFAULT(UseCRC32CIntrinsics, true);
362 }
363 } else if (UseCRC32CIntrinsics) {
364 warning("CRC32C is not available on the CPU");
365 FLAG_SET_DEFAULT(UseCRC32CIntrinsics, false);
366 }
367
368 if (FLAG_IS_DEFAULT(UseFMA)) {
369 FLAG_SET_DEFAULT(UseFMA, true);
370 }
371
372 if (UseMD5Intrinsics) {
373 warning("MD5 intrinsics are not available on this CPU");
374 FLAG_SET_DEFAULT(UseMD5Intrinsics, false);
375 }
376
377 if (auxv & (HWCAP_SHA1 | HWCAP_SHA2 | HWCAP_SHA512 | HWCAP_SHA3)) {
378 if (FLAG_IS_DEFAULT(UseSHA)) {
379 FLAG_SET_DEFAULT(UseSHA, true);
380 }
381 } else if (UseSHA) {
382 warning("SHA instructions are not available on this CPU");
383 FLAG_SET_DEFAULT(UseSHA, false);
384 }
385
386 if (UseSHA && (auxv & HWCAP_SHA1)) {
387 if (FLAG_IS_DEFAULT(UseSHA1Intrinsics)) {
388 FLAG_SET_DEFAULT(UseSHA1Intrinsics, true);
389 }
390 } else if (UseSHA1Intrinsics) {
391 warning("Intrinsics for SHA-1 crypto hash functions not available on this CPU.");
392 FLAG_SET_DEFAULT(UseSHA1Intrinsics, false);
393 }
394
395 if (UseSHA && (auxv & HWCAP_SHA2)) {
396 if (FLAG_IS_DEFAULT(UseSHA256Intrinsics)) {
397 FLAG_SET_DEFAULT(UseSHA256Intrinsics, true);
398 }
399 } else if (UseSHA256Intrinsics) {
400 warning("Intrinsics for SHA-224 and SHA-256 crypto hash functions not available on this CPU.");
401 FLAG_SET_DEFAULT(UseSHA256Intrinsics, false);
402 }
403
404 if (UseSHA && (auxv & HWCAP_SHA512)) {
405 // Do not auto-enable UseSHA512Intrinsics until it has been fully tested on hardware
406 // if (FLAG_IS_DEFAULT(UseSHA512Intrinsics)) {
407 // FLAG_SET_DEFAULT(UseSHA512Intrinsics, true);
408 // }
409 } else if (UseSHA512Intrinsics) {
410 warning("Intrinsics for SHA-384 and SHA-512 crypto hash functions not available on this CPU.");
411 FLAG_SET_DEFAULT(UseSHA512Intrinsics, false);
412 }
413
414 if (UseSHA && (auxv & HWCAP_SHA3)) {
415 // Do not auto-enable UseSHA3Intrinsics until it has been fully tested on hardware
416 // if (FLAG_IS_DEFAULT(UseSHA3Intrinsics)) {
417 // FLAG_SET_DEFAULT(UseSHA3Intrinsics, true);
418 // }
419 } else if (UseSHA3Intrinsics) {
420 warning("Intrinsics for SHA3-224, SHA3-256, SHA3-384 and SHA3-512 crypto hash functions not available on this CPU.");
421 FLAG_SET_DEFAULT(UseSHA3Intrinsics, false);
422 }
423
424 if (!(UseSHA1Intrinsics || UseSHA256Intrinsics || UseSHA512Intrinsics || UseSHA3Intrinsics)) {
425 FLAG_SET_DEFAULT(UseSHA, false);
426 }
427
428 if (auxv & HWCAP_PMULL) {
429 if (FLAG_IS_DEFAULT(UseGHASHIntrinsics)) {
430 FLAG_SET_DEFAULT(UseGHASHIntrinsics, true);
431 }
432 } else if (UseGHASHIntrinsics) {
433 warning("GHASH intrinsics are not available on this CPU");
434 FLAG_SET_DEFAULT(UseGHASHIntrinsics, false);
435 }
436
437 if (is_zva_enabled()) {
438 if (FLAG_IS_DEFAULT(UseBlockZeroing)) {
439 FLAG_SET_DEFAULT(UseBlockZeroing, true);
440 }
441 if (FLAG_IS_DEFAULT(BlockZeroingLowLimit)) {
442 FLAG_SET_DEFAULT(BlockZeroingLowLimit, 4 * VM_Version::zva_length());
443 }
444 } else if (UseBlockZeroing) {
445 warning("DC ZVA is not available on this CPU");
446 FLAG_SET_DEFAULT(UseBlockZeroing, false);
447 }
448
449 // This machine allows unaligned memory accesses
450 if (FLAG_IS_DEFAULT(UseUnalignedAccesses)) {
451 FLAG_SET_DEFAULT(UseUnalignedAccesses, true);
452 }
453
454 if (FLAG_IS_DEFAULT(UsePopCountInstruction)) {
455 FLAG_SET_DEFAULT(UsePopCountInstruction, true);
456 }
457
458 if (!UsePopCountInstruction) {
459 warning("UsePopCountInstruction is always enabled on this CPU");
460 UsePopCountInstruction = true;
461 }
462
463 #ifdef COMPILER2
464 if (FLAG_IS_DEFAULT(UseMultiplyToLenIntrinsic)) {
465 UseMultiplyToLenIntrinsic = true;
466 }
467
468 if (FLAG_IS_DEFAULT(UseSquareToLenIntrinsic)) {
469 UseSquareToLenIntrinsic = true;
470 }
471
472 if (FLAG_IS_DEFAULT(UseMulAddIntrinsic)) {
473 UseMulAddIntrinsic = true;
474 }
475
476 if (FLAG_IS_DEFAULT(UseMontgomeryMultiplyIntrinsic)) {
477 UseMontgomeryMultiplyIntrinsic = true;
478 }
479 if (FLAG_IS_DEFAULT(UseMontgomerySquareIntrinsic)) {
480 UseMontgomerySquareIntrinsic = true;
481 }
482
483 if (FLAG_IS_DEFAULT(OptoScheduling)) {
484 OptoScheduling = true;
485 }
486
487 if (FLAG_IS_DEFAULT(AlignVector)) {
488 AlignVector = AvoidUnalignedAccesses;
489 }
490 #endif
491 }
492
493 void VM_Version::initialize() {
494 ResourceMark rm;
495
496 stub_blob = BufferBlob::create("getPsrInfo_stub", stub_size);
497 if (stub_blob == NULL) {
498 vm_exit_during_initialization("Unable to allocate getPsrInfo_stub");
499 }
500
501 CodeBuffer c(stub_blob);
502 VM_Version_StubGenerator g(&c);
503 getPsrInfo_stub = CAST_TO_FN_PTR(getPsrInfo_stub_t,
504 g.generate_getPsrInfo());
505
506 get_processor_features();
507
508 UNSUPPORTED_OPTION(CriticalJNINatives);
509 }