1 /*
2 * Copyright (c) 1997, 2020, Oracle and/or its affiliates. All rights reserved.
3 * Copyright (c) 2015, 2020, Red Hat Inc. All rights reserved.
4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
5 *
6 * This code is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 only, as
8 * published by the Free Software Foundation.
9 *
10 * This code is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * version 2 for more details (a copy is included in the LICENSE file that
14 * accompanied this code).
15 *
16 * You should have received a copy of the GNU General Public License version
17 * 2 along with this work; if not, write to the Free Software Foundation,
18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 * or visit www.oracle.com if you need additional information or have any
22 * questions.
23 *
24 */
25
26 #include "precompiled.hpp"
27 #include "asm/macroAssembler.hpp"
28 #include "asm/macroAssembler.inline.hpp"
29 #include "memory/resourceArea.hpp"
30 #include "runtime/arguments.hpp"
31 #include "runtime/java.hpp"
32 #include "runtime/os.hpp"
33 #include "runtime/stubCodeGenerator.hpp"
34 #include "runtime/vm_version.hpp"
35 #include "utilities/macros.hpp"
36
37 #include OS_HEADER_INLINE(os)
38
39 #include <sys/auxv.h>
40 #include <asm/hwcap.h>
41
42 #ifndef HWCAP_AES
43 #define HWCAP_AES (1<<3)
44 #endif
45
46 #ifndef HWCAP_PMULL
47 #define HWCAP_PMULL (1<<4)
48 #endif
49
50 #ifndef HWCAP_SHA1
51 #define HWCAP_SHA1 (1<<5)
52 #endif
53
54 #ifndef HWCAP_SHA2
55 #define HWCAP_SHA2 (1<<6)
56 #endif
57
58 #ifndef HWCAP_CRC32
59 #define HWCAP_CRC32 (1<<7)
60 #endif
61
62 #ifndef HWCAP_ATOMICS
63 #define HWCAP_ATOMICS (1<<8)
64 #endif
65
66 #ifndef HWCAP_SHA512
67 #define HWCAP_SHA512 (1 << 21)
68 #endif
69
70 int VM_Version::_cpu;
71 int VM_Version::_model;
72 int VM_Version::_model2;
73 int VM_Version::_variant;
74 int VM_Version::_revision;
75 int VM_Version::_stepping;
76 bool VM_Version::_dcpop;
77 VM_Version::PsrInfo VM_Version::_psr_info = { 0, };
78
79 static BufferBlob* stub_blob;
80 static const int stub_size = 550;
81
82 extern "C" {
83 typedef void (*getPsrInfo_stub_t)(void*);
84 }
85 static getPsrInfo_stub_t getPsrInfo_stub = NULL;
86
87
88 class VM_Version_StubGenerator: public StubCodeGenerator {
89 public:
90
91 VM_Version_StubGenerator(CodeBuffer *c) : StubCodeGenerator(c) {}
92
93 address generate_getPsrInfo() {
94 StubCodeMark mark(this, "VM_Version", "getPsrInfo_stub");
95 # define __ _masm->
96 address start = __ pc();
97
98 // void getPsrInfo(VM_Version::PsrInfo* psr_info);
99
100 address entry = __ pc();
101
102 __ enter();
103
104 __ get_dczid_el0(rscratch1);
105 __ strw(rscratch1, Address(c_rarg0, in_bytes(VM_Version::dczid_el0_offset())));
106
107 __ get_ctr_el0(rscratch1);
108 __ strw(rscratch1, Address(c_rarg0, in_bytes(VM_Version::ctr_el0_offset())));
109
110 __ leave();
111 __ ret(lr);
112
113 # undef __
114
115 return start;
116 }
117 };
118
119
120 void VM_Version::get_processor_features() {
121 _supports_cx8 = true;
122 _supports_atomic_getset4 = true;
123 _supports_atomic_getadd4 = true;
124 _supports_atomic_getset8 = true;
125 _supports_atomic_getadd8 = true;
126
127 getPsrInfo_stub(&_psr_info);
128
129 int dcache_line = VM_Version::dcache_line_size();
130
131 // Limit AllocatePrefetchDistance so that it does not exceed the
132 // constraint in AllocatePrefetchDistanceConstraintFunc.
133 if (FLAG_IS_DEFAULT(AllocatePrefetchDistance))
134 FLAG_SET_DEFAULT(AllocatePrefetchDistance, MIN2(512, 3*dcache_line));
135
136 if (FLAG_IS_DEFAULT(AllocatePrefetchStepSize))
137 FLAG_SET_DEFAULT(AllocatePrefetchStepSize, dcache_line);
138 if (FLAG_IS_DEFAULT(PrefetchScanIntervalInBytes))
139 FLAG_SET_DEFAULT(PrefetchScanIntervalInBytes, 3*dcache_line);
140 if (FLAG_IS_DEFAULT(PrefetchCopyIntervalInBytes))
141 FLAG_SET_DEFAULT(PrefetchCopyIntervalInBytes, 3*dcache_line);
142 if (FLAG_IS_DEFAULT(SoftwarePrefetchHintDistance))
143 FLAG_SET_DEFAULT(SoftwarePrefetchHintDistance, 3*dcache_line);
144
145 if (PrefetchCopyIntervalInBytes != -1 &&
146 ((PrefetchCopyIntervalInBytes & 7) || (PrefetchCopyIntervalInBytes >= 32768))) {
147 warning("PrefetchCopyIntervalInBytes must be -1, or a multiple of 8 and < 32768");
148 PrefetchCopyIntervalInBytes &= ~7;
149 if (PrefetchCopyIntervalInBytes >= 32768)
150 PrefetchCopyIntervalInBytes = 32760;
151 }
152
153 if (AllocatePrefetchDistance !=-1 && (AllocatePrefetchDistance & 7)) {
154 warning("AllocatePrefetchDistance must be multiple of 8");
155 AllocatePrefetchDistance &= ~7;
156 }
157
158 if (AllocatePrefetchStepSize & 7) {
159 warning("AllocatePrefetchStepSize must be multiple of 8");
160 AllocatePrefetchStepSize &= ~7;
161 }
162
163 if (SoftwarePrefetchHintDistance != -1 &&
164 (SoftwarePrefetchHintDistance & 7)) {
165 warning("SoftwarePrefetchHintDistance must be -1, or a multiple of 8");
166 SoftwarePrefetchHintDistance &= ~7;
167 }
168
169 uint64_t auxv = getauxval(AT_HWCAP);
170
171 char buf[512];
172
173 _features = auxv;
174
175 int cpu_lines = 0;
176 if (FILE *f = fopen("/proc/cpuinfo", "r")) {
177 // need a large buffer as the flags line may include lots of text
178 char buf[1024], *p;
179 while (fgets(buf, sizeof (buf), f) != NULL) {
180 if ((p = strchr(buf, ':')) != NULL) {
181 long v = strtol(p+1, NULL, 0);
182 if (strncmp(buf, "CPU implementer", sizeof "CPU implementer" - 1) == 0) {
183 _cpu = v;
184 cpu_lines++;
185 } else if (strncmp(buf, "CPU variant", sizeof "CPU variant" - 1) == 0) {
186 _variant = v;
187 } else if (strncmp(buf, "CPU part", sizeof "CPU part" - 1) == 0) {
188 if (_model != v) _model2 = _model;
189 _model = v;
190 } else if (strncmp(buf, "CPU revision", sizeof "CPU revision" - 1) == 0) {
191 _revision = v;
192 } else if (strncmp(buf, "flags", sizeof("flags") - 1) == 0) {
193 if (strstr(p+1, "dcpop")) {
194 _dcpop = true;
195 }
196 }
197 }
198 }
199 fclose(f);
200 }
201
202 if (os::supports_map_sync()) {
203 // if dcpop is available publish data cache line flush size via
204 // generic field, otherwise let if default to zero thereby
205 // disabling writeback
206 if (_dcpop) {
207 _data_cache_line_flush_size = dcache_line;
208 }
209 }
210
211 // Enable vendor specific features
212
213 // Ampere eMAG
214 if (_cpu == CPU_AMCC && (_model == 0) && (_variant == 0x3)) {
215 if (FLAG_IS_DEFAULT(AvoidUnalignedAccesses)) {
216 FLAG_SET_DEFAULT(AvoidUnalignedAccesses, true);
217 }
218 if (FLAG_IS_DEFAULT(UseSIMDForMemoryOps)) {
219 FLAG_SET_DEFAULT(UseSIMDForMemoryOps, true);
220 }
221 if (FLAG_IS_DEFAULT(UseSIMDForArrayEquals)) {
222 FLAG_SET_DEFAULT(UseSIMDForArrayEquals, !(_revision == 1 || _revision == 2));
223 }
224 }
225
226 // ThunderX
227 if (_cpu == CPU_CAVIUM && (_model == 0xA1)) {
228 guarantee(_variant != 0, "Pre-release hardware no longer supported.");
229 if (FLAG_IS_DEFAULT(AvoidUnalignedAccesses)) {
230 FLAG_SET_DEFAULT(AvoidUnalignedAccesses, true);
231 }
232 if (FLAG_IS_DEFAULT(UseSIMDForMemoryOps)) {
233 FLAG_SET_DEFAULT(UseSIMDForMemoryOps, (_variant > 0));
234 }
235 if (FLAG_IS_DEFAULT(UseSIMDForArrayEquals)) {
236 FLAG_SET_DEFAULT(UseSIMDForArrayEquals, false);
237 }
238 }
239
240 // ThunderX2
241 if ((_cpu == CPU_CAVIUM && (_model == 0xAF)) ||
242 (_cpu == CPU_BROADCOM && (_model == 0x516))) {
243 if (FLAG_IS_DEFAULT(AvoidUnalignedAccesses)) {
244 FLAG_SET_DEFAULT(AvoidUnalignedAccesses, true);
245 }
246 if (FLAG_IS_DEFAULT(UseSIMDForMemoryOps)) {
247 FLAG_SET_DEFAULT(UseSIMDForMemoryOps, true);
248 }
249 }
250
251 // HiSilicon TSV110
252 if (_cpu == CPU_HISILICON && _model == 0xd01) {
253 if (FLAG_IS_DEFAULT(AvoidUnalignedAccesses)) {
254 FLAG_SET_DEFAULT(AvoidUnalignedAccesses, true);
255 }
256 if (FLAG_IS_DEFAULT(UseSIMDForMemoryOps)) {
257 FLAG_SET_DEFAULT(UseSIMDForMemoryOps, true);
258 }
259 }
260
261 // Cortex A53
262 if (_cpu == CPU_ARM && (_model == 0xd03 || _model2 == 0xd03)) {
263 _features |= CPU_A53MAC;
264 if (FLAG_IS_DEFAULT(UseSIMDForArrayEquals)) {
265 FLAG_SET_DEFAULT(UseSIMDForArrayEquals, false);
266 }
267 }
268
269 // Cortex A73
270 if (_cpu == CPU_ARM && (_model == 0xd09 || _model2 == 0xd09)) {
271 if (FLAG_IS_DEFAULT(SoftwarePrefetchHintDistance)) {
272 FLAG_SET_DEFAULT(SoftwarePrefetchHintDistance, -1);
273 }
274 // A73 is faster with short-and-easy-for-speculative-execution-loop
275 if (FLAG_IS_DEFAULT(UseSimpleArrayEquals)) {
276 FLAG_SET_DEFAULT(UseSimpleArrayEquals, true);
277 }
278 }
279
280 if (_cpu == CPU_ARM && (_model == 0xd07 || _model2 == 0xd07)) _features |= CPU_STXR_PREFETCH;
281 // If an olde style /proc/cpuinfo (cpu_lines == 1) then if _model is an A57 (0xd07)
282 // we assume the worst and assume we could be on a big little system and have
283 // undisclosed A53 cores which we could be swapped to at any stage
284 if (_cpu == CPU_ARM && cpu_lines == 1 && _model == 0xd07) _features |= CPU_A53MAC;
285
286 sprintf(buf, "0x%02x:0x%x:0x%03x:%d", _cpu, _variant, _model, _revision);
287 if (_model2) sprintf(buf+strlen(buf), "(0x%03x)", _model2);
288 if (auxv & HWCAP_ASIMD) strcat(buf, ", simd");
289 if (auxv & HWCAP_CRC32) strcat(buf, ", crc");
290 if (auxv & HWCAP_AES) strcat(buf, ", aes");
291 if (auxv & HWCAP_SHA1) strcat(buf, ", sha1");
292 if (auxv & HWCAP_SHA2) strcat(buf, ", sha256");
293 if (auxv & HWCAP_SHA512) strcat(buf, ", sha512");
294 if (auxv & HWCAP_ATOMICS) strcat(buf, ", lse");
295
296 _features_string = os::strdup(buf);
297
298 if (FLAG_IS_DEFAULT(UseCRC32)) {
299 UseCRC32 = (auxv & HWCAP_CRC32) != 0;
300 }
301
302 if (UseCRC32 && (auxv & HWCAP_CRC32) == 0) {
303 warning("UseCRC32 specified, but not supported on this CPU");
304 FLAG_SET_DEFAULT(UseCRC32, false);
305 }
306
307 if (FLAG_IS_DEFAULT(UseAdler32Intrinsics)) {
308 FLAG_SET_DEFAULT(UseAdler32Intrinsics, true);
309 }
310
311 if (UseVectorizedMismatchIntrinsic) {
312 warning("UseVectorizedMismatchIntrinsic specified, but not available on this CPU.");
313 FLAG_SET_DEFAULT(UseVectorizedMismatchIntrinsic, false);
314 }
315
316 if (auxv & HWCAP_ATOMICS) {
317 if (FLAG_IS_DEFAULT(UseLSE))
318 FLAG_SET_DEFAULT(UseLSE, true);
319 } else {
320 if (UseLSE) {
321 warning("UseLSE specified, but not supported on this CPU");
322 FLAG_SET_DEFAULT(UseLSE, false);
323 }
324 }
325
326 if (auxv & HWCAP_AES) {
327 UseAES = UseAES || FLAG_IS_DEFAULT(UseAES);
328 UseAESIntrinsics =
329 UseAESIntrinsics || (UseAES && FLAG_IS_DEFAULT(UseAESIntrinsics));
330 if (UseAESIntrinsics && !UseAES) {
331 warning("UseAESIntrinsics enabled, but UseAES not, enabling");
332 UseAES = true;
333 }
334 } else {
335 if (UseAES) {
336 warning("AES instructions are not available on this CPU");
337 FLAG_SET_DEFAULT(UseAES, false);
338 }
339 if (UseAESIntrinsics) {
340 warning("AES intrinsics are not available on this CPU");
341 FLAG_SET_DEFAULT(UseAESIntrinsics, false);
342 }
343 }
344
345 if (UseAESCTRIntrinsics) {
346 warning("AES/CTR intrinsics are not available on this CPU");
347 FLAG_SET_DEFAULT(UseAESCTRIntrinsics, false);
348 }
349
350 if (FLAG_IS_DEFAULT(UseCRC32Intrinsics)) {
351 UseCRC32Intrinsics = true;
352 }
353
354 if (auxv & HWCAP_CRC32) {
355 if (FLAG_IS_DEFAULT(UseCRC32CIntrinsics)) {
356 FLAG_SET_DEFAULT(UseCRC32CIntrinsics, true);
357 }
358 } else if (UseCRC32CIntrinsics) {
359 warning("CRC32C is not available on the CPU");
360 FLAG_SET_DEFAULT(UseCRC32CIntrinsics, false);
361 }
362
363 if (FLAG_IS_DEFAULT(UseFMA)) {
364 FLAG_SET_DEFAULT(UseFMA, true);
365 }
366
367 if (UseMD5Intrinsics) {
368 warning("MD5 intrinsics are not available on this CPU");
369 FLAG_SET_DEFAULT(UseMD5Intrinsics, false);
370 }
371
372 if (auxv & (HWCAP_SHA1 | HWCAP_SHA2)) {
373 if (FLAG_IS_DEFAULT(UseSHA)) {
374 FLAG_SET_DEFAULT(UseSHA, true);
375 }
376 } else if (UseSHA) {
377 warning("SHA instructions are not available on this CPU");
378 FLAG_SET_DEFAULT(UseSHA, false);
379 }
380
381 if (UseSHA && (auxv & HWCAP_SHA1)) {
382 if (FLAG_IS_DEFAULT(UseSHA1Intrinsics)) {
383 FLAG_SET_DEFAULT(UseSHA1Intrinsics, true);
384 }
385 } else if (UseSHA1Intrinsics) {
386 warning("Intrinsics for SHA-1 crypto hash functions not available on this CPU.");
387 FLAG_SET_DEFAULT(UseSHA1Intrinsics, false);
388 }
389
390 if (UseSHA && (auxv & HWCAP_SHA2)) {
391 if (FLAG_IS_DEFAULT(UseSHA256Intrinsics)) {
392 FLAG_SET_DEFAULT(UseSHA256Intrinsics, true);
393 }
394 } else if (UseSHA256Intrinsics) {
395 warning("Intrinsics for SHA-224 and SHA-256 crypto hash functions not available on this CPU.");
396 FLAG_SET_DEFAULT(UseSHA256Intrinsics, false);
397 }
398
399 if (UseSHA && (auxv & HWCAP_SHA512)) {
400 // Do not auto-enable UseSHA512Intrinsics until it has been fully tested on hardware
401 // if (FLAG_IS_DEFAULT(UseSHA512Intrinsics)) {
402 // FLAG_SET_DEFAULT(UseSHA512Intrinsics, true);
403 // }
404 } else if (UseSHA512Intrinsics) {
405 warning("Intrinsics for SHA-384 and SHA-512 crypto hash functions not available on this CPU.");
406 FLAG_SET_DEFAULT(UseSHA512Intrinsics, false);
407 }
408
409 if (!(UseSHA1Intrinsics || UseSHA256Intrinsics || UseSHA512Intrinsics)) {
410 FLAG_SET_DEFAULT(UseSHA, false);
411 }
412
413 if (auxv & HWCAP_PMULL) {
414 if (FLAG_IS_DEFAULT(UseGHASHIntrinsics)) {
415 FLAG_SET_DEFAULT(UseGHASHIntrinsics, true);
416 }
417 } else if (UseGHASHIntrinsics) {
418 warning("GHASH intrinsics are not available on this CPU");
419 FLAG_SET_DEFAULT(UseGHASHIntrinsics, false);
420 }
421
422 if (is_zva_enabled()) {
423 if (FLAG_IS_DEFAULT(UseBlockZeroing)) {
424 FLAG_SET_DEFAULT(UseBlockZeroing, true);
425 }
426 if (FLAG_IS_DEFAULT(BlockZeroingLowLimit)) {
427 FLAG_SET_DEFAULT(BlockZeroingLowLimit, 4 * VM_Version::zva_length());
428 }
429 } else if (UseBlockZeroing) {
430 warning("DC ZVA is not available on this CPU");
431 FLAG_SET_DEFAULT(UseBlockZeroing, false);
432 }
433
434 // This machine allows unaligned memory accesses
435 if (FLAG_IS_DEFAULT(UseUnalignedAccesses)) {
436 FLAG_SET_DEFAULT(UseUnalignedAccesses, true);
437 }
438
439 if (FLAG_IS_DEFAULT(UsePopCountInstruction)) {
440 FLAG_SET_DEFAULT(UsePopCountInstruction, true);
441 }
442
443 if (!UsePopCountInstruction) {
444 warning("UsePopCountInstruction is always enabled on this CPU");
445 UsePopCountInstruction = true;
446 }
447
448 #ifdef COMPILER2
449 if (FLAG_IS_DEFAULT(UseMultiplyToLenIntrinsic)) {
450 UseMultiplyToLenIntrinsic = true;
451 }
452
453 if (FLAG_IS_DEFAULT(UseSquareToLenIntrinsic)) {
454 UseSquareToLenIntrinsic = true;
455 }
456
457 if (FLAG_IS_DEFAULT(UseMulAddIntrinsic)) {
458 UseMulAddIntrinsic = true;
459 }
460
461 if (FLAG_IS_DEFAULT(UseMontgomeryMultiplyIntrinsic)) {
462 UseMontgomeryMultiplyIntrinsic = true;
463 }
464 if (FLAG_IS_DEFAULT(UseMontgomerySquareIntrinsic)) {
465 UseMontgomerySquareIntrinsic = true;
466 }
467
468 if (FLAG_IS_DEFAULT(OptoScheduling)) {
469 OptoScheduling = true;
470 }
471
472 if (FLAG_IS_DEFAULT(AlignVector)) {
473 AlignVector = AvoidUnalignedAccesses;
474 }
475 #endif
476 }
477
478 void VM_Version::initialize() {
479 ResourceMark rm;
480
481 stub_blob = BufferBlob::create("getPsrInfo_stub", stub_size);
482 if (stub_blob == NULL) {
483 vm_exit_during_initialization("Unable to allocate getPsrInfo_stub");
484 }
485
486 CodeBuffer c(stub_blob);
487 VM_Version_StubGenerator g(&c);
488 getPsrInfo_stub = CAST_TO_FN_PTR(getPsrInfo_stub_t,
489 g.generate_getPsrInfo());
490
491 get_processor_features();
492
493 UNSUPPORTED_OPTION(CriticalJNINatives);
494 }