src/hotspot/cpu/aarch64/assembler_aarch64.hpp

rev 60737 : 8252204: AArch64: Implement SHA3 accelerator/intrinsic
Reviewed-by: duke
Contributed-by: dongbo4@huawei.com

@@ -2401,10 +2401,44 @@
   INSN(sha512su0, 0b1100111011000000100000);
 
 #undef INSN
 
 #define INSN(NAME, opc)                           \
+  void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn, FloatRegister Vm, FloatRegister Va) { \
+    starti;                                                                                               \
+    assert(T == T16B, "arrangement must be T16B");                                                        \
+    f(0b11001110, 31, 24), f(opc, 23, 21), rf(Vm, 16), f(0b0, 15, 15), rf(Va, 10), rf(Vn, 5), rf(Vd, 0);  \
+  }
+
+  INSN(eor3, 0b000);
+  INSN(bcax, 0b001);
+
+#undef INSN
+
+#define INSN(NAME, opc)                                                                               \
+  void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn, FloatRegister Vm, unsigned imm) { \
+    starti;                                                                                           \
+    assert(T == T2D, "arrangement must be T2D");                                                      \
+    f(0b11001110, 31, 24), f(opc, 23, 21), rf(Vm, 16), f(imm, 15, 10), rf(Vn, 5), rf(Vd, 0);          \
+  }
+
+  INSN(xar, 0b100);
+
+#undef INSN
+
+#define INSN(NAME, opc)                                                                           \
+  void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn, FloatRegister Vm) {           \
+    starti;                                                                                       \
+    assert(T == T2D, "arrangement must be T2D");                                                  \
+    f(0b11001110, 31, 24), f(opc, 23, 21), rf(Vm, 16), f(0b100011, 15, 10), rf(Vn, 5), rf(Vd, 0); \
+  }
+
+  INSN(rax1, 0b011);
+
+#undef INSN
+
+#define INSN(NAME, opc)                           \
   void NAME(FloatRegister Vd, FloatRegister Vn) { \
     starti;                                       \
     f(opc, 31, 10), rf(Vn, 5), rf(Vd, 0);         \
   }