rev 60737 : 8252204: AArch64: Implement SHA3 accelerator/intrinsic
Reviewed-by: duke
Contributed-by: dongbo4@huawei.com
1 /*
2 * Copyright (c) 1997, 2020, Oracle and/or its affiliates. All rights reserved.
3 * Copyright (c) 2014, 2020, Red Hat Inc. All rights reserved.
4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
5 *
6 * This code is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 only, as
8 * published by the Free Software Foundation.
9 *
10 * This code is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * version 2 for more details (a copy is included in the LICENSE file that
14 * accompanied this code).
15 *
16 * You should have received a copy of the GNU General Public License version
17 * 2 along with this work; if not, write to the Free Software Foundation,
18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 * or visit www.oracle.com if you need additional information or have any
22 * questions.
23 *
24 */
25
26 #ifndef CPU_AARCH64_ASSEMBLER_AARCH64_HPP
27 #define CPU_AARCH64_ASSEMBLER_AARCH64_HPP
28
29 #include "asm/register.hpp"
30
31 // definitions of various symbolic names for machine registers
32
33 // First intercalls between C and Java which use 8 general registers
34 // and 8 floating registers
35
36 // we also have to copy between x86 and ARM registers but that's a
37 // secondary complication -- not all code employing C call convention
38 // executes as x86 code though -- we generate some of it
39
40 class Argument {
41 public:
42 enum {
43 n_int_register_parameters_c = 8, // r0, r1, ... r7 (c_rarg0, c_rarg1, ...)
44 n_float_register_parameters_c = 8, // v0, v1, ... v7 (c_farg0, c_farg1, ... )
45
46 n_int_register_parameters_j = 8, // r1, ... r7, r0 (rj_rarg0, j_rarg1, ...
47 n_float_register_parameters_j = 8 // v0, v1, ... v7 (j_farg0, j_farg1, ...
48 };
49 };
50
51 REGISTER_DECLARATION(Register, c_rarg0, r0);
52 REGISTER_DECLARATION(Register, c_rarg1, r1);
53 REGISTER_DECLARATION(Register, c_rarg2, r2);
54 REGISTER_DECLARATION(Register, c_rarg3, r3);
55 REGISTER_DECLARATION(Register, c_rarg4, r4);
56 REGISTER_DECLARATION(Register, c_rarg5, r5);
57 REGISTER_DECLARATION(Register, c_rarg6, r6);
58 REGISTER_DECLARATION(Register, c_rarg7, r7);
59
60 REGISTER_DECLARATION(FloatRegister, c_farg0, v0);
61 REGISTER_DECLARATION(FloatRegister, c_farg1, v1);
62 REGISTER_DECLARATION(FloatRegister, c_farg2, v2);
63 REGISTER_DECLARATION(FloatRegister, c_farg3, v3);
64 REGISTER_DECLARATION(FloatRegister, c_farg4, v4);
65 REGISTER_DECLARATION(FloatRegister, c_farg5, v5);
66 REGISTER_DECLARATION(FloatRegister, c_farg6, v6);
67 REGISTER_DECLARATION(FloatRegister, c_farg7, v7);
68
69 // Symbolically name the register arguments used by the Java calling convention.
70 // We have control over the convention for java so we can do what we please.
71 // What pleases us is to offset the java calling convention so that when
72 // we call a suitable jni method the arguments are lined up and we don't
73 // have to do much shuffling. A suitable jni method is non-static and a
74 // small number of arguments
75 //
76 // |--------------------------------------------------------------------|
77 // | c_rarg0 c_rarg1 c_rarg2 c_rarg3 c_rarg4 c_rarg5 c_rarg6 c_rarg7 |
78 // |--------------------------------------------------------------------|
79 // | r0 r1 r2 r3 r4 r5 r6 r7 |
80 // |--------------------------------------------------------------------|
81 // | j_rarg7 j_rarg0 j_rarg1 j_rarg2 j_rarg3 j_rarg4 j_rarg5 j_rarg6 |
82 // |--------------------------------------------------------------------|
83
84
85 REGISTER_DECLARATION(Register, j_rarg0, c_rarg1);
86 REGISTER_DECLARATION(Register, j_rarg1, c_rarg2);
87 REGISTER_DECLARATION(Register, j_rarg2, c_rarg3);
88 REGISTER_DECLARATION(Register, j_rarg3, c_rarg4);
89 REGISTER_DECLARATION(Register, j_rarg4, c_rarg5);
90 REGISTER_DECLARATION(Register, j_rarg5, c_rarg6);
91 REGISTER_DECLARATION(Register, j_rarg6, c_rarg7);
92 REGISTER_DECLARATION(Register, j_rarg7, c_rarg0);
93
94 // Java floating args are passed as per C
95
96 REGISTER_DECLARATION(FloatRegister, j_farg0, v0);
97 REGISTER_DECLARATION(FloatRegister, j_farg1, v1);
98 REGISTER_DECLARATION(FloatRegister, j_farg2, v2);
99 REGISTER_DECLARATION(FloatRegister, j_farg3, v3);
100 REGISTER_DECLARATION(FloatRegister, j_farg4, v4);
101 REGISTER_DECLARATION(FloatRegister, j_farg5, v5);
102 REGISTER_DECLARATION(FloatRegister, j_farg6, v6);
103 REGISTER_DECLARATION(FloatRegister, j_farg7, v7);
104
105 // registers used to hold VM data either temporarily within a method
106 // or across method calls
107
108 // volatile (caller-save) registers
109
110 // r8 is used for indirect result location return
111 // we use it and r9 as scratch registers
112 REGISTER_DECLARATION(Register, rscratch1, r8);
113 REGISTER_DECLARATION(Register, rscratch2, r9);
114
115 // current method -- must be in a call-clobbered register
116 REGISTER_DECLARATION(Register, rmethod, r12);
117
118 // non-volatile (callee-save) registers are r16-29
119 // of which the following are dedicated global state
120
121 // link register
122 REGISTER_DECLARATION(Register, lr, r30);
123 // frame pointer
124 REGISTER_DECLARATION(Register, rfp, r29);
125 // current thread
126 REGISTER_DECLARATION(Register, rthread, r28);
127 // base of heap
128 REGISTER_DECLARATION(Register, rheapbase, r27);
129 // constant pool cache
130 REGISTER_DECLARATION(Register, rcpool, r26);
131 // monitors allocated on stack
132 REGISTER_DECLARATION(Register, rmonitors, r25);
133 // locals on stack
134 REGISTER_DECLARATION(Register, rlocals, r24);
135 // bytecode pointer
136 REGISTER_DECLARATION(Register, rbcp, r22);
137 // Dispatch table base
138 REGISTER_DECLARATION(Register, rdispatch, r21);
139 // Java stack pointer
140 REGISTER_DECLARATION(Register, esp, r20);
141
142 #define assert_cond(ARG1) assert(ARG1, #ARG1)
143
144 namespace asm_util {
145 uint32_t encode_logical_immediate(bool is32, uint64_t imm);
146 };
147
148 using namespace asm_util;
149
150
151 class Assembler;
152
153 class Instruction_aarch64 {
154 unsigned insn;
155 #ifdef ASSERT
156 unsigned bits;
157 #endif
158 Assembler *assem;
159
160 public:
161
162 Instruction_aarch64(class Assembler *as) {
163 #ifdef ASSERT
164 bits = 0;
165 #endif
166 insn = 0;
167 assem = as;
168 }
169
170 inline ~Instruction_aarch64();
171
172 unsigned &get_insn() { return insn; }
173 #ifdef ASSERT
174 unsigned &get_bits() { return bits; }
175 #endif
176
177 static inline int32_t extend(unsigned val, int hi = 31, int lo = 0) {
178 union {
179 unsigned u;
180 int n;
181 };
182
183 u = val << (31 - hi);
184 n = n >> (31 - hi + lo);
185 return n;
186 }
187
188 static inline uint32_t extract(uint32_t val, int msb, int lsb) {
189 int nbits = msb - lsb + 1;
190 assert_cond(msb >= lsb);
191 uint32_t mask = (1U << nbits) - 1;
192 uint32_t result = val >> lsb;
193 result &= mask;
194 return result;
195 }
196
197 static inline int32_t sextract(uint32_t val, int msb, int lsb) {
198 uint32_t uval = extract(val, msb, lsb);
199 return extend(uval, msb - lsb);
200 }
201
202 static void patch(address a, int msb, int lsb, uint64_t val) {
203 int nbits = msb - lsb + 1;
204 guarantee(val < (1U << nbits), "Field too big for insn");
205 assert_cond(msb >= lsb);
206 unsigned mask = (1U << nbits) - 1;
207 val <<= lsb;
208 mask <<= lsb;
209 unsigned target = *(unsigned *)a;
210 target &= ~mask;
211 target |= val;
212 *(unsigned *)a = target;
213 }
214
215 static void spatch(address a, int msb, int lsb, int64_t val) {
216 int nbits = msb - lsb + 1;
217 int64_t chk = val >> (nbits - 1);
218 guarantee (chk == -1 || chk == 0, "Field too big for insn");
219 unsigned uval = val;
220 unsigned mask = (1U << nbits) - 1;
221 uval &= mask;
222 uval <<= lsb;
223 mask <<= lsb;
224 unsigned target = *(unsigned *)a;
225 target &= ~mask;
226 target |= uval;
227 *(unsigned *)a = target;
228 }
229
230 void f(unsigned val, int msb, int lsb) {
231 int nbits = msb - lsb + 1;
232 guarantee(val < (1U << nbits), "Field too big for insn");
233 assert_cond(msb >= lsb);
234 unsigned mask = (1U << nbits) - 1;
235 val <<= lsb;
236 mask <<= lsb;
237 insn |= val;
238 assert_cond((bits & mask) == 0);
239 #ifdef ASSERT
240 bits |= mask;
241 #endif
242 }
243
244 void f(unsigned val, int bit) {
245 f(val, bit, bit);
246 }
247
248 void sf(int64_t val, int msb, int lsb) {
249 int nbits = msb - lsb + 1;
250 int64_t chk = val >> (nbits - 1);
251 guarantee (chk == -1 || chk == 0, "Field too big for insn");
252 unsigned uval = val;
253 unsigned mask = (1U << nbits) - 1;
254 uval &= mask;
255 f(uval, lsb + nbits - 1, lsb);
256 }
257
258 void rf(Register r, int lsb) {
259 f(r->encoding_nocheck(), lsb + 4, lsb);
260 }
261
262 // reg|ZR
263 void zrf(Register r, int lsb) {
264 f(r->encoding_nocheck() - (r == zr), lsb + 4, lsb);
265 }
266
267 // reg|SP
268 void srf(Register r, int lsb) {
269 f(r == sp ? 31 : r->encoding_nocheck(), lsb + 4, lsb);
270 }
271
272 void rf(FloatRegister r, int lsb) {
273 f(r->encoding_nocheck(), lsb + 4, lsb);
274 }
275
276 unsigned get(int msb = 31, int lsb = 0) {
277 int nbits = msb - lsb + 1;
278 unsigned mask = ((1U << nbits) - 1) << lsb;
279 assert_cond((bits & mask) == mask);
280 return (insn & mask) >> lsb;
281 }
282
283 void fixed(unsigned value, unsigned mask) {
284 assert_cond ((mask & bits) == 0);
285 #ifdef ASSERT
286 bits |= mask;
287 #endif
288 insn |= value;
289 }
290 };
291
292 #define starti Instruction_aarch64 do_not_use(this); set_current(&do_not_use)
293
294 class PrePost {
295 int _offset;
296 Register _r;
297 public:
298 PrePost(Register reg, int o) : _offset(o), _r(reg) { }
299 int offset() { return _offset; }
300 Register reg() { return _r; }
301 };
302
303 class Pre : public PrePost {
304 public:
305 Pre(Register reg, int o) : PrePost(reg, o) { }
306 };
307 class Post : public PrePost {
308 Register _idx;
309 bool _is_postreg;
310 public:
311 Post(Register reg, int o) : PrePost(reg, o) { _idx = NULL; _is_postreg = false; }
312 Post(Register reg, Register idx) : PrePost(reg, 0) { _idx = idx; _is_postreg = true; }
313 Register idx_reg() { return _idx; }
314 bool is_postreg() {return _is_postreg; }
315 };
316
317 namespace ext
318 {
319 enum operation { uxtb, uxth, uxtw, uxtx, sxtb, sxth, sxtw, sxtx };
320 };
321
322 // Addressing modes
323 class Address {
324 public:
325
326 enum mode { no_mode, base_plus_offset, pre, post, post_reg, pcrel,
327 base_plus_offset_reg, literal };
328
329 // Shift and extend for base reg + reg offset addressing
330 class extend {
331 int _option, _shift;
332 ext::operation _op;
333 public:
334 extend() { }
335 extend(int s, int o, ext::operation op) : _option(o), _shift(s), _op(op) { }
336 int option() const{ return _option; }
337 int shift() const { return _shift; }
338 ext::operation op() const { return _op; }
339 };
340 class uxtw : public extend {
341 public:
342 uxtw(int shift = -1): extend(shift, 0b010, ext::uxtw) { }
343 };
344 class lsl : public extend {
345 public:
346 lsl(int shift = -1): extend(shift, 0b011, ext::uxtx) { }
347 };
348 class sxtw : public extend {
349 public:
350 sxtw(int shift = -1): extend(shift, 0b110, ext::sxtw) { }
351 };
352 class sxtx : public extend {
353 public:
354 sxtx(int shift = -1): extend(shift, 0b111, ext::sxtx) { }
355 };
356
357 private:
358 Register _base;
359 Register _index;
360 int64_t _offset;
361 enum mode _mode;
362 extend _ext;
363
364 RelocationHolder _rspec;
365
366 // Typically we use AddressLiterals we want to use their rval
367 // However in some situations we want the lval (effect address) of
368 // the item. We provide a special factory for making those lvals.
369 bool _is_lval;
370
371 // If the target is far we'll need to load the ea of this to a
372 // register to reach it. Otherwise if near we can do PC-relative
373 // addressing.
374 address _target;
375
376 public:
377 Address()
378 : _mode(no_mode) { }
379 Address(Register r)
380 : _base(r), _index(noreg), _offset(0), _mode(base_plus_offset), _target(0) { }
381 Address(Register r, int o)
382 : _base(r), _index(noreg), _offset(o), _mode(base_plus_offset), _target(0) { }
383 Address(Register r, long o)
384 : _base(r), _index(noreg), _offset(o), _mode(base_plus_offset), _target(0) { }
385 Address(Register r, long long o)
386 : _base(r), _index(noreg), _offset(o), _mode(base_plus_offset), _target(0) { }
387 Address(Register r, unsigned int o)
388 : _base(r), _index(noreg), _offset(o), _mode(base_plus_offset), _target(0) { }
389 Address(Register r, unsigned long o)
390 : _base(r), _index(noreg), _offset(o), _mode(base_plus_offset), _target(0) { }
391 Address(Register r, unsigned long long o)
392 : _base(r), _index(noreg), _offset(o), _mode(base_plus_offset), _target(0) { }
393 #ifdef ASSERT
394 Address(Register r, ByteSize disp)
395 : _base(r), _index(noreg), _offset(in_bytes(disp)), _mode(base_plus_offset), _target(0) { }
396 #endif
397 Address(Register r, Register r1, extend ext = lsl())
398 : _base(r), _index(r1), _offset(0), _mode(base_plus_offset_reg),
399 _ext(ext), _target(0) { }
400 Address(Pre p)
401 : _base(p.reg()), _offset(p.offset()), _mode(pre) { }
402 Address(Post p)
403 : _base(p.reg()), _index(p.idx_reg()), _offset(p.offset()),
404 _mode(p.is_postreg() ? post_reg : post), _target(0) { }
405 Address(address target, RelocationHolder const& rspec)
406 : _mode(literal),
407 _rspec(rspec),
408 _is_lval(false),
409 _target(target) { }
410 Address(address target, relocInfo::relocType rtype = relocInfo::external_word_type);
411 Address(Register base, RegisterOrConstant index, extend ext = lsl())
412 : _base (base),
413 _offset(0), _ext(ext), _target(0) {
414 if (index.is_register()) {
415 _mode = base_plus_offset_reg;
416 _index = index.as_register();
417 } else {
418 guarantee(ext.option() == ext::uxtx, "should be");
419 assert(index.is_constant(), "should be");
420 _mode = base_plus_offset;
421 _offset = index.as_constant() << ext.shift();
422 }
423 }
424
425 Register base() const {
426 guarantee((_mode == base_plus_offset | _mode == base_plus_offset_reg
427 | _mode == post | _mode == post_reg),
428 "wrong mode");
429 return _base;
430 }
431 int64_t offset() const {
432 return _offset;
433 }
434 Register index() const {
435 return _index;
436 }
437 mode getMode() const {
438 return _mode;
439 }
440 bool uses(Register reg) const { return _base == reg || _index == reg; }
441 address target() const { return _target; }
442 const RelocationHolder& rspec() const { return _rspec; }
443
444 void encode(Instruction_aarch64 *i) const {
445 i->f(0b111, 29, 27);
446 i->srf(_base, 5);
447
448 switch(_mode) {
449 case base_plus_offset:
450 {
451 unsigned size = i->get(31, 30);
452 if (i->get(26, 26) && i->get(23, 23)) {
453 // SIMD Q Type - Size = 128 bits
454 assert(size == 0, "bad size");
455 size = 0b100;
456 }
457 unsigned mask = (1 << size) - 1;
458 if (_offset < 0 || _offset & mask)
459 {
460 i->f(0b00, 25, 24);
461 i->f(0, 21), i->f(0b00, 11, 10);
462 i->sf(_offset, 20, 12);
463 } else {
464 i->f(0b01, 25, 24);
465 i->f(_offset >> size, 21, 10);
466 }
467 }
468 break;
469
470 case base_plus_offset_reg:
471 {
472 i->f(0b00, 25, 24);
473 i->f(1, 21);
474 i->rf(_index, 16);
475 i->f(_ext.option(), 15, 13);
476 unsigned size = i->get(31, 30);
477 if (i->get(26, 26) && i->get(23, 23)) {
478 // SIMD Q Type - Size = 128 bits
479 assert(size == 0, "bad size");
480 size = 0b100;
481 }
482 if (size == 0) // It's a byte
483 i->f(_ext.shift() >= 0, 12);
484 else {
485 if (_ext.shift() > 0)
486 assert(_ext.shift() == (int)size, "bad shift");
487 i->f(_ext.shift() > 0, 12);
488 }
489 i->f(0b10, 11, 10);
490 }
491 break;
492
493 case pre:
494 i->f(0b00, 25, 24);
495 i->f(0, 21), i->f(0b11, 11, 10);
496 i->sf(_offset, 20, 12);
497 break;
498
499 case post:
500 i->f(0b00, 25, 24);
501 i->f(0, 21), i->f(0b01, 11, 10);
502 i->sf(_offset, 20, 12);
503 break;
504
505 default:
506 ShouldNotReachHere();
507 }
508 }
509
510 void encode_pair(Instruction_aarch64 *i) const {
511 switch(_mode) {
512 case base_plus_offset:
513 i->f(0b010, 25, 23);
514 break;
515 case pre:
516 i->f(0b011, 25, 23);
517 break;
518 case post:
519 i->f(0b001, 25, 23);
520 break;
521 default:
522 ShouldNotReachHere();
523 }
524
525 unsigned size; // Operand shift in 32-bit words
526
527 if (i->get(26, 26)) { // float
528 switch(i->get(31, 30)) {
529 case 0b10:
530 size = 2; break;
531 case 0b01:
532 size = 1; break;
533 case 0b00:
534 size = 0; break;
535 default:
536 ShouldNotReachHere();
537 size = 0; // unreachable
538 }
539 } else {
540 size = i->get(31, 31);
541 }
542
543 size = 4 << size;
544 guarantee(_offset % size == 0, "bad offset");
545 i->sf(_offset / size, 21, 15);
546 i->srf(_base, 5);
547 }
548
549 void encode_nontemporal_pair(Instruction_aarch64 *i) const {
550 // Only base + offset is allowed
551 i->f(0b000, 25, 23);
552 unsigned size = i->get(31, 31);
553 size = 4 << size;
554 guarantee(_offset % size == 0, "bad offset");
555 i->sf(_offset / size, 21, 15);
556 i->srf(_base, 5);
557 guarantee(_mode == Address::base_plus_offset,
558 "Bad addressing mode for non-temporal op");
559 }
560
561 void lea(MacroAssembler *, Register) const;
562
563 static bool offset_ok_for_immed(int64_t offset, uint shift);
564 };
565
566 // Convience classes
567 class RuntimeAddress: public Address {
568
569 public:
570
571 RuntimeAddress(address target) : Address(target, relocInfo::runtime_call_type) {}
572
573 };
574
575 class OopAddress: public Address {
576
577 public:
578
579 OopAddress(address target) : Address(target, relocInfo::oop_type){}
580
581 };
582
583 class ExternalAddress: public Address {
584 private:
585 static relocInfo::relocType reloc_for_target(address target) {
586 // Sometimes ExternalAddress is used for values which aren't
587 // exactly addresses, like the card table base.
588 // external_word_type can't be used for values in the first page
589 // so just skip the reloc in that case.
590 return external_word_Relocation::can_be_relocated(target) ? relocInfo::external_word_type : relocInfo::none;
591 }
592
593 public:
594
595 ExternalAddress(address target) : Address(target, reloc_for_target(target)) {}
596
597 };
598
599 class InternalAddress: public Address {
600
601 public:
602
603 InternalAddress(address target) : Address(target, relocInfo::internal_word_type) {}
604 };
605
606 const int FPUStateSizeInWords = FloatRegisterImpl::number_of_registers *
607 FloatRegisterImpl::save_slots_per_register;
608
609 typedef enum {
610 PLDL1KEEP = 0b00000, PLDL1STRM, PLDL2KEEP, PLDL2STRM, PLDL3KEEP, PLDL3STRM,
611 PSTL1KEEP = 0b10000, PSTL1STRM, PSTL2KEEP, PSTL2STRM, PSTL3KEEP, PSTL3STRM,
612 PLIL1KEEP = 0b01000, PLIL1STRM, PLIL2KEEP, PLIL2STRM, PLIL3KEEP, PLIL3STRM
613 } prfop;
614
615 class Assembler : public AbstractAssembler {
616
617 #ifndef PRODUCT
618 static const uintptr_t asm_bp;
619
620 void emit_long(jint x) {
621 if ((uintptr_t)pc() == asm_bp)
622 asm volatile ("nop");
623 AbstractAssembler::emit_int32(x);
624 }
625 #else
626 void emit_long(jint x) {
627 AbstractAssembler::emit_int32(x);
628 }
629 #endif
630
631 public:
632
633 enum { instruction_size = 4 };
634
635 //---< calculate length of instruction >---
636 // We just use the values set above.
637 // instruction must start at passed address
638 static unsigned int instr_len(unsigned char *instr) { return instruction_size; }
639
640 //---< longest instructions >---
641 static unsigned int instr_maxlen() { return instruction_size; }
642
643 Address adjust(Register base, int offset, bool preIncrement) {
644 if (preIncrement)
645 return Address(Pre(base, offset));
646 else
647 return Address(Post(base, offset));
648 }
649
650 Address pre(Register base, int offset) {
651 return adjust(base, offset, true);
652 }
653
654 Address post(Register base, int offset) {
655 return adjust(base, offset, false);
656 }
657
658 Address post(Register base, Register idx) {
659 return Address(Post(base, idx));
660 }
661
662 Instruction_aarch64* current;
663
664 void set_current(Instruction_aarch64* i) { current = i; }
665
666 void f(unsigned val, int msb, int lsb) {
667 current->f(val, msb, lsb);
668 }
669 void f(unsigned val, int msb) {
670 current->f(val, msb, msb);
671 }
672 void sf(int64_t val, int msb, int lsb) {
673 current->sf(val, msb, lsb);
674 }
675 void rf(Register reg, int lsb) {
676 current->rf(reg, lsb);
677 }
678 void srf(Register reg, int lsb) {
679 current->srf(reg, lsb);
680 }
681 void zrf(Register reg, int lsb) {
682 current->zrf(reg, lsb);
683 }
684 void rf(FloatRegister reg, int lsb) {
685 current->rf(reg, lsb);
686 }
687 void fixed(unsigned value, unsigned mask) {
688 current->fixed(value, mask);
689 }
690
691 void emit() {
692 emit_long(current->get_insn());
693 assert_cond(current->get_bits() == 0xffffffff);
694 current = NULL;
695 }
696
697 typedef void (Assembler::* uncond_branch_insn)(address dest);
698 typedef void (Assembler::* compare_and_branch_insn)(Register Rt, address dest);
699 typedef void (Assembler::* test_and_branch_insn)(Register Rt, int bitpos, address dest);
700 typedef void (Assembler::* prefetch_insn)(address target, prfop);
701
702 void wrap_label(Label &L, uncond_branch_insn insn);
703 void wrap_label(Register r, Label &L, compare_and_branch_insn insn);
704 void wrap_label(Register r, int bitpos, Label &L, test_and_branch_insn insn);
705 void wrap_label(Label &L, prfop, prefetch_insn insn);
706
707 // PC-rel. addressing
708
709 void adr(Register Rd, address dest);
710 void _adrp(Register Rd, address dest);
711
712 void adr(Register Rd, const Address &dest);
713 void _adrp(Register Rd, const Address &dest);
714
715 void adr(Register Rd, Label &L) {
716 wrap_label(Rd, L, &Assembler::Assembler::adr);
717 }
718 void _adrp(Register Rd, Label &L) {
719 wrap_label(Rd, L, &Assembler::_adrp);
720 }
721
722 void adrp(Register Rd, const Address &dest, uint64_t &offset);
723
724 #undef INSN
725
726 void add_sub_immediate(Register Rd, Register Rn, unsigned uimm, int op,
727 int negated_op);
728
729 // Add/subtract (immediate)
730 #define INSN(NAME, decode, negated) \
731 void NAME(Register Rd, Register Rn, unsigned imm, unsigned shift) { \
732 starti; \
733 f(decode, 31, 29), f(0b10001, 28, 24), f(shift, 23, 22), f(imm, 21, 10); \
734 zrf(Rd, 0), srf(Rn, 5); \
735 } \
736 \
737 void NAME(Register Rd, Register Rn, unsigned imm) { \
738 starti; \
739 add_sub_immediate(Rd, Rn, imm, decode, negated); \
740 }
741
742 INSN(addsw, 0b001, 0b011);
743 INSN(subsw, 0b011, 0b001);
744 INSN(adds, 0b101, 0b111);
745 INSN(subs, 0b111, 0b101);
746
747 #undef INSN
748
749 #define INSN(NAME, decode, negated) \
750 void NAME(Register Rd, Register Rn, unsigned imm) { \
751 starti; \
752 add_sub_immediate(Rd, Rn, imm, decode, negated); \
753 }
754
755 INSN(addw, 0b000, 0b010);
756 INSN(subw, 0b010, 0b000);
757 INSN(add, 0b100, 0b110);
758 INSN(sub, 0b110, 0b100);
759
760 #undef INSN
761
762 // Logical (immediate)
763 #define INSN(NAME, decode, is32) \
764 void NAME(Register Rd, Register Rn, uint64_t imm) { \
765 starti; \
766 uint32_t val = encode_logical_immediate(is32, imm); \
767 f(decode, 31, 29), f(0b100100, 28, 23), f(val, 22, 10); \
768 srf(Rd, 0), zrf(Rn, 5); \
769 }
770
771 INSN(andw, 0b000, true);
772 INSN(orrw, 0b001, true);
773 INSN(eorw, 0b010, true);
774 INSN(andr, 0b100, false);
775 INSN(orr, 0b101, false);
776 INSN(eor, 0b110, false);
777
778 #undef INSN
779
780 #define INSN(NAME, decode, is32) \
781 void NAME(Register Rd, Register Rn, uint64_t imm) { \
782 starti; \
783 uint32_t val = encode_logical_immediate(is32, imm); \
784 f(decode, 31, 29), f(0b100100, 28, 23), f(val, 22, 10); \
785 zrf(Rd, 0), zrf(Rn, 5); \
786 }
787
788 INSN(ands, 0b111, false);
789 INSN(andsw, 0b011, true);
790
791 #undef INSN
792
793 // Move wide (immediate)
794 #define INSN(NAME, opcode) \
795 void NAME(Register Rd, unsigned imm, unsigned shift = 0) { \
796 assert_cond((shift/16)*16 == shift); \
797 starti; \
798 f(opcode, 31, 29), f(0b100101, 28, 23), f(shift/16, 22, 21), \
799 f(imm, 20, 5); \
800 rf(Rd, 0); \
801 }
802
803 INSN(movnw, 0b000);
804 INSN(movzw, 0b010);
805 INSN(movkw, 0b011);
806 INSN(movn, 0b100);
807 INSN(movz, 0b110);
808 INSN(movk, 0b111);
809
810 #undef INSN
811
812 // Bitfield
813 #define INSN(NAME, opcode, size) \
814 void NAME(Register Rd, Register Rn, unsigned immr, unsigned imms) { \
815 starti; \
816 guarantee(size == 1 || (immr < 32 && imms < 32), "incorrect immr/imms");\
817 f(opcode, 31, 22), f(immr, 21, 16), f(imms, 15, 10); \
818 zrf(Rn, 5), rf(Rd, 0); \
819 }
820
821 INSN(sbfmw, 0b0001001100, 0);
822 INSN(bfmw, 0b0011001100, 0);
823 INSN(ubfmw, 0b0101001100, 0);
824 INSN(sbfm, 0b1001001101, 1);
825 INSN(bfm, 0b1011001101, 1);
826 INSN(ubfm, 0b1101001101, 1);
827
828 #undef INSN
829
830 // Extract
831 #define INSN(NAME, opcode, size) \
832 void NAME(Register Rd, Register Rn, Register Rm, unsigned imms) { \
833 starti; \
834 guarantee(size == 1 || imms < 32, "incorrect imms"); \
835 f(opcode, 31, 21), f(imms, 15, 10); \
836 zrf(Rm, 16), zrf(Rn, 5), zrf(Rd, 0); \
837 }
838
839 INSN(extrw, 0b00010011100, 0);
840 INSN(extr, 0b10010011110, 1);
841
842 #undef INSN
843
844 // The maximum range of a branch is fixed for the AArch64
845 // architecture. In debug mode we shrink it in order to test
846 // trampolines, but not so small that branches in the interpreter
847 // are out of range.
848 static const uint64_t branch_range = NOT_DEBUG(128 * M) DEBUG_ONLY(2 * M);
849
850 static bool reachable_from_branch_at(address branch, address target) {
851 return uabs(target - branch) < branch_range;
852 }
853
854 // Unconditional branch (immediate)
855 #define INSN(NAME, opcode) \
856 void NAME(address dest) { \
857 starti; \
858 int64_t offset = (dest - pc()) >> 2; \
859 DEBUG_ONLY(assert(reachable_from_branch_at(pc(), dest), "debug only")); \
860 f(opcode, 31), f(0b00101, 30, 26), sf(offset, 25, 0); \
861 } \
862 void NAME(Label &L) { \
863 wrap_label(L, &Assembler::NAME); \
864 } \
865 void NAME(const Address &dest);
866
867 INSN(b, 0);
868 INSN(bl, 1);
869
870 #undef INSN
871
872 // Compare & branch (immediate)
873 #define INSN(NAME, opcode) \
874 void NAME(Register Rt, address dest) { \
875 int64_t offset = (dest - pc()) >> 2; \
876 starti; \
877 f(opcode, 31, 24), sf(offset, 23, 5), rf(Rt, 0); \
878 } \
879 void NAME(Register Rt, Label &L) { \
880 wrap_label(Rt, L, &Assembler::NAME); \
881 }
882
883 INSN(cbzw, 0b00110100);
884 INSN(cbnzw, 0b00110101);
885 INSN(cbz, 0b10110100);
886 INSN(cbnz, 0b10110101);
887
888 #undef INSN
889
890 // Test & branch (immediate)
891 #define INSN(NAME, opcode) \
892 void NAME(Register Rt, int bitpos, address dest) { \
893 int64_t offset = (dest - pc()) >> 2; \
894 int b5 = bitpos >> 5; \
895 bitpos &= 0x1f; \
896 starti; \
897 f(b5, 31), f(opcode, 30, 24), f(bitpos, 23, 19), sf(offset, 18, 5); \
898 rf(Rt, 0); \
899 } \
900 void NAME(Register Rt, int bitpos, Label &L) { \
901 wrap_label(Rt, bitpos, L, &Assembler::NAME); \
902 }
903
904 INSN(tbz, 0b0110110);
905 INSN(tbnz, 0b0110111);
906
907 #undef INSN
908
909 // Conditional branch (immediate)
910 enum Condition
911 {EQ, NE, HS, CS=HS, LO, CC=LO, MI, PL, VS, VC, HI, LS, GE, LT, GT, LE, AL, NV};
912
913 void br(Condition cond, address dest) {
914 int64_t offset = (dest - pc()) >> 2;
915 starti;
916 f(0b0101010, 31, 25), f(0, 24), sf(offset, 23, 5), f(0, 4), f(cond, 3, 0);
917 }
918
919 #define INSN(NAME, cond) \
920 void NAME(address dest) { \
921 br(cond, dest); \
922 }
923
924 INSN(beq, EQ);
925 INSN(bne, NE);
926 INSN(bhs, HS);
927 INSN(bcs, CS);
928 INSN(blo, LO);
929 INSN(bcc, CC);
930 INSN(bmi, MI);
931 INSN(bpl, PL);
932 INSN(bvs, VS);
933 INSN(bvc, VC);
934 INSN(bhi, HI);
935 INSN(bls, LS);
936 INSN(bge, GE);
937 INSN(blt, LT);
938 INSN(bgt, GT);
939 INSN(ble, LE);
940 INSN(bal, AL);
941 INSN(bnv, NV);
942
943 void br(Condition cc, Label &L);
944
945 #undef INSN
946
947 // Exception generation
948 void generate_exception(int opc, int op2, int LL, unsigned imm) {
949 starti;
950 f(0b11010100, 31, 24);
951 f(opc, 23, 21), f(imm, 20, 5), f(op2, 4, 2), f(LL, 1, 0);
952 }
953
954 #define INSN(NAME, opc, op2, LL) \
955 void NAME(unsigned imm) { \
956 generate_exception(opc, op2, LL, imm); \
957 }
958
959 INSN(svc, 0b000, 0, 0b01);
960 INSN(hvc, 0b000, 0, 0b10);
961 INSN(smc, 0b000, 0, 0b11);
962 INSN(brk, 0b001, 0, 0b00);
963 INSN(hlt, 0b010, 0, 0b00);
964 INSN(dcps1, 0b101, 0, 0b01);
965 INSN(dcps2, 0b101, 0, 0b10);
966 INSN(dcps3, 0b101, 0, 0b11);
967
968 #undef INSN
969
970 // System
971 void system(int op0, int op1, int CRn, int CRm, int op2,
972 Register rt = dummy_reg)
973 {
974 starti;
975 f(0b11010101000, 31, 21);
976 f(op0, 20, 19);
977 f(op1, 18, 16);
978 f(CRn, 15, 12);
979 f(CRm, 11, 8);
980 f(op2, 7, 5);
981 rf(rt, 0);
982 }
983
984 void hint(int imm) {
985 system(0b00, 0b011, 0b0010, 0b0000, imm);
986 }
987
988 void nop() {
989 hint(0);
990 }
991
992 void yield() {
993 hint(1);
994 }
995
996 void wfe() {
997 hint(2);
998 }
999
1000 void wfi() {
1001 hint(3);
1002 }
1003
1004 void sev() {
1005 hint(4);
1006 }
1007
1008 void sevl() {
1009 hint(5);
1010 }
1011
1012 // we only provide mrs and msr for the special purpose system
1013 // registers where op1 (instr[20:19]) == 11 and, (currently) only
1014 // use it for FPSR n.b msr has L (instr[21]) == 0 mrs has L == 1
1015
1016 void msr(int op1, int CRn, int CRm, int op2, Register rt) {
1017 starti;
1018 f(0b1101010100011, 31, 19);
1019 f(op1, 18, 16);
1020 f(CRn, 15, 12);
1021 f(CRm, 11, 8);
1022 f(op2, 7, 5);
1023 // writing zr is ok
1024 zrf(rt, 0);
1025 }
1026
1027 void mrs(int op1, int CRn, int CRm, int op2, Register rt) {
1028 starti;
1029 f(0b1101010100111, 31, 19);
1030 f(op1, 18, 16);
1031 f(CRn, 15, 12);
1032 f(CRm, 11, 8);
1033 f(op2, 7, 5);
1034 // reading to zr is a mistake
1035 rf(rt, 0);
1036 }
1037
1038 enum barrier {OSHLD = 0b0001, OSHST, OSH, NSHLD=0b0101, NSHST, NSH,
1039 ISHLD = 0b1001, ISHST, ISH, LD=0b1101, ST, SY};
1040
1041 void dsb(barrier imm) {
1042 system(0b00, 0b011, 0b00011, imm, 0b100);
1043 }
1044
1045 void dmb(barrier imm) {
1046 system(0b00, 0b011, 0b00011, imm, 0b101);
1047 }
1048
1049 void isb() {
1050 system(0b00, 0b011, 0b00011, SY, 0b110);
1051 }
1052
1053 void sys(int op1, int CRn, int CRm, int op2,
1054 Register rt = (Register)0b11111) {
1055 system(0b01, op1, CRn, CRm, op2, rt);
1056 }
1057
1058 // Only implement operations accessible from EL0 or higher, i.e.,
1059 // op1 CRn CRm op2
1060 // IC IVAU 3 7 5 1
1061 // DC CVAC 3 7 10 1
1062 // DC CVAP 3 7 12 1
1063 // DC CVAU 3 7 11 1
1064 // DC CIVAC 3 7 14 1
1065 // DC ZVA 3 7 4 1
1066 // So only deal with the CRm field.
1067 enum icache_maintenance {IVAU = 0b0101};
1068 enum dcache_maintenance {CVAC = 0b1010, CVAP = 0b1100, CVAU = 0b1011, CIVAC = 0b1110, ZVA = 0b100};
1069
1070 void dc(dcache_maintenance cm, Register Rt) {
1071 sys(0b011, 0b0111, cm, 0b001, Rt);
1072 }
1073
1074 void ic(icache_maintenance cm, Register Rt) {
1075 sys(0b011, 0b0111, cm, 0b001, Rt);
1076 }
1077
1078 // A more convenient access to dmb for our purposes
1079 enum Membar_mask_bits {
1080 // We can use ISH for a barrier because the ARM ARM says "This
1081 // architecture assumes that all Processing Elements that use the
1082 // same operating system or hypervisor are in the same Inner
1083 // Shareable shareability domain."
1084 StoreStore = ISHST,
1085 LoadStore = ISHLD,
1086 LoadLoad = ISHLD,
1087 StoreLoad = ISH,
1088 AnyAny = ISH
1089 };
1090
1091 void membar(Membar_mask_bits order_constraint) {
1092 dmb(Assembler::barrier(order_constraint));
1093 }
1094
1095 // Unconditional branch (register)
1096 void branch_reg(Register R, int opc) {
1097 starti;
1098 f(0b1101011, 31, 25);
1099 f(opc, 24, 21);
1100 f(0b11111000000, 20, 10);
1101 rf(R, 5);
1102 f(0b00000, 4, 0);
1103 }
1104
1105 #define INSN(NAME, opc) \
1106 void NAME(Register R) { \
1107 branch_reg(R, opc); \
1108 }
1109
1110 INSN(br, 0b0000);
1111 INSN(blr, 0b0001);
1112 INSN(ret, 0b0010);
1113
1114 void ret(void *p); // This forces a compile-time error for ret(0)
1115
1116 #undef INSN
1117
1118 #define INSN(NAME, opc) \
1119 void NAME() { \
1120 branch_reg(dummy_reg, opc); \
1121 }
1122
1123 INSN(eret, 0b0100);
1124 INSN(drps, 0b0101);
1125
1126 #undef INSN
1127
1128 // Load/store exclusive
1129 enum operand_size { byte, halfword, word, xword };
1130
1131 void load_store_exclusive(Register Rs, Register Rt1, Register Rt2,
1132 Register Rn, enum operand_size sz, int op, bool ordered) {
1133 starti;
1134 f(sz, 31, 30), f(0b001000, 29, 24), f(op, 23, 21);
1135 rf(Rs, 16), f(ordered, 15), zrf(Rt2, 10), srf(Rn, 5), zrf(Rt1, 0);
1136 }
1137
1138 void load_exclusive(Register dst, Register addr,
1139 enum operand_size sz, bool ordered) {
1140 load_store_exclusive(dummy_reg, dst, dummy_reg, addr,
1141 sz, 0b010, ordered);
1142 }
1143
1144 void store_exclusive(Register status, Register new_val, Register addr,
1145 enum operand_size sz, bool ordered) {
1146 load_store_exclusive(status, new_val, dummy_reg, addr,
1147 sz, 0b000, ordered);
1148 }
1149
1150 #define INSN4(NAME, sz, op, o0) /* Four registers */ \
1151 void NAME(Register Rs, Register Rt1, Register Rt2, Register Rn) { \
1152 guarantee(Rs != Rn && Rs != Rt1 && Rs != Rt2, "unpredictable instruction"); \
1153 load_store_exclusive(Rs, Rt1, Rt2, Rn, sz, op, o0); \
1154 }
1155
1156 #define INSN3(NAME, sz, op, o0) /* Three registers */ \
1157 void NAME(Register Rs, Register Rt, Register Rn) { \
1158 guarantee(Rs != Rn && Rs != Rt, "unpredictable instruction"); \
1159 load_store_exclusive(Rs, Rt, dummy_reg, Rn, sz, op, o0); \
1160 }
1161
1162 #define INSN2(NAME, sz, op, o0) /* Two registers */ \
1163 void NAME(Register Rt, Register Rn) { \
1164 load_store_exclusive(dummy_reg, Rt, dummy_reg, \
1165 Rn, sz, op, o0); \
1166 }
1167
1168 #define INSN_FOO(NAME, sz, op, o0) /* Three registers, encoded differently */ \
1169 void NAME(Register Rt1, Register Rt2, Register Rn) { \
1170 guarantee(Rt1 != Rt2, "unpredictable instruction"); \
1171 load_store_exclusive(dummy_reg, Rt1, Rt2, Rn, sz, op, o0); \
1172 }
1173
1174 // bytes
1175 INSN3(stxrb, byte, 0b000, 0);
1176 INSN3(stlxrb, byte, 0b000, 1);
1177 INSN2(ldxrb, byte, 0b010, 0);
1178 INSN2(ldaxrb, byte, 0b010, 1);
1179 INSN2(stlrb, byte, 0b100, 1);
1180 INSN2(ldarb, byte, 0b110, 1);
1181
1182 // halfwords
1183 INSN3(stxrh, halfword, 0b000, 0);
1184 INSN3(stlxrh, halfword, 0b000, 1);
1185 INSN2(ldxrh, halfword, 0b010, 0);
1186 INSN2(ldaxrh, halfword, 0b010, 1);
1187 INSN2(stlrh, halfword, 0b100, 1);
1188 INSN2(ldarh, halfword, 0b110, 1);
1189
1190 // words
1191 INSN3(stxrw, word, 0b000, 0);
1192 INSN3(stlxrw, word, 0b000, 1);
1193 INSN4(stxpw, word, 0b001, 0);
1194 INSN4(stlxpw, word, 0b001, 1);
1195 INSN2(ldxrw, word, 0b010, 0);
1196 INSN2(ldaxrw, word, 0b010, 1);
1197 INSN_FOO(ldxpw, word, 0b011, 0);
1198 INSN_FOO(ldaxpw, word, 0b011, 1);
1199 INSN2(stlrw, word, 0b100, 1);
1200 INSN2(ldarw, word, 0b110, 1);
1201
1202 // xwords
1203 INSN3(stxr, xword, 0b000, 0);
1204 INSN3(stlxr, xword, 0b000, 1);
1205 INSN4(stxp, xword, 0b001, 0);
1206 INSN4(stlxp, xword, 0b001, 1);
1207 INSN2(ldxr, xword, 0b010, 0);
1208 INSN2(ldaxr, xword, 0b010, 1);
1209 INSN_FOO(ldxp, xword, 0b011, 0);
1210 INSN_FOO(ldaxp, xword, 0b011, 1);
1211 INSN2(stlr, xword, 0b100, 1);
1212 INSN2(ldar, xword, 0b110, 1);
1213
1214 #undef INSN2
1215 #undef INSN3
1216 #undef INSN4
1217 #undef INSN_FOO
1218
1219 // 8.1 Compare and swap extensions
1220 void lse_cas(Register Rs, Register Rt, Register Rn,
1221 enum operand_size sz, bool a, bool r, bool not_pair) {
1222 starti;
1223 if (! not_pair) { // Pair
1224 assert(sz == word || sz == xword, "invalid size");
1225 /* The size bit is in bit 30, not 31 */
1226 sz = (operand_size)(sz == word ? 0b00:0b01);
1227 }
1228 f(sz, 31, 30), f(0b001000, 29, 24), f(not_pair ? 1 : 0, 23), f(a, 22), f(1, 21);
1229 zrf(Rs, 16), f(r, 15), f(0b11111, 14, 10), srf(Rn, 5), zrf(Rt, 0);
1230 }
1231
1232 // CAS
1233 #define INSN(NAME, a, r) \
1234 void NAME(operand_size sz, Register Rs, Register Rt, Register Rn) { \
1235 assert(Rs != Rn && Rs != Rt, "unpredictable instruction"); \
1236 lse_cas(Rs, Rt, Rn, sz, a, r, true); \
1237 }
1238 INSN(cas, false, false)
1239 INSN(casa, true, false)
1240 INSN(casl, false, true)
1241 INSN(casal, true, true)
1242 #undef INSN
1243
1244 // CASP
1245 #define INSN(NAME, a, r) \
1246 void NAME(operand_size sz, Register Rs, Register Rs1, \
1247 Register Rt, Register Rt1, Register Rn) { \
1248 assert((Rs->encoding() & 1) == 0 && (Rt->encoding() & 1) == 0 && \
1249 Rs->successor() == Rs1 && Rt->successor() == Rt1 && \
1250 Rs != Rn && Rs1 != Rn && Rs != Rt, "invalid registers"); \
1251 lse_cas(Rs, Rt, Rn, sz, a, r, false); \
1252 }
1253 INSN(casp, false, false)
1254 INSN(caspa, true, false)
1255 INSN(caspl, false, true)
1256 INSN(caspal, true, true)
1257 #undef INSN
1258
1259 // 8.1 Atomic operations
1260 void lse_atomic(Register Rs, Register Rt, Register Rn,
1261 enum operand_size sz, int op1, int op2, bool a, bool r) {
1262 starti;
1263 f(sz, 31, 30), f(0b111000, 29, 24), f(a, 23), f(r, 22), f(1, 21);
1264 zrf(Rs, 16), f(op1, 15), f(op2, 14, 12), f(0, 11, 10), srf(Rn, 5), zrf(Rt, 0);
1265 }
1266
1267 #define INSN(NAME, NAME_A, NAME_L, NAME_AL, op1, op2) \
1268 void NAME(operand_size sz, Register Rs, Register Rt, Register Rn) { \
1269 lse_atomic(Rs, Rt, Rn, sz, op1, op2, false, false); \
1270 } \
1271 void NAME_A(operand_size sz, Register Rs, Register Rt, Register Rn) { \
1272 lse_atomic(Rs, Rt, Rn, sz, op1, op2, true, false); \
1273 } \
1274 void NAME_L(operand_size sz, Register Rs, Register Rt, Register Rn) { \
1275 lse_atomic(Rs, Rt, Rn, sz, op1, op2, false, true); \
1276 } \
1277 void NAME_AL(operand_size sz, Register Rs, Register Rt, Register Rn) {\
1278 lse_atomic(Rs, Rt, Rn, sz, op1, op2, true, true); \
1279 }
1280 INSN(ldadd, ldadda, ldaddl, ldaddal, 0, 0b000);
1281 INSN(ldbic, ldbica, ldbicl, ldbical, 0, 0b001);
1282 INSN(ldeor, ldeora, ldeorl, ldeoral, 0, 0b010);
1283 INSN(ldorr, ldorra, ldorrl, ldorral, 0, 0b011);
1284 INSN(ldsmax, ldsmaxa, ldsmaxl, ldsmaxal, 0, 0b100);
1285 INSN(ldsmin, ldsmina, ldsminl, ldsminal, 0, 0b101);
1286 INSN(ldumax, ldumaxa, ldumaxl, ldumaxal, 0, 0b110);
1287 INSN(ldumin, ldumina, lduminl, lduminal, 0, 0b111);
1288 INSN(swp, swpa, swpl, swpal, 1, 0b000);
1289 #undef INSN
1290
1291 // Load register (literal)
1292 #define INSN(NAME, opc, V) \
1293 void NAME(Register Rt, address dest) { \
1294 int64_t offset = (dest - pc()) >> 2; \
1295 starti; \
1296 f(opc, 31, 30), f(0b011, 29, 27), f(V, 26), f(0b00, 25, 24), \
1297 sf(offset, 23, 5); \
1298 rf(Rt, 0); \
1299 } \
1300 void NAME(Register Rt, address dest, relocInfo::relocType rtype) { \
1301 InstructionMark im(this); \
1302 guarantee(rtype == relocInfo::internal_word_type, \
1303 "only internal_word_type relocs make sense here"); \
1304 code_section()->relocate(inst_mark(), InternalAddress(dest).rspec()); \
1305 NAME(Rt, dest); \
1306 } \
1307 void NAME(Register Rt, Label &L) { \
1308 wrap_label(Rt, L, &Assembler::NAME); \
1309 }
1310
1311 INSN(ldrw, 0b00, 0);
1312 INSN(ldr, 0b01, 0);
1313 INSN(ldrsw, 0b10, 0);
1314
1315 #undef INSN
1316
1317 #define INSN(NAME, opc, V) \
1318 void NAME(FloatRegister Rt, address dest) { \
1319 int64_t offset = (dest - pc()) >> 2; \
1320 starti; \
1321 f(opc, 31, 30), f(0b011, 29, 27), f(V, 26), f(0b00, 25, 24), \
1322 sf(offset, 23, 5); \
1323 rf((Register)Rt, 0); \
1324 }
1325
1326 INSN(ldrs, 0b00, 1);
1327 INSN(ldrd, 0b01, 1);
1328 INSN(ldrq, 0b10, 1);
1329
1330 #undef INSN
1331
1332 #define INSN(NAME, opc, V) \
1333 void NAME(address dest, prfop op = PLDL1KEEP) { \
1334 int64_t offset = (dest - pc()) >> 2; \
1335 starti; \
1336 f(opc, 31, 30), f(0b011, 29, 27), f(V, 26), f(0b00, 25, 24), \
1337 sf(offset, 23, 5); \
1338 f(op, 4, 0); \
1339 } \
1340 void NAME(Label &L, prfop op = PLDL1KEEP) { \
1341 wrap_label(L, op, &Assembler::NAME); \
1342 }
1343
1344 INSN(prfm, 0b11, 0);
1345
1346 #undef INSN
1347
1348 // Load/store
1349 void ld_st1(int opc, int p1, int V, int L,
1350 Register Rt1, Register Rt2, Address adr, bool no_allocate) {
1351 starti;
1352 f(opc, 31, 30), f(p1, 29, 27), f(V, 26), f(L, 22);
1353 zrf(Rt2, 10), zrf(Rt1, 0);
1354 if (no_allocate) {
1355 adr.encode_nontemporal_pair(current);
1356 } else {
1357 adr.encode_pair(current);
1358 }
1359 }
1360
1361 // Load/store register pair (offset)
1362 #define INSN(NAME, size, p1, V, L, no_allocate) \
1363 void NAME(Register Rt1, Register Rt2, Address adr) { \
1364 ld_st1(size, p1, V, L, Rt1, Rt2, adr, no_allocate); \
1365 }
1366
1367 INSN(stpw, 0b00, 0b101, 0, 0, false);
1368 INSN(ldpw, 0b00, 0b101, 0, 1, false);
1369 INSN(ldpsw, 0b01, 0b101, 0, 1, false);
1370 INSN(stp, 0b10, 0b101, 0, 0, false);
1371 INSN(ldp, 0b10, 0b101, 0, 1, false);
1372
1373 // Load/store no-allocate pair (offset)
1374 INSN(stnpw, 0b00, 0b101, 0, 0, true);
1375 INSN(ldnpw, 0b00, 0b101, 0, 1, true);
1376 INSN(stnp, 0b10, 0b101, 0, 0, true);
1377 INSN(ldnp, 0b10, 0b101, 0, 1, true);
1378
1379 #undef INSN
1380
1381 #define INSN(NAME, size, p1, V, L, no_allocate) \
1382 void NAME(FloatRegister Rt1, FloatRegister Rt2, Address adr) { \
1383 ld_st1(size, p1, V, L, (Register)Rt1, (Register)Rt2, adr, no_allocate); \
1384 }
1385
1386 INSN(stps, 0b00, 0b101, 1, 0, false);
1387 INSN(ldps, 0b00, 0b101, 1, 1, false);
1388 INSN(stpd, 0b01, 0b101, 1, 0, false);
1389 INSN(ldpd, 0b01, 0b101, 1, 1, false);
1390 INSN(stpq, 0b10, 0b101, 1, 0, false);
1391 INSN(ldpq, 0b10, 0b101, 1, 1, false);
1392
1393 #undef INSN
1394
1395 // Load/store register (all modes)
1396 void ld_st2(Register Rt, const Address &adr, int size, int op, int V = 0) {
1397 starti;
1398
1399 f(V, 26); // general reg?
1400 zrf(Rt, 0);
1401
1402 // Encoding for literal loads is done here (rather than pushed
1403 // down into Address::encode) because the encoding of this
1404 // instruction is too different from all of the other forms to
1405 // make it worth sharing.
1406 if (adr.getMode() == Address::literal) {
1407 assert(size == 0b10 || size == 0b11, "bad operand size in ldr");
1408 assert(op == 0b01, "literal form can only be used with loads");
1409 f(size & 0b01, 31, 30), f(0b011, 29, 27), f(0b00, 25, 24);
1410 int64_t offset = (adr.target() - pc()) >> 2;
1411 sf(offset, 23, 5);
1412 code_section()->relocate(pc(), adr.rspec());
1413 return;
1414 }
1415
1416 f(size, 31, 30);
1417 f(op, 23, 22); // str
1418 adr.encode(current);
1419 }
1420
1421 #define INSN(NAME, size, op) \
1422 void NAME(Register Rt, const Address &adr) { \
1423 ld_st2(Rt, adr, size, op); \
1424 } \
1425
1426 INSN(str, 0b11, 0b00);
1427 INSN(strw, 0b10, 0b00);
1428 INSN(strb, 0b00, 0b00);
1429 INSN(strh, 0b01, 0b00);
1430
1431 INSN(ldr, 0b11, 0b01);
1432 INSN(ldrw, 0b10, 0b01);
1433 INSN(ldrb, 0b00, 0b01);
1434 INSN(ldrh, 0b01, 0b01);
1435
1436 INSN(ldrsb, 0b00, 0b10);
1437 INSN(ldrsbw, 0b00, 0b11);
1438 INSN(ldrsh, 0b01, 0b10);
1439 INSN(ldrshw, 0b01, 0b11);
1440 INSN(ldrsw, 0b10, 0b10);
1441
1442 #undef INSN
1443
1444 #define INSN(NAME, size, op) \
1445 void NAME(const Address &adr, prfop pfop = PLDL1KEEP) { \
1446 ld_st2((Register)pfop, adr, size, op); \
1447 }
1448
1449 INSN(prfm, 0b11, 0b10); // FIXME: PRFM should not be used with
1450 // writeback modes, but the assembler
1451 // doesn't enfore that.
1452
1453 #undef INSN
1454
1455 #define INSN(NAME, size, op) \
1456 void NAME(FloatRegister Rt, const Address &adr) { \
1457 ld_st2((Register)Rt, adr, size, op, 1); \
1458 }
1459
1460 INSN(strd, 0b11, 0b00);
1461 INSN(strs, 0b10, 0b00);
1462 INSN(ldrd, 0b11, 0b01);
1463 INSN(ldrs, 0b10, 0b01);
1464 INSN(strq, 0b00, 0b10);
1465 INSN(ldrq, 0x00, 0b11);
1466
1467 #undef INSN
1468
1469 enum shift_kind { LSL, LSR, ASR, ROR };
1470
1471 void op_shifted_reg(unsigned decode,
1472 enum shift_kind kind, unsigned shift,
1473 unsigned size, unsigned op) {
1474 f(size, 31);
1475 f(op, 30, 29);
1476 f(decode, 28, 24);
1477 f(shift, 15, 10);
1478 f(kind, 23, 22);
1479 }
1480
1481 // Logical (shifted register)
1482 #define INSN(NAME, size, op, N) \
1483 void NAME(Register Rd, Register Rn, Register Rm, \
1484 enum shift_kind kind = LSL, unsigned shift = 0) { \
1485 starti; \
1486 guarantee(size == 1 || shift < 32, "incorrect shift"); \
1487 f(N, 21); \
1488 zrf(Rm, 16), zrf(Rn, 5), zrf(Rd, 0); \
1489 op_shifted_reg(0b01010, kind, shift, size, op); \
1490 }
1491
1492 INSN(andr, 1, 0b00, 0);
1493 INSN(orr, 1, 0b01, 0);
1494 INSN(eor, 1, 0b10, 0);
1495 INSN(ands, 1, 0b11, 0);
1496 INSN(andw, 0, 0b00, 0);
1497 INSN(orrw, 0, 0b01, 0);
1498 INSN(eorw, 0, 0b10, 0);
1499 INSN(andsw, 0, 0b11, 0);
1500
1501 #undef INSN
1502
1503 #define INSN(NAME, size, op, N) \
1504 void NAME(Register Rd, Register Rn, Register Rm, \
1505 enum shift_kind kind = LSL, unsigned shift = 0) { \
1506 starti; \
1507 f(N, 21); \
1508 zrf(Rm, 16), zrf(Rn, 5), zrf(Rd, 0); \
1509 op_shifted_reg(0b01010, kind, shift, size, op); \
1510 } \
1511 \
1512 /* These instructions have no immediate form. Provide an overload so \
1513 that if anyone does try to use an immediate operand -- this has \
1514 happened! -- we'll get a compile-time error. */ \
1515 void NAME(Register Rd, Register Rn, unsigned imm, \
1516 enum shift_kind kind = LSL, unsigned shift = 0) { \
1517 assert(false, " can't be used with immediate operand"); \
1518 }
1519
1520 INSN(bic, 1, 0b00, 1);
1521 INSN(orn, 1, 0b01, 1);
1522 INSN(eon, 1, 0b10, 1);
1523 INSN(bics, 1, 0b11, 1);
1524 INSN(bicw, 0, 0b00, 1);
1525 INSN(ornw, 0, 0b01, 1);
1526 INSN(eonw, 0, 0b10, 1);
1527 INSN(bicsw, 0, 0b11, 1);
1528
1529 #undef INSN
1530
1531 // Aliases for short forms of orn
1532 void mvn(Register Rd, Register Rm,
1533 enum shift_kind kind = LSL, unsigned shift = 0) {
1534 orn(Rd, zr, Rm, kind, shift);
1535 }
1536
1537 void mvnw(Register Rd, Register Rm,
1538 enum shift_kind kind = LSL, unsigned shift = 0) {
1539 ornw(Rd, zr, Rm, kind, shift);
1540 }
1541
1542 // Add/subtract (shifted register)
1543 #define INSN(NAME, size, op) \
1544 void NAME(Register Rd, Register Rn, Register Rm, \
1545 enum shift_kind kind, unsigned shift = 0) { \
1546 starti; \
1547 f(0, 21); \
1548 assert_cond(kind != ROR); \
1549 guarantee(size == 1 || shift < 32, "incorrect shift");\
1550 zrf(Rd, 0), zrf(Rn, 5), zrf(Rm, 16); \
1551 op_shifted_reg(0b01011, kind, shift, size, op); \
1552 }
1553
1554 INSN(add, 1, 0b000);
1555 INSN(sub, 1, 0b10);
1556 INSN(addw, 0, 0b000);
1557 INSN(subw, 0, 0b10);
1558
1559 INSN(adds, 1, 0b001);
1560 INSN(subs, 1, 0b11);
1561 INSN(addsw, 0, 0b001);
1562 INSN(subsw, 0, 0b11);
1563
1564 #undef INSN
1565
1566 // Add/subtract (extended register)
1567 #define INSN(NAME, op) \
1568 void NAME(Register Rd, Register Rn, Register Rm, \
1569 ext::operation option, int amount = 0) { \
1570 starti; \
1571 zrf(Rm, 16), srf(Rn, 5), srf(Rd, 0); \
1572 add_sub_extended_reg(op, 0b01011, Rd, Rn, Rm, 0b00, option, amount); \
1573 }
1574
1575 void add_sub_extended_reg(unsigned op, unsigned decode,
1576 Register Rd, Register Rn, Register Rm,
1577 unsigned opt, ext::operation option, unsigned imm) {
1578 guarantee(imm <= 4, "shift amount must be <= 4");
1579 f(op, 31, 29), f(decode, 28, 24), f(opt, 23, 22), f(1, 21);
1580 f(option, 15, 13), f(imm, 12, 10);
1581 }
1582
1583 INSN(addw, 0b000);
1584 INSN(subw, 0b010);
1585 INSN(add, 0b100);
1586 INSN(sub, 0b110);
1587
1588 #undef INSN
1589
1590 #define INSN(NAME, op) \
1591 void NAME(Register Rd, Register Rn, Register Rm, \
1592 ext::operation option, int amount = 0) { \
1593 starti; \
1594 zrf(Rm, 16), srf(Rn, 5), zrf(Rd, 0); \
1595 add_sub_extended_reg(op, 0b01011, Rd, Rn, Rm, 0b00, option, amount); \
1596 }
1597
1598 INSN(addsw, 0b001);
1599 INSN(subsw, 0b011);
1600 INSN(adds, 0b101);
1601 INSN(subs, 0b111);
1602
1603 #undef INSN
1604
1605 // Aliases for short forms of add and sub
1606 #define INSN(NAME) \
1607 void NAME(Register Rd, Register Rn, Register Rm) { \
1608 if (Rd == sp || Rn == sp) \
1609 NAME(Rd, Rn, Rm, ext::uxtx); \
1610 else \
1611 NAME(Rd, Rn, Rm, LSL); \
1612 }
1613
1614 INSN(addw);
1615 INSN(subw);
1616 INSN(add);
1617 INSN(sub);
1618
1619 INSN(addsw);
1620 INSN(subsw);
1621 INSN(adds);
1622 INSN(subs);
1623
1624 #undef INSN
1625
1626 // Add/subtract (with carry)
1627 void add_sub_carry(unsigned op, Register Rd, Register Rn, Register Rm) {
1628 starti;
1629 f(op, 31, 29);
1630 f(0b11010000, 28, 21);
1631 f(0b000000, 15, 10);
1632 zrf(Rm, 16), zrf(Rn, 5), zrf(Rd, 0);
1633 }
1634
1635 #define INSN(NAME, op) \
1636 void NAME(Register Rd, Register Rn, Register Rm) { \
1637 add_sub_carry(op, Rd, Rn, Rm); \
1638 }
1639
1640 INSN(adcw, 0b000);
1641 INSN(adcsw, 0b001);
1642 INSN(sbcw, 0b010);
1643 INSN(sbcsw, 0b011);
1644 INSN(adc, 0b100);
1645 INSN(adcs, 0b101);
1646 INSN(sbc,0b110);
1647 INSN(sbcs, 0b111);
1648
1649 #undef INSN
1650
1651 // Conditional compare (both kinds)
1652 void conditional_compare(unsigned op, int o1, int o2, int o3,
1653 Register Rn, unsigned imm5, unsigned nzcv,
1654 unsigned cond) {
1655 starti;
1656 f(op, 31, 29);
1657 f(0b11010010, 28, 21);
1658 f(cond, 15, 12);
1659 f(o1, 11);
1660 f(o2, 10);
1661 f(o3, 4);
1662 f(nzcv, 3, 0);
1663 f(imm5, 20, 16), zrf(Rn, 5);
1664 }
1665
1666 #define INSN(NAME, op) \
1667 void NAME(Register Rn, Register Rm, int imm, Condition cond) { \
1668 int regNumber = (Rm == zr ? 31 : (uintptr_t)Rm); \
1669 conditional_compare(op, 0, 0, 0, Rn, regNumber, imm, cond); \
1670 } \
1671 \
1672 void NAME(Register Rn, int imm5, int imm, Condition cond) { \
1673 conditional_compare(op, 1, 0, 0, Rn, imm5, imm, cond); \
1674 }
1675
1676 INSN(ccmnw, 0b001);
1677 INSN(ccmpw, 0b011);
1678 INSN(ccmn, 0b101);
1679 INSN(ccmp, 0b111);
1680
1681 #undef INSN
1682
1683 // Conditional select
1684 void conditional_select(unsigned op, unsigned op2,
1685 Register Rd, Register Rn, Register Rm,
1686 unsigned cond) {
1687 starti;
1688 f(op, 31, 29);
1689 f(0b11010100, 28, 21);
1690 f(cond, 15, 12);
1691 f(op2, 11, 10);
1692 zrf(Rm, 16), zrf(Rn, 5), rf(Rd, 0);
1693 }
1694
1695 #define INSN(NAME, op, op2) \
1696 void NAME(Register Rd, Register Rn, Register Rm, Condition cond) { \
1697 conditional_select(op, op2, Rd, Rn, Rm, cond); \
1698 }
1699
1700 INSN(cselw, 0b000, 0b00);
1701 INSN(csincw, 0b000, 0b01);
1702 INSN(csinvw, 0b010, 0b00);
1703 INSN(csnegw, 0b010, 0b01);
1704 INSN(csel, 0b100, 0b00);
1705 INSN(csinc, 0b100, 0b01);
1706 INSN(csinv, 0b110, 0b00);
1707 INSN(csneg, 0b110, 0b01);
1708
1709 #undef INSN
1710
1711 // Data processing
1712 void data_processing(unsigned op29, unsigned opcode,
1713 Register Rd, Register Rn) {
1714 f(op29, 31, 29), f(0b11010110, 28, 21);
1715 f(opcode, 15, 10);
1716 rf(Rn, 5), rf(Rd, 0);
1717 }
1718
1719 // (1 source)
1720 #define INSN(NAME, op29, opcode2, opcode) \
1721 void NAME(Register Rd, Register Rn) { \
1722 starti; \
1723 f(opcode2, 20, 16); \
1724 data_processing(op29, opcode, Rd, Rn); \
1725 }
1726
1727 INSN(rbitw, 0b010, 0b00000, 0b00000);
1728 INSN(rev16w, 0b010, 0b00000, 0b00001);
1729 INSN(revw, 0b010, 0b00000, 0b00010);
1730 INSN(clzw, 0b010, 0b00000, 0b00100);
1731 INSN(clsw, 0b010, 0b00000, 0b00101);
1732
1733 INSN(rbit, 0b110, 0b00000, 0b00000);
1734 INSN(rev16, 0b110, 0b00000, 0b00001);
1735 INSN(rev32, 0b110, 0b00000, 0b00010);
1736 INSN(rev, 0b110, 0b00000, 0b00011);
1737 INSN(clz, 0b110, 0b00000, 0b00100);
1738 INSN(cls, 0b110, 0b00000, 0b00101);
1739
1740 #undef INSN
1741
1742 // (2 sources)
1743 #define INSN(NAME, op29, opcode) \
1744 void NAME(Register Rd, Register Rn, Register Rm) { \
1745 starti; \
1746 rf(Rm, 16); \
1747 data_processing(op29, opcode, Rd, Rn); \
1748 }
1749
1750 INSN(udivw, 0b000, 0b000010);
1751 INSN(sdivw, 0b000, 0b000011);
1752 INSN(lslvw, 0b000, 0b001000);
1753 INSN(lsrvw, 0b000, 0b001001);
1754 INSN(asrvw, 0b000, 0b001010);
1755 INSN(rorvw, 0b000, 0b001011);
1756
1757 INSN(udiv, 0b100, 0b000010);
1758 INSN(sdiv, 0b100, 0b000011);
1759 INSN(lslv, 0b100, 0b001000);
1760 INSN(lsrv, 0b100, 0b001001);
1761 INSN(asrv, 0b100, 0b001010);
1762 INSN(rorv, 0b100, 0b001011);
1763
1764 #undef INSN
1765
1766 // (3 sources)
1767 void data_processing(unsigned op54, unsigned op31, unsigned o0,
1768 Register Rd, Register Rn, Register Rm,
1769 Register Ra) {
1770 starti;
1771 f(op54, 31, 29), f(0b11011, 28, 24);
1772 f(op31, 23, 21), f(o0, 15);
1773 zrf(Rm, 16), zrf(Ra, 10), zrf(Rn, 5), zrf(Rd, 0);
1774 }
1775
1776 #define INSN(NAME, op54, op31, o0) \
1777 void NAME(Register Rd, Register Rn, Register Rm, Register Ra) { \
1778 data_processing(op54, op31, o0, Rd, Rn, Rm, Ra); \
1779 }
1780
1781 INSN(maddw, 0b000, 0b000, 0);
1782 INSN(msubw, 0b000, 0b000, 1);
1783 INSN(madd, 0b100, 0b000, 0);
1784 INSN(msub, 0b100, 0b000, 1);
1785 INSN(smaddl, 0b100, 0b001, 0);
1786 INSN(smsubl, 0b100, 0b001, 1);
1787 INSN(umaddl, 0b100, 0b101, 0);
1788 INSN(umsubl, 0b100, 0b101, 1);
1789
1790 #undef INSN
1791
1792 #define INSN(NAME, op54, op31, o0) \
1793 void NAME(Register Rd, Register Rn, Register Rm) { \
1794 data_processing(op54, op31, o0, Rd, Rn, Rm, (Register)31); \
1795 }
1796
1797 INSN(smulh, 0b100, 0b010, 0);
1798 INSN(umulh, 0b100, 0b110, 0);
1799
1800 #undef INSN
1801
1802 // Floating-point data-processing (1 source)
1803 void data_processing(unsigned op31, unsigned type, unsigned opcode,
1804 FloatRegister Vd, FloatRegister Vn) {
1805 starti;
1806 f(op31, 31, 29);
1807 f(0b11110, 28, 24);
1808 f(type, 23, 22), f(1, 21), f(opcode, 20, 15), f(0b10000, 14, 10);
1809 rf(Vn, 5), rf(Vd, 0);
1810 }
1811
1812 #define INSN(NAME, op31, type, opcode) \
1813 void NAME(FloatRegister Vd, FloatRegister Vn) { \
1814 data_processing(op31, type, opcode, Vd, Vn); \
1815 }
1816
1817 private:
1818 INSN(i_fmovs, 0b000, 0b00, 0b000000);
1819 public:
1820 INSN(fabss, 0b000, 0b00, 0b000001);
1821 INSN(fnegs, 0b000, 0b00, 0b000010);
1822 INSN(fsqrts, 0b000, 0b00, 0b000011);
1823 INSN(fcvts, 0b000, 0b00, 0b000101); // Single-precision to double-precision
1824
1825 private:
1826 INSN(i_fmovd, 0b000, 0b01, 0b000000);
1827 public:
1828 INSN(fabsd, 0b000, 0b01, 0b000001);
1829 INSN(fnegd, 0b000, 0b01, 0b000010);
1830 INSN(fsqrtd, 0b000, 0b01, 0b000011);
1831 INSN(fcvtd, 0b000, 0b01, 0b000100); // Double-precision to single-precision
1832
1833 void fmovd(FloatRegister Vd, FloatRegister Vn) {
1834 assert(Vd != Vn, "should be");
1835 i_fmovd(Vd, Vn);
1836 }
1837
1838 void fmovs(FloatRegister Vd, FloatRegister Vn) {
1839 assert(Vd != Vn, "should be");
1840 i_fmovs(Vd, Vn);
1841 }
1842
1843 #undef INSN
1844
1845 // Floating-point data-processing (2 source)
1846 void data_processing(unsigned op31, unsigned type, unsigned opcode,
1847 FloatRegister Vd, FloatRegister Vn, FloatRegister Vm) {
1848 starti;
1849 f(op31, 31, 29);
1850 f(0b11110, 28, 24);
1851 f(type, 23, 22), f(1, 21), f(opcode, 15, 12), f(0b10, 11, 10);
1852 rf(Vm, 16), rf(Vn, 5), rf(Vd, 0);
1853 }
1854
1855 #define INSN(NAME, op31, type, opcode) \
1856 void NAME(FloatRegister Vd, FloatRegister Vn, FloatRegister Vm) { \
1857 data_processing(op31, type, opcode, Vd, Vn, Vm); \
1858 }
1859
1860 INSN(fmuls, 0b000, 0b00, 0b0000);
1861 INSN(fdivs, 0b000, 0b00, 0b0001);
1862 INSN(fadds, 0b000, 0b00, 0b0010);
1863 INSN(fsubs, 0b000, 0b00, 0b0011);
1864 INSN(fmaxs, 0b000, 0b00, 0b0100);
1865 INSN(fmins, 0b000, 0b00, 0b0101);
1866 INSN(fnmuls, 0b000, 0b00, 0b1000);
1867
1868 INSN(fmuld, 0b000, 0b01, 0b0000);
1869 INSN(fdivd, 0b000, 0b01, 0b0001);
1870 INSN(faddd, 0b000, 0b01, 0b0010);
1871 INSN(fsubd, 0b000, 0b01, 0b0011);
1872 INSN(fmaxd, 0b000, 0b01, 0b0100);
1873 INSN(fmind, 0b000, 0b01, 0b0101);
1874 INSN(fnmuld, 0b000, 0b01, 0b1000);
1875
1876 #undef INSN
1877
1878 // Floating-point data-processing (3 source)
1879 void data_processing(unsigned op31, unsigned type, unsigned o1, unsigned o0,
1880 FloatRegister Vd, FloatRegister Vn, FloatRegister Vm,
1881 FloatRegister Va) {
1882 starti;
1883 f(op31, 31, 29);
1884 f(0b11111, 28, 24);
1885 f(type, 23, 22), f(o1, 21), f(o0, 15);
1886 rf(Vm, 16), rf(Va, 10), rf(Vn, 5), rf(Vd, 0);
1887 }
1888
1889 #define INSN(NAME, op31, type, o1, o0) \
1890 void NAME(FloatRegister Vd, FloatRegister Vn, FloatRegister Vm, \
1891 FloatRegister Va) { \
1892 data_processing(op31, type, o1, o0, Vd, Vn, Vm, Va); \
1893 }
1894
1895 INSN(fmadds, 0b000, 0b00, 0, 0);
1896 INSN(fmsubs, 0b000, 0b00, 0, 1);
1897 INSN(fnmadds, 0b000, 0b00, 1, 0);
1898 INSN(fnmsubs, 0b000, 0b00, 1, 1);
1899
1900 INSN(fmaddd, 0b000, 0b01, 0, 0);
1901 INSN(fmsubd, 0b000, 0b01, 0, 1);
1902 INSN(fnmaddd, 0b000, 0b01, 1, 0);
1903 INSN(fnmsub, 0b000, 0b01, 1, 1);
1904
1905 #undef INSN
1906
1907 // Floating-point conditional select
1908 void fp_conditional_select(unsigned op31, unsigned type,
1909 unsigned op1, unsigned op2,
1910 Condition cond, FloatRegister Vd,
1911 FloatRegister Vn, FloatRegister Vm) {
1912 starti;
1913 f(op31, 31, 29);
1914 f(0b11110, 28, 24);
1915 f(type, 23, 22);
1916 f(op1, 21, 21);
1917 f(op2, 11, 10);
1918 f(cond, 15, 12);
1919 rf(Vm, 16), rf(Vn, 5), rf(Vd, 0);
1920 }
1921
1922 #define INSN(NAME, op31, type, op1, op2) \
1923 void NAME(FloatRegister Vd, FloatRegister Vn, \
1924 FloatRegister Vm, Condition cond) { \
1925 fp_conditional_select(op31, type, op1, op2, cond, Vd, Vn, Vm); \
1926 }
1927
1928 INSN(fcsels, 0b000, 0b00, 0b1, 0b11);
1929 INSN(fcseld, 0b000, 0b01, 0b1, 0b11);
1930
1931 #undef INSN
1932
1933 // Floating-point<->integer conversions
1934 void float_int_convert(unsigned op31, unsigned type,
1935 unsigned rmode, unsigned opcode,
1936 Register Rd, Register Rn) {
1937 starti;
1938 f(op31, 31, 29);
1939 f(0b11110, 28, 24);
1940 f(type, 23, 22), f(1, 21), f(rmode, 20, 19);
1941 f(opcode, 18, 16), f(0b000000, 15, 10);
1942 zrf(Rn, 5), zrf(Rd, 0);
1943 }
1944
1945 #define INSN(NAME, op31, type, rmode, opcode) \
1946 void NAME(Register Rd, FloatRegister Vn) { \
1947 float_int_convert(op31, type, rmode, opcode, Rd, (Register)Vn); \
1948 }
1949
1950 INSN(fcvtzsw, 0b000, 0b00, 0b11, 0b000);
1951 INSN(fcvtzs, 0b100, 0b00, 0b11, 0b000);
1952 INSN(fcvtzdw, 0b000, 0b01, 0b11, 0b000);
1953 INSN(fcvtzd, 0b100, 0b01, 0b11, 0b000);
1954
1955 INSN(fmovs, 0b000, 0b00, 0b00, 0b110);
1956 INSN(fmovd, 0b100, 0b01, 0b00, 0b110);
1957
1958 // INSN(fmovhid, 0b100, 0b10, 0b01, 0b110);
1959
1960 #undef INSN
1961
1962 #define INSN(NAME, op31, type, rmode, opcode) \
1963 void NAME(FloatRegister Vd, Register Rn) { \
1964 float_int_convert(op31, type, rmode, opcode, (Register)Vd, Rn); \
1965 }
1966
1967 INSN(fmovs, 0b000, 0b00, 0b00, 0b111);
1968 INSN(fmovd, 0b100, 0b01, 0b00, 0b111);
1969
1970 INSN(scvtfws, 0b000, 0b00, 0b00, 0b010);
1971 INSN(scvtfs, 0b100, 0b00, 0b00, 0b010);
1972 INSN(scvtfwd, 0b000, 0b01, 0b00, 0b010);
1973 INSN(scvtfd, 0b100, 0b01, 0b00, 0b010);
1974
1975 // INSN(fmovhid, 0b100, 0b10, 0b01, 0b111);
1976
1977 #undef INSN
1978
1979 // Floating-point compare
1980 void float_compare(unsigned op31, unsigned type,
1981 unsigned op, unsigned op2,
1982 FloatRegister Vn, FloatRegister Vm = (FloatRegister)0) {
1983 starti;
1984 f(op31, 31, 29);
1985 f(0b11110, 28, 24);
1986 f(type, 23, 22), f(1, 21);
1987 f(op, 15, 14), f(0b1000, 13, 10), f(op2, 4, 0);
1988 rf(Vn, 5), rf(Vm, 16);
1989 }
1990
1991
1992 #define INSN(NAME, op31, type, op, op2) \
1993 void NAME(FloatRegister Vn, FloatRegister Vm) { \
1994 float_compare(op31, type, op, op2, Vn, Vm); \
1995 }
1996
1997 #define INSN1(NAME, op31, type, op, op2) \
1998 void NAME(FloatRegister Vn, double d) { \
1999 assert_cond(d == 0.0); \
2000 float_compare(op31, type, op, op2, Vn); \
2001 }
2002
2003 INSN(fcmps, 0b000, 0b00, 0b00, 0b00000);
2004 INSN1(fcmps, 0b000, 0b00, 0b00, 0b01000);
2005 // INSN(fcmpes, 0b000, 0b00, 0b00, 0b10000);
2006 // INSN1(fcmpes, 0b000, 0b00, 0b00, 0b11000);
2007
2008 INSN(fcmpd, 0b000, 0b01, 0b00, 0b00000);
2009 INSN1(fcmpd, 0b000, 0b01, 0b00, 0b01000);
2010 // INSN(fcmped, 0b000, 0b01, 0b00, 0b10000);
2011 // INSN1(fcmped, 0b000, 0b01, 0b00, 0b11000);
2012
2013 #undef INSN
2014 #undef INSN1
2015
2016 // Floating-point Move (immediate)
2017 private:
2018 unsigned pack(double value);
2019
2020 void fmov_imm(FloatRegister Vn, double value, unsigned size) {
2021 starti;
2022 f(0b00011110, 31, 24), f(size, 23, 22), f(1, 21);
2023 f(pack(value), 20, 13), f(0b10000000, 12, 5);
2024 rf(Vn, 0);
2025 }
2026
2027 public:
2028
2029 void fmovs(FloatRegister Vn, double value) {
2030 if (value)
2031 fmov_imm(Vn, value, 0b00);
2032 else
2033 fmovs(Vn, zr);
2034 }
2035 void fmovd(FloatRegister Vn, double value) {
2036 if (value)
2037 fmov_imm(Vn, value, 0b01);
2038 else
2039 fmovd(Vn, zr);
2040 }
2041
2042 // Floating-point rounding
2043 // type: half-precision = 11
2044 // single = 00
2045 // double = 01
2046 // rmode: A = Away = 100
2047 // I = current = 111
2048 // M = MinusInf = 010
2049 // N = eveN = 000
2050 // P = PlusInf = 001
2051 // X = eXact = 110
2052 // Z = Zero = 011
2053 void float_round(unsigned type, unsigned rmode, FloatRegister Rd, FloatRegister Rn) {
2054 starti;
2055 f(0b00011110, 31, 24);
2056 f(type, 23, 22);
2057 f(0b1001, 21, 18);
2058 f(rmode, 17, 15);
2059 f(0b10000, 14, 10);
2060 rf(Rn, 5), rf(Rd, 0);
2061 }
2062 #define INSN(NAME, type, rmode) \
2063 void NAME(FloatRegister Vd, FloatRegister Vn) { \
2064 float_round(type, rmode, Vd, Vn); \
2065 }
2066
2067 public:
2068 INSN(frintah, 0b11, 0b100);
2069 INSN(frintih, 0b11, 0b111);
2070 INSN(frintmh, 0b11, 0b010);
2071 INSN(frintnh, 0b11, 0b000);
2072 INSN(frintph, 0b11, 0b001);
2073 INSN(frintxh, 0b11, 0b110);
2074 INSN(frintzh, 0b11, 0b011);
2075
2076 INSN(frintas, 0b00, 0b100);
2077 INSN(frintis, 0b00, 0b111);
2078 INSN(frintms, 0b00, 0b010);
2079 INSN(frintns, 0b00, 0b000);
2080 INSN(frintps, 0b00, 0b001);
2081 INSN(frintxs, 0b00, 0b110);
2082 INSN(frintzs, 0b00, 0b011);
2083
2084 INSN(frintad, 0b01, 0b100);
2085 INSN(frintid, 0b01, 0b111);
2086 INSN(frintmd, 0b01, 0b010);
2087 INSN(frintnd, 0b01, 0b000);
2088 INSN(frintpd, 0b01, 0b001);
2089 INSN(frintxd, 0b01, 0b110);
2090 INSN(frintzd, 0b01, 0b011);
2091 #undef INSN
2092
2093 /* SIMD extensions
2094 *
2095 * We just use FloatRegister in the following. They are exactly the same
2096 * as SIMD registers.
2097 */
2098 public:
2099
2100 enum SIMD_Arrangement {
2101 T8B, T16B, T4H, T8H, T2S, T4S, T1D, T2D, T1Q
2102 };
2103
2104 enum SIMD_RegVariant {
2105 B, H, S, D, Q
2106 };
2107
2108 private:
2109 static short SIMD_Size_in_bytes[];
2110
2111 public:
2112 #define INSN(NAME, op) \
2113 void NAME(FloatRegister Rt, SIMD_RegVariant T, const Address &adr) { \
2114 ld_st2((Register)Rt, adr, (int)T & 3, op + ((T==Q) ? 0b10:0b00), 1); \
2115 } \
2116
2117 INSN(ldr, 1);
2118 INSN(str, 0);
2119
2120 #undef INSN
2121
2122 private:
2123
2124 void ld_st(FloatRegister Vt, SIMD_Arrangement T, Register Xn, int op1, int op2) {
2125 starti;
2126 f(0,31), f((int)T & 1, 30);
2127 f(op1, 29, 21), f(0, 20, 16), f(op2, 15, 12);
2128 f((int)T >> 1, 11, 10), srf(Xn, 5), rf(Vt, 0);
2129 }
2130 void ld_st(FloatRegister Vt, SIMD_Arrangement T, Register Xn,
2131 int imm, int op1, int op2, int regs) {
2132
2133 bool replicate = op2 >> 2 == 3;
2134 // post-index value (imm) is formed differently for replicate/non-replicate ld* instructions
2135 int expectedImmediate = replicate ? regs * (1 << (T >> 1)) : SIMD_Size_in_bytes[T] * regs;
2136 guarantee(T < T1Q , "incorrect arrangement");
2137 guarantee(imm == expectedImmediate, "bad offset");
2138 starti;
2139 f(0,31), f((int)T & 1, 30);
2140 f(op1 | 0b100, 29, 21), f(0b11111, 20, 16), f(op2, 15, 12);
2141 f((int)T >> 1, 11, 10), srf(Xn, 5), rf(Vt, 0);
2142 }
2143 void ld_st(FloatRegister Vt, SIMD_Arrangement T, Register Xn,
2144 Register Xm, int op1, int op2) {
2145 starti;
2146 f(0,31), f((int)T & 1, 30);
2147 f(op1 | 0b100, 29, 21), rf(Xm, 16), f(op2, 15, 12);
2148 f((int)T >> 1, 11, 10), srf(Xn, 5), rf(Vt, 0);
2149 }
2150
2151 void ld_st(FloatRegister Vt, SIMD_Arrangement T, Address a, int op1, int op2, int regs) {
2152 switch (a.getMode()) {
2153 case Address::base_plus_offset:
2154 guarantee(a.offset() == 0, "no offset allowed here");
2155 ld_st(Vt, T, a.base(), op1, op2);
2156 break;
2157 case Address::post:
2158 ld_st(Vt, T, a.base(), a.offset(), op1, op2, regs);
2159 break;
2160 case Address::post_reg:
2161 ld_st(Vt, T, a.base(), a.index(), op1, op2);
2162 break;
2163 default:
2164 ShouldNotReachHere();
2165 }
2166 }
2167
2168 public:
2169
2170 #define INSN1(NAME, op1, op2) \
2171 void NAME(FloatRegister Vt, SIMD_Arrangement T, const Address &a) { \
2172 ld_st(Vt, T, a, op1, op2, 1); \
2173 }
2174
2175 #define INSN2(NAME, op1, op2) \
2176 void NAME(FloatRegister Vt, FloatRegister Vt2, SIMD_Arrangement T, const Address &a) { \
2177 assert(Vt->successor() == Vt2, "Registers must be ordered"); \
2178 ld_st(Vt, T, a, op1, op2, 2); \
2179 }
2180
2181 #define INSN3(NAME, op1, op2) \
2182 void NAME(FloatRegister Vt, FloatRegister Vt2, FloatRegister Vt3, \
2183 SIMD_Arrangement T, const Address &a) { \
2184 assert(Vt->successor() == Vt2 && Vt2->successor() == Vt3, \
2185 "Registers must be ordered"); \
2186 ld_st(Vt, T, a, op1, op2, 3); \
2187 }
2188
2189 #define INSN4(NAME, op1, op2) \
2190 void NAME(FloatRegister Vt, FloatRegister Vt2, FloatRegister Vt3, \
2191 FloatRegister Vt4, SIMD_Arrangement T, const Address &a) { \
2192 assert(Vt->successor() == Vt2 && Vt2->successor() == Vt3 && \
2193 Vt3->successor() == Vt4, "Registers must be ordered"); \
2194 ld_st(Vt, T, a, op1, op2, 4); \
2195 }
2196
2197 INSN1(ld1, 0b001100010, 0b0111);
2198 INSN2(ld1, 0b001100010, 0b1010);
2199 INSN3(ld1, 0b001100010, 0b0110);
2200 INSN4(ld1, 0b001100010, 0b0010);
2201
2202 INSN2(ld2, 0b001100010, 0b1000);
2203 INSN3(ld3, 0b001100010, 0b0100);
2204 INSN4(ld4, 0b001100010, 0b0000);
2205
2206 INSN1(st1, 0b001100000, 0b0111);
2207 INSN2(st1, 0b001100000, 0b1010);
2208 INSN3(st1, 0b001100000, 0b0110);
2209 INSN4(st1, 0b001100000, 0b0010);
2210
2211 INSN2(st2, 0b001100000, 0b1000);
2212 INSN3(st3, 0b001100000, 0b0100);
2213 INSN4(st4, 0b001100000, 0b0000);
2214
2215 INSN1(ld1r, 0b001101010, 0b1100);
2216 INSN2(ld2r, 0b001101011, 0b1100);
2217 INSN3(ld3r, 0b001101010, 0b1110);
2218 INSN4(ld4r, 0b001101011, 0b1110);
2219
2220 #undef INSN1
2221 #undef INSN2
2222 #undef INSN3
2223 #undef INSN4
2224
2225 #define INSN(NAME, opc) \
2226 void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn, FloatRegister Vm) { \
2227 starti; \
2228 assert(T == T8B || T == T16B, "must be T8B or T16B"); \
2229 f(0, 31), f((int)T & 1, 30), f(opc, 29, 21); \
2230 rf(Vm, 16), f(0b000111, 15, 10), rf(Vn, 5), rf(Vd, 0); \
2231 }
2232
2233 INSN(eor, 0b101110001);
2234 INSN(orr, 0b001110101);
2235 INSN(andr, 0b001110001);
2236 INSN(bic, 0b001110011);
2237 INSN(bif, 0b101110111);
2238 INSN(bit, 0b101110101);
2239 INSN(bsl, 0b101110011);
2240 INSN(orn, 0b001110111);
2241
2242 #undef INSN
2243
2244 #define INSN(NAME, opc, opc2, acceptT2D) \
2245 void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn, FloatRegister Vm) { \
2246 guarantee(T != T1Q && T != T1D, "incorrect arrangement"); \
2247 if (!acceptT2D) guarantee(T != T2D, "incorrect arrangement"); \
2248 starti; \
2249 f(0, 31), f((int)T & 1, 30), f(opc, 29), f(0b01110, 28, 24); \
2250 f((int)T >> 1, 23, 22), f(1, 21), rf(Vm, 16), f(opc2, 15, 10); \
2251 rf(Vn, 5), rf(Vd, 0); \
2252 }
2253
2254 INSN(addv, 0, 0b100001, true); // accepted arrangements: T8B, T16B, T4H, T8H, T2S, T4S, T2D
2255 INSN(subv, 1, 0b100001, true); // accepted arrangements: T8B, T16B, T4H, T8H, T2S, T4S, T2D
2256 INSN(mulv, 0, 0b100111, false); // accepted arrangements: T8B, T16B, T4H, T8H, T2S, T4S
2257 INSN(mlav, 0, 0b100101, false); // accepted arrangements: T8B, T16B, T4H, T8H, T2S, T4S
2258 INSN(mlsv, 1, 0b100101, false); // accepted arrangements: T8B, T16B, T4H, T8H, T2S, T4S
2259 INSN(sshl, 0, 0b010001, true); // accepted arrangements: T8B, T16B, T4H, T8H, T2S, T4S, T2D
2260 INSN(ushl, 1, 0b010001, true); // accepted arrangements: T8B, T16B, T4H, T8H, T2S, T4S, T2D
2261 INSN(addpv, 0, 0b101111, true); // accepted arrangements: T8B, T16B, T4H, T8H, T2S, T4S, T2D
2262 INSN(smullv, 0, 0b110000, false); // accepted arrangements: T8B, T16B, T4H, T8H, T2S, T4S
2263 INSN(umullv, 1, 0b110000, false); // accepted arrangements: T8B, T16B, T4H, T8H, T2S, T4S
2264 INSN(umlalv, 1, 0b100000, false); // accepted arrangements: T8B, T16B, T4H, T8H, T2S, T4S
2265
2266 #undef INSN
2267
2268 #define INSN(NAME, opc, opc2, accepted) \
2269 void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn) { \
2270 guarantee(T != T1Q && T != T1D, "incorrect arrangement"); \
2271 if (accepted < 3) guarantee(T != T2D, "incorrect arrangement"); \
2272 if (accepted < 2) guarantee(T != T2S, "incorrect arrangement"); \
2273 if (accepted < 1) guarantee(T == T8B || T == T16B, "incorrect arrangement"); \
2274 starti; \
2275 f(0, 31), f((int)T & 1, 30), f(opc, 29), f(0b01110, 28, 24); \
2276 f((int)T >> 1, 23, 22), f(opc2, 21, 10); \
2277 rf(Vn, 5), rf(Vd, 0); \
2278 }
2279
2280 INSN(absr, 0, 0b100000101110, 3); // accepted arrangements: T8B, T16B, T4H, T8H, T2S, T4S, T2D
2281 INSN(negr, 1, 0b100000101110, 3); // accepted arrangements: T8B, T16B, T4H, T8H, T2S, T4S, T2D
2282 INSN(notr, 1, 0b100000010110, 0); // accepted arrangements: T8B, T16B
2283 INSN(addv, 0, 0b110001101110, 1); // accepted arrangements: T8B, T16B, T4H, T8H, T4S
2284 INSN(cls, 0, 0b100000010010, 2); // accepted arrangements: T8B, T16B, T4H, T8H, T2S, T4S
2285 INSN(clz, 1, 0b100000010010, 2); // accepted arrangements: T8B, T16B, T4H, T8H, T2S, T4S
2286 INSN(cnt, 0, 0b100000010110, 0); // accepted arrangements: T8B, T16B
2287 INSN(uaddlp, 1, 0b100000001010, 2); // accepted arrangements: T8B, T16B, T4H, T8H, T2S, T4S
2288 INSN(uaddlv, 1, 0b110000001110, 1); // accepted arrangements: T8B, T16B, T4H, T8H, T4S
2289
2290 #undef INSN
2291
2292 #define INSN(NAME, opc) \
2293 void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn) { \
2294 starti; \
2295 assert(T == T4S, "arrangement must be T4S"); \
2296 f(0, 31), f((int)T & 1, 30), f(0b101110, 29, 24), f(opc, 23), \
2297 f(T == T4S ? 0 : 1, 22), f(0b110000111110, 21, 10); rf(Vn, 5), rf(Vd, 0); \
2298 }
2299
2300 INSN(fmaxv, 0);
2301 INSN(fminv, 1);
2302
2303 #undef INSN
2304
2305 #define INSN(NAME, op0, cmode0) \
2306 void NAME(FloatRegister Vd, SIMD_Arrangement T, unsigned imm8, unsigned lsl = 0) { \
2307 unsigned cmode = cmode0; \
2308 unsigned op = op0; \
2309 starti; \
2310 assert(lsl == 0 || \
2311 ((T == T4H || T == T8H) && lsl == 8) || \
2312 ((T == T2S || T == T4S) && ((lsl >> 3) < 4) && ((lsl & 7) == 0)), "invalid shift");\
2313 cmode |= lsl >> 2; \
2314 if (T == T4H || T == T8H) cmode |= 0b1000; \
2315 if (!(T == T4H || T == T8H || T == T2S || T == T4S)) { \
2316 assert(op == 0 && cmode0 == 0, "must be MOVI"); \
2317 cmode = 0b1110; \
2318 if (T == T1D || T == T2D) op = 1; \
2319 } \
2320 f(0, 31), f((int)T & 1, 30), f(op, 29), f(0b0111100000, 28, 19); \
2321 f(imm8 >> 5, 18, 16), f(cmode, 15, 12), f(0x01, 11, 10), f(imm8 & 0b11111, 9, 5); \
2322 rf(Vd, 0); \
2323 }
2324
2325 INSN(movi, 0, 0);
2326 INSN(orri, 0, 1);
2327 INSN(mvni, 1, 0);
2328 INSN(bici, 1, 1);
2329
2330 #undef INSN
2331
2332 #define INSN(NAME, op1, op2, op3) \
2333 void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn, FloatRegister Vm) { \
2334 starti; \
2335 assert(T == T2S || T == T4S || T == T2D, "invalid arrangement"); \
2336 f(0, 31), f((int)T & 1, 30), f(op1, 29), f(0b01110, 28, 24), f(op2, 23); \
2337 f(T==T2D ? 1:0, 22); f(1, 21), rf(Vm, 16), f(op3, 15, 10), rf(Vn, 5), rf(Vd, 0); \
2338 }
2339
2340 INSN(fadd, 0, 0, 0b110101);
2341 INSN(fdiv, 1, 0, 0b111111);
2342 INSN(fmul, 1, 0, 0b110111);
2343 INSN(fsub, 0, 1, 0b110101);
2344 INSN(fmla, 0, 0, 0b110011);
2345 INSN(fmls, 0, 1, 0b110011);
2346 INSN(fmax, 0, 0, 0b111101);
2347 INSN(fmin, 0, 1, 0b111101);
2348
2349 #undef INSN
2350
2351 #define INSN(NAME, opc) \
2352 void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn, FloatRegister Vm) { \
2353 starti; \
2354 assert(T == T4S, "arrangement must be T4S"); \
2355 f(0b01011110000, 31, 21), rf(Vm, 16), f(opc, 15, 10), rf(Vn, 5), rf(Vd, 0); \
2356 }
2357
2358 INSN(sha1c, 0b000000);
2359 INSN(sha1m, 0b001000);
2360 INSN(sha1p, 0b000100);
2361 INSN(sha1su0, 0b001100);
2362 INSN(sha256h2, 0b010100);
2363 INSN(sha256h, 0b010000);
2364 INSN(sha256su1, 0b011000);
2365
2366 #undef INSN
2367
2368 #define INSN(NAME, opc) \
2369 void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn) { \
2370 starti; \
2371 assert(T == T4S, "arrangement must be T4S"); \
2372 f(0b0101111000101000, 31, 16), f(opc, 15, 10), rf(Vn, 5), rf(Vd, 0); \
2373 }
2374
2375 INSN(sha1h, 0b000010);
2376 INSN(sha1su1, 0b000110);
2377 INSN(sha256su0, 0b001010);
2378
2379 #undef INSN
2380
2381 #define INSN(NAME, opc) \
2382 void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn, FloatRegister Vm) { \
2383 starti; \
2384 assert(T == T2D, "arrangement must be T2D"); \
2385 f(0b11001110011, 31, 21), rf(Vm, 16), f(opc, 15, 10), rf(Vn, 5), rf(Vd, 0); \
2386 }
2387
2388 INSN(sha512h, 0b100000);
2389 INSN(sha512h2, 0b100001);
2390 INSN(sha512su1, 0b100010);
2391
2392 #undef INSN
2393
2394 #define INSN(NAME, opc) \
2395 void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn) { \
2396 starti; \
2397 assert(T == T2D, "arrangement must be T2D"); \
2398 f(opc, 31, 10), rf(Vn, 5), rf(Vd, 0); \
2399 }
2400
2401 INSN(sha512su0, 0b1100111011000000100000);
2402
2403 #undef INSN
2404
2405 #define INSN(NAME, opc) \
2406 void NAME(FloatRegister Vd, FloatRegister Vn) { \
2407 starti; \
2408 f(opc, 31, 10), rf(Vn, 5), rf(Vd, 0); \
2409 }
2410
2411 INSN(aese, 0b0100111000101000010010);
2412 INSN(aesd, 0b0100111000101000010110);
2413 INSN(aesmc, 0b0100111000101000011010);
2414 INSN(aesimc, 0b0100111000101000011110);
2415
2416 #undef INSN
2417
2418 #define INSN(NAME, op1, op2) \
2419 void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn, FloatRegister Vm, int index = 0) { \
2420 starti; \
2421 assert(T == T2S || T == T4S || T == T2D, "invalid arrangement"); \
2422 assert(index >= 0 && ((T == T2D && index <= 1) || (T != T2D && index <= 3)), "invalid index"); \
2423 f(0, 31), f((int)T & 1, 30), f(op1, 29); f(0b011111, 28, 23); \
2424 f(T == T2D ? 1 : 0, 22), f(T == T2D ? 0 : index & 1, 21), rf(Vm, 16); \
2425 f(op2, 15, 12), f(T == T2D ? index : (index >> 1), 11), f(0, 10); \
2426 rf(Vn, 5), rf(Vd, 0); \
2427 }
2428
2429 // FMLA/FMLS - Vector - Scalar
2430 INSN(fmlavs, 0, 0b0001);
2431 INSN(fmlsvs, 0, 0b0101);
2432 // FMULX - Vector - Scalar
2433 INSN(fmulxvs, 1, 0b1001);
2434
2435 #undef INSN
2436
2437 // Floating-point Reciprocal Estimate
2438 void frecpe(FloatRegister Vd, FloatRegister Vn, SIMD_RegVariant type) {
2439 assert(type == D || type == S, "Wrong type for frecpe");
2440 starti;
2441 f(0b010111101, 31, 23);
2442 f(type == D ? 1 : 0, 22);
2443 f(0b100001110110, 21, 10);
2444 rf(Vn, 5), rf(Vd, 0);
2445 }
2446
2447 // (double) {a, b} -> (a + b)
2448 void faddpd(FloatRegister Vd, FloatRegister Vn) {
2449 starti;
2450 f(0b0111111001110000110110, 31, 10);
2451 rf(Vn, 5), rf(Vd, 0);
2452 }
2453
2454 void ins(FloatRegister Vd, SIMD_RegVariant T, FloatRegister Vn, int didx, int sidx) {
2455 starti;
2456 assert(T != Q, "invalid register variant");
2457 f(0b01101110000, 31, 21), f(((didx<<1)|1)<<(int)T, 20, 16), f(0, 15);
2458 f(sidx<<(int)T, 14, 11), f(1, 10), rf(Vn, 5), rf(Vd, 0);
2459 }
2460
2461 void umov(Register Rd, FloatRegister Vn, SIMD_RegVariant T, int idx) {
2462 starti;
2463 f(0, 31), f(T==D ? 1:0, 30), f(0b001110000, 29, 21);
2464 f(((idx<<1)|1)<<(int)T, 20, 16), f(0b001111, 15, 10);
2465 rf(Vn, 5), rf(Rd, 0);
2466 }
2467
2468 #define INSN(NAME, opc, opc2, isSHR) \
2469 void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn, int shift){ \
2470 starti; \
2471 /* The encodings for the immh:immb fields (bits 22:16) in *SHR are \
2472 * 0001 xxx 8B/16B, shift = 16 - UInt(immh:immb) \
2473 * 001x xxx 4H/8H, shift = 32 - UInt(immh:immb) \
2474 * 01xx xxx 2S/4S, shift = 64 - UInt(immh:immb) \
2475 * 1xxx xxx 1D/2D, shift = 128 - UInt(immh:immb) \
2476 * (1D is RESERVED) \
2477 * for SHL shift is calculated as: \
2478 * 0001 xxx 8B/16B, shift = UInt(immh:immb) - 8 \
2479 * 001x xxx 4H/8H, shift = UInt(immh:immb) - 16 \
2480 * 01xx xxx 2S/4S, shift = UInt(immh:immb) - 32 \
2481 * 1xxx xxx 1D/2D, shift = UInt(immh:immb) - 64 \
2482 * (1D is RESERVED) \
2483 */ \
2484 assert((1 << ((T>>1)+3)) > shift, "Invalid Shift value"); \
2485 int cVal = (1 << (((T >> 1) + 3) + (isSHR ? 1 : 0))); \
2486 int encodedShift = isSHR ? cVal - shift : cVal + shift; \
2487 f(0, 31), f(T & 1, 30), f(opc, 29), f(0b011110, 28, 23), \
2488 f(encodedShift, 22, 16); f(opc2, 15, 10), rf(Vn, 5), rf(Vd, 0); \
2489 }
2490
2491 INSN(shl, 0, 0b010101, /* isSHR = */ false);
2492 INSN(sshr, 0, 0b000001, /* isSHR = */ true);
2493 INSN(ushr, 1, 0b000001, /* isSHR = */ true);
2494
2495 #undef INSN
2496
2497 private:
2498 void _ushll(FloatRegister Vd, SIMD_Arrangement Ta, FloatRegister Vn, SIMD_Arrangement Tb, int shift) {
2499 starti;
2500 /* The encodings for the immh:immb fields (bits 22:16) are
2501 * 0001 xxx 8H, 8B/16b shift = xxx
2502 * 001x xxx 4S, 4H/8H shift = xxxx
2503 * 01xx xxx 2D, 2S/4S shift = xxxxx
2504 * 1xxx xxx RESERVED
2505 */
2506 assert((Tb >> 1) + 1 == (Ta >> 1), "Incompatible arrangement");
2507 assert((1 << ((Tb>>1)+3)) > shift, "Invalid shift value");
2508 f(0, 31), f(Tb & 1, 30), f(0b1011110, 29, 23), f((1 << ((Tb>>1)+3))|shift, 22, 16);
2509 f(0b101001, 15, 10), rf(Vn, 5), rf(Vd, 0);
2510 }
2511
2512 public:
2513 void ushll(FloatRegister Vd, SIMD_Arrangement Ta, FloatRegister Vn, SIMD_Arrangement Tb, int shift) {
2514 assert(Tb == T8B || Tb == T4H || Tb == T2S, "invalid arrangement");
2515 _ushll(Vd, Ta, Vn, Tb, shift);
2516 }
2517
2518 void ushll2(FloatRegister Vd, SIMD_Arrangement Ta, FloatRegister Vn, SIMD_Arrangement Tb, int shift) {
2519 assert(Tb == T16B || Tb == T8H || Tb == T4S, "invalid arrangement");
2520 _ushll(Vd, Ta, Vn, Tb, shift);
2521 }
2522
2523 // Move from general purpose register
2524 // mov Vd.T[index], Rn
2525 void mov(FloatRegister Vd, SIMD_Arrangement T, int index, Register Xn) {
2526 starti;
2527 f(0b01001110000, 31, 21), f(((1 << (T >> 1)) | (index << ((T >> 1) + 1))), 20, 16);
2528 f(0b000111, 15, 10), zrf(Xn, 5), rf(Vd, 0);
2529 }
2530
2531 // Move to general purpose register
2532 // mov Rd, Vn.T[index]
2533 void mov(Register Xd, FloatRegister Vn, SIMD_Arrangement T, int index) {
2534 guarantee(T >= T2S && T < T1Q, "only D and S arrangements are supported");
2535 starti;
2536 f(0, 31), f((T >= T1D) ? 1:0, 30), f(0b001110000, 29, 21);
2537 f(((1 << (T >> 1)) | (index << ((T >> 1) + 1))), 20, 16);
2538 f(0b001111, 15, 10), rf(Vn, 5), rf(Xd, 0);
2539 }
2540
2541 private:
2542 void _pmull(FloatRegister Vd, SIMD_Arrangement Ta, FloatRegister Vn, FloatRegister Vm, SIMD_Arrangement Tb) {
2543 starti;
2544 assert((Ta == T1Q && (Tb == T1D || Tb == T2D)) ||
2545 (Ta == T8H && (Tb == T8B || Tb == T16B)), "Invalid Size specifier");
2546 int size = (Ta == T1Q) ? 0b11 : 0b00;
2547 f(0, 31), f(Tb & 1, 30), f(0b001110, 29, 24), f(size, 23, 22);
2548 f(1, 21), rf(Vm, 16), f(0b111000, 15, 10), rf(Vn, 5), rf(Vd, 0);
2549 }
2550
2551 public:
2552 void pmull(FloatRegister Vd, SIMD_Arrangement Ta, FloatRegister Vn, FloatRegister Vm, SIMD_Arrangement Tb) {
2553 assert(Tb == T1D || Tb == T8B, "pmull assumes T1D or T8B as the second size specifier");
2554 _pmull(Vd, Ta, Vn, Vm, Tb);
2555 }
2556
2557 void pmull2(FloatRegister Vd, SIMD_Arrangement Ta, FloatRegister Vn, FloatRegister Vm, SIMD_Arrangement Tb) {
2558 assert(Tb == T2D || Tb == T16B, "pmull2 assumes T2D or T16B as the second size specifier");
2559 _pmull(Vd, Ta, Vn, Vm, Tb);
2560 }
2561
2562 void uqxtn(FloatRegister Vd, SIMD_Arrangement Tb, FloatRegister Vn, SIMD_Arrangement Ta) {
2563 starti;
2564 int size_b = (int)Tb >> 1;
2565 int size_a = (int)Ta >> 1;
2566 assert(size_b < 3 && size_b == size_a - 1, "Invalid size specifier");
2567 f(0, 31), f(Tb & 1, 30), f(0b101110, 29, 24), f(size_b, 23, 22);
2568 f(0b100001010010, 21, 10), rf(Vn, 5), rf(Vd, 0);
2569 }
2570
2571 void dup(FloatRegister Vd, SIMD_Arrangement T, Register Xs)
2572 {
2573 starti;
2574 assert(T != T1D, "reserved encoding");
2575 f(0,31), f((int)T & 1, 30), f(0b001110000, 29, 21);
2576 f((1 << (T >> 1)), 20, 16), f(0b000011, 15, 10), zrf(Xs, 5), rf(Vd, 0);
2577 }
2578
2579 void dup(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn, int index = 0)
2580 {
2581 starti;
2582 assert(T != T1D, "reserved encoding");
2583 f(0, 31), f((int)T & 1, 30), f(0b001110000, 29, 21);
2584 f(((1 << (T >> 1)) | (index << ((T >> 1) + 1))), 20, 16);
2585 f(0b000001, 15, 10), rf(Vn, 5), rf(Vd, 0);
2586 }
2587
2588 // AdvSIMD ZIP/UZP/TRN
2589 #define INSN(NAME, opcode) \
2590 void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn, FloatRegister Vm) { \
2591 guarantee(T != T1D && T != T1Q, "invalid arrangement"); \
2592 starti; \
2593 f(0, 31), f(0b001110, 29, 24), f(0, 21), f(0, 15); \
2594 f(opcode, 14, 12), f(0b10, 11, 10); \
2595 rf(Vm, 16), rf(Vn, 5), rf(Vd, 0); \
2596 f(T & 1, 30), f(T >> 1, 23, 22); \
2597 }
2598
2599 INSN(uzp1, 0b001);
2600 INSN(trn1, 0b010);
2601 INSN(zip1, 0b011);
2602 INSN(uzp2, 0b101);
2603 INSN(trn2, 0b110);
2604 INSN(zip2, 0b111);
2605
2606 #undef INSN
2607
2608 // CRC32 instructions
2609 #define INSN(NAME, c, sf, sz) \
2610 void NAME(Register Rd, Register Rn, Register Rm) { \
2611 starti; \
2612 f(sf, 31), f(0b0011010110, 30, 21), f(0b010, 15, 13), f(c, 12); \
2613 f(sz, 11, 10), rf(Rm, 16), rf(Rn, 5), rf(Rd, 0); \
2614 }
2615
2616 INSN(crc32b, 0, 0, 0b00);
2617 INSN(crc32h, 0, 0, 0b01);
2618 INSN(crc32w, 0, 0, 0b10);
2619 INSN(crc32x, 0, 1, 0b11);
2620 INSN(crc32cb, 1, 0, 0b00);
2621 INSN(crc32ch, 1, 0, 0b01);
2622 INSN(crc32cw, 1, 0, 0b10);
2623 INSN(crc32cx, 1, 1, 0b11);
2624
2625 #undef INSN
2626
2627 // Table vector lookup
2628 #define INSN(NAME, op) \
2629 void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn, unsigned registers, FloatRegister Vm) { \
2630 starti; \
2631 assert(T == T8B || T == T16B, "invalid arrangement"); \
2632 assert(0 < registers && registers <= 4, "invalid number of registers"); \
2633 f(0, 31), f((int)T & 1, 30), f(0b001110000, 29, 21), rf(Vm, 16), f(0, 15); \
2634 f(registers - 1, 14, 13), f(op, 12),f(0b00, 11, 10), rf(Vn, 5), rf(Vd, 0); \
2635 }
2636
2637 INSN(tbl, 0);
2638 INSN(tbx, 1);
2639
2640 #undef INSN
2641
2642 // AdvSIMD two-reg misc
2643 // In this instruction group, the 2 bits in the size field ([23:22]) may be
2644 // fixed or determined by the "SIMD_Arrangement T", or both. The additional
2645 // parameter "tmask" is a 2-bit mask used to indicate which bits in the size
2646 // field are determined by the SIMD_Arrangement. The bit of "tmask" should be
2647 // set to 1 if corresponding bit marked as "x" in the ArmARM.
2648 #define INSN(NAME, U, size, tmask, opcode) \
2649 void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn) { \
2650 starti; \
2651 assert((ASSERTION), MSG); \
2652 f(0, 31), f((int)T & 1, 30), f(U, 29), f(0b01110, 28, 24); \
2653 f(size | ((int)(T >> 1) & tmask), 23, 22), f(0b10000, 21, 17); \
2654 f(opcode, 16, 12), f(0b10, 11, 10), rf(Vn, 5), rf(Vd, 0); \
2655 }
2656
2657 #define MSG "invalid arrangement"
2658
2659 #define ASSERTION (T == T2S || T == T4S || T == T2D)
2660 INSN(fsqrt, 1, 0b10, 0b01, 0b11111);
2661 INSN(fabs, 0, 0b10, 0b01, 0b01111);
2662 INSN(fneg, 1, 0b10, 0b01, 0b01111);
2663 INSN(frintn, 0, 0b00, 0b01, 0b11000);
2664 INSN(frintm, 0, 0b00, 0b01, 0b11001);
2665 INSN(frintp, 0, 0b10, 0b01, 0b11000);
2666 #undef ASSERTION
2667
2668 #define ASSERTION (T == T8B || T == T16B || T == T4H || T == T8H || T == T2S || T == T4S)
2669 INSN(rev64, 0, 0b00, 0b11, 0b00000);
2670 #undef ASSERTION
2671
2672 #define ASSERTION (T == T8B || T == T16B || T == T4H || T == T8H)
2673 INSN(rev32, 1, 0b00, 0b11, 0b00000);
2674 #undef ASSERTION
2675
2676 #define ASSERTION (T == T8B || T == T16B)
2677 INSN(rev16, 0, 0b00, 0b11, 0b00001);
2678 INSN(rbit, 1, 0b01, 0b00, 0b00101);
2679 #undef ASSERTION
2680
2681 #undef MSG
2682
2683 #undef INSN
2684
2685 void ext(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn, FloatRegister Vm, int index)
2686 {
2687 starti;
2688 assert(T == T8B || T == T16B, "invalid arrangement");
2689 assert((T == T8B && index <= 0b0111) || (T == T16B && index <= 0b1111), "Invalid index value");
2690 f(0, 31), f((int)T & 1, 30), f(0b101110000, 29, 21);
2691 rf(Vm, 16), f(0, 15), f(index, 14, 11);
2692 f(0, 10), rf(Vn, 5), rf(Vd, 0);
2693 }
2694
2695 Assembler(CodeBuffer* code) : AbstractAssembler(code) {
2696 }
2697
2698 virtual RegisterOrConstant delayed_value_impl(intptr_t* delayed_value_addr,
2699 Register tmp,
2700 int offset) {
2701 ShouldNotCallThis();
2702 return RegisterOrConstant();
2703 }
2704
2705 // Stack overflow checking
2706 virtual void bang_stack_with_offset(int offset);
2707
2708 static bool operand_valid_for_logical_immediate(bool is32, uint64_t imm);
2709 static bool operand_valid_for_add_sub_immediate(int64_t imm);
2710 static bool operand_valid_for_float_immediate(double imm);
2711
2712 void emit_data64(jlong data, relocInfo::relocType rtype, int format = 0);
2713 void emit_data64(jlong data, RelocationHolder const& rspec, int format = 0);
2714 };
2715
2716 inline Assembler::Membar_mask_bits operator|(Assembler::Membar_mask_bits a,
2717 Assembler::Membar_mask_bits b) {
2718 return Assembler::Membar_mask_bits(unsigned(a)|unsigned(b));
2719 }
2720
2721 Instruction_aarch64::~Instruction_aarch64() {
2722 assem->emit();
2723 }
2724
2725 #undef starti
2726
2727 // Invert a condition
2728 inline const Assembler::Condition operator~(const Assembler::Condition cond) {
2729 return Assembler::Condition(int(cond) ^ 1);
2730 }
2731
2732 class BiasedLockingCounters;
2733
2734 extern "C" void das(uint64_t start, int len);
2735
2736 #endif // CPU_AARCH64_ASSEMBLER_AARCH64_HPP
--- EOF ---