458 mov(dst, (u_int64_t)l);
459 }
460
461 inline void mov(Register dst, int i)
462 {
463 mov(dst, (long)i);
464 }
465
466 void movptr(Register r, uintptr_t imm64);
467
468 // Macro to mov replicated immediate to vector register.
469 // Where imm32 == hex abcdefgh, Vd will get the following values
470 // for different arrangements in T
471 // T8B: Vd = ghghghghghghghgh
472 // T16B: Vd = ghghghghghghghghghghghghghghghgh
473 // T4H: Vd = efghefghefghefgh
474 // T8H: Vd = efghefghefghefghefghefghefghefgh
475 // T2S: Vd = abcdefghabcdefgh
476 // T4S: Vd = abcdefghabcdefghabcdefghabcdefgh
477 // T1D/T2D: invalid
478 void mov(FloatRegister Vd, SIMD_Arrangement T, u_int32_t imm32) {
479 assert(T != T1D && T != T2D, "invalid arrangement");
480 u_int32_t nimm32 = ~imm32;
481 if (T == T8B || T == T16B) { imm32 &= 0xff; nimm32 &= 0xff; }
482 if (T == T4H || T == T8H) { imm32 &= 0xffff; nimm32 &= 0xffff; }
483 u_int32_t x = imm32;
484 int movi_cnt = 0;
485 int movn_cnt = 0;
486 while (x) { if (x & 0xff) movi_cnt++; x >>= 8; }
487 x = nimm32;
488 while (x) { if (x & 0xff) movn_cnt++; x >>= 8; }
489 if (movn_cnt < movi_cnt) imm32 = nimm32;
490 unsigned lsl = 0;
491 while (imm32 && (imm32 & 0xff) == 0) { lsl += 8; imm32 >>= 8; }
492 if (movn_cnt < movi_cnt)
493 mvni(Vd, T, imm32 & 0xff, lsl);
494 else
495 movi(Vd, T, imm32 & 0xff, lsl);
496 imm32 >>= 8; lsl += 8;
497 while (imm32) {
498 while ((imm32 & 0xff) == 0) { lsl += 8; imm32 >>= 8; }
499 if (movn_cnt < movi_cnt)
500 bici(Vd, T, imm32 & 0xff, lsl);
501 else
502 orri(Vd, T, imm32 & 0xff, lsl);
503 lsl += 8; imm32 >>= 8;
504 }
505 }
506
507 // macro instructions for accessing and updating floating point
508 // status register
509 //
510 // FPSR : op1 == 011
511 // CRn == 0100
512 // CRm == 0100
513 // op2 == 001
514
515 inline void get_fpsr(Register reg)
516 {
517 mrs(0b11, 0b0100, 0b0100, 0b001, reg);
518 }
519
520 inline void set_fpsr(Register reg)
521 {
522 msr(0b011, 0b0100, 0b0100, 0b001, reg);
523 }
524
525 inline void clear_fpsr()
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458 mov(dst, (u_int64_t)l);
459 }
460
461 inline void mov(Register dst, int i)
462 {
463 mov(dst, (long)i);
464 }
465
466 void movptr(Register r, uintptr_t imm64);
467
468 // Macro to mov replicated immediate to vector register.
469 // Where imm32 == hex abcdefgh, Vd will get the following values
470 // for different arrangements in T
471 // T8B: Vd = ghghghghghghghgh
472 // T16B: Vd = ghghghghghghghghghghghghghghghgh
473 // T4H: Vd = efghefghefghefgh
474 // T8H: Vd = efghefghefghefghefghefghefghefgh
475 // T2S: Vd = abcdefghabcdefgh
476 // T4S: Vd = abcdefghabcdefghabcdefghabcdefgh
477 // T1D/T2D: invalid
478 void mov(FloatRegister Vd, SIMD_Arrangement T, u_int32_t imm32);
479
480 // macro instructions for accessing and updating floating point
481 // status register
482 //
483 // FPSR : op1 == 011
484 // CRn == 0100
485 // CRm == 0100
486 // op2 == 001
487
488 inline void get_fpsr(Register reg)
489 {
490 mrs(0b11, 0b0100, 0b0100, 0b001, reg);
491 }
492
493 inline void set_fpsr(Register reg)
494 {
495 msr(0b011, 0b0100, 0b0100, 0b001, reg);
496 }
497
498 inline void clear_fpsr()
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