--- old/src/hotspot/cpu/aarch64/gc/shared/barrierSetAssembler_aarch64.cpp	2019-09-02 10:59:24.652957425 +0000
+++ new/src/hotspot/cpu/aarch64/gc/shared/barrierSetAssembler_aarch64.cpp	2019-09-02 10:59:23.540907488 +0000
@@ -76,22 +76,35 @@
                                    Address dst, Register val, Register tmp1, Register tmp2, Register tmp3) {
   bool in_heap = (decorators & IN_HEAP) != 0;
   bool in_native = (decorators & IN_NATIVE) != 0;
+  bool is_not_null = (decorators & IS_NOT_NULL) != 0;
+
   switch (type) {
   case T_OBJECT:
   case T_ARRAY: {
-    val = val == noreg ? zr : val;
-    if (in_heap) {
-      if (UseCompressedOops) {
-        assert(!dst.uses(val), "not enough registers");
-        if (val != zr) {
-          __ encode_heap_oop(val);
+   if (in_heap) {
+      if (val == noreg) {
+        assert(!is_not_null, "inconsistent access");
+        if (UseCompressedOops) {
+          __ strw(zr, dst);
+        } else {
+          __ str(zr, dst);
         }
-        __ strw(val, dst);
       } else {
-        __ str(val, dst);
+        if (UseCompressedOops) {
+          assert(!dst.uses(val), "not enough registers");
+          if (is_not_null) {
+            __ encode_heap_oop_not_null(val);
+          } else {
+            __ encode_heap_oop(val);
+          }
+          __ strw(val, dst); 
+        } else {
+          __ str(val, dst);
+        }
       }
     } else {
       assert(in_native, "why else?");
+      assert(val != noreg, "not supported");
       __ str(val, dst);
     }
     break;
@@ -231,7 +244,7 @@
 }
 
 void BarrierSetAssembler::nmethod_entry_barrier(MacroAssembler* masm)  {
-// DMS CHECK: 8210498: nmethod entry barriers is not implemented
+// FIXME: 8210498: nmethod entry barriers is not implemented
 #if 0
  BarrierSetNMethod* bs_nm = BarrierSet::barrier_set()->barrier_set_nmethod();
   if (bs_nm == NULL) {