9 *
10 * This code is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * version 2 for more details (a copy is included in the LICENSE file that
14 * accompanied this code).
15 *
16 * You should have received a copy of the GNU General Public License version
17 * 2 along with this work; if not, write to the Free Software Foundation,
18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 * or visit www.oracle.com if you need additional information or have any
22 * questions.
23 *
24 */
25
26 #include "precompiled.hpp"
27 #include "asm/macroAssembler.hpp"
28 #include "asm/macroAssembler.inline.hpp"
29 #include "code/debugInfoRec.hpp"
30 #include "code/icBuffer.hpp"
31 #include "code/vtableStubs.hpp"
32 #include "interpreter/interpreter.hpp"
33 #include "interpreter/interp_masm.hpp"
34 #include "logging/log.hpp"
35 #include "memory/resourceArea.hpp"
36 #include "oops/compiledICHolder.hpp"
37 #include "runtime/safepointMechanism.hpp"
38 #include "runtime/sharedRuntime.hpp"
39 #include "runtime/vframeArray.hpp"
40 #include "utilities/align.hpp"
41 #include "vmreg_aarch64.inline.hpp"
42 #ifdef COMPILER1
43 #include "c1/c1_Runtime1.hpp"
44 #endif
45 #if COMPILER2_OR_JVMCI
46 #include "adfiles/ad_aarch64.hpp"
47 #include "opto/runtime.hpp"
48 #endif
272 case T_SHORT:
273 case T_INT:
274 if (int_args < Argument::n_int_register_parameters_j) {
275 regs[i].set1(INT_ArgReg[int_args++]->as_VMReg());
276 } else {
277 regs[i].set1(VMRegImpl::stack2reg(stk_args));
278 stk_args += 2;
279 }
280 break;
281 case T_VOID:
282 // halves of T_LONG or T_DOUBLE
283 assert(i != 0 && (sig_bt[i - 1] == T_LONG || sig_bt[i - 1] == T_DOUBLE), "expecting half");
284 regs[i].set_bad();
285 break;
286 case T_LONG:
287 assert((i + 1) < total_args_passed && sig_bt[i + 1] == T_VOID, "expecting half");
288 // fall through
289 case T_OBJECT:
290 case T_ARRAY:
291 case T_ADDRESS:
292 if (int_args < Argument::n_int_register_parameters_j) {
293 regs[i].set2(INT_ArgReg[int_args++]->as_VMReg());
294 } else {
295 regs[i].set2(VMRegImpl::stack2reg(stk_args));
296 stk_args += 2;
297 }
298 break;
299 case T_FLOAT:
300 if (fp_args < Argument::n_float_register_parameters_j) {
301 regs[i].set1(FP_ArgReg[fp_args++]->as_VMReg());
302 } else {
303 regs[i].set1(VMRegImpl::stack2reg(stk_args));
304 stk_args += 2;
305 }
306 break;
307 case T_DOUBLE:
308 assert((i + 1) < total_args_passed && sig_bt[i + 1] == T_VOID, "expecting half");
309 if (fp_args < Argument::n_float_register_parameters_j) {
310 regs[i].set2(FP_ArgReg[fp_args++]->as_VMReg());
311 } else {
312 regs[i].set2(VMRegImpl::stack2reg(stk_args));
313 stk_args += 2;
314 }
315 break;
316 default:
317 ShouldNotReachHere();
318 break;
319 }
320 }
321
322 return align_up(stk_args, 2);
323 }
324
325 // Patch the callers callsite with entry to compiled code if it exists.
326 static void patch_callers_callsite(MacroAssembler *masm) {
327 Label L;
328 __ ldr(rscratch1, Address(rmethod, in_bytes(Method::code_offset())));
329 __ cbz(rscratch1, L);
330
331 __ enter();
332 __ push_CPU_state();
333
334 // VM needs caller's callsite
335 // VM needs target method
336 // This needs to be a long call since we will relocate this adapter to
337 // the codeBuffer and it may not reach
338
339 #ifndef PRODUCT
340 assert(frame::arg_reg_save_area_bytes == 0, "not expecting frame reg save area");
341 #endif
342
343 __ mov(c_rarg0, rmethod);
344 __ mov(c_rarg1, lr);
345 __ lea(rscratch1, RuntimeAddress(CAST_FROM_FN_PTR(address, SharedRuntime::fixup_callers_callsite)));
346 __ blrt(rscratch1, 2, 0, 0);
347 __ maybe_isb();
348
349 __ pop_CPU_state();
350 // restore sp
351 __ leave();
352 __ bind(L);
353 }
354
355 static void gen_c2i_adapter(MacroAssembler *masm,
356 int total_args_passed,
357 int comp_args_on_stack,
358 const BasicType *sig_bt,
359 const VMRegPair *regs,
360 Label& skip_fixup) {
361 // Before we get into the guts of the C2I adapter, see if we should be here
362 // at all. We've come from compiled code and are attempting to jump to the
363 // interpreter, which means the caller made a static call to get here
364 // (vcalls always get a compiled target if there is one). Check for a
365 // compiled target. If there is one, we need to patch the caller's call.
366 patch_callers_callsite(masm);
367
368 __ bind(skip_fixup);
369
370 int words_pushed = 0;
371
372 // Since all args are passed on the stack, total_args_passed *
373 // Interpreter::stackElementSize is the space we need.
374
375 int extraspace = total_args_passed * Interpreter::stackElementSize;
376
377 __ mov(r13, sp);
378
379 // stack is aligned, keep it that way
380 extraspace = align_up(extraspace, 2*wordSize);
381
382 if (extraspace)
383 __ sub(sp, sp, extraspace);
384
385 // Now write the args into the outgoing interpreter space
386 for (int i = 0; i < total_args_passed; i++) {
387 if (sig_bt[i] == T_VOID) {
388 assert(i > 0 && (sig_bt[i-1] == T_LONG || sig_bt[i-1] == T_DOUBLE), "missing half");
389 continue;
390 }
391
392 // offset to start parameters
393 int st_off = (total_args_passed - i - 1) * Interpreter::stackElementSize;
394 int next_off = st_off - Interpreter::stackElementSize;
395
396 // Say 4 args:
397 // i st_off
398 // 0 32 T_LONG
399 // 1 24 T_VOID
400 // 2 16 T_OBJECT
401 // 3 8 T_BOOL
402 // - 0 return address
403 //
404 // However to make thing extra confusing. Because we can fit a long/double in
405 // a single slot on a 64 bt vm and it would be silly to break them up, the interpreter
406 // leaves one slot empty and only stores to a single slot. In this case the
407 // slot that is occupied is the T_VOID slot. See I said it was confusing.
408
409 VMReg r_1 = regs[i].first();
410 VMReg r_2 = regs[i].second();
411 if (!r_1->is_valid()) {
412 assert(!r_2->is_valid(), "");
413 continue;
414 }
415 if (r_1->is_stack()) {
416 // memory to memory use rscratch1
417 int ld_off = (r_1->reg2stack() * VMRegImpl::stack_slot_size
418 + extraspace
419 + words_pushed * wordSize);
420 if (!r_2->is_valid()) {
421 // sign extend??
422 __ ldrw(rscratch1, Address(sp, ld_off));
423 __ str(rscratch1, Address(sp, st_off));
424
425 } else {
426
427 __ ldr(rscratch1, Address(sp, ld_off));
428
429 // Two VMREgs|OptoRegs can be T_OBJECT, T_ADDRESS, T_DOUBLE, T_LONG
430 // T_DOUBLE and T_LONG use two slots in the interpreter
431 if ( sig_bt[i] == T_LONG || sig_bt[i] == T_DOUBLE) {
432 // ld_off == LSW, ld_off+wordSize == MSW
433 // st_off == MSW, next_off == LSW
434 __ str(rscratch1, Address(sp, next_off));
435 #ifdef ASSERT
436 // Overwrite the unused slot with known junk
437 __ mov(rscratch1, 0xdeadffffdeadaaaaul);
438 __ str(rscratch1, Address(sp, st_off));
439 #endif /* ASSERT */
440 } else {
441 __ str(rscratch1, Address(sp, st_off));
442 }
443 }
444 } else if (r_1->is_Register()) {
445 Register r = r_1->as_Register();
446 if (!r_2->is_valid()) {
447 // must be only an int (or less ) so move only 32bits to slot
448 // why not sign extend??
449 __ str(r, Address(sp, st_off));
450 } else {
451 // Two VMREgs|OptoRegs can be T_OBJECT, T_ADDRESS, T_DOUBLE, T_LONG
452 // T_DOUBLE and T_LONG use two slots in the interpreter
453 if ( sig_bt[i] == T_LONG || sig_bt[i] == T_DOUBLE) {
454 // long/double in gpr
455 #ifdef ASSERT
456 // Overwrite the unused slot with known junk
457 __ mov(rscratch1, 0xdeadffffdeadaaabul);
458 __ str(rscratch1, Address(sp, st_off));
459 #endif /* ASSERT */
460 __ str(r, Address(sp, next_off));
461 } else {
462 __ str(r, Address(sp, st_off));
463 }
464 }
465 } else {
466 assert(r_1->is_FloatRegister(), "");
467 if (!r_2->is_valid()) {
468 // only a float use just part of the slot
469 __ strs(r_1->as_FloatRegister(), Address(sp, st_off));
470 } else {
471 #ifdef ASSERT
472 // Overwrite the unused slot with known junk
473 __ mov(rscratch1, 0xdeadffffdeadaaacul);
474 __ str(rscratch1, Address(sp, st_off));
475 #endif /* ASSERT */
476 __ strd(r_1->as_FloatRegister(), Address(sp, next_off));
477 }
478 }
479 }
480
481 __ mov(esp, sp); // Interp expects args on caller's expression stack
482
483 __ ldr(rscratch1, Address(rmethod, in_bytes(Method::interpreter_entry_offset())));
484 __ br(rscratch1);
485 }
486
487
488 void SharedRuntime::gen_i2c_adapter(MacroAssembler *masm,
489 int total_args_passed,
490 int comp_args_on_stack,
491 const BasicType *sig_bt,
492 const VMRegPair *regs) {
493
494 // Note: r13 contains the senderSP on entry. We must preserve it since
495 // we may do a i2c -> c2i transition if we lose a race where compiled
496 // code goes non-entrant while we get args ready.
497
498 // In addition we use r13 to locate all the interpreter args because
499 // we must align the stack to 16 bytes.
500
501 // Adapters are frameless.
502
503 // An i2c adapter is frameless because the *caller* frame, which is
504 // interpreted, routinely repairs its own esp (from
505 // interpreter_frame_last_sp), even if a callee has modified the
506 // stack pointer. It also recalculates and aligns sp.
507
508 // A c2i adapter is frameless because the *callee* frame, which is
509 // interpreted, routinely repairs its caller's sp (from sender_sp,
510 // which is set up via the senderSP register).
511
512 // In other words, if *either* the caller or callee is interpreted, we can
532 range_check(masm, rax, r11,
533 Interpreter::code()->code_start(), Interpreter::code()->code_end(),
534 L_ok);
535 if (StubRoutines::code1() != NULL)
536 range_check(masm, rax, r11,
537 StubRoutines::code1()->code_begin(), StubRoutines::code1()->code_end(),
538 L_ok);
539 if (StubRoutines::code2() != NULL)
540 range_check(masm, rax, r11,
541 StubRoutines::code2()->code_begin(), StubRoutines::code2()->code_end(),
542 L_ok);
543 const char* msg = "i2c adapter must return to an interpreter frame";
544 __ block_comment(msg);
545 __ stop(msg);
546 __ bind(L_ok);
547 __ block_comment("} verify_i2ce ");
548 #endif
549 }
550
551 // Cut-out for having no stack args.
552 int comp_words_on_stack = align_up(comp_args_on_stack*VMRegImpl::stack_slot_size, wordSize)>>LogBytesPerWord;
553 if (comp_args_on_stack) {
554 __ sub(rscratch1, sp, comp_words_on_stack * wordSize);
555 __ andr(sp, rscratch1, -16);
556 }
557
558 // Will jump to the compiled code just as if compiled code was doing it.
559 // Pre-load the register-jump target early, to schedule it better.
560 __ ldr(rscratch1, Address(rmethod, in_bytes(Method::from_compiled_offset())));
561
562 #if INCLUDE_JVMCI
563 if (EnableJVMCI || UseAOT) {
564 // check if this call should be routed towards a specific entry point
565 __ ldr(rscratch2, Address(rthread, in_bytes(JavaThread::jvmci_alternate_call_target_offset())));
566 Label no_alternative_target;
567 __ cbz(rscratch2, no_alternative_target);
568 __ mov(rscratch1, rscratch2);
569 __ str(zr, Address(rthread, in_bytes(JavaThread::jvmci_alternate_call_target_offset())));
570 __ bind(no_alternative_target);
571 }
572 #endif // INCLUDE_JVMCI
573
574 // Now generate the shuffle code.
575 for (int i = 0; i < total_args_passed; i++) {
576 if (sig_bt[i] == T_VOID) {
577 assert(i > 0 && (sig_bt[i-1] == T_LONG || sig_bt[i-1] == T_DOUBLE), "missing half");
578 continue;
579 }
580
581 // Pick up 0, 1 or 2 words from SP+offset.
582
583 assert(!regs[i].second()->is_valid() || regs[i].first()->next() == regs[i].second(),
584 "scrambled load targets?");
585 // Load in argument order going down.
586 int ld_off = (total_args_passed - i - 1)*Interpreter::stackElementSize;
587 // Point to interpreter value (vs. tag)
588 int next_off = ld_off - Interpreter::stackElementSize;
589 //
590 //
591 //
592 VMReg r_1 = regs[i].first();
593 VMReg r_2 = regs[i].second();
594 if (!r_1->is_valid()) {
595 assert(!r_2->is_valid(), "");
596 continue;
597 }
598 if (r_1->is_stack()) {
599 // Convert stack slot to an SP offset (+ wordSize to account for return address )
600 int st_off = regs[i].first()->reg2stack()*VMRegImpl::stack_slot_size;
601 if (!r_2->is_valid()) {
602 // sign extend???
603 __ ldrsw(rscratch2, Address(esp, ld_off));
604 __ str(rscratch2, Address(sp, st_off));
605 } else {
606 //
607 // We are using two optoregs. This can be either T_OBJECT,
608 // T_ADDRESS, T_LONG, or T_DOUBLE the interpreter allocates
609 // two slots but only uses one for thr T_LONG or T_DOUBLE case
610 // So we must adjust where to pick up the data to match the
611 // interpreter.
612 //
613 // Interpreter local[n] == MSW, local[n+1] == LSW however locals
614 // are accessed as negative so LSW is at LOW address
615
616 // ld_off is MSW so get LSW
617 const int offset = (sig_bt[i]==T_LONG||sig_bt[i]==T_DOUBLE)?
618 next_off : ld_off;
619 __ ldr(rscratch2, Address(esp, offset));
620 // st_off is LSW (i.e. reg.first())
621 __ str(rscratch2, Address(sp, st_off));
622 }
623 } else if (r_1->is_Register()) { // Register argument
624 Register r = r_1->as_Register();
625 if (r_2->is_valid()) {
626 //
627 // We are using two VMRegs. This can be either T_OBJECT,
628 // T_ADDRESS, T_LONG, or T_DOUBLE the interpreter allocates
629 // two slots but only uses one for thr T_LONG or T_DOUBLE case
630 // So we must adjust where to pick up the data to match the
631 // interpreter.
632
633 const int offset = (sig_bt[i]==T_LONG||sig_bt[i]==T_DOUBLE)?
634 next_off : ld_off;
635
636 // this can be a misaligned move
637 __ ldr(r, Address(esp, offset));
638 } else {
639 // sign extend and use a full word?
640 __ ldrw(r, Address(esp, ld_off));
641 }
642 } else {
643 if (!r_2->is_valid()) {
644 __ ldrs(r_1->as_FloatRegister(), Address(esp, ld_off));
645 } else {
646 __ ldrd(r_1->as_FloatRegister(), Address(esp, next_off));
647 }
648 }
649 }
650
651 // 6243940 We might end up in handle_wrong_method if
652 // the callee is deoptimized as we race thru here. If that
653 // happens we don't want to take a safepoint because the
654 // caller frame will look interpreted and arguments are now
655 // "compiled" so it is much better to make this transition
656 // invisible to the stack walking code. Unfortunately if
657 // we try and find the callee by normal means a safepoint
658 // is possible. So we stash the desired callee in the thread
659 // and the vm will find there should this case occur.
660
661 __ str(rmethod, Address(rthread, JavaThread::callee_target_offset()));
662
663 __ br(rscratch1);
664 }
665
666 #ifdef BUILTIN_SIM
667 static void generate_i2c_adapter_name(char *result, int total_args_passed, const BasicType *sig_bt)
668 {
669 strcpy(result, "i2c(");
670 int idx = 4;
671 for (int i = 0; i < total_args_passed; i++) {
672 switch(sig_bt[i]) {
673 case T_BOOLEAN:
674 result[idx++] = 'Z';
675 break;
676 case T_CHAR:
677 result[idx++] = 'C';
678 break;
679 case T_FLOAT:
680 result[idx++] = 'F';
681 break;
682 case T_DOUBLE:
713 result[idx++] = 'N';
714 break;
715 case T_METADATA:
716 result[idx++] = 'M';
717 break;
718 case T_NARROWKLASS:
719 result[idx++] = 'K';
720 break;
721 default:
722 result[idx++] = '?';
723 break;
724 }
725 }
726 result[idx++] = ')';
727 result[idx] = '\0';
728 }
729 #endif
730
731 // ---------------------------------------------------------------
732 AdapterHandlerEntry* SharedRuntime::generate_i2c2i_adapters(MacroAssembler *masm,
733 int total_args_passed,
734 int comp_args_on_stack,
735 const BasicType *sig_bt,
736 const VMRegPair *regs,
737 AdapterFingerPrint* fingerprint) {
738 address i2c_entry = __ pc();
739 #ifdef BUILTIN_SIM
740 char *name = NULL;
741 AArch64Simulator *sim = NULL;
742 size_t len = 65536;
743 if (NotifySimulator) {
744 name = NEW_C_HEAP_ARRAY(char, len, mtInternal);
745 }
746
747 if (name) {
748 generate_i2c_adapter_name(name, total_args_passed, sig_bt);
749 sim = AArch64Simulator::get_current(UseSimulatorCache, DisableBCCheck);
750 sim->notifyCompile(name, i2c_entry);
751 }
752 #endif
753 gen_i2c_adapter(masm, total_args_passed, comp_args_on_stack, sig_bt, regs);
754
755 address c2i_unverified_entry = __ pc();
756 Label skip_fixup;
757
758 Label ok;
759
760 Register holder = rscratch2;
761 Register receiver = j_rarg0;
762 Register tmp = r10; // A call-clobbered register not used for arg passing
763
764 // -------------------------------------------------------------------------
765 // Generate a C2I adapter. On entry we know rmethod holds the Method* during calls
766 // to the interpreter. The args start out packed in the compiled layout. They
767 // need to be unpacked into the interpreter layout. This will almost always
768 // require some stack space. We grow the current (compiled) stack, then repack
769 // the args. We finally end in a jump to the generic interpreter entry point.
770 // On exit from the interpreter, the interpreter will restore our SP (lest the
771 // compiled code, which relys solely on SP and not FP, get sick).
772
773 {
774 __ block_comment("c2i_unverified_entry {");
775 __ load_klass(rscratch1, receiver);
776 __ ldr(tmp, Address(holder, CompiledICHolder::holder_klass_offset()));
777 __ cmp(rscratch1, tmp);
778 __ ldr(rmethod, Address(holder, CompiledICHolder::holder_metadata_offset()));
779 __ br(Assembler::EQ, ok);
780 __ far_jump(RuntimeAddress(SharedRuntime::get_ic_miss_stub()));
781
782 __ bind(ok);
783 // Method might have been compiled since the call site was patched to
784 // interpreted; if that is the case treat it as a miss so we can get
785 // the call site corrected.
786 __ ldr(rscratch1, Address(rmethod, in_bytes(Method::code_offset())));
787 __ cbz(rscratch1, skip_fixup);
788 __ far_jump(RuntimeAddress(SharedRuntime::get_ic_miss_stub()));
789 __ block_comment("} c2i_unverified_entry");
790 }
791
792 address c2i_entry = __ pc();
793
794 #ifdef BUILTIN_SIM
795 if (name) {
796 name[0] = 'c';
797 name[2] = 'i';
798 sim->notifyCompile(name, c2i_entry);
799 FREE_C_HEAP_ARRAY(char, name, mtInternal);
800 }
801 #endif
802
803 gen_c2i_adapter(masm, total_args_passed, comp_args_on_stack, sig_bt, regs, skip_fixup);
804
805 __ flush();
806 return AdapterHandlerLibrary::new_entry(fingerprint, i2c_entry, c2i_entry, c2i_unverified_entry);
807 }
808
809 int SharedRuntime::c_calling_convention(const BasicType *sig_bt,
810 VMRegPair *regs,
811 VMRegPair *regs2,
812 int total_args_passed) {
813 assert(regs2 == NULL, "not needed on AArch64");
814
815 // We return the amount of VMRegImpl stack slots we need to reserve for all
816 // the arguments NOT counting out_preserve_stack_slots.
817
818 static const Register INT_ArgReg[Argument::n_int_register_parameters_c] = {
819 c_rarg0, c_rarg1, c_rarg2, c_rarg3, c_rarg4, c_rarg5, c_rarg6, c_rarg7
820 };
821 static const FloatRegister FP_ArgReg[Argument::n_float_register_parameters_c] = {
822 c_farg0, c_farg1, c_farg2, c_farg3,
823 c_farg4, c_farg5, c_farg6, c_farg7
824 };
825
826 uint int_args = 0;
3179 __ str(zr, Address(rthread, JavaThread::exception_handler_pc_offset()));
3180 __ str(zr, Address(rthread, JavaThread::exception_pc_offset()));
3181 #endif
3182 // Clear the exception oop so GC no longer processes it as a root.
3183 __ str(zr, Address(rthread, JavaThread::exception_oop_offset()));
3184
3185 // r0: exception oop
3186 // r8: exception handler
3187 // r4: exception pc
3188 // Jump to handler
3189
3190 __ br(r8);
3191
3192 // Make sure all code is generated
3193 masm->flush();
3194
3195 // Set exception blob
3196 _exception_blob = ExceptionBlob::create(&buffer, oop_maps, SimpleRuntimeFrame::framesize >> 1);
3197 }
3198 #endif // COMPILER2_OR_JVMCI
|
9 *
10 * This code is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * version 2 for more details (a copy is included in the LICENSE file that
14 * accompanied this code).
15 *
16 * You should have received a copy of the GNU General Public License version
17 * 2 along with this work; if not, write to the Free Software Foundation,
18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 * or visit www.oracle.com if you need additional information or have any
22 * questions.
23 *
24 */
25
26 #include "precompiled.hpp"
27 #include "asm/macroAssembler.hpp"
28 #include "asm/macroAssembler.inline.hpp"
29 #include "classfile/symbolTable.hpp"
30 #include "code/debugInfoRec.hpp"
31 #include "code/icBuffer.hpp"
32 #include "code/vtableStubs.hpp"
33 #include "interpreter/interpreter.hpp"
34 #include "interpreter/interp_masm.hpp"
35 #include "logging/log.hpp"
36 #include "memory/resourceArea.hpp"
37 #include "oops/compiledICHolder.hpp"
38 #include "runtime/safepointMechanism.hpp"
39 #include "runtime/sharedRuntime.hpp"
40 #include "runtime/vframeArray.hpp"
41 #include "utilities/align.hpp"
42 #include "vmreg_aarch64.inline.hpp"
43 #ifdef COMPILER1
44 #include "c1/c1_Runtime1.hpp"
45 #endif
46 #if COMPILER2_OR_JVMCI
47 #include "adfiles/ad_aarch64.hpp"
48 #include "opto/runtime.hpp"
49 #endif
273 case T_SHORT:
274 case T_INT:
275 if (int_args < Argument::n_int_register_parameters_j) {
276 regs[i].set1(INT_ArgReg[int_args++]->as_VMReg());
277 } else {
278 regs[i].set1(VMRegImpl::stack2reg(stk_args));
279 stk_args += 2;
280 }
281 break;
282 case T_VOID:
283 // halves of T_LONG or T_DOUBLE
284 assert(i != 0 && (sig_bt[i - 1] == T_LONG || sig_bt[i - 1] == T_DOUBLE), "expecting half");
285 regs[i].set_bad();
286 break;
287 case T_LONG:
288 assert((i + 1) < total_args_passed && sig_bt[i + 1] == T_VOID, "expecting half");
289 // fall through
290 case T_OBJECT:
291 case T_ARRAY:
292 case T_ADDRESS:
293 case T_VALUETYPE:
294 if (int_args < Argument::n_int_register_parameters_j) {
295 regs[i].set2(INT_ArgReg[int_args++]->as_VMReg());
296 } else {
297 regs[i].set2(VMRegImpl::stack2reg(stk_args));
298 stk_args += 2;
299 }
300 break;
301 case T_FLOAT:
302 if (fp_args < Argument::n_float_register_parameters_j) {
303 regs[i].set1(FP_ArgReg[fp_args++]->as_VMReg());
304 } else {
305 regs[i].set1(VMRegImpl::stack2reg(stk_args));
306 stk_args += 2;
307 }
308 break;
309 case T_DOUBLE:
310 assert((i + 1) < total_args_passed && sig_bt[i + 1] == T_VOID, "expecting half");
311 if (fp_args < Argument::n_float_register_parameters_j) {
312 regs[i].set2(FP_ArgReg[fp_args++]->as_VMReg());
313 } else {
314 regs[i].set2(VMRegImpl::stack2reg(stk_args));
315 stk_args += 2;
316 }
317 break;
318 default:
319 ShouldNotReachHere();
320 break;
321 }
322 }
323
324 return align_up(stk_args, 2);
325 }
326
327
328 // const uint SharedRuntime::java_return_convention_max_int = Argument::n_int_register_parameters_j+1;
329 const uint SharedRuntime::java_return_convention_max_int = 6;
330 const uint SharedRuntime::java_return_convention_max_float = Argument::n_float_register_parameters_j;
331
332 int SharedRuntime::java_return_convention(const BasicType *sig_bt, VMRegPair *regs, int total_args_passed) {
333
334 // Create the mapping between argument positions and
335 // registers.
336 // r1, r2 used to address klasses and states, exclude it from return convention to avoid colision
337
338 static const Register INT_ArgReg[java_return_convention_max_int] = {
339 r0 /* j_rarg7 */, j_rarg6, j_rarg5, j_rarg4, j_rarg3, j_rarg2
340 };
341
342 static const FloatRegister FP_ArgReg[java_return_convention_max_float] = {
343 j_farg0, j_farg1, j_farg2, j_farg3, j_farg4, j_farg5, j_farg6, j_farg7
344 };
345
346 uint int_args = 0;
347 uint fp_args = 0;
348
349 for (int i = 0; i < total_args_passed; i++) {
350 switch (sig_bt[i]) {
351 case T_BOOLEAN:
352 case T_CHAR:
353 case T_BYTE:
354 case T_SHORT:
355 case T_INT:
356 if (int_args < Argument::n_int_register_parameters_j) {
357 regs[i].set1(INT_ArgReg[int_args]->as_VMReg());
358 int_args ++;
359 } else {
360 // Should we have gurantee here?
361 return -1;
362 }
363 break;
364 case T_VOID:
365 // halves of T_LONG or T_DOUBLE
366 assert(i != 0 && (sig_bt[i - 1] == T_LONG || sig_bt[i - 1] == T_DOUBLE), "expecting half");
367 regs[i].set_bad();
368 break;
369 case T_LONG:
370 assert((i + 1) < total_args_passed && sig_bt[i + 1] == T_VOID, "expecting half");
371 // fall through
372 case T_OBJECT:
373 case T_ARRAY:
374 case T_ADDRESS:
375 // Should T_METADATA be added to java_calling_convention as well ?
376 case T_METADATA:
377 case T_VALUETYPE:
378 if (int_args < Argument::n_int_register_parameters_j) {
379 regs[i].set2(INT_ArgReg[int_args]->as_VMReg());
380 int_args ++;
381 } else {
382 return -1;
383 }
384 break;
385 case T_FLOAT:
386 if (fp_args < Argument::n_float_register_parameters_j) {
387 regs[i].set1(FP_ArgReg[fp_args]->as_VMReg());
388 fp_args ++;
389 } else {
390 return -1;
391 }
392 break;
393 case T_DOUBLE:
394 assert((i + 1) < total_args_passed && sig_bt[i + 1] == T_VOID, "expecting half");
395 if (fp_args < Argument::n_float_register_parameters_j) {
396 regs[i].set2(FP_ArgReg[fp_args]->as_VMReg());
397 fp_args ++;
398 } else {
399 return -1;
400 }
401 break;
402 default:
403 ShouldNotReachHere();
404 break;
405 }
406 }
407
408 return int_args + fp_args;
409 }
410
411 // Patch the callers callsite with entry to compiled code if it exists.
412 static void patch_callers_callsite(MacroAssembler *masm) {
413 Label L;
414 __ ldr(rscratch1, Address(rmethod, in_bytes(Method::code_offset())));
415 __ cbz(rscratch1, L);
416
417 __ enter();
418 __ push_CPU_state();
419
420 // VM needs caller's callsite
421 // VM needs target method
422 // This needs to be a long call since we will relocate this adapter to
423 // the codeBuffer and it may not reach
424
425 #ifndef PRODUCT
426 assert(frame::arg_reg_save_area_bytes == 0, "not expecting frame reg save area");
427 #endif
428
429 __ mov(c_rarg0, rmethod);
430 __ mov(c_rarg1, lr);
431 __ lea(rscratch1, RuntimeAddress(CAST_FROM_FN_PTR(address, SharedRuntime::fixup_callers_callsite)));
432 __ blrt(rscratch1, 2, 0, 0);
433 __ maybe_isb();
434
435 __ pop_CPU_state();
436 // restore sp
437 __ leave();
438 __ bind(L);
439 }
440
441 // For each value type argument, sig includes the list of fields of
442 // the value type. This utility function computes the number of
443 // arguments for the call if value types are passed by reference (the
444 // calling convention the interpreter expects).
445 static int compute_total_args_passed_int(const GrowableArray<SigEntry>* sig_extended) {
446 int total_args_passed = 0;
447 if (ValueTypePassFieldsAsArgs) {
448 for (int i = 0; i < sig_extended->length(); i++) {
449 BasicType bt = sig_extended->at(i)._bt;
450 if (SigEntry::is_reserved_entry(sig_extended, i)) {
451 // Ignore reserved entry
452 } else if (bt == T_VALUETYPE) {
453 // In sig_extended, a value type argument starts with:
454 // T_VALUETYPE, followed by the types of the fields of the
455 // value type and T_VOID to mark the end of the value
456 // type. Value types are flattened so, for instance, in the
457 // case of a value type with an int field and a value type
458 // field that itself has 2 fields, an int and a long:
459 // T_VALUETYPE T_INT T_VALUETYPE T_INT T_LONG T_VOID (second
460 // slot for the T_LONG) T_VOID (inner T_VALUETYPE) T_VOID
461 // (outer T_VALUETYPE)
462 total_args_passed++;
463 int vt = 1;
464 do {
465 i++;
466 BasicType bt = sig_extended->at(i)._bt;
467 BasicType prev_bt = sig_extended->at(i-1)._bt;
468 if (bt == T_VALUETYPE) {
469 vt++;
470 } else if (bt == T_VOID &&
471 prev_bt != T_LONG &&
472 prev_bt != T_DOUBLE) {
473 vt--;
474 }
475 } while (vt != 0);
476 } else {
477 total_args_passed++;
478 }
479 }
480 } else {
481 total_args_passed = sig_extended->length();
482 }
483
484 return total_args_passed;
485 }
486
487
488 static void gen_c2i_adapter_helper(MacroAssembler* masm, BasicType bt, const VMRegPair& reg_pair, int extraspace, const Address& to) {
489
490 assert(bt != T_VALUETYPE || !ValueTypePassFieldsAsArgs, "no value type here");
491
492 // Say 4 args:
493 // i st_off
494 // 0 32 T_LONG
495 // 1 24 T_VOID
496 // 2 16 T_OBJECT
497 // 3 8 T_BOOL
498 // - 0 return address
499 //
500 // However to make thing extra confusing. Because we can fit a long/double in
501 // a single slot on a 64 bt vm and it would be silly to break them up, the interpreter
502 // leaves one slot empty and only stores to a single slot. In this case the
503 // slot that is occupied is the T_VOID slot. See I said it was confusing.
504
505 // int next_off = st_off - Interpreter::stackElementSize;
506
507 VMReg r_1 = reg_pair.first();
508 VMReg r_2 = reg_pair.second();
509
510 if (!r_1->is_valid()) {
511 assert(!r_2->is_valid(), "");
512 return;
513 }
514
515 if (r_1->is_stack()) {
516 // memory to memory use rscratch1
517 // DMS CHECK: words_pushed is always 0 ?
518 // int ld_off = (r_1->reg2stack() * VMRegImpl::stack_slot_size + extraspace + words_pushed * wordSize);
519 int ld_off = (r_1->reg2stack() * VMRegImpl::stack_slot_size + extraspace);
520 if (!r_2->is_valid()) {
521 // sign extend??
522 __ ldrw(rscratch1, Address(sp, ld_off));
523 __ str(rscratch1, to);
524
525 } else {
526 __ ldr(rscratch1, Address(sp, ld_off));
527 __ str(rscratch1, to);
528 }
529 } else if (r_1->is_Register()) {
530 Register r = r_1->as_Register();
531 __ str(r, to);
532
533 // DMS CHECK: removed redundant if
534 //if (!r_2->is_valid()) {
535 // // must be only an int (or less ) so move only 32bits to slot
536 // // why not sign extend??
537 // __ str(r, to);
538 // } else {
539 // __ str(r, to);
540 // }
541 } else {
542 assert(r_1->is_FloatRegister(), "");
543 if (!r_2->is_valid()) {
544 // only a float use just part of the slot
545 __ strs(r_1->as_FloatRegister(), to);
546 } else {
547 __ strd(r_1->as_FloatRegister(), to);
548 }
549 }
550 }
551
552 static void gen_c2i_adapter(MacroAssembler *masm,
553 const GrowableArray<SigEntry>* sig_extended,
554 const VMRegPair *regs,
555 Label& skip_fixup,
556 address start,
557 OopMapSet* oop_maps,
558 int& frame_complete,
559 int& frame_size_in_words,
560 bool alloc_value_receiver) {
561
562 // Before we get into the guts of the C2I adapter, see if we should be here
563 // at all. We've come from compiled code and are attempting to jump to the
564 // interpreter, which means the caller made a static call to get here
565 // (vcalls always get a compiled target if there is one). Check for a
566 // compiled target. If there is one, we need to patch the caller's call.
567 patch_callers_callsite(masm);
568
569 __ bind(skip_fixup);
570
571 bool has_value_argument = false;
572 if (ValueTypePassFieldsAsArgs) {
573 // Is there a value type argument?
574 for (int i = 0; i < sig_extended->length() && !has_value_argument; i++) {
575 has_value_argument = (sig_extended->at(i)._bt == T_VALUETYPE);
576 }
577 if (has_value_argument) {
578 // There is at least a value type argument: we're coming from
579 // compiled code so we have no buffers to back the value
580 // types. Allocate the buffers here with a runtime call.
581 OopMap* map = RegisterSaver::save_live_registers(masm, 0, &frame_size_in_words);
582
583 frame_complete = __ offset();
584 address the_pc = __ pc();
585
586 __ set_last_Java_frame(noreg, noreg, the_pc, rscratch1);
587
588 __ mov(c_rarg0, rthread);
589 __ mov(c_rarg1, r1);
590 __ mov(c_rarg2, (int64_t)alloc_value_receiver);
591
592 __ lea(rscratch1, RuntimeAddress(CAST_FROM_FN_PTR(address, SharedRuntime::allocate_value_types)));
593 __ blrt(rscratch1, 3, 0, 1);
594
595 oop_maps->add_gc_map((int)(__ pc() - start), map);
596 __ reset_last_Java_frame(false);
597
598 RegisterSaver::restore_live_registers(masm);
599
600 Label no_exception;
601 __ ldr(r0, Address(rthread, Thread::pending_exception_offset()));
602 __ cbz(r0, no_exception);
603
604 __ str(zr, Address(rthread, JavaThread::vm_result_offset()));
605 __ ldr(r0, Address(rthread, Thread::pending_exception_offset()));
606 __ b(RuntimeAddress(StubRoutines::forward_exception_entry()));
607
608 __ bind(no_exception);
609
610 // We get an array of objects from the runtime call
611 __ get_vm_result(r10, rthread);
612 __ get_vm_result_2(r1, rthread); // TODO: required to keep the callee Method live?
613 }
614 }
615
616 int words_pushed = 0;
617
618 // Since all args are passed on the stack, total_args_passed *
619 // Interpreter::stackElementSize is the space we need.
620
621 int total_args_passed = compute_total_args_passed_int(sig_extended);
622 int extraspace = total_args_passed * Interpreter::stackElementSize;
623
624 __ mov(r13, sp);
625
626 // stack is aligned, keep it that way
627 extraspace = align_up(extraspace, 2 * wordSize);
628 if (extraspace)
629 __ sub(sp, sp, extraspace);
630
631 // Now write the args into the outgoing interpreter space
632
633 int ignored = 0, next_vt_arg = 0, next_arg_int = 0;
634 bool has_oop_field = false;
635
636 for (int next_arg_comp = 0; next_arg_comp < total_args_passed; next_arg_comp++) {
637 BasicType bt = sig_extended->at(next_arg_comp)._bt;
638 // offset to start parameters
639 int st_off = (total_args_passed - next_arg_int - 1) * Interpreter::stackElementSize;
640
641 if (!ValueTypePassFieldsAsArgs || bt != T_VALUETYPE) {
642 if (SigEntry::is_reserved_entry(sig_extended, next_arg_comp)) {
643 continue; // Ignore reserved entry
644 }
645
646 if (bt == T_VOID) {
647 assert(next_arg_comp > 0 && (sig_extended->at(next_arg_comp - 1)._bt == T_LONG || sig_extended->at(next_arg_comp - 1)._bt == T_DOUBLE), "missing half");
648 next_arg_int ++;
649 continue;
650 }
651
652 int next_off = st_off - Interpreter::stackElementSize;
653 int offset = (bt == T_LONG || bt == T_DOUBLE) ? next_off : st_off;
654
655 gen_c2i_adapter_helper(masm, bt, regs[next_arg_comp], extraspace, Address(sp, offset));
656 next_arg_int ++;
657
658 } else {
659 ignored++;
660 // get the buffer from the just allocated pool of buffers
661 int index = arrayOopDesc::base_offset_in_bytes(T_OBJECT) + next_vt_arg * type2aelembytes(T_VALUETYPE);
662 // DMS CHECK: Is r11 correct register here and below?
663 __ load_heap_oop(r11, Address(r10, index));
664 next_vt_arg++;
665 next_arg_int++;
666 int vt = 1;
667 // write fields we get from compiled code in registers/stack
668 // slots to the buffer: we know we are done with that value type
669 // argument when we hit the T_VOID that acts as an end of value
670 // type delimiter for this value type. Value types are flattened
671 // so we might encounter embedded value types. Each entry in
672 // sig_extended contains a field offset in the buffer.
673 do {
674 next_arg_comp++;
675 BasicType bt = sig_extended->at(next_arg_comp)._bt;
676 BasicType prev_bt = sig_extended->at(next_arg_comp - 1)._bt;
677 if (bt == T_VALUETYPE) {
678 vt++;
679 ignored++;
680 } else if (bt == T_VOID && prev_bt != T_LONG && prev_bt != T_DOUBLE) {
681 vt--;
682 ignored++;
683 } else if (SigEntry::is_reserved_entry(sig_extended, next_arg_comp)) {
684 // Ignore reserved entry
685 } else {
686 int off = sig_extended->at(next_arg_comp)._offset;
687 assert(off > 0, "offset in object should be positive");
688 gen_c2i_adapter_helper(masm, bt, regs[next_arg_comp - ignored], extraspace, Address(r11, off));
689 }
690 } while (vt != 0);
691 // pass the buffer to the interpreter
692 __ str(r11, Address(sp, st_off));
693 }
694
695 }
696
697 // If a value type was allocated and initialized, apply post barrier to all oop fields
698 if (has_value_argument && has_oop_field) {
699 __ push(r13); // save senderSP
700 __ push(r1); // save callee
701 // Allocate argument register save area
702 if (frame::arg_reg_save_area_bytes != 0) {
703 __ sub(sp, sp, frame::arg_reg_save_area_bytes);
704 }
705 __ call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::apply_post_barriers), rthread, r10);
706 // De-allocate argument register save area
707 if (frame::arg_reg_save_area_bytes != 0) {
708 __ add(sp, sp, frame::arg_reg_save_area_bytes);
709 }
710 __ pop(r1); // restore callee
711 __ pop(r13); // restore sender SP
712 }
713
714
715 __ mov(esp, sp); // Interp expects args on caller's expression stack
716
717 __ ldr(rscratch1, Address(rmethod, in_bytes(Method::interpreter_entry_offset())));
718 __ br(rscratch1);
719 }
720
721
722 static void gen_i2c_adapter_helper(MacroAssembler* masm, BasicType bt, const VMRegPair& reg_pair, const Address& from) {
723
724 assert(bt != T_VALUETYPE || !ValueTypePassFieldsAsArgs, "no value type here");
725
726 VMReg r_1 = reg_pair.first();
727 VMReg r_2 = reg_pair.second();
728 if (!r_1->is_valid()) {
729 assert(!r_2->is_valid(), "");
730 return;
731 }
732
733 if (r_1->is_stack()) {
734 // Convert stack slot to an SP offset (+ wordSize to account for return address )
735 int st_off = r_1->reg2stack() * VMRegImpl::stack_slot_size;
736 if (!r_2->is_valid()) {
737 // sign extend???
738 __ ldrsw(rscratch2, from);
739 __ str(rscratch2, Address(sp, st_off));
740 } else {
741 //
742 // We are using two optoregs. This can be either T_OBJECT,
743 // T_ADDRESS, T_LONG, or T_DOUBLE the interpreter allocates
744 // two slots but only uses one for thr T_LONG or T_DOUBLE case
745 // So we must adjust where to pick up the data to match the
746 // interpreter.
747 //
748 // Interpreter local[n] == MSW, local[n+1] == LSW however locals
749 // are accessed as negative so LSW is at LOW address
750
751 // ld_off is MSW so get LSW
752 __ ldr(rscratch2, from);
753 // st_off is LSW (i.e. reg.first())
754 __ str(rscratch2, Address(sp, st_off));
755 }
756 } else if (r_1->is_Register()) { // Register argument
757 Register r = r_1->as_Register();
758 if (r_2->is_valid()) {
759 //
760 // We are using two VMRegs. This can be either T_OBJECT,
761 // T_ADDRESS, T_LONG, or T_DOUBLE the interpreter allocates
762 // two slots but only uses one for thr T_LONG or T_DOUBLE case
763 // So we must adjust where to pick up the data to match the
764 // interpreter.
765 // this can be a misaligned move
766 __ ldr(r, from);
767 } else {
768 // sign extend and use a full word?
769 __ ldrw(r, from);
770 }
771 } else {
772 if (!r_2->is_valid()) {
773 __ ldrs(r_1->as_FloatRegister(), from);
774 } else {
775 __ ldrd(r_1->as_FloatRegister(), from);
776 }
777 }
778 }
779
780 void SharedRuntime::gen_i2c_adapter(MacroAssembler *masm, int comp_args_on_stack, const GrowableArray<SigEntry>* sig, const VMRegPair *regs) {
781
782
783 // Note: r13 contains the senderSP on entry. We must preserve it since
784 // we may do a i2c -> c2i transition if we lose a race where compiled
785 // code goes non-entrant while we get args ready.
786
787 // In addition we use r13 to locate all the interpreter args because
788 // we must align the stack to 16 bytes.
789
790 // Adapters are frameless.
791
792 // An i2c adapter is frameless because the *caller* frame, which is
793 // interpreted, routinely repairs its own esp (from
794 // interpreter_frame_last_sp), even if a callee has modified the
795 // stack pointer. It also recalculates and aligns sp.
796
797 // A c2i adapter is frameless because the *callee* frame, which is
798 // interpreted, routinely repairs its caller's sp (from sender_sp,
799 // which is set up via the senderSP register).
800
801 // In other words, if *either* the caller or callee is interpreted, we can
821 range_check(masm, rax, r11,
822 Interpreter::code()->code_start(), Interpreter::code()->code_end(),
823 L_ok);
824 if (StubRoutines::code1() != NULL)
825 range_check(masm, rax, r11,
826 StubRoutines::code1()->code_begin(), StubRoutines::code1()->code_end(),
827 L_ok);
828 if (StubRoutines::code2() != NULL)
829 range_check(masm, rax, r11,
830 StubRoutines::code2()->code_begin(), StubRoutines::code2()->code_end(),
831 L_ok);
832 const char* msg = "i2c adapter must return to an interpreter frame";
833 __ block_comment(msg);
834 __ stop(msg);
835 __ bind(L_ok);
836 __ block_comment("} verify_i2ce ");
837 #endif
838 }
839
840 // Cut-out for having no stack args.
841 int comp_words_on_stack = align_up(comp_args_on_stack*VMRegImpl::stack_slot_size, wordSize) >> LogBytesPerWord;
842 if (comp_args_on_stack) {
843 __ sub(rscratch1, sp, comp_words_on_stack * wordSize);
844 __ andr(sp, rscratch1, -16);
845 }
846
847 // Will jump to the compiled code just as if compiled code was doing it.
848 // Pre-load the register-jump target early, to schedule it better.
849 __ ldr(rscratch1, Address(rmethod, in_bytes(Method::from_compiled_offset())));
850
851 #if INCLUDE_JVMCI
852 if (EnableJVMCI || UseAOT) {
853 // check if this call should be routed towards a specific entry point
854 __ ldr(rscratch2, Address(rthread, in_bytes(JavaThread::jvmci_alternate_call_target_offset())));
855 Label no_alternative_target;
856 __ cbz(rscratch2, no_alternative_target);
857 __ mov(rscratch1, rscratch2);
858 __ str(zr, Address(rthread, in_bytes(JavaThread::jvmci_alternate_call_target_offset())));
859 __ bind(no_alternative_target);
860 }
861 #endif // INCLUDE_JVMCI
862
863 int total_args_passed = compute_total_args_passed_int(sig);
864
865 int ignored = 0, next_arg_int = 0;
866
867 // Now generate the shuffle code.
868 for (int next_arg_comp = 0; next_arg_comp < total_args_passed; next_arg_comp++) {
869
870 assert(ignored <= next_arg_comp, "shouldn't skip over more slots than there are arguments");
871 assert(next_arg_int <= total_args_passed, "more arguments from the interpreter than expected?");
872
873 BasicType bt = sig->at(next_arg_comp)._bt;
874 int ld_off = (total_args_passed - next_arg_int - 1) * Interpreter::stackElementSize;
875 // Pick up 0, 1 or 2 words from SP+offset.
876 assert(!regs[next_arg_comp].second()->is_valid() || regs[next_arg_comp].first()->next() == regs[next_arg_comp].second(), "scrambled load targets?");
877 //
878 if (!ValueTypePassFieldsAsArgs || bt != T_VALUETYPE) {
879 // Load in argument order going down.
880 // Point to interpreter value (vs. tag)
881 if (SigEntry::is_reserved_entry(sig, next_arg_comp)) {
882 continue; // Ignore reserved entry
883 }
884
885 if (bt == T_VOID) {
886 assert(next_arg_comp > 0 && (sig->at(next_arg_comp - 1)._bt == T_LONG || sig->at(next_arg_comp - 1)._bt == T_DOUBLE), "missing half");
887 next_arg_int++;
888 continue;
889 }
890
891 int next_off = ld_off - Interpreter::stackElementSize;
892 int offset = (bt == T_LONG || bt == T_DOUBLE) ? next_off : ld_off;
893
894 gen_i2c_adapter_helper(masm, bt, regs[next_arg_comp - ignored], Address(esp, offset));
895
896 next_arg_int++;
897 } else {
898 next_arg_int++;
899 ignored++;
900 // get the buffer for that value type
901 __ ldr(r10, Address(sp, ld_off));
902 int vt = 1;
903 // load fields to registers/stack slots from the buffer: we know
904 // we are done with that value type argument when we hit the
905 // T_VOID that acts as an end of value type delimiter for this
906 // value type. Value types are flattened so we might encounter
907 // embedded value types. Each entry in sig_extended contains a
908 // field offset in the buffer.
909 do {
910 next_arg_comp++;
911 BasicType bt = sig->at(next_arg_comp)._bt;
912 BasicType prev_bt = sig->at(next_arg_comp - 1)._bt;
913 BasicType bt_int = sig->at(next_arg_int)._bt;
914
915 if (bt == T_VALUETYPE) {
916 vt++;
917 ignored++;
918 } else if (bt == T_VOID && prev_bt != T_LONG && prev_bt != T_DOUBLE) {
919 vt--;
920 ignored++;
921 } else if (SigEntry::is_reserved_entry(sig, next_arg_comp)) {
922 // Ignore reserved entry
923 } else {
924 int off = sig->at(next_arg_comp)._offset;
925 assert(off > 0, "offset in object should be positive");
926 gen_i2c_adapter_helper(masm, bt, regs[next_arg_comp - ignored], Address(r10, off));
927 }
928 } while (vt != 0);
929 }
930 } // for
931
932 // 6243940 We might end up in handle_wrong_method if
933 // the callee is deoptimized as we race thru here. If that
934 // happens we don't want to take a safepoint because the
935 // caller frame will look interpreted and arguments are now
936 // "compiled" so it is much better to make this transition
937 // invisible to the stack walking code. Unfortunately if
938 // we try and find the callee by normal means a safepoint
939 // is possible. So we stash the desired callee in the thread
940 // and the vm will find there should this case occur.
941
942 __ str(rmethod, Address(rthread, JavaThread::callee_target_offset()));
943 __ br(rscratch1);
944 }
945
946 #ifdef BUILTIN_SIM
947 static void generate_i2c_adapter_name(char *result, int total_args_passed, const BasicType *sig_bt)
948 {
949 strcpy(result, "i2c(");
950 int idx = 4;
951 for (int i = 0; i < total_args_passed; i++) {
952 switch(sig_bt[i]) {
953 case T_BOOLEAN:
954 result[idx++] = 'Z';
955 break;
956 case T_CHAR:
957 result[idx++] = 'C';
958 break;
959 case T_FLOAT:
960 result[idx++] = 'F';
961 break;
962 case T_DOUBLE:
993 result[idx++] = 'N';
994 break;
995 case T_METADATA:
996 result[idx++] = 'M';
997 break;
998 case T_NARROWKLASS:
999 result[idx++] = 'K';
1000 break;
1001 default:
1002 result[idx++] = '?';
1003 break;
1004 }
1005 }
1006 result[idx++] = ')';
1007 result[idx] = '\0';
1008 }
1009 #endif
1010
1011 // ---------------------------------------------------------------
1012 AdapterHandlerEntry* SharedRuntime::generate_i2c2i_adapters(MacroAssembler *masm,
1013 int comp_args_on_stack,
1014 int comp_args_on_stack_cc,
1015 const GrowableArray<SigEntry>* sig,
1016 const VMRegPair* regs,
1017 const GrowableArray<SigEntry>* sig_cc,
1018 const VMRegPair* regs_cc,
1019 const GrowableArray<SigEntry>* sig_cc_ro,
1020 const VMRegPair* regs_cc_ro,
1021 AdapterFingerPrint* fingerprint,
1022 AdapterBlob*& new_adapter) {
1023 address i2c_entry = __ pc();
1024 gen_i2c_adapter(masm, comp_args_on_stack_cc, sig_cc, regs_cc);
1025
1026 address c2i_unverified_entry = __ pc();
1027 Label skip_fixup;
1028
1029 Label ok;
1030
1031 Register holder = rscratch2;
1032 Register receiver = j_rarg0;
1033 Register tmp = r10; // A call-clobbered register not used for arg passing
1034
1035 // -------------------------------------------------------------------------
1036 // Generate a C2I adapter. On entry we know rmethod holds the Method* during calls
1037 // to the interpreter. The args start out packed in the compiled layout. They
1038 // need to be unpacked into the interpreter layout. This will almost always
1039 // require some stack space. We grow the current (compiled) stack, then repack
1040 // the args. We finally end in a jump to the generic interpreter entry point.
1041 // On exit from the interpreter, the interpreter will restore our SP (lest the
1042 // compiled code, which relys solely on SP and not FP, get sick).
1043
1044 {
1045 __ block_comment("c2i_unverified_entry {");
1046 __ load_klass(rscratch1, receiver);
1047 __ ldr(tmp, Address(holder, CompiledICHolder::holder_klass_offset()));
1048 __ cmp(rscratch1, tmp);
1049 __ ldr(rmethod, Address(holder, CompiledICHolder::holder_metadata_offset()));
1050 __ br(Assembler::EQ, ok);
1051 __ far_jump(RuntimeAddress(SharedRuntime::get_ic_miss_stub()));
1052
1053 __ bind(ok);
1054 // Method might have been compiled since the call site was patched to
1055 // interpreted; if that is the case treat it as a miss so we can get
1056 // the call site corrected.
1057 __ ldr(rscratch1, Address(rmethod, in_bytes(Method::code_offset())));
1058 __ cbz(rscratch1, skip_fixup);
1059 __ far_jump(RuntimeAddress(SharedRuntime::get_ic_miss_stub()));
1060 __ block_comment("} c2i_unverified_entry");
1061 }
1062
1063
1064 OopMapSet* oop_maps = new OopMapSet();
1065 int frame_complete = CodeOffsets::frame_never_safe;
1066 int frame_size_in_words = 0;
1067
1068 // Scalarized c2i adapter with non-scalarized receiver (i.e., don't pack receiver)
1069 address c2i_value_ro_entry = __ pc();
1070 if (regs_cc != regs_cc_ro) {
1071 Label unused;
1072 gen_c2i_adapter(masm, sig_cc_ro, regs_cc_ro, skip_fixup, i2c_entry, oop_maps, frame_complete, frame_size_in_words, false);
1073 skip_fixup = unused;
1074 }
1075
1076 // Scalarized c2i adapter
1077 address c2i_entry = __ pc();
1078 gen_c2i_adapter(masm, sig_cc, regs_cc, skip_fixup, i2c_entry, oop_maps, frame_complete, frame_size_in_words, true);
1079
1080 // Non-scalarized c2i adapter
1081 address c2i_value_entry = c2i_entry;
1082 if (regs != regs_cc) {
1083 c2i_value_entry = __ pc();
1084 Label unused;
1085 gen_c2i_adapter(masm, sig, regs, unused, i2c_entry, oop_maps, frame_complete, frame_size_in_words, false);
1086 }
1087
1088 __ flush();
1089
1090 // The c2i adapter might safepoint and trigger a GC. The caller must make sure that
1091 // the GC knows about the location of oop argument locations passed to the c2i adapter.
1092 bool caller_must_gc_arguments = (regs != regs_cc);
1093 new_adapter = AdapterBlob::create(masm->code(), frame_complete, frame_size_in_words, oop_maps, caller_must_gc_arguments);
1094 return AdapterHandlerLibrary::new_entry(fingerprint, i2c_entry, c2i_entry, c2i_value_entry, c2i_value_ro_entry, c2i_unverified_entry);
1095 }
1096
1097 int SharedRuntime::c_calling_convention(const BasicType *sig_bt,
1098 VMRegPair *regs,
1099 VMRegPair *regs2,
1100 int total_args_passed) {
1101 assert(regs2 == NULL, "not needed on AArch64");
1102
1103 // We return the amount of VMRegImpl stack slots we need to reserve for all
1104 // the arguments NOT counting out_preserve_stack_slots.
1105
1106 static const Register INT_ArgReg[Argument::n_int_register_parameters_c] = {
1107 c_rarg0, c_rarg1, c_rarg2, c_rarg3, c_rarg4, c_rarg5, c_rarg6, c_rarg7
1108 };
1109 static const FloatRegister FP_ArgReg[Argument::n_float_register_parameters_c] = {
1110 c_farg0, c_farg1, c_farg2, c_farg3,
1111 c_farg4, c_farg5, c_farg6, c_farg7
1112 };
1113
1114 uint int_args = 0;
3467 __ str(zr, Address(rthread, JavaThread::exception_handler_pc_offset()));
3468 __ str(zr, Address(rthread, JavaThread::exception_pc_offset()));
3469 #endif
3470 // Clear the exception oop so GC no longer processes it as a root.
3471 __ str(zr, Address(rthread, JavaThread::exception_oop_offset()));
3472
3473 // r0: exception oop
3474 // r8: exception handler
3475 // r4: exception pc
3476 // Jump to handler
3477
3478 __ br(r8);
3479
3480 // Make sure all code is generated
3481 masm->flush();
3482
3483 // Set exception blob
3484 _exception_blob = ExceptionBlob::create(&buffer, oop_maps, SimpleRuntimeFrame::framesize >> 1);
3485 }
3486 #endif // COMPILER2_OR_JVMCI
3487
3488 BufferedValueTypeBlob* SharedRuntime::generate_buffered_value_type_adapter(const ValueKlass* vk) {
3489 BufferBlob* buf = BufferBlob::create("value types pack/unpack", 16 * K);
3490 CodeBuffer buffer(buf);
3491 short buffer_locs[20];
3492 buffer.insts()->initialize_shared_locs((relocInfo*)buffer_locs,
3493 sizeof(buffer_locs)/sizeof(relocInfo));
3494
3495 MacroAssembler _masm(&buffer);
3496 MacroAssembler* masm = &_masm;
3497
3498 const Array<SigEntry>* sig_vk = vk->extended_sig();
3499 const Array<VMRegPair>* regs = vk->return_regs();
3500
3501 int pack_fields_off = __ offset();
3502
3503 int j = 1;
3504 for (int i = 0; i < sig_vk->length(); i++) {
3505 BasicType bt = sig_vk->at(i)._bt;
3506 if (bt == T_VALUETYPE) {
3507 continue;
3508 }
3509 if (bt == T_VOID) {
3510 if (sig_vk->at(i-1)._bt == T_LONG ||
3511 sig_vk->at(i-1)._bt == T_DOUBLE) {
3512 j++;
3513 }
3514 continue;
3515 }
3516 int off = sig_vk->at(i)._offset;
3517 VMRegPair pair = regs->at(j);
3518 VMReg r_1 = pair.first();
3519 VMReg r_2 = pair.second();
3520 Address to(r0, off);
3521 if (bt == T_FLOAT) {
3522 __ strs(r_1->as_FloatRegister(), to);
3523 } else if (bt == T_DOUBLE) {
3524 __ strd(r_1->as_FloatRegister(), to);
3525 } else if (bt == T_OBJECT || bt == T_ARRAY) {
3526 Register val = r_1->as_Register();
3527 assert_different_registers(r0, val);
3528 // We don't need barriers because the destination is a newly allocated object.
3529 // Also, we cannot use store_heap_oop(to, val) because it uses r8 as tmp.
3530 if (UseCompressedOops) {
3531 __ encode_heap_oop(val);
3532 __ str(val, to);
3533 } else {
3534 __ str(val, to);
3535 }
3536 } else {
3537 assert(is_java_primitive(bt), "unexpected basic type");
3538 assert_different_registers(r0, r_1->as_Register());
3539 size_t size_in_bytes = type2aelembytes(bt);
3540 __ store_sized_value(to, r_1->as_Register(), size_in_bytes);
3541 }
3542 j++;
3543 }
3544 assert(j == regs->length(), "missed a field?");
3545
3546 __ ret(lr);
3547
3548 int unpack_fields_off = __ offset();
3549
3550 j = 1;
3551 for (int i = 0; i < sig_vk->length(); i++) {
3552 BasicType bt = sig_vk->at(i)._bt;
3553 if (bt == T_VALUETYPE) {
3554 continue;
3555 }
3556 if (bt == T_VOID) {
3557 if (sig_vk->at(i-1)._bt == T_LONG ||
3558 sig_vk->at(i-1)._bt == T_DOUBLE) {
3559 j++;
3560 }
3561 continue;
3562 }
3563 int off = sig_vk->at(i)._offset;
3564 VMRegPair pair = regs->at(j);
3565 VMReg r_1 = pair.first();
3566 VMReg r_2 = pair.second();
3567 Address from(r0, off);
3568 if (bt == T_FLOAT) {
3569 __ ldrs(r_1->as_FloatRegister(), from);
3570 } else if (bt == T_DOUBLE) {
3571 __ ldrd(r_1->as_FloatRegister(), from);
3572 } else if (bt == T_OBJECT || bt == T_ARRAY) {
3573 assert_different_registers(r0, r_1->as_Register());
3574 __ load_heap_oop(r_1->as_Register(), from);
3575 } else {
3576 assert(is_java_primitive(bt), "unexpected basic type");
3577 assert_different_registers(r0, r_1->as_Register());
3578
3579 size_t size_in_bytes = type2aelembytes(bt);
3580 __ load_sized_value(r_1->as_Register(), from, size_in_bytes, bt != T_CHAR && bt != T_BOOLEAN);
3581 }
3582 j++;
3583 }
3584 assert(j == regs->length(), "missed a field?");
3585
3586 if (StressValueTypeReturnedAsFields) {
3587 __ load_klass(r0, r0);
3588 __ orr(r0, r0, 1);
3589 }
3590
3591 __ ret(lr);
3592
3593 __ flush();
3594
3595 return BufferedValueTypeBlob::create(&buffer, pack_fields_off, unpack_fields_off);
3596 }
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