541
542 switch (c->type()) {
543 case T_INT: {
544 assert(patch_code == lir_patch_none, "no patching handled here");
545 __ movw(dest->as_register(), c->as_jint());
546 break;
547 }
548
549 case T_ADDRESS: {
550 assert(patch_code == lir_patch_none, "no patching handled here");
551 __ mov(dest->as_register(), c->as_jint());
552 break;
553 }
554
555 case T_LONG: {
556 assert(patch_code == lir_patch_none, "no patching handled here");
557 __ mov(dest->as_register_lo(), (intptr_t)c->as_jlong());
558 break;
559 }
560
561 case T_OBJECT: {
562 if (patch_code == lir_patch_none) {
563 jobject2reg(c->as_jobject(), dest->as_register());
564 } else {
565 jobject2reg_with_patching(dest->as_register(), info);
566 }
567 break;
568 }
569
570 case T_METADATA: {
571 if (patch_code != lir_patch_none) {
572 klass2reg_with_patching(dest->as_register(), info);
573 } else {
574 __ mov_metadata(dest->as_register(), c->as_metadata());
575 }
576 break;
577 }
578
579 case T_FLOAT: {
580 if (__ operand_valid_for_float_immediate(c->as_jfloat())) {
587 }
588
589 case T_DOUBLE: {
590 if (__ operand_valid_for_float_immediate(c->as_jdouble())) {
591 __ fmovd(dest->as_double_reg(), (c->as_jdouble()));
592 } else {
593 __ adr(rscratch1, InternalAddress(double_constant(c->as_jdouble())));
594 __ ldrd(dest->as_double_reg(), Address(rscratch1));
595 }
596 break;
597 }
598
599 default:
600 ShouldNotReachHere();
601 }
602 }
603
604 void LIR_Assembler::const2stack(LIR_Opr src, LIR_Opr dest) {
605 LIR_Const* c = src->as_constant_ptr();
606 switch (c->type()) {
607 case T_OBJECT:
608 {
609 if (! c->as_jobject())
610 __ str(zr, frame_map()->address_for_slot(dest->single_stack_ix()));
611 else {
612 const2reg(src, FrameMap::rscratch1_opr, lir_patch_none, NULL);
613 reg2stack(FrameMap::rscratch1_opr, dest, c->type(), false);
614 }
615 }
616 break;
617 case T_ADDRESS:
618 {
619 const2reg(src, FrameMap::rscratch1_opr, lir_patch_none, NULL);
620 reg2stack(FrameMap::rscratch1_opr, dest, c->type(), false);
621 }
622 case T_INT:
623 case T_FLOAT:
624 {
625 Register reg = zr;
626 if (c->as_jint_bits() == 0)
653 void LIR_Assembler::const2mem(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info, bool wide) {
654 assert(src->is_constant(), "should not call otherwise");
655 LIR_Const* c = src->as_constant_ptr();
656 LIR_Address* to_addr = dest->as_address_ptr();
657
658 void (Assembler::* insn)(Register Rt, const Address &adr);
659
660 switch (type) {
661 case T_ADDRESS:
662 assert(c->as_jint() == 0, "should be");
663 insn = &Assembler::str;
664 break;
665 case T_LONG:
666 assert(c->as_jlong() == 0, "should be");
667 insn = &Assembler::str;
668 break;
669 case T_INT:
670 assert(c->as_jint() == 0, "should be");
671 insn = &Assembler::strw;
672 break;
673 case T_OBJECT:
674 case T_ARRAY:
675 assert(c->as_jobject() == 0, "should be");
676 if (UseCompressedOops && !wide) {
677 insn = &Assembler::strw;
678 } else {
679 insn = &Assembler::str;
680 }
681 break;
682 case T_CHAR:
683 case T_SHORT:
684 assert(c->as_jint() == 0, "should be");
685 insn = &Assembler::strh;
686 break;
687 case T_BOOLEAN:
688 case T_BYTE:
689 assert(c->as_jint() == 0, "should be");
690 insn = &Assembler::strb;
691 break;
692 default:
693 ShouldNotReachHere();
694 insn = &Assembler::str; // unreachable
695 }
696
697 if (info) add_debug_info_for_null_check_here(info);
698 (_masm->*insn)(zr, as_Address(to_addr, rscratch1));
699 }
700
701 void LIR_Assembler::reg2reg(LIR_Opr src, LIR_Opr dest) {
702 assert(src->is_register(), "should not call otherwise");
703 assert(dest->is_register(), "should not call otherwise");
704
705 // move between cpu-registers
706 if (dest->is_single_cpu()) {
707 if (src->type() == T_LONG) {
708 // Can do LONG -> OBJECT
709 move_regs(src->as_register_lo(), dest->as_register());
710 return;
711 }
712 assert(src->is_single_cpu(), "must match");
713 if (src->type() == T_OBJECT) {
714 __ verify_oop(src->as_register());
715 }
716 move_regs(src->as_register(), dest->as_register());
717
718 } else if (dest->is_double_cpu()) {
719 if (src->type() == T_OBJECT || src->type() == T_ARRAY) {
720 // Surprising to me but we can see move of a long to t_object
721 __ verify_oop(src->as_register());
722 move_regs(src->as_register(), dest->as_register_lo());
723 return;
724 }
725 assert(src->is_double_cpu(), "must match");
726 Register f_lo = src->as_register_lo();
727 Register f_hi = src->as_register_hi();
728 Register t_lo = dest->as_register_lo();
729 Register t_hi = dest->as_register_hi();
730 assert(f_hi == f_lo, "must be same");
731 assert(t_hi == t_lo, "must be same");
732 move_regs(f_lo, t_lo);
733
734 } else if (dest->is_single_fpu()) {
735 __ fmovs(dest->as_float_reg(), src->as_float_reg());
736
737 } else if (dest->is_double_fpu()) {
738 __ fmovd(dest->as_double_reg(), src->as_double_reg());
739
740 } else {
741 ShouldNotReachHere();
742 }
743 }
744
745 void LIR_Assembler::reg2stack(LIR_Opr src, LIR_Opr dest, BasicType type, bool pop_fpu_stack) {
746 if (src->is_single_cpu()) {
747 if (type == T_ARRAY || type == T_OBJECT) {
748 __ str(src->as_register(), frame_map()->address_for_slot(dest->single_stack_ix()));
749 __ verify_oop(src->as_register());
750 } else if (type == T_METADATA || type == T_DOUBLE) {
751 __ str(src->as_register(), frame_map()->address_for_slot(dest->single_stack_ix()));
752 } else {
753 __ strw(src->as_register(), frame_map()->address_for_slot(dest->single_stack_ix()));
754 }
755
756 } else if (src->is_double_cpu()) {
757 Address dest_addr_LO = frame_map()->address_for_slot(dest->double_stack_ix(), lo_word_offset_in_bytes);
758 __ str(src->as_register_lo(), dest_addr_LO);
759
760 } else if (src->is_single_fpu()) {
761 Address dest_addr = frame_map()->address_for_slot(dest->single_stack_ix());
762 __ strs(src->as_float_reg(), dest_addr);
763
764 } else if (src->is_double_fpu()) {
765 Address dest_addr = frame_map()->address_for_slot(dest->double_stack_ix());
766 __ strd(src->as_double_reg(), dest_addr);
767
768 } else {
769 ShouldNotReachHere();
770 }
771
772 }
773
774
775 void LIR_Assembler::reg2mem(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool pop_fpu_stack, bool wide, bool /* unaligned */) {
776 LIR_Address* to_addr = dest->as_address_ptr();
777 PatchingStub* patch = NULL;
778 Register compressed_src = rscratch1;
779
780 if (patch_code != lir_patch_none) {
781 deoptimize_trap(info);
782 return;
783 }
784
785 if (type == T_ARRAY || type == T_OBJECT) {
786 __ verify_oop(src->as_register());
787
788 if (UseCompressedOops && !wide) {
789 __ encode_heap_oop(compressed_src, src->as_register());
790 } else {
791 compressed_src = src->as_register();
792 }
793 }
794
795 int null_check_here = code_offset();
796 switch (type) {
797 case T_FLOAT: {
798 __ strs(src->as_float_reg(), as_Address(to_addr));
799 break;
800 }
801
802 case T_DOUBLE: {
803 __ strd(src->as_double_reg(), as_Address(to_addr));
804 break;
805 }
806
807 case T_ARRAY: // fall through
808 case T_OBJECT: // fall through
809 if (UseCompressedOops && !wide) {
810 __ strw(compressed_src, as_Address(to_addr, rscratch2));
811 } else {
812 __ str(compressed_src, as_Address(to_addr));
813 }
814 break;
815 case T_METADATA:
816 // We get here to store a method pointer to the stack to pass to
817 // a dtrace runtime call. This can't work on 64 bit with
818 // compressed klass ptrs: T_METADATA can be a compressed klass
819 // ptr or a 64 bit method pointer.
820 ShouldNotReachHere();
821 __ str(src->as_register(), as_Address(to_addr));
822 break;
823 case T_ADDRESS:
824 __ str(src->as_register(), as_Address(to_addr));
825 break;
826 case T_INT:
840
841 case T_CHAR: // fall through
842 case T_SHORT:
843 __ strh(src->as_register(), as_Address(to_addr));
844 break;
845
846 default:
847 ShouldNotReachHere();
848 }
849 if (info != NULL) {
850 add_debug_info_for_null_check(null_check_here, info);
851 }
852 }
853
854
855 void LIR_Assembler::stack2reg(LIR_Opr src, LIR_Opr dest, BasicType type) {
856 assert(src->is_stack(), "should not call otherwise");
857 assert(dest->is_register(), "should not call otherwise");
858
859 if (dest->is_single_cpu()) {
860 if (type == T_ARRAY || type == T_OBJECT) {
861 __ ldr(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix()));
862 __ verify_oop(dest->as_register());
863 } else if (type == T_METADATA) {
864 __ ldr(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix()));
865 } else {
866 __ ldrw(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix()));
867 }
868
869 } else if (dest->is_double_cpu()) {
870 Address src_addr_LO = frame_map()->address_for_slot(src->double_stack_ix(), lo_word_offset_in_bytes);
871 __ ldr(dest->as_register_lo(), src_addr_LO);
872
873 } else if (dest->is_single_fpu()) {
874 Address src_addr = frame_map()->address_for_slot(src->single_stack_ix());
875 __ ldrs(dest->as_float_reg(), src_addr);
876
877 } else if (dest->is_double_fpu()) {
878 Address src_addr = frame_map()->address_for_slot(src->double_stack_ix());
879 __ ldrd(dest->as_double_reg(), src_addr);
880
912 add_call_info_here(info);
913 }
914
915 void LIR_Assembler::stack2stack(LIR_Opr src, LIR_Opr dest, BasicType type) {
916
917 LIR_Opr temp;
918 if (type == T_LONG || type == T_DOUBLE)
919 temp = FrameMap::rscratch1_long_opr;
920 else
921 temp = FrameMap::rscratch1_opr;
922
923 stack2reg(src, temp, src->type());
924 reg2stack(temp, dest, dest->type(), false);
925 }
926
927
928 void LIR_Assembler::mem2reg(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool wide, bool /* unaligned */) {
929 LIR_Address* addr = src->as_address_ptr();
930 LIR_Address* from_addr = src->as_address_ptr();
931
932 if (addr->base()->type() == T_OBJECT) {
933 __ verify_oop(addr->base()->as_pointer_register());
934 }
935
936 if (patch_code != lir_patch_none) {
937 deoptimize_trap(info);
938 return;
939 }
940
941 if (info != NULL) {
942 add_debug_info_for_null_check_here(info);
943 }
944 int null_check_here = code_offset();
945 switch (type) {
946 case T_FLOAT: {
947 __ ldrs(dest->as_float_reg(), as_Address(from_addr));
948 break;
949 }
950
951 case T_DOUBLE: {
952 __ ldrd(dest->as_double_reg(), as_Address(from_addr));
953 break;
954 }
955
956 case T_ARRAY: // fall through
957 case T_OBJECT: // fall through
958 if (UseCompressedOops && !wide) {
959 __ ldrw(dest->as_register(), as_Address(from_addr));
960 } else {
961 __ ldr(dest->as_register(), as_Address(from_addr));
962 }
963 break;
964 case T_METADATA:
965 // We get here to store a method pointer to the stack to pass to
966 // a dtrace runtime call. This can't work on 64 bit with
967 // compressed klass ptrs: T_METADATA can be a compressed klass
968 // ptr or a 64 bit method pointer.
969 ShouldNotReachHere();
970 __ ldr(dest->as_register(), as_Address(from_addr));
971 break;
972 case T_ADDRESS:
973 // FIXME: OMG this is a horrible kludge. Any offset from an
974 // address that matches klass_offset_in_bytes() will be loaded
975 // as a word, not a long.
990
991 case T_BYTE:
992 __ ldrsb(dest->as_register(), as_Address(from_addr));
993 break;
994 case T_BOOLEAN: {
995 __ ldrb(dest->as_register(), as_Address(from_addr));
996 break;
997 }
998
999 case T_CHAR:
1000 __ ldrh(dest->as_register(), as_Address(from_addr));
1001 break;
1002 case T_SHORT:
1003 __ ldrsh(dest->as_register(), as_Address(from_addr));
1004 break;
1005
1006 default:
1007 ShouldNotReachHere();
1008 }
1009
1010 if (type == T_ARRAY || type == T_OBJECT) {
1011 if (UseCompressedOops && !wide) {
1012 __ decode_heap_oop(dest->as_register());
1013 }
1014 __ verify_oop(dest->as_register());
1015 } else if (type == T_ADDRESS && addr->disp() == oopDesc::klass_offset_in_bytes()) {
1016 if (UseCompressedClassPointers) {
1017 __ decode_klass_not_null(dest->as_register());
1018 }
1019 }
1020 }
1021
1022
1023 int LIR_Assembler::array_element_size(BasicType type) const {
1024 int elem_size = type2aelembytes(type);
1025 return exact_log2(elem_size);
1026 }
1027
1028
1029 void LIR_Assembler::emit_op3(LIR_Op3* op) {
1030 switch (op->code()) {
1193 __ ldrb(rscratch1, Address(op->klass()->as_register(),
1194 InstanceKlass::init_state_offset()));
1195 __ cmpw(rscratch1, InstanceKlass::fully_initialized);
1196 add_debug_info_for_null_check_here(op->stub()->info());
1197 __ br(Assembler::NE, *op->stub()->entry());
1198 }
1199 __ allocate_object(op->obj()->as_register(),
1200 op->tmp1()->as_register(),
1201 op->tmp2()->as_register(),
1202 op->header_size(),
1203 op->object_size(),
1204 op->klass()->as_register(),
1205 *op->stub()->entry());
1206 __ bind(*op->stub()->continuation());
1207 }
1208
1209 void LIR_Assembler::emit_alloc_array(LIR_OpAllocArray* op) {
1210 Register len = op->len()->as_register();
1211 __ uxtw(len, len);
1212
1213 if (UseSlowPath ||
1214 (!UseFastNewObjectArray && (op->type() == T_OBJECT || op->type() == T_ARRAY)) ||
1215 (!UseFastNewTypeArray && (op->type() != T_OBJECT && op->type() != T_ARRAY))) {
1216 __ b(*op->stub()->entry());
1217 } else {
1218 Register tmp1 = op->tmp1()->as_register();
1219 Register tmp2 = op->tmp2()->as_register();
1220 Register tmp3 = op->tmp3()->as_register();
1221 if (len == tmp1) {
1222 tmp1 = tmp3;
1223 } else if (len == tmp2) {
1224 tmp2 = tmp3;
1225 } else if (len == tmp3) {
1226 // everything is ok
1227 } else {
1228 __ mov(tmp3, len);
1229 }
1230 __ allocate_array(op->obj()->as_register(),
1231 len,
1232 tmp1,
1233 tmp2,
1911 }
1912 }
1913 } else {
1914 Register rreg = right->as_register();
1915 __ corrected_idivl(dreg, lreg, rreg, is_irem, rscratch1);
1916 }
1917 }
1918
1919
1920 void LIR_Assembler::comp_op(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Op2* op) {
1921 if (opr1->is_constant() && opr2->is_single_cpu()) {
1922 // tableswitch
1923 Register reg = as_reg(opr2);
1924 struct tableswitch &table = switches[opr1->as_constant_ptr()->as_jint()];
1925 __ tableswitch(reg, table._first_key, table._last_key, table._branches, table._after);
1926 } else if (opr1->is_single_cpu() || opr1->is_double_cpu()) {
1927 Register reg1 = as_reg(opr1);
1928 if (opr2->is_single_cpu()) {
1929 // cpu register - cpu register
1930 Register reg2 = opr2->as_register();
1931 if (opr1->type() == T_OBJECT || opr1->type() == T_ARRAY) {
1932 __ cmpoop(reg1, reg2);
1933 } else {
1934 assert(opr2->type() != T_OBJECT && opr2->type() != T_ARRAY, "cmp int, oop?");
1935 __ cmpw(reg1, reg2);
1936 }
1937 return;
1938 }
1939 if (opr2->is_double_cpu()) {
1940 // cpu register - cpu register
1941 Register reg2 = opr2->as_register_lo();
1942 __ cmp(reg1, reg2);
1943 return;
1944 }
1945
1946 if (opr2->is_constant()) {
1947 bool is_32bit = false; // width of register operand
1948 jlong imm;
1949
1950 switch(opr2->type()) {
1951 case T_INT:
1952 imm = opr2->as_constant_ptr()->as_jint();
1953 is_32bit = true;
1954 break;
1955 case T_LONG:
1956 imm = opr2->as_constant_ptr()->as_jlong();
1957 break;
1958 case T_ADDRESS:
1959 imm = opr2->as_constant_ptr()->as_jint();
1960 break;
1961 case T_OBJECT:
1962 case T_ARRAY:
1963 jobject2reg(opr2->as_constant_ptr()->as_jobject(), rscratch1);
1964 __ cmpoop(reg1, rscratch1);
1965 return;
1966 default:
1967 ShouldNotReachHere();
1968 imm = 0; // unreachable
1969 break;
1970 }
1971
1972 if (Assembler::operand_valid_for_add_sub_immediate(imm)) {
1973 if (is_32bit)
1974 __ cmpw(reg1, imm);
1975 else
1976 __ subs(zr, reg1, imm);
1977 return;
1978 } else {
1979 __ mov(rscratch1, imm);
1980 if (is_32bit)
2108 __ b(_unwind_handler_entry);
2109 }
2110
2111
2112 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, LIR_Opr count, LIR_Opr dest, LIR_Opr tmp) {
2113 Register lreg = left->is_single_cpu() ? left->as_register() : left->as_register_lo();
2114 Register dreg = dest->is_single_cpu() ? dest->as_register() : dest->as_register_lo();
2115
2116 switch (left->type()) {
2117 case T_INT: {
2118 switch (code) {
2119 case lir_shl: __ lslvw (dreg, lreg, count->as_register()); break;
2120 case lir_shr: __ asrvw (dreg, lreg, count->as_register()); break;
2121 case lir_ushr: __ lsrvw (dreg, lreg, count->as_register()); break;
2122 default:
2123 ShouldNotReachHere();
2124 break;
2125 }
2126 break;
2127 case T_LONG:
2128 case T_ADDRESS:
2129 case T_OBJECT:
2130 switch (code) {
2131 case lir_shl: __ lslv (dreg, lreg, count->as_register()); break;
2132 case lir_shr: __ asrv (dreg, lreg, count->as_register()); break;
2133 case lir_ushr: __ lsrv (dreg, lreg, count->as_register()); break;
2134 default:
2135 ShouldNotReachHere();
2136 break;
2137 }
2138 break;
2139 default:
2140 ShouldNotReachHere();
2141 break;
2142 }
2143 }
2144 }
2145
2146
2147 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, jint count, LIR_Opr dest) {
2148 Register dreg = dest->is_single_cpu() ? dest->as_register() : dest->as_register_lo();
2149 Register lreg = left->is_single_cpu() ? left->as_register() : left->as_register_lo();
2150
2151 switch (left->type()) {
2152 case T_INT: {
2153 switch (code) {
2154 case lir_shl: __ lslw (dreg, lreg, count); break;
2155 case lir_shr: __ asrw (dreg, lreg, count); break;
2156 case lir_ushr: __ lsrw (dreg, lreg, count); break;
2157 default:
2158 ShouldNotReachHere();
2159 break;
2160 }
2161 break;
2162 case T_LONG:
2163 case T_ADDRESS:
2164 case T_OBJECT:
2165 switch (code) {
2166 case lir_shl: __ lsl (dreg, lreg, count); break;
2167 case lir_shr: __ asr (dreg, lreg, count); break;
2168 case lir_ushr: __ lsr (dreg, lreg, count); break;
2169 default:
2170 ShouldNotReachHere();
2171 break;
2172 }
2173 break;
2174 default:
2175 ShouldNotReachHere();
2176 break;
2177 }
2178 }
2179 }
2180
2181
2182 void LIR_Assembler::store_parameter(Register r, int offset_from_rsp_in_words) {
2183 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
2872
2873
2874 void LIR_Assembler::rt_call(LIR_Opr result, address dest, const LIR_OprList* args, LIR_Opr tmp, CodeEmitInfo* info) {
2875 assert(!tmp->is_valid(), "don't need temporary");
2876
2877 CodeBlob *cb = CodeCache::find_blob(dest);
2878 if (cb) {
2879 __ far_call(RuntimeAddress(dest));
2880 } else {
2881 __ mov(rscratch1, RuntimeAddress(dest));
2882 int len = args->length();
2883 int type = 0;
2884 if (! result->is_illegal()) {
2885 switch (result->type()) {
2886 case T_VOID:
2887 type = 0;
2888 break;
2889 case T_INT:
2890 case T_LONG:
2891 case T_OBJECT:
2892 type = 1;
2893 break;
2894 case T_FLOAT:
2895 type = 2;
2896 break;
2897 case T_DOUBLE:
2898 type = 3;
2899 break;
2900 default:
2901 ShouldNotReachHere();
2902 break;
2903 }
2904 }
2905 int num_gpargs = 0;
2906 int num_fpargs = 0;
2907 for (int i = 0; i < args->length(); i++) {
2908 LIR_Opr arg = args->at(i);
2909 if (arg->type() == T_FLOAT || arg->type() == T_DOUBLE) {
2910 num_fpargs++;
2911 } else {
3138 #endif
3139 }
3140
3141 void LIR_Assembler::atomic_op(LIR_Code code, LIR_Opr src, LIR_Opr data, LIR_Opr dest, LIR_Opr tmp_op) {
3142 Address addr = as_Address(src->as_address_ptr());
3143 BasicType type = src->type();
3144 bool is_oop = type == T_OBJECT || type == T_ARRAY;
3145
3146 void (MacroAssembler::* add)(Register prev, RegisterOrConstant incr, Register addr);
3147 void (MacroAssembler::* xchg)(Register prev, Register newv, Register addr);
3148
3149 switch(type) {
3150 case T_INT:
3151 xchg = &MacroAssembler::atomic_xchgalw;
3152 add = &MacroAssembler::atomic_addalw;
3153 break;
3154 case T_LONG:
3155 xchg = &MacroAssembler::atomic_xchgal;
3156 add = &MacroAssembler::atomic_addal;
3157 break;
3158 case T_OBJECT:
3159 case T_ARRAY:
3160 if (UseCompressedOops) {
3161 xchg = &MacroAssembler::atomic_xchgalw;
3162 add = &MacroAssembler::atomic_addalw;
3163 } else {
3164 xchg = &MacroAssembler::atomic_xchgal;
3165 add = &MacroAssembler::atomic_addal;
3166 }
3167 break;
3168 default:
3169 ShouldNotReachHere();
3170 xchg = &MacroAssembler::atomic_xchgal;
3171 add = &MacroAssembler::atomic_addal; // unreachable
3172 }
3173
3174 switch (code) {
3175 case lir_xadd:
3176 {
3177 RegisterOrConstant inc;
|
541
542 switch (c->type()) {
543 case T_INT: {
544 assert(patch_code == lir_patch_none, "no patching handled here");
545 __ movw(dest->as_register(), c->as_jint());
546 break;
547 }
548
549 case T_ADDRESS: {
550 assert(patch_code == lir_patch_none, "no patching handled here");
551 __ mov(dest->as_register(), c->as_jint());
552 break;
553 }
554
555 case T_LONG: {
556 assert(patch_code == lir_patch_none, "no patching handled here");
557 __ mov(dest->as_register_lo(), (intptr_t)c->as_jlong());
558 break;
559 }
560
561 case T_VALUETYPE:
562 case T_OBJECT: {
563 if (patch_code == lir_patch_none) {
564 jobject2reg(c->as_jobject(), dest->as_register());
565 } else {
566 jobject2reg_with_patching(dest->as_register(), info);
567 }
568 break;
569 }
570
571 case T_METADATA: {
572 if (patch_code != lir_patch_none) {
573 klass2reg_with_patching(dest->as_register(), info);
574 } else {
575 __ mov_metadata(dest->as_register(), c->as_metadata());
576 }
577 break;
578 }
579
580 case T_FLOAT: {
581 if (__ operand_valid_for_float_immediate(c->as_jfloat())) {
588 }
589
590 case T_DOUBLE: {
591 if (__ operand_valid_for_float_immediate(c->as_jdouble())) {
592 __ fmovd(dest->as_double_reg(), (c->as_jdouble()));
593 } else {
594 __ adr(rscratch1, InternalAddress(double_constant(c->as_jdouble())));
595 __ ldrd(dest->as_double_reg(), Address(rscratch1));
596 }
597 break;
598 }
599
600 default:
601 ShouldNotReachHere();
602 }
603 }
604
605 void LIR_Assembler::const2stack(LIR_Opr src, LIR_Opr dest) {
606 LIR_Const* c = src->as_constant_ptr();
607 switch (c->type()) {
608 case T_VALUETYPE:
609 case T_OBJECT:
610 {
611 if (! c->as_jobject())
612 __ str(zr, frame_map()->address_for_slot(dest->single_stack_ix()));
613 else {
614 const2reg(src, FrameMap::rscratch1_opr, lir_patch_none, NULL);
615 reg2stack(FrameMap::rscratch1_opr, dest, c->type(), false);
616 }
617 }
618 break;
619 case T_ADDRESS:
620 {
621 const2reg(src, FrameMap::rscratch1_opr, lir_patch_none, NULL);
622 reg2stack(FrameMap::rscratch1_opr, dest, c->type(), false);
623 }
624 case T_INT:
625 case T_FLOAT:
626 {
627 Register reg = zr;
628 if (c->as_jint_bits() == 0)
655 void LIR_Assembler::const2mem(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info, bool wide) {
656 assert(src->is_constant(), "should not call otherwise");
657 LIR_Const* c = src->as_constant_ptr();
658 LIR_Address* to_addr = dest->as_address_ptr();
659
660 void (Assembler::* insn)(Register Rt, const Address &adr);
661
662 switch (type) {
663 case T_ADDRESS:
664 assert(c->as_jint() == 0, "should be");
665 insn = &Assembler::str;
666 break;
667 case T_LONG:
668 assert(c->as_jlong() == 0, "should be");
669 insn = &Assembler::str;
670 break;
671 case T_INT:
672 assert(c->as_jint() == 0, "should be");
673 insn = &Assembler::strw;
674 break;
675 case T_VALUETYPE:
676 case T_OBJECT:
677 case T_ARRAY:
678 assert(c->as_jobject() == 0, "should be");
679 if (UseCompressedOops && !wide) {
680 insn = &Assembler::strw;
681 } else {
682 insn = &Assembler::str;
683 }
684 break;
685 case T_CHAR:
686 case T_SHORT:
687 assert(c->as_jint() == 0, "should be");
688 insn = &Assembler::strh;
689 break;
690 case T_BOOLEAN:
691 case T_BYTE:
692 assert(c->as_jint() == 0, "should be");
693 insn = &Assembler::strb;
694 break;
695 default:
696 ShouldNotReachHere();
697 insn = &Assembler::str; // unreachable
698 }
699
700 if (info) add_debug_info_for_null_check_here(info);
701 (_masm->*insn)(zr, as_Address(to_addr, rscratch1));
702 }
703
704 void LIR_Assembler::reg2reg(LIR_Opr src, LIR_Opr dest) {
705 assert(src->is_register(), "should not call otherwise");
706 assert(dest->is_register(), "should not call otherwise");
707
708 // move between cpu-registers
709 if (dest->is_single_cpu()) {
710 if (src->type() == T_LONG) {
711 // Can do LONG -> OBJECT
712 move_regs(src->as_register_lo(), dest->as_register());
713 return;
714 }
715 assert(src->is_single_cpu(), "must match");
716 if (src->type() == T_OBJECT || src->type() == T_VALUETYPE) {
717 __ verify_oop(src->as_register());
718 }
719 move_regs(src->as_register(), dest->as_register());
720
721 } else if (dest->is_double_cpu()) {
722 if (src->type() == T_OBJECT || src->type() == T_ARRAY || src->type() == T_VALUETYPE) {
723 // Surprising to me but we can see move of a long to t_object
724 __ verify_oop(src->as_register());
725 move_regs(src->as_register(), dest->as_register_lo());
726 return;
727 }
728 assert(src->is_double_cpu(), "must match");
729 Register f_lo = src->as_register_lo();
730 Register f_hi = src->as_register_hi();
731 Register t_lo = dest->as_register_lo();
732 Register t_hi = dest->as_register_hi();
733 assert(f_hi == f_lo, "must be same");
734 assert(t_hi == t_lo, "must be same");
735 move_regs(f_lo, t_lo);
736
737 } else if (dest->is_single_fpu()) {
738 __ fmovs(dest->as_float_reg(), src->as_float_reg());
739
740 } else if (dest->is_double_fpu()) {
741 __ fmovd(dest->as_double_reg(), src->as_double_reg());
742
743 } else {
744 ShouldNotReachHere();
745 }
746 }
747
748 void LIR_Assembler::reg2stack(LIR_Opr src, LIR_Opr dest, BasicType type, bool pop_fpu_stack) {
749 if (src->is_single_cpu()) {
750 if (type == T_ARRAY || type == T_OBJECT || type == T_VALUETYPE) {
751 __ str(src->as_register(), frame_map()->address_for_slot(dest->single_stack_ix()));
752 __ verify_oop(src->as_register());
753 } else if (type == T_METADATA || type == T_DOUBLE) {
754 __ str(src->as_register(), frame_map()->address_for_slot(dest->single_stack_ix()));
755 } else {
756 __ strw(src->as_register(), frame_map()->address_for_slot(dest->single_stack_ix()));
757 }
758
759 } else if (src->is_double_cpu()) {
760 Address dest_addr_LO = frame_map()->address_for_slot(dest->double_stack_ix(), lo_word_offset_in_bytes);
761 __ str(src->as_register_lo(), dest_addr_LO);
762
763 } else if (src->is_single_fpu()) {
764 Address dest_addr = frame_map()->address_for_slot(dest->single_stack_ix());
765 __ strs(src->as_float_reg(), dest_addr);
766
767 } else if (src->is_double_fpu()) {
768 Address dest_addr = frame_map()->address_for_slot(dest->double_stack_ix());
769 __ strd(src->as_double_reg(), dest_addr);
770
771 } else {
772 ShouldNotReachHere();
773 }
774
775 }
776
777
778 void LIR_Assembler::reg2mem(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool pop_fpu_stack, bool wide, bool /* unaligned */) {
779 LIR_Address* to_addr = dest->as_address_ptr();
780 PatchingStub* patch = NULL;
781 Register compressed_src = rscratch1;
782
783 if (patch_code != lir_patch_none) {
784 deoptimize_trap(info);
785 return;
786 }
787
788 if (type == T_ARRAY || type == T_OBJECT || type == T_VALUETYPE) {
789 __ verify_oop(src->as_register());
790
791 if (UseCompressedOops && !wide) {
792 __ encode_heap_oop(compressed_src, src->as_register());
793 } else {
794 compressed_src = src->as_register();
795 }
796 }
797
798 int null_check_here = code_offset();
799 switch (type) {
800 case T_FLOAT: {
801 __ strs(src->as_float_reg(), as_Address(to_addr));
802 break;
803 }
804
805 case T_DOUBLE: {
806 __ strd(src->as_double_reg(), as_Address(to_addr));
807 break;
808 }
809
810 case T_VALUETYPE: // fall through
811 case T_ARRAY: // fall through
812 case T_OBJECT: // fall through
813 if (UseCompressedOops && !wide) {
814 __ strw(compressed_src, as_Address(to_addr, rscratch2));
815 } else {
816 __ str(compressed_src, as_Address(to_addr));
817 }
818 break;
819 case T_METADATA:
820 // We get here to store a method pointer to the stack to pass to
821 // a dtrace runtime call. This can't work on 64 bit with
822 // compressed klass ptrs: T_METADATA can be a compressed klass
823 // ptr or a 64 bit method pointer.
824 ShouldNotReachHere();
825 __ str(src->as_register(), as_Address(to_addr));
826 break;
827 case T_ADDRESS:
828 __ str(src->as_register(), as_Address(to_addr));
829 break;
830 case T_INT:
844
845 case T_CHAR: // fall through
846 case T_SHORT:
847 __ strh(src->as_register(), as_Address(to_addr));
848 break;
849
850 default:
851 ShouldNotReachHere();
852 }
853 if (info != NULL) {
854 add_debug_info_for_null_check(null_check_here, info);
855 }
856 }
857
858
859 void LIR_Assembler::stack2reg(LIR_Opr src, LIR_Opr dest, BasicType type) {
860 assert(src->is_stack(), "should not call otherwise");
861 assert(dest->is_register(), "should not call otherwise");
862
863 if (dest->is_single_cpu()) {
864 if (type == T_ARRAY || type == T_OBJECT || type == T_VALUETYPE) {
865 __ ldr(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix()));
866 __ verify_oop(dest->as_register());
867 } else if (type == T_METADATA) {
868 __ ldr(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix()));
869 } else {
870 __ ldrw(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix()));
871 }
872
873 } else if (dest->is_double_cpu()) {
874 Address src_addr_LO = frame_map()->address_for_slot(src->double_stack_ix(), lo_word_offset_in_bytes);
875 __ ldr(dest->as_register_lo(), src_addr_LO);
876
877 } else if (dest->is_single_fpu()) {
878 Address src_addr = frame_map()->address_for_slot(src->single_stack_ix());
879 __ ldrs(dest->as_float_reg(), src_addr);
880
881 } else if (dest->is_double_fpu()) {
882 Address src_addr = frame_map()->address_for_slot(src->double_stack_ix());
883 __ ldrd(dest->as_double_reg(), src_addr);
884
916 add_call_info_here(info);
917 }
918
919 void LIR_Assembler::stack2stack(LIR_Opr src, LIR_Opr dest, BasicType type) {
920
921 LIR_Opr temp;
922 if (type == T_LONG || type == T_DOUBLE)
923 temp = FrameMap::rscratch1_long_opr;
924 else
925 temp = FrameMap::rscratch1_opr;
926
927 stack2reg(src, temp, src->type());
928 reg2stack(temp, dest, dest->type(), false);
929 }
930
931
932 void LIR_Assembler::mem2reg(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool wide, bool /* unaligned */) {
933 LIR_Address* addr = src->as_address_ptr();
934 LIR_Address* from_addr = src->as_address_ptr();
935
936 if (addr->base()->type() == T_OBJECT || addr->base()->type() == T_VALUETYPE) {
937 __ verify_oop(addr->base()->as_pointer_register());
938 }
939
940 if (patch_code != lir_patch_none) {
941 deoptimize_trap(info);
942 return;
943 }
944
945 if (info != NULL) {
946 add_debug_info_for_null_check_here(info);
947 }
948 int null_check_here = code_offset();
949 switch (type) {
950 case T_FLOAT: {
951 __ ldrs(dest->as_float_reg(), as_Address(from_addr));
952 break;
953 }
954
955 case T_DOUBLE: {
956 __ ldrd(dest->as_double_reg(), as_Address(from_addr));
957 break;
958 }
959
960 case T_VALUETYPE: // fall through
961 case T_ARRAY: // fall through
962 case T_OBJECT: // fall through
963 if (UseCompressedOops && !wide) {
964 __ ldrw(dest->as_register(), as_Address(from_addr));
965 } else {
966 __ ldr(dest->as_register(), as_Address(from_addr));
967 }
968 break;
969 case T_METADATA:
970 // We get here to store a method pointer to the stack to pass to
971 // a dtrace runtime call. This can't work on 64 bit with
972 // compressed klass ptrs: T_METADATA can be a compressed klass
973 // ptr or a 64 bit method pointer.
974 ShouldNotReachHere();
975 __ ldr(dest->as_register(), as_Address(from_addr));
976 break;
977 case T_ADDRESS:
978 // FIXME: OMG this is a horrible kludge. Any offset from an
979 // address that matches klass_offset_in_bytes() will be loaded
980 // as a word, not a long.
995
996 case T_BYTE:
997 __ ldrsb(dest->as_register(), as_Address(from_addr));
998 break;
999 case T_BOOLEAN: {
1000 __ ldrb(dest->as_register(), as_Address(from_addr));
1001 break;
1002 }
1003
1004 case T_CHAR:
1005 __ ldrh(dest->as_register(), as_Address(from_addr));
1006 break;
1007 case T_SHORT:
1008 __ ldrsh(dest->as_register(), as_Address(from_addr));
1009 break;
1010
1011 default:
1012 ShouldNotReachHere();
1013 }
1014
1015 if (type == T_ARRAY || type == T_OBJECT || type == T_VALUETYPE) {
1016 if (UseCompressedOops && !wide) {
1017 __ decode_heap_oop(dest->as_register());
1018 }
1019 __ verify_oop(dest->as_register());
1020 } else if (type == T_ADDRESS && addr->disp() == oopDesc::klass_offset_in_bytes()) {
1021 if (UseCompressedClassPointers) {
1022 __ decode_klass_not_null(dest->as_register());
1023 }
1024 }
1025 }
1026
1027
1028 int LIR_Assembler::array_element_size(BasicType type) const {
1029 int elem_size = type2aelembytes(type);
1030 return exact_log2(elem_size);
1031 }
1032
1033
1034 void LIR_Assembler::emit_op3(LIR_Op3* op) {
1035 switch (op->code()) {
1198 __ ldrb(rscratch1, Address(op->klass()->as_register(),
1199 InstanceKlass::init_state_offset()));
1200 __ cmpw(rscratch1, InstanceKlass::fully_initialized);
1201 add_debug_info_for_null_check_here(op->stub()->info());
1202 __ br(Assembler::NE, *op->stub()->entry());
1203 }
1204 __ allocate_object(op->obj()->as_register(),
1205 op->tmp1()->as_register(),
1206 op->tmp2()->as_register(),
1207 op->header_size(),
1208 op->object_size(),
1209 op->klass()->as_register(),
1210 *op->stub()->entry());
1211 __ bind(*op->stub()->continuation());
1212 }
1213
1214 void LIR_Assembler::emit_alloc_array(LIR_OpAllocArray* op) {
1215 Register len = op->len()->as_register();
1216 __ uxtw(len, len);
1217
1218 if (UseSlowPath || op->type() == T_VALUETYPE ||
1219 (!UseFastNewObjectArray && (op->type() == T_OBJECT || op->type() == T_ARRAY)) ||
1220 (!UseFastNewTypeArray && (op->type() != T_OBJECT && op->type() != T_ARRAY))) {
1221 __ b(*op->stub()->entry());
1222 } else {
1223 Register tmp1 = op->tmp1()->as_register();
1224 Register tmp2 = op->tmp2()->as_register();
1225 Register tmp3 = op->tmp3()->as_register();
1226 if (len == tmp1) {
1227 tmp1 = tmp3;
1228 } else if (len == tmp2) {
1229 tmp2 = tmp3;
1230 } else if (len == tmp3) {
1231 // everything is ok
1232 } else {
1233 __ mov(tmp3, len);
1234 }
1235 __ allocate_array(op->obj()->as_register(),
1236 len,
1237 tmp1,
1238 tmp2,
1916 }
1917 }
1918 } else {
1919 Register rreg = right->as_register();
1920 __ corrected_idivl(dreg, lreg, rreg, is_irem, rscratch1);
1921 }
1922 }
1923
1924
1925 void LIR_Assembler::comp_op(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Op2* op) {
1926 if (opr1->is_constant() && opr2->is_single_cpu()) {
1927 // tableswitch
1928 Register reg = as_reg(opr2);
1929 struct tableswitch &table = switches[opr1->as_constant_ptr()->as_jint()];
1930 __ tableswitch(reg, table._first_key, table._last_key, table._branches, table._after);
1931 } else if (opr1->is_single_cpu() || opr1->is_double_cpu()) {
1932 Register reg1 = as_reg(opr1);
1933 if (opr2->is_single_cpu()) {
1934 // cpu register - cpu register
1935 Register reg2 = opr2->as_register();
1936 if (opr1->type() == T_OBJECT || opr1->type() == T_ARRAY || opr1->type() == T_VALUETYPE) {
1937 __ cmpoop(reg1, reg2);
1938 } else {
1939 assert(opr2->type() != T_OBJECT && opr2->type() != T_ARRAY && opr2->type() != T_VALUETYPE, "cmp int, oop?");
1940 __ cmpw(reg1, reg2);
1941 }
1942 return;
1943 }
1944 if (opr2->is_double_cpu()) {
1945 // cpu register - cpu register
1946 Register reg2 = opr2->as_register_lo();
1947 __ cmp(reg1, reg2);
1948 return;
1949 }
1950
1951 if (opr2->is_constant()) {
1952 bool is_32bit = false; // width of register operand
1953 jlong imm;
1954
1955 switch(opr2->type()) {
1956 case T_INT:
1957 imm = opr2->as_constant_ptr()->as_jint();
1958 is_32bit = true;
1959 break;
1960 case T_LONG:
1961 imm = opr2->as_constant_ptr()->as_jlong();
1962 break;
1963 case T_ADDRESS:
1964 imm = opr2->as_constant_ptr()->as_jint();
1965 break;
1966 case T_VALUETYPE:
1967 case T_OBJECT:
1968 case T_ARRAY:
1969 jobject2reg(opr2->as_constant_ptr()->as_jobject(), rscratch1);
1970 __ cmpoop(reg1, rscratch1);
1971 return;
1972 default:
1973 ShouldNotReachHere();
1974 imm = 0; // unreachable
1975 break;
1976 }
1977
1978 if (Assembler::operand_valid_for_add_sub_immediate(imm)) {
1979 if (is_32bit)
1980 __ cmpw(reg1, imm);
1981 else
1982 __ subs(zr, reg1, imm);
1983 return;
1984 } else {
1985 __ mov(rscratch1, imm);
1986 if (is_32bit)
2114 __ b(_unwind_handler_entry);
2115 }
2116
2117
2118 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, LIR_Opr count, LIR_Opr dest, LIR_Opr tmp) {
2119 Register lreg = left->is_single_cpu() ? left->as_register() : left->as_register_lo();
2120 Register dreg = dest->is_single_cpu() ? dest->as_register() : dest->as_register_lo();
2121
2122 switch (left->type()) {
2123 case T_INT: {
2124 switch (code) {
2125 case lir_shl: __ lslvw (dreg, lreg, count->as_register()); break;
2126 case lir_shr: __ asrvw (dreg, lreg, count->as_register()); break;
2127 case lir_ushr: __ lsrvw (dreg, lreg, count->as_register()); break;
2128 default:
2129 ShouldNotReachHere();
2130 break;
2131 }
2132 break;
2133 case T_LONG:
2134 case T_VALUETYPE:
2135 case T_ADDRESS:
2136 case T_OBJECT:
2137 switch (code) {
2138 case lir_shl: __ lslv (dreg, lreg, count->as_register()); break;
2139 case lir_shr: __ asrv (dreg, lreg, count->as_register()); break;
2140 case lir_ushr: __ lsrv (dreg, lreg, count->as_register()); break;
2141 default:
2142 ShouldNotReachHere();
2143 break;
2144 }
2145 break;
2146 default:
2147 ShouldNotReachHere();
2148 break;
2149 }
2150 }
2151 }
2152
2153
2154 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, jint count, LIR_Opr dest) {
2155 Register dreg = dest->is_single_cpu() ? dest->as_register() : dest->as_register_lo();
2156 Register lreg = left->is_single_cpu() ? left->as_register() : left->as_register_lo();
2157
2158 switch (left->type()) {
2159 case T_INT: {
2160 switch (code) {
2161 case lir_shl: __ lslw (dreg, lreg, count); break;
2162 case lir_shr: __ asrw (dreg, lreg, count); break;
2163 case lir_ushr: __ lsrw (dreg, lreg, count); break;
2164 default:
2165 ShouldNotReachHere();
2166 break;
2167 }
2168 break;
2169 case T_LONG:
2170 case T_ADDRESS:
2171 case T_VALUETYPE:
2172 case T_OBJECT:
2173 switch (code) {
2174 case lir_shl: __ lsl (dreg, lreg, count); break;
2175 case lir_shr: __ asr (dreg, lreg, count); break;
2176 case lir_ushr: __ lsr (dreg, lreg, count); break;
2177 default:
2178 ShouldNotReachHere();
2179 break;
2180 }
2181 break;
2182 default:
2183 ShouldNotReachHere();
2184 break;
2185 }
2186 }
2187 }
2188
2189
2190 void LIR_Assembler::store_parameter(Register r, int offset_from_rsp_in_words) {
2191 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
2880
2881
2882 void LIR_Assembler::rt_call(LIR_Opr result, address dest, const LIR_OprList* args, LIR_Opr tmp, CodeEmitInfo* info) {
2883 assert(!tmp->is_valid(), "don't need temporary");
2884
2885 CodeBlob *cb = CodeCache::find_blob(dest);
2886 if (cb) {
2887 __ far_call(RuntimeAddress(dest));
2888 } else {
2889 __ mov(rscratch1, RuntimeAddress(dest));
2890 int len = args->length();
2891 int type = 0;
2892 if (! result->is_illegal()) {
2893 switch (result->type()) {
2894 case T_VOID:
2895 type = 0;
2896 break;
2897 case T_INT:
2898 case T_LONG:
2899 case T_OBJECT:
2900 case T_VALUETYPE:
2901 type = 1;
2902 break;
2903 case T_FLOAT:
2904 type = 2;
2905 break;
2906 case T_DOUBLE:
2907 type = 3;
2908 break;
2909 default:
2910 ShouldNotReachHere();
2911 break;
2912 }
2913 }
2914 int num_gpargs = 0;
2915 int num_fpargs = 0;
2916 for (int i = 0; i < args->length(); i++) {
2917 LIR_Opr arg = args->at(i);
2918 if (arg->type() == T_FLOAT || arg->type() == T_DOUBLE) {
2919 num_fpargs++;
2920 } else {
3147 #endif
3148 }
3149
3150 void LIR_Assembler::atomic_op(LIR_Code code, LIR_Opr src, LIR_Opr data, LIR_Opr dest, LIR_Opr tmp_op) {
3151 Address addr = as_Address(src->as_address_ptr());
3152 BasicType type = src->type();
3153 bool is_oop = type == T_OBJECT || type == T_ARRAY;
3154
3155 void (MacroAssembler::* add)(Register prev, RegisterOrConstant incr, Register addr);
3156 void (MacroAssembler::* xchg)(Register prev, Register newv, Register addr);
3157
3158 switch(type) {
3159 case T_INT:
3160 xchg = &MacroAssembler::atomic_xchgalw;
3161 add = &MacroAssembler::atomic_addalw;
3162 break;
3163 case T_LONG:
3164 xchg = &MacroAssembler::atomic_xchgal;
3165 add = &MacroAssembler::atomic_addal;
3166 break;
3167 case T_VALUETYPE:
3168 case T_OBJECT:
3169 case T_ARRAY:
3170 if (UseCompressedOops) {
3171 xchg = &MacroAssembler::atomic_xchgalw;
3172 add = &MacroAssembler::atomic_addalw;
3173 } else {
3174 xchg = &MacroAssembler::atomic_xchgal;
3175 add = &MacroAssembler::atomic_addal;
3176 }
3177 break;
3178 default:
3179 ShouldNotReachHere();
3180 xchg = &MacroAssembler::atomic_xchgal;
3181 add = &MacroAssembler::atomic_addal; // unreachable
3182 }
3183
3184 switch (code) {
3185 case lir_xadd:
3186 {
3187 RegisterOrConstant inc;
|