1 /*
2 * Copyright (c) 2000, 2018, Oracle and/or its affiliates. All rights reserved.
3 * Copyright (c) 2014, Red Hat Inc. All rights reserved.
4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
5 *
6 * This code is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 only, as
8 * published by the Free Software Foundation.
9 *
10 * This code is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * version 2 for more details (a copy is included in the LICENSE file that
14 * accompanied this code).
15 *
16 * You should have received a copy of the GNU General Public License version
17 * 2 along with this work; if not, write to the Free Software Foundation,
18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 * or visit www.oracle.com if you need additional information or have any
22 * questions.
23 *
24 */
25
26 #include "precompiled.hpp"
27 #include "asm/macroAssembler.inline.hpp"
28 #include "asm/assembler.hpp"
29 #include "c1/c1_CodeStubs.hpp"
30 #include "c1/c1_Compilation.hpp"
31 #include "c1/c1_LIRAssembler.hpp"
32 #include "c1/c1_MacroAssembler.hpp"
33 #include "c1/c1_Runtime1.hpp"
34 #include "c1/c1_ValueStack.hpp"
35 #include "ci/ciArrayKlass.hpp"
36 #include "ci/ciInstance.hpp"
37 #include "gc/shared/barrierSet.hpp"
38 #include "gc/shared/cardTableBarrierSet.hpp"
39 #include "gc/shared/collectedHeap.hpp"
40 #include "nativeInst_aarch64.hpp"
41 #include "oops/objArrayKlass.hpp"
42 #include "runtime/frame.inline.hpp"
43 #include "runtime/sharedRuntime.hpp"
44 #include "vmreg_aarch64.inline.hpp"
45
46
47
48 #ifndef PRODUCT
49 #define COMMENT(x) do { __ block_comment(x); } while (0)
50 #else
51 #define COMMENT(x)
52 #endif
53
54 NEEDS_CLEANUP // remove this definitions ?
55 const Register IC_Klass = rscratch2; // where the IC klass is cached
56 const Register SYNC_header = r0; // synchronization header
57 const Register SHIFT_count = r0; // where count for shift operations must be
58
59 #define __ _masm->
60
61
62 static void select_different_registers(Register preserve,
63 Register extra,
64 Register &tmp1,
65 Register &tmp2) {
66 if (tmp1 == preserve) {
67 assert_different_registers(tmp1, tmp2, extra);
68 tmp1 = extra;
69 } else if (tmp2 == preserve) {
70 assert_different_registers(tmp1, tmp2, extra);
71 tmp2 = extra;
72 }
73 assert_different_registers(preserve, tmp1, tmp2);
74 }
75
76
77
78 static void select_different_registers(Register preserve,
79 Register extra,
80 Register &tmp1,
81 Register &tmp2,
82 Register &tmp3) {
83 if (tmp1 == preserve) {
84 assert_different_registers(tmp1, tmp2, tmp3, extra);
85 tmp1 = extra;
86 } else if (tmp2 == preserve) {
87 assert_different_registers(tmp1, tmp2, tmp3, extra);
88 tmp2 = extra;
89 } else if (tmp3 == preserve) {
90 assert_different_registers(tmp1, tmp2, tmp3, extra);
91 tmp3 = extra;
92 }
93 assert_different_registers(preserve, tmp1, tmp2, tmp3);
94 }
95
96
97 bool LIR_Assembler::is_small_constant(LIR_Opr opr) { Unimplemented(); return false; }
98
99
100 LIR_Opr LIR_Assembler::receiverOpr() {
101 return FrameMap::receiver_opr;
102 }
103
104 LIR_Opr LIR_Assembler::osrBufferPointer() {
105 return FrameMap::as_pointer_opr(receiverOpr()->as_register());
106 }
107
108 //--------------fpu register translations-----------------------
109
110
111 address LIR_Assembler::float_constant(float f) {
112 address const_addr = __ float_constant(f);
113 if (const_addr == NULL) {
114 bailout("const section overflow");
115 return __ code()->consts()->start();
116 } else {
117 return const_addr;
118 }
119 }
120
121
122 address LIR_Assembler::double_constant(double d) {
123 address const_addr = __ double_constant(d);
124 if (const_addr == NULL) {
125 bailout("const section overflow");
126 return __ code()->consts()->start();
127 } else {
128 return const_addr;
129 }
130 }
131
132 address LIR_Assembler::int_constant(jlong n) {
133 address const_addr = __ long_constant(n);
134 if (const_addr == NULL) {
135 bailout("const section overflow");
136 return __ code()->consts()->start();
137 } else {
138 return const_addr;
139 }
140 }
141
142 void LIR_Assembler::set_24bit_FPU() { Unimplemented(); }
143
144 void LIR_Assembler::reset_FPU() { Unimplemented(); }
145
146 void LIR_Assembler::fpop() { Unimplemented(); }
147
148 void LIR_Assembler::fxch(int i) { Unimplemented(); }
149
150 void LIR_Assembler::fld(int i) { Unimplemented(); }
151
152 void LIR_Assembler::ffree(int i) { Unimplemented(); }
153
154 void LIR_Assembler::breakpoint() { Unimplemented(); }
155
156 void LIR_Assembler::push(LIR_Opr opr) { Unimplemented(); }
157
158 void LIR_Assembler::pop(LIR_Opr opr) { Unimplemented(); }
159
160 bool LIR_Assembler::is_literal_address(LIR_Address* addr) { Unimplemented(); return false; }
161 //-------------------------------------------
162
163 static Register as_reg(LIR_Opr op) {
164 return op->is_double_cpu() ? op->as_register_lo() : op->as_register();
165 }
166
167 static jlong as_long(LIR_Opr data) {
168 jlong result;
169 switch (data->type()) {
170 case T_INT:
171 result = (data->as_jint());
172 break;
173 case T_LONG:
174 result = (data->as_jlong());
175 break;
176 default:
177 ShouldNotReachHere();
178 result = 0; // unreachable
179 }
180 return result;
181 }
182
183 Address LIR_Assembler::as_Address(LIR_Address* addr, Register tmp) {
184 Register base = addr->base()->as_pointer_register();
185 LIR_Opr opr = addr->index();
186 if (opr->is_cpu_register()) {
187 Register index;
188 if (opr->is_single_cpu())
189 index = opr->as_register();
190 else
191 index = opr->as_register_lo();
192 assert(addr->disp() == 0, "must be");
193 switch(opr->type()) {
194 case T_INT:
195 return Address(base, index, Address::sxtw(addr->scale()));
196 case T_LONG:
197 return Address(base, index, Address::lsl(addr->scale()));
198 default:
199 ShouldNotReachHere();
200 }
201 } else {
202 intptr_t addr_offset = intptr_t(addr->disp());
203 if (Address::offset_ok_for_immed(addr_offset, addr->scale()))
204 return Address(base, addr_offset, Address::lsl(addr->scale()));
205 else {
206 __ mov(tmp, addr_offset);
207 return Address(base, tmp, Address::lsl(addr->scale()));
208 }
209 }
210 return Address();
211 }
212
213 Address LIR_Assembler::as_Address_hi(LIR_Address* addr) {
214 ShouldNotReachHere();
215 return Address();
216 }
217
218 Address LIR_Assembler::as_Address(LIR_Address* addr) {
219 return as_Address(addr, rscratch1);
220 }
221
222 Address LIR_Assembler::as_Address_lo(LIR_Address* addr) {
223 return as_Address(addr, rscratch1); // Ouch
224 // FIXME: This needs to be much more clever. See x86.
225 }
226
227
228 void LIR_Assembler::osr_entry() {
229 offsets()->set_value(CodeOffsets::OSR_Entry, code_offset());
230 BlockBegin* osr_entry = compilation()->hir()->osr_entry();
231 ValueStack* entry_state = osr_entry->state();
232 int number_of_locks = entry_state->locks_size();
233
234 // we jump here if osr happens with the interpreter
235 // state set up to continue at the beginning of the
236 // loop that triggered osr - in particular, we have
237 // the following registers setup:
238 //
239 // r2: osr buffer
240 //
241
242 // build frame
243 ciMethod* m = compilation()->method();
244 __ build_frame(initial_frame_size_in_bytes(), bang_size_in_bytes());
245
246 // OSR buffer is
247 //
248 // locals[nlocals-1..0]
249 // monitors[0..number_of_locks]
250 //
251 // locals is a direct copy of the interpreter frame so in the osr buffer
252 // so first slot in the local array is the last local from the interpreter
253 // and last slot is local[0] (receiver) from the interpreter
254 //
255 // Similarly with locks. The first lock slot in the osr buffer is the nth lock
256 // from the interpreter frame, the nth lock slot in the osr buffer is 0th lock
257 // in the interpreter frame (the method lock if a sync method)
258
259 // Initialize monitors in the compiled activation.
260 // r2: pointer to osr buffer
261 //
262 // All other registers are dead at this point and the locals will be
263 // copied into place by code emitted in the IR.
264
265 Register OSR_buf = osrBufferPointer()->as_pointer_register();
266 { assert(frame::interpreter_frame_monitor_size() == BasicObjectLock::size(), "adjust code below");
267 int monitor_offset = BytesPerWord * method()->max_locals() +
268 (2 * BytesPerWord) * (number_of_locks - 1);
269 // SharedRuntime::OSR_migration_begin() packs BasicObjectLocks in
270 // the OSR buffer using 2 word entries: first the lock and then
271 // the oop.
272 for (int i = 0; i < number_of_locks; i++) {
273 int slot_offset = monitor_offset - ((i * 2) * BytesPerWord);
274 #ifdef ASSERT
275 // verify the interpreter's monitor has a non-null object
276 {
277 Label L;
278 __ ldr(rscratch1, Address(OSR_buf, slot_offset + 1*BytesPerWord));
279 __ cbnz(rscratch1, L);
280 __ stop("locked object is NULL");
281 __ bind(L);
282 }
283 #endif
284 __ ldr(r19, Address(OSR_buf, slot_offset + 0));
285 __ str(r19, frame_map()->address_for_monitor_lock(i));
286 __ ldr(r19, Address(OSR_buf, slot_offset + 1*BytesPerWord));
287 __ str(r19, frame_map()->address_for_monitor_object(i));
288 }
289 }
290 }
291
292
293 // inline cache check; done before the frame is built.
294 int LIR_Assembler::check_icache() {
295 Register receiver = FrameMap::receiver_opr->as_register();
296 Register ic_klass = IC_Klass;
297 int start_offset = __ offset();
298 __ inline_cache_check(receiver, ic_klass);
299
300 // if icache check fails, then jump to runtime routine
301 // Note: RECEIVER must still contain the receiver!
302 Label dont;
303 __ br(Assembler::EQ, dont);
304 __ far_jump(RuntimeAddress(SharedRuntime::get_ic_miss_stub()));
305
306 // We align the verified entry point unless the method body
307 // (including its inline cache check) will fit in a single 64-byte
308 // icache line.
309 if (! method()->is_accessor() || __ offset() - start_offset > 4 * 4) {
310 // force alignment after the cache check.
311 __ align(CodeEntryAlignment);
312 }
313
314 __ bind(dont);
315 return start_offset;
316 }
317
318
319 void LIR_Assembler::jobject2reg(jobject o, Register reg) {
320 if (o == NULL) {
321 __ mov(reg, zr);
322 } else {
323 __ movoop(reg, o, /*immediate*/true);
324 }
325 }
326
327 void LIR_Assembler::deoptimize_trap(CodeEmitInfo *info) {
328 address target = NULL;
329 relocInfo::relocType reloc_type = relocInfo::none;
330
331 switch (patching_id(info)) {
332 case PatchingStub::access_field_id:
333 target = Runtime1::entry_for(Runtime1::access_field_patching_id);
334 reloc_type = relocInfo::section_word_type;
335 break;
336 case PatchingStub::load_klass_id:
337 target = Runtime1::entry_for(Runtime1::load_klass_patching_id);
338 reloc_type = relocInfo::metadata_type;
339 break;
340 case PatchingStub::load_mirror_id:
341 target = Runtime1::entry_for(Runtime1::load_mirror_patching_id);
342 reloc_type = relocInfo::oop_type;
343 break;
344 case PatchingStub::load_appendix_id:
345 target = Runtime1::entry_for(Runtime1::load_appendix_patching_id);
346 reloc_type = relocInfo::oop_type;
347 break;
348 default: ShouldNotReachHere();
349 }
350
351 __ far_call(RuntimeAddress(target));
352 add_call_info_here(info);
353 }
354
355 void LIR_Assembler::jobject2reg_with_patching(Register reg, CodeEmitInfo *info) {
356 deoptimize_trap(info);
357 }
358
359
360 // This specifies the rsp decrement needed to build the frame
361 int LIR_Assembler::initial_frame_size_in_bytes() const {
362 // if rounding, must let FrameMap know!
363
364 // The frame_map records size in slots (32bit word)
365
366 // subtract two words to account for return address and link
367 return (frame_map()->framesize() - (2*VMRegImpl::slots_per_word)) * VMRegImpl::stack_slot_size;
368 }
369
370
371 int LIR_Assembler::emit_exception_handler() {
372 // if the last instruction is a call (typically to do a throw which
373 // is coming at the end after block reordering) the return address
374 // must still point into the code area in order to avoid assertion
375 // failures when searching for the corresponding bci => add a nop
376 // (was bug 5/14/1999 - gri)
377 __ nop();
378
379 // generate code for exception handler
380 address handler_base = __ start_a_stub(exception_handler_size());
381 if (handler_base == NULL) {
382 // not enough space left for the handler
383 bailout("exception handler overflow");
384 return -1;
385 }
386
387 int offset = code_offset();
388
389 // the exception oop and pc are in r0, and r3
390 // no other registers need to be preserved, so invalidate them
391 __ invalidate_registers(false, true, true, false, true, true);
392
393 // check that there is really an exception
394 __ verify_not_null_oop(r0);
395
396 // search an exception handler (r0: exception oop, r3: throwing pc)
397 __ far_call(RuntimeAddress(Runtime1::entry_for(Runtime1::handle_exception_from_callee_id))); __ should_not_reach_here();
398 guarantee(code_offset() - offset <= exception_handler_size(), "overflow");
399 __ end_a_stub();
400
401 return offset;
402 }
403
404
405 // Emit the code to remove the frame from the stack in the exception
406 // unwind path.
407 int LIR_Assembler::emit_unwind_handler() {
408 #ifndef PRODUCT
409 if (CommentedAssembly) {
410 _masm->block_comment("Unwind handler");
411 }
412 #endif
413
414 int offset = code_offset();
415
416 // Fetch the exception from TLS and clear out exception related thread state
417 __ ldr(r0, Address(rthread, JavaThread::exception_oop_offset()));
418 __ str(zr, Address(rthread, JavaThread::exception_oop_offset()));
419 __ str(zr, Address(rthread, JavaThread::exception_pc_offset()));
420
421 __ bind(_unwind_handler_entry);
422 __ verify_not_null_oop(r0);
423 if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) {
424 __ mov(r19, r0); // Preserve the exception
425 }
426
427 // Preform needed unlocking
428 MonitorExitStub* stub = NULL;
429 if (method()->is_synchronized()) {
430 monitor_address(0, FrameMap::r0_opr);
431 stub = new MonitorExitStub(FrameMap::r0_opr, true, 0);
432 __ unlock_object(r5, r4, r0, *stub->entry());
433 __ bind(*stub->continuation());
434 }
435
436 if (compilation()->env()->dtrace_method_probes()) {
437 __ call_Unimplemented();
438 #if 0
439 __ movptr(Address(rsp, 0), rax);
440 __ mov_metadata(Address(rsp, sizeof(void*)), method()->constant_encoding());
441 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, SharedRuntime::dtrace_method_exit)));
442 #endif
443 }
444
445 if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) {
446 __ mov(r0, r19); // Restore the exception
447 }
448
449 // remove the activation and dispatch to the unwind handler
450 __ block_comment("remove_frame and dispatch to the unwind handler");
451 __ remove_frame(initial_frame_size_in_bytes());
452 __ far_jump(RuntimeAddress(Runtime1::entry_for(Runtime1::unwind_exception_id)));
453
454 // Emit the slow path assembly
455 if (stub != NULL) {
456 stub->emit_code(this);
457 }
458
459 return offset;
460 }
461
462
463 int LIR_Assembler::emit_deopt_handler() {
464 // if the last instruction is a call (typically to do a throw which
465 // is coming at the end after block reordering) the return address
466 // must still point into the code area in order to avoid assertion
467 // failures when searching for the corresponding bci => add a nop
468 // (was bug 5/14/1999 - gri)
469 __ nop();
470
471 // generate code for exception handler
472 address handler_base = __ start_a_stub(deopt_handler_size());
473 if (handler_base == NULL) {
474 // not enough space left for the handler
475 bailout("deopt handler overflow");
476 return -1;
477 }
478
479 int offset = code_offset();
480
481 __ adr(lr, pc());
482 __ far_jump(RuntimeAddress(SharedRuntime::deopt_blob()->unpack()));
483 guarantee(code_offset() - offset <= deopt_handler_size(), "overflow");
484 __ end_a_stub();
485
486 return offset;
487 }
488
489 void LIR_Assembler::add_debug_info_for_branch(address adr, CodeEmitInfo* info) {
490 _masm->code_section()->relocate(adr, relocInfo::poll_type);
491 int pc_offset = code_offset();
492 flush_debug_info(pc_offset);
493 info->record_debug_info(compilation()->debug_info_recorder(), pc_offset);
494 if (info->exception_handlers() != NULL) {
495 compilation()->add_exception_handlers_for_pco(pc_offset, info->exception_handlers());
496 }
497 }
498
499 void LIR_Assembler::return_op(LIR_Opr result) {
500 assert(result->is_illegal() || !result->is_single_cpu() || result->as_register() == r0, "word returns are in r0,");
501
502 // Pop the stack before the safepoint code
503 __ remove_frame(initial_frame_size_in_bytes());
504
505 if (StackReservedPages > 0 && compilation()->has_reserved_stack_access()) {
506 __ reserved_stack_check();
507 }
508
509 address polling_page(os::get_polling_page());
510 __ read_polling_page(rscratch1, polling_page, relocInfo::poll_return_type);
511 __ ret(lr);
512 }
513
514 int LIR_Assembler::safepoint_poll(LIR_Opr tmp, CodeEmitInfo* info) {
515 address polling_page(os::get_polling_page());
516 guarantee(info != NULL, "Shouldn't be NULL");
517 assert(os::is_poll_address(polling_page), "should be");
518 __ get_polling_page(rscratch1, polling_page, relocInfo::poll_type);
519 add_debug_info_for_branch(info); // This isn't just debug info:
520 // it's the oop map
521 __ read_polling_page(rscratch1, relocInfo::poll_type);
522 return __ offset();
523 }
524
525
526 void LIR_Assembler::move_regs(Register from_reg, Register to_reg) {
527 if (from_reg == r31_sp)
528 from_reg = sp;
529 if (to_reg == r31_sp)
530 to_reg = sp;
531 __ mov(to_reg, from_reg);
532 }
533
534 void LIR_Assembler::swap_reg(Register a, Register b) { Unimplemented(); }
535
536
537 void LIR_Assembler::const2reg(LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
538 assert(src->is_constant(), "should not call otherwise");
539 assert(dest->is_register(), "should not call otherwise");
540 LIR_Const* c = src->as_constant_ptr();
541
542 switch (c->type()) {
543 case T_INT: {
544 assert(patch_code == lir_patch_none, "no patching handled here");
545 __ movw(dest->as_register(), c->as_jint());
546 break;
547 }
548
549 case T_ADDRESS: {
550 assert(patch_code == lir_patch_none, "no patching handled here");
551 __ mov(dest->as_register(), c->as_jint());
552 break;
553 }
554
555 case T_LONG: {
556 assert(patch_code == lir_patch_none, "no patching handled here");
557 __ mov(dest->as_register_lo(), (intptr_t)c->as_jlong());
558 break;
559 }
560
561 case T_VALUETYPE:
562 case T_OBJECT: {
563 if (patch_code == lir_patch_none) {
564 jobject2reg(c->as_jobject(), dest->as_register());
565 } else {
566 jobject2reg_with_patching(dest->as_register(), info);
567 }
568 break;
569 }
570
571 case T_METADATA: {
572 if (patch_code != lir_patch_none) {
573 klass2reg_with_patching(dest->as_register(), info);
574 } else {
575 __ mov_metadata(dest->as_register(), c->as_metadata());
576 }
577 break;
578 }
579
580 case T_FLOAT: {
581 if (__ operand_valid_for_float_immediate(c->as_jfloat())) {
582 __ fmovs(dest->as_float_reg(), (c->as_jfloat()));
583 } else {
584 __ adr(rscratch1, InternalAddress(float_constant(c->as_jfloat())));
585 __ ldrs(dest->as_float_reg(), Address(rscratch1));
586 }
587 break;
588 }
589
590 case T_DOUBLE: {
591 if (__ operand_valid_for_float_immediate(c->as_jdouble())) {
592 __ fmovd(dest->as_double_reg(), (c->as_jdouble()));
593 } else {
594 __ adr(rscratch1, InternalAddress(double_constant(c->as_jdouble())));
595 __ ldrd(dest->as_double_reg(), Address(rscratch1));
596 }
597 break;
598 }
599
600 default:
601 ShouldNotReachHere();
602 }
603 }
604
605 void LIR_Assembler::const2stack(LIR_Opr src, LIR_Opr dest) {
606 LIR_Const* c = src->as_constant_ptr();
607 switch (c->type()) {
608 case T_VALUETYPE:
609 case T_OBJECT:
610 {
611 if (! c->as_jobject())
612 __ str(zr, frame_map()->address_for_slot(dest->single_stack_ix()));
613 else {
614 const2reg(src, FrameMap::rscratch1_opr, lir_patch_none, NULL);
615 reg2stack(FrameMap::rscratch1_opr, dest, c->type(), false);
616 }
617 }
618 break;
619 case T_ADDRESS:
620 {
621 const2reg(src, FrameMap::rscratch1_opr, lir_patch_none, NULL);
622 reg2stack(FrameMap::rscratch1_opr, dest, c->type(), false);
623 }
624 case T_INT:
625 case T_FLOAT:
626 {
627 Register reg = zr;
628 if (c->as_jint_bits() == 0)
629 __ strw(zr, frame_map()->address_for_slot(dest->single_stack_ix()));
630 else {
631 __ movw(rscratch1, c->as_jint_bits());
632 __ strw(rscratch1, frame_map()->address_for_slot(dest->single_stack_ix()));
633 }
634 }
635 break;
636 case T_LONG:
637 case T_DOUBLE:
638 {
639 Register reg = zr;
640 if (c->as_jlong_bits() == 0)
641 __ str(zr, frame_map()->address_for_slot(dest->double_stack_ix(),
642 lo_word_offset_in_bytes));
643 else {
644 __ mov(rscratch1, (intptr_t)c->as_jlong_bits());
645 __ str(rscratch1, frame_map()->address_for_slot(dest->double_stack_ix(),
646 lo_word_offset_in_bytes));
647 }
648 }
649 break;
650 default:
651 ShouldNotReachHere();
652 }
653 }
654
655 void LIR_Assembler::const2mem(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info, bool wide) {
656 assert(src->is_constant(), "should not call otherwise");
657 LIR_Const* c = src->as_constant_ptr();
658 LIR_Address* to_addr = dest->as_address_ptr();
659
660 void (Assembler::* insn)(Register Rt, const Address &adr);
661
662 switch (type) {
663 case T_ADDRESS:
664 assert(c->as_jint() == 0, "should be");
665 insn = &Assembler::str;
666 break;
667 case T_LONG:
668 assert(c->as_jlong() == 0, "should be");
669 insn = &Assembler::str;
670 break;
671 case T_INT:
672 assert(c->as_jint() == 0, "should be");
673 insn = &Assembler::strw;
674 break;
675 case T_VALUETYPE:
676 case T_OBJECT:
677 case T_ARRAY:
678 assert(c->as_jobject() == 0, "should be");
679 if (UseCompressedOops && !wide) {
680 insn = &Assembler::strw;
681 } else {
682 insn = &Assembler::str;
683 }
684 break;
685 case T_CHAR:
686 case T_SHORT:
687 assert(c->as_jint() == 0, "should be");
688 insn = &Assembler::strh;
689 break;
690 case T_BOOLEAN:
691 case T_BYTE:
692 assert(c->as_jint() == 0, "should be");
693 insn = &Assembler::strb;
694 break;
695 default:
696 ShouldNotReachHere();
697 insn = &Assembler::str; // unreachable
698 }
699
700 if (info) add_debug_info_for_null_check_here(info);
701 (_masm->*insn)(zr, as_Address(to_addr, rscratch1));
702 }
703
704 void LIR_Assembler::reg2reg(LIR_Opr src, LIR_Opr dest) {
705 assert(src->is_register(), "should not call otherwise");
706 assert(dest->is_register(), "should not call otherwise");
707
708 // move between cpu-registers
709 if (dest->is_single_cpu()) {
710 if (src->type() == T_LONG) {
711 // Can do LONG -> OBJECT
712 move_regs(src->as_register_lo(), dest->as_register());
713 return;
714 }
715 assert(src->is_single_cpu(), "must match");
716 if (src->type() == T_OBJECT || src->type() == T_VALUETYPE) {
717 __ verify_oop(src->as_register());
718 }
719 move_regs(src->as_register(), dest->as_register());
720
721 } else if (dest->is_double_cpu()) {
722 if (src->type() == T_OBJECT || src->type() == T_ARRAY || src->type() == T_VALUETYPE) {
723 // Surprising to me but we can see move of a long to t_object
724 __ verify_oop(src->as_register());
725 move_regs(src->as_register(), dest->as_register_lo());
726 return;
727 }
728 assert(src->is_double_cpu(), "must match");
729 Register f_lo = src->as_register_lo();
730 Register f_hi = src->as_register_hi();
731 Register t_lo = dest->as_register_lo();
732 Register t_hi = dest->as_register_hi();
733 assert(f_hi == f_lo, "must be same");
734 assert(t_hi == t_lo, "must be same");
735 move_regs(f_lo, t_lo);
736
737 } else if (dest->is_single_fpu()) {
738 __ fmovs(dest->as_float_reg(), src->as_float_reg());
739
740 } else if (dest->is_double_fpu()) {
741 __ fmovd(dest->as_double_reg(), src->as_double_reg());
742
743 } else {
744 ShouldNotReachHere();
745 }
746 }
747
748 void LIR_Assembler::reg2stack(LIR_Opr src, LIR_Opr dest, BasicType type, bool pop_fpu_stack) {
749 if (src->is_single_cpu()) {
750 if (type == T_ARRAY || type == T_OBJECT || type == T_VALUETYPE) {
751 __ str(src->as_register(), frame_map()->address_for_slot(dest->single_stack_ix()));
752 __ verify_oop(src->as_register());
753 } else if (type == T_METADATA || type == T_DOUBLE) {
754 __ str(src->as_register(), frame_map()->address_for_slot(dest->single_stack_ix()));
755 } else {
756 __ strw(src->as_register(), frame_map()->address_for_slot(dest->single_stack_ix()));
757 }
758
759 } else if (src->is_double_cpu()) {
760 Address dest_addr_LO = frame_map()->address_for_slot(dest->double_stack_ix(), lo_word_offset_in_bytes);
761 __ str(src->as_register_lo(), dest_addr_LO);
762
763 } else if (src->is_single_fpu()) {
764 Address dest_addr = frame_map()->address_for_slot(dest->single_stack_ix());
765 __ strs(src->as_float_reg(), dest_addr);
766
767 } else if (src->is_double_fpu()) {
768 Address dest_addr = frame_map()->address_for_slot(dest->double_stack_ix());
769 __ strd(src->as_double_reg(), dest_addr);
770
771 } else {
772 ShouldNotReachHere();
773 }
774
775 }
776
777
778 void LIR_Assembler::reg2mem(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool pop_fpu_stack, bool wide, bool /* unaligned */) {
779 LIR_Address* to_addr = dest->as_address_ptr();
780 PatchingStub* patch = NULL;
781 Register compressed_src = rscratch1;
782
783 if (patch_code != lir_patch_none) {
784 deoptimize_trap(info);
785 return;
786 }
787
788 if (type == T_ARRAY || type == T_OBJECT || type == T_VALUETYPE) {
789 __ verify_oop(src->as_register());
790
791 if (UseCompressedOops && !wide) {
792 __ encode_heap_oop(compressed_src, src->as_register());
793 } else {
794 compressed_src = src->as_register();
795 }
796 }
797
798 int null_check_here = code_offset();
799 switch (type) {
800 case T_FLOAT: {
801 __ strs(src->as_float_reg(), as_Address(to_addr));
802 break;
803 }
804
805 case T_DOUBLE: {
806 __ strd(src->as_double_reg(), as_Address(to_addr));
807 break;
808 }
809
810 case T_VALUETYPE: // fall through
811 case T_ARRAY: // fall through
812 case T_OBJECT: // fall through
813 if (UseCompressedOops && !wide) {
814 __ strw(compressed_src, as_Address(to_addr, rscratch2));
815 } else {
816 __ str(compressed_src, as_Address(to_addr));
817 }
818 break;
819 case T_METADATA:
820 // We get here to store a method pointer to the stack to pass to
821 // a dtrace runtime call. This can't work on 64 bit with
822 // compressed klass ptrs: T_METADATA can be a compressed klass
823 // ptr or a 64 bit method pointer.
824 ShouldNotReachHere();
825 __ str(src->as_register(), as_Address(to_addr));
826 break;
827 case T_ADDRESS:
828 __ str(src->as_register(), as_Address(to_addr));
829 break;
830 case T_INT:
831 __ strw(src->as_register(), as_Address(to_addr));
832 break;
833
834 case T_LONG: {
835 __ str(src->as_register_lo(), as_Address_lo(to_addr));
836 break;
837 }
838
839 case T_BYTE: // fall through
840 case T_BOOLEAN: {
841 __ strb(src->as_register(), as_Address(to_addr));
842 break;
843 }
844
845 case T_CHAR: // fall through
846 case T_SHORT:
847 __ strh(src->as_register(), as_Address(to_addr));
848 break;
849
850 default:
851 ShouldNotReachHere();
852 }
853 if (info != NULL) {
854 add_debug_info_for_null_check(null_check_here, info);
855 }
856 }
857
858
859 void LIR_Assembler::stack2reg(LIR_Opr src, LIR_Opr dest, BasicType type) {
860 assert(src->is_stack(), "should not call otherwise");
861 assert(dest->is_register(), "should not call otherwise");
862
863 if (dest->is_single_cpu()) {
864 if (type == T_ARRAY || type == T_OBJECT || type == T_VALUETYPE) {
865 __ ldr(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix()));
866 __ verify_oop(dest->as_register());
867 } else if (type == T_METADATA) {
868 __ ldr(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix()));
869 } else {
870 __ ldrw(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix()));
871 }
872
873 } else if (dest->is_double_cpu()) {
874 Address src_addr_LO = frame_map()->address_for_slot(src->double_stack_ix(), lo_word_offset_in_bytes);
875 __ ldr(dest->as_register_lo(), src_addr_LO);
876
877 } else if (dest->is_single_fpu()) {
878 Address src_addr = frame_map()->address_for_slot(src->single_stack_ix());
879 __ ldrs(dest->as_float_reg(), src_addr);
880
881 } else if (dest->is_double_fpu()) {
882 Address src_addr = frame_map()->address_for_slot(src->double_stack_ix());
883 __ ldrd(dest->as_double_reg(), src_addr);
884
885 } else {
886 ShouldNotReachHere();
887 }
888 }
889
890
891 void LIR_Assembler::klass2reg_with_patching(Register reg, CodeEmitInfo* info) {
892 address target = NULL;
893 relocInfo::relocType reloc_type = relocInfo::none;
894
895 switch (patching_id(info)) {
896 case PatchingStub::access_field_id:
897 target = Runtime1::entry_for(Runtime1::access_field_patching_id);
898 reloc_type = relocInfo::section_word_type;
899 break;
900 case PatchingStub::load_klass_id:
901 target = Runtime1::entry_for(Runtime1::load_klass_patching_id);
902 reloc_type = relocInfo::metadata_type;
903 break;
904 case PatchingStub::load_mirror_id:
905 target = Runtime1::entry_for(Runtime1::load_mirror_patching_id);
906 reloc_type = relocInfo::oop_type;
907 break;
908 case PatchingStub::load_appendix_id:
909 target = Runtime1::entry_for(Runtime1::load_appendix_patching_id);
910 reloc_type = relocInfo::oop_type;
911 break;
912 default: ShouldNotReachHere();
913 }
914
915 __ far_call(RuntimeAddress(target));
916 add_call_info_here(info);
917 }
918
919 void LIR_Assembler::stack2stack(LIR_Opr src, LIR_Opr dest, BasicType type) {
920
921 LIR_Opr temp;
922 if (type == T_LONG || type == T_DOUBLE)
923 temp = FrameMap::rscratch1_long_opr;
924 else
925 temp = FrameMap::rscratch1_opr;
926
927 stack2reg(src, temp, src->type());
928 reg2stack(temp, dest, dest->type(), false);
929 }
930
931
932 void LIR_Assembler::mem2reg(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool wide, bool /* unaligned */) {
933 LIR_Address* addr = src->as_address_ptr();
934 LIR_Address* from_addr = src->as_address_ptr();
935
936 if (addr->base()->type() == T_OBJECT || addr->base()->type() == T_VALUETYPE) {
937 __ verify_oop(addr->base()->as_pointer_register());
938 }
939
940 if (patch_code != lir_patch_none) {
941 deoptimize_trap(info);
942 return;
943 }
944
945 if (info != NULL) {
946 add_debug_info_for_null_check_here(info);
947 }
948 int null_check_here = code_offset();
949 switch (type) {
950 case T_FLOAT: {
951 __ ldrs(dest->as_float_reg(), as_Address(from_addr));
952 break;
953 }
954
955 case T_DOUBLE: {
956 __ ldrd(dest->as_double_reg(), as_Address(from_addr));
957 break;
958 }
959
960 case T_VALUETYPE: // fall through
961 case T_ARRAY: // fall through
962 case T_OBJECT: // fall through
963 if (UseCompressedOops && !wide) {
964 __ ldrw(dest->as_register(), as_Address(from_addr));
965 } else {
966 __ ldr(dest->as_register(), as_Address(from_addr));
967 }
968 break;
969 case T_METADATA:
970 // We get here to store a method pointer to the stack to pass to
971 // a dtrace runtime call. This can't work on 64 bit with
972 // compressed klass ptrs: T_METADATA can be a compressed klass
973 // ptr or a 64 bit method pointer.
974 ShouldNotReachHere();
975 __ ldr(dest->as_register(), as_Address(from_addr));
976 break;
977 case T_ADDRESS:
978 // FIXME: OMG this is a horrible kludge. Any offset from an
979 // address that matches klass_offset_in_bytes() will be loaded
980 // as a word, not a long.
981 if (UseCompressedClassPointers && addr->disp() == oopDesc::klass_offset_in_bytes()) {
982 __ ldrw(dest->as_register(), as_Address(from_addr));
983 } else {
984 __ ldr(dest->as_register(), as_Address(from_addr));
985 }
986 break;
987 case T_INT:
988 __ ldrw(dest->as_register(), as_Address(from_addr));
989 break;
990
991 case T_LONG: {
992 __ ldr(dest->as_register_lo(), as_Address_lo(from_addr));
993 break;
994 }
995
996 case T_BYTE:
997 __ ldrsb(dest->as_register(), as_Address(from_addr));
998 break;
999 case T_BOOLEAN: {
1000 __ ldrb(dest->as_register(), as_Address(from_addr));
1001 break;
1002 }
1003
1004 case T_CHAR:
1005 __ ldrh(dest->as_register(), as_Address(from_addr));
1006 break;
1007 case T_SHORT:
1008 __ ldrsh(dest->as_register(), as_Address(from_addr));
1009 break;
1010
1011 default:
1012 ShouldNotReachHere();
1013 }
1014
1015 if (type == T_ARRAY || type == T_OBJECT || type == T_VALUETYPE) {
1016 if (UseCompressedOops && !wide) {
1017 __ decode_heap_oop(dest->as_register());
1018 }
1019 __ verify_oop(dest->as_register());
1020 } else if (type == T_ADDRESS && addr->disp() == oopDesc::klass_offset_in_bytes()) {
1021 if (UseCompressedClassPointers) {
1022 __ decode_klass_not_null(dest->as_register());
1023 }
1024 }
1025 }
1026
1027
1028 int LIR_Assembler::array_element_size(BasicType type) const {
1029 int elem_size = type2aelembytes(type);
1030 return exact_log2(elem_size);
1031 }
1032
1033
1034 void LIR_Assembler::emit_op3(LIR_Op3* op) {
1035 switch (op->code()) {
1036 case lir_idiv:
1037 case lir_irem:
1038 arithmetic_idiv(op->code(),
1039 op->in_opr1(),
1040 op->in_opr2(),
1041 op->in_opr3(),
1042 op->result_opr(),
1043 op->info());
1044 break;
1045 case lir_fmad:
1046 __ fmaddd(op->result_opr()->as_double_reg(),
1047 op->in_opr1()->as_double_reg(),
1048 op->in_opr2()->as_double_reg(),
1049 op->in_opr3()->as_double_reg());
1050 break;
1051 case lir_fmaf:
1052 __ fmadds(op->result_opr()->as_float_reg(),
1053 op->in_opr1()->as_float_reg(),
1054 op->in_opr2()->as_float_reg(),
1055 op->in_opr3()->as_float_reg());
1056 break;
1057 default: ShouldNotReachHere(); break;
1058 }
1059 }
1060
1061 void LIR_Assembler::emit_opBranch(LIR_OpBranch* op) {
1062 #ifdef ASSERT
1063 assert(op->block() == NULL || op->block()->label() == op->label(), "wrong label");
1064 if (op->block() != NULL) _branch_target_blocks.append(op->block());
1065 if (op->ublock() != NULL) _branch_target_blocks.append(op->ublock());
1066 #endif
1067
1068 if (op->cond() == lir_cond_always) {
1069 if (op->info() != NULL) add_debug_info_for_branch(op->info());
1070 __ b(*(op->label()));
1071 } else {
1072 Assembler::Condition acond;
1073 if (op->code() == lir_cond_float_branch) {
1074 bool is_unordered = (op->ublock() == op->block());
1075 // Assembler::EQ does not permit unordered branches, so we add
1076 // another branch here. Likewise, Assembler::NE does not permit
1077 // ordered branches.
1078 if (is_unordered && op->cond() == lir_cond_equal
1079 || !is_unordered && op->cond() == lir_cond_notEqual)
1080 __ br(Assembler::VS, *(op->ublock()->label()));
1081 switch(op->cond()) {
1082 case lir_cond_equal: acond = Assembler::EQ; break;
1083 case lir_cond_notEqual: acond = Assembler::NE; break;
1084 case lir_cond_less: acond = (is_unordered ? Assembler::LT : Assembler::LO); break;
1085 case lir_cond_lessEqual: acond = (is_unordered ? Assembler::LE : Assembler::LS); break;
1086 case lir_cond_greaterEqual: acond = (is_unordered ? Assembler::HS : Assembler::GE); break;
1087 case lir_cond_greater: acond = (is_unordered ? Assembler::HI : Assembler::GT); break;
1088 default: ShouldNotReachHere();
1089 acond = Assembler::EQ; // unreachable
1090 }
1091 } else {
1092 switch (op->cond()) {
1093 case lir_cond_equal: acond = Assembler::EQ; break;
1094 case lir_cond_notEqual: acond = Assembler::NE; break;
1095 case lir_cond_less: acond = Assembler::LT; break;
1096 case lir_cond_lessEqual: acond = Assembler::LE; break;
1097 case lir_cond_greaterEqual: acond = Assembler::GE; break;
1098 case lir_cond_greater: acond = Assembler::GT; break;
1099 case lir_cond_belowEqual: acond = Assembler::LS; break;
1100 case lir_cond_aboveEqual: acond = Assembler::HS; break;
1101 default: ShouldNotReachHere();
1102 acond = Assembler::EQ; // unreachable
1103 }
1104 }
1105 __ br(acond,*(op->label()));
1106 }
1107 }
1108
1109
1110
1111 void LIR_Assembler::emit_opConvert(LIR_OpConvert* op) {
1112 LIR_Opr src = op->in_opr();
1113 LIR_Opr dest = op->result_opr();
1114
1115 switch (op->bytecode()) {
1116 case Bytecodes::_i2f:
1117 {
1118 __ scvtfws(dest->as_float_reg(), src->as_register());
1119 break;
1120 }
1121 case Bytecodes::_i2d:
1122 {
1123 __ scvtfwd(dest->as_double_reg(), src->as_register());
1124 break;
1125 }
1126 case Bytecodes::_l2d:
1127 {
1128 __ scvtfd(dest->as_double_reg(), src->as_register_lo());
1129 break;
1130 }
1131 case Bytecodes::_l2f:
1132 {
1133 __ scvtfs(dest->as_float_reg(), src->as_register_lo());
1134 break;
1135 }
1136 case Bytecodes::_f2d:
1137 {
1138 __ fcvts(dest->as_double_reg(), src->as_float_reg());
1139 break;
1140 }
1141 case Bytecodes::_d2f:
1142 {
1143 __ fcvtd(dest->as_float_reg(), src->as_double_reg());
1144 break;
1145 }
1146 case Bytecodes::_i2c:
1147 {
1148 __ ubfx(dest->as_register(), src->as_register(), 0, 16);
1149 break;
1150 }
1151 case Bytecodes::_i2l:
1152 {
1153 __ sxtw(dest->as_register_lo(), src->as_register());
1154 break;
1155 }
1156 case Bytecodes::_i2s:
1157 {
1158 __ sxth(dest->as_register(), src->as_register());
1159 break;
1160 }
1161 case Bytecodes::_i2b:
1162 {
1163 __ sxtb(dest->as_register(), src->as_register());
1164 break;
1165 }
1166 case Bytecodes::_l2i:
1167 {
1168 _masm->block_comment("FIXME: This could be a no-op");
1169 __ uxtw(dest->as_register(), src->as_register_lo());
1170 break;
1171 }
1172 case Bytecodes::_d2l:
1173 {
1174 __ fcvtzd(dest->as_register_lo(), src->as_double_reg());
1175 break;
1176 }
1177 case Bytecodes::_f2i:
1178 {
1179 __ fcvtzsw(dest->as_register(), src->as_float_reg());
1180 break;
1181 }
1182 case Bytecodes::_f2l:
1183 {
1184 __ fcvtzs(dest->as_register_lo(), src->as_float_reg());
1185 break;
1186 }
1187 case Bytecodes::_d2i:
1188 {
1189 __ fcvtzdw(dest->as_register(), src->as_double_reg());
1190 break;
1191 }
1192 default: ShouldNotReachHere();
1193 }
1194 }
1195
1196 void LIR_Assembler::emit_alloc_obj(LIR_OpAllocObj* op) {
1197 if (op->init_check()) {
1198 __ ldrb(rscratch1, Address(op->klass()->as_register(),
1199 InstanceKlass::init_state_offset()));
1200 __ cmpw(rscratch1, InstanceKlass::fully_initialized);
1201 add_debug_info_for_null_check_here(op->stub()->info());
1202 __ br(Assembler::NE, *op->stub()->entry());
1203 }
1204 __ allocate_object(op->obj()->as_register(),
1205 op->tmp1()->as_register(),
1206 op->tmp2()->as_register(),
1207 op->header_size(),
1208 op->object_size(),
1209 op->klass()->as_register(),
1210 *op->stub()->entry());
1211 __ bind(*op->stub()->continuation());
1212 }
1213
1214 void LIR_Assembler::emit_alloc_array(LIR_OpAllocArray* op) {
1215 Register len = op->len()->as_register();
1216 __ uxtw(len, len);
1217
1218 if (UseSlowPath || op->type() == T_VALUETYPE ||
1219 (!UseFastNewObjectArray && (op->type() == T_OBJECT || op->type() == T_ARRAY)) ||
1220 (!UseFastNewTypeArray && (op->type() != T_OBJECT && op->type() != T_ARRAY))) {
1221 __ b(*op->stub()->entry());
1222 } else {
1223 Register tmp1 = op->tmp1()->as_register();
1224 Register tmp2 = op->tmp2()->as_register();
1225 Register tmp3 = op->tmp3()->as_register();
1226 if (len == tmp1) {
1227 tmp1 = tmp3;
1228 } else if (len == tmp2) {
1229 tmp2 = tmp3;
1230 } else if (len == tmp3) {
1231 // everything is ok
1232 } else {
1233 __ mov(tmp3, len);
1234 }
1235 __ allocate_array(op->obj()->as_register(),
1236 len,
1237 tmp1,
1238 tmp2,
1239 arrayOopDesc::header_size(op->type()),
1240 array_element_size(op->type()),
1241 op->klass()->as_register(),
1242 *op->stub()->entry());
1243 }
1244 __ bind(*op->stub()->continuation());
1245 }
1246
1247 void LIR_Assembler::type_profile_helper(Register mdo,
1248 ciMethodData *md, ciProfileData *data,
1249 Register recv, Label* update_done) {
1250 for (uint i = 0; i < ReceiverTypeData::row_limit(); i++) {
1251 Label next_test;
1252 // See if the receiver is receiver[n].
1253 __ lea(rscratch2, Address(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i))));
1254 __ ldr(rscratch1, Address(rscratch2));
1255 __ cmp(recv, rscratch1);
1256 __ br(Assembler::NE, next_test);
1257 Address data_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i)));
1258 __ addptr(data_addr, DataLayout::counter_increment);
1259 __ b(*update_done);
1260 __ bind(next_test);
1261 }
1262
1263 // Didn't find receiver; find next empty slot and fill it in
1264 for (uint i = 0; i < ReceiverTypeData::row_limit(); i++) {
1265 Label next_test;
1266 __ lea(rscratch2,
1267 Address(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i))));
1268 Address recv_addr(rscratch2);
1269 __ ldr(rscratch1, recv_addr);
1270 __ cbnz(rscratch1, next_test);
1271 __ str(recv, recv_addr);
1272 __ mov(rscratch1, DataLayout::counter_increment);
1273 __ lea(rscratch2, Address(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i))));
1274 __ str(rscratch1, Address(rscratch2));
1275 __ b(*update_done);
1276 __ bind(next_test);
1277 }
1278 }
1279
1280 void LIR_Assembler::emit_typecheck_helper(LIR_OpTypeCheck *op, Label* success, Label* failure, Label* obj_is_null) {
1281 // we always need a stub for the failure case.
1282 CodeStub* stub = op->stub();
1283 Register obj = op->object()->as_register();
1284 Register k_RInfo = op->tmp1()->as_register();
1285 Register klass_RInfo = op->tmp2()->as_register();
1286 Register dst = op->result_opr()->as_register();
1287 ciKlass* k = op->klass();
1288 Register Rtmp1 = noreg;
1289
1290 // check if it needs to be profiled
1291 ciMethodData* md;
1292 ciProfileData* data;
1293
1294 const bool should_profile = op->should_profile();
1295
1296 if (should_profile) {
1297 ciMethod* method = op->profiled_method();
1298 assert(method != NULL, "Should have method");
1299 int bci = op->profiled_bci();
1300 md = method->method_data_or_null();
1301 assert(md != NULL, "Sanity");
1302 data = md->bci_to_data(bci);
1303 assert(data != NULL, "need data for type check");
1304 assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check");
1305 }
1306 Label profile_cast_success, profile_cast_failure;
1307 Label *success_target = should_profile ? &profile_cast_success : success;
1308 Label *failure_target = should_profile ? &profile_cast_failure : failure;
1309
1310 if (obj == k_RInfo) {
1311 k_RInfo = dst;
1312 } else if (obj == klass_RInfo) {
1313 klass_RInfo = dst;
1314 }
1315 if (k->is_loaded() && !UseCompressedClassPointers) {
1316 select_different_registers(obj, dst, k_RInfo, klass_RInfo);
1317 } else {
1318 Rtmp1 = op->tmp3()->as_register();
1319 select_different_registers(obj, dst, k_RInfo, klass_RInfo, Rtmp1);
1320 }
1321
1322 assert_different_registers(obj, k_RInfo, klass_RInfo);
1323
1324 if (should_profile) {
1325 Label not_null;
1326 __ cbnz(obj, not_null);
1327 // Object is null; update MDO and exit
1328 Register mdo = klass_RInfo;
1329 __ mov_metadata(mdo, md->constant_encoding());
1330 Address data_addr
1331 = __ form_address(rscratch2, mdo,
1332 md->byte_offset_of_slot(data, DataLayout::flags_offset()),
1333 0);
1334 __ ldrb(rscratch1, data_addr);
1335 __ orr(rscratch1, rscratch1, BitData::null_seen_byte_constant());
1336 __ strb(rscratch1, data_addr);
1337 __ b(*obj_is_null);
1338 __ bind(not_null);
1339 } else {
1340 __ cbz(obj, *obj_is_null);
1341 }
1342
1343 if (!k->is_loaded()) {
1344 klass2reg_with_patching(k_RInfo, op->info_for_patch());
1345 } else {
1346 __ mov_metadata(k_RInfo, k->constant_encoding());
1347 }
1348 __ verify_oop(obj);
1349
1350 if (op->fast_check()) {
1351 // get object class
1352 // not a safepoint as obj null check happens earlier
1353 __ load_klass(rscratch1, obj);
1354 __ cmp( rscratch1, k_RInfo);
1355
1356 __ br(Assembler::NE, *failure_target);
1357 // successful cast, fall through to profile or jump
1358 } else {
1359 // get object class
1360 // not a safepoint as obj null check happens earlier
1361 __ load_klass(klass_RInfo, obj);
1362 if (k->is_loaded()) {
1363 // See if we get an immediate positive hit
1364 __ ldr(rscratch1, Address(klass_RInfo, long(k->super_check_offset())));
1365 __ cmp(k_RInfo, rscratch1);
1366 if ((juint)in_bytes(Klass::secondary_super_cache_offset()) != k->super_check_offset()) {
1367 __ br(Assembler::NE, *failure_target);
1368 // successful cast, fall through to profile or jump
1369 } else {
1370 // See if we get an immediate positive hit
1371 __ br(Assembler::EQ, *success_target);
1372 // check for self
1373 __ cmp(klass_RInfo, k_RInfo);
1374 __ br(Assembler::EQ, *success_target);
1375
1376 __ stp(klass_RInfo, k_RInfo, Address(__ pre(sp, -2 * wordSize)));
1377 __ far_call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id)));
1378 __ ldr(klass_RInfo, Address(__ post(sp, 2 * wordSize)));
1379 // result is a boolean
1380 __ cbzw(klass_RInfo, *failure_target);
1381 // successful cast, fall through to profile or jump
1382 }
1383 } else {
1384 // perform the fast part of the checking logic
1385 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, success_target, failure_target, NULL);
1386 // call out-of-line instance of __ check_klass_subtype_slow_path(...):
1387 __ stp(klass_RInfo, k_RInfo, Address(__ pre(sp, -2 * wordSize)));
1388 __ far_call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id)));
1389 __ ldp(k_RInfo, klass_RInfo, Address(__ post(sp, 2 * wordSize)));
1390 // result is a boolean
1391 __ cbz(k_RInfo, *failure_target);
1392 // successful cast, fall through to profile or jump
1393 }
1394 }
1395 if (should_profile) {
1396 Register mdo = klass_RInfo, recv = k_RInfo;
1397 __ bind(profile_cast_success);
1398 __ mov_metadata(mdo, md->constant_encoding());
1399 __ load_klass(recv, obj);
1400 Label update_done;
1401 type_profile_helper(mdo, md, data, recv, success);
1402 __ b(*success);
1403
1404 __ bind(profile_cast_failure);
1405 __ mov_metadata(mdo, md->constant_encoding());
1406 Address counter_addr
1407 = __ form_address(rscratch2, mdo,
1408 md->byte_offset_of_slot(data, CounterData::count_offset()),
1409 0);
1410 __ ldr(rscratch1, counter_addr);
1411 __ sub(rscratch1, rscratch1, DataLayout::counter_increment);
1412 __ str(rscratch1, counter_addr);
1413 __ b(*failure);
1414 }
1415 __ b(*success);
1416 }
1417
1418
1419 void LIR_Assembler::emit_opTypeCheck(LIR_OpTypeCheck* op) {
1420 const bool should_profile = op->should_profile();
1421
1422 LIR_Code code = op->code();
1423 if (code == lir_store_check) {
1424 Register value = op->object()->as_register();
1425 Register array = op->array()->as_register();
1426 Register k_RInfo = op->tmp1()->as_register();
1427 Register klass_RInfo = op->tmp2()->as_register();
1428 Register Rtmp1 = op->tmp3()->as_register();
1429
1430 CodeStub* stub = op->stub();
1431
1432 // check if it needs to be profiled
1433 ciMethodData* md;
1434 ciProfileData* data;
1435
1436 if (should_profile) {
1437 ciMethod* method = op->profiled_method();
1438 assert(method != NULL, "Should have method");
1439 int bci = op->profiled_bci();
1440 md = method->method_data_or_null();
1441 assert(md != NULL, "Sanity");
1442 data = md->bci_to_data(bci);
1443 assert(data != NULL, "need data for type check");
1444 assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check");
1445 }
1446 Label profile_cast_success, profile_cast_failure, done;
1447 Label *success_target = should_profile ? &profile_cast_success : &done;
1448 Label *failure_target = should_profile ? &profile_cast_failure : stub->entry();
1449
1450 if (should_profile) {
1451 Label not_null;
1452 __ cbnz(value, not_null);
1453 // Object is null; update MDO and exit
1454 Register mdo = klass_RInfo;
1455 __ mov_metadata(mdo, md->constant_encoding());
1456 Address data_addr
1457 = __ form_address(rscratch2, mdo,
1458 md->byte_offset_of_slot(data, DataLayout::flags_offset()),
1459 0);
1460 __ ldrb(rscratch1, data_addr);
1461 __ orr(rscratch1, rscratch1, BitData::null_seen_byte_constant());
1462 __ strb(rscratch1, data_addr);
1463 __ b(done);
1464 __ bind(not_null);
1465 } else {
1466 __ cbz(value, done);
1467 }
1468
1469 add_debug_info_for_null_check_here(op->info_for_exception());
1470 __ load_klass(k_RInfo, array);
1471 __ load_klass(klass_RInfo, value);
1472
1473 // get instance klass (it's already uncompressed)
1474 __ ldr(k_RInfo, Address(k_RInfo, ObjArrayKlass::element_klass_offset()));
1475 // perform the fast part of the checking logic
1476 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, success_target, failure_target, NULL);
1477 // call out-of-line instance of __ check_klass_subtype_slow_path(...):
1478 __ stp(klass_RInfo, k_RInfo, Address(__ pre(sp, -2 * wordSize)));
1479 __ far_call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id)));
1480 __ ldp(k_RInfo, klass_RInfo, Address(__ post(sp, 2 * wordSize)));
1481 // result is a boolean
1482 __ cbzw(k_RInfo, *failure_target);
1483 // fall through to the success case
1484
1485 if (should_profile) {
1486 Register mdo = klass_RInfo, recv = k_RInfo;
1487 __ bind(profile_cast_success);
1488 __ mov_metadata(mdo, md->constant_encoding());
1489 __ load_klass(recv, value);
1490 Label update_done;
1491 type_profile_helper(mdo, md, data, recv, &done);
1492 __ b(done);
1493
1494 __ bind(profile_cast_failure);
1495 __ mov_metadata(mdo, md->constant_encoding());
1496 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()));
1497 __ lea(rscratch2, counter_addr);
1498 __ ldr(rscratch1, Address(rscratch2));
1499 __ sub(rscratch1, rscratch1, DataLayout::counter_increment);
1500 __ str(rscratch1, Address(rscratch2));
1501 __ b(*stub->entry());
1502 }
1503
1504 __ bind(done);
1505 } else if (code == lir_checkcast) {
1506 Register obj = op->object()->as_register();
1507 Register dst = op->result_opr()->as_register();
1508 Label success;
1509 emit_typecheck_helper(op, &success, op->stub()->entry(), &success);
1510 __ bind(success);
1511 if (dst != obj) {
1512 __ mov(dst, obj);
1513 }
1514 } else if (code == lir_instanceof) {
1515 Register obj = op->object()->as_register();
1516 Register dst = op->result_opr()->as_register();
1517 Label success, failure, done;
1518 emit_typecheck_helper(op, &success, &failure, &failure);
1519 __ bind(failure);
1520 __ mov(dst, zr);
1521 __ b(done);
1522 __ bind(success);
1523 __ mov(dst, 1);
1524 __ bind(done);
1525 } else {
1526 ShouldNotReachHere();
1527 }
1528 }
1529
1530 void LIR_Assembler::casw(Register addr, Register newval, Register cmpval) {
1531 __ cmpxchg(addr, cmpval, newval, Assembler::word, /* acquire*/ true, /* release*/ true, /* weak*/ false, rscratch1);
1532 __ cset(rscratch1, Assembler::NE);
1533 __ membar(__ AnyAny);
1534 }
1535
1536 void LIR_Assembler::casl(Register addr, Register newval, Register cmpval) {
1537 __ cmpxchg(addr, cmpval, newval, Assembler::xword, /* acquire*/ true, /* release*/ true, /* weak*/ false, rscratch1);
1538 __ cset(rscratch1, Assembler::NE);
1539 __ membar(__ AnyAny);
1540 }
1541
1542
1543 void LIR_Assembler::emit_compare_and_swap(LIR_OpCompareAndSwap* op) {
1544 assert(VM_Version::supports_cx8(), "wrong machine");
1545 Register addr;
1546 if (op->addr()->is_register()) {
1547 addr = as_reg(op->addr());
1548 } else {
1549 assert(op->addr()->is_address(), "what else?");
1550 LIR_Address* addr_ptr = op->addr()->as_address_ptr();
1551 assert(addr_ptr->disp() == 0, "need 0 disp");
1552 assert(addr_ptr->index() == LIR_OprDesc::illegalOpr(), "need 0 index");
1553 addr = as_reg(addr_ptr->base());
1554 }
1555 Register newval = as_reg(op->new_value());
1556 Register cmpval = as_reg(op->cmp_value());
1557
1558 if (op->code() == lir_cas_obj) {
1559 if (UseCompressedOops) {
1560 Register t1 = op->tmp1()->as_register();
1561 assert(op->tmp1()->is_valid(), "must be");
1562 __ encode_heap_oop(t1, cmpval);
1563 cmpval = t1;
1564 __ encode_heap_oop(rscratch2, newval);
1565 newval = rscratch2;
1566 casw(addr, newval, cmpval);
1567 } else {
1568 casl(addr, newval, cmpval);
1569 }
1570 } else if (op->code() == lir_cas_int) {
1571 casw(addr, newval, cmpval);
1572 } else {
1573 casl(addr, newval, cmpval);
1574 }
1575 }
1576
1577
1578 void LIR_Assembler::cmove(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Opr result, BasicType type) {
1579
1580 Assembler::Condition acond, ncond;
1581 switch (condition) {
1582 case lir_cond_equal: acond = Assembler::EQ; ncond = Assembler::NE; break;
1583 case lir_cond_notEqual: acond = Assembler::NE; ncond = Assembler::EQ; break;
1584 case lir_cond_less: acond = Assembler::LT; ncond = Assembler::GE; break;
1585 case lir_cond_lessEqual: acond = Assembler::LE; ncond = Assembler::GT; break;
1586 case lir_cond_greaterEqual: acond = Assembler::GE; ncond = Assembler::LT; break;
1587 case lir_cond_greater: acond = Assembler::GT; ncond = Assembler::LE; break;
1588 case lir_cond_belowEqual:
1589 case lir_cond_aboveEqual:
1590 default: ShouldNotReachHere();
1591 acond = Assembler::EQ; ncond = Assembler::NE; // unreachable
1592 }
1593
1594 assert(result->is_single_cpu() || result->is_double_cpu(),
1595 "expect single register for result");
1596 if (opr1->is_constant() && opr2->is_constant()
1597 && opr1->type() == T_INT && opr2->type() == T_INT) {
1598 jint val1 = opr1->as_jint();
1599 jint val2 = opr2->as_jint();
1600 if (val1 == 0 && val2 == 1) {
1601 __ cset(result->as_register(), ncond);
1602 return;
1603 } else if (val1 == 1 && val2 == 0) {
1604 __ cset(result->as_register(), acond);
1605 return;
1606 }
1607 }
1608
1609 if (opr1->is_constant() && opr2->is_constant()
1610 && opr1->type() == T_LONG && opr2->type() == T_LONG) {
1611 jlong val1 = opr1->as_jlong();
1612 jlong val2 = opr2->as_jlong();
1613 if (val1 == 0 && val2 == 1) {
1614 __ cset(result->as_register_lo(), ncond);
1615 return;
1616 } else if (val1 == 1 && val2 == 0) {
1617 __ cset(result->as_register_lo(), acond);
1618 return;
1619 }
1620 }
1621
1622 if (opr1->is_stack()) {
1623 stack2reg(opr1, FrameMap::rscratch1_opr, result->type());
1624 opr1 = FrameMap::rscratch1_opr;
1625 } else if (opr1->is_constant()) {
1626 LIR_Opr tmp
1627 = opr1->type() == T_LONG ? FrameMap::rscratch1_long_opr : FrameMap::rscratch1_opr;
1628 const2reg(opr1, tmp, lir_patch_none, NULL);
1629 opr1 = tmp;
1630 }
1631
1632 if (opr2->is_stack()) {
1633 stack2reg(opr2, FrameMap::rscratch2_opr, result->type());
1634 opr2 = FrameMap::rscratch2_opr;
1635 } else if (opr2->is_constant()) {
1636 LIR_Opr tmp
1637 = opr2->type() == T_LONG ? FrameMap::rscratch2_long_opr : FrameMap::rscratch2_opr;
1638 const2reg(opr2, tmp, lir_patch_none, NULL);
1639 opr2 = tmp;
1640 }
1641
1642 if (result->type() == T_LONG)
1643 __ csel(result->as_register_lo(), opr1->as_register_lo(), opr2->as_register_lo(), acond);
1644 else
1645 __ csel(result->as_register(), opr1->as_register(), opr2->as_register(), acond);
1646 }
1647
1648 void LIR_Assembler::arith_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest, CodeEmitInfo* info, bool pop_fpu_stack) {
1649 assert(info == NULL, "should never be used, idiv/irem and ldiv/lrem not handled by this method");
1650
1651 if (left->is_single_cpu()) {
1652 Register lreg = left->as_register();
1653 Register dreg = as_reg(dest);
1654
1655 if (right->is_single_cpu()) {
1656 // cpu register - cpu register
1657
1658 assert(left->type() == T_INT && right->type() == T_INT && dest->type() == T_INT,
1659 "should be");
1660 Register rreg = right->as_register();
1661 switch (code) {
1662 case lir_add: __ addw (dest->as_register(), lreg, rreg); break;
1663 case lir_sub: __ subw (dest->as_register(), lreg, rreg); break;
1664 case lir_mul: __ mulw (dest->as_register(), lreg, rreg); break;
1665 default: ShouldNotReachHere();
1666 }
1667
1668 } else if (right->is_double_cpu()) {
1669 Register rreg = right->as_register_lo();
1670 // single_cpu + double_cpu: can happen with obj+long
1671 assert(code == lir_add || code == lir_sub, "mismatched arithmetic op");
1672 switch (code) {
1673 case lir_add: __ add(dreg, lreg, rreg); break;
1674 case lir_sub: __ sub(dreg, lreg, rreg); break;
1675 default: ShouldNotReachHere();
1676 }
1677 } else if (right->is_constant()) {
1678 // cpu register - constant
1679 jlong c;
1680
1681 // FIXME. This is fugly: we really need to factor all this logic.
1682 switch(right->type()) {
1683 case T_LONG:
1684 c = right->as_constant_ptr()->as_jlong();
1685 break;
1686 case T_INT:
1687 case T_ADDRESS:
1688 c = right->as_constant_ptr()->as_jint();
1689 break;
1690 default:
1691 ShouldNotReachHere();
1692 c = 0; // unreachable
1693 break;
1694 }
1695
1696 assert(code == lir_add || code == lir_sub, "mismatched arithmetic op");
1697 if (c == 0 && dreg == lreg) {
1698 COMMENT("effective nop elided");
1699 return;
1700 }
1701 switch(left->type()) {
1702 case T_INT:
1703 switch (code) {
1704 case lir_add: __ addw(dreg, lreg, c); break;
1705 case lir_sub: __ subw(dreg, lreg, c); break;
1706 default: ShouldNotReachHere();
1707 }
1708 break;
1709 case T_OBJECT:
1710 case T_ADDRESS:
1711 switch (code) {
1712 case lir_add: __ add(dreg, lreg, c); break;
1713 case lir_sub: __ sub(dreg, lreg, c); break;
1714 default: ShouldNotReachHere();
1715 }
1716 break;
1717 default:
1718 ShouldNotReachHere();
1719 }
1720 } else {
1721 ShouldNotReachHere();
1722 }
1723
1724 } else if (left->is_double_cpu()) {
1725 Register lreg_lo = left->as_register_lo();
1726
1727 if (right->is_double_cpu()) {
1728 // cpu register - cpu register
1729 Register rreg_lo = right->as_register_lo();
1730 switch (code) {
1731 case lir_add: __ add (dest->as_register_lo(), lreg_lo, rreg_lo); break;
1732 case lir_sub: __ sub (dest->as_register_lo(), lreg_lo, rreg_lo); break;
1733 case lir_mul: __ mul (dest->as_register_lo(), lreg_lo, rreg_lo); break;
1734 case lir_div: __ corrected_idivq(dest->as_register_lo(), lreg_lo, rreg_lo, false, rscratch1); break;
1735 case lir_rem: __ corrected_idivq(dest->as_register_lo(), lreg_lo, rreg_lo, true, rscratch1); break;
1736 default:
1737 ShouldNotReachHere();
1738 }
1739
1740 } else if (right->is_constant()) {
1741 jlong c = right->as_constant_ptr()->as_jlong();
1742 Register dreg = as_reg(dest);
1743 switch (code) {
1744 case lir_add:
1745 case lir_sub:
1746 if (c == 0 && dreg == lreg_lo) {
1747 COMMENT("effective nop elided");
1748 return;
1749 }
1750 code == lir_add ? __ add(dreg, lreg_lo, c) : __ sub(dreg, lreg_lo, c);
1751 break;
1752 case lir_div:
1753 assert(c > 0 && is_power_of_2_long(c), "divisor must be power-of-2 constant");
1754 if (c == 1) {
1755 // move lreg_lo to dreg if divisor is 1
1756 __ mov(dreg, lreg_lo);
1757 } else {
1758 unsigned int shift = exact_log2_long(c);
1759 // use rscratch1 as intermediate result register
1760 __ asr(rscratch1, lreg_lo, 63);
1761 __ add(rscratch1, lreg_lo, rscratch1, Assembler::LSR, 64 - shift);
1762 __ asr(dreg, rscratch1, shift);
1763 }
1764 break;
1765 case lir_rem:
1766 assert(c > 0 && is_power_of_2_long(c), "divisor must be power-of-2 constant");
1767 if (c == 1) {
1768 // move 0 to dreg if divisor is 1
1769 __ mov(dreg, zr);
1770 } else {
1771 // use rscratch1 as intermediate result register
1772 __ negs(rscratch1, lreg_lo);
1773 __ andr(dreg, lreg_lo, c - 1);
1774 __ andr(rscratch1, rscratch1, c - 1);
1775 __ csneg(dreg, dreg, rscratch1, Assembler::MI);
1776 }
1777 break;
1778 default:
1779 ShouldNotReachHere();
1780 }
1781 } else {
1782 ShouldNotReachHere();
1783 }
1784 } else if (left->is_single_fpu()) {
1785 assert(right->is_single_fpu(), "right hand side of float arithmetics needs to be float register");
1786 switch (code) {
1787 case lir_add: __ fadds (dest->as_float_reg(), left->as_float_reg(), right->as_float_reg()); break;
1788 case lir_sub: __ fsubs (dest->as_float_reg(), left->as_float_reg(), right->as_float_reg()); break;
1789 case lir_mul: __ fmuls (dest->as_float_reg(), left->as_float_reg(), right->as_float_reg()); break;
1790 case lir_div: __ fdivs (dest->as_float_reg(), left->as_float_reg(), right->as_float_reg()); break;
1791 default:
1792 ShouldNotReachHere();
1793 }
1794 } else if (left->is_double_fpu()) {
1795 if (right->is_double_fpu()) {
1796 // cpu register - cpu register
1797 switch (code) {
1798 case lir_add: __ faddd (dest->as_double_reg(), left->as_double_reg(), right->as_double_reg()); break;
1799 case lir_sub: __ fsubd (dest->as_double_reg(), left->as_double_reg(), right->as_double_reg()); break;
1800 case lir_mul: __ fmuld (dest->as_double_reg(), left->as_double_reg(), right->as_double_reg()); break;
1801 case lir_div: __ fdivd (dest->as_double_reg(), left->as_double_reg(), right->as_double_reg()); break;
1802 default:
1803 ShouldNotReachHere();
1804 }
1805 } else {
1806 if (right->is_constant()) {
1807 ShouldNotReachHere();
1808 }
1809 ShouldNotReachHere();
1810 }
1811 } else if (left->is_single_stack() || left->is_address()) {
1812 assert(left == dest, "left and dest must be equal");
1813 ShouldNotReachHere();
1814 } else {
1815 ShouldNotReachHere();
1816 }
1817 }
1818
1819 void LIR_Assembler::arith_fpu_implementation(LIR_Code code, int left_index, int right_index, int dest_index, bool pop_fpu_stack) { Unimplemented(); }
1820
1821
1822 void LIR_Assembler::intrinsic_op(LIR_Code code, LIR_Opr value, LIR_Opr unused, LIR_Opr dest, LIR_Op* op) {
1823 switch(code) {
1824 case lir_abs : __ fabsd(dest->as_double_reg(), value->as_double_reg()); break;
1825 case lir_sqrt: __ fsqrtd(dest->as_double_reg(), value->as_double_reg()); break;
1826 default : ShouldNotReachHere();
1827 }
1828 }
1829
1830 void LIR_Assembler::logic_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst) {
1831
1832 assert(left->is_single_cpu() || left->is_double_cpu(), "expect single or double register");
1833 Register Rleft = left->is_single_cpu() ? left->as_register() :
1834 left->as_register_lo();
1835 if (dst->is_single_cpu()) {
1836 Register Rdst = dst->as_register();
1837 if (right->is_constant()) {
1838 switch (code) {
1839 case lir_logic_and: __ andw (Rdst, Rleft, right->as_jint()); break;
1840 case lir_logic_or: __ orrw (Rdst, Rleft, right->as_jint()); break;
1841 case lir_logic_xor: __ eorw (Rdst, Rleft, right->as_jint()); break;
1842 default: ShouldNotReachHere(); break;
1843 }
1844 } else {
1845 Register Rright = right->is_single_cpu() ? right->as_register() :
1846 right->as_register_lo();
1847 switch (code) {
1848 case lir_logic_and: __ andw (Rdst, Rleft, Rright); break;
1849 case lir_logic_or: __ orrw (Rdst, Rleft, Rright); break;
1850 case lir_logic_xor: __ eorw (Rdst, Rleft, Rright); break;
1851 default: ShouldNotReachHere(); break;
1852 }
1853 }
1854 } else {
1855 Register Rdst = dst->as_register_lo();
1856 if (right->is_constant()) {
1857 switch (code) {
1858 case lir_logic_and: __ andr (Rdst, Rleft, right->as_jlong()); break;
1859 case lir_logic_or: __ orr (Rdst, Rleft, right->as_jlong()); break;
1860 case lir_logic_xor: __ eor (Rdst, Rleft, right->as_jlong()); break;
1861 default: ShouldNotReachHere(); break;
1862 }
1863 } else {
1864 Register Rright = right->is_single_cpu() ? right->as_register() :
1865 right->as_register_lo();
1866 switch (code) {
1867 case lir_logic_and: __ andr (Rdst, Rleft, Rright); break;
1868 case lir_logic_or: __ orr (Rdst, Rleft, Rright); break;
1869 case lir_logic_xor: __ eor (Rdst, Rleft, Rright); break;
1870 default: ShouldNotReachHere(); break;
1871 }
1872 }
1873 }
1874 }
1875
1876
1877
1878 void LIR_Assembler::arithmetic_idiv(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr illegal, LIR_Opr result, CodeEmitInfo* info) {
1879
1880 // opcode check
1881 assert((code == lir_idiv) || (code == lir_irem), "opcode must be idiv or irem");
1882 bool is_irem = (code == lir_irem);
1883
1884 // operand check
1885 assert(left->is_single_cpu(), "left must be register");
1886 assert(right->is_single_cpu() || right->is_constant(), "right must be register or constant");
1887 assert(result->is_single_cpu(), "result must be register");
1888 Register lreg = left->as_register();
1889 Register dreg = result->as_register();
1890
1891 // power-of-2 constant check and codegen
1892 if (right->is_constant()) {
1893 int c = right->as_constant_ptr()->as_jint();
1894 assert(c > 0 && is_power_of_2(c), "divisor must be power-of-2 constant");
1895 if (is_irem) {
1896 if (c == 1) {
1897 // move 0 to dreg if divisor is 1
1898 __ movw(dreg, zr);
1899 } else {
1900 // use rscratch1 as intermediate result register
1901 __ negsw(rscratch1, lreg);
1902 __ andw(dreg, lreg, c - 1);
1903 __ andw(rscratch1, rscratch1, c - 1);
1904 __ csnegw(dreg, dreg, rscratch1, Assembler::MI);
1905 }
1906 } else {
1907 if (c == 1) {
1908 // move lreg to dreg if divisor is 1
1909 __ movw(dreg, lreg);
1910 } else {
1911 unsigned int shift = exact_log2(c);
1912 // use rscratch1 as intermediate result register
1913 __ asrw(rscratch1, lreg, 31);
1914 __ addw(rscratch1, lreg, rscratch1, Assembler::LSR, 32 - shift);
1915 __ asrw(dreg, rscratch1, shift);
1916 }
1917 }
1918 } else {
1919 Register rreg = right->as_register();
1920 __ corrected_idivl(dreg, lreg, rreg, is_irem, rscratch1);
1921 }
1922 }
1923
1924
1925 void LIR_Assembler::comp_op(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Op2* op) {
1926 if (opr1->is_constant() && opr2->is_single_cpu()) {
1927 // tableswitch
1928 Register reg = as_reg(opr2);
1929 struct tableswitch &table = switches[opr1->as_constant_ptr()->as_jint()];
1930 __ tableswitch(reg, table._first_key, table._last_key, table._branches, table._after);
1931 } else if (opr1->is_single_cpu() || opr1->is_double_cpu()) {
1932 Register reg1 = as_reg(opr1);
1933 if (opr2->is_single_cpu()) {
1934 // cpu register - cpu register
1935 Register reg2 = opr2->as_register();
1936 if (opr1->type() == T_OBJECT || opr1->type() == T_ARRAY || opr1->type() == T_VALUETYPE) {
1937 __ cmpoop(reg1, reg2);
1938 } else {
1939 assert(opr2->type() != T_OBJECT && opr2->type() != T_ARRAY && opr2->type() != T_VALUETYPE, "cmp int, oop?");
1940 __ cmpw(reg1, reg2);
1941 }
1942 return;
1943 }
1944 if (opr2->is_double_cpu()) {
1945 // cpu register - cpu register
1946 Register reg2 = opr2->as_register_lo();
1947 __ cmp(reg1, reg2);
1948 return;
1949 }
1950
1951 if (opr2->is_constant()) {
1952 bool is_32bit = false; // width of register operand
1953 jlong imm;
1954
1955 switch(opr2->type()) {
1956 case T_INT:
1957 imm = opr2->as_constant_ptr()->as_jint();
1958 is_32bit = true;
1959 break;
1960 case T_LONG:
1961 imm = opr2->as_constant_ptr()->as_jlong();
1962 break;
1963 case T_ADDRESS:
1964 imm = opr2->as_constant_ptr()->as_jint();
1965 break;
1966 case T_VALUETYPE:
1967 case T_OBJECT:
1968 case T_ARRAY:
1969 jobject2reg(opr2->as_constant_ptr()->as_jobject(), rscratch1);
1970 __ cmpoop(reg1, rscratch1);
1971 return;
1972 default:
1973 ShouldNotReachHere();
1974 imm = 0; // unreachable
1975 break;
1976 }
1977
1978 if (Assembler::operand_valid_for_add_sub_immediate(imm)) {
1979 if (is_32bit)
1980 __ cmpw(reg1, imm);
1981 else
1982 __ subs(zr, reg1, imm);
1983 return;
1984 } else {
1985 __ mov(rscratch1, imm);
1986 if (is_32bit)
1987 __ cmpw(reg1, rscratch1);
1988 else
1989 __ cmp(reg1, rscratch1);
1990 return;
1991 }
1992 } else
1993 ShouldNotReachHere();
1994 } else if (opr1->is_single_fpu()) {
1995 FloatRegister reg1 = opr1->as_float_reg();
1996 assert(opr2->is_single_fpu(), "expect single float register");
1997 FloatRegister reg2 = opr2->as_float_reg();
1998 __ fcmps(reg1, reg2);
1999 } else if (opr1->is_double_fpu()) {
2000 FloatRegister reg1 = opr1->as_double_reg();
2001 assert(opr2->is_double_fpu(), "expect double float register");
2002 FloatRegister reg2 = opr2->as_double_reg();
2003 __ fcmpd(reg1, reg2);
2004 } else {
2005 ShouldNotReachHere();
2006 }
2007 }
2008
2009 void LIR_Assembler::comp_fl2i(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst, LIR_Op2* op){
2010 if (code == lir_cmp_fd2i || code == lir_ucmp_fd2i) {
2011 bool is_unordered_less = (code == lir_ucmp_fd2i);
2012 if (left->is_single_fpu()) {
2013 __ float_cmp(true, is_unordered_less ? -1 : 1, left->as_float_reg(), right->as_float_reg(), dst->as_register());
2014 } else if (left->is_double_fpu()) {
2015 __ float_cmp(false, is_unordered_less ? -1 : 1, left->as_double_reg(), right->as_double_reg(), dst->as_register());
2016 } else {
2017 ShouldNotReachHere();
2018 }
2019 } else if (code == lir_cmp_l2i) {
2020 Label done;
2021 __ cmp(left->as_register_lo(), right->as_register_lo());
2022 __ mov(dst->as_register(), (u_int64_t)-1L);
2023 __ br(Assembler::LT, done);
2024 __ csinc(dst->as_register(), zr, zr, Assembler::EQ);
2025 __ bind(done);
2026 } else {
2027 ShouldNotReachHere();
2028 }
2029 }
2030
2031
2032 void LIR_Assembler::align_call(LIR_Code code) { }
2033
2034
2035 void LIR_Assembler::call(LIR_OpJavaCall* op, relocInfo::relocType rtype) {
2036 address call = __ trampoline_call(Address(op->addr(), rtype));
2037 if (call == NULL) {
2038 bailout("trampoline stub overflow");
2039 return;
2040 }
2041 add_call_info(code_offset(), op->info());
2042 }
2043
2044
2045 void LIR_Assembler::ic_call(LIR_OpJavaCall* op) {
2046 address call = __ ic_call(op->addr());
2047 if (call == NULL) {
2048 bailout("trampoline stub overflow");
2049 return;
2050 }
2051 add_call_info(code_offset(), op->info());
2052 }
2053
2054
2055 /* Currently, vtable-dispatch is only enabled for sparc platforms */
2056 void LIR_Assembler::vtable_call(LIR_OpJavaCall* op) {
2057 ShouldNotReachHere();
2058 }
2059
2060
2061 void LIR_Assembler::emit_static_call_stub() {
2062 address call_pc = __ pc();
2063 address stub = __ start_a_stub(call_stub_size());
2064 if (stub == NULL) {
2065 bailout("static call stub overflow");
2066 return;
2067 }
2068
2069 int start = __ offset();
2070
2071 __ relocate(static_stub_Relocation::spec(call_pc));
2072 __ mov_metadata(rmethod, (Metadata*)NULL);
2073 __ movptr(rscratch1, 0);
2074 __ br(rscratch1);
2075
2076 assert(__ offset() - start <= call_stub_size(), "stub too big");
2077 __ end_a_stub();
2078 }
2079
2080
2081 void LIR_Assembler::throw_op(LIR_Opr exceptionPC, LIR_Opr exceptionOop, CodeEmitInfo* info) {
2082 assert(exceptionOop->as_register() == r0, "must match");
2083 assert(exceptionPC->as_register() == r3, "must match");
2084
2085 // exception object is not added to oop map by LinearScan
2086 // (LinearScan assumes that no oops are in fixed registers)
2087 info->add_register_oop(exceptionOop);
2088 Runtime1::StubID unwind_id;
2089
2090 // get current pc information
2091 // pc is only needed if the method has an exception handler, the unwind code does not need it.
2092 int pc_for_athrow_offset = __ offset();
2093 InternalAddress pc_for_athrow(__ pc());
2094 __ adr(exceptionPC->as_register(), pc_for_athrow);
2095 add_call_info(pc_for_athrow_offset, info); // for exception handler
2096
2097 __ verify_not_null_oop(r0);
2098 // search an exception handler (r0: exception oop, r3: throwing pc)
2099 if (compilation()->has_fpu_code()) {
2100 unwind_id = Runtime1::handle_exception_id;
2101 } else {
2102 unwind_id = Runtime1::handle_exception_nofpu_id;
2103 }
2104 __ far_call(RuntimeAddress(Runtime1::entry_for(unwind_id)));
2105
2106 // FIXME: enough room for two byte trap ????
2107 __ nop();
2108 }
2109
2110
2111 void LIR_Assembler::unwind_op(LIR_Opr exceptionOop) {
2112 assert(exceptionOop->as_register() == r0, "must match");
2113
2114 __ b(_unwind_handler_entry);
2115 }
2116
2117
2118 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, LIR_Opr count, LIR_Opr dest, LIR_Opr tmp) {
2119 Register lreg = left->is_single_cpu() ? left->as_register() : left->as_register_lo();
2120 Register dreg = dest->is_single_cpu() ? dest->as_register() : dest->as_register_lo();
2121
2122 switch (left->type()) {
2123 case T_INT: {
2124 switch (code) {
2125 case lir_shl: __ lslvw (dreg, lreg, count->as_register()); break;
2126 case lir_shr: __ asrvw (dreg, lreg, count->as_register()); break;
2127 case lir_ushr: __ lsrvw (dreg, lreg, count->as_register()); break;
2128 default:
2129 ShouldNotReachHere();
2130 break;
2131 }
2132 break;
2133 case T_LONG:
2134 case T_VALUETYPE:
2135 case T_ADDRESS:
2136 case T_OBJECT:
2137 switch (code) {
2138 case lir_shl: __ lslv (dreg, lreg, count->as_register()); break;
2139 case lir_shr: __ asrv (dreg, lreg, count->as_register()); break;
2140 case lir_ushr: __ lsrv (dreg, lreg, count->as_register()); break;
2141 default:
2142 ShouldNotReachHere();
2143 break;
2144 }
2145 break;
2146 default:
2147 ShouldNotReachHere();
2148 break;
2149 }
2150 }
2151 }
2152
2153
2154 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, jint count, LIR_Opr dest) {
2155 Register dreg = dest->is_single_cpu() ? dest->as_register() : dest->as_register_lo();
2156 Register lreg = left->is_single_cpu() ? left->as_register() : left->as_register_lo();
2157
2158 switch (left->type()) {
2159 case T_INT: {
2160 switch (code) {
2161 case lir_shl: __ lslw (dreg, lreg, count); break;
2162 case lir_shr: __ asrw (dreg, lreg, count); break;
2163 case lir_ushr: __ lsrw (dreg, lreg, count); break;
2164 default:
2165 ShouldNotReachHere();
2166 break;
2167 }
2168 break;
2169 case T_LONG:
2170 case T_ADDRESS:
2171 case T_VALUETYPE:
2172 case T_OBJECT:
2173 switch (code) {
2174 case lir_shl: __ lsl (dreg, lreg, count); break;
2175 case lir_shr: __ asr (dreg, lreg, count); break;
2176 case lir_ushr: __ lsr (dreg, lreg, count); break;
2177 default:
2178 ShouldNotReachHere();
2179 break;
2180 }
2181 break;
2182 default:
2183 ShouldNotReachHere();
2184 break;
2185 }
2186 }
2187 }
2188
2189
2190 void LIR_Assembler::store_parameter(Register r, int offset_from_rsp_in_words) {
2191 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
2192 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
2193 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
2194 __ str (r, Address(sp, offset_from_rsp_in_bytes));
2195 }
2196
2197
2198 void LIR_Assembler::store_parameter(jint c, int offset_from_rsp_in_words) {
2199 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
2200 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
2201 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
2202 __ mov (rscratch1, c);
2203 __ str (rscratch1, Address(sp, offset_from_rsp_in_bytes));
2204 }
2205
2206
2207 void LIR_Assembler::store_parameter(jobject o, int offset_from_rsp_in_words) {
2208 ShouldNotReachHere();
2209 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
2210 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
2211 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
2212 __ lea(rscratch1, __ constant_oop_address(o));
2213 __ str(rscratch1, Address(sp, offset_from_rsp_in_bytes));
2214 }
2215
2216
2217 // This code replaces a call to arraycopy; no exception may
2218 // be thrown in this code, they must be thrown in the System.arraycopy
2219 // activation frame; we could save some checks if this would not be the case
2220 void LIR_Assembler::emit_arraycopy(LIR_OpArrayCopy* op) {
2221 ciArrayKlass* default_type = op->expected_type();
2222 Register src = op->src()->as_register();
2223 Register dst = op->dst()->as_register();
2224 Register src_pos = op->src_pos()->as_register();
2225 Register dst_pos = op->dst_pos()->as_register();
2226 Register length = op->length()->as_register();
2227 Register tmp = op->tmp()->as_register();
2228
2229 __ resolve(ACCESS_READ, src);
2230 __ resolve(ACCESS_WRITE, dst);
2231
2232 CodeStub* stub = op->stub();
2233 int flags = op->flags();
2234 BasicType basic_type = default_type != NULL ? default_type->element_type()->basic_type() : T_ILLEGAL;
2235 if (basic_type == T_ARRAY) basic_type = T_OBJECT;
2236
2237 // if we don't know anything, just go through the generic arraycopy
2238 if (default_type == NULL // || basic_type == T_OBJECT
2239 ) {
2240 Label done;
2241 assert(src == r1 && src_pos == r2, "mismatch in calling convention");
2242
2243 // Save the arguments in case the generic arraycopy fails and we
2244 // have to fall back to the JNI stub
2245 __ stp(dst, dst_pos, Address(sp, 0*BytesPerWord));
2246 __ stp(length, src_pos, Address(sp, 2*BytesPerWord));
2247 __ str(src, Address(sp, 4*BytesPerWord));
2248
2249 address copyfunc_addr = StubRoutines::generic_arraycopy();
2250 assert(copyfunc_addr != NULL, "generic arraycopy stub required");
2251
2252 // The arguments are in java calling convention so we shift them
2253 // to C convention
2254 assert_different_registers(c_rarg0, j_rarg1, j_rarg2, j_rarg3, j_rarg4);
2255 __ mov(c_rarg0, j_rarg0);
2256 assert_different_registers(c_rarg1, j_rarg2, j_rarg3, j_rarg4);
2257 __ mov(c_rarg1, j_rarg1);
2258 assert_different_registers(c_rarg2, j_rarg3, j_rarg4);
2259 __ mov(c_rarg2, j_rarg2);
2260 assert_different_registers(c_rarg3, j_rarg4);
2261 __ mov(c_rarg3, j_rarg3);
2262 __ mov(c_rarg4, j_rarg4);
2263 #ifndef PRODUCT
2264 if (PrintC1Statistics) {
2265 __ incrementw(ExternalAddress((address)&Runtime1::_generic_arraycopystub_cnt));
2266 }
2267 #endif
2268 __ far_call(RuntimeAddress(copyfunc_addr));
2269
2270 __ cbz(r0, *stub->continuation());
2271
2272 // Reload values from the stack so they are where the stub
2273 // expects them.
2274 __ ldp(dst, dst_pos, Address(sp, 0*BytesPerWord));
2275 __ ldp(length, src_pos, Address(sp, 2*BytesPerWord));
2276 __ ldr(src, Address(sp, 4*BytesPerWord));
2277
2278 // r0 is -1^K where K == partial copied count
2279 __ eonw(rscratch1, r0, 0);
2280 // adjust length down and src/end pos up by partial copied count
2281 __ subw(length, length, rscratch1);
2282 __ addw(src_pos, src_pos, rscratch1);
2283 __ addw(dst_pos, dst_pos, rscratch1);
2284 __ b(*stub->entry());
2285
2286 __ bind(*stub->continuation());
2287 return;
2288 }
2289
2290 assert(default_type != NULL && default_type->is_array_klass() && default_type->is_loaded(), "must be true at this point");
2291
2292 int elem_size = type2aelembytes(basic_type);
2293 int shift_amount;
2294 int scale = exact_log2(elem_size);
2295
2296 Address src_length_addr = Address(src, arrayOopDesc::length_offset_in_bytes());
2297 Address dst_length_addr = Address(dst, arrayOopDesc::length_offset_in_bytes());
2298 Address src_klass_addr = Address(src, oopDesc::klass_offset_in_bytes());
2299 Address dst_klass_addr = Address(dst, oopDesc::klass_offset_in_bytes());
2300
2301 // test for NULL
2302 if (flags & LIR_OpArrayCopy::src_null_check) {
2303 __ cbz(src, *stub->entry());
2304 }
2305 if (flags & LIR_OpArrayCopy::dst_null_check) {
2306 __ cbz(dst, *stub->entry());
2307 }
2308
2309 // If the compiler was not able to prove that exact type of the source or the destination
2310 // of the arraycopy is an array type, check at runtime if the source or the destination is
2311 // an instance type.
2312 if (flags & LIR_OpArrayCopy::type_check) {
2313 if (!(flags & LIR_OpArrayCopy::LIR_OpArrayCopy::dst_objarray)) {
2314 __ load_klass(tmp, dst);
2315 __ ldrw(rscratch1, Address(tmp, in_bytes(Klass::layout_helper_offset())));
2316 __ cmpw(rscratch1, Klass::_lh_neutral_value);
2317 __ br(Assembler::GE, *stub->entry());
2318 }
2319
2320 if (!(flags & LIR_OpArrayCopy::LIR_OpArrayCopy::src_objarray)) {
2321 __ load_klass(tmp, src);
2322 __ ldrw(rscratch1, Address(tmp, in_bytes(Klass::layout_helper_offset())));
2323 __ cmpw(rscratch1, Klass::_lh_neutral_value);
2324 __ br(Assembler::GE, *stub->entry());
2325 }
2326 }
2327
2328 // check if negative
2329 if (flags & LIR_OpArrayCopy::src_pos_positive_check) {
2330 __ cmpw(src_pos, 0);
2331 __ br(Assembler::LT, *stub->entry());
2332 }
2333 if (flags & LIR_OpArrayCopy::dst_pos_positive_check) {
2334 __ cmpw(dst_pos, 0);
2335 __ br(Assembler::LT, *stub->entry());
2336 }
2337
2338 if (flags & LIR_OpArrayCopy::length_positive_check) {
2339 __ cmpw(length, 0);
2340 __ br(Assembler::LT, *stub->entry());
2341 }
2342
2343 if (flags & LIR_OpArrayCopy::src_range_check) {
2344 __ addw(tmp, src_pos, length);
2345 __ ldrw(rscratch1, src_length_addr);
2346 __ cmpw(tmp, rscratch1);
2347 __ br(Assembler::HI, *stub->entry());
2348 }
2349 if (flags & LIR_OpArrayCopy::dst_range_check) {
2350 __ addw(tmp, dst_pos, length);
2351 __ ldrw(rscratch1, dst_length_addr);
2352 __ cmpw(tmp, rscratch1);
2353 __ br(Assembler::HI, *stub->entry());
2354 }
2355
2356 if (flags & LIR_OpArrayCopy::type_check) {
2357 // We don't know the array types are compatible
2358 if (basic_type != T_OBJECT) {
2359 // Simple test for basic type arrays
2360 if (UseCompressedClassPointers) {
2361 __ ldrw(tmp, src_klass_addr);
2362 __ ldrw(rscratch1, dst_klass_addr);
2363 __ cmpw(tmp, rscratch1);
2364 } else {
2365 __ ldr(tmp, src_klass_addr);
2366 __ ldr(rscratch1, dst_klass_addr);
2367 __ cmp(tmp, rscratch1);
2368 }
2369 __ br(Assembler::NE, *stub->entry());
2370 } else {
2371 // For object arrays, if src is a sub class of dst then we can
2372 // safely do the copy.
2373 Label cont, slow;
2374
2375 #define PUSH(r1, r2) \
2376 stp(r1, r2, __ pre(sp, -2 * wordSize));
2377
2378 #define POP(r1, r2) \
2379 ldp(r1, r2, __ post(sp, 2 * wordSize));
2380
2381 __ PUSH(src, dst);
2382
2383 __ load_klass(src, src);
2384 __ load_klass(dst, dst);
2385
2386 __ check_klass_subtype_fast_path(src, dst, tmp, &cont, &slow, NULL);
2387
2388 __ PUSH(src, dst);
2389 __ far_call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id)));
2390 __ POP(src, dst);
2391
2392 __ cbnz(src, cont);
2393
2394 __ bind(slow);
2395 __ POP(src, dst);
2396
2397 address copyfunc_addr = StubRoutines::checkcast_arraycopy();
2398 if (copyfunc_addr != NULL) { // use stub if available
2399 // src is not a sub class of dst so we have to do a
2400 // per-element check.
2401
2402 int mask = LIR_OpArrayCopy::src_objarray|LIR_OpArrayCopy::dst_objarray;
2403 if ((flags & mask) != mask) {
2404 // Check that at least both of them object arrays.
2405 assert(flags & mask, "one of the two should be known to be an object array");
2406
2407 if (!(flags & LIR_OpArrayCopy::src_objarray)) {
2408 __ load_klass(tmp, src);
2409 } else if (!(flags & LIR_OpArrayCopy::dst_objarray)) {
2410 __ load_klass(tmp, dst);
2411 }
2412 int lh_offset = in_bytes(Klass::layout_helper_offset());
2413 Address klass_lh_addr(tmp, lh_offset);
2414 jint objArray_lh = Klass::array_layout_helper(T_OBJECT);
2415 __ ldrw(rscratch1, klass_lh_addr);
2416 __ mov(rscratch2, objArray_lh);
2417 __ eorw(rscratch1, rscratch1, rscratch2);
2418 __ cbnzw(rscratch1, *stub->entry());
2419 }
2420
2421 // Spill because stubs can use any register they like and it's
2422 // easier to restore just those that we care about.
2423 __ stp(dst, dst_pos, Address(sp, 0*BytesPerWord));
2424 __ stp(length, src_pos, Address(sp, 2*BytesPerWord));
2425 __ str(src, Address(sp, 4*BytesPerWord));
2426
2427 __ lea(c_rarg0, Address(src, src_pos, Address::uxtw(scale)));
2428 __ add(c_rarg0, c_rarg0, arrayOopDesc::base_offset_in_bytes(basic_type));
2429 assert_different_registers(c_rarg0, dst, dst_pos, length);
2430 __ lea(c_rarg1, Address(dst, dst_pos, Address::uxtw(scale)));
2431 __ add(c_rarg1, c_rarg1, arrayOopDesc::base_offset_in_bytes(basic_type));
2432 assert_different_registers(c_rarg1, dst, length);
2433 __ uxtw(c_rarg2, length);
2434 assert_different_registers(c_rarg2, dst);
2435
2436 __ load_klass(c_rarg4, dst);
2437 __ ldr(c_rarg4, Address(c_rarg4, ObjArrayKlass::element_klass_offset()));
2438 __ ldrw(c_rarg3, Address(c_rarg4, Klass::super_check_offset_offset()));
2439 __ far_call(RuntimeAddress(copyfunc_addr));
2440
2441 #ifndef PRODUCT
2442 if (PrintC1Statistics) {
2443 Label failed;
2444 __ cbnz(r0, failed);
2445 __ incrementw(ExternalAddress((address)&Runtime1::_arraycopy_checkcast_cnt));
2446 __ bind(failed);
2447 }
2448 #endif
2449
2450 __ cbz(r0, *stub->continuation());
2451
2452 #ifndef PRODUCT
2453 if (PrintC1Statistics) {
2454 __ incrementw(ExternalAddress((address)&Runtime1::_arraycopy_checkcast_attempt_cnt));
2455 }
2456 #endif
2457 assert_different_registers(dst, dst_pos, length, src_pos, src, r0, rscratch1);
2458
2459 // Restore previously spilled arguments
2460 __ ldp(dst, dst_pos, Address(sp, 0*BytesPerWord));
2461 __ ldp(length, src_pos, Address(sp, 2*BytesPerWord));
2462 __ ldr(src, Address(sp, 4*BytesPerWord));
2463
2464 // return value is -1^K where K is partial copied count
2465 __ eonw(rscratch1, r0, zr);
2466 // adjust length down and src/end pos up by partial copied count
2467 __ subw(length, length, rscratch1);
2468 __ addw(src_pos, src_pos, rscratch1);
2469 __ addw(dst_pos, dst_pos, rscratch1);
2470 }
2471
2472 __ b(*stub->entry());
2473
2474 __ bind(cont);
2475 __ POP(src, dst);
2476 }
2477 }
2478
2479 #ifdef ASSERT
2480 if (basic_type != T_OBJECT || !(flags & LIR_OpArrayCopy::type_check)) {
2481 // Sanity check the known type with the incoming class. For the
2482 // primitive case the types must match exactly with src.klass and
2483 // dst.klass each exactly matching the default type. For the
2484 // object array case, if no type check is needed then either the
2485 // dst type is exactly the expected type and the src type is a
2486 // subtype which we can't check or src is the same array as dst
2487 // but not necessarily exactly of type default_type.
2488 Label known_ok, halt;
2489 __ mov_metadata(tmp, default_type->constant_encoding());
2490 if (UseCompressedClassPointers) {
2491 __ encode_klass_not_null(tmp);
2492 }
2493
2494 if (basic_type != T_OBJECT) {
2495
2496 if (UseCompressedClassPointers) {
2497 __ ldrw(rscratch1, dst_klass_addr);
2498 __ cmpw(tmp, rscratch1);
2499 } else {
2500 __ ldr(rscratch1, dst_klass_addr);
2501 __ cmp(tmp, rscratch1);
2502 }
2503 __ br(Assembler::NE, halt);
2504 if (UseCompressedClassPointers) {
2505 __ ldrw(rscratch1, src_klass_addr);
2506 __ cmpw(tmp, rscratch1);
2507 } else {
2508 __ ldr(rscratch1, src_klass_addr);
2509 __ cmp(tmp, rscratch1);
2510 }
2511 __ br(Assembler::EQ, known_ok);
2512 } else {
2513 if (UseCompressedClassPointers) {
2514 __ ldrw(rscratch1, dst_klass_addr);
2515 __ cmpw(tmp, rscratch1);
2516 } else {
2517 __ ldr(rscratch1, dst_klass_addr);
2518 __ cmp(tmp, rscratch1);
2519 }
2520 __ br(Assembler::EQ, known_ok);
2521 __ cmp(src, dst);
2522 __ br(Assembler::EQ, known_ok);
2523 }
2524 __ bind(halt);
2525 __ stop("incorrect type information in arraycopy");
2526 __ bind(known_ok);
2527 }
2528 #endif
2529
2530 #ifndef PRODUCT
2531 if (PrintC1Statistics) {
2532 __ incrementw(ExternalAddress(Runtime1::arraycopy_count_address(basic_type)));
2533 }
2534 #endif
2535
2536 __ lea(c_rarg0, Address(src, src_pos, Address::uxtw(scale)));
2537 __ add(c_rarg0, c_rarg0, arrayOopDesc::base_offset_in_bytes(basic_type));
2538 assert_different_registers(c_rarg0, dst, dst_pos, length);
2539 __ lea(c_rarg1, Address(dst, dst_pos, Address::uxtw(scale)));
2540 __ add(c_rarg1, c_rarg1, arrayOopDesc::base_offset_in_bytes(basic_type));
2541 assert_different_registers(c_rarg1, dst, length);
2542 __ uxtw(c_rarg2, length);
2543 assert_different_registers(c_rarg2, dst);
2544
2545 bool disjoint = (flags & LIR_OpArrayCopy::overlapping) == 0;
2546 bool aligned = (flags & LIR_OpArrayCopy::unaligned) == 0;
2547 const char *name;
2548 address entry = StubRoutines::select_arraycopy_function(basic_type, aligned, disjoint, name, false);
2549
2550 CodeBlob *cb = CodeCache::find_blob(entry);
2551 if (cb) {
2552 __ far_call(RuntimeAddress(entry));
2553 } else {
2554 __ call_VM_leaf(entry, 3);
2555 }
2556
2557 __ bind(*stub->continuation());
2558 }
2559
2560
2561
2562
2563 void LIR_Assembler::emit_lock(LIR_OpLock* op) {
2564 Register obj = op->obj_opr()->as_register(); // may not be an oop
2565 Register hdr = op->hdr_opr()->as_register();
2566 Register lock = op->lock_opr()->as_register();
2567 if (!UseFastLocking) {
2568 __ b(*op->stub()->entry());
2569 } else if (op->code() == lir_lock) {
2570 Register scratch = noreg;
2571 if (UseBiasedLocking) {
2572 scratch = op->scratch_opr()->as_register();
2573 }
2574 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
2575 __ resolve(ACCESS_READ | ACCESS_WRITE, obj);
2576 // add debug info for NullPointerException only if one is possible
2577 int null_check_offset = __ lock_object(hdr, obj, lock, scratch, *op->stub()->entry());
2578 if (op->info() != NULL) {
2579 add_debug_info_for_null_check(null_check_offset, op->info());
2580 }
2581 // done
2582 } else if (op->code() == lir_unlock) {
2583 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
2584 __ unlock_object(hdr, obj, lock, *op->stub()->entry());
2585 } else {
2586 Unimplemented();
2587 }
2588 __ bind(*op->stub()->continuation());
2589 }
2590
2591
2592 void LIR_Assembler::emit_profile_call(LIR_OpProfileCall* op) {
2593 ciMethod* method = op->profiled_method();
2594 int bci = op->profiled_bci();
2595 ciMethod* callee = op->profiled_callee();
2596
2597 // Update counter for all call types
2598 ciMethodData* md = method->method_data_or_null();
2599 assert(md != NULL, "Sanity");
2600 ciProfileData* data = md->bci_to_data(bci);
2601 assert(data != NULL && data->is_CounterData(), "need CounterData for calls");
2602 assert(op->mdo()->is_single_cpu(), "mdo must be allocated");
2603 Register mdo = op->mdo()->as_register();
2604 __ mov_metadata(mdo, md->constant_encoding());
2605 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()));
2606 // Perform additional virtual call profiling for invokevirtual and
2607 // invokeinterface bytecodes
2608 if (op->should_profile_receiver_type()) {
2609 assert(op->recv()->is_single_cpu(), "recv must be allocated");
2610 Register recv = op->recv()->as_register();
2611 assert_different_registers(mdo, recv);
2612 assert(data->is_VirtualCallData(), "need VirtualCallData for virtual calls");
2613 ciKlass* known_klass = op->known_holder();
2614 if (C1OptimizeVirtualCallProfiling && known_klass != NULL) {
2615 // We know the type that will be seen at this call site; we can
2616 // statically update the MethodData* rather than needing to do
2617 // dynamic tests on the receiver type
2618
2619 // NOTE: we should probably put a lock around this search to
2620 // avoid collisions by concurrent compilations
2621 ciVirtualCallData* vc_data = (ciVirtualCallData*) data;
2622 uint i;
2623 for (i = 0; i < VirtualCallData::row_limit(); i++) {
2624 ciKlass* receiver = vc_data->receiver(i);
2625 if (known_klass->equals(receiver)) {
2626 Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)));
2627 __ addptr(data_addr, DataLayout::counter_increment);
2628 return;
2629 }
2630 }
2631
2632 // Receiver type not found in profile data; select an empty slot
2633
2634 // Note that this is less efficient than it should be because it
2635 // always does a write to the receiver part of the
2636 // VirtualCallData rather than just the first time
2637 for (i = 0; i < VirtualCallData::row_limit(); i++) {
2638 ciKlass* receiver = vc_data->receiver(i);
2639 if (receiver == NULL) {
2640 Address recv_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_offset(i)));
2641 __ mov_metadata(rscratch1, known_klass->constant_encoding());
2642 __ lea(rscratch2, recv_addr);
2643 __ str(rscratch1, Address(rscratch2));
2644 Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)));
2645 __ addptr(data_addr, DataLayout::counter_increment);
2646 return;
2647 }
2648 }
2649 } else {
2650 __ load_klass(recv, recv);
2651 Label update_done;
2652 type_profile_helper(mdo, md, data, recv, &update_done);
2653 // Receiver did not match any saved receiver and there is no empty row for it.
2654 // Increment total counter to indicate polymorphic case.
2655 __ addptr(counter_addr, DataLayout::counter_increment);
2656
2657 __ bind(update_done);
2658 }
2659 } else {
2660 // Static call
2661 __ addptr(counter_addr, DataLayout::counter_increment);
2662 }
2663 }
2664
2665
2666 void LIR_Assembler::emit_delay(LIR_OpDelay*) {
2667 Unimplemented();
2668 }
2669
2670
2671 void LIR_Assembler::monitor_address(int monitor_no, LIR_Opr dst) {
2672 __ lea(dst->as_register(), frame_map()->address_for_monitor_lock(monitor_no));
2673 }
2674
2675 void LIR_Assembler::emit_updatecrc32(LIR_OpUpdateCRC32* op) {
2676 assert(op->crc()->is_single_cpu(), "crc must be register");
2677 assert(op->val()->is_single_cpu(), "byte value must be register");
2678 assert(op->result_opr()->is_single_cpu(), "result must be register");
2679 Register crc = op->crc()->as_register();
2680 Register val = op->val()->as_register();
2681 Register res = op->result_opr()->as_register();
2682
2683 assert_different_registers(val, crc, res);
2684 unsigned long offset;
2685 __ adrp(res, ExternalAddress(StubRoutines::crc_table_addr()), offset);
2686 if (offset) __ add(res, res, offset);
2687
2688 __ mvnw(crc, crc); // ~crc
2689 __ update_byte_crc32(crc, val, res);
2690 __ mvnw(res, crc); // ~crc
2691 }
2692
2693 void LIR_Assembler::emit_profile_type(LIR_OpProfileType* op) {
2694 COMMENT("emit_profile_type {");
2695 Register obj = op->obj()->as_register();
2696 Register tmp = op->tmp()->as_pointer_register();
2697 Address mdo_addr = as_Address(op->mdp()->as_address_ptr());
2698 ciKlass* exact_klass = op->exact_klass();
2699 intptr_t current_klass = op->current_klass();
2700 bool not_null = op->not_null();
2701 bool no_conflict = op->no_conflict();
2702
2703 Label update, next, none;
2704
2705 bool do_null = !not_null;
2706 bool exact_klass_set = exact_klass != NULL && ciTypeEntries::valid_ciklass(current_klass) == exact_klass;
2707 bool do_update = !TypeEntries::is_type_unknown(current_klass) && !exact_klass_set;
2708
2709 assert(do_null || do_update, "why are we here?");
2710 assert(!TypeEntries::was_null_seen(current_klass) || do_update, "why are we here?");
2711 assert(mdo_addr.base() != rscratch1, "wrong register");
2712
2713 __ verify_oop(obj);
2714
2715 if (tmp != obj) {
2716 __ mov(tmp, obj);
2717 }
2718 if (do_null) {
2719 __ cbnz(tmp, update);
2720 if (!TypeEntries::was_null_seen(current_klass)) {
2721 __ ldr(rscratch2, mdo_addr);
2722 __ orr(rscratch2, rscratch2, TypeEntries::null_seen);
2723 __ str(rscratch2, mdo_addr);
2724 }
2725 if (do_update) {
2726 #ifndef ASSERT
2727 __ b(next);
2728 }
2729 #else
2730 __ b(next);
2731 }
2732 } else {
2733 __ cbnz(tmp, update);
2734 __ stop("unexpected null obj");
2735 #endif
2736 }
2737
2738 __ bind(update);
2739
2740 if (do_update) {
2741 #ifdef ASSERT
2742 if (exact_klass != NULL) {
2743 Label ok;
2744 __ load_klass(tmp, tmp);
2745 __ mov_metadata(rscratch1, exact_klass->constant_encoding());
2746 __ eor(rscratch1, tmp, rscratch1);
2747 __ cbz(rscratch1, ok);
2748 __ stop("exact klass and actual klass differ");
2749 __ bind(ok);
2750 }
2751 #endif
2752 if (!no_conflict) {
2753 if (exact_klass == NULL || TypeEntries::is_type_none(current_klass)) {
2754 if (exact_klass != NULL) {
2755 __ mov_metadata(tmp, exact_klass->constant_encoding());
2756 } else {
2757 __ load_klass(tmp, tmp);
2758 }
2759
2760 __ ldr(rscratch2, mdo_addr);
2761 __ eor(tmp, tmp, rscratch2);
2762 __ andr(rscratch1, tmp, TypeEntries::type_klass_mask);
2763 // klass seen before, nothing to do. The unknown bit may have been
2764 // set already but no need to check.
2765 __ cbz(rscratch1, next);
2766
2767 __ tbnz(tmp, exact_log2(TypeEntries::type_unknown), next); // already unknown. Nothing to do anymore.
2768
2769 if (TypeEntries::is_type_none(current_klass)) {
2770 __ cbz(rscratch2, none);
2771 __ cmp(rscratch2, (u1)TypeEntries::null_seen);
2772 __ br(Assembler::EQ, none);
2773 // There is a chance that the checks above (re-reading profiling
2774 // data from memory) fail if another thread has just set the
2775 // profiling to this obj's klass
2776 __ dmb(Assembler::ISHLD);
2777 __ ldr(rscratch2, mdo_addr);
2778 __ eor(tmp, tmp, rscratch2);
2779 __ andr(rscratch1, tmp, TypeEntries::type_klass_mask);
2780 __ cbz(rscratch1, next);
2781 }
2782 } else {
2783 assert(ciTypeEntries::valid_ciklass(current_klass) != NULL &&
2784 ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "conflict only");
2785
2786 __ ldr(tmp, mdo_addr);
2787 __ tbnz(tmp, exact_log2(TypeEntries::type_unknown), next); // already unknown. Nothing to do anymore.
2788 }
2789
2790 // different than before. Cannot keep accurate profile.
2791 __ ldr(rscratch2, mdo_addr);
2792 __ orr(rscratch2, rscratch2, TypeEntries::type_unknown);
2793 __ str(rscratch2, mdo_addr);
2794
2795 if (TypeEntries::is_type_none(current_klass)) {
2796 __ b(next);
2797
2798 __ bind(none);
2799 // first time here. Set profile type.
2800 __ str(tmp, mdo_addr);
2801 }
2802 } else {
2803 // There's a single possible klass at this profile point
2804 assert(exact_klass != NULL, "should be");
2805 if (TypeEntries::is_type_none(current_klass)) {
2806 __ mov_metadata(tmp, exact_klass->constant_encoding());
2807 __ ldr(rscratch2, mdo_addr);
2808 __ eor(tmp, tmp, rscratch2);
2809 __ andr(rscratch1, tmp, TypeEntries::type_klass_mask);
2810 __ cbz(rscratch1, next);
2811 #ifdef ASSERT
2812 {
2813 Label ok;
2814 __ ldr(rscratch1, mdo_addr);
2815 __ cbz(rscratch1, ok);
2816 __ cmp(rscratch1, (u1)TypeEntries::null_seen);
2817 __ br(Assembler::EQ, ok);
2818 // may have been set by another thread
2819 __ dmb(Assembler::ISHLD);
2820 __ mov_metadata(rscratch1, exact_klass->constant_encoding());
2821 __ ldr(rscratch2, mdo_addr);
2822 __ eor(rscratch2, rscratch1, rscratch2);
2823 __ andr(rscratch2, rscratch2, TypeEntries::type_mask);
2824 __ cbz(rscratch2, ok);
2825
2826 __ stop("unexpected profiling mismatch");
2827 __ bind(ok);
2828 }
2829 #endif
2830 // first time here. Set profile type.
2831 __ ldr(tmp, mdo_addr);
2832 } else {
2833 assert(ciTypeEntries::valid_ciklass(current_klass) != NULL &&
2834 ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "inconsistent");
2835
2836 __ ldr(tmp, mdo_addr);
2837 __ tbnz(tmp, exact_log2(TypeEntries::type_unknown), next); // already unknown. Nothing to do anymore.
2838
2839 __ orr(tmp, tmp, TypeEntries::type_unknown);
2840 __ str(tmp, mdo_addr);
2841 // FIXME: Write barrier needed here?
2842 }
2843 }
2844
2845 __ bind(next);
2846 }
2847 COMMENT("} emit_profile_type");
2848 }
2849
2850
2851 void LIR_Assembler::align_backward_branch_target() {
2852 }
2853
2854
2855 void LIR_Assembler::negate(LIR_Opr left, LIR_Opr dest, LIR_Opr tmp) {
2856 // tmp must be unused
2857 assert(tmp->is_illegal(), "wasting a register if tmp is allocated");
2858
2859 if (left->is_single_cpu()) {
2860 assert(dest->is_single_cpu(), "expect single result reg");
2861 __ negw(dest->as_register(), left->as_register());
2862 } else if (left->is_double_cpu()) {
2863 assert(dest->is_double_cpu(), "expect double result reg");
2864 __ neg(dest->as_register_lo(), left->as_register_lo());
2865 } else if (left->is_single_fpu()) {
2866 assert(dest->is_single_fpu(), "expect single float result reg");
2867 __ fnegs(dest->as_float_reg(), left->as_float_reg());
2868 } else {
2869 assert(left->is_double_fpu(), "expect double float operand reg");
2870 assert(dest->is_double_fpu(), "expect double float result reg");
2871 __ fnegd(dest->as_double_reg(), left->as_double_reg());
2872 }
2873 }
2874
2875
2876 void LIR_Assembler::leal(LIR_Opr addr, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
2877 assert(patch_code == lir_patch_none, "Patch code not supported");
2878 __ lea(dest->as_register_lo(), as_Address(addr->as_address_ptr()));
2879 }
2880
2881
2882 void LIR_Assembler::rt_call(LIR_Opr result, address dest, const LIR_OprList* args, LIR_Opr tmp, CodeEmitInfo* info) {
2883 assert(!tmp->is_valid(), "don't need temporary");
2884
2885 CodeBlob *cb = CodeCache::find_blob(dest);
2886 if (cb) {
2887 __ far_call(RuntimeAddress(dest));
2888 } else {
2889 __ mov(rscratch1, RuntimeAddress(dest));
2890 int len = args->length();
2891 int type = 0;
2892 if (! result->is_illegal()) {
2893 switch (result->type()) {
2894 case T_VOID:
2895 type = 0;
2896 break;
2897 case T_INT:
2898 case T_LONG:
2899 case T_OBJECT:
2900 case T_VALUETYPE:
2901 type = 1;
2902 break;
2903 case T_FLOAT:
2904 type = 2;
2905 break;
2906 case T_DOUBLE:
2907 type = 3;
2908 break;
2909 default:
2910 ShouldNotReachHere();
2911 break;
2912 }
2913 }
2914 int num_gpargs = 0;
2915 int num_fpargs = 0;
2916 for (int i = 0; i < args->length(); i++) {
2917 LIR_Opr arg = args->at(i);
2918 if (arg->type() == T_FLOAT || arg->type() == T_DOUBLE) {
2919 num_fpargs++;
2920 } else {
2921 num_gpargs++;
2922 }
2923 }
2924 __ blrt(rscratch1, num_gpargs, num_fpargs, type);
2925 }
2926
2927 if (info != NULL) {
2928 add_call_info_here(info);
2929 }
2930 __ maybe_isb();
2931 }
2932
2933 void LIR_Assembler::volatile_move_op(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info) {
2934 if (dest->is_address() || src->is_address()) {
2935 move_op(src, dest, type, lir_patch_none, info,
2936 /*pop_fpu_stack*/false, /*unaligned*/false, /*wide*/false);
2937 } else {
2938 ShouldNotReachHere();
2939 }
2940 }
2941
2942 #ifdef ASSERT
2943 // emit run-time assertion
2944 void LIR_Assembler::emit_assert(LIR_OpAssert* op) {
2945 assert(op->code() == lir_assert, "must be");
2946
2947 if (op->in_opr1()->is_valid()) {
2948 assert(op->in_opr2()->is_valid(), "both operands must be valid");
2949 comp_op(op->condition(), op->in_opr1(), op->in_opr2(), op);
2950 } else {
2951 assert(op->in_opr2()->is_illegal(), "both operands must be illegal");
2952 assert(op->condition() == lir_cond_always, "no other conditions allowed");
2953 }
2954
2955 Label ok;
2956 if (op->condition() != lir_cond_always) {
2957 Assembler::Condition acond = Assembler::AL;
2958 switch (op->condition()) {
2959 case lir_cond_equal: acond = Assembler::EQ; break;
2960 case lir_cond_notEqual: acond = Assembler::NE; break;
2961 case lir_cond_less: acond = Assembler::LT; break;
2962 case lir_cond_lessEqual: acond = Assembler::LE; break;
2963 case lir_cond_greaterEqual: acond = Assembler::GE; break;
2964 case lir_cond_greater: acond = Assembler::GT; break;
2965 case lir_cond_belowEqual: acond = Assembler::LS; break;
2966 case lir_cond_aboveEqual: acond = Assembler::HS; break;
2967 default: ShouldNotReachHere();
2968 }
2969 __ br(acond, ok);
2970 }
2971 if (op->halt()) {
2972 const char* str = __ code_string(op->msg());
2973 __ stop(str);
2974 } else {
2975 breakpoint();
2976 }
2977 __ bind(ok);
2978 }
2979 #endif
2980
2981 #ifndef PRODUCT
2982 #define COMMENT(x) do { __ block_comment(x); } while (0)
2983 #else
2984 #define COMMENT(x)
2985 #endif
2986
2987 void LIR_Assembler::membar() {
2988 COMMENT("membar");
2989 __ membar(MacroAssembler::AnyAny);
2990 }
2991
2992 void LIR_Assembler::membar_acquire() {
2993 __ membar(Assembler::LoadLoad|Assembler::LoadStore);
2994 }
2995
2996 void LIR_Assembler::membar_release() {
2997 __ membar(Assembler::LoadStore|Assembler::StoreStore);
2998 }
2999
3000 void LIR_Assembler::membar_loadload() {
3001 __ membar(Assembler::LoadLoad);
3002 }
3003
3004 void LIR_Assembler::membar_storestore() {
3005 __ membar(MacroAssembler::StoreStore);
3006 }
3007
3008 void LIR_Assembler::membar_loadstore() { __ membar(MacroAssembler::LoadStore); }
3009
3010 void LIR_Assembler::membar_storeload() { __ membar(MacroAssembler::StoreLoad); }
3011
3012 void LIR_Assembler::on_spin_wait() {
3013 Unimplemented();
3014 }
3015
3016 void LIR_Assembler::get_thread(LIR_Opr result_reg) {
3017 __ mov(result_reg->as_register(), rthread);
3018 }
3019
3020
3021 void LIR_Assembler::peephole(LIR_List *lir) {
3022 #if 0
3023 if (tableswitch_count >= max_tableswitches)
3024 return;
3025
3026 /*
3027 This finite-state automaton recognizes sequences of compare-and-
3028 branch instructions. We will turn them into a tableswitch. You
3029 could argue that C1 really shouldn't be doing this sort of
3030 optimization, but without it the code is really horrible.
3031 */
3032
3033 enum { start_s, cmp1_s, beq_s, cmp_s } state;
3034 int first_key, last_key = -2147483648;
3035 int next_key = 0;
3036 int start_insn = -1;
3037 int last_insn = -1;
3038 Register reg = noreg;
3039 LIR_Opr reg_opr;
3040 state = start_s;
3041
3042 LIR_OpList* inst = lir->instructions_list();
3043 for (int i = 0; i < inst->length(); i++) {
3044 LIR_Op* op = inst->at(i);
3045 switch (state) {
3046 case start_s:
3047 first_key = -1;
3048 start_insn = i;
3049 switch (op->code()) {
3050 case lir_cmp:
3051 LIR_Opr opr1 = op->as_Op2()->in_opr1();
3052 LIR_Opr opr2 = op->as_Op2()->in_opr2();
3053 if (opr1->is_cpu_register() && opr1->is_single_cpu()
3054 && opr2->is_constant()
3055 && opr2->type() == T_INT) {
3056 reg_opr = opr1;
3057 reg = opr1->as_register();
3058 first_key = opr2->as_constant_ptr()->as_jint();
3059 next_key = first_key + 1;
3060 state = cmp_s;
3061 goto next_state;
3062 }
3063 break;
3064 }
3065 break;
3066 case cmp_s:
3067 switch (op->code()) {
3068 case lir_branch:
3069 if (op->as_OpBranch()->cond() == lir_cond_equal) {
3070 state = beq_s;
3071 last_insn = i;
3072 goto next_state;
3073 }
3074 }
3075 state = start_s;
3076 break;
3077 case beq_s:
3078 switch (op->code()) {
3079 case lir_cmp: {
3080 LIR_Opr opr1 = op->as_Op2()->in_opr1();
3081 LIR_Opr opr2 = op->as_Op2()->in_opr2();
3082 if (opr1->is_cpu_register() && opr1->is_single_cpu()
3083 && opr1->as_register() == reg
3084 && opr2->is_constant()
3085 && opr2->type() == T_INT
3086 && opr2->as_constant_ptr()->as_jint() == next_key) {
3087 last_key = next_key;
3088 next_key++;
3089 state = cmp_s;
3090 goto next_state;
3091 }
3092 }
3093 }
3094 last_key = next_key;
3095 state = start_s;
3096 break;
3097 default:
3098 assert(false, "impossible state");
3099 }
3100 if (state == start_s) {
3101 if (first_key < last_key - 5L && reg != noreg) {
3102 {
3103 // printf("found run register %d starting at insn %d low value %d high value %d\n",
3104 // reg->encoding(),
3105 // start_insn, first_key, last_key);
3106 // for (int i = 0; i < inst->length(); i++) {
3107 // inst->at(i)->print();
3108 // tty->print("\n");
3109 // }
3110 // tty->print("\n");
3111 }
3112
3113 struct tableswitch *sw = &switches[tableswitch_count];
3114 sw->_insn_index = start_insn, sw->_first_key = first_key,
3115 sw->_last_key = last_key, sw->_reg = reg;
3116 inst->insert_before(last_insn + 1, new LIR_OpLabel(&sw->_after));
3117 {
3118 // Insert the new table of branches
3119 int offset = last_insn;
3120 for (int n = first_key; n < last_key; n++) {
3121 inst->insert_before
3122 (last_insn + 1,
3123 new LIR_OpBranch(lir_cond_always, T_ILLEGAL,
3124 inst->at(offset)->as_OpBranch()->label()));
3125 offset -= 2, i++;
3126 }
3127 }
3128 // Delete all the old compare-and-branch instructions
3129 for (int n = first_key; n < last_key; n++) {
3130 inst->remove_at(start_insn);
3131 inst->remove_at(start_insn);
3132 }
3133 // Insert the tableswitch instruction
3134 inst->insert_before(start_insn,
3135 new LIR_Op2(lir_cmp, lir_cond_always,
3136 LIR_OprFact::intConst(tableswitch_count),
3137 reg_opr));
3138 inst->insert_before(start_insn + 1, new LIR_OpLabel(&sw->_branches));
3139 tableswitch_count++;
3140 }
3141 reg = noreg;
3142 last_key = -2147483648;
3143 }
3144 next_state:
3145 ;
3146 }
3147 #endif
3148 }
3149
3150 void LIR_Assembler::atomic_op(LIR_Code code, LIR_Opr src, LIR_Opr data, LIR_Opr dest, LIR_Opr tmp_op) {
3151 Address addr = as_Address(src->as_address_ptr());
3152 BasicType type = src->type();
3153 bool is_oop = type == T_OBJECT || type == T_ARRAY;
3154
3155 void (MacroAssembler::* add)(Register prev, RegisterOrConstant incr, Register addr);
3156 void (MacroAssembler::* xchg)(Register prev, Register newv, Register addr);
3157
3158 switch(type) {
3159 case T_INT:
3160 xchg = &MacroAssembler::atomic_xchgalw;
3161 add = &MacroAssembler::atomic_addalw;
3162 break;
3163 case T_LONG:
3164 xchg = &MacroAssembler::atomic_xchgal;
3165 add = &MacroAssembler::atomic_addal;
3166 break;
3167 case T_VALUETYPE:
3168 case T_OBJECT:
3169 case T_ARRAY:
3170 if (UseCompressedOops) {
3171 xchg = &MacroAssembler::atomic_xchgalw;
3172 add = &MacroAssembler::atomic_addalw;
3173 } else {
3174 xchg = &MacroAssembler::atomic_xchgal;
3175 add = &MacroAssembler::atomic_addal;
3176 }
3177 break;
3178 default:
3179 ShouldNotReachHere();
3180 xchg = &MacroAssembler::atomic_xchgal;
3181 add = &MacroAssembler::atomic_addal; // unreachable
3182 }
3183
3184 switch (code) {
3185 case lir_xadd:
3186 {
3187 RegisterOrConstant inc;
3188 Register tmp = as_reg(tmp_op);
3189 Register dst = as_reg(dest);
3190 if (data->is_constant()) {
3191 inc = RegisterOrConstant(as_long(data));
3192 assert_different_registers(dst, addr.base(), tmp,
3193 rscratch1, rscratch2);
3194 } else {
3195 inc = RegisterOrConstant(as_reg(data));
3196 assert_different_registers(inc.as_register(), dst, addr.base(), tmp,
3197 rscratch1, rscratch2);
3198 }
3199 __ lea(tmp, addr);
3200 (_masm->*add)(dst, inc, tmp);
3201 break;
3202 }
3203 case lir_xchg:
3204 {
3205 Register tmp = tmp_op->as_register();
3206 Register obj = as_reg(data);
3207 Register dst = as_reg(dest);
3208 if (is_oop && UseCompressedOops) {
3209 __ encode_heap_oop(rscratch2, obj);
3210 obj = rscratch2;
3211 }
3212 assert_different_registers(obj, addr.base(), tmp, rscratch1, dst);
3213 __ lea(tmp, addr);
3214 (_masm->*xchg)(dst, obj, tmp);
3215 if (is_oop && UseCompressedOops) {
3216 __ decode_heap_oop(dst);
3217 }
3218 }
3219 break;
3220 default:
3221 ShouldNotReachHere();
3222 }
3223 __ membar(__ AnyAny);
3224 }
3225
3226 #undef __