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src/share/vm/opto/chaitin.cpp

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 823           //         RegL  RegI  RegFlags   RegF RegD    INTPRESSURE  FLOATPRESSURE
 824           // IA32     2     1     1          1    1          6           6
 825           // IA64     1     1     1          1    1         50          41
 826           // SPARC    2     2     2          2    2         48 (24)     52 (26)
 827           // SPARCV9  2     2     2          2    2         48 (24)     52 (26)
 828           // AMD64    1     1     1          1    1         14          15
 829           // -----------------------------------------------------
 830 #if defined(SPARC)
 831           lrg.set_reg_pressure(2);  // use for v9 as well
 832 #else
 833           lrg.set_reg_pressure(1);  // normally one value per register
 834 #endif
 835           if( n_type->isa_oop_ptr() ) {
 836             lrg._is_oop = 1;
 837           }
 838           break;
 839         case Op_RegL:           // Check for long or double
 840         case Op_RegD:
 841           lrg.set_num_regs(2);
 842           // Define platform specific register pressure
 843 #if defined(SPARC) || defined(ARM)
 844           lrg.set_reg_pressure(2);
 845 #elif defined(IA32)
 846           if( ireg == Op_RegL ) {
 847             lrg.set_reg_pressure(2);
 848           } else {
 849             lrg.set_reg_pressure(1);
 850           }
 851 #else
 852           lrg.set_reg_pressure(1);  // normally one value per register
 853 #endif
 854           // If this def of a double forces a mis-aligned double,
 855           // flag as '_fat_proj' - really flag as allowing misalignment
 856           // AND changes how we count interferences.  A mis-aligned
 857           // double can interfere with TWO aligned pairs, or effectively
 858           // FOUR registers!
 859           if (rm.is_misaligned_pair()) {
 860             lrg._fat_proj = 1;
 861             lrg._is_bound = 1;
 862           }
 863           break;




 823           //         RegL  RegI  RegFlags   RegF RegD    INTPRESSURE  FLOATPRESSURE
 824           // IA32     2     1     1          1    1          6           6
 825           // IA64     1     1     1          1    1         50          41
 826           // SPARC    2     2     2          2    2         48 (24)     52 (26)
 827           // SPARCV9  2     2     2          2    2         48 (24)     52 (26)
 828           // AMD64    1     1     1          1    1         14          15
 829           // -----------------------------------------------------
 830 #if defined(SPARC)
 831           lrg.set_reg_pressure(2);  // use for v9 as well
 832 #else
 833           lrg.set_reg_pressure(1);  // normally one value per register
 834 #endif
 835           if( n_type->isa_oop_ptr() ) {
 836             lrg._is_oop = 1;
 837           }
 838           break;
 839         case Op_RegL:           // Check for long or double
 840         case Op_RegD:
 841           lrg.set_num_regs(2);
 842           // Define platform specific register pressure
 843 #if defined(SPARC) || defined(ARM32)
 844           lrg.set_reg_pressure(2);
 845 #elif defined(IA32)
 846           if( ireg == Op_RegL ) {
 847             lrg.set_reg_pressure(2);
 848           } else {
 849             lrg.set_reg_pressure(1);
 850           }
 851 #else
 852           lrg.set_reg_pressure(1);  // normally one value per register
 853 #endif
 854           // If this def of a double forces a mis-aligned double,
 855           // flag as '_fat_proj' - really flag as allowing misalignment
 856           // AND changes how we count interferences.  A mis-aligned
 857           // double can interfere with TWO aligned pairs, or effectively
 858           // FOUR registers!
 859           if (rm.is_misaligned_pair()) {
 860             lrg._fat_proj = 1;
 861             lrg._is_bound = 1;
 862           }
 863           break;


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