2121
2122 assert(assigned_reg >= pd_first_fpu_reg && assigned_reg <= pd_last_fpu_reg, "no fpu register");
2123 assert(interval->assigned_regHi() == any_reg, "must not have hi register");
2124 return LIR_OprFact::single_fpu(assigned_reg - pd_first_fpu_reg);
2125 }
2126
2127 case T_DOUBLE: {
2128 #ifdef X86
2129 if (UseSSE >= 2) {
2130 assert(assigned_reg >= pd_first_xmm_reg && assigned_reg <= pd_last_xmm_reg, "no xmm register");
2131 assert(interval->assigned_regHi() == any_reg, "must not have hi register (double xmm values are stored in one register)");
2132 return LIR_OprFact::double_xmm(assigned_reg - pd_first_xmm_reg);
2133 }
2134 #endif
2135
2136 #ifdef SPARC
2137 assert(assigned_reg >= pd_first_fpu_reg && assigned_reg <= pd_last_fpu_reg, "no fpu register");
2138 assert(interval->assigned_regHi() >= pd_first_fpu_reg && interval->assigned_regHi() <= pd_last_fpu_reg, "no fpu register");
2139 assert(assigned_reg % 2 == 0 && assigned_reg + 1 == interval->assigned_regHi(), "must be sequential and even");
2140 LIR_Opr result = LIR_OprFact::double_fpu(interval->assigned_regHi() - pd_first_fpu_reg, assigned_reg - pd_first_fpu_reg);
2141 #elif defined(ARM)
2142 assert(assigned_reg >= pd_first_fpu_reg && assigned_reg <= pd_last_fpu_reg, "no fpu register");
2143 assert(interval->assigned_regHi() >= pd_first_fpu_reg && interval->assigned_regHi() <= pd_last_fpu_reg, "no fpu register");
2144 assert(assigned_reg % 2 == 0 && assigned_reg + 1 == interval->assigned_regHi(), "must be sequential and even");
2145 LIR_Opr result = LIR_OprFact::double_fpu(assigned_reg - pd_first_fpu_reg, interval->assigned_regHi() - pd_first_fpu_reg);
2146 #else
2147 assert(assigned_reg >= pd_first_fpu_reg && assigned_reg <= pd_last_fpu_reg, "no fpu register");
2148 assert(interval->assigned_regHi() == any_reg, "must not have hi register (double fpu values are stored in one register on Intel)");
2149 LIR_Opr result = LIR_OprFact::double_fpu(assigned_reg - pd_first_fpu_reg);
2150 #endif
2151 return result;
2152 }
2153 #endif // __SOFTFP__
2154
2155 default: {
2156 ShouldNotReachHere();
2157 return LIR_OprFact::illegalOpr;
2158 }
2159 }
2160 }
2161 }
2710 // On SPARC, fpu_regnrLo/fpu_regnrHi represents the two halves of
2711 // the double as float registers in the native ordering. On X86,
2712 // fpu_regnrLo is a FPU stack slot whose VMReg represents
2713 // the low-order word of the double and fpu_regnrLo + 1 is the
2714 // name for the other half. *first and *second must represent the
2715 // least and most significant words, respectively.
2716
2717 #ifdef X86
2718 // the exact location of fpu stack values is only known
2719 // during fpu stack allocation, so the stack allocator object
2720 // must be present
2721 assert(use_fpu_stack_allocation(), "should not have float stack values without fpu stack allocation (all floats must be SSE2)");
2722 assert(_fpu_stack_allocator != NULL, "must be present");
2723 opr = _fpu_stack_allocator->to_fpu_stack(opr);
2724
2725 assert(opr->fpu_regnrLo() == opr->fpu_regnrHi(), "assumed in calculation (only fpu_regnrLo is used)");
2726 #endif
2727 #ifdef SPARC
2728 assert(opr->fpu_regnrLo() == opr->fpu_regnrHi() + 1, "assumed in calculation (only fpu_regnrHi is used)");
2729 #endif
2730 #ifdef ARM
2731 assert(opr->fpu_regnrHi() == opr->fpu_regnrLo() + 1, "assumed in calculation (only fpu_regnrLo is used)");
2732 #endif
2733 #ifdef PPC
2734 assert(opr->fpu_regnrLo() == opr->fpu_regnrHi(), "assumed in calculation (only fpu_regnrHi is used)");
2735 #endif
2736
2737 #ifdef VM_LITTLE_ENDIAN
2738 VMReg rname_first = frame_map()->fpu_regname(opr->fpu_regnrLo());
2739 #else
2740 VMReg rname_first = frame_map()->fpu_regname(opr->fpu_regnrHi());
2741 #endif
2742
2743 #ifdef _LP64
2744 first = new LocationValue(Location::new_reg_loc(Location::dbl, rname_first));
2745 second = _int_0_scope_value;
2746 #else
2747 first = new LocationValue(Location::new_reg_loc(Location::normal, rname_first));
2748 // %%% This is probably a waste but we'll keep things as they were for now
2749 if (true) {
2750 VMReg rname_second = rname_first->next();
|
2121
2122 assert(assigned_reg >= pd_first_fpu_reg && assigned_reg <= pd_last_fpu_reg, "no fpu register");
2123 assert(interval->assigned_regHi() == any_reg, "must not have hi register");
2124 return LIR_OprFact::single_fpu(assigned_reg - pd_first_fpu_reg);
2125 }
2126
2127 case T_DOUBLE: {
2128 #ifdef X86
2129 if (UseSSE >= 2) {
2130 assert(assigned_reg >= pd_first_xmm_reg && assigned_reg <= pd_last_xmm_reg, "no xmm register");
2131 assert(interval->assigned_regHi() == any_reg, "must not have hi register (double xmm values are stored in one register)");
2132 return LIR_OprFact::double_xmm(assigned_reg - pd_first_xmm_reg);
2133 }
2134 #endif
2135
2136 #ifdef SPARC
2137 assert(assigned_reg >= pd_first_fpu_reg && assigned_reg <= pd_last_fpu_reg, "no fpu register");
2138 assert(interval->assigned_regHi() >= pd_first_fpu_reg && interval->assigned_regHi() <= pd_last_fpu_reg, "no fpu register");
2139 assert(assigned_reg % 2 == 0 && assigned_reg + 1 == interval->assigned_regHi(), "must be sequential and even");
2140 LIR_Opr result = LIR_OprFact::double_fpu(interval->assigned_regHi() - pd_first_fpu_reg, assigned_reg - pd_first_fpu_reg);
2141 #elif defined(ARM32)
2142 assert(assigned_reg >= pd_first_fpu_reg && assigned_reg <= pd_last_fpu_reg, "no fpu register");
2143 assert(interval->assigned_regHi() >= pd_first_fpu_reg && interval->assigned_regHi() <= pd_last_fpu_reg, "no fpu register");
2144 assert(assigned_reg % 2 == 0 && assigned_reg + 1 == interval->assigned_regHi(), "must be sequential and even");
2145 LIR_Opr result = LIR_OprFact::double_fpu(assigned_reg - pd_first_fpu_reg, interval->assigned_regHi() - pd_first_fpu_reg);
2146 #else
2147 assert(assigned_reg >= pd_first_fpu_reg && assigned_reg <= pd_last_fpu_reg, "no fpu register");
2148 assert(interval->assigned_regHi() == any_reg, "must not have hi register (double fpu values are stored in one register on Intel)");
2149 LIR_Opr result = LIR_OprFact::double_fpu(assigned_reg - pd_first_fpu_reg);
2150 #endif
2151 return result;
2152 }
2153 #endif // __SOFTFP__
2154
2155 default: {
2156 ShouldNotReachHere();
2157 return LIR_OprFact::illegalOpr;
2158 }
2159 }
2160 }
2161 }
2710 // On SPARC, fpu_regnrLo/fpu_regnrHi represents the two halves of
2711 // the double as float registers in the native ordering. On X86,
2712 // fpu_regnrLo is a FPU stack slot whose VMReg represents
2713 // the low-order word of the double and fpu_regnrLo + 1 is the
2714 // name for the other half. *first and *second must represent the
2715 // least and most significant words, respectively.
2716
2717 #ifdef X86
2718 // the exact location of fpu stack values is only known
2719 // during fpu stack allocation, so the stack allocator object
2720 // must be present
2721 assert(use_fpu_stack_allocation(), "should not have float stack values without fpu stack allocation (all floats must be SSE2)");
2722 assert(_fpu_stack_allocator != NULL, "must be present");
2723 opr = _fpu_stack_allocator->to_fpu_stack(opr);
2724
2725 assert(opr->fpu_regnrLo() == opr->fpu_regnrHi(), "assumed in calculation (only fpu_regnrLo is used)");
2726 #endif
2727 #ifdef SPARC
2728 assert(opr->fpu_regnrLo() == opr->fpu_regnrHi() + 1, "assumed in calculation (only fpu_regnrHi is used)");
2729 #endif
2730 #ifdef ARM32
2731 assert(opr->fpu_regnrHi() == opr->fpu_regnrLo() + 1, "assumed in calculation (only fpu_regnrLo is used)");
2732 #endif
2733 #ifdef PPC
2734 assert(opr->fpu_regnrLo() == opr->fpu_regnrHi(), "assumed in calculation (only fpu_regnrHi is used)");
2735 #endif
2736
2737 #ifdef VM_LITTLE_ENDIAN
2738 VMReg rname_first = frame_map()->fpu_regname(opr->fpu_regnrLo());
2739 #else
2740 VMReg rname_first = frame_map()->fpu_regname(opr->fpu_regnrHi());
2741 #endif
2742
2743 #ifdef _LP64
2744 first = new LocationValue(Location::new_reg_loc(Location::dbl, rname_first));
2745 second = _int_0_scope_value;
2746 #else
2747 first = new LocationValue(Location::new_reg_loc(Location::normal, rname_first));
2748 // %%% This is probably a waste but we'll keep things as they were for now
2749 if (true) {
2750 VMReg rname_second = rname_first->next();
|