1 /*
2 * Copyright (c) 1997, 2015, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #include "precompiled.hpp"
26 #include "asm/assembler.hpp"
27 #include "asm/assembler.inline.hpp"
28 #include "gc/shared/cardTableModRefBS.hpp"
29 #include "gc/shared/collectedHeap.inline.hpp"
30 #include "interpreter/interpreter.hpp"
31 #include "memory/resourceArea.hpp"
32 #include "prims/methodHandles.hpp"
33 #include "runtime/biasedLocking.hpp"
34 #include "runtime/interfaceSupport.hpp"
35 #include "runtime/objectMonitor.hpp"
36 #include "runtime/os.hpp"
37 #include "runtime/sharedRuntime.hpp"
38 #include "runtime/stubRoutines.hpp"
39 #include "utilities/macros.hpp"
40 #if INCLUDE_ALL_GCS
41 #include "gc/g1/g1CollectedHeap.inline.hpp"
42 #include "gc/g1/g1SATBCardTableModRefBS.hpp"
43 #include "gc/g1/heapRegion.hpp"
44 #endif // INCLUDE_ALL_GCS
45
46 #ifdef PRODUCT
47 #define BLOCK_COMMENT(str) /* nothing */
48 #define STOP(error) stop(error)
49 #else
50 #define BLOCK_COMMENT(str) block_comment(str)
51 #define STOP(error) block_comment(error); stop(error)
52 #endif
53
54 #define BIND(label) bind(label); BLOCK_COMMENT(#label ":")
55 // Implementation of AddressLiteral
56
57 // A 2-D table for managing compressed displacement(disp8) on EVEX enabled platforms.
58 unsigned char tuple_table[Assembler::EVEX_ETUP + 1][Assembler::AVX_512bit + 1] = {
59 // -----------------Table 4.5 -------------------- //
60 16, 32, 64, // EVEX_FV(0)
61 4, 4, 4, // EVEX_FV(1) - with Evex.b
62 16, 32, 64, // EVEX_FV(2) - with Evex.w
63 8, 8, 8, // EVEX_FV(3) - with Evex.w and Evex.b
64 8, 16, 32, // EVEX_HV(0)
65 4, 4, 4, // EVEX_HV(1) - with Evex.b
66 // -----------------Table 4.6 -------------------- //
67 16, 32, 64, // EVEX_FVM(0)
68 1, 1, 1, // EVEX_T1S(0)
69 2, 2, 2, // EVEX_T1S(1)
70 4, 4, 4, // EVEX_T1S(2)
71 8, 8, 8, // EVEX_T1S(3)
72 4, 4, 4, // EVEX_T1F(0)
73 8, 8, 8, // EVEX_T1F(1)
74 8, 8, 8, // EVEX_T2(0)
75 0, 16, 16, // EVEX_T2(1)
76 0, 16, 16, // EVEX_T4(0)
77 0, 0, 32, // EVEX_T4(1)
78 0, 0, 32, // EVEX_T8(0)
79 8, 16, 32, // EVEX_HVM(0)
80 4, 8, 16, // EVEX_QVM(0)
81 2, 4, 8, // EVEX_OVM(0)
82 16, 16, 16, // EVEX_M128(0)
83 8, 32, 64, // EVEX_DUP(0)
84 0, 0, 0 // EVEX_NTUP
85 };
86
87 AddressLiteral::AddressLiteral(address target, relocInfo::relocType rtype) {
88 _is_lval = false;
89 _target = target;
90 switch (rtype) {
91 case relocInfo::oop_type:
92 case relocInfo::metadata_type:
93 // Oops are a special case. Normally they would be their own section
94 // but in cases like icBuffer they are literals in the code stream that
95 // we don't have a section for. We use none so that we get a literal address
96 // which is always patchable.
97 break;
98 case relocInfo::external_word_type:
99 _rspec = external_word_Relocation::spec(target);
100 break;
101 case relocInfo::internal_word_type:
102 _rspec = internal_word_Relocation::spec(target);
103 break;
104 case relocInfo::opt_virtual_call_type:
105 _rspec = opt_virtual_call_Relocation::spec();
106 break;
107 case relocInfo::static_call_type:
108 _rspec = static_call_Relocation::spec();
109 break;
110 case relocInfo::runtime_call_type:
111 _rspec = runtime_call_Relocation::spec();
112 break;
113 case relocInfo::poll_type:
114 case relocInfo::poll_return_type:
115 _rspec = Relocation::spec_simple(rtype);
116 break;
117 case relocInfo::none:
118 break;
119 default:
120 ShouldNotReachHere();
121 break;
122 }
123 }
124
125 // Implementation of Address
126
127 #ifdef _LP64
128
129 Address Address::make_array(ArrayAddress adr) {
130 // Not implementable on 64bit machines
131 // Should have been handled higher up the call chain.
132 ShouldNotReachHere();
133 return Address();
134 }
135
136 // exceedingly dangerous constructor
137 Address::Address(int disp, address loc, relocInfo::relocType rtype) {
138 _base = noreg;
139 _index = noreg;
140 _scale = no_scale;
141 _disp = disp;
142 switch (rtype) {
143 case relocInfo::external_word_type:
144 _rspec = external_word_Relocation::spec(loc);
145 break;
146 case relocInfo::internal_word_type:
147 _rspec = internal_word_Relocation::spec(loc);
148 break;
149 case relocInfo::runtime_call_type:
150 // HMM
151 _rspec = runtime_call_Relocation::spec();
152 break;
153 case relocInfo::poll_type:
154 case relocInfo::poll_return_type:
155 _rspec = Relocation::spec_simple(rtype);
156 break;
157 case relocInfo::none:
158 break;
159 default:
160 ShouldNotReachHere();
161 }
162 }
163 #else // LP64
164
165 Address Address::make_array(ArrayAddress adr) {
166 AddressLiteral base = adr.base();
167 Address index = adr.index();
168 assert(index._disp == 0, "must not have disp"); // maybe it can?
169 Address array(index._base, index._index, index._scale, (intptr_t) base.target());
170 array._rspec = base._rspec;
171 return array;
172 }
173
174 // exceedingly dangerous constructor
175 Address::Address(address loc, RelocationHolder spec) {
176 _base = noreg;
177 _index = noreg;
178 _scale = no_scale;
179 _disp = (intptr_t) loc;
180 _rspec = spec;
181 }
182
183 #endif // _LP64
184
185
186
187 // Convert the raw encoding form into the form expected by the constructor for
188 // Address. An index of 4 (rsp) corresponds to having no index, so convert
189 // that to noreg for the Address constructor.
190 Address Address::make_raw(int base, int index, int scale, int disp, relocInfo::relocType disp_reloc) {
191 RelocationHolder rspec;
192 if (disp_reloc != relocInfo::none) {
193 rspec = Relocation::spec_simple(disp_reloc);
194 }
195 bool valid_index = index != rsp->encoding();
196 if (valid_index) {
197 Address madr(as_Register(base), as_Register(index), (Address::ScaleFactor)scale, in_ByteSize(disp));
198 madr._rspec = rspec;
199 return madr;
200 } else {
201 Address madr(as_Register(base), noreg, Address::no_scale, in_ByteSize(disp));
202 madr._rspec = rspec;
203 return madr;
204 }
205 }
206
207 // Implementation of Assembler
208
209 int AbstractAssembler::code_fill_byte() {
210 return (u_char)'\xF4'; // hlt
211 }
212
213 // make this go away someday
214 void Assembler::emit_data(jint data, relocInfo::relocType rtype, int format) {
215 if (rtype == relocInfo::none)
216 emit_int32(data);
217 else
218 emit_data(data, Relocation::spec_simple(rtype), format);
219 }
220
221 void Assembler::emit_data(jint data, RelocationHolder const& rspec, int format) {
222 assert(imm_operand == 0, "default format must be immediate in this file");
223 assert(inst_mark() != NULL, "must be inside InstructionMark");
224 if (rspec.type() != relocInfo::none) {
225 #ifdef ASSERT
226 check_relocation(rspec, format);
227 #endif
228 // Do not use AbstractAssembler::relocate, which is not intended for
229 // embedded words. Instead, relocate to the enclosing instruction.
230
231 // hack. call32 is too wide for mask so use disp32
232 if (format == call32_operand)
233 code_section()->relocate(inst_mark(), rspec, disp32_operand);
234 else
235 code_section()->relocate(inst_mark(), rspec, format);
236 }
237 emit_int32(data);
238 }
239
240 static int encode(Register r) {
241 int enc = r->encoding();
242 if (enc >= 8) {
243 enc -= 8;
244 }
245 return enc;
246 }
247
248 void Assembler::emit_arith_b(int op1, int op2, Register dst, int imm8) {
249 assert(dst->has_byte_register(), "must have byte register");
250 assert(isByte(op1) && isByte(op2), "wrong opcode");
251 assert(isByte(imm8), "not a byte");
252 assert((op1 & 0x01) == 0, "should be 8bit operation");
253 emit_int8(op1);
254 emit_int8(op2 | encode(dst));
255 emit_int8(imm8);
256 }
257
258
259 void Assembler::emit_arith(int op1, int op2, Register dst, int32_t imm32) {
260 assert(isByte(op1) && isByte(op2), "wrong opcode");
261 assert((op1 & 0x01) == 1, "should be 32bit operation");
262 assert((op1 & 0x02) == 0, "sign-extension bit should not be set");
263 if (is8bit(imm32)) {
264 emit_int8(op1 | 0x02); // set sign bit
265 emit_int8(op2 | encode(dst));
266 emit_int8(imm32 & 0xFF);
267 } else {
268 emit_int8(op1);
269 emit_int8(op2 | encode(dst));
270 emit_int32(imm32);
271 }
272 }
273
274 // Force generation of a 4 byte immediate value even if it fits into 8bit
275 void Assembler::emit_arith_imm32(int op1, int op2, Register dst, int32_t imm32) {
276 assert(isByte(op1) && isByte(op2), "wrong opcode");
277 assert((op1 & 0x01) == 1, "should be 32bit operation");
278 assert((op1 & 0x02) == 0, "sign-extension bit should not be set");
279 emit_int8(op1);
280 emit_int8(op2 | encode(dst));
281 emit_int32(imm32);
282 }
283
284 // immediate-to-memory forms
285 void Assembler::emit_arith_operand(int op1, Register rm, Address adr, int32_t imm32) {
286 assert((op1 & 0x01) == 1, "should be 32bit operation");
287 assert((op1 & 0x02) == 0, "sign-extension bit should not be set");
288 if (is8bit(imm32)) {
289 emit_int8(op1 | 0x02); // set sign bit
290 emit_operand(rm, adr, 1);
291 emit_int8(imm32 & 0xFF);
292 } else {
293 emit_int8(op1);
294 emit_operand(rm, adr, 4);
295 emit_int32(imm32);
296 }
297 }
298
299
300 void Assembler::emit_arith(int op1, int op2, Register dst, Register src) {
301 assert(isByte(op1) && isByte(op2), "wrong opcode");
302 emit_int8(op1);
303 emit_int8(op2 | encode(dst) << 3 | encode(src));
304 }
305
306
307 bool Assembler::query_compressed_disp_byte(int disp, bool is_evex_inst, int vector_len,
308 int cur_tuple_type, int in_size_in_bits, int cur_encoding) {
309 int mod_idx = 0;
310 // We will test if the displacement fits the compressed format and if so
311 // apply the compression to the displacment iff the result is8bit.
312 if (VM_Version::supports_evex() && is_evex_inst) {
313 switch (cur_tuple_type) {
314 case EVEX_FV:
315 if ((cur_encoding & VEX_W) == VEX_W) {
316 mod_idx += 2 + ((cur_encoding & EVEX_Rb) == EVEX_Rb) ? 1 : 0;
317 } else {
318 mod_idx = ((cur_encoding & EVEX_Rb) == EVEX_Rb) ? 1 : 0;
319 }
320 break;
321
322 case EVEX_HV:
323 mod_idx = ((cur_encoding & EVEX_Rb) == EVEX_Rb) ? 1 : 0;
324 break;
325
326 case EVEX_FVM:
327 break;
328
329 case EVEX_T1S:
330 switch (in_size_in_bits) {
331 case EVEX_8bit:
332 break;
333
334 case EVEX_16bit:
335 mod_idx = 1;
336 break;
337
338 case EVEX_32bit:
339 mod_idx = 2;
340 break;
341
342 case EVEX_64bit:
343 mod_idx = 3;
344 break;
345 }
346 break;
347
348 case EVEX_T1F:
349 case EVEX_T2:
350 case EVEX_T4:
351 mod_idx = (in_size_in_bits == EVEX_64bit) ? 1 : 0;
352 break;
353
354 case EVEX_T8:
355 break;
356
357 case EVEX_HVM:
358 break;
359
360 case EVEX_QVM:
361 break;
362
363 case EVEX_OVM:
364 break;
365
366 case EVEX_M128:
367 break;
368
369 case EVEX_DUP:
370 break;
371
372 default:
373 assert(0, "no valid evex tuple_table entry");
374 break;
375 }
376
377 if (vector_len >= AVX_128bit && vector_len <= AVX_512bit) {
378 int disp_factor = tuple_table[cur_tuple_type + mod_idx][vector_len];
379 if ((disp % disp_factor) == 0) {
380 int new_disp = disp / disp_factor;
381 if ((-0x80 <= new_disp && new_disp < 0x80)) {
382 disp = new_disp;
383 }
384 } else {
385 return false;
386 }
387 }
388 }
389 return (-0x80 <= disp && disp < 0x80);
390 }
391
392
393 bool Assembler::emit_compressed_disp_byte(int &disp) {
394 int mod_idx = 0;
395 // We will test if the displacement fits the compressed format and if so
396 // apply the compression to the displacment iff the result is8bit.
397 if (VM_Version::supports_evex() && is_evex_instruction) {
398 switch (tuple_type) {
399 case EVEX_FV:
400 if ((evex_encoding & VEX_W) == VEX_W) {
401 mod_idx += 2 + ((evex_encoding & EVEX_Rb) == EVEX_Rb) ? 1 : 0;
402 } else {
403 mod_idx = ((evex_encoding & EVEX_Rb) == EVEX_Rb) ? 1 : 0;
404 }
405 break;
406
407 case EVEX_HV:
408 mod_idx = ((evex_encoding & EVEX_Rb) == EVEX_Rb) ? 1 : 0;
409 break;
410
411 case EVEX_FVM:
412 break;
413
414 case EVEX_T1S:
415 switch (input_size_in_bits) {
416 case EVEX_8bit:
417 break;
418
419 case EVEX_16bit:
420 mod_idx = 1;
421 break;
422
423 case EVEX_32bit:
424 mod_idx = 2;
425 break;
426
427 case EVEX_64bit:
428 mod_idx = 3;
429 break;
430 }
431 break;
432
433 case EVEX_T1F:
434 case EVEX_T2:
435 case EVEX_T4:
436 mod_idx = (input_size_in_bits == EVEX_64bit) ? 1 : 0;
437 break;
438
439 case EVEX_T8:
440 break;
441
442 case EVEX_HVM:
443 break;
444
445 case EVEX_QVM:
446 break;
447
448 case EVEX_OVM:
449 break;
450
451 case EVEX_M128:
452 break;
453
454 case EVEX_DUP:
455 break;
456
457 default:
458 assert(0, "no valid evex tuple_table entry");
459 break;
460 }
461
462 if (avx_vector_len >= AVX_128bit && avx_vector_len <= AVX_512bit) {
463 int disp_factor = tuple_table[tuple_type + mod_idx][avx_vector_len];
464 if ((disp % disp_factor) == 0) {
465 int new_disp = disp / disp_factor;
466 if (is8bit(new_disp)) {
467 disp = new_disp;
468 }
469 } else {
470 return false;
471 }
472 }
473 }
474 return is8bit(disp);
475 }
476
477
478 void Assembler::emit_operand(Register reg, Register base, Register index,
479 Address::ScaleFactor scale, int disp,
480 RelocationHolder const& rspec,
481 int rip_relative_correction) {
482 relocInfo::relocType rtype = (relocInfo::relocType) rspec.type();
483
484 // Encode the registers as needed in the fields they are used in
485
486 int regenc = encode(reg) << 3;
487 int indexenc = index->is_valid() ? encode(index) << 3 : 0;
488 int baseenc = base->is_valid() ? encode(base) : 0;
489
490 if (base->is_valid()) {
491 if (index->is_valid()) {
492 assert(scale != Address::no_scale, "inconsistent address");
493 // [base + index*scale + disp]
494 if (disp == 0 && rtype == relocInfo::none &&
495 base != rbp LP64_ONLY(&& base != r13)) {
496 // [base + index*scale]
497 // [00 reg 100][ss index base]
498 assert(index != rsp, "illegal addressing mode");
499 emit_int8(0x04 | regenc);
500 emit_int8(scale << 6 | indexenc | baseenc);
501 } else if (emit_compressed_disp_byte(disp) && rtype == relocInfo::none) {
502 // [base + index*scale + imm8]
503 // [01 reg 100][ss index base] imm8
504 assert(index != rsp, "illegal addressing mode");
505 emit_int8(0x44 | regenc);
506 emit_int8(scale << 6 | indexenc | baseenc);
507 emit_int8(disp & 0xFF);
508 } else {
509 // [base + index*scale + disp32]
510 // [10 reg 100][ss index base] disp32
511 assert(index != rsp, "illegal addressing mode");
512 emit_int8(0x84 | regenc);
513 emit_int8(scale << 6 | indexenc | baseenc);
514 emit_data(disp, rspec, disp32_operand);
515 }
516 } else if (base == rsp LP64_ONLY(|| base == r12)) {
517 // [rsp + disp]
518 if (disp == 0 && rtype == relocInfo::none) {
519 // [rsp]
520 // [00 reg 100][00 100 100]
521 emit_int8(0x04 | regenc);
522 emit_int8(0x24);
523 } else if (emit_compressed_disp_byte(disp) && rtype == relocInfo::none) {
524 // [rsp + imm8]
525 // [01 reg 100][00 100 100] disp8
526 emit_int8(0x44 | regenc);
527 emit_int8(0x24);
528 emit_int8(disp & 0xFF);
529 } else {
530 // [rsp + imm32]
531 // [10 reg 100][00 100 100] disp32
532 emit_int8(0x84 | regenc);
533 emit_int8(0x24);
534 emit_data(disp, rspec, disp32_operand);
535 }
536 } else {
537 // [base + disp]
538 assert(base != rsp LP64_ONLY(&& base != r12), "illegal addressing mode");
539 if (disp == 0 && rtype == relocInfo::none &&
540 base != rbp LP64_ONLY(&& base != r13)) {
541 // [base]
542 // [00 reg base]
543 emit_int8(0x00 | regenc | baseenc);
544 } else if (emit_compressed_disp_byte(disp) && rtype == relocInfo::none) {
545 // [base + disp8]
546 // [01 reg base] disp8
547 emit_int8(0x40 | regenc | baseenc);
548 emit_int8(disp & 0xFF);
549 } else {
550 // [base + disp32]
551 // [10 reg base] disp32
552 emit_int8(0x80 | regenc | baseenc);
553 emit_data(disp, rspec, disp32_operand);
554 }
555 }
556 } else {
557 if (index->is_valid()) {
558 assert(scale != Address::no_scale, "inconsistent address");
559 // [index*scale + disp]
560 // [00 reg 100][ss index 101] disp32
561 assert(index != rsp, "illegal addressing mode");
562 emit_int8(0x04 | regenc);
563 emit_int8(scale << 6 | indexenc | 0x05);
564 emit_data(disp, rspec, disp32_operand);
565 } else if (rtype != relocInfo::none ) {
566 // [disp] (64bit) RIP-RELATIVE (32bit) abs
567 // [00 000 101] disp32
568
569 emit_int8(0x05 | regenc);
570 // Note that the RIP-rel. correction applies to the generated
571 // disp field, but _not_ to the target address in the rspec.
572
573 // disp was created by converting the target address minus the pc
574 // at the start of the instruction. That needs more correction here.
575 // intptr_t disp = target - next_ip;
576 assert(inst_mark() != NULL, "must be inside InstructionMark");
577 address next_ip = pc() + sizeof(int32_t) + rip_relative_correction;
578 int64_t adjusted = disp;
579 // Do rip-rel adjustment for 64bit
580 LP64_ONLY(adjusted -= (next_ip - inst_mark()));
581 assert(is_simm32(adjusted),
582 "must be 32bit offset (RIP relative address)");
583 emit_data((int32_t) adjusted, rspec, disp32_operand);
584
585 } else {
586 // 32bit never did this, did everything as the rip-rel/disp code above
587 // [disp] ABSOLUTE
588 // [00 reg 100][00 100 101] disp32
589 emit_int8(0x04 | regenc);
590 emit_int8(0x25);
591 emit_data(disp, rspec, disp32_operand);
592 }
593 }
594 is_evex_instruction = false;
595 }
596
597 void Assembler::emit_operand(XMMRegister reg, Register base, Register index,
598 Address::ScaleFactor scale, int disp,
599 RelocationHolder const& rspec) {
600 if (UseAVX > 2) {
601 int xreg_enc = reg->encoding();
602 if (xreg_enc > 15) {
603 XMMRegister new_reg = as_XMMRegister(xreg_enc & 0xf);
604 emit_operand((Register)new_reg, base, index, scale, disp, rspec);
605 return;
606 }
607 }
608 emit_operand((Register)reg, base, index, scale, disp, rspec);
609 }
610
611 // Secret local extension to Assembler::WhichOperand:
612 #define end_pc_operand (_WhichOperand_limit)
613
614 address Assembler::locate_operand(address inst, WhichOperand which) {
615 // Decode the given instruction, and return the address of
616 // an embedded 32-bit operand word.
617
618 // If "which" is disp32_operand, selects the displacement portion
619 // of an effective address specifier.
620 // If "which" is imm64_operand, selects the trailing immediate constant.
621 // If "which" is call32_operand, selects the displacement of a call or jump.
622 // Caller is responsible for ensuring that there is such an operand,
623 // and that it is 32/64 bits wide.
624
625 // If "which" is end_pc_operand, find the end of the instruction.
626
627 address ip = inst;
628 bool is_64bit = false;
629
630 debug_only(bool has_disp32 = false);
631 int tail_size = 0; // other random bytes (#32, #16, etc.) at end of insn
632
633 again_after_prefix:
634 switch (0xFF & *ip++) {
635
636 // These convenience macros generate groups of "case" labels for the switch.
637 #define REP4(x) (x)+0: case (x)+1: case (x)+2: case (x)+3
638 #define REP8(x) (x)+0: case (x)+1: case (x)+2: case (x)+3: \
639 case (x)+4: case (x)+5: case (x)+6: case (x)+7
640 #define REP16(x) REP8((x)+0): \
641 case REP8((x)+8)
642
643 case CS_segment:
644 case SS_segment:
645 case DS_segment:
646 case ES_segment:
647 case FS_segment:
648 case GS_segment:
649 // Seems dubious
650 LP64_ONLY(assert(false, "shouldn't have that prefix"));
651 assert(ip == inst+1, "only one prefix allowed");
652 goto again_after_prefix;
653
654 case 0x67:
655 case REX:
656 case REX_B:
657 case REX_X:
658 case REX_XB:
659 case REX_R:
660 case REX_RB:
661 case REX_RX:
662 case REX_RXB:
663 NOT_LP64(assert(false, "64bit prefixes"));
664 goto again_after_prefix;
665
666 case REX_W:
667 case REX_WB:
668 case REX_WX:
669 case REX_WXB:
670 case REX_WR:
671 case REX_WRB:
672 case REX_WRX:
673 case REX_WRXB:
674 NOT_LP64(assert(false, "64bit prefixes"));
675 is_64bit = true;
676 goto again_after_prefix;
677
678 case 0xFF: // pushq a; decl a; incl a; call a; jmp a
679 case 0x88: // movb a, r
680 case 0x89: // movl a, r
681 case 0x8A: // movb r, a
682 case 0x8B: // movl r, a
683 case 0x8F: // popl a
684 debug_only(has_disp32 = true);
685 break;
686
687 case 0x68: // pushq #32
688 if (which == end_pc_operand) {
689 return ip + 4;
690 }
691 assert(which == imm_operand && !is_64bit, "pushl has no disp32 or 64bit immediate");
692 return ip; // not produced by emit_operand
693
694 case 0x66: // movw ... (size prefix)
695 again_after_size_prefix2:
696 switch (0xFF & *ip++) {
697 case REX:
698 case REX_B:
699 case REX_X:
700 case REX_XB:
701 case REX_R:
702 case REX_RB:
703 case REX_RX:
704 case REX_RXB:
705 case REX_W:
706 case REX_WB:
707 case REX_WX:
708 case REX_WXB:
709 case REX_WR:
710 case REX_WRB:
711 case REX_WRX:
712 case REX_WRXB:
713 NOT_LP64(assert(false, "64bit prefix found"));
714 goto again_after_size_prefix2;
715 case 0x8B: // movw r, a
716 case 0x89: // movw a, r
717 debug_only(has_disp32 = true);
718 break;
719 case 0xC7: // movw a, #16
720 debug_only(has_disp32 = true);
721 tail_size = 2; // the imm16
722 break;
723 case 0x0F: // several SSE/SSE2 variants
724 ip--; // reparse the 0x0F
725 goto again_after_prefix;
726 default:
727 ShouldNotReachHere();
728 }
729 break;
730
731 case REP8(0xB8): // movl/q r, #32/#64(oop?)
732 if (which == end_pc_operand) return ip + (is_64bit ? 8 : 4);
733 // these asserts are somewhat nonsensical
734 #ifndef _LP64
735 assert(which == imm_operand || which == disp32_operand,
736 err_msg("which %d is_64_bit %d ip " INTPTR_FORMAT, which, is_64bit, p2i(ip)));
737 #else
738 assert((which == call32_operand || which == imm_operand) && is_64bit ||
739 which == narrow_oop_operand && !is_64bit,
740 err_msg("which %d is_64_bit %d ip " INTPTR_FORMAT, which, is_64bit, p2i(ip)));
741 #endif // _LP64
742 return ip;
743
744 case 0x69: // imul r, a, #32
745 case 0xC7: // movl a, #32(oop?)
746 tail_size = 4;
747 debug_only(has_disp32 = true); // has both kinds of operands!
748 break;
749
750 case 0x0F: // movx..., etc.
751 switch (0xFF & *ip++) {
752 case 0x3A: // pcmpestri
753 tail_size = 1;
754 case 0x38: // ptest, pmovzxbw
755 ip++; // skip opcode
756 debug_only(has_disp32 = true); // has both kinds of operands!
757 break;
758
759 case 0x70: // pshufd r, r/a, #8
760 debug_only(has_disp32 = true); // has both kinds of operands!
761 case 0x73: // psrldq r, #8
762 tail_size = 1;
763 break;
764
765 case 0x12: // movlps
766 case 0x28: // movaps
767 case 0x2E: // ucomiss
768 case 0x2F: // comiss
769 case 0x54: // andps
770 case 0x55: // andnps
771 case 0x56: // orps
772 case 0x57: // xorps
773 case 0x6E: // movd
774 case 0x7E: // movd
775 case 0xAE: // ldmxcsr, stmxcsr, fxrstor, fxsave, clflush
776 debug_only(has_disp32 = true);
777 break;
778
779 case 0xAD: // shrd r, a, %cl
780 case 0xAF: // imul r, a
781 case 0xBE: // movsbl r, a (movsxb)
782 case 0xBF: // movswl r, a (movsxw)
783 case 0xB6: // movzbl r, a (movzxb)
784 case 0xB7: // movzwl r, a (movzxw)
785 case REP16(0x40): // cmovl cc, r, a
786 case 0xB0: // cmpxchgb
787 case 0xB1: // cmpxchg
788 case 0xC1: // xaddl
789 case 0xC7: // cmpxchg8
790 case REP16(0x90): // setcc a
791 debug_only(has_disp32 = true);
792 // fall out of the switch to decode the address
793 break;
794
795 case 0xC4: // pinsrw r, a, #8
796 debug_only(has_disp32 = true);
797 case 0xC5: // pextrw r, r, #8
798 tail_size = 1; // the imm8
799 break;
800
801 case 0xAC: // shrd r, a, #8
802 debug_only(has_disp32 = true);
803 tail_size = 1; // the imm8
804 break;
805
806 case REP16(0x80): // jcc rdisp32
807 if (which == end_pc_operand) return ip + 4;
808 assert(which == call32_operand, "jcc has no disp32 or imm");
809 return ip;
810 default:
811 ShouldNotReachHere();
812 }
813 break;
814
815 case 0x81: // addl a, #32; addl r, #32
816 // also: orl, adcl, sbbl, andl, subl, xorl, cmpl
817 // on 32bit in the case of cmpl, the imm might be an oop
818 tail_size = 4;
819 debug_only(has_disp32 = true); // has both kinds of operands!
820 break;
821
822 case 0x83: // addl a, #8; addl r, #8
823 // also: orl, adcl, sbbl, andl, subl, xorl, cmpl
824 debug_only(has_disp32 = true); // has both kinds of operands!
825 tail_size = 1;
826 break;
827
828 case 0x9B:
829 switch (0xFF & *ip++) {
830 case 0xD9: // fnstcw a
831 debug_only(has_disp32 = true);
832 break;
833 default:
834 ShouldNotReachHere();
835 }
836 break;
837
838 case REP4(0x00): // addb a, r; addl a, r; addb r, a; addl r, a
839 case REP4(0x10): // adc...
840 case REP4(0x20): // and...
841 case REP4(0x30): // xor...
842 case REP4(0x08): // or...
843 case REP4(0x18): // sbb...
844 case REP4(0x28): // sub...
845 case 0xF7: // mull a
846 case 0x8D: // lea r, a
847 case 0x87: // xchg r, a
848 case REP4(0x38): // cmp...
849 case 0x85: // test r, a
850 debug_only(has_disp32 = true); // has both kinds of operands!
851 break;
852
853 case 0xC1: // sal a, #8; sar a, #8; shl a, #8; shr a, #8
854 case 0xC6: // movb a, #8
855 case 0x80: // cmpb a, #8
856 case 0x6B: // imul r, a, #8
857 debug_only(has_disp32 = true); // has both kinds of operands!
858 tail_size = 1; // the imm8
859 break;
860
861 case 0xC4: // VEX_3bytes
862 case 0xC5: // VEX_2bytes
863 assert((UseAVX > 0), "shouldn't have VEX prefix");
864 assert(ip == inst+1, "no prefixes allowed");
865 // C4 and C5 are also used as opcodes for PINSRW and PEXTRW instructions
866 // but they have prefix 0x0F and processed when 0x0F processed above.
867 //
868 // In 32-bit mode the VEX first byte C4 and C5 alias onto LDS and LES
869 // instructions (these instructions are not supported in 64-bit mode).
870 // To distinguish them bits [7:6] are set in the VEX second byte since
871 // ModRM byte can not be of the form 11xxxxxx in 32-bit mode. To set
872 // those VEX bits REX and vvvv bits are inverted.
873 //
874 // Fortunately C2 doesn't generate these instructions so we don't need
875 // to check for them in product version.
876
877 // Check second byte
878 NOT_LP64(assert((0xC0 & *ip) == 0xC0, "shouldn't have LDS and LES instructions"));
879
880 // First byte
881 if ((0xFF & *inst) == VEX_3bytes) {
882 ip++; // third byte
883 is_64bit = ((VEX_W & *ip) == VEX_W);
884 }
885 ip++; // opcode
886 // To find the end of instruction (which == end_pc_operand).
887 switch (0xFF & *ip) {
888 case 0x61: // pcmpestri r, r/a, #8
889 case 0x70: // pshufd r, r/a, #8
890 case 0x73: // psrldq r, #8
891 tail_size = 1; // the imm8
892 break;
893 default:
894 break;
895 }
896 ip++; // skip opcode
897 debug_only(has_disp32 = true); // has both kinds of operands!
898 break;
899
900 case 0x62: // EVEX_4bytes
901 assert((UseAVX > 0), "shouldn't have EVEX prefix");
902 assert(ip == inst+1, "no prefixes allowed");
903 // no EVEX collisions, all instructions that have 0x62 opcodes
904 // have EVEX versions and are subopcodes of 0x66
905 ip++; // skip P0 and exmaine W in P1
906 is_64bit = ((VEX_W & *ip) == VEX_W);
907 ip++; // move to P2
908 ip++; // skip P2, move to opcode
909 // To find the end of instruction (which == end_pc_operand).
910 switch (0xFF & *ip) {
911 case 0x61: // pcmpestri r, r/a, #8
912 case 0x70: // pshufd r, r/a, #8
913 case 0x73: // psrldq r, #8
914 tail_size = 1; // the imm8
915 break;
916 default:
917 break;
918 }
919 ip++; // skip opcode
920 debug_only(has_disp32 = true); // has both kinds of operands!
921 break;
922
923 case 0xD1: // sal a, 1; sar a, 1; shl a, 1; shr a, 1
924 case 0xD3: // sal a, %cl; sar a, %cl; shl a, %cl; shr a, %cl
925 case 0xD9: // fld_s a; fst_s a; fstp_s a; fldcw a
926 case 0xDD: // fld_d a; fst_d a; fstp_d a
927 case 0xDB: // fild_s a; fistp_s a; fld_x a; fstp_x a
928 case 0xDF: // fild_d a; fistp_d a
929 case 0xD8: // fadd_s a; fsubr_s a; fmul_s a; fdivr_s a; fcomp_s a
930 case 0xDC: // fadd_d a; fsubr_d a; fmul_d a; fdivr_d a; fcomp_d a
931 case 0xDE: // faddp_d a; fsubrp_d a; fmulp_d a; fdivrp_d a; fcompp_d a
932 debug_only(has_disp32 = true);
933 break;
934
935 case 0xE8: // call rdisp32
936 case 0xE9: // jmp rdisp32
937 if (which == end_pc_operand) return ip + 4;
938 assert(which == call32_operand, "call has no disp32 or imm");
939 return ip;
940
941 case 0xF0: // Lock
942 assert(os::is_MP(), "only on MP");
943 goto again_after_prefix;
944
945 case 0xF3: // For SSE
946 case 0xF2: // For SSE2
947 switch (0xFF & *ip++) {
948 case REX:
949 case REX_B:
950 case REX_X:
951 case REX_XB:
952 case REX_R:
953 case REX_RB:
954 case REX_RX:
955 case REX_RXB:
956 case REX_W:
957 case REX_WB:
958 case REX_WX:
959 case REX_WXB:
960 case REX_WR:
961 case REX_WRB:
962 case REX_WRX:
963 case REX_WRXB:
964 NOT_LP64(assert(false, "found 64bit prefix"));
965 ip++;
966 default:
967 ip++;
968 }
969 debug_only(has_disp32 = true); // has both kinds of operands!
970 break;
971
972 default:
973 ShouldNotReachHere();
974
975 #undef REP8
976 #undef REP16
977 }
978
979 assert(which != call32_operand, "instruction is not a call, jmp, or jcc");
980 #ifdef _LP64
981 assert(which != imm_operand, "instruction is not a movq reg, imm64");
982 #else
983 // assert(which != imm_operand || has_imm32, "instruction has no imm32 field");
984 assert(which != imm_operand || has_disp32, "instruction has no imm32 field");
985 #endif // LP64
986 assert(which != disp32_operand || has_disp32, "instruction has no disp32 field");
987
988 // parse the output of emit_operand
989 int op2 = 0xFF & *ip++;
990 int base = op2 & 0x07;
991 int op3 = -1;
992 const int b100 = 4;
993 const int b101 = 5;
994 if (base == b100 && (op2 >> 6) != 3) {
995 op3 = 0xFF & *ip++;
996 base = op3 & 0x07; // refetch the base
997 }
998 // now ip points at the disp (if any)
999
1000 switch (op2 >> 6) {
1001 case 0:
1002 // [00 reg 100][ss index base]
1003 // [00 reg 100][00 100 esp]
1004 // [00 reg base]
1005 // [00 reg 100][ss index 101][disp32]
1006 // [00 reg 101] [disp32]
1007
1008 if (base == b101) {
1009 if (which == disp32_operand)
1010 return ip; // caller wants the disp32
1011 ip += 4; // skip the disp32
1012 }
1013 break;
1014
1015 case 1:
1016 // [01 reg 100][ss index base][disp8]
1017 // [01 reg 100][00 100 esp][disp8]
1018 // [01 reg base] [disp8]
1019 ip += 1; // skip the disp8
1020 break;
1021
1022 case 2:
1023 // [10 reg 100][ss index base][disp32]
1024 // [10 reg 100][00 100 esp][disp32]
1025 // [10 reg base] [disp32]
1026 if (which == disp32_operand)
1027 return ip; // caller wants the disp32
1028 ip += 4; // skip the disp32
1029 break;
1030
1031 case 3:
1032 // [11 reg base] (not a memory addressing mode)
1033 break;
1034 }
1035
1036 if (which == end_pc_operand) {
1037 return ip + tail_size;
1038 }
1039
1040 #ifdef _LP64
1041 assert(which == narrow_oop_operand && !is_64bit, "instruction is not a movl adr, imm32");
1042 #else
1043 assert(which == imm_operand, "instruction has only an imm field");
1044 #endif // LP64
1045 return ip;
1046 }
1047
1048 address Assembler::locate_next_instruction(address inst) {
1049 // Secretly share code with locate_operand:
1050 return locate_operand(inst, end_pc_operand);
1051 }
1052
1053
1054 #ifdef ASSERT
1055 void Assembler::check_relocation(RelocationHolder const& rspec, int format) {
1056 address inst = inst_mark();
1057 assert(inst != NULL && inst < pc(), "must point to beginning of instruction");
1058 address opnd;
1059
1060 Relocation* r = rspec.reloc();
1061 if (r->type() == relocInfo::none) {
1062 return;
1063 } else if (r->is_call() || format == call32_operand) {
1064 // assert(format == imm32_operand, "cannot specify a nonzero format");
1065 opnd = locate_operand(inst, call32_operand);
1066 } else if (r->is_data()) {
1067 assert(format == imm_operand || format == disp32_operand
1068 LP64_ONLY(|| format == narrow_oop_operand), "format ok");
1069 opnd = locate_operand(inst, (WhichOperand)format);
1070 } else {
1071 assert(format == imm_operand, "cannot specify a format");
1072 return;
1073 }
1074 assert(opnd == pc(), "must put operand where relocs can find it");
1075 }
1076 #endif // ASSERT
1077
1078 void Assembler::emit_operand32(Register reg, Address adr) {
1079 assert(reg->encoding() < 8, "no extended registers");
1080 assert(!adr.base_needs_rex() && !adr.index_needs_rex(), "no extended registers");
1081 emit_operand(reg, adr._base, adr._index, adr._scale, adr._disp,
1082 adr._rspec);
1083 }
1084
1085 void Assembler::emit_operand(Register reg, Address adr,
1086 int rip_relative_correction) {
1087 emit_operand(reg, adr._base, adr._index, adr._scale, adr._disp,
1088 adr._rspec,
1089 rip_relative_correction);
1090 }
1091
1092 void Assembler::emit_operand(XMMRegister reg, Address adr) {
1093 emit_operand(reg, adr._base, adr._index, adr._scale, adr._disp,
1094 adr._rspec);
1095 }
1096
1097 // MMX operations
1098 void Assembler::emit_operand(MMXRegister reg, Address adr) {
1099 assert(!adr.base_needs_rex() && !adr.index_needs_rex(), "no extended registers");
1100 emit_operand((Register)reg, adr._base, adr._index, adr._scale, adr._disp, adr._rspec);
1101 }
1102
1103 // work around gcc (3.2.1-7a) bug
1104 void Assembler::emit_operand(Address adr, MMXRegister reg) {
1105 assert(!adr.base_needs_rex() && !adr.index_needs_rex(), "no extended registers");
1106 emit_operand((Register)reg, adr._base, adr._index, adr._scale, adr._disp, adr._rspec);
1107 }
1108
1109
1110 void Assembler::emit_farith(int b1, int b2, int i) {
1111 assert(isByte(b1) && isByte(b2), "wrong opcode");
1112 assert(0 <= i && i < 8, "illegal stack offset");
1113 emit_int8(b1);
1114 emit_int8(b2 + i);
1115 }
1116
1117
1118 // Now the Assembler instructions (identical for 32/64 bits)
1119
1120 void Assembler::adcl(Address dst, int32_t imm32) {
1121 InstructionMark im(this);
1122 prefix(dst);
1123 emit_arith_operand(0x81, rdx, dst, imm32);
1124 }
1125
1126 void Assembler::adcl(Address dst, Register src) {
1127 InstructionMark im(this);
1128 prefix(dst, src);
1129 emit_int8(0x11);
1130 emit_operand(src, dst);
1131 }
1132
1133 void Assembler::adcl(Register dst, int32_t imm32) {
1134 prefix(dst);
1135 emit_arith(0x81, 0xD0, dst, imm32);
1136 }
1137
1138 void Assembler::adcl(Register dst, Address src) {
1139 InstructionMark im(this);
1140 prefix(src, dst);
1141 emit_int8(0x13);
1142 emit_operand(dst, src);
1143 }
1144
1145 void Assembler::adcl(Register dst, Register src) {
1146 (void) prefix_and_encode(dst->encoding(), src->encoding());
1147 emit_arith(0x13, 0xC0, dst, src);
1148 }
1149
1150 void Assembler::addl(Address dst, int32_t imm32) {
1151 InstructionMark im(this);
1152 prefix(dst);
1153 emit_arith_operand(0x81, rax, dst, imm32);
1154 }
1155
1156 void Assembler::addl(Address dst, Register src) {
1157 InstructionMark im(this);
1158 prefix(dst, src);
1159 emit_int8(0x01);
1160 emit_operand(src, dst);
1161 }
1162
1163 void Assembler::addl(Register dst, int32_t imm32) {
1164 prefix(dst);
1165 emit_arith(0x81, 0xC0, dst, imm32);
1166 }
1167
1168 void Assembler::addl(Register dst, Address src) {
1169 InstructionMark im(this);
1170 prefix(src, dst);
1171 emit_int8(0x03);
1172 emit_operand(dst, src);
1173 }
1174
1175 void Assembler::addl(Register dst, Register src) {
1176 (void) prefix_and_encode(dst->encoding(), src->encoding());
1177 emit_arith(0x03, 0xC0, dst, src);
1178 }
1179
1180 void Assembler::addr_nop_4() {
1181 assert(UseAddressNop, "no CPU support");
1182 // 4 bytes: NOP DWORD PTR [EAX+0]
1183 emit_int8(0x0F);
1184 emit_int8(0x1F);
1185 emit_int8(0x40); // emit_rm(cbuf, 0x1, EAX_enc, EAX_enc);
1186 emit_int8(0); // 8-bits offset (1 byte)
1187 }
1188
1189 void Assembler::addr_nop_5() {
1190 assert(UseAddressNop, "no CPU support");
1191 // 5 bytes: NOP DWORD PTR [EAX+EAX*0+0] 8-bits offset
1192 emit_int8(0x0F);
1193 emit_int8(0x1F);
1194 emit_int8(0x44); // emit_rm(cbuf, 0x1, EAX_enc, 0x4);
1195 emit_int8(0x00); // emit_rm(cbuf, 0x0, EAX_enc, EAX_enc);
1196 emit_int8(0); // 8-bits offset (1 byte)
1197 }
1198
1199 void Assembler::addr_nop_7() {
1200 assert(UseAddressNop, "no CPU support");
1201 // 7 bytes: NOP DWORD PTR [EAX+0] 32-bits offset
1202 emit_int8(0x0F);
1203 emit_int8(0x1F);
1204 emit_int8((unsigned char)0x80);
1205 // emit_rm(cbuf, 0x2, EAX_enc, EAX_enc);
1206 emit_int32(0); // 32-bits offset (4 bytes)
1207 }
1208
1209 void Assembler::addr_nop_8() {
1210 assert(UseAddressNop, "no CPU support");
1211 // 8 bytes: NOP DWORD PTR [EAX+EAX*0+0] 32-bits offset
1212 emit_int8(0x0F);
1213 emit_int8(0x1F);
1214 emit_int8((unsigned char)0x84);
1215 // emit_rm(cbuf, 0x2, EAX_enc, 0x4);
1216 emit_int8(0x00); // emit_rm(cbuf, 0x0, EAX_enc, EAX_enc);
1217 emit_int32(0); // 32-bits offset (4 bytes)
1218 }
1219
1220 void Assembler::addsd(XMMRegister dst, XMMRegister src) {
1221 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1222 if (VM_Version::supports_evex()) {
1223 emit_simd_arith_q(0x58, dst, src, VEX_SIMD_F2);
1224 } else {
1225 emit_simd_arith(0x58, dst, src, VEX_SIMD_F2);
1226 }
1227 }
1228
1229 void Assembler::addsd(XMMRegister dst, Address src) {
1230 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1231 if (VM_Version::supports_evex()) {
1232 tuple_type = EVEX_T1S;
1233 input_size_in_bits = EVEX_64bit;
1234 emit_simd_arith_q(0x58, dst, src, VEX_SIMD_F2);
1235 } else {
1236 emit_simd_arith(0x58, dst, src, VEX_SIMD_F2);
1237 }
1238 }
1239
1240 void Assembler::addss(XMMRegister dst, XMMRegister src) {
1241 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1242 emit_simd_arith(0x58, dst, src, VEX_SIMD_F3);
1243 }
1244
1245 void Assembler::addss(XMMRegister dst, Address src) {
1246 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1247 if (VM_Version::supports_evex()) {
1248 tuple_type = EVEX_T1S;
1249 input_size_in_bits = EVEX_32bit;
1250 }
1251 emit_simd_arith(0x58, dst, src, VEX_SIMD_F3);
1252 }
1253
1254 void Assembler::aesdec(XMMRegister dst, Address src) {
1255 assert(VM_Version::supports_aes(), "");
1256 InstructionMark im(this);
1257 simd_prefix(dst, dst, src, VEX_SIMD_66, false,
1258 VEX_OPCODE_0F_38, false, AVX_128bit, true);
1259 emit_int8((unsigned char)0xDE);
1260 emit_operand(dst, src);
1261 }
1262
1263 void Assembler::aesdec(XMMRegister dst, XMMRegister src) {
1264 assert(VM_Version::supports_aes(), "");
1265 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, false,
1266 VEX_OPCODE_0F_38, false, AVX_128bit, true);
1267 emit_int8((unsigned char)0xDE);
1268 emit_int8(0xC0 | encode);
1269 }
1270
1271 void Assembler::aesdeclast(XMMRegister dst, Address src) {
1272 assert(VM_Version::supports_aes(), "");
1273 InstructionMark im(this);
1274 simd_prefix(dst, dst, src, VEX_SIMD_66, false,
1275 VEX_OPCODE_0F_38, false, AVX_128bit, true);
1276 emit_int8((unsigned char)0xDF);
1277 emit_operand(dst, src);
1278 }
1279
1280 void Assembler::aesdeclast(XMMRegister dst, XMMRegister src) {
1281 assert(VM_Version::supports_aes(), "");
1282 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, false,
1283 VEX_OPCODE_0F_38, false, AVX_128bit, true);
1284 emit_int8((unsigned char)0xDF);
1285 emit_int8((unsigned char)(0xC0 | encode));
1286 }
1287
1288 void Assembler::aesenc(XMMRegister dst, Address src) {
1289 assert(VM_Version::supports_aes(), "");
1290 InstructionMark im(this);
1291 simd_prefix(dst, dst, src, VEX_SIMD_66, false,
1292 VEX_OPCODE_0F_38, false, AVX_128bit, true);
1293 emit_int8((unsigned char)0xDC);
1294 emit_operand(dst, src);
1295 }
1296
1297 void Assembler::aesenc(XMMRegister dst, XMMRegister src) {
1298 assert(VM_Version::supports_aes(), "");
1299 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, false,
1300 VEX_OPCODE_0F_38, false, AVX_128bit, true);
1301 emit_int8((unsigned char)0xDC);
1302 emit_int8(0xC0 | encode);
1303 }
1304
1305 void Assembler::aesenclast(XMMRegister dst, Address src) {
1306 assert(VM_Version::supports_aes(), "");
1307 InstructionMark im(this);
1308 simd_prefix(dst, dst, src, VEX_SIMD_66, false,
1309 VEX_OPCODE_0F_38, false, AVX_128bit, true);
1310 emit_int8((unsigned char)0xDD);
1311 emit_operand(dst, src);
1312 }
1313
1314 void Assembler::aesenclast(XMMRegister dst, XMMRegister src) {
1315 assert(VM_Version::supports_aes(), "");
1316 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, false,
1317 VEX_OPCODE_0F_38, false, AVX_128bit, true);
1318 emit_int8((unsigned char)0xDD);
1319 emit_int8((unsigned char)(0xC0 | encode));
1320 }
1321
1322
1323 void Assembler::andl(Address dst, int32_t imm32) {
1324 InstructionMark im(this);
1325 prefix(dst);
1326 emit_int8((unsigned char)0x81);
1327 emit_operand(rsp, dst, 4);
1328 emit_int32(imm32);
1329 }
1330
1331 void Assembler::andl(Register dst, int32_t imm32) {
1332 prefix(dst);
1333 emit_arith(0x81, 0xE0, dst, imm32);
1334 }
1335
1336 void Assembler::andl(Register dst, Address src) {
1337 InstructionMark im(this);
1338 prefix(src, dst);
1339 emit_int8(0x23);
1340 emit_operand(dst, src);
1341 }
1342
1343 void Assembler::andl(Register dst, Register src) {
1344 (void) prefix_and_encode(dst->encoding(), src->encoding());
1345 emit_arith(0x23, 0xC0, dst, src);
1346 }
1347
1348 void Assembler::andnl(Register dst, Register src1, Register src2) {
1349 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1350 int encode = vex_prefix_0F38_and_encode(dst, src1, src2, false);
1351 emit_int8((unsigned char)0xF2);
1352 emit_int8((unsigned char)(0xC0 | encode));
1353 }
1354
1355 void Assembler::andnl(Register dst, Register src1, Address src2) {
1356 InstructionMark im(this);
1357 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1358 vex_prefix_0F38(dst, src1, src2, false);
1359 emit_int8((unsigned char)0xF2);
1360 emit_operand(dst, src2);
1361 }
1362
1363 void Assembler::bsfl(Register dst, Register src) {
1364 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1365 emit_int8(0x0F);
1366 emit_int8((unsigned char)0xBC);
1367 emit_int8((unsigned char)(0xC0 | encode));
1368 }
1369
1370 void Assembler::bsrl(Register dst, Register src) {
1371 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1372 emit_int8(0x0F);
1373 emit_int8((unsigned char)0xBD);
1374 emit_int8((unsigned char)(0xC0 | encode));
1375 }
1376
1377 void Assembler::bswapl(Register reg) { // bswap
1378 int encode = prefix_and_encode(reg->encoding());
1379 emit_int8(0x0F);
1380 emit_int8((unsigned char)(0xC8 | encode));
1381 }
1382
1383 void Assembler::blsil(Register dst, Register src) {
1384 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1385 int encode = vex_prefix_0F38_and_encode(rbx, dst, src, false);
1386 emit_int8((unsigned char)0xF3);
1387 emit_int8((unsigned char)(0xC0 | encode));
1388 }
1389
1390 void Assembler::blsil(Register dst, Address src) {
1391 InstructionMark im(this);
1392 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1393 vex_prefix_0F38(rbx, dst, src, false);
1394 emit_int8((unsigned char)0xF3);
1395 emit_operand(rbx, src);
1396 }
1397
1398 void Assembler::blsmskl(Register dst, Register src) {
1399 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1400 int encode = vex_prefix_0F38_and_encode(rdx, dst, src, false);
1401 emit_int8((unsigned char)0xF3);
1402 emit_int8((unsigned char)(0xC0 | encode));
1403 }
1404
1405 void Assembler::blsmskl(Register dst, Address src) {
1406 InstructionMark im(this);
1407 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1408 vex_prefix_0F38(rdx, dst, src, false);
1409 emit_int8((unsigned char)0xF3);
1410 emit_operand(rdx, src);
1411 }
1412
1413 void Assembler::blsrl(Register dst, Register src) {
1414 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1415 int encode = vex_prefix_0F38_and_encode(rcx, dst, src, false);
1416 emit_int8((unsigned char)0xF3);
1417 emit_int8((unsigned char)(0xC0 | encode));
1418 }
1419
1420 void Assembler::blsrl(Register dst, Address src) {
1421 InstructionMark im(this);
1422 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1423 vex_prefix_0F38(rcx, dst, src, false);
1424 emit_int8((unsigned char)0xF3);
1425 emit_operand(rcx, src);
1426 }
1427
1428 void Assembler::call(Label& L, relocInfo::relocType rtype) {
1429 // suspect disp32 is always good
1430 int operand = LP64_ONLY(disp32_operand) NOT_LP64(imm_operand);
1431
1432 if (L.is_bound()) {
1433 const int long_size = 5;
1434 int offs = (int)( target(L) - pc() );
1435 assert(offs <= 0, "assembler error");
1436 InstructionMark im(this);
1437 // 1110 1000 #32-bit disp
1438 emit_int8((unsigned char)0xE8);
1439 emit_data(offs - long_size, rtype, operand);
1440 } else {
1441 InstructionMark im(this);
1442 // 1110 1000 #32-bit disp
1443 L.add_patch_at(code(), locator());
1444
1445 emit_int8((unsigned char)0xE8);
1446 emit_data(int(0), rtype, operand);
1447 }
1448 }
1449
1450 void Assembler::call(Register dst) {
1451 int encode = prefix_and_encode(dst->encoding());
1452 emit_int8((unsigned char)0xFF);
1453 emit_int8((unsigned char)(0xD0 | encode));
1454 }
1455
1456
1457 void Assembler::call(Address adr) {
1458 InstructionMark im(this);
1459 prefix(adr);
1460 emit_int8((unsigned char)0xFF);
1461 emit_operand(rdx, adr);
1462 }
1463
1464 void Assembler::call_literal(address entry, RelocationHolder const& rspec) {
1465 assert(entry != NULL, "call most probably wrong");
1466 InstructionMark im(this);
1467 emit_int8((unsigned char)0xE8);
1468 intptr_t disp = entry - (pc() + sizeof(int32_t));
1469 assert(is_simm32(disp), "must be 32bit offset (call2)");
1470 // Technically, should use call32_operand, but this format is
1471 // implied by the fact that we're emitting a call instruction.
1472
1473 int operand = LP64_ONLY(disp32_operand) NOT_LP64(call32_operand);
1474 emit_data((int) disp, rspec, operand);
1475 }
1476
1477 void Assembler::cdql() {
1478 emit_int8((unsigned char)0x99);
1479 }
1480
1481 void Assembler::cld() {
1482 emit_int8((unsigned char)0xFC);
1483 }
1484
1485 void Assembler::cmovl(Condition cc, Register dst, Register src) {
1486 NOT_LP64(guarantee(VM_Version::supports_cmov(), "illegal instruction"));
1487 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1488 emit_int8(0x0F);
1489 emit_int8(0x40 | cc);
1490 emit_int8((unsigned char)(0xC0 | encode));
1491 }
1492
1493
1494 void Assembler::cmovl(Condition cc, Register dst, Address src) {
1495 NOT_LP64(guarantee(VM_Version::supports_cmov(), "illegal instruction"));
1496 prefix(src, dst);
1497 emit_int8(0x0F);
1498 emit_int8(0x40 | cc);
1499 emit_operand(dst, src);
1500 }
1501
1502 void Assembler::cmpb(Address dst, int imm8) {
1503 InstructionMark im(this);
1504 prefix(dst);
1505 emit_int8((unsigned char)0x80);
1506 emit_operand(rdi, dst, 1);
1507 emit_int8(imm8);
1508 }
1509
1510 void Assembler::cmpl(Address dst, int32_t imm32) {
1511 InstructionMark im(this);
1512 prefix(dst);
1513 emit_int8((unsigned char)0x81);
1514 emit_operand(rdi, dst, 4);
1515 emit_int32(imm32);
1516 }
1517
1518 void Assembler::cmpl(Register dst, int32_t imm32) {
1519 prefix(dst);
1520 emit_arith(0x81, 0xF8, dst, imm32);
1521 }
1522
1523 void Assembler::cmpl(Register dst, Register src) {
1524 (void) prefix_and_encode(dst->encoding(), src->encoding());
1525 emit_arith(0x3B, 0xC0, dst, src);
1526 }
1527
1528
1529 void Assembler::cmpl(Register dst, Address src) {
1530 InstructionMark im(this);
1531 prefix(src, dst);
1532 emit_int8((unsigned char)0x3B);
1533 emit_operand(dst, src);
1534 }
1535
1536 void Assembler::cmpw(Address dst, int imm16) {
1537 InstructionMark im(this);
1538 assert(!dst.base_needs_rex() && !dst.index_needs_rex(), "no extended registers");
1539 emit_int8(0x66);
1540 emit_int8((unsigned char)0x81);
1541 emit_operand(rdi, dst, 2);
1542 emit_int16(imm16);
1543 }
1544
1545 // The 32-bit cmpxchg compares the value at adr with the contents of rax,
1546 // and stores reg into adr if so; otherwise, the value at adr is loaded into rax,.
1547 // The ZF is set if the compared values were equal, and cleared otherwise.
1548 void Assembler::cmpxchgl(Register reg, Address adr) { // cmpxchg
1549 InstructionMark im(this);
1550 prefix(adr, reg);
1551 emit_int8(0x0F);
1552 emit_int8((unsigned char)0xB1);
1553 emit_operand(reg, adr);
1554 }
1555
1556 // The 8-bit cmpxchg compares the value at adr with the contents of rax,
1557 // and stores reg into adr if so; otherwise, the value at adr is loaded into rax,.
1558 // The ZF is set if the compared values were equal, and cleared otherwise.
1559 void Assembler::cmpxchgb(Register reg, Address adr) { // cmpxchg
1560 InstructionMark im(this);
1561 prefix(adr, reg, true);
1562 emit_int8(0x0F);
1563 emit_int8((unsigned char)0xB0);
1564 emit_operand(reg, adr);
1565 }
1566
1567 void Assembler::comisd(XMMRegister dst, Address src) {
1568 // NOTE: dbx seems to decode this as comiss even though the
1569 // 0x66 is there. Strangly ucomisd comes out correct
1570 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1571 if (VM_Version::supports_evex()) {
1572 tuple_type = EVEX_T1S;
1573 input_size_in_bits = EVEX_64bit;
1574 emit_simd_arith_nonds_q(0x2F, dst, src, VEX_SIMD_66, true);
1575 } else {
1576 emit_simd_arith_nonds(0x2F, dst, src, VEX_SIMD_66);
1577 }
1578 }
1579
1580 void Assembler::comisd(XMMRegister dst, XMMRegister src) {
1581 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1582 if (VM_Version::supports_evex()) {
1583 emit_simd_arith_nonds_q(0x2F, dst, src, VEX_SIMD_66, true);
1584 } else {
1585 emit_simd_arith_nonds(0x2F, dst, src, VEX_SIMD_66);
1586 }
1587 }
1588
1589 void Assembler::comiss(XMMRegister dst, Address src) {
1590 if (VM_Version::supports_evex()) {
1591 tuple_type = EVEX_T1S;
1592 input_size_in_bits = EVEX_32bit;
1593 }
1594 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1595 emit_simd_arith_nonds(0x2F, dst, src, VEX_SIMD_NONE, true);
1596 }
1597
1598 void Assembler::comiss(XMMRegister dst, XMMRegister src) {
1599 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1600 emit_simd_arith_nonds(0x2F, dst, src, VEX_SIMD_NONE, true);
1601 }
1602
1603 void Assembler::cpuid() {
1604 emit_int8(0x0F);
1605 emit_int8((unsigned char)0xA2);
1606 }
1607
1608 void Assembler::cvtdq2pd(XMMRegister dst, XMMRegister src) {
1609 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1610 emit_simd_arith_nonds(0xE6, dst, src, VEX_SIMD_F3);
1611 }
1612
1613 void Assembler::cvtdq2ps(XMMRegister dst, XMMRegister src) {
1614 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1615 emit_simd_arith_nonds(0x5B, dst, src, VEX_SIMD_NONE);
1616 }
1617
1618 void Assembler::cvtsd2ss(XMMRegister dst, XMMRegister src) {
1619 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1620 if (VM_Version::supports_evex()) {
1621 emit_simd_arith_q(0x5A, dst, src, VEX_SIMD_F2);
1622 } else {
1623 emit_simd_arith(0x5A, dst, src, VEX_SIMD_F2);
1624 }
1625 }
1626
1627 void Assembler::cvtsd2ss(XMMRegister dst, Address src) {
1628 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1629 if (VM_Version::supports_evex()) {
1630 tuple_type = EVEX_T1F;
1631 input_size_in_bits = EVEX_64bit;
1632 emit_simd_arith_q(0x5A, dst, src, VEX_SIMD_F2);
1633 } else {
1634 emit_simd_arith(0x5A, dst, src, VEX_SIMD_F2);
1635 }
1636 }
1637
1638 void Assembler::cvtsi2sdl(XMMRegister dst, Register src) {
1639 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1640 int encode = 0;
1641 if (VM_Version::supports_evex()) {
1642 encode = simd_prefix_and_encode_q(dst, dst, src, VEX_SIMD_F2, true);
1643 } else {
1644 encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, false);
1645 }
1646 emit_int8(0x2A);
1647 emit_int8((unsigned char)(0xC0 | encode));
1648 }
1649
1650 void Assembler::cvtsi2sdl(XMMRegister dst, Address src) {
1651 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1652 if (VM_Version::supports_evex()) {
1653 tuple_type = EVEX_T1S;
1654 input_size_in_bits = EVEX_32bit;
1655 emit_simd_arith_q(0x2A, dst, src, VEX_SIMD_F2, true);
1656 } else {
1657 emit_simd_arith(0x2A, dst, src, VEX_SIMD_F2);
1658 }
1659 }
1660
1661 void Assembler::cvtsi2ssl(XMMRegister dst, Register src) {
1662 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1663 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, true);
1664 emit_int8(0x2A);
1665 emit_int8((unsigned char)(0xC0 | encode));
1666 }
1667
1668 void Assembler::cvtsi2ssl(XMMRegister dst, Address src) {
1669 if (VM_Version::supports_evex()) {
1670 tuple_type = EVEX_T1S;
1671 input_size_in_bits = EVEX_32bit;
1672 }
1673 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1674 emit_simd_arith(0x2A, dst, src, VEX_SIMD_F3, true);
1675 }
1676
1677 void Assembler::cvtss2sd(XMMRegister dst, XMMRegister src) {
1678 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1679 emit_simd_arith(0x5A, dst, src, VEX_SIMD_F3);
1680 }
1681
1682 void Assembler::cvtss2sd(XMMRegister dst, Address src) {
1683 if (VM_Version::supports_evex()) {
1684 tuple_type = EVEX_T1S;
1685 input_size_in_bits = EVEX_32bit;
1686 }
1687 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1688 emit_simd_arith(0x5A, dst, src, VEX_SIMD_F3);
1689 }
1690
1691
1692 void Assembler::cvttsd2sil(Register dst, XMMRegister src) {
1693 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1694 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, true);
1695 emit_int8(0x2C);
1696 emit_int8((unsigned char)(0xC0 | encode));
1697 }
1698
1699 void Assembler::cvttss2sil(Register dst, XMMRegister src) {
1700 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1701 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, true);
1702 emit_int8(0x2C);
1703 emit_int8((unsigned char)(0xC0 | encode));
1704 }
1705
1706 void Assembler::decl(Address dst) {
1707 // Don't use it directly. Use MacroAssembler::decrement() instead.
1708 InstructionMark im(this);
1709 prefix(dst);
1710 emit_int8((unsigned char)0xFF);
1711 emit_operand(rcx, dst);
1712 }
1713
1714 void Assembler::divsd(XMMRegister dst, Address src) {
1715 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1716 if (VM_Version::supports_evex()) {
1717 tuple_type = EVEX_T1S;
1718 input_size_in_bits = EVEX_64bit;
1719 emit_simd_arith_q(0x5E, dst, src, VEX_SIMD_F2);
1720 } else {
1721 emit_simd_arith(0x5E, dst, src, VEX_SIMD_F2);
1722 }
1723 }
1724
1725 void Assembler::divsd(XMMRegister dst, XMMRegister src) {
1726 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1727 if (VM_Version::supports_evex()) {
1728 emit_simd_arith_q(0x5E, dst, src, VEX_SIMD_F2);
1729 } else {
1730 emit_simd_arith(0x5E, dst, src, VEX_SIMD_F2);
1731 }
1732 }
1733
1734 void Assembler::divss(XMMRegister dst, Address src) {
1735 if (VM_Version::supports_evex()) {
1736 tuple_type = EVEX_T1S;
1737 input_size_in_bits = EVEX_32bit;
1738 }
1739 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1740 emit_simd_arith(0x5E, dst, src, VEX_SIMD_F3);
1741 }
1742
1743 void Assembler::divss(XMMRegister dst, XMMRegister src) {
1744 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1745 emit_simd_arith(0x5E, dst, src, VEX_SIMD_F3);
1746 }
1747
1748 void Assembler::emms() {
1749 NOT_LP64(assert(VM_Version::supports_mmx(), ""));
1750 emit_int8(0x0F);
1751 emit_int8(0x77);
1752 }
1753
1754 void Assembler::hlt() {
1755 emit_int8((unsigned char)0xF4);
1756 }
1757
1758 void Assembler::idivl(Register src) {
1759 int encode = prefix_and_encode(src->encoding());
1760 emit_int8((unsigned char)0xF7);
1761 emit_int8((unsigned char)(0xF8 | encode));
1762 }
1763
1764 void Assembler::divl(Register src) { // Unsigned
1765 int encode = prefix_and_encode(src->encoding());
1766 emit_int8((unsigned char)0xF7);
1767 emit_int8((unsigned char)(0xF0 | encode));
1768 }
1769
1770 void Assembler::imull(Register dst, Register src) {
1771 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1772 emit_int8(0x0F);
1773 emit_int8((unsigned char)0xAF);
1774 emit_int8((unsigned char)(0xC0 | encode));
1775 }
1776
1777
1778 void Assembler::imull(Register dst, Register src, int value) {
1779 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1780 if (is8bit(value)) {
1781 emit_int8(0x6B);
1782 emit_int8((unsigned char)(0xC0 | encode));
1783 emit_int8(value & 0xFF);
1784 } else {
1785 emit_int8(0x69);
1786 emit_int8((unsigned char)(0xC0 | encode));
1787 emit_int32(value);
1788 }
1789 }
1790
1791 void Assembler::imull(Register dst, Address src) {
1792 InstructionMark im(this);
1793 prefix(src, dst);
1794 emit_int8(0x0F);
1795 emit_int8((unsigned char) 0xAF);
1796 emit_operand(dst, src);
1797 }
1798
1799
1800 void Assembler::incl(Address dst) {
1801 // Don't use it directly. Use MacroAssembler::increment() instead.
1802 InstructionMark im(this);
1803 prefix(dst);
1804 emit_int8((unsigned char)0xFF);
1805 emit_operand(rax, dst);
1806 }
1807
1808 void Assembler::jcc(Condition cc, Label& L, bool maybe_short) {
1809 InstructionMark im(this);
1810 assert((0 <= cc) && (cc < 16), "illegal cc");
1811 if (L.is_bound()) {
1812 address dst = target(L);
1813 assert(dst != NULL, "jcc most probably wrong");
1814
1815 const int short_size = 2;
1816 const int long_size = 6;
1817 intptr_t offs = (intptr_t)dst - (intptr_t)pc();
1818 if (maybe_short && is8bit(offs - short_size)) {
1819 // 0111 tttn #8-bit disp
1820 emit_int8(0x70 | cc);
1821 emit_int8((offs - short_size) & 0xFF);
1822 } else {
1823 // 0000 1111 1000 tttn #32-bit disp
1824 assert(is_simm32(offs - long_size),
1825 "must be 32bit offset (call4)");
1826 emit_int8(0x0F);
1827 emit_int8((unsigned char)(0x80 | cc));
1828 emit_int32(offs - long_size);
1829 }
1830 } else {
1831 // Note: could eliminate cond. jumps to this jump if condition
1832 // is the same however, seems to be rather unlikely case.
1833 // Note: use jccb() if label to be bound is very close to get
1834 // an 8-bit displacement
1835 L.add_patch_at(code(), locator());
1836 emit_int8(0x0F);
1837 emit_int8((unsigned char)(0x80 | cc));
1838 emit_int32(0);
1839 }
1840 }
1841
1842 void Assembler::jccb(Condition cc, Label& L) {
1843 if (L.is_bound()) {
1844 const int short_size = 2;
1845 address entry = target(L);
1846 #ifdef ASSERT
1847 intptr_t dist = (intptr_t)entry - ((intptr_t)pc() + short_size);
1848 intptr_t delta = short_branch_delta();
1849 if (delta != 0) {
1850 dist += (dist < 0 ? (-delta) :delta);
1851 }
1852 assert(is8bit(dist), "Dispacement too large for a short jmp");
1853 #endif
1854 intptr_t offs = (intptr_t)entry - (intptr_t)pc();
1855 // 0111 tttn #8-bit disp
1856 emit_int8(0x70 | cc);
1857 emit_int8((offs - short_size) & 0xFF);
1858 } else {
1859 InstructionMark im(this);
1860 L.add_patch_at(code(), locator());
1861 emit_int8(0x70 | cc);
1862 emit_int8(0);
1863 }
1864 }
1865
1866 void Assembler::jmp(Address adr) {
1867 InstructionMark im(this);
1868 prefix(adr);
1869 emit_int8((unsigned char)0xFF);
1870 emit_operand(rsp, adr);
1871 }
1872
1873 void Assembler::jmp(Label& L, bool maybe_short) {
1874 if (L.is_bound()) {
1875 address entry = target(L);
1876 assert(entry != NULL, "jmp most probably wrong");
1877 InstructionMark im(this);
1878 const int short_size = 2;
1879 const int long_size = 5;
1880 intptr_t offs = entry - pc();
1881 if (maybe_short && is8bit(offs - short_size)) {
1882 emit_int8((unsigned char)0xEB);
1883 emit_int8((offs - short_size) & 0xFF);
1884 } else {
1885 emit_int8((unsigned char)0xE9);
1886 emit_int32(offs - long_size);
1887 }
1888 } else {
1889 // By default, forward jumps are always 32-bit displacements, since
1890 // we can't yet know where the label will be bound. If you're sure that
1891 // the forward jump will not run beyond 256 bytes, use jmpb to
1892 // force an 8-bit displacement.
1893 InstructionMark im(this);
1894 L.add_patch_at(code(), locator());
1895 emit_int8((unsigned char)0xE9);
1896 emit_int32(0);
1897 }
1898 }
1899
1900 void Assembler::jmp(Register entry) {
1901 int encode = prefix_and_encode(entry->encoding());
1902 emit_int8((unsigned char)0xFF);
1903 emit_int8((unsigned char)(0xE0 | encode));
1904 }
1905
1906 void Assembler::jmp_literal(address dest, RelocationHolder const& rspec) {
1907 InstructionMark im(this);
1908 emit_int8((unsigned char)0xE9);
1909 assert(dest != NULL, "must have a target");
1910 intptr_t disp = dest - (pc() + sizeof(int32_t));
1911 assert(is_simm32(disp), "must be 32bit offset (jmp)");
1912 emit_data(disp, rspec.reloc(), call32_operand);
1913 }
1914
1915 void Assembler::jmpb(Label& L) {
1916 if (L.is_bound()) {
1917 const int short_size = 2;
1918 address entry = target(L);
1919 assert(entry != NULL, "jmp most probably wrong");
1920 #ifdef ASSERT
1921 intptr_t dist = (intptr_t)entry - ((intptr_t)pc() + short_size);
1922 intptr_t delta = short_branch_delta();
1923 if (delta != 0) {
1924 dist += (dist < 0 ? (-delta) :delta);
1925 }
1926 assert(is8bit(dist), "Dispacement too large for a short jmp");
1927 #endif
1928 intptr_t offs = entry - pc();
1929 emit_int8((unsigned char)0xEB);
1930 emit_int8((offs - short_size) & 0xFF);
1931 } else {
1932 InstructionMark im(this);
1933 L.add_patch_at(code(), locator());
1934 emit_int8((unsigned char)0xEB);
1935 emit_int8(0);
1936 }
1937 }
1938
1939 void Assembler::ldmxcsr( Address src) {
1940 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1941 InstructionMark im(this);
1942 prefix(src);
1943 emit_int8(0x0F);
1944 emit_int8((unsigned char)0xAE);
1945 emit_operand(as_Register(2), src);
1946 }
1947
1948 void Assembler::leal(Register dst, Address src) {
1949 InstructionMark im(this);
1950 #ifdef _LP64
1951 emit_int8(0x67); // addr32
1952 prefix(src, dst);
1953 #endif // LP64
1954 emit_int8((unsigned char)0x8D);
1955 emit_operand(dst, src);
1956 }
1957
1958 void Assembler::lfence() {
1959 emit_int8(0x0F);
1960 emit_int8((unsigned char)0xAE);
1961 emit_int8((unsigned char)0xE8);
1962 }
1963
1964 void Assembler::lock() {
1965 emit_int8((unsigned char)0xF0);
1966 }
1967
1968 void Assembler::lzcntl(Register dst, Register src) {
1969 assert(VM_Version::supports_lzcnt(), "encoding is treated as BSR");
1970 emit_int8((unsigned char)0xF3);
1971 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1972 emit_int8(0x0F);
1973 emit_int8((unsigned char)0xBD);
1974 emit_int8((unsigned char)(0xC0 | encode));
1975 }
1976
1977 // Emit mfence instruction
1978 void Assembler::mfence() {
1979 NOT_LP64(assert(VM_Version::supports_sse2(), "unsupported");)
1980 emit_int8(0x0F);
1981 emit_int8((unsigned char)0xAE);
1982 emit_int8((unsigned char)0xF0);
1983 }
1984
1985 void Assembler::mov(Register dst, Register src) {
1986 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src));
1987 }
1988
1989 void Assembler::movapd(XMMRegister dst, XMMRegister src) {
1990 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1991 if (VM_Version::supports_evex()) {
1992 emit_simd_arith_nonds_q(0x28, dst, src, VEX_SIMD_66, true);
1993 } else {
1994 emit_simd_arith_nonds(0x28, dst, src, VEX_SIMD_66);
1995 }
1996 }
1997
1998 void Assembler::movaps(XMMRegister dst, XMMRegister src) {
1999 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2000 emit_simd_arith_nonds(0x28, dst, src, VEX_SIMD_NONE);
2001 }
2002
2003 void Assembler::movlhps(XMMRegister dst, XMMRegister src) {
2004 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2005 int encode = simd_prefix_and_encode(dst, src, src, VEX_SIMD_NONE, true, VEX_OPCODE_0F,
2006 false, AVX_128bit);
2007 emit_int8(0x16);
2008 emit_int8((unsigned char)(0xC0 | encode));
2009 }
2010
2011 void Assembler::movb(Register dst, Address src) {
2012 NOT_LP64(assert(dst->has_byte_register(), "must have byte register"));
2013 InstructionMark im(this);
2014 prefix(src, dst, true);
2015 emit_int8((unsigned char)0x8A);
2016 emit_operand(dst, src);
2017 }
2018
2019 void Assembler::kmovq(KRegister dst, KRegister src) {
2020 NOT_LP64(assert(VM_Version::supports_evex(), ""));
2021 int encode = kreg_prefix_and_encode(dst, knoreg, src, VEX_SIMD_NONE,
2022 true, VEX_OPCODE_0F, true);
2023 emit_int8((unsigned char)0x90);
2024 emit_int8((unsigned char)(0xC0 | encode));
2025 }
2026
2027 void Assembler::kmovq(KRegister dst, Address src) {
2028 NOT_LP64(assert(VM_Version::supports_evex(), ""));
2029 int dst_enc = dst->encoding();
2030 int nds_enc = 0;
2031 vex_prefix(src, nds_enc, dst_enc, VEX_SIMD_NONE,
2032 VEX_OPCODE_0F, true, AVX_128bit, true, true);
2033 emit_int8((unsigned char)0x90);
2034 emit_operand((Register)dst, src);
2035 }
2036
2037 void Assembler::kmovq(Address dst, KRegister src) {
2038 NOT_LP64(assert(VM_Version::supports_evex(), ""));
2039 int src_enc = src->encoding();
2040 int nds_enc = 0;
2041 vex_prefix(dst, nds_enc, src_enc, VEX_SIMD_NONE,
2042 VEX_OPCODE_0F, true, AVX_128bit, true, true);
2043 emit_int8((unsigned char)0x90);
2044 emit_operand((Register)src, dst);
2045 }
2046
2047 void Assembler::kmovql(KRegister dst, Register src) {
2048 NOT_LP64(assert(VM_Version::supports_evex(), ""));
2049 bool supports_bw = VM_Version::supports_avx512bw();
2050 VexSimdPrefix pre = supports_bw ? VEX_SIMD_F2 : VEX_SIMD_NONE;
2051 int encode = kreg_prefix_and_encode(dst, knoreg, src, pre, true,
2052 VEX_OPCODE_0F, supports_bw);
2053 emit_int8((unsigned char)0x92);
2054 emit_int8((unsigned char)(0xC0 | encode));
2055 }
2056
2057 void Assembler::kmovdl(KRegister dst, Register src) {
2058 NOT_LP64(assert(VM_Version::supports_evex(), ""));
2059 VexSimdPrefix pre = VM_Version::supports_avx512bw() ? VEX_SIMD_F2 : VEX_SIMD_NONE;
2060 int encode = kreg_prefix_and_encode(dst, knoreg, src, pre, true, VEX_OPCODE_0F, false);
2061 emit_int8((unsigned char)0x92);
2062 emit_int8((unsigned char)(0xC0 | encode));
2063 }
2064
2065 void Assembler::movb(Address dst, int imm8) {
2066 InstructionMark im(this);
2067 prefix(dst);
2068 emit_int8((unsigned char)0xC6);
2069 emit_operand(rax, dst, 1);
2070 emit_int8(imm8);
2071 }
2072
2073
2074 void Assembler::movb(Address dst, Register src) {
2075 assert(src->has_byte_register(), "must have byte register");
2076 InstructionMark im(this);
2077 prefix(dst, src, true);
2078 emit_int8((unsigned char)0x88);
2079 emit_operand(src, dst);
2080 }
2081
2082 void Assembler::movdl(XMMRegister dst, Register src) {
2083 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2084 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_66, true);
2085 emit_int8(0x6E);
2086 emit_int8((unsigned char)(0xC0 | encode));
2087 }
2088
2089 void Assembler::movdl(Register dst, XMMRegister src) {
2090 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2091 // swap src/dst to get correct prefix
2092 int encode = simd_prefix_and_encode(src, dst, VEX_SIMD_66, true);
2093 emit_int8(0x7E);
2094 emit_int8((unsigned char)(0xC0 | encode));
2095 }
2096
2097 void Assembler::movdl(XMMRegister dst, Address src) {
2098 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2099 if (VM_Version::supports_evex()) {
2100 tuple_type = EVEX_T1S;
2101 input_size_in_bits = EVEX_32bit;
2102 }
2103 InstructionMark im(this);
2104 simd_prefix(dst, src, VEX_SIMD_66, true, VEX_OPCODE_0F);
2105 emit_int8(0x6E);
2106 emit_operand(dst, src);
2107 }
2108
2109 void Assembler::movdl(Address dst, XMMRegister src) {
2110 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2111 if (VM_Version::supports_evex()) {
2112 tuple_type = EVEX_T1S;
2113 input_size_in_bits = EVEX_32bit;
2114 }
2115 InstructionMark im(this);
2116 simd_prefix(dst, src, VEX_SIMD_66, true);
2117 emit_int8(0x7E);
2118 emit_operand(src, dst);
2119 }
2120
2121 void Assembler::movdqa(XMMRegister dst, XMMRegister src) {
2122 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2123 emit_simd_arith_nonds(0x6F, dst, src, VEX_SIMD_66);
2124 }
2125
2126 void Assembler::movdqa(XMMRegister dst, Address src) {
2127 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2128 if (VM_Version::supports_evex()) {
2129 tuple_type = EVEX_FVM;
2130 }
2131 emit_simd_arith_nonds(0x6F, dst, src, VEX_SIMD_66);
2132 }
2133
2134 void Assembler::movdqu(XMMRegister dst, Address src) {
2135 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2136 if (VM_Version::supports_evex()) {
2137 tuple_type = EVEX_FVM;
2138 }
2139 emit_simd_arith_nonds(0x6F, dst, src, VEX_SIMD_F3);
2140 }
2141
2142 void Assembler::movdqu(XMMRegister dst, XMMRegister src) {
2143 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2144 emit_simd_arith_nonds(0x6F, dst, src, VEX_SIMD_F3);
2145 }
2146
2147 void Assembler::movdqu(Address dst, XMMRegister src) {
2148 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2149 if (VM_Version::supports_evex()) {
2150 tuple_type = EVEX_FVM;
2151 }
2152 InstructionMark im(this);
2153 simd_prefix(dst, src, VEX_SIMD_F3, false);
2154 emit_int8(0x7F);
2155 emit_operand(src, dst);
2156 }
2157
2158 // Move Unaligned 256bit Vector
2159 void Assembler::vmovdqu(XMMRegister dst, XMMRegister src) {
2160 assert(UseAVX > 0, "");
2161 if (VM_Version::supports_evex()) {
2162 tuple_type = EVEX_FVM;
2163 }
2164 int vector_len = AVX_256bit;
2165 int encode = vex_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_F3, vector_len);
2166 emit_int8(0x6F);
2167 emit_int8((unsigned char)(0xC0 | encode));
2168 }
2169
2170 void Assembler::vmovdqu(XMMRegister dst, Address src) {
2171 assert(UseAVX > 0, "");
2172 if (VM_Version::supports_evex()) {
2173 tuple_type = EVEX_FVM;
2174 }
2175 InstructionMark im(this);
2176 int vector_len = AVX_256bit;
2177 vex_prefix(dst, xnoreg, src, VEX_SIMD_F3, vector_len, false);
2178 emit_int8(0x6F);
2179 emit_operand(dst, src);
2180 }
2181
2182 void Assembler::vmovdqu(Address dst, XMMRegister src) {
2183 assert(UseAVX > 0, "");
2184 if (VM_Version::supports_evex()) {
2185 tuple_type = EVEX_FVM;
2186 }
2187 InstructionMark im(this);
2188 int vector_len = AVX_256bit;
2189 // swap src<->dst for encoding
2190 assert(src != xnoreg, "sanity");
2191 vex_prefix(src, xnoreg, dst, VEX_SIMD_F3, vector_len, false);
2192 emit_int8(0x7F);
2193 emit_operand(src, dst);
2194 }
2195
2196 // Move Unaligned EVEX enabled Vector (programmable : 8,16,32,64)
2197 void Assembler::evmovdqu(XMMRegister dst, XMMRegister src, int vector_len) {
2198 assert(UseAVX > 0, "");
2199 int src_enc = src->encoding();
2200 int dst_enc = dst->encoding();
2201 int encode = vex_prefix_and_encode(dst_enc, 0, src_enc, VEX_SIMD_F3, VEX_OPCODE_0F,
2202 true, vector_len, false, false);
2203 emit_int8(0x6F);
2204 emit_int8((unsigned char)(0xC0 | encode));
2205 }
2206
2207 void Assembler::evmovdqu(XMMRegister dst, Address src, int vector_len) {
2208 assert(UseAVX > 0, "");
2209 InstructionMark im(this);
2210 if (VM_Version::supports_evex()) {
2211 tuple_type = EVEX_FVM;
2212 vex_prefix_q(dst, xnoreg, src, VEX_SIMD_F3, vector_len, false);
2213 } else {
2214 vex_prefix(dst, xnoreg, src, VEX_SIMD_F3, vector_len, false);
2215 }
2216 emit_int8(0x6F);
2217 emit_operand(dst, src);
2218 }
2219
2220 void Assembler::evmovdqu(Address dst, XMMRegister src, int vector_len) {
2221 assert(UseAVX > 0, "");
2222 InstructionMark im(this);
2223 assert(src != xnoreg, "sanity");
2224 if (VM_Version::supports_evex()) {
2225 tuple_type = EVEX_FVM;
2226 // swap src<->dst for encoding
2227 vex_prefix_q(src, xnoreg, dst, VEX_SIMD_F3, vector_len, false);
2228 } else {
2229 // swap src<->dst for encoding
2230 vex_prefix(src, xnoreg, dst, VEX_SIMD_F3, vector_len, false);
2231 }
2232 emit_int8(0x7F);
2233 emit_operand(src, dst);
2234 }
2235
2236 // Uses zero extension on 64bit
2237
2238 void Assembler::movl(Register dst, int32_t imm32) {
2239 int encode = prefix_and_encode(dst->encoding());
2240 emit_int8((unsigned char)(0xB8 | encode));
2241 emit_int32(imm32);
2242 }
2243
2244 void Assembler::movl(Register dst, Register src) {
2245 int encode = prefix_and_encode(dst->encoding(), src->encoding());
2246 emit_int8((unsigned char)0x8B);
2247 emit_int8((unsigned char)(0xC0 | encode));
2248 }
2249
2250 void Assembler::movl(Register dst, Address src) {
2251 InstructionMark im(this);
2252 prefix(src, dst);
2253 emit_int8((unsigned char)0x8B);
2254 emit_operand(dst, src);
2255 }
2256
2257 void Assembler::movl(Address dst, int32_t imm32) {
2258 InstructionMark im(this);
2259 prefix(dst);
2260 emit_int8((unsigned char)0xC7);
2261 emit_operand(rax, dst, 4);
2262 emit_int32(imm32);
2263 }
2264
2265 void Assembler::movl(Address dst, Register src) {
2266 InstructionMark im(this);
2267 prefix(dst, src);
2268 emit_int8((unsigned char)0x89);
2269 emit_operand(src, dst);
2270 }
2271
2272 // New cpus require to use movsd and movss to avoid partial register stall
2273 // when loading from memory. But for old Opteron use movlpd instead of movsd.
2274 // The selection is done in MacroAssembler::movdbl() and movflt().
2275 void Assembler::movlpd(XMMRegister dst, Address src) {
2276 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2277 if (VM_Version::supports_evex()) {
2278 tuple_type = EVEX_T1S;
2279 input_size_in_bits = EVEX_32bit;
2280 }
2281 emit_simd_arith(0x12, dst, src, VEX_SIMD_66, true);
2282 }
2283
2284 void Assembler::movq( MMXRegister dst, Address src ) {
2285 assert( VM_Version::supports_mmx(), "" );
2286 emit_int8(0x0F);
2287 emit_int8(0x6F);
2288 emit_operand(dst, src);
2289 }
2290
2291 void Assembler::movq( Address dst, MMXRegister src ) {
2292 assert( VM_Version::supports_mmx(), "" );
2293 emit_int8(0x0F);
2294 emit_int8(0x7F);
2295 // workaround gcc (3.2.1-7a) bug
2296 // In that version of gcc with only an emit_operand(MMX, Address)
2297 // gcc will tail jump and try and reverse the parameters completely
2298 // obliterating dst in the process. By having a version available
2299 // that doesn't need to swap the args at the tail jump the bug is
2300 // avoided.
2301 emit_operand(dst, src);
2302 }
2303
2304 void Assembler::movq(XMMRegister dst, Address src) {
2305 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2306 InstructionMark im(this);
2307 if (VM_Version::supports_evex()) {
2308 tuple_type = EVEX_T1S;
2309 input_size_in_bits = EVEX_64bit;
2310 simd_prefix_q(dst, xnoreg, src, VEX_SIMD_F3, true);
2311 } else {
2312 simd_prefix(dst, src, VEX_SIMD_F3, true, VEX_OPCODE_0F);
2313 }
2314 emit_int8(0x7E);
2315 emit_operand(dst, src);
2316 }
2317
2318 void Assembler::movq(Address dst, XMMRegister src) {
2319 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2320 InstructionMark im(this);
2321 if (VM_Version::supports_evex()) {
2322 tuple_type = EVEX_T1S;
2323 input_size_in_bits = EVEX_64bit;
2324 simd_prefix(src, xnoreg, dst, VEX_SIMD_66, true,
2325 VEX_OPCODE_0F, true, AVX_128bit);
2326 } else {
2327 simd_prefix(dst, src, VEX_SIMD_66, true);
2328 }
2329 emit_int8((unsigned char)0xD6);
2330 emit_operand(src, dst);
2331 }
2332
2333 void Assembler::movsbl(Register dst, Address src) { // movsxb
2334 InstructionMark im(this);
2335 prefix(src, dst);
2336 emit_int8(0x0F);
2337 emit_int8((unsigned char)0xBE);
2338 emit_operand(dst, src);
2339 }
2340
2341 void Assembler::movsbl(Register dst, Register src) { // movsxb
2342 NOT_LP64(assert(src->has_byte_register(), "must have byte register"));
2343 int encode = prefix_and_encode(dst->encoding(), src->encoding(), true);
2344 emit_int8(0x0F);
2345 emit_int8((unsigned char)0xBE);
2346 emit_int8((unsigned char)(0xC0 | encode));
2347 }
2348
2349 void Assembler::movsd(XMMRegister dst, XMMRegister src) {
2350 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2351 if (VM_Version::supports_evex()) {
2352 emit_simd_arith_q(0x10, dst, src, VEX_SIMD_F2, true);
2353 } else {
2354 emit_simd_arith(0x10, dst, src, VEX_SIMD_F2);
2355 }
2356 }
2357
2358 void Assembler::movsd(XMMRegister dst, Address src) {
2359 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2360 if (VM_Version::supports_evex()) {
2361 tuple_type = EVEX_T1S;
2362 input_size_in_bits = EVEX_64bit;
2363 emit_simd_arith_nonds_q(0x10, dst, src, VEX_SIMD_F2, true);
2364 } else {
2365 emit_simd_arith_nonds(0x10, dst, src, VEX_SIMD_F2);
2366 }
2367 }
2368
2369 void Assembler::movsd(Address dst, XMMRegister src) {
2370 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2371 InstructionMark im(this);
2372 if (VM_Version::supports_evex()) {
2373 tuple_type = EVEX_T1S;
2374 input_size_in_bits = EVEX_64bit;
2375 simd_prefix_q(src, xnoreg, dst, VEX_SIMD_F2);
2376 } else {
2377 simd_prefix(src, xnoreg, dst, VEX_SIMD_F2, false);
2378 }
2379 emit_int8(0x11);
2380 emit_operand(src, dst);
2381 }
2382
2383 void Assembler::movss(XMMRegister dst, XMMRegister src) {
2384 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2385 emit_simd_arith(0x10, dst, src, VEX_SIMD_F3, true);
2386 }
2387
2388 void Assembler::movss(XMMRegister dst, Address src) {
2389 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2390 if (VM_Version::supports_evex()) {
2391 tuple_type = EVEX_T1S;
2392 input_size_in_bits = EVEX_32bit;
2393 }
2394 emit_simd_arith_nonds(0x10, dst, src, VEX_SIMD_F3, true);
2395 }
2396
2397 void Assembler::movss(Address dst, XMMRegister src) {
2398 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2399 if (VM_Version::supports_evex()) {
2400 tuple_type = EVEX_T1S;
2401 input_size_in_bits = EVEX_32bit;
2402 }
2403 InstructionMark im(this);
2404 simd_prefix(dst, src, VEX_SIMD_F3, false);
2405 emit_int8(0x11);
2406 emit_operand(src, dst);
2407 }
2408
2409 void Assembler::movswl(Register dst, Address src) { // movsxw
2410 InstructionMark im(this);
2411 prefix(src, dst);
2412 emit_int8(0x0F);
2413 emit_int8((unsigned char)0xBF);
2414 emit_operand(dst, src);
2415 }
2416
2417 void Assembler::movswl(Register dst, Register src) { // movsxw
2418 int encode = prefix_and_encode(dst->encoding(), src->encoding());
2419 emit_int8(0x0F);
2420 emit_int8((unsigned char)0xBF);
2421 emit_int8((unsigned char)(0xC0 | encode));
2422 }
2423
2424 void Assembler::movw(Address dst, int imm16) {
2425 InstructionMark im(this);
2426
2427 emit_int8(0x66); // switch to 16-bit mode
2428 prefix(dst);
2429 emit_int8((unsigned char)0xC7);
2430 emit_operand(rax, dst, 2);
2431 emit_int16(imm16);
2432 }
2433
2434 void Assembler::movw(Register dst, Address src) {
2435 InstructionMark im(this);
2436 emit_int8(0x66);
2437 prefix(src, dst);
2438 emit_int8((unsigned char)0x8B);
2439 emit_operand(dst, src);
2440 }
2441
2442 void Assembler::movw(Address dst, Register src) {
2443 InstructionMark im(this);
2444 emit_int8(0x66);
2445 prefix(dst, src);
2446 emit_int8((unsigned char)0x89);
2447 emit_operand(src, dst);
2448 }
2449
2450 void Assembler::movzbl(Register dst, Address src) { // movzxb
2451 InstructionMark im(this);
2452 prefix(src, dst);
2453 emit_int8(0x0F);
2454 emit_int8((unsigned char)0xB6);
2455 emit_operand(dst, src);
2456 }
2457
2458 void Assembler::movzbl(Register dst, Register src) { // movzxb
2459 NOT_LP64(assert(src->has_byte_register(), "must have byte register"));
2460 int encode = prefix_and_encode(dst->encoding(), src->encoding(), true);
2461 emit_int8(0x0F);
2462 emit_int8((unsigned char)0xB6);
2463 emit_int8(0xC0 | encode);
2464 }
2465
2466 void Assembler::movzwl(Register dst, Address src) { // movzxw
2467 InstructionMark im(this);
2468 prefix(src, dst);
2469 emit_int8(0x0F);
2470 emit_int8((unsigned char)0xB7);
2471 emit_operand(dst, src);
2472 }
2473
2474 void Assembler::movzwl(Register dst, Register src) { // movzxw
2475 int encode = prefix_and_encode(dst->encoding(), src->encoding());
2476 emit_int8(0x0F);
2477 emit_int8((unsigned char)0xB7);
2478 emit_int8(0xC0 | encode);
2479 }
2480
2481 void Assembler::mull(Address src) {
2482 InstructionMark im(this);
2483 prefix(src);
2484 emit_int8((unsigned char)0xF7);
2485 emit_operand(rsp, src);
2486 }
2487
2488 void Assembler::mull(Register src) {
2489 int encode = prefix_and_encode(src->encoding());
2490 emit_int8((unsigned char)0xF7);
2491 emit_int8((unsigned char)(0xE0 | encode));
2492 }
2493
2494 void Assembler::mulsd(XMMRegister dst, Address src) {
2495 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2496 if (VM_Version::supports_evex()) {
2497 tuple_type = EVEX_T1S;
2498 input_size_in_bits = EVEX_64bit;
2499 emit_simd_arith_q(0x59, dst, src, VEX_SIMD_F2);
2500 } else {
2501 emit_simd_arith(0x59, dst, src, VEX_SIMD_F2);
2502 }
2503 }
2504
2505 void Assembler::mulsd(XMMRegister dst, XMMRegister src) {
2506 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2507 if (VM_Version::supports_evex()) {
2508 emit_simd_arith_q(0x59, dst, src, VEX_SIMD_F2);
2509 } else {
2510 emit_simd_arith(0x59, dst, src, VEX_SIMD_F2);
2511 }
2512 }
2513
2514 void Assembler::mulss(XMMRegister dst, Address src) {
2515 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2516 if (VM_Version::supports_evex()) {
2517 tuple_type = EVEX_T1S;
2518 input_size_in_bits = EVEX_32bit;
2519 }
2520 emit_simd_arith(0x59, dst, src, VEX_SIMD_F3);
2521 }
2522
2523 void Assembler::mulss(XMMRegister dst, XMMRegister src) {
2524 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2525 emit_simd_arith(0x59, dst, src, VEX_SIMD_F3);
2526 }
2527
2528 void Assembler::negl(Register dst) {
2529 int encode = prefix_and_encode(dst->encoding());
2530 emit_int8((unsigned char)0xF7);
2531 emit_int8((unsigned char)(0xD8 | encode));
2532 }
2533
2534 void Assembler::nop(int i) {
2535 #ifdef ASSERT
2536 assert(i > 0, " ");
2537 // The fancy nops aren't currently recognized by debuggers making it a
2538 // pain to disassemble code while debugging. If asserts are on clearly
2539 // speed is not an issue so simply use the single byte traditional nop
2540 // to do alignment.
2541
2542 for (; i > 0 ; i--) emit_int8((unsigned char)0x90);
2543 return;
2544
2545 #endif // ASSERT
2546
2547 if (UseAddressNop && VM_Version::is_intel()) {
2548 //
2549 // Using multi-bytes nops "0x0F 0x1F [address]" for Intel
2550 // 1: 0x90
2551 // 2: 0x66 0x90
2552 // 3: 0x66 0x66 0x90 (don't use "0x0F 0x1F 0x00" - need patching safe padding)
2553 // 4: 0x0F 0x1F 0x40 0x00
2554 // 5: 0x0F 0x1F 0x44 0x00 0x00
2555 // 6: 0x66 0x0F 0x1F 0x44 0x00 0x00
2556 // 7: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00
2557 // 8: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2558 // 9: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2559 // 10: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2560 // 11: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2561
2562 // The rest coding is Intel specific - don't use consecutive address nops
2563
2564 // 12: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
2565 // 13: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
2566 // 14: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
2567 // 15: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
2568
2569 while(i >= 15) {
2570 // For Intel don't generate consecutive addess nops (mix with regular nops)
2571 i -= 15;
2572 emit_int8(0x66); // size prefix
2573 emit_int8(0x66); // size prefix
2574 emit_int8(0x66); // size prefix
2575 addr_nop_8();
2576 emit_int8(0x66); // size prefix
2577 emit_int8(0x66); // size prefix
2578 emit_int8(0x66); // size prefix
2579 emit_int8((unsigned char)0x90);
2580 // nop
2581 }
2582 switch (i) {
2583 case 14:
2584 emit_int8(0x66); // size prefix
2585 case 13:
2586 emit_int8(0x66); // size prefix
2587 case 12:
2588 addr_nop_8();
2589 emit_int8(0x66); // size prefix
2590 emit_int8(0x66); // size prefix
2591 emit_int8(0x66); // size prefix
2592 emit_int8((unsigned char)0x90);
2593 // nop
2594 break;
2595 case 11:
2596 emit_int8(0x66); // size prefix
2597 case 10:
2598 emit_int8(0x66); // size prefix
2599 case 9:
2600 emit_int8(0x66); // size prefix
2601 case 8:
2602 addr_nop_8();
2603 break;
2604 case 7:
2605 addr_nop_7();
2606 break;
2607 case 6:
2608 emit_int8(0x66); // size prefix
2609 case 5:
2610 addr_nop_5();
2611 break;
2612 case 4:
2613 addr_nop_4();
2614 break;
2615 case 3:
2616 // Don't use "0x0F 0x1F 0x00" - need patching safe padding
2617 emit_int8(0x66); // size prefix
2618 case 2:
2619 emit_int8(0x66); // size prefix
2620 case 1:
2621 emit_int8((unsigned char)0x90);
2622 // nop
2623 break;
2624 default:
2625 assert(i == 0, " ");
2626 }
2627 return;
2628 }
2629 if (UseAddressNop && VM_Version::is_amd()) {
2630 //
2631 // Using multi-bytes nops "0x0F 0x1F [address]" for AMD.
2632 // 1: 0x90
2633 // 2: 0x66 0x90
2634 // 3: 0x66 0x66 0x90 (don't use "0x0F 0x1F 0x00" - need patching safe padding)
2635 // 4: 0x0F 0x1F 0x40 0x00
2636 // 5: 0x0F 0x1F 0x44 0x00 0x00
2637 // 6: 0x66 0x0F 0x1F 0x44 0x00 0x00
2638 // 7: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00
2639 // 8: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2640 // 9: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2641 // 10: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2642 // 11: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2643
2644 // The rest coding is AMD specific - use consecutive address nops
2645
2646 // 12: 0x66 0x0F 0x1F 0x44 0x00 0x00 0x66 0x0F 0x1F 0x44 0x00 0x00
2647 // 13: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 0x66 0x0F 0x1F 0x44 0x00 0x00
2648 // 14: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00
2649 // 15: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00
2650 // 16: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2651 // Size prefixes (0x66) are added for larger sizes
2652
2653 while(i >= 22) {
2654 i -= 11;
2655 emit_int8(0x66); // size prefix
2656 emit_int8(0x66); // size prefix
2657 emit_int8(0x66); // size prefix
2658 addr_nop_8();
2659 }
2660 // Generate first nop for size between 21-12
2661 switch (i) {
2662 case 21:
2663 i -= 1;
2664 emit_int8(0x66); // size prefix
2665 case 20:
2666 case 19:
2667 i -= 1;
2668 emit_int8(0x66); // size prefix
2669 case 18:
2670 case 17:
2671 i -= 1;
2672 emit_int8(0x66); // size prefix
2673 case 16:
2674 case 15:
2675 i -= 8;
2676 addr_nop_8();
2677 break;
2678 case 14:
2679 case 13:
2680 i -= 7;
2681 addr_nop_7();
2682 break;
2683 case 12:
2684 i -= 6;
2685 emit_int8(0x66); // size prefix
2686 addr_nop_5();
2687 break;
2688 default:
2689 assert(i < 12, " ");
2690 }
2691
2692 // Generate second nop for size between 11-1
2693 switch (i) {
2694 case 11:
2695 emit_int8(0x66); // size prefix
2696 case 10:
2697 emit_int8(0x66); // size prefix
2698 case 9:
2699 emit_int8(0x66); // size prefix
2700 case 8:
2701 addr_nop_8();
2702 break;
2703 case 7:
2704 addr_nop_7();
2705 break;
2706 case 6:
2707 emit_int8(0x66); // size prefix
2708 case 5:
2709 addr_nop_5();
2710 break;
2711 case 4:
2712 addr_nop_4();
2713 break;
2714 case 3:
2715 // Don't use "0x0F 0x1F 0x00" - need patching safe padding
2716 emit_int8(0x66); // size prefix
2717 case 2:
2718 emit_int8(0x66); // size prefix
2719 case 1:
2720 emit_int8((unsigned char)0x90);
2721 // nop
2722 break;
2723 default:
2724 assert(i == 0, " ");
2725 }
2726 return;
2727 }
2728
2729 // Using nops with size prefixes "0x66 0x90".
2730 // From AMD Optimization Guide:
2731 // 1: 0x90
2732 // 2: 0x66 0x90
2733 // 3: 0x66 0x66 0x90
2734 // 4: 0x66 0x66 0x66 0x90
2735 // 5: 0x66 0x66 0x90 0x66 0x90
2736 // 6: 0x66 0x66 0x90 0x66 0x66 0x90
2737 // 7: 0x66 0x66 0x66 0x90 0x66 0x66 0x90
2738 // 8: 0x66 0x66 0x66 0x90 0x66 0x66 0x66 0x90
2739 // 9: 0x66 0x66 0x90 0x66 0x66 0x90 0x66 0x66 0x90
2740 // 10: 0x66 0x66 0x66 0x90 0x66 0x66 0x90 0x66 0x66 0x90
2741 //
2742 while(i > 12) {
2743 i -= 4;
2744 emit_int8(0x66); // size prefix
2745 emit_int8(0x66);
2746 emit_int8(0x66);
2747 emit_int8((unsigned char)0x90);
2748 // nop
2749 }
2750 // 1 - 12 nops
2751 if(i > 8) {
2752 if(i > 9) {
2753 i -= 1;
2754 emit_int8(0x66);
2755 }
2756 i -= 3;
2757 emit_int8(0x66);
2758 emit_int8(0x66);
2759 emit_int8((unsigned char)0x90);
2760 }
2761 // 1 - 8 nops
2762 if(i > 4) {
2763 if(i > 6) {
2764 i -= 1;
2765 emit_int8(0x66);
2766 }
2767 i -= 3;
2768 emit_int8(0x66);
2769 emit_int8(0x66);
2770 emit_int8((unsigned char)0x90);
2771 }
2772 switch (i) {
2773 case 4:
2774 emit_int8(0x66);
2775 case 3:
2776 emit_int8(0x66);
2777 case 2:
2778 emit_int8(0x66);
2779 case 1:
2780 emit_int8((unsigned char)0x90);
2781 break;
2782 default:
2783 assert(i == 0, " ");
2784 }
2785 }
2786
2787 void Assembler::notl(Register dst) {
2788 int encode = prefix_and_encode(dst->encoding());
2789 emit_int8((unsigned char)0xF7);
2790 emit_int8((unsigned char)(0xD0 | encode));
2791 }
2792
2793 void Assembler::orl(Address dst, int32_t imm32) {
2794 InstructionMark im(this);
2795 prefix(dst);
2796 emit_arith_operand(0x81, rcx, dst, imm32);
2797 }
2798
2799 void Assembler::orl(Register dst, int32_t imm32) {
2800 prefix(dst);
2801 emit_arith(0x81, 0xC8, dst, imm32);
2802 }
2803
2804 void Assembler::orl(Register dst, Address src) {
2805 InstructionMark im(this);
2806 prefix(src, dst);
2807 emit_int8(0x0B);
2808 emit_operand(dst, src);
2809 }
2810
2811 void Assembler::orl(Register dst, Register src) {
2812 (void) prefix_and_encode(dst->encoding(), src->encoding());
2813 emit_arith(0x0B, 0xC0, dst, src);
2814 }
2815
2816 void Assembler::orl(Address dst, Register src) {
2817 InstructionMark im(this);
2818 prefix(dst, src);
2819 emit_int8(0x09);
2820 emit_operand(src, dst);
2821 }
2822
2823 void Assembler::packuswb(XMMRegister dst, Address src) {
2824 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2825 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
2826 if (VM_Version::supports_evex()) {
2827 tuple_type = EVEX_FV;
2828 input_size_in_bits = EVEX_32bit;
2829 }
2830 emit_simd_arith(0x67, dst, src, VEX_SIMD_66,
2831 false, (VM_Version::supports_avx512dq() == false));
2832 }
2833
2834 void Assembler::packuswb(XMMRegister dst, XMMRegister src) {
2835 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2836 emit_simd_arith(0x67, dst, src, VEX_SIMD_66,
2837 false, (VM_Version::supports_avx512dq() == false));
2838 }
2839
2840 void Assembler::vpackuswb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
2841 assert(UseAVX > 0, "some form of AVX must be enabled");
2842 emit_vex_arith(0x67, dst, nds, src, VEX_SIMD_66, vector_len,
2843 false, (VM_Version::supports_avx512dq() == false));
2844 }
2845
2846 void Assembler::vpermq(XMMRegister dst, XMMRegister src, int imm8, int vector_len) {
2847 assert(VM_Version::supports_avx2(), "");
2848 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, false,
2849 VEX_OPCODE_0F_3A, true, vector_len);
2850 emit_int8(0x00);
2851 emit_int8(0xC0 | encode);
2852 emit_int8(imm8);
2853 }
2854
2855 void Assembler::pause() {
2856 emit_int8((unsigned char)0xF3);
2857 emit_int8((unsigned char)0x90);
2858 }
2859
2860 void Assembler::pcmpestri(XMMRegister dst, Address src, int imm8) {
2861 assert(VM_Version::supports_sse4_2(), "");
2862 InstructionMark im(this);
2863 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, false, VEX_OPCODE_0F_3A,
2864 false, AVX_128bit, true);
2865 emit_int8(0x61);
2866 emit_operand(dst, src);
2867 emit_int8(imm8);
2868 }
2869
2870 void Assembler::pcmpestri(XMMRegister dst, XMMRegister src, int imm8) {
2871 assert(VM_Version::supports_sse4_2(), "");
2872 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, false,
2873 VEX_OPCODE_0F_3A, false, AVX_128bit, true);
2874 emit_int8(0x61);
2875 emit_int8((unsigned char)(0xC0 | encode));
2876 emit_int8(imm8);
2877 }
2878
2879 void Assembler::pextrd(Register dst, XMMRegister src, int imm8) {
2880 assert(VM_Version::supports_sse4_1(), "");
2881 int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_66, true, VEX_OPCODE_0F_3A,
2882 false, AVX_128bit, (VM_Version::supports_avx512dq() == false));
2883 emit_int8(0x16);
2884 emit_int8((unsigned char)(0xC0 | encode));
2885 emit_int8(imm8);
2886 }
2887
2888 void Assembler::pextrq(Register dst, XMMRegister src, int imm8) {
2889 assert(VM_Version::supports_sse4_1(), "");
2890 int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_66, true, VEX_OPCODE_0F_3A,
2891 false, AVX_128bit, (VM_Version::supports_avx512dq() == false));
2892 emit_int8(0x16);
2893 emit_int8((unsigned char)(0xC0 | encode));
2894 emit_int8(imm8);
2895 }
2896
2897 void Assembler::pinsrd(XMMRegister dst, Register src, int imm8) {
2898 assert(VM_Version::supports_sse4_1(), "");
2899 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_66, true, VEX_OPCODE_0F_3A,
2900 false, AVX_128bit, (VM_Version::supports_avx512dq() == false));
2901 emit_int8(0x22);
2902 emit_int8((unsigned char)(0xC0 | encode));
2903 emit_int8(imm8);
2904 }
2905
2906 void Assembler::pinsrq(XMMRegister dst, Register src, int imm8) {
2907 assert(VM_Version::supports_sse4_1(), "");
2908 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_66, true, VEX_OPCODE_0F_3A,
2909 false, AVX_128bit, (VM_Version::supports_avx512dq() == false));
2910 emit_int8(0x22);
2911 emit_int8((unsigned char)(0xC0 | encode));
2912 emit_int8(imm8);
2913 }
2914
2915 void Assembler::pmovzxbw(XMMRegister dst, Address src) {
2916 assert(VM_Version::supports_sse4_1(), "");
2917 if (VM_Version::supports_evex()) {
2918 tuple_type = EVEX_HVM;
2919 }
2920 InstructionMark im(this);
2921 simd_prefix(dst, src, VEX_SIMD_66, false, VEX_OPCODE_0F_38);
2922 emit_int8(0x30);
2923 emit_operand(dst, src);
2924 }
2925
2926 void Assembler::pmovzxbw(XMMRegister dst, XMMRegister src) {
2927 assert(VM_Version::supports_sse4_1(), "");
2928 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, false, VEX_OPCODE_0F_38);
2929 emit_int8(0x30);
2930 emit_int8((unsigned char)(0xC0 | encode));
2931 }
2932
2933 // generic
2934 void Assembler::pop(Register dst) {
2935 int encode = prefix_and_encode(dst->encoding());
2936 emit_int8(0x58 | encode);
2937 }
2938
2939 void Assembler::popcntl(Register dst, Address src) {
2940 assert(VM_Version::supports_popcnt(), "must support");
2941 InstructionMark im(this);
2942 emit_int8((unsigned char)0xF3);
2943 prefix(src, dst);
2944 emit_int8(0x0F);
2945 emit_int8((unsigned char)0xB8);
2946 emit_operand(dst, src);
2947 }
2948
2949 void Assembler::popcntl(Register dst, Register src) {
2950 assert(VM_Version::supports_popcnt(), "must support");
2951 emit_int8((unsigned char)0xF3);
2952 int encode = prefix_and_encode(dst->encoding(), src->encoding());
2953 emit_int8(0x0F);
2954 emit_int8((unsigned char)0xB8);
2955 emit_int8((unsigned char)(0xC0 | encode));
2956 }
2957
2958 void Assembler::popf() {
2959 emit_int8((unsigned char)0x9D);
2960 }
2961
2962 #ifndef _LP64 // no 32bit push/pop on amd64
2963 void Assembler::popl(Address dst) {
2964 // NOTE: this will adjust stack by 8byte on 64bits
2965 InstructionMark im(this);
2966 prefix(dst);
2967 emit_int8((unsigned char)0x8F);
2968 emit_operand(rax, dst);
2969 }
2970 #endif
2971
2972 void Assembler::prefetch_prefix(Address src) {
2973 prefix(src);
2974 emit_int8(0x0F);
2975 }
2976
2977 void Assembler::prefetchnta(Address src) {
2978 NOT_LP64(assert(VM_Version::supports_sse(), "must support"));
2979 InstructionMark im(this);
2980 prefetch_prefix(src);
2981 emit_int8(0x18);
2982 emit_operand(rax, src); // 0, src
2983 }
2984
2985 void Assembler::prefetchr(Address src) {
2986 assert(VM_Version::supports_3dnow_prefetch(), "must support");
2987 InstructionMark im(this);
2988 prefetch_prefix(src);
2989 emit_int8(0x0D);
2990 emit_operand(rax, src); // 0, src
2991 }
2992
2993 void Assembler::prefetcht0(Address src) {
2994 NOT_LP64(assert(VM_Version::supports_sse(), "must support"));
2995 InstructionMark im(this);
2996 prefetch_prefix(src);
2997 emit_int8(0x18);
2998 emit_operand(rcx, src); // 1, src
2999 }
3000
3001 void Assembler::prefetcht1(Address src) {
3002 NOT_LP64(assert(VM_Version::supports_sse(), "must support"));
3003 InstructionMark im(this);
3004 prefetch_prefix(src);
3005 emit_int8(0x18);
3006 emit_operand(rdx, src); // 2, src
3007 }
3008
3009 void Assembler::prefetcht2(Address src) {
3010 NOT_LP64(assert(VM_Version::supports_sse(), "must support"));
3011 InstructionMark im(this);
3012 prefetch_prefix(src);
3013 emit_int8(0x18);
3014 emit_operand(rbx, src); // 3, src
3015 }
3016
3017 void Assembler::prefetchw(Address src) {
3018 assert(VM_Version::supports_3dnow_prefetch(), "must support");
3019 InstructionMark im(this);
3020 prefetch_prefix(src);
3021 emit_int8(0x0D);
3022 emit_operand(rcx, src); // 1, src
3023 }
3024
3025 void Assembler::prefix(Prefix p) {
3026 emit_int8(p);
3027 }
3028
3029 void Assembler::pshufb(XMMRegister dst, XMMRegister src) {
3030 assert(VM_Version::supports_ssse3(), "");
3031 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, false, VEX_OPCODE_0F_38,
3032 false, AVX_128bit, (VM_Version::supports_avx512bw() == false));
3033 emit_int8(0x00);
3034 emit_int8((unsigned char)(0xC0 | encode));
3035 }
3036
3037 void Assembler::pshufb(XMMRegister dst, Address src) {
3038 assert(VM_Version::supports_ssse3(), "");
3039 if (VM_Version::supports_evex()) {
3040 tuple_type = EVEX_FVM;
3041 }
3042 InstructionMark im(this);
3043 simd_prefix(dst, dst, src, VEX_SIMD_66, false, VEX_OPCODE_0F_38,
3044 false, AVX_128bit, (VM_Version::supports_avx512bw() == false));
3045 emit_int8(0x00);
3046 emit_operand(dst, src);
3047 }
3048
3049 void Assembler::pshufd(XMMRegister dst, XMMRegister src, int mode) {
3050 assert(isByte(mode), "invalid value");
3051 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3052 emit_simd_arith_nonds(0x70, dst, src, VEX_SIMD_66);
3053 emit_int8(mode & 0xFF);
3054
3055 }
3056
3057 void Assembler::pshufd(XMMRegister dst, Address src, int mode) {
3058 assert(isByte(mode), "invalid value");
3059 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3060 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
3061 if (VM_Version::supports_evex()) {
3062 tuple_type = EVEX_FV;
3063 input_size_in_bits = EVEX_32bit;
3064 }
3065 InstructionMark im(this);
3066 simd_prefix(dst, src, VEX_SIMD_66, false);
3067 emit_int8(0x70);
3068 emit_operand(dst, src);
3069 emit_int8(mode & 0xFF);
3070 }
3071
3072 void Assembler::pshuflw(XMMRegister dst, XMMRegister src, int mode) {
3073 assert(isByte(mode), "invalid value");
3074 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3075 emit_simd_arith_nonds(0x70, dst, src, VEX_SIMD_F2, false,
3076 (VM_Version::supports_avx512bw() == false));
3077 emit_int8(mode & 0xFF);
3078 }
3079
3080 void Assembler::pshuflw(XMMRegister dst, Address src, int mode) {
3081 assert(isByte(mode), "invalid value");
3082 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3083 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
3084 if (VM_Version::supports_evex()) {
3085 tuple_type = EVEX_FVM;
3086 }
3087 InstructionMark im(this);
3088 simd_prefix(dst, xnoreg, src, VEX_SIMD_F2, false, VEX_OPCODE_0F,
3089 false, AVX_128bit, (VM_Version::supports_avx512bw() == false));
3090 emit_int8(0x70);
3091 emit_operand(dst, src);
3092 emit_int8(mode & 0xFF);
3093 }
3094
3095 void Assembler::psrldq(XMMRegister dst, int shift) {
3096 // Shift 128 bit value in xmm register by number of bytes.
3097 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3098 int encode = simd_prefix_and_encode(xmm3, dst, dst, VEX_SIMD_66, true, VEX_OPCODE_0F,
3099 false, AVX_128bit, (VM_Version::supports_avx512bw() == false));
3100 emit_int8(0x73);
3101 emit_int8((unsigned char)(0xC0 | encode));
3102 emit_int8(shift);
3103 }
3104
3105 void Assembler::ptest(XMMRegister dst, Address src) {
3106 assert(VM_Version::supports_sse4_1(), "");
3107 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
3108 InstructionMark im(this);
3109 simd_prefix(dst, src, VEX_SIMD_66, false, VEX_OPCODE_0F_38);
3110 emit_int8(0x17);
3111 emit_operand(dst, src);
3112 }
3113
3114 void Assembler::ptest(XMMRegister dst, XMMRegister src) {
3115 assert(VM_Version::supports_sse4_1(), "");
3116 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66,
3117 false, VEX_OPCODE_0F_38);
3118 emit_int8(0x17);
3119 emit_int8((unsigned char)(0xC0 | encode));
3120 }
3121
3122 void Assembler::vptest(XMMRegister dst, Address src) {
3123 assert(VM_Version::supports_avx(), "");
3124 InstructionMark im(this);
3125 int vector_len = AVX_256bit;
3126 assert(dst != xnoreg, "sanity");
3127 int dst_enc = dst->encoding();
3128 // swap src<->dst for encoding
3129 vex_prefix(src, 0, dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_38, false, vector_len);
3130 emit_int8(0x17);
3131 emit_operand(dst, src);
3132 }
3133
3134 void Assembler::vptest(XMMRegister dst, XMMRegister src) {
3135 assert(VM_Version::supports_avx(), "");
3136 int vector_len = AVX_256bit;
3137 int encode = vex_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66,
3138 vector_len, VEX_OPCODE_0F_38);
3139 emit_int8(0x17);
3140 emit_int8((unsigned char)(0xC0 | encode));
3141 }
3142
3143 void Assembler::punpcklbw(XMMRegister dst, Address src) {
3144 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3145 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
3146 if (VM_Version::supports_evex()) {
3147 tuple_type = EVEX_FVM;
3148 }
3149 emit_simd_arith(0x60, dst, src, VEX_SIMD_66);
3150 }
3151
3152 void Assembler::punpcklbw(XMMRegister dst, XMMRegister src) {
3153 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3154 emit_simd_arith(0x60, dst, src, VEX_SIMD_66);
3155 }
3156
3157 void Assembler::punpckldq(XMMRegister dst, Address src) {
3158 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3159 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
3160 if (VM_Version::supports_evex()) {
3161 tuple_type = EVEX_FV;
3162 input_size_in_bits = EVEX_32bit;
3163 }
3164 emit_simd_arith(0x62, dst, src, VEX_SIMD_66);
3165 }
3166
3167 void Assembler::punpckldq(XMMRegister dst, XMMRegister src) {
3168 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3169 emit_simd_arith(0x62, dst, src, VEX_SIMD_66);
3170 }
3171
3172 void Assembler::punpcklqdq(XMMRegister dst, XMMRegister src) {
3173 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3174 emit_simd_arith(0x6C, dst, src, VEX_SIMD_66);
3175 }
3176
3177 void Assembler::push(int32_t imm32) {
3178 // in 64bits we push 64bits onto the stack but only
3179 // take a 32bit immediate
3180 emit_int8(0x68);
3181 emit_int32(imm32);
3182 }
3183
3184 void Assembler::push(Register src) {
3185 int encode = prefix_and_encode(src->encoding());
3186
3187 emit_int8(0x50 | encode);
3188 }
3189
3190 void Assembler::pushf() {
3191 emit_int8((unsigned char)0x9C);
3192 }
3193
3194 #ifndef _LP64 // no 32bit push/pop on amd64
3195 void Assembler::pushl(Address src) {
3196 // Note this will push 64bit on 64bit
3197 InstructionMark im(this);
3198 prefix(src);
3199 emit_int8((unsigned char)0xFF);
3200 emit_operand(rsi, src);
3201 }
3202 #endif
3203
3204 void Assembler::rcll(Register dst, int imm8) {
3205 assert(isShiftCount(imm8), "illegal shift count");
3206 int encode = prefix_and_encode(dst->encoding());
3207 if (imm8 == 1) {
3208 emit_int8((unsigned char)0xD1);
3209 emit_int8((unsigned char)(0xD0 | encode));
3210 } else {
3211 emit_int8((unsigned char)0xC1);
3212 emit_int8((unsigned char)0xD0 | encode);
3213 emit_int8(imm8);
3214 }
3215 }
3216
3217 void Assembler::rdtsc() {
3218 emit_int8((unsigned char)0x0F);
3219 emit_int8((unsigned char)0x31);
3220 }
3221
3222 // copies data from [esi] to [edi] using rcx pointer sized words
3223 // generic
3224 void Assembler::rep_mov() {
3225 emit_int8((unsigned char)0xF3);
3226 // MOVSQ
3227 LP64_ONLY(prefix(REX_W));
3228 emit_int8((unsigned char)0xA5);
3229 }
3230
3231 // sets rcx bytes with rax, value at [edi]
3232 void Assembler::rep_stosb() {
3233 emit_int8((unsigned char)0xF3); // REP
3234 LP64_ONLY(prefix(REX_W));
3235 emit_int8((unsigned char)0xAA); // STOSB
3236 }
3237
3238 // sets rcx pointer sized words with rax, value at [edi]
3239 // generic
3240 void Assembler::rep_stos() {
3241 emit_int8((unsigned char)0xF3); // REP
3242 LP64_ONLY(prefix(REX_W)); // LP64:STOSQ, LP32:STOSD
3243 emit_int8((unsigned char)0xAB);
3244 }
3245
3246 // scans rcx pointer sized words at [edi] for occurance of rax,
3247 // generic
3248 void Assembler::repne_scan() { // repne_scan
3249 emit_int8((unsigned char)0xF2);
3250 // SCASQ
3251 LP64_ONLY(prefix(REX_W));
3252 emit_int8((unsigned char)0xAF);
3253 }
3254
3255 #ifdef _LP64
3256 // scans rcx 4 byte words at [edi] for occurance of rax,
3257 // generic
3258 void Assembler::repne_scanl() { // repne_scan
3259 emit_int8((unsigned char)0xF2);
3260 // SCASL
3261 emit_int8((unsigned char)0xAF);
3262 }
3263 #endif
3264
3265 void Assembler::ret(int imm16) {
3266 if (imm16 == 0) {
3267 emit_int8((unsigned char)0xC3);
3268 } else {
3269 emit_int8((unsigned char)0xC2);
3270 emit_int16(imm16);
3271 }
3272 }
3273
3274 void Assembler::sahf() {
3275 #ifdef _LP64
3276 // Not supported in 64bit mode
3277 ShouldNotReachHere();
3278 #endif
3279 emit_int8((unsigned char)0x9E);
3280 }
3281
3282 void Assembler::sarl(Register dst, int imm8) {
3283 int encode = prefix_and_encode(dst->encoding());
3284 assert(isShiftCount(imm8), "illegal shift count");
3285 if (imm8 == 1) {
3286 emit_int8((unsigned char)0xD1);
3287 emit_int8((unsigned char)(0xF8 | encode));
3288 } else {
3289 emit_int8((unsigned char)0xC1);
3290 emit_int8((unsigned char)(0xF8 | encode));
3291 emit_int8(imm8);
3292 }
3293 }
3294
3295 void Assembler::sarl(Register dst) {
3296 int encode = prefix_and_encode(dst->encoding());
3297 emit_int8((unsigned char)0xD3);
3298 emit_int8((unsigned char)(0xF8 | encode));
3299 }
3300
3301 void Assembler::sbbl(Address dst, int32_t imm32) {
3302 InstructionMark im(this);
3303 prefix(dst);
3304 emit_arith_operand(0x81, rbx, dst, imm32);
3305 }
3306
3307 void Assembler::sbbl(Register dst, int32_t imm32) {
3308 prefix(dst);
3309 emit_arith(0x81, 0xD8, dst, imm32);
3310 }
3311
3312
3313 void Assembler::sbbl(Register dst, Address src) {
3314 InstructionMark im(this);
3315 prefix(src, dst);
3316 emit_int8(0x1B);
3317 emit_operand(dst, src);
3318 }
3319
3320 void Assembler::sbbl(Register dst, Register src) {
3321 (void) prefix_and_encode(dst->encoding(), src->encoding());
3322 emit_arith(0x1B, 0xC0, dst, src);
3323 }
3324
3325 void Assembler::setb(Condition cc, Register dst) {
3326 assert(0 <= cc && cc < 16, "illegal cc");
3327 int encode = prefix_and_encode(dst->encoding(), true);
3328 emit_int8(0x0F);
3329 emit_int8((unsigned char)0x90 | cc);
3330 emit_int8((unsigned char)(0xC0 | encode));
3331 }
3332
3333 void Assembler::shll(Register dst, int imm8) {
3334 assert(isShiftCount(imm8), "illegal shift count");
3335 int encode = prefix_and_encode(dst->encoding());
3336 if (imm8 == 1 ) {
3337 emit_int8((unsigned char)0xD1);
3338 emit_int8((unsigned char)(0xE0 | encode));
3339 } else {
3340 emit_int8((unsigned char)0xC1);
3341 emit_int8((unsigned char)(0xE0 | encode));
3342 emit_int8(imm8);
3343 }
3344 }
3345
3346 void Assembler::shll(Register dst) {
3347 int encode = prefix_and_encode(dst->encoding());
3348 emit_int8((unsigned char)0xD3);
3349 emit_int8((unsigned char)(0xE0 | encode));
3350 }
3351
3352 void Assembler::shrl(Register dst, int imm8) {
3353 assert(isShiftCount(imm8), "illegal shift count");
3354 int encode = prefix_and_encode(dst->encoding());
3355 emit_int8((unsigned char)0xC1);
3356 emit_int8((unsigned char)(0xE8 | encode));
3357 emit_int8(imm8);
3358 }
3359
3360 void Assembler::shrl(Register dst) {
3361 int encode = prefix_and_encode(dst->encoding());
3362 emit_int8((unsigned char)0xD3);
3363 emit_int8((unsigned char)(0xE8 | encode));
3364 }
3365
3366 // copies a single word from [esi] to [edi]
3367 void Assembler::smovl() {
3368 emit_int8((unsigned char)0xA5);
3369 }
3370
3371 void Assembler::sqrtsd(XMMRegister dst, XMMRegister src) {
3372 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3373 if (VM_Version::supports_evex()) {
3374 emit_simd_arith_q(0x51, dst, src, VEX_SIMD_F2);
3375 } else {
3376 emit_simd_arith(0x51, dst, src, VEX_SIMD_F2);
3377 }
3378 }
3379
3380 void Assembler::sqrtsd(XMMRegister dst, Address src) {
3381 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3382 if (VM_Version::supports_evex()) {
3383 tuple_type = EVEX_T1S;
3384 input_size_in_bits = EVEX_64bit;
3385 emit_simd_arith_q(0x51, dst, src, VEX_SIMD_F2);
3386 } else {
3387 emit_simd_arith(0x51, dst, src, VEX_SIMD_F2);
3388 }
3389 }
3390
3391 void Assembler::sqrtss(XMMRegister dst, XMMRegister src) {
3392 NOT_LP64(assert(VM_Version::supports_sse(), ""));
3393 emit_simd_arith(0x51, dst, src, VEX_SIMD_F3);
3394 }
3395
3396 void Assembler::std() {
3397 emit_int8((unsigned char)0xFD);
3398 }
3399
3400 void Assembler::sqrtss(XMMRegister dst, Address src) {
3401 NOT_LP64(assert(VM_Version::supports_sse(), ""));
3402 if (VM_Version::supports_evex()) {
3403 tuple_type = EVEX_T1S;
3404 input_size_in_bits = EVEX_32bit;
3405 }
3406 emit_simd_arith(0x51, dst, src, VEX_SIMD_F3);
3407 }
3408
3409 void Assembler::stmxcsr( Address dst) {
3410 NOT_LP64(assert(VM_Version::supports_sse(), ""));
3411 InstructionMark im(this);
3412 prefix(dst);
3413 emit_int8(0x0F);
3414 emit_int8((unsigned char)0xAE);
3415 emit_operand(as_Register(3), dst);
3416 }
3417
3418 void Assembler::subl(Address dst, int32_t imm32) {
3419 InstructionMark im(this);
3420 prefix(dst);
3421 emit_arith_operand(0x81, rbp, dst, imm32);
3422 }
3423
3424 void Assembler::subl(Address dst, Register src) {
3425 InstructionMark im(this);
3426 prefix(dst, src);
3427 emit_int8(0x29);
3428 emit_operand(src, dst);
3429 }
3430
3431 void Assembler::subl(Register dst, int32_t imm32) {
3432 prefix(dst);
3433 emit_arith(0x81, 0xE8, dst, imm32);
3434 }
3435
3436 // Force generation of a 4 byte immediate value even if it fits into 8bit
3437 void Assembler::subl_imm32(Register dst, int32_t imm32) {
3438 prefix(dst);
3439 emit_arith_imm32(0x81, 0xE8, dst, imm32);
3440 }
3441
3442 void Assembler::subl(Register dst, Address src) {
3443 InstructionMark im(this);
3444 prefix(src, dst);
3445 emit_int8(0x2B);
3446 emit_operand(dst, src);
3447 }
3448
3449 void Assembler::subl(Register dst, Register src) {
3450 (void) prefix_and_encode(dst->encoding(), src->encoding());
3451 emit_arith(0x2B, 0xC0, dst, src);
3452 }
3453
3454 void Assembler::subsd(XMMRegister dst, XMMRegister src) {
3455 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3456 if (VM_Version::supports_evex()) {
3457 emit_simd_arith_q(0x5C, dst, src, VEX_SIMD_F2);
3458 } else {
3459 emit_simd_arith(0x5C, dst, src, VEX_SIMD_F2);
3460 }
3461 }
3462
3463 void Assembler::subsd(XMMRegister dst, Address src) {
3464 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3465 if (VM_Version::supports_evex()) {
3466 tuple_type = EVEX_T1S;
3467 input_size_in_bits = EVEX_64bit;
3468 }
3469 emit_simd_arith_q(0x5C, dst, src, VEX_SIMD_F2);
3470 }
3471
3472 void Assembler::subss(XMMRegister dst, XMMRegister src) {
3473 NOT_LP64(assert(VM_Version::supports_sse(), ""));
3474 emit_simd_arith(0x5C, dst, src, VEX_SIMD_F3);
3475 }
3476
3477 void Assembler::subss(XMMRegister dst, Address src) {
3478 NOT_LP64(assert(VM_Version::supports_sse(), ""));
3479 if (VM_Version::supports_evex()) {
3480 tuple_type = EVEX_T1S;
3481 input_size_in_bits = EVEX_32bit;
3482 }
3483 emit_simd_arith(0x5C, dst, src, VEX_SIMD_F3);
3484 }
3485
3486 void Assembler::testb(Register dst, int imm8) {
3487 NOT_LP64(assert(dst->has_byte_register(), "must have byte register"));
3488 (void) prefix_and_encode(dst->encoding(), true);
3489 emit_arith_b(0xF6, 0xC0, dst, imm8);
3490 }
3491
3492 void Assembler::testl(Register dst, int32_t imm32) {
3493 // not using emit_arith because test
3494 // doesn't support sign-extension of
3495 // 8bit operands
3496 int encode = dst->encoding();
3497 if (encode == 0) {
3498 emit_int8((unsigned char)0xA9);
3499 } else {
3500 encode = prefix_and_encode(encode);
3501 emit_int8((unsigned char)0xF7);
3502 emit_int8((unsigned char)(0xC0 | encode));
3503 }
3504 emit_int32(imm32);
3505 }
3506
3507 void Assembler::testl(Register dst, Register src) {
3508 (void) prefix_and_encode(dst->encoding(), src->encoding());
3509 emit_arith(0x85, 0xC0, dst, src);
3510 }
3511
3512 void Assembler::testl(Register dst, Address src) {
3513 InstructionMark im(this);
3514 prefix(src, dst);
3515 emit_int8((unsigned char)0x85);
3516 emit_operand(dst, src);
3517 }
3518
3519 void Assembler::tzcntl(Register dst, Register src) {
3520 assert(VM_Version::supports_bmi1(), "tzcnt instruction not supported");
3521 emit_int8((unsigned char)0xF3);
3522 int encode = prefix_and_encode(dst->encoding(), src->encoding());
3523 emit_int8(0x0F);
3524 emit_int8((unsigned char)0xBC);
3525 emit_int8((unsigned char)0xC0 | encode);
3526 }
3527
3528 void Assembler::tzcntq(Register dst, Register src) {
3529 assert(VM_Version::supports_bmi1(), "tzcnt instruction not supported");
3530 emit_int8((unsigned char)0xF3);
3531 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
3532 emit_int8(0x0F);
3533 emit_int8((unsigned char)0xBC);
3534 emit_int8((unsigned char)(0xC0 | encode));
3535 }
3536
3537 void Assembler::ucomisd(XMMRegister dst, Address src) {
3538 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3539 if (VM_Version::supports_evex()) {
3540 tuple_type = EVEX_T1S;
3541 input_size_in_bits = EVEX_64bit;
3542 emit_simd_arith_nonds_q(0x2E, dst, src, VEX_SIMD_66, true);
3543 } else {
3544 emit_simd_arith_nonds(0x2E, dst, src, VEX_SIMD_66);
3545 }
3546 }
3547
3548 void Assembler::ucomisd(XMMRegister dst, XMMRegister src) {
3549 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3550 if (VM_Version::supports_evex()) {
3551 emit_simd_arith_nonds_q(0x2E, dst, src, VEX_SIMD_66, true);
3552 } else {
3553 emit_simd_arith_nonds(0x2E, dst, src, VEX_SIMD_66);
3554 }
3555 }
3556
3557 void Assembler::ucomiss(XMMRegister dst, Address src) {
3558 NOT_LP64(assert(VM_Version::supports_sse(), ""));
3559 if (VM_Version::supports_evex()) {
3560 tuple_type = EVEX_T1S;
3561 input_size_in_bits = EVEX_32bit;
3562 }
3563 emit_simd_arith_nonds(0x2E, dst, src, VEX_SIMD_NONE, true);
3564 }
3565
3566 void Assembler::ucomiss(XMMRegister dst, XMMRegister src) {
3567 NOT_LP64(assert(VM_Version::supports_sse(), ""));
3568 emit_simd_arith_nonds(0x2E, dst, src, VEX_SIMD_NONE, true);
3569 }
3570
3571 void Assembler::xabort(int8_t imm8) {
3572 emit_int8((unsigned char)0xC6);
3573 emit_int8((unsigned char)0xF8);
3574 emit_int8((unsigned char)(imm8 & 0xFF));
3575 }
3576
3577 void Assembler::xaddl(Address dst, Register src) {
3578 InstructionMark im(this);
3579 prefix(dst, src);
3580 emit_int8(0x0F);
3581 emit_int8((unsigned char)0xC1);
3582 emit_operand(src, dst);
3583 }
3584
3585 void Assembler::xbegin(Label& abort, relocInfo::relocType rtype) {
3586 InstructionMark im(this);
3587 relocate(rtype);
3588 if (abort.is_bound()) {
3589 address entry = target(abort);
3590 assert(entry != NULL, "abort entry NULL");
3591 intptr_t offset = entry - pc();
3592 emit_int8((unsigned char)0xC7);
3593 emit_int8((unsigned char)0xF8);
3594 emit_int32(offset - 6); // 2 opcode + 4 address
3595 } else {
3596 abort.add_patch_at(code(), locator());
3597 emit_int8((unsigned char)0xC7);
3598 emit_int8((unsigned char)0xF8);
3599 emit_int32(0);
3600 }
3601 }
3602
3603 void Assembler::xchgl(Register dst, Address src) { // xchg
3604 InstructionMark im(this);
3605 prefix(src, dst);
3606 emit_int8((unsigned char)0x87);
3607 emit_operand(dst, src);
3608 }
3609
3610 void Assembler::xchgl(Register dst, Register src) {
3611 int encode = prefix_and_encode(dst->encoding(), src->encoding());
3612 emit_int8((unsigned char)0x87);
3613 emit_int8((unsigned char)(0xC0 | encode));
3614 }
3615
3616 void Assembler::xend() {
3617 emit_int8((unsigned char)0x0F);
3618 emit_int8((unsigned char)0x01);
3619 emit_int8((unsigned char)0xD5);
3620 }
3621
3622 void Assembler::xgetbv() {
3623 emit_int8(0x0F);
3624 emit_int8(0x01);
3625 emit_int8((unsigned char)0xD0);
3626 }
3627
3628 void Assembler::xorl(Register dst, int32_t imm32) {
3629 prefix(dst);
3630 emit_arith(0x81, 0xF0, dst, imm32);
3631 }
3632
3633 void Assembler::xorl(Register dst, Address src) {
3634 InstructionMark im(this);
3635 prefix(src, dst);
3636 emit_int8(0x33);
3637 emit_operand(dst, src);
3638 }
3639
3640 void Assembler::xorl(Register dst, Register src) {
3641 (void) prefix_and_encode(dst->encoding(), src->encoding());
3642 emit_arith(0x33, 0xC0, dst, src);
3643 }
3644
3645
3646 // AVX 3-operands scalar float-point arithmetic instructions
3647
3648 void Assembler::vaddsd(XMMRegister dst, XMMRegister nds, Address src) {
3649 assert(VM_Version::supports_avx(), "");
3650 if (VM_Version::supports_evex()) {
3651 tuple_type = EVEX_T1S;
3652 input_size_in_bits = EVEX_64bit;
3653 emit_vex_arith_q(0x58, dst, nds, src, VEX_SIMD_F2, AVX_128bit);
3654 } else {
3655 emit_vex_arith(0x58, dst, nds, src, VEX_SIMD_F2, AVX_128bit);
3656 }
3657 }
3658
3659 void Assembler::vaddsd(XMMRegister dst, XMMRegister nds, XMMRegister src) {
3660 assert(VM_Version::supports_avx(), "");
3661 if (VM_Version::supports_evex()) {
3662 emit_vex_arith_q(0x58, dst, nds, src, VEX_SIMD_F2, AVX_128bit);
3663 } else {
3664 emit_vex_arith(0x58, dst, nds, src, VEX_SIMD_F2, AVX_128bit);
3665 }
3666 }
3667
3668 void Assembler::vaddss(XMMRegister dst, XMMRegister nds, Address src) {
3669 assert(VM_Version::supports_avx(), "");
3670 if (VM_Version::supports_evex()) {
3671 tuple_type = EVEX_T1S;
3672 input_size_in_bits = EVEX_32bit;
3673 }
3674 emit_vex_arith(0x58, dst, nds, src, VEX_SIMD_F3, AVX_128bit);
3675 }
3676
3677 void Assembler::vaddss(XMMRegister dst, XMMRegister nds, XMMRegister src) {
3678 assert(VM_Version::supports_avx(), "");
3679 emit_vex_arith(0x58, dst, nds, src, VEX_SIMD_F3, AVX_128bit);
3680 }
3681
3682 void Assembler::vdivsd(XMMRegister dst, XMMRegister nds, Address src) {
3683 assert(VM_Version::supports_avx(), "");
3684 if (VM_Version::supports_evex()) {
3685 tuple_type = EVEX_T1S;
3686 input_size_in_bits = EVEX_64bit;
3687 emit_vex_arith_q(0x5E, dst, nds, src, VEX_SIMD_F2, AVX_128bit);
3688 } else {
3689 emit_vex_arith(0x5E, dst, nds, src, VEX_SIMD_F2, AVX_128bit);
3690 }
3691 }
3692
3693 void Assembler::vdivsd(XMMRegister dst, XMMRegister nds, XMMRegister src) {
3694 assert(VM_Version::supports_avx(), "");
3695 if (VM_Version::supports_evex()) {
3696 emit_vex_arith_q(0x5E, dst, nds, src, VEX_SIMD_F2, AVX_128bit);
3697 } else {
3698 emit_vex_arith(0x5E, dst, nds, src, VEX_SIMD_F2, AVX_128bit);
3699 }
3700 }
3701
3702 void Assembler::vdivss(XMMRegister dst, XMMRegister nds, Address src) {
3703 assert(VM_Version::supports_avx(), "");
3704 if (VM_Version::supports_evex()) {
3705 tuple_type = EVEX_T1S;
3706 input_size_in_bits = EVEX_32bit;
3707 }
3708 emit_vex_arith(0x5E, dst, nds, src, VEX_SIMD_F3, AVX_128bit);
3709 }
3710
3711 void Assembler::vdivss(XMMRegister dst, XMMRegister nds, XMMRegister src) {
3712 assert(VM_Version::supports_avx(), "");
3713 emit_vex_arith(0x5E, dst, nds, src, VEX_SIMD_F3, AVX_128bit);
3714 }
3715
3716 void Assembler::vmulsd(XMMRegister dst, XMMRegister nds, Address src) {
3717 assert(VM_Version::supports_avx(), "");
3718 if (VM_Version::supports_evex()) {
3719 tuple_type = EVEX_T1S;
3720 input_size_in_bits = EVEX_64bit;
3721 emit_vex_arith_q(0x59, dst, nds, src, VEX_SIMD_F2, AVX_128bit);
3722 } else {
3723 emit_vex_arith(0x59, dst, nds, src, VEX_SIMD_F2, AVX_128bit);
3724 }
3725 }
3726
3727 void Assembler::vmulsd(XMMRegister dst, XMMRegister nds, XMMRegister src) {
3728 assert(VM_Version::supports_avx(), "");
3729 if (VM_Version::supports_evex()) {
3730 emit_vex_arith_q(0x59, dst, nds, src, VEX_SIMD_F2, AVX_128bit);
3731 } else {
3732 emit_vex_arith(0x59, dst, nds, src, VEX_SIMD_F2, AVX_128bit);
3733 }
3734 }
3735
3736 void Assembler::vmulss(XMMRegister dst, XMMRegister nds, Address src) {
3737 assert(VM_Version::supports_avx(), "");
3738 if (VM_Version::supports_evex()) {
3739 tuple_type = EVEX_T1S;
3740 input_size_in_bits = EVEX_32bit;
3741 }
3742 emit_vex_arith(0x59, dst, nds, src, VEX_SIMD_F3, AVX_128bit);
3743 }
3744
3745 void Assembler::vmulss(XMMRegister dst, XMMRegister nds, XMMRegister src) {
3746 assert(VM_Version::supports_avx(), "");
3747 emit_vex_arith(0x59, dst, nds, src, VEX_SIMD_F3, AVX_128bit);
3748 }
3749
3750 void Assembler::vsubsd(XMMRegister dst, XMMRegister nds, Address src) {
3751 assert(VM_Version::supports_avx(), "");
3752 if (VM_Version::supports_evex()) {
3753 tuple_type = EVEX_T1S;
3754 input_size_in_bits = EVEX_64bit;
3755 emit_vex_arith_q(0x5C, dst, nds, src, VEX_SIMD_F2, AVX_128bit);
3756 } else {
3757 emit_vex_arith(0x5C, dst, nds, src, VEX_SIMD_F2, AVX_128bit);
3758 }
3759 }
3760
3761 void Assembler::vsubsd(XMMRegister dst, XMMRegister nds, XMMRegister src) {
3762 assert(VM_Version::supports_avx(), "");
3763 if (VM_Version::supports_evex()) {
3764 emit_vex_arith_q(0x5C, dst, nds, src, VEX_SIMD_F2, AVX_128bit);
3765 } else {
3766 emit_vex_arith(0x5C, dst, nds, src, VEX_SIMD_F2, AVX_128bit);
3767 }
3768 }
3769
3770 void Assembler::vsubss(XMMRegister dst, XMMRegister nds, Address src) {
3771 assert(VM_Version::supports_avx(), "");
3772 if (VM_Version::supports_evex()) {
3773 tuple_type = EVEX_T1S;
3774 input_size_in_bits = EVEX_32bit;
3775 }
3776 emit_vex_arith(0x5C, dst, nds, src, VEX_SIMD_F3, AVX_128bit);
3777 }
3778
3779 void Assembler::vsubss(XMMRegister dst, XMMRegister nds, XMMRegister src) {
3780 assert(VM_Version::supports_avx(), "");
3781 emit_vex_arith(0x5C, dst, nds, src, VEX_SIMD_F3, AVX_128bit);
3782 }
3783
3784 //====================VECTOR ARITHMETIC=====================================
3785
3786 // Float-point vector arithmetic
3787
3788 void Assembler::addpd(XMMRegister dst, XMMRegister src) {
3789 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3790 if (VM_Version::supports_evex()) {
3791 emit_simd_arith_q(0x58, dst, src, VEX_SIMD_66);
3792 } else {
3793 emit_simd_arith(0x58, dst, src, VEX_SIMD_66);
3794 }
3795 }
3796
3797 void Assembler::addps(XMMRegister dst, XMMRegister src) {
3798 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3799 emit_simd_arith(0x58, dst, src, VEX_SIMD_NONE);
3800 }
3801
3802 void Assembler::vaddpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3803 assert(VM_Version::supports_avx(), "");
3804 if (VM_Version::supports_evex()) {
3805 emit_vex_arith_q(0x58, dst, nds, src, VEX_SIMD_66, vector_len);
3806 } else {
3807 emit_vex_arith(0x58, dst, nds, src, VEX_SIMD_66, vector_len);
3808 }
3809 }
3810
3811 void Assembler::vaddps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3812 assert(VM_Version::supports_avx(), "");
3813 emit_vex_arith(0x58, dst, nds, src, VEX_SIMD_NONE, vector_len);
3814 }
3815
3816 void Assembler::vaddpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
3817 assert(VM_Version::supports_avx(), "");
3818 if (VM_Version::supports_evex()) {
3819 tuple_type = EVEX_FV;
3820 input_size_in_bits = EVEX_64bit;
3821 emit_vex_arith_q(0x58, dst, nds, src, VEX_SIMD_66, vector_len);
3822 } else {
3823 emit_vex_arith(0x58, dst, nds, src, VEX_SIMD_66, vector_len);
3824 }
3825 }
3826
3827 void Assembler::vaddps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
3828 assert(VM_Version::supports_avx(), "");
3829 if (VM_Version::supports_evex()) {
3830 tuple_type = EVEX_FV;
3831 input_size_in_bits = EVEX_32bit;
3832 }
3833 emit_vex_arith(0x58, dst, nds, src, VEX_SIMD_NONE, vector_len);
3834 }
3835
3836 void Assembler::subpd(XMMRegister dst, XMMRegister src) {
3837 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3838 if (VM_Version::supports_evex()) {
3839 emit_simd_arith_q(0x5C, dst, src, VEX_SIMD_66);
3840 } else {
3841 emit_simd_arith(0x5C, dst, src, VEX_SIMD_66);
3842 }
3843 }
3844
3845 void Assembler::subps(XMMRegister dst, XMMRegister src) {
3846 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3847 emit_simd_arith(0x5C, dst, src, VEX_SIMD_NONE);
3848 }
3849
3850 void Assembler::vsubpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3851 assert(VM_Version::supports_avx(), "");
3852 if (VM_Version::supports_evex()) {
3853 emit_vex_arith_q(0x5C, dst, nds, src, VEX_SIMD_66, vector_len);
3854 } else {
3855 emit_vex_arith(0x5C, dst, nds, src, VEX_SIMD_66, vector_len);
3856 }
3857 }
3858
3859 void Assembler::vsubps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3860 assert(VM_Version::supports_avx(), "");
3861 emit_vex_arith(0x5C, dst, nds, src, VEX_SIMD_NONE, vector_len);
3862 }
3863
3864 void Assembler::vsubpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
3865 assert(VM_Version::supports_avx(), "");
3866 if (VM_Version::supports_evex()) {
3867 tuple_type = EVEX_FV;
3868 input_size_in_bits = EVEX_64bit;
3869 emit_vex_arith_q(0x5C, dst, nds, src, VEX_SIMD_66, vector_len);
3870 } else {
3871 emit_vex_arith(0x5C, dst, nds, src, VEX_SIMD_66, vector_len);
3872 }
3873 }
3874
3875 void Assembler::vsubps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
3876 assert(VM_Version::supports_avx(), "");
3877 if (VM_Version::supports_evex()) {
3878 tuple_type = EVEX_FV;
3879 input_size_in_bits = EVEX_32bit;
3880 }
3881 emit_vex_arith(0x5C, dst, nds, src, VEX_SIMD_NONE, vector_len);
3882 }
3883
3884 void Assembler::mulpd(XMMRegister dst, XMMRegister src) {
3885 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3886 if (VM_Version::supports_evex()) {
3887 emit_simd_arith_q(0x59, dst, src, VEX_SIMD_66);
3888 } else {
3889 emit_simd_arith(0x59, dst, src, VEX_SIMD_66);
3890 }
3891 }
3892
3893 void Assembler::mulps(XMMRegister dst, XMMRegister src) {
3894 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3895 emit_simd_arith(0x59, dst, src, VEX_SIMD_NONE);
3896 }
3897
3898 void Assembler::vmulpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3899 assert(VM_Version::supports_avx(), "");
3900 if (VM_Version::supports_evex()) {
3901 emit_vex_arith_q(0x59, dst, nds, src, VEX_SIMD_66, vector_len);
3902 } else {
3903 emit_vex_arith(0x59, dst, nds, src, VEX_SIMD_66, vector_len);
3904 }
3905 }
3906
3907 void Assembler::vmulps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3908 assert(VM_Version::supports_avx(), "");
3909 emit_vex_arith(0x59, dst, nds, src, VEX_SIMD_NONE, vector_len);
3910 }
3911
3912 void Assembler::vmulpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
3913 assert(VM_Version::supports_avx(), "");
3914 if (VM_Version::supports_evex()) {
3915 tuple_type = EVEX_FV;
3916 input_size_in_bits = EVEX_64bit;
3917 emit_vex_arith_q(0x59, dst, nds, src, VEX_SIMD_66, vector_len);
3918 } else {
3919 emit_vex_arith(0x59, dst, nds, src, VEX_SIMD_66, vector_len);
3920 }
3921 }
3922
3923 void Assembler::vmulps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
3924 assert(VM_Version::supports_avx(), "");
3925 if (VM_Version::supports_evex()) {
3926 tuple_type = EVEX_FV;
3927 input_size_in_bits = EVEX_32bit;
3928 }
3929 emit_vex_arith(0x59, dst, nds, src, VEX_SIMD_NONE, vector_len);
3930 }
3931
3932 void Assembler::divpd(XMMRegister dst, XMMRegister src) {
3933 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3934 if (VM_Version::supports_evex()) {
3935 emit_simd_arith_q(0x5E, dst, src, VEX_SIMD_66);
3936 } else {
3937 emit_simd_arith(0x5E, dst, src, VEX_SIMD_66);
3938 }
3939 }
3940
3941 void Assembler::divps(XMMRegister dst, XMMRegister src) {
3942 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3943 emit_simd_arith(0x5E, dst, src, VEX_SIMD_NONE);
3944 }
3945
3946 void Assembler::vdivpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3947 assert(VM_Version::supports_avx(), "");
3948 if (VM_Version::supports_evex()) {
3949 emit_vex_arith_q(0x5E, dst, nds, src, VEX_SIMD_66, vector_len);
3950 } else {
3951 emit_vex_arith(0x5E, dst, nds, src, VEX_SIMD_66, vector_len);
3952 }
3953 }
3954
3955 void Assembler::vdivps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3956 assert(VM_Version::supports_avx(), "");
3957 emit_vex_arith(0x5E, dst, nds, src, VEX_SIMD_NONE, vector_len);
3958 }
3959
3960 void Assembler::vdivpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
3961 assert(VM_Version::supports_avx(), "");
3962 if (VM_Version::supports_evex()) {
3963 tuple_type = EVEX_FV;
3964 input_size_in_bits = EVEX_64bit;
3965 emit_vex_arith_q(0x5E, dst, nds, src, VEX_SIMD_66, vector_len);
3966 } else {
3967 emit_vex_arith(0x5E, dst, nds, src, VEX_SIMD_66, vector_len);
3968 }
3969 }
3970
3971 void Assembler::vdivps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
3972 assert(VM_Version::supports_avx(), "");
3973 if (VM_Version::supports_evex()) {
3974 tuple_type = EVEX_FV;
3975 input_size_in_bits = EVEX_32bit;
3976 }
3977 emit_vex_arith(0x5E, dst, nds, src, VEX_SIMD_NONE, vector_len);
3978 }
3979
3980 void Assembler::andpd(XMMRegister dst, XMMRegister src) {
3981 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3982 if (VM_Version::supports_evex() && VM_Version::supports_avx512dq()) {
3983 emit_simd_arith_q(0x54, dst, src, VEX_SIMD_66);
3984 } else {
3985 emit_simd_arith(0x54, dst, src, VEX_SIMD_66, false, true);
3986 }
3987 }
3988
3989 void Assembler::andps(XMMRegister dst, XMMRegister src) {
3990 NOT_LP64(assert(VM_Version::supports_sse(), ""));
3991 emit_simd_arith(0x54, dst, src, VEX_SIMD_NONE, false,
3992 (VM_Version::supports_avx512dq() == false));
3993 }
3994
3995 void Assembler::andps(XMMRegister dst, Address src) {
3996 NOT_LP64(assert(VM_Version::supports_sse(), ""));
3997 if (VM_Version::supports_evex()) {
3998 tuple_type = EVEX_FV;
3999 input_size_in_bits = EVEX_32bit;
4000 }
4001 emit_simd_arith(0x54, dst, src, VEX_SIMD_NONE,
4002 false, (VM_Version::supports_avx512dq() == false));
4003 }
4004
4005 void Assembler::andpd(XMMRegister dst, Address src) {
4006 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4007 if (VM_Version::supports_evex() && VM_Version::supports_avx512dq()) {
4008 tuple_type = EVEX_FV;
4009 input_size_in_bits = EVEX_64bit;
4010 emit_simd_arith_q(0x54, dst, src, VEX_SIMD_66);
4011 } else {
4012 emit_simd_arith(0x54, dst, src, VEX_SIMD_66, false, true);
4013 }
4014 }
4015
4016 void Assembler::vandpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4017 assert(VM_Version::supports_avx(), "");
4018 if (VM_Version::supports_evex() && VM_Version::supports_avx512dq()) {
4019 emit_vex_arith_q(0x54, dst, nds, src, VEX_SIMD_66, vector_len);
4020 } else {
4021 emit_vex_arith(0x54, dst, nds, src, VEX_SIMD_66, vector_len, true);
4022 }
4023 }
4024
4025 void Assembler::vandps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4026 assert(VM_Version::supports_avx(), "");
4027 bool legacy_mode = (VM_Version::supports_avx512dq() == false);
4028 emit_vex_arith(0x54, dst, nds, src, VEX_SIMD_NONE, vector_len, legacy_mode);
4029 }
4030
4031 void Assembler::vandpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4032 assert(VM_Version::supports_avx(), "");
4033 if (VM_Version::supports_evex() && VM_Version::supports_avx512dq()) {
4034 tuple_type = EVEX_FV;
4035 input_size_in_bits = EVEX_64bit;
4036 emit_vex_arith_q(0x54, dst, nds, src, VEX_SIMD_66, vector_len);
4037 } else {
4038 emit_vex_arith(0x54, dst, nds, src, VEX_SIMD_66, vector_len, true);
4039 }
4040 }
4041
4042 void Assembler::vandps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4043 assert(VM_Version::supports_avx(), "");
4044 if (VM_Version::supports_evex()) {
4045 tuple_type = EVEX_FV;
4046 input_size_in_bits = EVEX_32bit;
4047 }
4048 emit_vex_arith(0x54, dst, nds, src, VEX_SIMD_NONE, vector_len,
4049 (VM_Version::supports_avx512dq() == false));
4050 }
4051
4052 void Assembler::xorpd(XMMRegister dst, XMMRegister src) {
4053 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4054 if (VM_Version::supports_evex() && VM_Version::supports_avx512dq()) {
4055 emit_simd_arith_q(0x57, dst, src, VEX_SIMD_66);
4056 } else {
4057 emit_simd_arith(0x57, dst, src, VEX_SIMD_66, false, true);
4058 }
4059 }
4060
4061 void Assembler::xorps(XMMRegister dst, XMMRegister src) {
4062 NOT_LP64(assert(VM_Version::supports_sse(), ""));
4063 emit_simd_arith(0x57, dst, src, VEX_SIMD_NONE,
4064 false, (VM_Version::supports_avx512dq() == false));
4065 }
4066
4067 void Assembler::xorpd(XMMRegister dst, Address src) {
4068 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4069 if (VM_Version::supports_evex() && VM_Version::supports_avx512dq()) {
4070 tuple_type = EVEX_FV;
4071 input_size_in_bits = EVEX_64bit;
4072 emit_simd_arith_q(0x57, dst, src, VEX_SIMD_66);
4073 } else {
4074 emit_simd_arith(0x57, dst, src, VEX_SIMD_66, false, true);
4075 }
4076 }
4077
4078 void Assembler::xorps(XMMRegister dst, Address src) {
4079 NOT_LP64(assert(VM_Version::supports_sse(), ""));
4080 if (VM_Version::supports_evex()) {
4081 tuple_type = EVEX_FV;
4082 input_size_in_bits = EVEX_32bit;
4083 }
4084 emit_simd_arith(0x57, dst, src, VEX_SIMD_NONE, false,
4085 (VM_Version::supports_avx512dq() == false));
4086 }
4087
4088 void Assembler::vxorpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4089 assert(VM_Version::supports_avx(), "");
4090 if (VM_Version::supports_evex() && VM_Version::supports_avx512dq()) {
4091 emit_vex_arith_q(0x57, dst, nds, src, VEX_SIMD_66, vector_len);
4092 } else {
4093 emit_vex_arith(0x57, dst, nds, src, VEX_SIMD_66, vector_len, true);
4094 }
4095 }
4096
4097 void Assembler::vxorps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4098 assert(VM_Version::supports_avx(), "");
4099 emit_vex_arith(0x57, dst, nds, src, VEX_SIMD_NONE, vector_len,
4100 (VM_Version::supports_avx512dq() == false));
4101 }
4102
4103 void Assembler::vxorpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4104 assert(VM_Version::supports_avx(), "");
4105 if (VM_Version::supports_evex() && VM_Version::supports_avx512dq()) {
4106 tuple_type = EVEX_FV;
4107 input_size_in_bits = EVEX_64bit;
4108 emit_vex_arith_q(0x57, dst, nds, src, VEX_SIMD_66, vector_len);
4109 } else {
4110 emit_vex_arith(0x57, dst, nds, src, VEX_SIMD_66, vector_len, true);
4111 }
4112 }
4113
4114 void Assembler::vxorps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4115 assert(VM_Version::supports_avx(), "");
4116 if (VM_Version::supports_evex()) {
4117 tuple_type = EVEX_FV;
4118 input_size_in_bits = EVEX_32bit;
4119 }
4120 emit_vex_arith(0x57, dst, nds, src, VEX_SIMD_NONE, vector_len,
4121 (VM_Version::supports_avx512dq() == false));
4122 }
4123
4124 // Integer vector arithmetic
4125 void Assembler::vphaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4126 assert(VM_Version::supports_avx() && (vector_len == 0) ||
4127 VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
4128 int encode = vex_prefix_and_encode(dst, nds, src, VEX_SIMD_66, vector_len,
4129 VEX_OPCODE_0F_38, true, false);
4130 emit_int8(0x01);
4131 emit_int8((unsigned char)(0xC0 | encode));
4132 }
4133
4134 void Assembler::vphaddd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4135 assert(VM_Version::supports_avx() && (vector_len == 0) ||
4136 VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
4137 int encode = vex_prefix_and_encode(dst, nds, src, VEX_SIMD_66, vector_len,
4138 VEX_OPCODE_0F_38, true, false);
4139 emit_int8(0x02);
4140 emit_int8((unsigned char)(0xC0 | encode));
4141 }
4142
4143 void Assembler::paddb(XMMRegister dst, XMMRegister src) {
4144 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4145 emit_simd_arith(0xFC, dst, src, VEX_SIMD_66);
4146 }
4147
4148 void Assembler::paddw(XMMRegister dst, XMMRegister src) {
4149 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4150 emit_simd_arith(0xFD, dst, src, VEX_SIMD_66);
4151 }
4152
4153 void Assembler::paddd(XMMRegister dst, XMMRegister src) {
4154 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4155 emit_simd_arith(0xFE, dst, src, VEX_SIMD_66);
4156 }
4157
4158 void Assembler::paddq(XMMRegister dst, XMMRegister src) {
4159 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4160 if (VM_Version::supports_evex()) {
4161 emit_simd_arith_q(0xD4, dst, src, VEX_SIMD_66);
4162 } else {
4163 emit_simd_arith(0xD4, dst, src, VEX_SIMD_66);
4164 }
4165 }
4166
4167 void Assembler::phaddw(XMMRegister dst, XMMRegister src) {
4168 NOT_LP64(assert(VM_Version::supports_sse3(), ""));
4169 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, false,
4170 VEX_OPCODE_0F_38, false, AVX_128bit, true);
4171 emit_int8(0x01);
4172 emit_int8((unsigned char)(0xC0 | encode));
4173 }
4174
4175 void Assembler::phaddd(XMMRegister dst, XMMRegister src) {
4176 NOT_LP64(assert(VM_Version::supports_sse3(), ""));
4177 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, false,
4178 VEX_OPCODE_0F_38, false, AVX_128bit, true);
4179 emit_int8(0x02);
4180 emit_int8((unsigned char)(0xC0 | encode));
4181 }
4182
4183 void Assembler::vpaddb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4184 assert(UseAVX > 0, "requires some form of AVX");
4185 emit_vex_arith(0xFC, dst, nds, src, VEX_SIMD_66, vector_len,
4186 (VM_Version::supports_avx512bw() == false));
4187 }
4188
4189 void Assembler::vpaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4190 assert(UseAVX > 0, "requires some form of AVX");
4191 emit_vex_arith(0xFD, dst, nds, src, VEX_SIMD_66, vector_len,
4192 (VM_Version::supports_avx512bw() == false));
4193 }
4194
4195 void Assembler::vpaddd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4196 assert(UseAVX > 0, "requires some form of AVX");
4197 emit_vex_arith(0xFE, dst, nds, src, VEX_SIMD_66, vector_len);
4198 }
4199
4200 void Assembler::vpaddq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4201 assert(UseAVX > 0, "requires some form of AVX");
4202 if (VM_Version::supports_evex()) {
4203 emit_vex_arith_q(0xD4, dst, nds, src, VEX_SIMD_66, vector_len);
4204 } else {
4205 emit_vex_arith(0xD4, dst, nds, src, VEX_SIMD_66, vector_len);
4206 }
4207 }
4208
4209 void Assembler::vpaddb(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4210 assert(UseAVX > 0, "requires some form of AVX");
4211 if (VM_Version::supports_evex()) {
4212 tuple_type = EVEX_FVM;
4213 }
4214 emit_vex_arith(0xFC, dst, nds, src, VEX_SIMD_66, vector_len);
4215 }
4216
4217 void Assembler::vpaddw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4218 assert(UseAVX > 0, "requires some form of AVX");
4219 if (VM_Version::supports_evex()) {
4220 tuple_type = EVEX_FVM;
4221 }
4222 emit_vex_arith(0xFD, dst, nds, src, VEX_SIMD_66, vector_len);
4223 }
4224
4225 void Assembler::vpaddd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4226 assert(UseAVX > 0, "requires some form of AVX");
4227 if (VM_Version::supports_evex()) {
4228 tuple_type = EVEX_FV;
4229 input_size_in_bits = EVEX_32bit;
4230 }
4231 emit_vex_arith(0xFE, dst, nds, src, VEX_SIMD_66, vector_len);
4232 }
4233
4234 void Assembler::vpaddq(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4235 assert(UseAVX > 0, "requires some form of AVX");
4236 if (VM_Version::supports_evex()) {
4237 tuple_type = EVEX_FV;
4238 input_size_in_bits = EVEX_64bit;
4239 emit_vex_arith_q(0xD4, dst, nds, src, VEX_SIMD_66, vector_len);
4240 } else {
4241 emit_vex_arith(0xD4, dst, nds, src, VEX_SIMD_66, vector_len);
4242 }
4243 }
4244
4245 void Assembler::psubb(XMMRegister dst, XMMRegister src) {
4246 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4247 emit_simd_arith(0xF8, dst, src, VEX_SIMD_66);
4248 }
4249
4250 void Assembler::psubw(XMMRegister dst, XMMRegister src) {
4251 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4252 emit_simd_arith(0xF9, dst, src, VEX_SIMD_66);
4253 }
4254
4255 void Assembler::psubd(XMMRegister dst, XMMRegister src) {
4256 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4257 emit_simd_arith(0xFA, dst, src, VEX_SIMD_66);
4258 }
4259
4260 void Assembler::psubq(XMMRegister dst, XMMRegister src) {
4261 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4262 if (VM_Version::supports_evex()) {
4263 emit_simd_arith_q(0xFB, dst, src, VEX_SIMD_66);
4264 } else {
4265 emit_simd_arith(0xFB, dst, src, VEX_SIMD_66);
4266 }
4267 }
4268
4269 void Assembler::vpsubb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4270 assert(UseAVX > 0, "requires some form of AVX");
4271 emit_vex_arith(0xF8, dst, nds, src, VEX_SIMD_66, vector_len,
4272 (VM_Version::supports_avx512bw() == false));
4273 }
4274
4275 void Assembler::vpsubw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4276 assert(UseAVX > 0, "requires some form of AVX");
4277 emit_vex_arith(0xF9, dst, nds, src, VEX_SIMD_66, vector_len,
4278 (VM_Version::supports_avx512bw() == false));
4279 }
4280
4281 void Assembler::vpsubd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4282 assert(UseAVX > 0, "requires some form of AVX");
4283 emit_vex_arith(0xFA, dst, nds, src, VEX_SIMD_66, vector_len);
4284 }
4285
4286 void Assembler::vpsubq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4287 assert(UseAVX > 0, "requires some form of AVX");
4288 if (VM_Version::supports_evex()) {
4289 emit_vex_arith_q(0xFB, dst, nds, src, VEX_SIMD_66, vector_len);
4290 } else {
4291 emit_vex_arith(0xFB, dst, nds, src, VEX_SIMD_66, vector_len);
4292 }
4293 }
4294
4295 void Assembler::vpsubb(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4296 assert(UseAVX > 0, "requires some form of AVX");
4297 if (VM_Version::supports_evex()) {
4298 tuple_type = EVEX_FVM;
4299 }
4300 emit_vex_arith(0xF8, dst, nds, src, VEX_SIMD_66, vector_len,
4301 (VM_Version::supports_avx512bw() == false));
4302 }
4303
4304 void Assembler::vpsubw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4305 assert(UseAVX > 0, "requires some form of AVX");
4306 if (VM_Version::supports_evex()) {
4307 tuple_type = EVEX_FVM;
4308 }
4309 emit_vex_arith(0xF9, dst, nds, src, VEX_SIMD_66, vector_len,
4310 (VM_Version::supports_avx512bw() == false));
4311 }
4312
4313 void Assembler::vpsubd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4314 assert(UseAVX > 0, "requires some form of AVX");
4315 if (VM_Version::supports_evex()) {
4316 tuple_type = EVEX_FV;
4317 input_size_in_bits = EVEX_32bit;
4318 }
4319 emit_vex_arith(0xFA, dst, nds, src, VEX_SIMD_66, vector_len);
4320 }
4321
4322 void Assembler::vpsubq(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4323 assert(UseAVX > 0, "requires some form of AVX");
4324 if (VM_Version::supports_evex()) {
4325 tuple_type = EVEX_FV;
4326 input_size_in_bits = EVEX_64bit;
4327 emit_vex_arith_q(0xFB, dst, nds, src, VEX_SIMD_66, vector_len);
4328 } else {
4329 emit_vex_arith(0xFB, dst, nds, src, VEX_SIMD_66, vector_len);
4330 }
4331 }
4332
4333 void Assembler::pmullw(XMMRegister dst, XMMRegister src) {
4334 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4335 emit_simd_arith(0xD5, dst, src, VEX_SIMD_66,
4336 (VM_Version::supports_avx512bw() == false));
4337 }
4338
4339 void Assembler::pmulld(XMMRegister dst, XMMRegister src) {
4340 assert(VM_Version::supports_sse4_1(), "");
4341 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66,
4342 false, VEX_OPCODE_0F_38);
4343 emit_int8(0x40);
4344 emit_int8((unsigned char)(0xC0 | encode));
4345 }
4346
4347 void Assembler::vpmullw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4348 assert(UseAVX > 0, "requires some form of AVX");
4349 emit_vex_arith(0xD5, dst, nds, src, VEX_SIMD_66, vector_len,
4350 (VM_Version::supports_avx512bw() == false));
4351 }
4352
4353 void Assembler::vpmulld(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4354 assert(UseAVX > 0, "requires some form of AVX");
4355 int encode = vex_prefix_and_encode(dst, nds, src, VEX_SIMD_66,
4356 vector_len, VEX_OPCODE_0F_38);
4357 emit_int8(0x40);
4358 emit_int8((unsigned char)(0xC0 | encode));
4359 }
4360
4361 void Assembler::vpmullq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4362 assert(UseAVX > 2, "requires some form of AVX");
4363 int src_enc = src->encoding();
4364 int dst_enc = dst->encoding();
4365 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4366 int encode = vex_prefix_and_encode(dst_enc, nds_enc, src_enc, VEX_SIMD_66,
4367 VEX_OPCODE_0F_38, true, vector_len, false, false);
4368 emit_int8(0x40);
4369 emit_int8((unsigned char)(0xC0 | encode));
4370 }
4371
4372 void Assembler::vpmullw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4373 assert(UseAVX > 0, "requires some form of AVX");
4374 if (VM_Version::supports_evex()) {
4375 tuple_type = EVEX_FVM;
4376 }
4377 emit_vex_arith(0xD5, dst, nds, src, VEX_SIMD_66, vector_len);
4378 }
4379
4380 void Assembler::vpmulld(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4381 assert(UseAVX > 0, "requires some form of AVX");
4382 if (VM_Version::supports_evex()) {
4383 tuple_type = EVEX_FV;
4384 input_size_in_bits = EVEX_32bit;
4385 }
4386 InstructionMark im(this);
4387 int dst_enc = dst->encoding();
4388 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4389 vex_prefix(src, nds_enc, dst_enc, VEX_SIMD_66,
4390 VEX_OPCODE_0F_38, false, vector_len);
4391 emit_int8(0x40);
4392 emit_operand(dst, src);
4393 }
4394
4395 void Assembler::vpmullq(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4396 assert(UseAVX > 0, "requires some form of AVX");
4397 if (VM_Version::supports_evex()) {
4398 tuple_type = EVEX_FV;
4399 input_size_in_bits = EVEX_64bit;
4400 }
4401 InstructionMark im(this);
4402 int dst_enc = dst->encoding();
4403 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4404 vex_prefix(src, nds_enc, dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_38, true, vector_len);
4405 emit_int8(0x40);
4406 emit_operand(dst, src);
4407 }
4408
4409 // Shift packed integers left by specified number of bits.
4410 void Assembler::psllw(XMMRegister dst, int shift) {
4411 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4412 // XMM6 is for /6 encoding: 66 0F 71 /6 ib
4413 int encode = simd_prefix_and_encode(xmm6, dst, dst, VEX_SIMD_66, false, VEX_OPCODE_0F,
4414 false, AVX_128bit, (VM_Version::supports_avx512bw() == false));
4415 emit_int8(0x71);
4416 emit_int8((unsigned char)(0xC0 | encode));
4417 emit_int8(shift & 0xFF);
4418 }
4419
4420 void Assembler::pslld(XMMRegister dst, int shift) {
4421 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4422 // XMM6 is for /6 encoding: 66 0F 72 /6 ib
4423 int encode = simd_prefix_and_encode(xmm6, dst, dst, VEX_SIMD_66, false);
4424 emit_int8(0x72);
4425 emit_int8((unsigned char)(0xC0 | encode));
4426 emit_int8(shift & 0xFF);
4427 }
4428
4429 void Assembler::psllq(XMMRegister dst, int shift) {
4430 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4431 // XMM6 is for /6 encoding: 66 0F 73 /6 ib
4432 int encode = simd_prefix_and_encode(xmm6, dst, dst, VEX_SIMD_66, false, VEX_OPCODE_0F, true);
4433 emit_int8(0x73);
4434 emit_int8((unsigned char)(0xC0 | encode));
4435 emit_int8(shift & 0xFF);
4436 }
4437
4438 void Assembler::psllw(XMMRegister dst, XMMRegister shift) {
4439 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4440 emit_simd_arith(0xF1, dst, shift, VEX_SIMD_66, false,
4441 (VM_Version::supports_avx512bw() == false));
4442 }
4443
4444 void Assembler::pslld(XMMRegister dst, XMMRegister shift) {
4445 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4446 emit_simd_arith(0xF2, dst, shift, VEX_SIMD_66);
4447 }
4448
4449 void Assembler::psllq(XMMRegister dst, XMMRegister shift) {
4450 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4451 if (VM_Version::supports_evex()) {
4452 emit_simd_arith_q(0xF3, dst, shift, VEX_SIMD_66);
4453 } else {
4454 emit_simd_arith(0xF3, dst, shift, VEX_SIMD_66);
4455 }
4456 }
4457
4458 void Assembler::vpsllw(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
4459 assert(UseAVX > 0, "requires some form of AVX");
4460 // XMM6 is for /6 encoding: 66 0F 71 /6 ib
4461 emit_vex_arith(0x71, xmm6, dst, src, VEX_SIMD_66, vector_len,
4462 (VM_Version::supports_avx512bw() == false));
4463 emit_int8(shift & 0xFF);
4464 }
4465
4466 void Assembler::vpslld(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
4467 assert(UseAVX > 0, "requires some form of AVX");
4468 // XMM6 is for /6 encoding: 66 0F 72 /6 ib
4469 emit_vex_arith(0x72, xmm6, dst, src, VEX_SIMD_66, vector_len);
4470 emit_int8(shift & 0xFF);
4471 }
4472
4473 void Assembler::vpsllq(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
4474 assert(UseAVX > 0, "requires some form of AVX");
4475 // XMM6 is for /6 encoding: 66 0F 73 /6 ib
4476 if (VM_Version::supports_evex()) {
4477 emit_vex_arith_q(0x73, xmm6, dst, src, VEX_SIMD_66, vector_len);
4478 } else {
4479 emit_vex_arith(0x73, xmm6, dst, src, VEX_SIMD_66, vector_len);
4480 }
4481 emit_int8(shift & 0xFF);
4482 }
4483
4484 void Assembler::vpsllw(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
4485 assert(UseAVX > 0, "requires some form of AVX");
4486 emit_vex_arith(0xF1, dst, src, shift, VEX_SIMD_66, vector_len,
4487 (VM_Version::supports_avx512bw() == false));
4488 }
4489
4490 void Assembler::vpslld(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
4491 assert(UseAVX > 0, "requires some form of AVX");
4492 emit_vex_arith(0xF2, dst, src, shift, VEX_SIMD_66, vector_len);
4493 }
4494
4495 void Assembler::vpsllq(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
4496 assert(UseAVX > 0, "requires some form of AVX");
4497 if (VM_Version::supports_evex()) {
4498 emit_vex_arith_q(0xF3, dst, src, shift, VEX_SIMD_66, vector_len);
4499 } else {
4500 emit_vex_arith(0xF3, dst, src, shift, VEX_SIMD_66, vector_len);
4501 }
4502 }
4503
4504 // Shift packed integers logically right by specified number of bits.
4505 void Assembler::psrlw(XMMRegister dst, int shift) {
4506 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4507 // XMM2 is for /2 encoding: 66 0F 71 /2 ib
4508 int encode = simd_prefix_and_encode(xmm2, dst, dst, VEX_SIMD_66, false, VEX_OPCODE_0F,
4509 (VM_Version::supports_avx512bw() == false));
4510 emit_int8(0x71);
4511 emit_int8((unsigned char)(0xC0 | encode));
4512 emit_int8(shift & 0xFF);
4513 }
4514
4515 void Assembler::psrld(XMMRegister dst, int shift) {
4516 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4517 // XMM2 is for /2 encoding: 66 0F 72 /2 ib
4518 int encode = simd_prefix_and_encode(xmm2, dst, dst, VEX_SIMD_66, false);
4519 emit_int8(0x72);
4520 emit_int8((unsigned char)(0xC0 | encode));
4521 emit_int8(shift & 0xFF);
4522 }
4523
4524 void Assembler::psrlq(XMMRegister dst, int shift) {
4525 // Do not confuse it with psrldq SSE2 instruction which
4526 // shifts 128 bit value in xmm register by number of bytes.
4527 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4528 // XMM2 is for /2 encoding: 66 0F 73 /2 ib
4529 int encode = 0;
4530 if (VM_Version::supports_evex() && VM_Version::supports_avx512bw()) {
4531 encode = simd_prefix_and_encode(xmm2, dst, dst, VEX_SIMD_66, true, VEX_OPCODE_0F, false);
4532 } else {
4533 encode = simd_prefix_and_encode(xmm2, dst, dst, VEX_SIMD_66, false, VEX_OPCODE_0F, true);
4534 }
4535 emit_int8(0x73);
4536 emit_int8((unsigned char)(0xC0 | encode));
4537 emit_int8(shift & 0xFF);
4538 }
4539
4540 void Assembler::psrlw(XMMRegister dst, XMMRegister shift) {
4541 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4542 emit_simd_arith(0xD1, dst, shift, VEX_SIMD_66, false,
4543 (VM_Version::supports_avx512bw() == false));
4544 }
4545
4546 void Assembler::psrld(XMMRegister dst, XMMRegister shift) {
4547 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4548 emit_simd_arith(0xD2, dst, shift, VEX_SIMD_66);
4549 }
4550
4551 void Assembler::psrlq(XMMRegister dst, XMMRegister shift) {
4552 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4553 if (VM_Version::supports_evex()) {
4554 emit_simd_arith_q(0xD3, dst, shift, VEX_SIMD_66);
4555 } else {
4556 emit_simd_arith(0xD3, dst, shift, VEX_SIMD_66);
4557 }
4558 }
4559
4560 void Assembler::vpsrlw(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
4561 assert(UseAVX > 0, "requires some form of AVX");
4562 // XMM2 is for /2 encoding: 66 0F 73 /2 ib
4563 emit_vex_arith(0x71, xmm2, dst, src, VEX_SIMD_66, vector_len,
4564 (VM_Version::supports_avx512bw() == false));
4565 emit_int8(shift & 0xFF);
4566 }
4567
4568 void Assembler::vpsrld(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
4569 assert(UseAVX > 0, "requires some form of AVX");
4570 // XMM2 is for /2 encoding: 66 0F 73 /2 ib
4571 emit_vex_arith(0x72, xmm2, dst, src, VEX_SIMD_66, vector_len);
4572 emit_int8(shift & 0xFF);
4573 }
4574
4575 void Assembler::vpsrlq(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
4576 assert(UseAVX > 0, "requires some form of AVX");
4577 // XMM2 is for /2 encoding: 66 0F 73 /2 ib
4578 if (VM_Version::supports_evex()) {
4579 emit_vex_arith_q(0x73, xmm2, dst, src, VEX_SIMD_66, vector_len);
4580 } else {
4581 emit_vex_arith(0x73, xmm2, dst, src, VEX_SIMD_66, vector_len);
4582 }
4583 emit_int8(shift & 0xFF);
4584 }
4585
4586 void Assembler::vpsrlw(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
4587 assert(UseAVX > 0, "requires some form of AVX");
4588 emit_vex_arith(0xD1, dst, src, shift, VEX_SIMD_66, vector_len,
4589 (VM_Version::supports_avx512bw() == false));
4590 }
4591
4592 void Assembler::vpsrld(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
4593 assert(UseAVX > 0, "requires some form of AVX");
4594 emit_vex_arith(0xD2, dst, src, shift, VEX_SIMD_66, vector_len);
4595 }
4596
4597 void Assembler::vpsrlq(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
4598 assert(UseAVX > 0, "requires some form of AVX");
4599 if (VM_Version::supports_evex()) {
4600 emit_vex_arith_q(0xD3, dst, src, shift, VEX_SIMD_66, vector_len);
4601 } else {
4602 emit_vex_arith(0xD3, dst, src, shift, VEX_SIMD_66, vector_len);
4603 }
4604 }
4605
4606 // Shift packed integers arithmetically right by specified number of bits.
4607 void Assembler::psraw(XMMRegister dst, int shift) {
4608 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4609 // XMM4 is for /4 encoding: 66 0F 71 /4 ib
4610 int encode = simd_prefix_and_encode(xmm4, dst, dst, VEX_SIMD_66, false, VEX_OPCODE_0F,
4611 (VM_Version::supports_avx512bw() == false));
4612 emit_int8(0x71);
4613 emit_int8((unsigned char)(0xC0 | encode));
4614 emit_int8(shift & 0xFF);
4615 }
4616
4617 void Assembler::psrad(XMMRegister dst, int shift) {
4618 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4619 // XMM4 is for /4 encoding: 66 0F 72 /4 ib
4620 int encode = simd_prefix_and_encode(xmm4, dst, dst, VEX_SIMD_66, false);
4621 emit_int8(0x72);
4622 emit_int8((unsigned char)(0xC0 | encode));
4623 emit_int8(shift & 0xFF);
4624 }
4625
4626 void Assembler::psraw(XMMRegister dst, XMMRegister shift) {
4627 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4628 emit_simd_arith(0xE1, dst, shift, VEX_SIMD_66,
4629 (VM_Version::supports_avx512bw() == false));
4630 }
4631
4632 void Assembler::psrad(XMMRegister dst, XMMRegister shift) {
4633 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4634 emit_simd_arith(0xE2, dst, shift, VEX_SIMD_66);
4635 }
4636
4637 void Assembler::vpsraw(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
4638 assert(UseAVX > 0, "requires some form of AVX");
4639 // XMM4 is for /4 encoding: 66 0F 71 /4 ib
4640 emit_vex_arith(0x71, xmm4, dst, src, VEX_SIMD_66, vector_len,
4641 (VM_Version::supports_avx512bw() == false));
4642 emit_int8(shift & 0xFF);
4643 }
4644
4645 void Assembler::vpsrad(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
4646 assert(UseAVX > 0, "requires some form of AVX");
4647 // XMM4 is for /4 encoding: 66 0F 71 /4 ib
4648 emit_vex_arith(0x72, xmm4, dst, src, VEX_SIMD_66, vector_len);
4649 emit_int8(shift & 0xFF);
4650 }
4651
4652 void Assembler::vpsraw(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
4653 assert(UseAVX > 0, "requires some form of AVX");
4654 emit_vex_arith(0xE1, dst, src, shift, VEX_SIMD_66, vector_len,
4655 (VM_Version::supports_avx512bw() == false));
4656 }
4657
4658 void Assembler::vpsrad(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
4659 assert(UseAVX > 0, "requires some form of AVX");
4660 emit_vex_arith(0xE2, dst, src, shift, VEX_SIMD_66, vector_len);
4661 }
4662
4663
4664 // AND packed integers
4665 void Assembler::pand(XMMRegister dst, XMMRegister src) {
4666 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4667 emit_simd_arith(0xDB, dst, src, VEX_SIMD_66);
4668 }
4669
4670 void Assembler::vpand(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4671 assert(UseAVX > 0, "requires some form of AVX");
4672 emit_vex_arith(0xDB, dst, nds, src, VEX_SIMD_66, vector_len);
4673 }
4674
4675 void Assembler::vpand(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4676 assert(UseAVX > 0, "requires some form of AVX");
4677 if (VM_Version::supports_evex()) {
4678 tuple_type = EVEX_FV;
4679 input_size_in_bits = EVEX_32bit;
4680 }
4681 emit_vex_arith(0xDB, dst, nds, src, VEX_SIMD_66, vector_len);
4682 }
4683
4684 void Assembler::por(XMMRegister dst, XMMRegister src) {
4685 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4686 emit_simd_arith(0xEB, dst, src, VEX_SIMD_66);
4687 }
4688
4689 void Assembler::vpor(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4690 assert(UseAVX > 0, "requires some form of AVX");
4691 emit_vex_arith(0xEB, dst, nds, src, VEX_SIMD_66, vector_len);
4692 }
4693
4694 void Assembler::vpor(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4695 assert(UseAVX > 0, "requires some form of AVX");
4696 if (VM_Version::supports_evex()) {
4697 tuple_type = EVEX_FV;
4698 input_size_in_bits = EVEX_32bit;
4699 }
4700 emit_vex_arith(0xEB, dst, nds, src, VEX_SIMD_66, vector_len);
4701 }
4702
4703 void Assembler::pxor(XMMRegister dst, XMMRegister src) {
4704 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4705 emit_simd_arith(0xEF, dst, src, VEX_SIMD_66);
4706 }
4707
4708 void Assembler::vpxor(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4709 assert(UseAVX > 0, "requires some form of AVX");
4710 emit_vex_arith(0xEF, dst, nds, src, VEX_SIMD_66, vector_len);
4711 }
4712
4713 void Assembler::vpxor(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4714 assert(UseAVX > 0, "requires some form of AVX");
4715 if (VM_Version::supports_evex()) {
4716 tuple_type = EVEX_FV;
4717 input_size_in_bits = EVEX_32bit;
4718 }
4719 emit_vex_arith(0xEF, dst, nds, src, VEX_SIMD_66, vector_len);
4720 }
4721
4722
4723 void Assembler::vinsertf128h(XMMRegister dst, XMMRegister nds, XMMRegister src) {
4724 assert(VM_Version::supports_avx(), "");
4725 int vector_len = AVX_256bit;
4726 int encode = vex_prefix_and_encode(dst, nds, src, VEX_SIMD_66, vector_len, VEX_OPCODE_0F_3A);
4727 emit_int8(0x18);
4728 emit_int8((unsigned char)(0xC0 | encode));
4729 // 0x00 - insert into lower 128 bits
4730 // 0x01 - insert into upper 128 bits
4731 emit_int8(0x01);
4732 }
4733
4734 void Assembler::vinsertf64x4h(XMMRegister dst, XMMRegister nds, XMMRegister src) {
4735 assert(VM_Version::supports_evex(), "");
4736 int vector_len = AVX_512bit;
4737 int src_enc = src->encoding();
4738 int dst_enc = dst->encoding();
4739 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4740 int encode = vex_prefix_and_encode(dst_enc, nds_enc, src_enc, VEX_SIMD_66,
4741 VEX_OPCODE_0F_3A, true, vector_len, false, false);
4742 emit_int8(0x1A);
4743 emit_int8((unsigned char)(0xC0 | encode));
4744 // 0x00 - insert into lower 256 bits
4745 // 0x01 - insert into upper 256 bits
4746 emit_int8(0x01);
4747 }
4748
4749 void Assembler::vinsertf64x4h(XMMRegister dst, Address src) {
4750 assert(VM_Version::supports_avx(), "");
4751 if (VM_Version::supports_evex()) {
4752 tuple_type = EVEX_T4;
4753 input_size_in_bits = EVEX_64bit;
4754 }
4755 InstructionMark im(this);
4756 int vector_len = AVX_512bit;
4757 assert(dst != xnoreg, "sanity");
4758 int dst_enc = dst->encoding();
4759 // swap src<->dst for encoding
4760 vex_prefix(src, dst_enc, dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_3A, true, vector_len);
4761 emit_int8(0x1A);
4762 emit_operand(dst, src);
4763 // 0x01 - insert into upper 128 bits
4764 emit_int8(0x01);
4765 }
4766
4767 void Assembler::vinsertf128h(XMMRegister dst, Address src) {
4768 assert(VM_Version::supports_avx(), "");
4769 if (VM_Version::supports_evex()) {
4770 tuple_type = EVEX_T4;
4771 input_size_in_bits = EVEX_32bit;
4772 }
4773 InstructionMark im(this);
4774 int vector_len = AVX_256bit;
4775 assert(dst != xnoreg, "sanity");
4776 int dst_enc = dst->encoding();
4777 // swap src<->dst for encoding
4778 vex_prefix(src, dst_enc, dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_3A, false, vector_len);
4779 emit_int8(0x18);
4780 emit_operand(dst, src);
4781 // 0x01 - insert into upper 128 bits
4782 emit_int8(0x01);
4783 }
4784
4785 void Assembler::vextractf128h(XMMRegister dst, XMMRegister src) {
4786 assert(VM_Version::supports_avx(), "");
4787 int vector_len = AVX_256bit;
4788 int encode = vex_prefix_and_encode(src, xnoreg, dst, VEX_SIMD_66, vector_len, VEX_OPCODE_0F_3A);
4789 emit_int8(0x19);
4790 emit_int8((unsigned char)(0xC0 | encode));
4791 // 0x00 - insert into lower 128 bits
4792 // 0x01 - insert into upper 128 bits
4793 emit_int8(0x01);
4794 }
4795
4796 void Assembler::vextractf128h(Address dst, XMMRegister src) {
4797 assert(VM_Version::supports_avx(), "");
4798 if (VM_Version::supports_evex()) {
4799 tuple_type = EVEX_T4;
4800 input_size_in_bits = EVEX_32bit;
4801 }
4802 InstructionMark im(this);
4803 int vector_len = AVX_256bit;
4804 assert(src != xnoreg, "sanity");
4805 int src_enc = src->encoding();
4806 vex_prefix(dst, 0, src_enc, VEX_SIMD_66, VEX_OPCODE_0F_3A, false, vector_len);
4807 emit_int8(0x19);
4808 emit_operand(src, dst);
4809 // 0x01 - extract from upper 128 bits
4810 emit_int8(0x01);
4811 }
4812
4813 void Assembler::vinserti128h(XMMRegister dst, XMMRegister nds, XMMRegister src) {
4814 assert(VM_Version::supports_avx2(), "");
4815 int vector_len = AVX_256bit;
4816 int encode = vex_prefix_and_encode(dst, nds, src, VEX_SIMD_66, vector_len, VEX_OPCODE_0F_3A);
4817 emit_int8(0x38);
4818 emit_int8((unsigned char)(0xC0 | encode));
4819 // 0x00 - insert into lower 128 bits
4820 // 0x01 - insert into upper 128 bits
4821 emit_int8(0x01);
4822 }
4823
4824 void Assembler::vinserti64x4h(XMMRegister dst, XMMRegister nds, XMMRegister src) {
4825 assert(VM_Version::supports_evex(), "");
4826 int vector_len = AVX_512bit;
4827 int src_enc = src->encoding();
4828 int dst_enc = dst->encoding();
4829 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4830 int encode = vex_prefix_and_encode(dst_enc, nds_enc, src_enc, VEX_SIMD_66, VEX_OPCODE_0F_3A,
4831 VM_Version::supports_avx512dq(), vector_len, false, false);
4832 emit_int8(0x38);
4833 emit_int8((unsigned char)(0xC0 | encode));
4834 // 0x00 - insert into lower 256 bits
4835 // 0x01 - insert into upper 256 bits
4836 emit_int8(0x01);
4837 }
4838
4839 void Assembler::vinserti128h(XMMRegister dst, Address src) {
4840 assert(VM_Version::supports_avx2(), "");
4841 if (VM_Version::supports_evex()) {
4842 tuple_type = EVEX_T4;
4843 input_size_in_bits = EVEX_32bit;
4844 }
4845 InstructionMark im(this);
4846 int vector_len = AVX_256bit;
4847 assert(dst != xnoreg, "sanity");
4848 int dst_enc = dst->encoding();
4849 // swap src<->dst for encoding
4850 vex_prefix(src, dst_enc, dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_3A, false, vector_len);
4851 emit_int8(0x38);
4852 emit_operand(dst, src);
4853 // 0x01 - insert into upper 128 bits
4854 emit_int8(0x01);
4855 }
4856
4857 void Assembler::vextracti128h(XMMRegister dst, XMMRegister src) {
4858 assert(VM_Version::supports_avx(), "");
4859 int vector_len = AVX_256bit;
4860 int encode = vex_prefix_and_encode(src, xnoreg, dst, VEX_SIMD_66, vector_len, VEX_OPCODE_0F_3A);
4861 emit_int8(0x39);
4862 emit_int8((unsigned char)(0xC0 | encode));
4863 // 0x00 - insert into lower 128 bits
4864 // 0x01 - insert into upper 128 bits
4865 emit_int8(0x01);
4866 }
4867
4868 void Assembler::vextracti128h(Address dst, XMMRegister src) {
4869 assert(VM_Version::supports_avx2(), "");
4870 if (VM_Version::supports_evex()) {
4871 tuple_type = EVEX_T4;
4872 input_size_in_bits = EVEX_32bit;
4873 }
4874 InstructionMark im(this);
4875 int vector_len = AVX_256bit;
4876 assert(src != xnoreg, "sanity");
4877 int src_enc = src->encoding();
4878 vex_prefix(dst, 0, src_enc, VEX_SIMD_66, VEX_OPCODE_0F_3A, false, vector_len);
4879 emit_int8(0x39);
4880 emit_operand(src, dst);
4881 // 0x01 - extract from upper 128 bits
4882 emit_int8(0x01);
4883 }
4884
4885 void Assembler::vextracti64x4h(XMMRegister dst, XMMRegister src) {
4886 assert(VM_Version::supports_evex(), "");
4887 int vector_len = AVX_512bit;
4888 int src_enc = src->encoding();
4889 int dst_enc = dst->encoding();
4890 int encode = vex_prefix_and_encode(src_enc, 0, dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_3A,
4891 true, vector_len, false, false);
4892 emit_int8(0x3B);
4893 emit_int8((unsigned char)(0xC0 | encode));
4894 // 0x01 - extract from upper 256 bits
4895 emit_int8(0x01);
4896 }
4897
4898 void Assembler::vextracti64x2h(XMMRegister dst, XMMRegister src, int value) {
4899 assert(VM_Version::supports_evex(), "");
4900 int vector_len = AVX_512bit;
4901 int src_enc = src->encoding();
4902 int dst_enc = dst->encoding();
4903 int encode = vex_prefix_and_encode(src_enc, 0, dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_3A,
4904 VM_Version::supports_avx512dq(), vector_len, false, false);
4905 emit_int8(0x39);
4906 emit_int8((unsigned char)(0xC0 | encode));
4907 // 0x01 - extract from bits 255:128
4908 // 0x02 - extract from bits 383:256
4909 // 0x03 - extract from bits 511:384
4910 emit_int8(value & 0x3);
4911 }
4912
4913 void Assembler::vextractf64x4h(XMMRegister dst, XMMRegister src) {
4914 assert(VM_Version::supports_evex(), "");
4915 int vector_len = AVX_512bit;
4916 int src_enc = src->encoding();
4917 int dst_enc = dst->encoding();
4918 int encode = vex_prefix_and_encode(src_enc, 0, dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_3A,
4919 VM_Version::supports_avx512dq(), vector_len, false, false);
4920 emit_int8(0x1B);
4921 emit_int8((unsigned char)(0xC0 | encode));
4922 // 0x01 - extract from upper 256 bits
4923 emit_int8(0x01);
4924 }
4925
4926 void Assembler::vextractf64x4h(Address dst, XMMRegister src) {
4927 assert(VM_Version::supports_avx2(), "");
4928 tuple_type = EVEX_T4;
4929 input_size_in_bits = EVEX_64bit;
4930 InstructionMark im(this);
4931 int vector_len = AVX_512bit;
4932 assert(src != xnoreg, "sanity");
4933 int src_enc = src->encoding();
4934 vex_prefix(dst, 0, src_enc, VEX_SIMD_66, VEX_OPCODE_0F_3A,
4935 VM_Version::supports_avx512dq(), vector_len);
4936 emit_int8(0x1B);
4937 emit_operand(src, dst);
4938 // 0x01 - extract from upper 128 bits
4939 emit_int8(0x01);
4940 }
4941
4942 void Assembler::vextractf32x4h(XMMRegister dst, XMMRegister src, int value) {
4943 assert(VM_Version::supports_evex(), "");
4944 int vector_len = AVX_512bit;
4945 int src_enc = src->encoding();
4946 int dst_enc = dst->encoding();
4947 int encode = vex_prefix_and_encode(src_enc, 0, dst_enc, VEX_SIMD_66,
4948 VEX_OPCODE_0F_3A, false, vector_len, false, false);
4949 emit_int8(0x19);
4950 emit_int8((unsigned char)(0xC0 | encode));
4951 // 0x01 - extract from bits 255:128
4952 // 0x02 - extract from bits 383:256
4953 // 0x03 - extract from bits 511:384
4954 emit_int8(value & 0x3);
4955 }
4956
4957 void Assembler::vextractf64x2h(XMMRegister dst, XMMRegister src, int value) {
4958 assert(VM_Version::supports_evex(), "");
4959 int vector_len = AVX_512bit;
4960 int src_enc = src->encoding();
4961 int dst_enc = dst->encoding();
4962 int encode = vex_prefix_and_encode(src_enc, 0, dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_3A,
4963 VM_Version::supports_avx512dq(), vector_len, false, false);
4964 emit_int8(0x19);
4965 emit_int8((unsigned char)(0xC0 | encode));
4966 // 0x01 - extract from bits 255:128
4967 // 0x02 - extract from bits 383:256
4968 // 0x03 - extract from bits 511:384
4969 emit_int8(value & 0x3);
4970 }
4971
4972 // duplicate 4-bytes integer data from src into 8 locations in dest
4973 void Assembler::vpbroadcastd(XMMRegister dst, XMMRegister src) {
4974 assert(VM_Version::supports_avx2(), "");
4975 int vector_len = AVX_256bit;
4976 int encode = vex_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66,
4977 vector_len, VEX_OPCODE_0F_38, false);
4978 emit_int8(0x58);
4979 emit_int8((unsigned char)(0xC0 | encode));
4980 }
4981
4982 // duplicate 4-bytes integer data from src into 8 locations in dest
4983 void Assembler::evpbroadcastd(XMMRegister dst, XMMRegister src, int vector_len) {
4984 assert(VM_Version::supports_evex(), "");
4985 int encode = vex_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66,
4986 vector_len, VEX_OPCODE_0F_38, false);
4987 emit_int8(0x58);
4988 emit_int8((unsigned char)(0xC0 | encode));
4989 }
4990
4991 // Carry-Less Multiplication Quadword
4992 void Assembler::pclmulqdq(XMMRegister dst, XMMRegister src, int mask) {
4993 assert(VM_Version::supports_clmul(), "");
4994 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, false,
4995 VEX_OPCODE_0F_3A, false, AVX_128bit, true);
4996 emit_int8(0x44);
4997 emit_int8((unsigned char)(0xC0 | encode));
4998 emit_int8((unsigned char)mask);
4999 }
5000
5001 // Carry-Less Multiplication Quadword
5002 void Assembler::vpclmulqdq(XMMRegister dst, XMMRegister nds, XMMRegister src, int mask) {
5003 assert(VM_Version::supports_avx() && VM_Version::supports_clmul(), "");
5004 int vector_len = AVX_128bit;
5005 int encode = vex_prefix_and_encode(dst, nds, src, VEX_SIMD_66,
5006 vector_len, VEX_OPCODE_0F_3A, true);
5007 emit_int8(0x44);
5008 emit_int8((unsigned char)(0xC0 | encode));
5009 emit_int8((unsigned char)mask);
5010 }
5011
5012 void Assembler::vzeroupper() {
5013 assert(VM_Version::supports_avx(), "");
5014 if (UseAVX < 3)
5015 {
5016 (void)vex_prefix_and_encode(xmm0, xmm0, xmm0, VEX_SIMD_NONE);
5017 emit_int8(0x77);
5018 }
5019 }
5020
5021
5022 #ifndef _LP64
5023 // 32bit only pieces of the assembler
5024
5025 void Assembler::cmp_literal32(Register src1, int32_t imm32, RelocationHolder const& rspec) {
5026 // NO PREFIX AS NEVER 64BIT
5027 InstructionMark im(this);
5028 emit_int8((unsigned char)0x81);
5029 emit_int8((unsigned char)(0xF8 | src1->encoding()));
5030 emit_data(imm32, rspec, 0);
5031 }
5032
5033 void Assembler::cmp_literal32(Address src1, int32_t imm32, RelocationHolder const& rspec) {
5034 // NO PREFIX AS NEVER 64BIT (not even 32bit versions of 64bit regs
5035 InstructionMark im(this);
5036 emit_int8((unsigned char)0x81);
5037 emit_operand(rdi, src1);
5038 emit_data(imm32, rspec, 0);
5039 }
5040
5041 // The 64-bit (32bit platform) cmpxchg compares the value at adr with the contents of rdx:rax,
5042 // and stores rcx:rbx into adr if so; otherwise, the value at adr is loaded
5043 // into rdx:rax. The ZF is set if the compared values were equal, and cleared otherwise.
5044 void Assembler::cmpxchg8(Address adr) {
5045 InstructionMark im(this);
5046 emit_int8(0x0F);
5047 emit_int8((unsigned char)0xC7);
5048 emit_operand(rcx, adr);
5049 }
5050
5051 void Assembler::decl(Register dst) {
5052 // Don't use it directly. Use MacroAssembler::decrementl() instead.
5053 emit_int8(0x48 | dst->encoding());
5054 }
5055
5056 #endif // _LP64
5057
5058 // 64bit typically doesn't use the x87 but needs to for the trig funcs
5059
5060 void Assembler::fabs() {
5061 emit_int8((unsigned char)0xD9);
5062 emit_int8((unsigned char)0xE1);
5063 }
5064
5065 void Assembler::fadd(int i) {
5066 emit_farith(0xD8, 0xC0, i);
5067 }
5068
5069 void Assembler::fadd_d(Address src) {
5070 InstructionMark im(this);
5071 emit_int8((unsigned char)0xDC);
5072 emit_operand32(rax, src);
5073 }
5074
5075 void Assembler::fadd_s(Address src) {
5076 InstructionMark im(this);
5077 emit_int8((unsigned char)0xD8);
5078 emit_operand32(rax, src);
5079 }
5080
5081 void Assembler::fadda(int i) {
5082 emit_farith(0xDC, 0xC0, i);
5083 }
5084
5085 void Assembler::faddp(int i) {
5086 emit_farith(0xDE, 0xC0, i);
5087 }
5088
5089 void Assembler::fchs() {
5090 emit_int8((unsigned char)0xD9);
5091 emit_int8((unsigned char)0xE0);
5092 }
5093
5094 void Assembler::fcom(int i) {
5095 emit_farith(0xD8, 0xD0, i);
5096 }
5097
5098 void Assembler::fcomp(int i) {
5099 emit_farith(0xD8, 0xD8, i);
5100 }
5101
5102 void Assembler::fcomp_d(Address src) {
5103 InstructionMark im(this);
5104 emit_int8((unsigned char)0xDC);
5105 emit_operand32(rbx, src);
5106 }
5107
5108 void Assembler::fcomp_s(Address src) {
5109 InstructionMark im(this);
5110 emit_int8((unsigned char)0xD8);
5111 emit_operand32(rbx, src);
5112 }
5113
5114 void Assembler::fcompp() {
5115 emit_int8((unsigned char)0xDE);
5116 emit_int8((unsigned char)0xD9);
5117 }
5118
5119 void Assembler::fcos() {
5120 emit_int8((unsigned char)0xD9);
5121 emit_int8((unsigned char)0xFF);
5122 }
5123
5124 void Assembler::fdecstp() {
5125 emit_int8((unsigned char)0xD9);
5126 emit_int8((unsigned char)0xF6);
5127 }
5128
5129 void Assembler::fdiv(int i) {
5130 emit_farith(0xD8, 0xF0, i);
5131 }
5132
5133 void Assembler::fdiv_d(Address src) {
5134 InstructionMark im(this);
5135 emit_int8((unsigned char)0xDC);
5136 emit_operand32(rsi, src);
5137 }
5138
5139 void Assembler::fdiv_s(Address src) {
5140 InstructionMark im(this);
5141 emit_int8((unsigned char)0xD8);
5142 emit_operand32(rsi, src);
5143 }
5144
5145 void Assembler::fdiva(int i) {
5146 emit_farith(0xDC, 0xF8, i);
5147 }
5148
5149 // Note: The Intel manual (Pentium Processor User's Manual, Vol.3, 1994)
5150 // is erroneous for some of the floating-point instructions below.
5151
5152 void Assembler::fdivp(int i) {
5153 emit_farith(0xDE, 0xF8, i); // ST(0) <- ST(0) / ST(1) and pop (Intel manual wrong)
5154 }
5155
5156 void Assembler::fdivr(int i) {
5157 emit_farith(0xD8, 0xF8, i);
5158 }
5159
5160 void Assembler::fdivr_d(Address src) {
5161 InstructionMark im(this);
5162 emit_int8((unsigned char)0xDC);
5163 emit_operand32(rdi, src);
5164 }
5165
5166 void Assembler::fdivr_s(Address src) {
5167 InstructionMark im(this);
5168 emit_int8((unsigned char)0xD8);
5169 emit_operand32(rdi, src);
5170 }
5171
5172 void Assembler::fdivra(int i) {
5173 emit_farith(0xDC, 0xF0, i);
5174 }
5175
5176 void Assembler::fdivrp(int i) {
5177 emit_farith(0xDE, 0xF0, i); // ST(0) <- ST(1) / ST(0) and pop (Intel manual wrong)
5178 }
5179
5180 void Assembler::ffree(int i) {
5181 emit_farith(0xDD, 0xC0, i);
5182 }
5183
5184 void Assembler::fild_d(Address adr) {
5185 InstructionMark im(this);
5186 emit_int8((unsigned char)0xDF);
5187 emit_operand32(rbp, adr);
5188 }
5189
5190 void Assembler::fild_s(Address adr) {
5191 InstructionMark im(this);
5192 emit_int8((unsigned char)0xDB);
5193 emit_operand32(rax, adr);
5194 }
5195
5196 void Assembler::fincstp() {
5197 emit_int8((unsigned char)0xD9);
5198 emit_int8((unsigned char)0xF7);
5199 }
5200
5201 void Assembler::finit() {
5202 emit_int8((unsigned char)0x9B);
5203 emit_int8((unsigned char)0xDB);
5204 emit_int8((unsigned char)0xE3);
5205 }
5206
5207 void Assembler::fist_s(Address adr) {
5208 InstructionMark im(this);
5209 emit_int8((unsigned char)0xDB);
5210 emit_operand32(rdx, adr);
5211 }
5212
5213 void Assembler::fistp_d(Address adr) {
5214 InstructionMark im(this);
5215 emit_int8((unsigned char)0xDF);
5216 emit_operand32(rdi, adr);
5217 }
5218
5219 void Assembler::fistp_s(Address adr) {
5220 InstructionMark im(this);
5221 emit_int8((unsigned char)0xDB);
5222 emit_operand32(rbx, adr);
5223 }
5224
5225 void Assembler::fld1() {
5226 emit_int8((unsigned char)0xD9);
5227 emit_int8((unsigned char)0xE8);
5228 }
5229
5230 void Assembler::fld_d(Address adr) {
5231 InstructionMark im(this);
5232 emit_int8((unsigned char)0xDD);
5233 emit_operand32(rax, adr);
5234 }
5235
5236 void Assembler::fld_s(Address adr) {
5237 InstructionMark im(this);
5238 emit_int8((unsigned char)0xD9);
5239 emit_operand32(rax, adr);
5240 }
5241
5242
5243 void Assembler::fld_s(int index) {
5244 emit_farith(0xD9, 0xC0, index);
5245 }
5246
5247 void Assembler::fld_x(Address adr) {
5248 InstructionMark im(this);
5249 emit_int8((unsigned char)0xDB);
5250 emit_operand32(rbp, adr);
5251 }
5252
5253 void Assembler::fldcw(Address src) {
5254 InstructionMark im(this);
5255 emit_int8((unsigned char)0xD9);
5256 emit_operand32(rbp, src);
5257 }
5258
5259 void Assembler::fldenv(Address src) {
5260 InstructionMark im(this);
5261 emit_int8((unsigned char)0xD9);
5262 emit_operand32(rsp, src);
5263 }
5264
5265 void Assembler::fldlg2() {
5266 emit_int8((unsigned char)0xD9);
5267 emit_int8((unsigned char)0xEC);
5268 }
5269
5270 void Assembler::fldln2() {
5271 emit_int8((unsigned char)0xD9);
5272 emit_int8((unsigned char)0xED);
5273 }
5274
5275 void Assembler::fldz() {
5276 emit_int8((unsigned char)0xD9);
5277 emit_int8((unsigned char)0xEE);
5278 }
5279
5280 void Assembler::flog() {
5281 fldln2();
5282 fxch();
5283 fyl2x();
5284 }
5285
5286 void Assembler::flog10() {
5287 fldlg2();
5288 fxch();
5289 fyl2x();
5290 }
5291
5292 void Assembler::fmul(int i) {
5293 emit_farith(0xD8, 0xC8, i);
5294 }
5295
5296 void Assembler::fmul_d(Address src) {
5297 InstructionMark im(this);
5298 emit_int8((unsigned char)0xDC);
5299 emit_operand32(rcx, src);
5300 }
5301
5302 void Assembler::fmul_s(Address src) {
5303 InstructionMark im(this);
5304 emit_int8((unsigned char)0xD8);
5305 emit_operand32(rcx, src);
5306 }
5307
5308 void Assembler::fmula(int i) {
5309 emit_farith(0xDC, 0xC8, i);
5310 }
5311
5312 void Assembler::fmulp(int i) {
5313 emit_farith(0xDE, 0xC8, i);
5314 }
5315
5316 void Assembler::fnsave(Address dst) {
5317 InstructionMark im(this);
5318 emit_int8((unsigned char)0xDD);
5319 emit_operand32(rsi, dst);
5320 }
5321
5322 void Assembler::fnstcw(Address src) {
5323 InstructionMark im(this);
5324 emit_int8((unsigned char)0x9B);
5325 emit_int8((unsigned char)0xD9);
5326 emit_operand32(rdi, src);
5327 }
5328
5329 void Assembler::fnstsw_ax() {
5330 emit_int8((unsigned char)0xDF);
5331 emit_int8((unsigned char)0xE0);
5332 }
5333
5334 void Assembler::fprem() {
5335 emit_int8((unsigned char)0xD9);
5336 emit_int8((unsigned char)0xF8);
5337 }
5338
5339 void Assembler::fprem1() {
5340 emit_int8((unsigned char)0xD9);
5341 emit_int8((unsigned char)0xF5);
5342 }
5343
5344 void Assembler::frstor(Address src) {
5345 InstructionMark im(this);
5346 emit_int8((unsigned char)0xDD);
5347 emit_operand32(rsp, src);
5348 }
5349
5350 void Assembler::fsin() {
5351 emit_int8((unsigned char)0xD9);
5352 emit_int8((unsigned char)0xFE);
5353 }
5354
5355 void Assembler::fsqrt() {
5356 emit_int8((unsigned char)0xD9);
5357 emit_int8((unsigned char)0xFA);
5358 }
5359
5360 void Assembler::fst_d(Address adr) {
5361 InstructionMark im(this);
5362 emit_int8((unsigned char)0xDD);
5363 emit_operand32(rdx, adr);
5364 }
5365
5366 void Assembler::fst_s(Address adr) {
5367 InstructionMark im(this);
5368 emit_int8((unsigned char)0xD9);
5369 emit_operand32(rdx, adr);
5370 }
5371
5372 void Assembler::fstp_d(Address adr) {
5373 InstructionMark im(this);
5374 emit_int8((unsigned char)0xDD);
5375 emit_operand32(rbx, adr);
5376 }
5377
5378 void Assembler::fstp_d(int index) {
5379 emit_farith(0xDD, 0xD8, index);
5380 }
5381
5382 void Assembler::fstp_s(Address adr) {
5383 InstructionMark im(this);
5384 emit_int8((unsigned char)0xD9);
5385 emit_operand32(rbx, adr);
5386 }
5387
5388 void Assembler::fstp_x(Address adr) {
5389 InstructionMark im(this);
5390 emit_int8((unsigned char)0xDB);
5391 emit_operand32(rdi, adr);
5392 }
5393
5394 void Assembler::fsub(int i) {
5395 emit_farith(0xD8, 0xE0, i);
5396 }
5397
5398 void Assembler::fsub_d(Address src) {
5399 InstructionMark im(this);
5400 emit_int8((unsigned char)0xDC);
5401 emit_operand32(rsp, src);
5402 }
5403
5404 void Assembler::fsub_s(Address src) {
5405 InstructionMark im(this);
5406 emit_int8((unsigned char)0xD8);
5407 emit_operand32(rsp, src);
5408 }
5409
5410 void Assembler::fsuba(int i) {
5411 emit_farith(0xDC, 0xE8, i);
5412 }
5413
5414 void Assembler::fsubp(int i) {
5415 emit_farith(0xDE, 0xE8, i); // ST(0) <- ST(0) - ST(1) and pop (Intel manual wrong)
5416 }
5417
5418 void Assembler::fsubr(int i) {
5419 emit_farith(0xD8, 0xE8, i);
5420 }
5421
5422 void Assembler::fsubr_d(Address src) {
5423 InstructionMark im(this);
5424 emit_int8((unsigned char)0xDC);
5425 emit_operand32(rbp, src);
5426 }
5427
5428 void Assembler::fsubr_s(Address src) {
5429 InstructionMark im(this);
5430 emit_int8((unsigned char)0xD8);
5431 emit_operand32(rbp, src);
5432 }
5433
5434 void Assembler::fsubra(int i) {
5435 emit_farith(0xDC, 0xE0, i);
5436 }
5437
5438 void Assembler::fsubrp(int i) {
5439 emit_farith(0xDE, 0xE0, i); // ST(0) <- ST(1) - ST(0) and pop (Intel manual wrong)
5440 }
5441
5442 void Assembler::ftan() {
5443 emit_int8((unsigned char)0xD9);
5444 emit_int8((unsigned char)0xF2);
5445 emit_int8((unsigned char)0xDD);
5446 emit_int8((unsigned char)0xD8);
5447 }
5448
5449 void Assembler::ftst() {
5450 emit_int8((unsigned char)0xD9);
5451 emit_int8((unsigned char)0xE4);
5452 }
5453
5454 void Assembler::fucomi(int i) {
5455 // make sure the instruction is supported (introduced for P6, together with cmov)
5456 guarantee(VM_Version::supports_cmov(), "illegal instruction");
5457 emit_farith(0xDB, 0xE8, i);
5458 }
5459
5460 void Assembler::fucomip(int i) {
5461 // make sure the instruction is supported (introduced for P6, together with cmov)
5462 guarantee(VM_Version::supports_cmov(), "illegal instruction");
5463 emit_farith(0xDF, 0xE8, i);
5464 }
5465
5466 void Assembler::fwait() {
5467 emit_int8((unsigned char)0x9B);
5468 }
5469
5470 void Assembler::fxch(int i) {
5471 emit_farith(0xD9, 0xC8, i);
5472 }
5473
5474 void Assembler::fyl2x() {
5475 emit_int8((unsigned char)0xD9);
5476 emit_int8((unsigned char)0xF1);
5477 }
5478
5479 void Assembler::frndint() {
5480 emit_int8((unsigned char)0xD9);
5481 emit_int8((unsigned char)0xFC);
5482 }
5483
5484 void Assembler::f2xm1() {
5485 emit_int8((unsigned char)0xD9);
5486 emit_int8((unsigned char)0xF0);
5487 }
5488
5489 void Assembler::fldl2e() {
5490 emit_int8((unsigned char)0xD9);
5491 emit_int8((unsigned char)0xEA);
5492 }
5493
5494 // SSE SIMD prefix byte values corresponding to VexSimdPrefix encoding.
5495 static int simd_pre[4] = { 0, 0x66, 0xF3, 0xF2 };
5496 // SSE opcode second byte values (first is 0x0F) corresponding to VexOpcode encoding.
5497 static int simd_opc[4] = { 0, 0, 0x38, 0x3A };
5498
5499 // Generate SSE legacy REX prefix and SIMD opcode based on VEX encoding.
5500 void Assembler::rex_prefix(Address adr, XMMRegister xreg, VexSimdPrefix pre, VexOpcode opc, bool rex_w) {
5501 if (pre > 0) {
5502 emit_int8(simd_pre[pre]);
5503 }
5504 if (rex_w) {
5505 prefixq(adr, xreg);
5506 } else {
5507 prefix(adr, xreg);
5508 }
5509 if (opc > 0) {
5510 emit_int8(0x0F);
5511 int opc2 = simd_opc[opc];
5512 if (opc2 > 0) {
5513 emit_int8(opc2);
5514 }
5515 }
5516 }
5517
5518 int Assembler::rex_prefix_and_encode(int dst_enc, int src_enc, VexSimdPrefix pre, VexOpcode opc, bool rex_w) {
5519 if (pre > 0) {
5520 emit_int8(simd_pre[pre]);
5521 }
5522 int encode = (rex_w) ? prefixq_and_encode(dst_enc, src_enc) :
5523 prefix_and_encode(dst_enc, src_enc);
5524 if (opc > 0) {
5525 emit_int8(0x0F);
5526 int opc2 = simd_opc[opc];
5527 if (opc2 > 0) {
5528 emit_int8(opc2);
5529 }
5530 }
5531 return encode;
5532 }
5533
5534
5535 void Assembler::vex_prefix(bool vex_r, bool vex_b, bool vex_x, bool vex_w, int nds_enc, VexSimdPrefix pre, VexOpcode opc, int vector_len) {
5536 if (vex_b || vex_x || vex_w || (opc == VEX_OPCODE_0F_38) || (opc == VEX_OPCODE_0F_3A)) {
5537 prefix(VEX_3bytes);
5538
5539 int byte1 = (vex_r ? VEX_R : 0) | (vex_x ? VEX_X : 0) | (vex_b ? VEX_B : 0);
5540 byte1 = (~byte1) & 0xE0;
5541 byte1 |= opc;
5542 emit_int8(byte1);
5543
5544 int byte2 = ((~nds_enc) & 0xf) << 3;
5545 byte2 |= (vex_w ? VEX_W : 0) | ((vector_len > 0) ? 4 : 0) | pre;
5546 emit_int8(byte2);
5547 } else {
5548 prefix(VEX_2bytes);
5549
5550 int byte1 = vex_r ? VEX_R : 0;
5551 byte1 = (~byte1) & 0x80;
5552 byte1 |= ((~nds_enc) & 0xf) << 3;
5553 byte1 |= ((vector_len > 0 ) ? 4 : 0) | pre;
5554 emit_int8(byte1);
5555 }
5556 }
5557
5558 // This is a 4 byte encoding
5559 void Assembler::evex_prefix(bool vex_r, bool vex_b, bool vex_x, bool vex_w, bool evex_r, bool evex_v,
5560 int nds_enc, VexSimdPrefix pre, VexOpcode opc,
5561 bool is_extended_context, bool is_merge_context,
5562 int vector_len, bool no_mask_reg ){
5563 // EVEX 0x62 prefix
5564 prefix(EVEX_4bytes);
5565 evex_encoding = (vex_w ? VEX_W : 0) | (evex_r ? EVEX_Rb : 0);
5566
5567 // P0: byte 2, initialized to RXBR`00mm
5568 // instead of not'd
5569 int byte2 = (vex_r ? VEX_R : 0) | (vex_x ? VEX_X : 0) | (vex_b ? VEX_B : 0) | (evex_r ? EVEX_Rb : 0);
5570 byte2 = (~byte2) & 0xF0;
5571 // confine opc opcode extensions in mm bits to lower two bits
5572 // of form {0F, 0F_38, 0F_3A}
5573 byte2 |= opc;
5574 emit_int8(byte2);
5575
5576 // P1: byte 3 as Wvvvv1pp
5577 int byte3 = ((~nds_enc) & 0xf) << 3;
5578 // p[10] is always 1
5579 byte3 |= EVEX_F;
5580 byte3 |= (vex_w & 1) << 7;
5581 // confine pre opcode extensions in pp bits to lower two bits
5582 // of form {66, F3, F2}
5583 byte3 |= pre;
5584 emit_int8(byte3);
5585
5586 // P2: byte 4 as zL'Lbv'aaa
5587 int byte4 = (no_mask_reg) ? 0 : 1; // kregs are implemented in the low 3 bits as aaa (hard code k1, it will be initialized for now)
5588 // EVEX.v` for extending EVEX.vvvv or VIDX
5589 byte4 |= (evex_v ? 0: EVEX_V);
5590 // third EXEC.b for broadcast actions
5591 byte4 |= (is_extended_context ? EVEX_Rb : 0);
5592 // fourth EVEX.L'L for vector length : 0 is 128, 1 is 256, 2 is 512, currently we do not support 1024
5593 byte4 |= ((vector_len) & 0x3) << 5;
5594 // last is EVEX.z for zero/merge actions
5595 byte4 |= (is_merge_context ? EVEX_Z : 0);
5596 emit_int8(byte4);
5597 }
5598
5599 void Assembler::vex_prefix(Address adr, int nds_enc, int xreg_enc, VexSimdPrefix pre,
5600 VexOpcode opc, bool vex_w, int vector_len, bool legacy_mode, bool no_mask_reg) {
5601 bool vex_r = (xreg_enc >= 8);
5602 bool vex_b = adr.base_needs_rex();
5603 bool vex_x = adr.index_needs_rex();
5604 avx_vector_len = vector_len;
5605
5606 // if vector length is turned off, revert to AVX for vectors smaller than AVX_512bit
5607 if (VM_Version::supports_avx512vl() == false) {
5608 switch (vector_len) {
5609 case AVX_128bit:
5610 case AVX_256bit:
5611 legacy_mode = true;
5612 break;
5613 }
5614 }
5615
5616 if ((UseAVX > 2) && (legacy_mode == false))
5617 {
5618 bool evex_r = (xreg_enc >= 16);
5619 bool evex_v = (nds_enc >= 16);
5620 is_evex_instruction = true;
5621 evex_prefix(vex_r, vex_b, vex_x, vex_w, evex_r, evex_v, nds_enc, pre, opc, false, false, vector_len, no_mask_reg);
5622 } else {
5623 vex_prefix(vex_r, vex_b, vex_x, vex_w, nds_enc, pre, opc, vector_len);
5624 }
5625 }
5626
5627 int Assembler::vex_prefix_and_encode(int dst_enc, int nds_enc, int src_enc, VexSimdPrefix pre, VexOpcode opc,
5628 bool vex_w, int vector_len, bool legacy_mode, bool no_mask_reg ) {
5629 bool vex_r = (dst_enc >= 8);
5630 bool vex_b = (src_enc >= 8);
5631 bool vex_x = false;
5632 avx_vector_len = vector_len;
5633
5634 // if vector length is turned off, revert to AVX for vectors smaller than AVX_512bit
5635 if (VM_Version::supports_avx512vl() == false) {
5636 switch (vector_len) {
5637 case AVX_128bit:
5638 case AVX_256bit:
5639 legacy_mode = true;
5640 break;
5641 }
5642 }
5643
5644 if ((UseAVX > 2) && (legacy_mode == false))
5645 {
5646 bool evex_r = (dst_enc >= 16);
5647 bool evex_v = (nds_enc >= 16);
5648 // can use vex_x as bank extender on rm encoding
5649 vex_x = (src_enc >= 16);
5650 evex_prefix(vex_r, vex_b, vex_x, vex_w, evex_r, evex_v, nds_enc, pre, opc, false, false, vector_len, no_mask_reg);
5651 } else {
5652 vex_prefix(vex_r, vex_b, vex_x, vex_w, nds_enc, pre, opc, vector_len);
5653 }
5654
5655 // return modrm byte components for operands
5656 return (((dst_enc & 7) << 3) | (src_enc & 7));
5657 }
5658
5659
5660 void Assembler::simd_prefix(XMMRegister xreg, XMMRegister nds, Address adr, VexSimdPrefix pre,
5661 bool no_mask_reg, VexOpcode opc, bool rex_w, int vector_len, bool legacy_mode) {
5662 if (UseAVX > 0) {
5663 int xreg_enc = xreg->encoding();
5664 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
5665 vex_prefix(adr, nds_enc, xreg_enc, pre, opc, rex_w, vector_len, legacy_mode, no_mask_reg);
5666 } else {
5667 assert((nds == xreg) || (nds == xnoreg), "wrong sse encoding");
5668 rex_prefix(adr, xreg, pre, opc, rex_w);
5669 }
5670 }
5671
5672 int Assembler::simd_prefix_and_encode(XMMRegister dst, XMMRegister nds, XMMRegister src, VexSimdPrefix pre,
5673 bool no_mask_reg, VexOpcode opc, bool rex_w, int vector_len, bool legacy_mode) {
5674 int dst_enc = dst->encoding();
5675 int src_enc = src->encoding();
5676 if (UseAVX > 0) {
5677 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
5678 return vex_prefix_and_encode(dst_enc, nds_enc, src_enc, pre, opc, rex_w, vector_len, legacy_mode, no_mask_reg);
5679 } else {
5680 assert((nds == dst) || (nds == src) || (nds == xnoreg), "wrong sse encoding");
5681 return rex_prefix_and_encode(dst_enc, src_enc, pre, opc, rex_w);
5682 }
5683 }
5684
5685 int Assembler::kreg_prefix_and_encode(KRegister dst, KRegister nds, KRegister src, VexSimdPrefix pre,
5686 bool no_mask_reg, VexOpcode opc, bool rex_w, int vector_len) {
5687 int dst_enc = dst->encoding();
5688 int src_enc = src->encoding();
5689 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
5690 return vex_prefix_and_encode(dst_enc, nds_enc, src_enc, pre, opc, rex_w, vector_len, true, no_mask_reg);
5691 }
5692
5693 int Assembler::kreg_prefix_and_encode(KRegister dst, KRegister nds, Register src, VexSimdPrefix pre,
5694 bool no_mask_reg, VexOpcode opc, bool rex_w, int vector_len) {
5695 int dst_enc = dst->encoding();
5696 int src_enc = src->encoding();
5697 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
5698 return vex_prefix_and_encode(dst_enc, nds_enc, src_enc, pre, opc, rex_w, vector_len, true, no_mask_reg);
5699 }
5700
5701 void Assembler::emit_simd_arith(int opcode, XMMRegister dst, Address src, VexSimdPrefix pre, bool no_mask_reg, bool legacy_mode) {
5702 InstructionMark im(this);
5703 simd_prefix(dst, dst, src, pre, no_mask_reg, VEX_OPCODE_0F, false, AVX_128bit, legacy_mode);
5704 emit_int8(opcode);
5705 emit_operand(dst, src);
5706 }
5707
5708 void Assembler::emit_simd_arith_q(int opcode, XMMRegister dst, Address src, VexSimdPrefix pre, bool no_mask_reg) {
5709 InstructionMark im(this);
5710 simd_prefix_q(dst, dst, src, pre, no_mask_reg);
5711 emit_int8(opcode);
5712 emit_operand(dst, src);
5713 }
5714
5715 void Assembler::emit_simd_arith(int opcode, XMMRegister dst, XMMRegister src, VexSimdPrefix pre, bool no_mask_reg, bool legacy_mode) {
5716 int encode = simd_prefix_and_encode(dst, dst, src, pre, no_mask_reg, VEX_OPCODE_0F, false, AVX_128bit, legacy_mode);
5717 emit_int8(opcode);
5718 emit_int8((unsigned char)(0xC0 | encode));
5719 }
5720
5721 void Assembler::emit_simd_arith_q(int opcode, XMMRegister dst, XMMRegister src, VexSimdPrefix pre, bool no_mask_reg) {
5722 int encode = simd_prefix_and_encode(dst, dst, src, pre, no_mask_reg, VEX_OPCODE_0F, true, AVX_128bit);
5723 emit_int8(opcode);
5724 emit_int8((unsigned char)(0xC0 | encode));
5725 }
5726
5727 // Versions with no second source register (non-destructive source).
5728 void Assembler::emit_simd_arith_nonds(int opcode, XMMRegister dst, Address src, VexSimdPrefix pre, bool opNoRegMask) {
5729 InstructionMark im(this);
5730 simd_prefix(dst, xnoreg, src, pre, opNoRegMask);
5731 emit_int8(opcode);
5732 emit_operand(dst, src);
5733 }
5734
5735 void Assembler::emit_simd_arith_nonds_q(int opcode, XMMRegister dst, Address src, VexSimdPrefix pre, bool opNoRegMask) {
5736 InstructionMark im(this);
5737 simd_prefix_q(dst, xnoreg, src, pre, opNoRegMask);
5738 emit_int8(opcode);
5739 emit_operand(dst, src);
5740 }
5741
5742 void Assembler::emit_simd_arith_nonds(int opcode, XMMRegister dst, XMMRegister src, VexSimdPrefix pre, bool no_mask_reg, bool legacy_mode) {
5743 int encode = simd_prefix_and_encode(dst, xnoreg, src, pre, no_mask_reg, VEX_OPCODE_0F, legacy_mode, AVX_128bit);
5744 emit_int8(opcode);
5745 emit_int8((unsigned char)(0xC0 | encode));
5746 }
5747
5748 void Assembler::emit_simd_arith_nonds_q(int opcode, XMMRegister dst, XMMRegister src, VexSimdPrefix pre, bool no_mask_reg) {
5749 int encode = simd_prefix_and_encode(dst, xnoreg, src, pre, no_mask_reg, VEX_OPCODE_0F, true, AVX_128bit);
5750 emit_int8(opcode);
5751 emit_int8((unsigned char)(0xC0 | encode));
5752 }
5753
5754 // 3-operands AVX instructions
5755 void Assembler::emit_vex_arith(int opcode, XMMRegister dst, XMMRegister nds, Address src,
5756 VexSimdPrefix pre, int vector_len, bool no_mask_reg, bool legacy_mode) {
5757 InstructionMark im(this);
5758 vex_prefix(dst, nds, src, pre, vector_len, no_mask_reg, legacy_mode);
5759 emit_int8(opcode);
5760 emit_operand(dst, src);
5761 }
5762
5763 void Assembler::emit_vex_arith_q(int opcode, XMMRegister dst, XMMRegister nds,
5764 Address src, VexSimdPrefix pre, int vector_len, bool no_mask_reg) {
5765 InstructionMark im(this);
5766 vex_prefix_q(dst, nds, src, pre, vector_len, no_mask_reg);
5767 emit_int8(opcode);
5768 emit_operand(dst, src);
5769 }
5770
5771 void Assembler::emit_vex_arith(int opcode, XMMRegister dst, XMMRegister nds, XMMRegister src,
5772 VexSimdPrefix pre, int vector_len, bool no_mask_reg, bool legacy_mode) {
5773 int encode = vex_prefix_and_encode(dst, nds, src, pre, vector_len, VEX_OPCODE_0F, false, no_mask_reg);
5774 emit_int8(opcode);
5775 emit_int8((unsigned char)(0xC0 | encode));
5776 }
5777
5778 void Assembler::emit_vex_arith_q(int opcode, XMMRegister dst, XMMRegister nds, XMMRegister src,
5779 VexSimdPrefix pre, int vector_len, bool no_mask_reg) {
5780 int src_enc = src->encoding();
5781 int dst_enc = dst->encoding();
5782 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
5783 int encode = vex_prefix_and_encode(dst_enc, nds_enc, src_enc, pre, VEX_OPCODE_0F, true, vector_len, false, no_mask_reg);
5784 emit_int8(opcode);
5785 emit_int8((unsigned char)(0xC0 | encode));
5786 }
5787
5788 #ifndef _LP64
5789
5790 void Assembler::incl(Register dst) {
5791 // Don't use it directly. Use MacroAssembler::incrementl() instead.
5792 emit_int8(0x40 | dst->encoding());
5793 }
5794
5795 void Assembler::lea(Register dst, Address src) {
5796 leal(dst, src);
5797 }
5798
5799 void Assembler::mov_literal32(Address dst, int32_t imm32, RelocationHolder const& rspec) {
5800 InstructionMark im(this);
5801 emit_int8((unsigned char)0xC7);
5802 emit_operand(rax, dst);
5803 emit_data((int)imm32, rspec, 0);
5804 }
5805
5806 void Assembler::mov_literal32(Register dst, int32_t imm32, RelocationHolder const& rspec) {
5807 InstructionMark im(this);
5808 int encode = prefix_and_encode(dst->encoding());
5809 emit_int8((unsigned char)(0xB8 | encode));
5810 emit_data((int)imm32, rspec, 0);
5811 }
5812
5813 void Assembler::popa() { // 32bit
5814 emit_int8(0x61);
5815 }
5816
5817 void Assembler::push_literal32(int32_t imm32, RelocationHolder const& rspec) {
5818 InstructionMark im(this);
5819 emit_int8(0x68);
5820 emit_data(imm32, rspec, 0);
5821 }
5822
5823 void Assembler::pusha() { // 32bit
5824 emit_int8(0x60);
5825 }
5826
5827 void Assembler::set_byte_if_not_zero(Register dst) {
5828 emit_int8(0x0F);
5829 emit_int8((unsigned char)0x95);
5830 emit_int8((unsigned char)(0xE0 | dst->encoding()));
5831 }
5832
5833 void Assembler::shldl(Register dst, Register src) {
5834 emit_int8(0x0F);
5835 emit_int8((unsigned char)0xA5);
5836 emit_int8((unsigned char)(0xC0 | src->encoding() << 3 | dst->encoding()));
5837 }
5838
5839 void Assembler::shrdl(Register dst, Register src) {
5840 emit_int8(0x0F);
5841 emit_int8((unsigned char)0xAD);
5842 emit_int8((unsigned char)(0xC0 | src->encoding() << 3 | dst->encoding()));
5843 }
5844
5845 #else // LP64
5846
5847 void Assembler::set_byte_if_not_zero(Register dst) {
5848 int enc = prefix_and_encode(dst->encoding(), true);
5849 emit_int8(0x0F);
5850 emit_int8((unsigned char)0x95);
5851 emit_int8((unsigned char)(0xE0 | enc));
5852 }
5853
5854 // 64bit only pieces of the assembler
5855 // This should only be used by 64bit instructions that can use rip-relative
5856 // it cannot be used by instructions that want an immediate value.
5857
5858 bool Assembler::reachable(AddressLiteral adr) {
5859 int64_t disp;
5860 // None will force a 64bit literal to the code stream. Likely a placeholder
5861 // for something that will be patched later and we need to certain it will
5862 // always be reachable.
5863 if (adr.reloc() == relocInfo::none) {
5864 return false;
5865 }
5866 if (adr.reloc() == relocInfo::internal_word_type) {
5867 // This should be rip relative and easily reachable.
5868 return true;
5869 }
5870 if (adr.reloc() == relocInfo::virtual_call_type ||
5871 adr.reloc() == relocInfo::opt_virtual_call_type ||
5872 adr.reloc() == relocInfo::static_call_type ||
5873 adr.reloc() == relocInfo::static_stub_type ) {
5874 // This should be rip relative within the code cache and easily
5875 // reachable until we get huge code caches. (At which point
5876 // ic code is going to have issues).
5877 return true;
5878 }
5879 if (adr.reloc() != relocInfo::external_word_type &&
5880 adr.reloc() != relocInfo::poll_return_type && // these are really external_word but need special
5881 adr.reloc() != relocInfo::poll_type && // relocs to identify them
5882 adr.reloc() != relocInfo::runtime_call_type ) {
5883 return false;
5884 }
5885
5886 // Stress the correction code
5887 if (ForceUnreachable) {
5888 // Must be runtimecall reloc, see if it is in the codecache
5889 // Flipping stuff in the codecache to be unreachable causes issues
5890 // with things like inline caches where the additional instructions
5891 // are not handled.
5892 if (CodeCache::find_blob(adr._target) == NULL) {
5893 return false;
5894 }
5895 }
5896 // For external_word_type/runtime_call_type if it is reachable from where we
5897 // are now (possibly a temp buffer) and where we might end up
5898 // anywhere in the codeCache then we are always reachable.
5899 // This would have to change if we ever save/restore shared code
5900 // to be more pessimistic.
5901 disp = (int64_t)adr._target - ((int64_t)CodeCache::low_bound() + sizeof(int));
5902 if (!is_simm32(disp)) return false;
5903 disp = (int64_t)adr._target - ((int64_t)CodeCache::high_bound() + sizeof(int));
5904 if (!is_simm32(disp)) return false;
5905
5906 disp = (int64_t)adr._target - ((int64_t)pc() + sizeof(int));
5907
5908 // Because rip relative is a disp + address_of_next_instruction and we
5909 // don't know the value of address_of_next_instruction we apply a fudge factor
5910 // to make sure we will be ok no matter the size of the instruction we get placed into.
5911 // We don't have to fudge the checks above here because they are already worst case.
5912
5913 // 12 == override/rex byte, opcode byte, rm byte, sib byte, a 4-byte disp , 4-byte literal
5914 // + 4 because better safe than sorry.
5915 const int fudge = 12 + 4;
5916 if (disp < 0) {
5917 disp -= fudge;
5918 } else {
5919 disp += fudge;
5920 }
5921 return is_simm32(disp);
5922 }
5923
5924 // Check if the polling page is not reachable from the code cache using rip-relative
5925 // addressing.
5926 bool Assembler::is_polling_page_far() {
5927 intptr_t addr = (intptr_t)os::get_polling_page();
5928 return ForceUnreachable ||
5929 !is_simm32(addr - (intptr_t)CodeCache::low_bound()) ||
5930 !is_simm32(addr - (intptr_t)CodeCache::high_bound());
5931 }
5932
5933 void Assembler::emit_data64(jlong data,
5934 relocInfo::relocType rtype,
5935 int format) {
5936 if (rtype == relocInfo::none) {
5937 emit_int64(data);
5938 } else {
5939 emit_data64(data, Relocation::spec_simple(rtype), format);
5940 }
5941 }
5942
5943 void Assembler::emit_data64(jlong data,
5944 RelocationHolder const& rspec,
5945 int format) {
5946 assert(imm_operand == 0, "default format must be immediate in this file");
5947 assert(imm_operand == format, "must be immediate");
5948 assert(inst_mark() != NULL, "must be inside InstructionMark");
5949 // Do not use AbstractAssembler::relocate, which is not intended for
5950 // embedded words. Instead, relocate to the enclosing instruction.
5951 code_section()->relocate(inst_mark(), rspec, format);
5952 #ifdef ASSERT
5953 check_relocation(rspec, format);
5954 #endif
5955 emit_int64(data);
5956 }
5957
5958 int Assembler::prefix_and_encode(int reg_enc, bool byteinst) {
5959 if (reg_enc >= 8) {
5960 prefix(REX_B);
5961 reg_enc -= 8;
5962 } else if (byteinst && reg_enc >= 4) {
5963 prefix(REX);
5964 }
5965 return reg_enc;
5966 }
5967
5968 int Assembler::prefixq_and_encode(int reg_enc) {
5969 if (reg_enc < 8) {
5970 prefix(REX_W);
5971 } else {
5972 prefix(REX_WB);
5973 reg_enc -= 8;
5974 }
5975 return reg_enc;
5976 }
5977
5978 int Assembler::prefix_and_encode(int dst_enc, int src_enc, bool byteinst) {
5979 if (dst_enc < 8) {
5980 if (src_enc >= 8) {
5981 prefix(REX_B);
5982 src_enc -= 8;
5983 } else if (byteinst && src_enc >= 4) {
5984 prefix(REX);
5985 }
5986 } else {
5987 if (src_enc < 8) {
5988 prefix(REX_R);
5989 } else {
5990 prefix(REX_RB);
5991 src_enc -= 8;
5992 }
5993 dst_enc -= 8;
5994 }
5995 return dst_enc << 3 | src_enc;
5996 }
5997
5998 int Assembler::prefixq_and_encode(int dst_enc, int src_enc) {
5999 if (dst_enc < 8) {
6000 if (src_enc < 8) {
6001 prefix(REX_W);
6002 } else {
6003 prefix(REX_WB);
6004 src_enc -= 8;
6005 }
6006 } else {
6007 if (src_enc < 8) {
6008 prefix(REX_WR);
6009 } else {
6010 prefix(REX_WRB);
6011 src_enc -= 8;
6012 }
6013 dst_enc -= 8;
6014 }
6015 return dst_enc << 3 | src_enc;
6016 }
6017
6018 void Assembler::prefix(Register reg) {
6019 if (reg->encoding() >= 8) {
6020 prefix(REX_B);
6021 }
6022 }
6023
6024 void Assembler::prefix(Address adr) {
6025 if (adr.base_needs_rex()) {
6026 if (adr.index_needs_rex()) {
6027 prefix(REX_XB);
6028 } else {
6029 prefix(REX_B);
6030 }
6031 } else {
6032 if (adr.index_needs_rex()) {
6033 prefix(REX_X);
6034 }
6035 }
6036 }
6037
6038 void Assembler::prefixq(Address adr) {
6039 if (adr.base_needs_rex()) {
6040 if (adr.index_needs_rex()) {
6041 prefix(REX_WXB);
6042 } else {
6043 prefix(REX_WB);
6044 }
6045 } else {
6046 if (adr.index_needs_rex()) {
6047 prefix(REX_WX);
6048 } else {
6049 prefix(REX_W);
6050 }
6051 }
6052 }
6053
6054
6055 void Assembler::prefix(Address adr, Register reg, bool byteinst) {
6056 if (reg->encoding() < 8) {
6057 if (adr.base_needs_rex()) {
6058 if (adr.index_needs_rex()) {
6059 prefix(REX_XB);
6060 } else {
6061 prefix(REX_B);
6062 }
6063 } else {
6064 if (adr.index_needs_rex()) {
6065 prefix(REX_X);
6066 } else if (byteinst && reg->encoding() >= 4 ) {
6067 prefix(REX);
6068 }
6069 }
6070 } else {
6071 if (adr.base_needs_rex()) {
6072 if (adr.index_needs_rex()) {
6073 prefix(REX_RXB);
6074 } else {
6075 prefix(REX_RB);
6076 }
6077 } else {
6078 if (adr.index_needs_rex()) {
6079 prefix(REX_RX);
6080 } else {
6081 prefix(REX_R);
6082 }
6083 }
6084 }
6085 }
6086
6087 void Assembler::prefixq(Address adr, Register src) {
6088 if (src->encoding() < 8) {
6089 if (adr.base_needs_rex()) {
6090 if (adr.index_needs_rex()) {
6091 prefix(REX_WXB);
6092 } else {
6093 prefix(REX_WB);
6094 }
6095 } else {
6096 if (adr.index_needs_rex()) {
6097 prefix(REX_WX);
6098 } else {
6099 prefix(REX_W);
6100 }
6101 }
6102 } else {
6103 if (adr.base_needs_rex()) {
6104 if (adr.index_needs_rex()) {
6105 prefix(REX_WRXB);
6106 } else {
6107 prefix(REX_WRB);
6108 }
6109 } else {
6110 if (adr.index_needs_rex()) {
6111 prefix(REX_WRX);
6112 } else {
6113 prefix(REX_WR);
6114 }
6115 }
6116 }
6117 }
6118
6119 void Assembler::prefix(Address adr, XMMRegister reg) {
6120 if (reg->encoding() < 8) {
6121 if (adr.base_needs_rex()) {
6122 if (adr.index_needs_rex()) {
6123 prefix(REX_XB);
6124 } else {
6125 prefix(REX_B);
6126 }
6127 } else {
6128 if (adr.index_needs_rex()) {
6129 prefix(REX_X);
6130 }
6131 }
6132 } else {
6133 if (adr.base_needs_rex()) {
6134 if (adr.index_needs_rex()) {
6135 prefix(REX_RXB);
6136 } else {
6137 prefix(REX_RB);
6138 }
6139 } else {
6140 if (adr.index_needs_rex()) {
6141 prefix(REX_RX);
6142 } else {
6143 prefix(REX_R);
6144 }
6145 }
6146 }
6147 }
6148
6149 void Assembler::prefixq(Address adr, XMMRegister src) {
6150 if (src->encoding() < 8) {
6151 if (adr.base_needs_rex()) {
6152 if (adr.index_needs_rex()) {
6153 prefix(REX_WXB);
6154 } else {
6155 prefix(REX_WB);
6156 }
6157 } else {
6158 if (adr.index_needs_rex()) {
6159 prefix(REX_WX);
6160 } else {
6161 prefix(REX_W);
6162 }
6163 }
6164 } else {
6165 if (adr.base_needs_rex()) {
6166 if (adr.index_needs_rex()) {
6167 prefix(REX_WRXB);
6168 } else {
6169 prefix(REX_WRB);
6170 }
6171 } else {
6172 if (adr.index_needs_rex()) {
6173 prefix(REX_WRX);
6174 } else {
6175 prefix(REX_WR);
6176 }
6177 }
6178 }
6179 }
6180
6181 void Assembler::adcq(Register dst, int32_t imm32) {
6182 (void) prefixq_and_encode(dst->encoding());
6183 emit_arith(0x81, 0xD0, dst, imm32);
6184 }
6185
6186 void Assembler::adcq(Register dst, Address src) {
6187 InstructionMark im(this);
6188 prefixq(src, dst);
6189 emit_int8(0x13);
6190 emit_operand(dst, src);
6191 }
6192
6193 void Assembler::adcq(Register dst, Register src) {
6194 (void) prefixq_and_encode(dst->encoding(), src->encoding());
6195 emit_arith(0x13, 0xC0, dst, src);
6196 }
6197
6198 void Assembler::addq(Address dst, int32_t imm32) {
6199 InstructionMark im(this);
6200 prefixq(dst);
6201 emit_arith_operand(0x81, rax, dst,imm32);
6202 }
6203
6204 void Assembler::addq(Address dst, Register src) {
6205 InstructionMark im(this);
6206 prefixq(dst, src);
6207 emit_int8(0x01);
6208 emit_operand(src, dst);
6209 }
6210
6211 void Assembler::addq(Register dst, int32_t imm32) {
6212 (void) prefixq_and_encode(dst->encoding());
6213 emit_arith(0x81, 0xC0, dst, imm32);
6214 }
6215
6216 void Assembler::addq(Register dst, Address src) {
6217 InstructionMark im(this);
6218 prefixq(src, dst);
6219 emit_int8(0x03);
6220 emit_operand(dst, src);
6221 }
6222
6223 void Assembler::addq(Register dst, Register src) {
6224 (void) prefixq_and_encode(dst->encoding(), src->encoding());
6225 emit_arith(0x03, 0xC0, dst, src);
6226 }
6227
6228 void Assembler::adcxq(Register dst, Register src) {
6229 //assert(VM_Version::supports_adx(), "adx instructions not supported");
6230 emit_int8((unsigned char)0x66);
6231 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
6232 emit_int8(0x0F);
6233 emit_int8(0x38);
6234 emit_int8((unsigned char)0xF6);
6235 emit_int8((unsigned char)(0xC0 | encode));
6236 }
6237
6238 void Assembler::adoxq(Register dst, Register src) {
6239 //assert(VM_Version::supports_adx(), "adx instructions not supported");
6240 emit_int8((unsigned char)0xF3);
6241 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
6242 emit_int8(0x0F);
6243 emit_int8(0x38);
6244 emit_int8((unsigned char)0xF6);
6245 emit_int8((unsigned char)(0xC0 | encode));
6246 }
6247
6248 void Assembler::andq(Address dst, int32_t imm32) {
6249 InstructionMark im(this);
6250 prefixq(dst);
6251 emit_int8((unsigned char)0x81);
6252 emit_operand(rsp, dst, 4);
6253 emit_int32(imm32);
6254 }
6255
6256 void Assembler::andq(Register dst, int32_t imm32) {
6257 (void) prefixq_and_encode(dst->encoding());
6258 emit_arith(0x81, 0xE0, dst, imm32);
6259 }
6260
6261 void Assembler::andq(Register dst, Address src) {
6262 InstructionMark im(this);
6263 prefixq(src, dst);
6264 emit_int8(0x23);
6265 emit_operand(dst, src);
6266 }
6267
6268 void Assembler::andq(Register dst, Register src) {
6269 (void) prefixq_and_encode(dst->encoding(), src->encoding());
6270 emit_arith(0x23, 0xC0, dst, src);
6271 }
6272
6273 void Assembler::andnq(Register dst, Register src1, Register src2) {
6274 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
6275 int encode = vex_prefix_0F38_and_encode_q(dst, src1, src2);
6276 emit_int8((unsigned char)0xF2);
6277 emit_int8((unsigned char)(0xC0 | encode));
6278 }
6279
6280 void Assembler::andnq(Register dst, Register src1, Address src2) {
6281 if (VM_Version::supports_evex()) {
6282 tuple_type = EVEX_T1S;
6283 input_size_in_bits = EVEX_64bit;
6284 }
6285 InstructionMark im(this);
6286 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
6287 vex_prefix_0F38_q(dst, src1, src2);
6288 emit_int8((unsigned char)0xF2);
6289 emit_operand(dst, src2);
6290 }
6291
6292 void Assembler::bsfq(Register dst, Register src) {
6293 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
6294 emit_int8(0x0F);
6295 emit_int8((unsigned char)0xBC);
6296 emit_int8((unsigned char)(0xC0 | encode));
6297 }
6298
6299 void Assembler::bsrq(Register dst, Register src) {
6300 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
6301 emit_int8(0x0F);
6302 emit_int8((unsigned char)0xBD);
6303 emit_int8((unsigned char)(0xC0 | encode));
6304 }
6305
6306 void Assembler::bswapq(Register reg) {
6307 int encode = prefixq_and_encode(reg->encoding());
6308 emit_int8(0x0F);
6309 emit_int8((unsigned char)(0xC8 | encode));
6310 }
6311
6312 void Assembler::blsiq(Register dst, Register src) {
6313 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
6314 int encode = vex_prefix_0F38_and_encode_q(rbx, dst, src);
6315 emit_int8((unsigned char)0xF3);
6316 emit_int8((unsigned char)(0xC0 | encode));
6317 }
6318
6319 void Assembler::blsiq(Register dst, Address src) {
6320 InstructionMark im(this);
6321 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
6322 vex_prefix_0F38_q(rbx, dst, src);
6323 emit_int8((unsigned char)0xF3);
6324 emit_operand(rbx, src);
6325 }
6326
6327 void Assembler::blsmskq(Register dst, Register src) {
6328 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
6329 int encode = vex_prefix_0F38_and_encode_q(rdx, dst, src);
6330 emit_int8((unsigned char)0xF3);
6331 emit_int8((unsigned char)(0xC0 | encode));
6332 }
6333
6334 void Assembler::blsmskq(Register dst, Address src) {
6335 InstructionMark im(this);
6336 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
6337 vex_prefix_0F38_q(rdx, dst, src);
6338 emit_int8((unsigned char)0xF3);
6339 emit_operand(rdx, src);
6340 }
6341
6342 void Assembler::blsrq(Register dst, Register src) {
6343 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
6344 int encode = vex_prefix_0F38_and_encode_q(rcx, dst, src);
6345 emit_int8((unsigned char)0xF3);
6346 emit_int8((unsigned char)(0xC0 | encode));
6347 }
6348
6349 void Assembler::blsrq(Register dst, Address src) {
6350 InstructionMark im(this);
6351 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
6352 vex_prefix_0F38_q(rcx, dst, src);
6353 emit_int8((unsigned char)0xF3);
6354 emit_operand(rcx, src);
6355 }
6356
6357 void Assembler::cdqq() {
6358 prefix(REX_W);
6359 emit_int8((unsigned char)0x99);
6360 }
6361
6362 void Assembler::clflush(Address adr) {
6363 prefix(adr);
6364 emit_int8(0x0F);
6365 emit_int8((unsigned char)0xAE);
6366 emit_operand(rdi, adr);
6367 }
6368
6369 void Assembler::cmovq(Condition cc, Register dst, Register src) {
6370 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
6371 emit_int8(0x0F);
6372 emit_int8(0x40 | cc);
6373 emit_int8((unsigned char)(0xC0 | encode));
6374 }
6375
6376 void Assembler::cmovq(Condition cc, Register dst, Address src) {
6377 InstructionMark im(this);
6378 prefixq(src, dst);
6379 emit_int8(0x0F);
6380 emit_int8(0x40 | cc);
6381 emit_operand(dst, src);
6382 }
6383
6384 void Assembler::cmpq(Address dst, int32_t imm32) {
6385 InstructionMark im(this);
6386 prefixq(dst);
6387 emit_int8((unsigned char)0x81);
6388 emit_operand(rdi, dst, 4);
6389 emit_int32(imm32);
6390 }
6391
6392 void Assembler::cmpq(Register dst, int32_t imm32) {
6393 (void) prefixq_and_encode(dst->encoding());
6394 emit_arith(0x81, 0xF8, dst, imm32);
6395 }
6396
6397 void Assembler::cmpq(Address dst, Register src) {
6398 InstructionMark im(this);
6399 prefixq(dst, src);
6400 emit_int8(0x3B);
6401 emit_operand(src, dst);
6402 }
6403
6404 void Assembler::cmpq(Register dst, Register src) {
6405 (void) prefixq_and_encode(dst->encoding(), src->encoding());
6406 emit_arith(0x3B, 0xC0, dst, src);
6407 }
6408
6409 void Assembler::cmpq(Register dst, Address src) {
6410 InstructionMark im(this);
6411 prefixq(src, dst);
6412 emit_int8(0x3B);
6413 emit_operand(dst, src);
6414 }
6415
6416 void Assembler::cmpxchgq(Register reg, Address adr) {
6417 InstructionMark im(this);
6418 prefixq(adr, reg);
6419 emit_int8(0x0F);
6420 emit_int8((unsigned char)0xB1);
6421 emit_operand(reg, adr);
6422 }
6423
6424 void Assembler::cvtsi2sdq(XMMRegister dst, Register src) {
6425 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6426 int encode = simd_prefix_and_encode_q(dst, dst, src, VEX_SIMD_F2, true);
6427 emit_int8(0x2A);
6428 emit_int8((unsigned char)(0xC0 | encode));
6429 }
6430
6431 void Assembler::cvtsi2sdq(XMMRegister dst, Address src) {
6432 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6433 if (VM_Version::supports_evex()) {
6434 tuple_type = EVEX_T1S;
6435 input_size_in_bits = EVEX_32bit;
6436 }
6437 InstructionMark im(this);
6438 simd_prefix_q(dst, dst, src, VEX_SIMD_F2, true);
6439 emit_int8(0x2A);
6440 emit_operand(dst, src);
6441 }
6442
6443 void Assembler::cvtsi2ssq(XMMRegister dst, Register src) {
6444 NOT_LP64(assert(VM_Version::supports_sse(), ""));
6445 int encode = simd_prefix_and_encode_q(dst, dst, src, VEX_SIMD_F3, true);
6446 emit_int8(0x2A);
6447 emit_int8((unsigned char)(0xC0 | encode));
6448 }
6449
6450 void Assembler::cvtsi2ssq(XMMRegister dst, Address src) {
6451 NOT_LP64(assert(VM_Version::supports_sse(), ""));
6452 if (VM_Version::supports_evex()) {
6453 tuple_type = EVEX_T1S;
6454 input_size_in_bits = EVEX_32bit;
6455 }
6456 InstructionMark im(this);
6457 simd_prefix_q(dst, dst, src, VEX_SIMD_F3, true);
6458 emit_int8(0x2A);
6459 emit_operand(dst, src);
6460 }
6461
6462 void Assembler::cvttsd2siq(Register dst, XMMRegister src) {
6463 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6464 int encode = simd_prefix_and_encode_q(dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, true);
6465 emit_int8(0x2C);
6466 emit_int8((unsigned char)(0xC0 | encode));
6467 }
6468
6469 void Assembler::cvttss2siq(Register dst, XMMRegister src) {
6470 NOT_LP64(assert(VM_Version::supports_sse(), ""));
6471 int encode = simd_prefix_and_encode_q(dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, true);
6472 emit_int8(0x2C);
6473 emit_int8((unsigned char)(0xC0 | encode));
6474 }
6475
6476 void Assembler::decl(Register dst) {
6477 // Don't use it directly. Use MacroAssembler::decrementl() instead.
6478 // Use two-byte form (one-byte form is a REX prefix in 64-bit mode)
6479 int encode = prefix_and_encode(dst->encoding());
6480 emit_int8((unsigned char)0xFF);
6481 emit_int8((unsigned char)(0xC8 | encode));
6482 }
6483
6484 void Assembler::decq(Register dst) {
6485 // Don't use it directly. Use MacroAssembler::decrementq() instead.
6486 // Use two-byte form (one-byte from is a REX prefix in 64-bit mode)
6487 int encode = prefixq_and_encode(dst->encoding());
6488 emit_int8((unsigned char)0xFF);
6489 emit_int8(0xC8 | encode);
6490 }
6491
6492 void Assembler::decq(Address dst) {
6493 // Don't use it directly. Use MacroAssembler::decrementq() instead.
6494 InstructionMark im(this);
6495 prefixq(dst);
6496 emit_int8((unsigned char)0xFF);
6497 emit_operand(rcx, dst);
6498 }
6499
6500 void Assembler::fxrstor(Address src) {
6501 prefixq(src);
6502 emit_int8(0x0F);
6503 emit_int8((unsigned char)0xAE);
6504 emit_operand(as_Register(1), src);
6505 }
6506
6507 void Assembler::fxsave(Address dst) {
6508 prefixq(dst);
6509 emit_int8(0x0F);
6510 emit_int8((unsigned char)0xAE);
6511 emit_operand(as_Register(0), dst);
6512 }
6513
6514 void Assembler::idivq(Register src) {
6515 int encode = prefixq_and_encode(src->encoding());
6516 emit_int8((unsigned char)0xF7);
6517 emit_int8((unsigned char)(0xF8 | encode));
6518 }
6519
6520 void Assembler::imulq(Register dst, Register src) {
6521 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
6522 emit_int8(0x0F);
6523 emit_int8((unsigned char)0xAF);
6524 emit_int8((unsigned char)(0xC0 | encode));
6525 }
6526
6527 void Assembler::imulq(Register dst, Register src, int value) {
6528 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
6529 if (is8bit(value)) {
6530 emit_int8(0x6B);
6531 emit_int8((unsigned char)(0xC0 | encode));
6532 emit_int8(value & 0xFF);
6533 } else {
6534 emit_int8(0x69);
6535 emit_int8((unsigned char)(0xC0 | encode));
6536 emit_int32(value);
6537 }
6538 }
6539
6540 void Assembler::imulq(Register dst, Address src) {
6541 InstructionMark im(this);
6542 prefixq(src, dst);
6543 emit_int8(0x0F);
6544 emit_int8((unsigned char) 0xAF);
6545 emit_operand(dst, src);
6546 }
6547
6548 void Assembler::incl(Register dst) {
6549 // Don't use it directly. Use MacroAssembler::incrementl() instead.
6550 // Use two-byte form (one-byte from is a REX prefix in 64-bit mode)
6551 int encode = prefix_and_encode(dst->encoding());
6552 emit_int8((unsigned char)0xFF);
6553 emit_int8((unsigned char)(0xC0 | encode));
6554 }
6555
6556 void Assembler::incq(Register dst) {
6557 // Don't use it directly. Use MacroAssembler::incrementq() instead.
6558 // Use two-byte form (one-byte from is a REX prefix in 64-bit mode)
6559 int encode = prefixq_and_encode(dst->encoding());
6560 emit_int8((unsigned char)0xFF);
6561 emit_int8((unsigned char)(0xC0 | encode));
6562 }
6563
6564 void Assembler::incq(Address dst) {
6565 // Don't use it directly. Use MacroAssembler::incrementq() instead.
6566 InstructionMark im(this);
6567 prefixq(dst);
6568 emit_int8((unsigned char)0xFF);
6569 emit_operand(rax, dst);
6570 }
6571
6572 void Assembler::lea(Register dst, Address src) {
6573 leaq(dst, src);
6574 }
6575
6576 void Assembler::leaq(Register dst, Address src) {
6577 InstructionMark im(this);
6578 prefixq(src, dst);
6579 emit_int8((unsigned char)0x8D);
6580 emit_operand(dst, src);
6581 }
6582
6583 void Assembler::mov64(Register dst, int64_t imm64) {
6584 InstructionMark im(this);
6585 int encode = prefixq_and_encode(dst->encoding());
6586 emit_int8((unsigned char)(0xB8 | encode));
6587 emit_int64(imm64);
6588 }
6589
6590 void Assembler::mov_literal64(Register dst, intptr_t imm64, RelocationHolder const& rspec) {
6591 InstructionMark im(this);
6592 int encode = prefixq_and_encode(dst->encoding());
6593 emit_int8(0xB8 | encode);
6594 emit_data64(imm64, rspec);
6595 }
6596
6597 void Assembler::mov_narrow_oop(Register dst, int32_t imm32, RelocationHolder const& rspec) {
6598 InstructionMark im(this);
6599 int encode = prefix_and_encode(dst->encoding());
6600 emit_int8((unsigned char)(0xB8 | encode));
6601 emit_data((int)imm32, rspec, narrow_oop_operand);
6602 }
6603
6604 void Assembler::mov_narrow_oop(Address dst, int32_t imm32, RelocationHolder const& rspec) {
6605 InstructionMark im(this);
6606 prefix(dst);
6607 emit_int8((unsigned char)0xC7);
6608 emit_operand(rax, dst, 4);
6609 emit_data((int)imm32, rspec, narrow_oop_operand);
6610 }
6611
6612 void Assembler::cmp_narrow_oop(Register src1, int32_t imm32, RelocationHolder const& rspec) {
6613 InstructionMark im(this);
6614 int encode = prefix_and_encode(src1->encoding());
6615 emit_int8((unsigned char)0x81);
6616 emit_int8((unsigned char)(0xF8 | encode));
6617 emit_data((int)imm32, rspec, narrow_oop_operand);
6618 }
6619
6620 void Assembler::cmp_narrow_oop(Address src1, int32_t imm32, RelocationHolder const& rspec) {
6621 InstructionMark im(this);
6622 prefix(src1);
6623 emit_int8((unsigned char)0x81);
6624 emit_operand(rax, src1, 4);
6625 emit_data((int)imm32, rspec, narrow_oop_operand);
6626 }
6627
6628 void Assembler::lzcntq(Register dst, Register src) {
6629 assert(VM_Version::supports_lzcnt(), "encoding is treated as BSR");
6630 emit_int8((unsigned char)0xF3);
6631 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
6632 emit_int8(0x0F);
6633 emit_int8((unsigned char)0xBD);
6634 emit_int8((unsigned char)(0xC0 | encode));
6635 }
6636
6637 void Assembler::movdq(XMMRegister dst, Register src) {
6638 // table D-1 says MMX/SSE2
6639 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6640 int encode = simd_prefix_and_encode_q(dst, src, VEX_SIMD_66, true);
6641 emit_int8(0x6E);
6642 emit_int8((unsigned char)(0xC0 | encode));
6643 }
6644
6645 void Assembler::movdq(Register dst, XMMRegister src) {
6646 // table D-1 says MMX/SSE2
6647 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6648 // swap src/dst to get correct prefix
6649 int encode = simd_prefix_and_encode_q(src, dst, VEX_SIMD_66, true);
6650 emit_int8(0x7E);
6651 emit_int8((unsigned char)(0xC0 | encode));
6652 }
6653
6654 void Assembler::movq(Register dst, Register src) {
6655 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
6656 emit_int8((unsigned char)0x8B);
6657 emit_int8((unsigned char)(0xC0 | encode));
6658 }
6659
6660 void Assembler::movq(Register dst, Address src) {
6661 InstructionMark im(this);
6662 prefixq(src, dst);
6663 emit_int8((unsigned char)0x8B);
6664 emit_operand(dst, src);
6665 }
6666
6667 void Assembler::movq(Address dst, Register src) {
6668 InstructionMark im(this);
6669 prefixq(dst, src);
6670 emit_int8((unsigned char)0x89);
6671 emit_operand(src, dst);
6672 }
6673
6674 void Assembler::movsbq(Register dst, Address src) {
6675 InstructionMark im(this);
6676 prefixq(src, dst);
6677 emit_int8(0x0F);
6678 emit_int8((unsigned char)0xBE);
6679 emit_operand(dst, src);
6680 }
6681
6682 void Assembler::movsbq(Register dst, Register src) {
6683 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
6684 emit_int8(0x0F);
6685 emit_int8((unsigned char)0xBE);
6686 emit_int8((unsigned char)(0xC0 | encode));
6687 }
6688
6689 void Assembler::movslq(Register dst, int32_t imm32) {
6690 // dbx shows movslq(rcx, 3) as movq $0x0000000049000000,(%rbx)
6691 // and movslq(r8, 3); as movl $0x0000000048000000,(%rbx)
6692 // as a result we shouldn't use until tested at runtime...
6693 ShouldNotReachHere();
6694 InstructionMark im(this);
6695 int encode = prefixq_and_encode(dst->encoding());
6696 emit_int8((unsigned char)(0xC7 | encode));
6697 emit_int32(imm32);
6698 }
6699
6700 void Assembler::movslq(Address dst, int32_t imm32) {
6701 assert(is_simm32(imm32), "lost bits");
6702 InstructionMark im(this);
6703 prefixq(dst);
6704 emit_int8((unsigned char)0xC7);
6705 emit_operand(rax, dst, 4);
6706 emit_int32(imm32);
6707 }
6708
6709 void Assembler::movslq(Register dst, Address src) {
6710 InstructionMark im(this);
6711 prefixq(src, dst);
6712 emit_int8(0x63);
6713 emit_operand(dst, src);
6714 }
6715
6716 void Assembler::movslq(Register dst, Register src) {
6717 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
6718 emit_int8(0x63);
6719 emit_int8((unsigned char)(0xC0 | encode));
6720 }
6721
6722 void Assembler::movswq(Register dst, Address src) {
6723 InstructionMark im(this);
6724 prefixq(src, dst);
6725 emit_int8(0x0F);
6726 emit_int8((unsigned char)0xBF);
6727 emit_operand(dst, src);
6728 }
6729
6730 void Assembler::movswq(Register dst, Register src) {
6731 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
6732 emit_int8((unsigned char)0x0F);
6733 emit_int8((unsigned char)0xBF);
6734 emit_int8((unsigned char)(0xC0 | encode));
6735 }
6736
6737 void Assembler::movzbq(Register dst, Address src) {
6738 InstructionMark im(this);
6739 prefixq(src, dst);
6740 emit_int8((unsigned char)0x0F);
6741 emit_int8((unsigned char)0xB6);
6742 emit_operand(dst, src);
6743 }
6744
6745 void Assembler::movzbq(Register dst, Register src) {
6746 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
6747 emit_int8(0x0F);
6748 emit_int8((unsigned char)0xB6);
6749 emit_int8(0xC0 | encode);
6750 }
6751
6752 void Assembler::movzwq(Register dst, Address src) {
6753 InstructionMark im(this);
6754 prefixq(src, dst);
6755 emit_int8((unsigned char)0x0F);
6756 emit_int8((unsigned char)0xB7);
6757 emit_operand(dst, src);
6758 }
6759
6760 void Assembler::movzwq(Register dst, Register src) {
6761 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
6762 emit_int8((unsigned char)0x0F);
6763 emit_int8((unsigned char)0xB7);
6764 emit_int8((unsigned char)(0xC0 | encode));
6765 }
6766
6767 void Assembler::mulq(Address src) {
6768 InstructionMark im(this);
6769 prefixq(src);
6770 emit_int8((unsigned char)0xF7);
6771 emit_operand(rsp, src);
6772 }
6773
6774 void Assembler::mulq(Register src) {
6775 int encode = prefixq_and_encode(src->encoding());
6776 emit_int8((unsigned char)0xF7);
6777 emit_int8((unsigned char)(0xE0 | encode));
6778 }
6779
6780 void Assembler::mulxq(Register dst1, Register dst2, Register src) {
6781 assert(VM_Version::supports_bmi2(), "bit manipulation instructions not supported");
6782 int encode = vex_prefix_and_encode(dst1->encoding(), dst2->encoding(), src->encoding(),
6783 VEX_SIMD_F2, VEX_OPCODE_0F_38, true, AVX_128bit, true, false);
6784 emit_int8((unsigned char)0xF6);
6785 emit_int8((unsigned char)(0xC0 | encode));
6786 }
6787
6788 void Assembler::negq(Register dst) {
6789 int encode = prefixq_and_encode(dst->encoding());
6790 emit_int8((unsigned char)0xF7);
6791 emit_int8((unsigned char)(0xD8 | encode));
6792 }
6793
6794 void Assembler::notq(Register dst) {
6795 int encode = prefixq_and_encode(dst->encoding());
6796 emit_int8((unsigned char)0xF7);
6797 emit_int8((unsigned char)(0xD0 | encode));
6798 }
6799
6800 void Assembler::orq(Address dst, int32_t imm32) {
6801 InstructionMark im(this);
6802 prefixq(dst);
6803 emit_int8((unsigned char)0x81);
6804 emit_operand(rcx, dst, 4);
6805 emit_int32(imm32);
6806 }
6807
6808 void Assembler::orq(Register dst, int32_t imm32) {
6809 (void) prefixq_and_encode(dst->encoding());
6810 emit_arith(0x81, 0xC8, dst, imm32);
6811 }
6812
6813 void Assembler::orq(Register dst, Address src) {
6814 InstructionMark im(this);
6815 prefixq(src, dst);
6816 emit_int8(0x0B);
6817 emit_operand(dst, src);
6818 }
6819
6820 void Assembler::orq(Register dst, Register src) {
6821 (void) prefixq_and_encode(dst->encoding(), src->encoding());
6822 emit_arith(0x0B, 0xC0, dst, src);
6823 }
6824
6825 void Assembler::popa() { // 64bit
6826 movq(r15, Address(rsp, 0));
6827 movq(r14, Address(rsp, wordSize));
6828 movq(r13, Address(rsp, 2 * wordSize));
6829 movq(r12, Address(rsp, 3 * wordSize));
6830 movq(r11, Address(rsp, 4 * wordSize));
6831 movq(r10, Address(rsp, 5 * wordSize));
6832 movq(r9, Address(rsp, 6 * wordSize));
6833 movq(r8, Address(rsp, 7 * wordSize));
6834 movq(rdi, Address(rsp, 8 * wordSize));
6835 movq(rsi, Address(rsp, 9 * wordSize));
6836 movq(rbp, Address(rsp, 10 * wordSize));
6837 // skip rsp
6838 movq(rbx, Address(rsp, 12 * wordSize));
6839 movq(rdx, Address(rsp, 13 * wordSize));
6840 movq(rcx, Address(rsp, 14 * wordSize));
6841 movq(rax, Address(rsp, 15 * wordSize));
6842
6843 addq(rsp, 16 * wordSize);
6844 }
6845
6846 void Assembler::popcntq(Register dst, Address src) {
6847 assert(VM_Version::supports_popcnt(), "must support");
6848 InstructionMark im(this);
6849 emit_int8((unsigned char)0xF3);
6850 prefixq(src, dst);
6851 emit_int8((unsigned char)0x0F);
6852 emit_int8((unsigned char)0xB8);
6853 emit_operand(dst, src);
6854 }
6855
6856 void Assembler::popcntq(Register dst, Register src) {
6857 assert(VM_Version::supports_popcnt(), "must support");
6858 emit_int8((unsigned char)0xF3);
6859 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
6860 emit_int8((unsigned char)0x0F);
6861 emit_int8((unsigned char)0xB8);
6862 emit_int8((unsigned char)(0xC0 | encode));
6863 }
6864
6865 void Assembler::popq(Address dst) {
6866 InstructionMark im(this);
6867 prefixq(dst);
6868 emit_int8((unsigned char)0x8F);
6869 emit_operand(rax, dst);
6870 }
6871
6872 void Assembler::pusha() { // 64bit
6873 // we have to store original rsp. ABI says that 128 bytes
6874 // below rsp are local scratch.
6875 movq(Address(rsp, -5 * wordSize), rsp);
6876
6877 subq(rsp, 16 * wordSize);
6878
6879 movq(Address(rsp, 15 * wordSize), rax);
6880 movq(Address(rsp, 14 * wordSize), rcx);
6881 movq(Address(rsp, 13 * wordSize), rdx);
6882 movq(Address(rsp, 12 * wordSize), rbx);
6883 // skip rsp
6884 movq(Address(rsp, 10 * wordSize), rbp);
6885 movq(Address(rsp, 9 * wordSize), rsi);
6886 movq(Address(rsp, 8 * wordSize), rdi);
6887 movq(Address(rsp, 7 * wordSize), r8);
6888 movq(Address(rsp, 6 * wordSize), r9);
6889 movq(Address(rsp, 5 * wordSize), r10);
6890 movq(Address(rsp, 4 * wordSize), r11);
6891 movq(Address(rsp, 3 * wordSize), r12);
6892 movq(Address(rsp, 2 * wordSize), r13);
6893 movq(Address(rsp, wordSize), r14);
6894 movq(Address(rsp, 0), r15);
6895 }
6896
6897 void Assembler::pushq(Address src) {
6898 InstructionMark im(this);
6899 prefixq(src);
6900 emit_int8((unsigned char)0xFF);
6901 emit_operand(rsi, src);
6902 }
6903
6904 void Assembler::rclq(Register dst, int imm8) {
6905 assert(isShiftCount(imm8 >> 1), "illegal shift count");
6906 int encode = prefixq_and_encode(dst->encoding());
6907 if (imm8 == 1) {
6908 emit_int8((unsigned char)0xD1);
6909 emit_int8((unsigned char)(0xD0 | encode));
6910 } else {
6911 emit_int8((unsigned char)0xC1);
6912 emit_int8((unsigned char)(0xD0 | encode));
6913 emit_int8(imm8);
6914 }
6915 }
6916
6917 void Assembler::rcrq(Register dst, int imm8) {
6918 assert(isShiftCount(imm8 >> 1), "illegal shift count");
6919 int encode = prefixq_and_encode(dst->encoding());
6920 if (imm8 == 1) {
6921 emit_int8((unsigned char)0xD1);
6922 emit_int8((unsigned char)(0xD8 | encode));
6923 } else {
6924 emit_int8((unsigned char)0xC1);
6925 emit_int8((unsigned char)(0xD8 | encode));
6926 emit_int8(imm8);
6927 }
6928 }
6929
6930 void Assembler::rorq(Register dst, int imm8) {
6931 assert(isShiftCount(imm8 >> 1), "illegal shift count");
6932 int encode = prefixq_and_encode(dst->encoding());
6933 if (imm8 == 1) {
6934 emit_int8((unsigned char)0xD1);
6935 emit_int8((unsigned char)(0xC8 | encode));
6936 } else {
6937 emit_int8((unsigned char)0xC1);
6938 emit_int8((unsigned char)(0xc8 | encode));
6939 emit_int8(imm8);
6940 }
6941 }
6942
6943 void Assembler::rorxq(Register dst, Register src, int imm8) {
6944 assert(VM_Version::supports_bmi2(), "bit manipulation instructions not supported");
6945 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F2,
6946 VEX_OPCODE_0F_3A, true, AVX_128bit, true, false);
6947 emit_int8((unsigned char)0xF0);
6948 emit_int8((unsigned char)(0xC0 | encode));
6949 emit_int8(imm8);
6950 }
6951
6952 void Assembler::sarq(Register dst, int imm8) {
6953 assert(isShiftCount(imm8 >> 1), "illegal shift count");
6954 int encode = prefixq_and_encode(dst->encoding());
6955 if (imm8 == 1) {
6956 emit_int8((unsigned char)0xD1);
6957 emit_int8((unsigned char)(0xF8 | encode));
6958 } else {
6959 emit_int8((unsigned char)0xC1);
6960 emit_int8((unsigned char)(0xF8 | encode));
6961 emit_int8(imm8);
6962 }
6963 }
6964
6965 void Assembler::sarq(Register dst) {
6966 int encode = prefixq_and_encode(dst->encoding());
6967 emit_int8((unsigned char)0xD3);
6968 emit_int8((unsigned char)(0xF8 | encode));
6969 }
6970
6971 void Assembler::sbbq(Address dst, int32_t imm32) {
6972 InstructionMark im(this);
6973 prefixq(dst);
6974 emit_arith_operand(0x81, rbx, dst, imm32);
6975 }
6976
6977 void Assembler::sbbq(Register dst, int32_t imm32) {
6978 (void) prefixq_and_encode(dst->encoding());
6979 emit_arith(0x81, 0xD8, dst, imm32);
6980 }
6981
6982 void Assembler::sbbq(Register dst, Address src) {
6983 InstructionMark im(this);
6984 prefixq(src, dst);
6985 emit_int8(0x1B);
6986 emit_operand(dst, src);
6987 }
6988
6989 void Assembler::sbbq(Register dst, Register src) {
6990 (void) prefixq_and_encode(dst->encoding(), src->encoding());
6991 emit_arith(0x1B, 0xC0, dst, src);
6992 }
6993
6994 void Assembler::shlq(Register dst, int imm8) {
6995 assert(isShiftCount(imm8 >> 1), "illegal shift count");
6996 int encode = prefixq_and_encode(dst->encoding());
6997 if (imm8 == 1) {
6998 emit_int8((unsigned char)0xD1);
6999 emit_int8((unsigned char)(0xE0 | encode));
7000 } else {
7001 emit_int8((unsigned char)0xC1);
7002 emit_int8((unsigned char)(0xE0 | encode));
7003 emit_int8(imm8);
7004 }
7005 }
7006
7007 void Assembler::shlq(Register dst) {
7008 int encode = prefixq_and_encode(dst->encoding());
7009 emit_int8((unsigned char)0xD3);
7010 emit_int8((unsigned char)(0xE0 | encode));
7011 }
7012
7013 void Assembler::shrq(Register dst, int imm8) {
7014 assert(isShiftCount(imm8 >> 1), "illegal shift count");
7015 int encode = prefixq_and_encode(dst->encoding());
7016 emit_int8((unsigned char)0xC1);
7017 emit_int8((unsigned char)(0xE8 | encode));
7018 emit_int8(imm8);
7019 }
7020
7021 void Assembler::shrq(Register dst) {
7022 int encode = prefixq_and_encode(dst->encoding());
7023 emit_int8((unsigned char)0xD3);
7024 emit_int8(0xE8 | encode);
7025 }
7026
7027 void Assembler::subq(Address dst, int32_t imm32) {
7028 InstructionMark im(this);
7029 prefixq(dst);
7030 emit_arith_operand(0x81, rbp, dst, imm32);
7031 }
7032
7033 void Assembler::subq(Address dst, Register src) {
7034 InstructionMark im(this);
7035 prefixq(dst, src);
7036 emit_int8(0x29);
7037 emit_operand(src, dst);
7038 }
7039
7040 void Assembler::subq(Register dst, int32_t imm32) {
7041 (void) prefixq_and_encode(dst->encoding());
7042 emit_arith(0x81, 0xE8, dst, imm32);
7043 }
7044
7045 // Force generation of a 4 byte immediate value even if it fits into 8bit
7046 void Assembler::subq_imm32(Register dst, int32_t imm32) {
7047 (void) prefixq_and_encode(dst->encoding());
7048 emit_arith_imm32(0x81, 0xE8, dst, imm32);
7049 }
7050
7051 void Assembler::subq(Register dst, Address src) {
7052 InstructionMark im(this);
7053 prefixq(src, dst);
7054 emit_int8(0x2B);
7055 emit_operand(dst, src);
7056 }
7057
7058 void Assembler::subq(Register dst, Register src) {
7059 (void) prefixq_and_encode(dst->encoding(), src->encoding());
7060 emit_arith(0x2B, 0xC0, dst, src);
7061 }
7062
7063 void Assembler::testq(Register dst, int32_t imm32) {
7064 // not using emit_arith because test
7065 // doesn't support sign-extension of
7066 // 8bit operands
7067 int encode = dst->encoding();
7068 if (encode == 0) {
7069 prefix(REX_W);
7070 emit_int8((unsigned char)0xA9);
7071 } else {
7072 encode = prefixq_and_encode(encode);
7073 emit_int8((unsigned char)0xF7);
7074 emit_int8((unsigned char)(0xC0 | encode));
7075 }
7076 emit_int32(imm32);
7077 }
7078
7079 void Assembler::testq(Register dst, Register src) {
7080 (void) prefixq_and_encode(dst->encoding(), src->encoding());
7081 emit_arith(0x85, 0xC0, dst, src);
7082 }
7083
7084 void Assembler::xaddq(Address dst, Register src) {
7085 InstructionMark im(this);
7086 prefixq(dst, src);
7087 emit_int8(0x0F);
7088 emit_int8((unsigned char)0xC1);
7089 emit_operand(src, dst);
7090 }
7091
7092 void Assembler::xchgq(Register dst, Address src) {
7093 InstructionMark im(this);
7094 prefixq(src, dst);
7095 emit_int8((unsigned char)0x87);
7096 emit_operand(dst, src);
7097 }
7098
7099 void Assembler::xchgq(Register dst, Register src) {
7100 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
7101 emit_int8((unsigned char)0x87);
7102 emit_int8((unsigned char)(0xc0 | encode));
7103 }
7104
7105 void Assembler::xorq(Register dst, Register src) {
7106 (void) prefixq_and_encode(dst->encoding(), src->encoding());
7107 emit_arith(0x33, 0xC0, dst, src);
7108 }
7109
7110 void Assembler::xorq(Register dst, Address src) {
7111 InstructionMark im(this);
7112 prefixq(src, dst);
7113 emit_int8(0x33);
7114 emit_operand(dst, src);
7115 }
7116
7117 #endif // !LP64