src/cpu/sparc/vm/assembler_sparc.hpp

*** 1,7 ****
  /*
!  * Copyright (c) 1997, 2014, Oracle and/or its affiliates. All rights reserved.
   * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
   *
   * This code is free software; you can redistribute it and/or modify it
   * under the terms of the GNU General Public License version 2 only, as
   * published by the Free Software Foundation.
--- 1,7 ----
  /*
!  * Copyright (c) 1997, 2015, Oracle and/or its affiliates. All rights reserved.
   * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
   *
   * This code is free software; you can redistribute it and/or modify it
   * under the terms of the GNU General Public License version 2 only, as
   * published by the Free Software Foundation.
*** 127,136 ****
--- 127,137 ----
      alignaddr_op3  = 0x36,
      faligndata_op3 = 0x36,
      flog3_op3    = 0x36,
      edge_op3     = 0x36,
      fsrc_op3     = 0x36,
+     xmulx_op3    = 0x36,
      impdep2_op3  = 0x37,
      stpartialf_op3 = 0x37,
      jmpl_op3     = 0x38,
      rett_op3     = 0x39,
      trap_op3     = 0x3a,
*** 218,227 ****
--- 219,230 ----
      fdtoi_opf          = 0xd2,
  
      mdtox_opf          = 0x110,
      mstouw_opf         = 0x111,
      mstosw_opf         = 0x113,
+     xmulx_opf          = 0x115,
+     xmulxhi_opf        = 0x116,
      mxtod_opf          = 0x118,
      mwtos_opf          = 0x119,
  
      aes_kexpand0_opf   = 0x130,
      aes_kexpand2_opf   = 0x131,
*** 1210,1219 ****
--- 1213,1225 ----
    void movdtox(  FloatRegister s, Register d ) { vis3_only();  emit_int32( op(arith_op) | rd(d) | op3(mftoi_op3) | opf(mdtox_opf) | fs2(s, FloatRegisterImpl::D)); }
  
    void movwtos( Register s, FloatRegister d ) { vis3_only();  emit_int32( op(arith_op) | fd(d, FloatRegisterImpl::S) | op3(mftoi_op3) | opf(mwtos_opf) | rs2(s)); }
    void movxtod( Register s, FloatRegister d ) { vis3_only();  emit_int32( op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(mftoi_op3) | opf(mxtod_opf) | rs2(s)); }
  
+   void xmulx(Register s1, Register s2, Register d) { vis3_only(); emit_int32( op(arith_op) | rd(d) | op3(xmulx_op3) | rs1(s1) | opf(xmulx_opf) | rs2(s2)); }
+   void xmulxhi(Register s1, Register s2, Register d) { vis3_only(); emit_int32( op(arith_op) | rd(d) | op3(xmulx_op3) | rs1(s1) | opf(xmulxhi_opf) | rs2(s2)); }
+ 
    // Crypto SHA instructions
  
    void sha1()   { sha1_only();    emit_int32( op(arith_op) | op3(sha_op3) | opf(sha1_opf)); }
    void sha256() { sha256_only();  emit_int32( op(arith_op) | op3(sha_op3) | opf(sha256_opf)); }
    void sha512() { sha512_only();  emit_int32( op(arith_op) | op3(sha_op3) | opf(sha512_opf)); }