1 /*
2 * Copyright (c) 1997, 2014, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
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23 */
24
25 #ifndef CPU_SPARC_VM_ASSEMBLER_SPARC_HPP
26 #define CPU_SPARC_VM_ASSEMBLER_SPARC_HPP
27
28 #include "asm/register.hpp"
29
30 // The SPARC Assembler: Pure assembler doing NO optimizations on the instruction
31 // level; i.e., what you write
32 // is what you get. The Assembler is generating code into a CodeBuffer.
33
34 class Assembler : public AbstractAssembler {
35 friend class AbstractAssembler;
36 friend class AddressLiteral;
37
38 // code patchers need various routines like inv_wdisp()
39 friend class NativeInstruction;
40 friend class NativeGeneralJump;
41 friend class Relocation;
42 friend class Label;
43
44 public:
45 // op carries format info; see page 62 & 267
46
47 enum ops {
48 call_op = 1, // fmt 1
49 branch_op = 0, // also sethi (fmt2)
50 arith_op = 2, // fmt 3, arith & misc
51 ldst_op = 3 // fmt 3, load/store
52 };
53
54 enum op2s {
55 bpr_op2 = 3,
56 fb_op2 = 6,
57 fbp_op2 = 5,
58 br_op2 = 2,
59 bp_op2 = 1,
60 sethi_op2 = 4
61 };
62
63 enum op3s {
64 // selected op3s
65 add_op3 = 0x00,
66 and_op3 = 0x01,
67 or_op3 = 0x02,
68 xor_op3 = 0x03,
69 sub_op3 = 0x04,
70 andn_op3 = 0x05,
71 orn_op3 = 0x06,
72 xnor_op3 = 0x07,
73 addc_op3 = 0x08,
74 mulx_op3 = 0x09,
75 umul_op3 = 0x0a,
76 smul_op3 = 0x0b,
77 subc_op3 = 0x0c,
78 udivx_op3 = 0x0d,
79 udiv_op3 = 0x0e,
80 sdiv_op3 = 0x0f,
81
82 addcc_op3 = 0x10,
83 andcc_op3 = 0x11,
84 orcc_op3 = 0x12,
85 xorcc_op3 = 0x13,
86 subcc_op3 = 0x14,
87 andncc_op3 = 0x15,
88 orncc_op3 = 0x16,
89 xnorcc_op3 = 0x17,
90 addccc_op3 = 0x18,
91 aes4_op3 = 0x19,
92 umulcc_op3 = 0x1a,
93 smulcc_op3 = 0x1b,
94 subccc_op3 = 0x1c,
95 udivcc_op3 = 0x1e,
96 sdivcc_op3 = 0x1f,
97
98 taddcc_op3 = 0x20,
99 tsubcc_op3 = 0x21,
100 taddcctv_op3 = 0x22,
101 tsubcctv_op3 = 0x23,
102 mulscc_op3 = 0x24,
103 sll_op3 = 0x25,
104 sllx_op3 = 0x25,
105 srl_op3 = 0x26,
106 srlx_op3 = 0x26,
107 sra_op3 = 0x27,
108 srax_op3 = 0x27,
109 rdreg_op3 = 0x28,
110 membar_op3 = 0x28,
111
112 flushw_op3 = 0x2b,
113 movcc_op3 = 0x2c,
114 sdivx_op3 = 0x2d,
115 popc_op3 = 0x2e,
116 movr_op3 = 0x2f,
117
118 sir_op3 = 0x30,
119 wrreg_op3 = 0x30,
120 saved_op3 = 0x31,
121
122 fpop1_op3 = 0x34,
123 fpop2_op3 = 0x35,
124 impdep1_op3 = 0x36,
125 aes3_op3 = 0x36,
126 sha_op3 = 0x36,
127 alignaddr_op3 = 0x36,
128 faligndata_op3 = 0x36,
129 flog3_op3 = 0x36,
130 edge_op3 = 0x36,
131 fsrc_op3 = 0x36,
132 impdep2_op3 = 0x37,
133 stpartialf_op3 = 0x37,
134 jmpl_op3 = 0x38,
135 rett_op3 = 0x39,
136 trap_op3 = 0x3a,
137 flush_op3 = 0x3b,
138 save_op3 = 0x3c,
139 restore_op3 = 0x3d,
140 done_op3 = 0x3e,
141 retry_op3 = 0x3e,
142
143 lduw_op3 = 0x00,
144 ldub_op3 = 0x01,
145 lduh_op3 = 0x02,
146 ldd_op3 = 0x03,
147 stw_op3 = 0x04,
148 stb_op3 = 0x05,
149 sth_op3 = 0x06,
150 std_op3 = 0x07,
151 ldsw_op3 = 0x08,
152 ldsb_op3 = 0x09,
153 ldsh_op3 = 0x0a,
154 ldx_op3 = 0x0b,
155
156 stx_op3 = 0x0e,
157 swap_op3 = 0x0f,
158
159 stwa_op3 = 0x14,
160 stxa_op3 = 0x1e,
161
162 ldf_op3 = 0x20,
163 ldfsr_op3 = 0x21,
164 ldqf_op3 = 0x22,
165 lddf_op3 = 0x23,
166 stf_op3 = 0x24,
167 stfsr_op3 = 0x25,
168 stqf_op3 = 0x26,
169 stdf_op3 = 0x27,
170
171 prefetch_op3 = 0x2d,
172
173 casa_op3 = 0x3c,
174 casxa_op3 = 0x3e,
175
176 mftoi_op3 = 0x36,
177
178 alt_bit_op3 = 0x10,
179 cc_bit_op3 = 0x10
180 };
181
182 enum opfs {
183 // selected opfs
184 edge8n_opf = 0x01,
185
186 fmovs_opf = 0x01,
187 fmovd_opf = 0x02,
188
189 fnegs_opf = 0x05,
190 fnegd_opf = 0x06,
191
192 alignaddr_opf = 0x18,
193
194 fadds_opf = 0x41,
195 faddd_opf = 0x42,
196 fsubs_opf = 0x45,
197 fsubd_opf = 0x46,
198
199 faligndata_opf = 0x48,
200
201 fmuls_opf = 0x49,
202 fmuld_opf = 0x4a,
203 fdivs_opf = 0x4d,
204 fdivd_opf = 0x4e,
205
206 fcmps_opf = 0x51,
207 fcmpd_opf = 0x52,
208
209 fstox_opf = 0x81,
210 fdtox_opf = 0x82,
211 fxtos_opf = 0x84,
212 fxtod_opf = 0x88,
213 fitos_opf = 0xc4,
214 fdtos_opf = 0xc6,
215 fitod_opf = 0xc8,
216 fstod_opf = 0xc9,
217 fstoi_opf = 0xd1,
218 fdtoi_opf = 0xd2,
219
220 mdtox_opf = 0x110,
221 mstouw_opf = 0x111,
222 mstosw_opf = 0x113,
223 mxtod_opf = 0x118,
224 mwtos_opf = 0x119,
225
226 aes_kexpand0_opf = 0x130,
227 aes_kexpand2_opf = 0x131,
228
229 sha1_opf = 0x141,
230 sha256_opf = 0x142,
231 sha512_opf = 0x143
232 };
233
234 enum op5s {
235 aes_eround01_op5 = 0x00,
236 aes_eround23_op5 = 0x01,
237 aes_dround01_op5 = 0x02,
238 aes_dround23_op5 = 0x03,
239 aes_eround01_l_op5 = 0x04,
240 aes_eround23_l_op5 = 0x05,
241 aes_dround01_l_op5 = 0x06,
242 aes_dround23_l_op5 = 0x07,
243 aes_kexpand1_op5 = 0x08
244 };
245
246 enum RCondition { rc_z = 1, rc_lez = 2, rc_lz = 3, rc_nz = 5, rc_gz = 6, rc_gez = 7, rc_last = rc_gez };
247
248 enum Condition {
249 // for FBfcc & FBPfcc instruction
250 f_never = 0,
251 f_notEqual = 1,
252 f_notZero = 1,
253 f_lessOrGreater = 2,
254 f_unorderedOrLess = 3,
255 f_less = 4,
256 f_unorderedOrGreater = 5,
257 f_greater = 6,
258 f_unordered = 7,
259 f_always = 8,
260 f_equal = 9,
261 f_zero = 9,
262 f_unorderedOrEqual = 10,
263 f_greaterOrEqual = 11,
264 f_unorderedOrGreaterOrEqual = 12,
265 f_lessOrEqual = 13,
266 f_unorderedOrLessOrEqual = 14,
267 f_ordered = 15,
268
269 // V8 coproc, pp 123 v8 manual
270
271 cp_always = 8,
272 cp_never = 0,
273 cp_3 = 7,
274 cp_2 = 6,
275 cp_2or3 = 5,
276 cp_1 = 4,
277 cp_1or3 = 3,
278 cp_1or2 = 2,
279 cp_1or2or3 = 1,
280 cp_0 = 9,
281 cp_0or3 = 10,
282 cp_0or2 = 11,
283 cp_0or2or3 = 12,
284 cp_0or1 = 13,
285 cp_0or1or3 = 14,
286 cp_0or1or2 = 15,
287
288
289 // for integers
290
291 never = 0,
292 equal = 1,
293 zero = 1,
294 lessEqual = 2,
295 less = 3,
296 lessEqualUnsigned = 4,
297 lessUnsigned = 5,
298 carrySet = 5,
299 negative = 6,
300 overflowSet = 7,
301 always = 8,
302 notEqual = 9,
303 notZero = 9,
304 greater = 10,
305 greaterEqual = 11,
306 greaterUnsigned = 12,
307 greaterEqualUnsigned = 13,
308 carryClear = 13,
309 positive = 14,
310 overflowClear = 15
311 };
312
313 enum CC {
314 icc = 0, xcc = 2,
315 // ptr_cc is the correct condition code for a pointer or intptr_t:
316 ptr_cc = NOT_LP64(icc) LP64_ONLY(xcc),
317 fcc0 = 0, fcc1 = 1, fcc2 = 2, fcc3 = 3
318 };
319
320 enum PrefetchFcn {
321 severalReads = 0, oneRead = 1, severalWritesAndPossiblyReads = 2, oneWrite = 3, page = 4
322 };
323
324 public:
325 // Helper functions for groups of instructions
326
327 enum Predict { pt = 1, pn = 0 }; // pt = predict taken
328
329 enum Membar_mask_bits { // page 184, v9
330 StoreStore = 1 << 3,
331 LoadStore = 1 << 2,
332 StoreLoad = 1 << 1,
333 LoadLoad = 1 << 0,
334
335 Sync = 1 << 6,
336 MemIssue = 1 << 5,
337 Lookaside = 1 << 4
338 };
339
340 static bool is_in_wdisp_range(address a, address b, int nbits) {
341 intptr_t d = intptr_t(b) - intptr_t(a);
342 return is_simm(d, nbits + 2);
343 }
344
345 address target_distance(Label& L) {
346 // Assembler::target(L) should be called only when
347 // a branch instruction is emitted since non-bound
348 // labels record current pc() as a branch address.
349 if (L.is_bound()) return target(L);
350 // Return current address for non-bound labels.
351 return pc();
352 }
353
354 // test if label is in simm16 range in words (wdisp16).
355 bool is_in_wdisp16_range(Label& L) {
356 return is_in_wdisp_range(target_distance(L), pc(), 16);
357 }
358 // test if the distance between two addresses fits in simm30 range in words
359 static bool is_in_wdisp30_range(address a, address b) {
360 return is_in_wdisp_range(a, b, 30);
361 }
362
363 enum ASIs { // page 72, v9
364 ASI_PRIMARY = 0x80,
365 ASI_PRIMARY_NOFAULT = 0x82,
366 ASI_PRIMARY_LITTLE = 0x88,
367 // 8x8-bit partial store
368 ASI_PST8_PRIMARY = 0xC0,
369 // Block initializing store
370 ASI_ST_BLKINIT_PRIMARY = 0xE2,
371 // Most-Recently-Used (MRU) BIS variant
372 ASI_ST_BLKINIT_MRU_PRIMARY = 0xF2
373 // add more from book as needed
374 };
375
376 protected:
377 // helpers
378
379 // x is supposed to fit in a field "nbits" wide
380 // and be sign-extended. Check the range.
381
382 static void assert_signed_range(intptr_t x, int nbits) {
383 assert(nbits == 32 || (-(1 << nbits-1) <= x && x < ( 1 << nbits-1)),
384 err_msg("value out of range: x=" INTPTR_FORMAT ", nbits=%d", x, nbits));
385 }
386
387 static void assert_signed_word_disp_range(intptr_t x, int nbits) {
388 assert( (x & 3) == 0, "not word aligned");
389 assert_signed_range(x, nbits + 2);
390 }
391
392 static void assert_unsigned_const(int x, int nbits) {
393 assert( juint(x) < juint(1 << nbits), "unsigned constant out of range");
394 }
395
396 // fields: note bits numbered from LSB = 0,
397 // fields known by inclusive bit range
398
399 static int fmask(juint hi_bit, juint lo_bit) {
400 assert( hi_bit >= lo_bit && 0 <= lo_bit && hi_bit < 32, "bad bits");
401 return (1 << ( hi_bit-lo_bit + 1 )) - 1;
402 }
403
404 // inverse of u_field
405
406 static int inv_u_field(int x, int hi_bit, int lo_bit) {
407 juint r = juint(x) >> lo_bit;
408 r &= fmask( hi_bit, lo_bit);
409 return int(r);
410 }
411
412
413 // signed version: extract from field and sign-extend
414
415 static int inv_s_field(int x, int hi_bit, int lo_bit) {
416 int sign_shift = 31 - hi_bit;
417 return inv_u_field( ((x << sign_shift) >> sign_shift), hi_bit, lo_bit);
418 }
419
420 // given a field that ranges from hi_bit to lo_bit (inclusive,
421 // LSB = 0), and an unsigned value for the field,
422 // shift it into the field
423
424 #ifdef ASSERT
425 static int u_field(int x, int hi_bit, int lo_bit) {
426 assert( ( x & ~fmask(hi_bit, lo_bit)) == 0,
427 "value out of range");
428 int r = x << lo_bit;
429 assert( inv_u_field(r, hi_bit, lo_bit) == x, "just checking");
430 return r;
431 }
432 #else
433 // make sure this is inlined as it will reduce code size significantly
434 #define u_field(x, hi_bit, lo_bit) ((x) << (lo_bit))
435 #endif
436
437 static int inv_op( int x ) { return inv_u_field(x, 31, 30); }
438 static int inv_op2( int x ) { return inv_u_field(x, 24, 22); }
439 static int inv_op3( int x ) { return inv_u_field(x, 24, 19); }
440 static int inv_cond( int x ){ return inv_u_field(x, 28, 25); }
441
442 static bool inv_immed( int x ) { return (x & Assembler::immed(true)) != 0; }
443
444 static Register inv_rd( int x ) { return as_Register(inv_u_field(x, 29, 25)); }
445 static Register inv_rs1( int x ) { return as_Register(inv_u_field(x, 18, 14)); }
446 static Register inv_rs2( int x ) { return as_Register(inv_u_field(x, 4, 0)); }
447
448 static int op( int x) { return u_field(x, 31, 30); }
449 static int rd( Register r) { return u_field(r->encoding(), 29, 25); }
450 static int fcn( int x) { return u_field(x, 29, 25); }
451 static int op3( int x) { return u_field(x, 24, 19); }
452 static int rs1( Register r) { return u_field(r->encoding(), 18, 14); }
453 static int rs2( Register r) { return u_field(r->encoding(), 4, 0); }
454 static int annul( bool a) { return u_field(a ? 1 : 0, 29, 29); }
455 static int cond( int x) { return u_field(x, 28, 25); }
456 static int cond_mov( int x) { return u_field(x, 17, 14); }
457 static int rcond( RCondition x) { return u_field(x, 12, 10); }
458 static int op2( int x) { return u_field(x, 24, 22); }
459 static int predict( bool p) { return u_field(p ? 1 : 0, 19, 19); }
460 static int branchcc( CC fcca) { return u_field(fcca, 21, 20); }
461 static int cmpcc( CC fcca) { return u_field(fcca, 26, 25); }
462 static int imm_asi( int x) { return u_field(x, 12, 5); }
463 static int immed( bool i) { return u_field(i ? 1 : 0, 13, 13); }
464 static int opf_low6( int w) { return u_field(w, 10, 5); }
465 static int opf_low5( int w) { return u_field(w, 9, 5); }
466 static int op5( int x) { return u_field(x, 8, 5); }
467 static int trapcc( CC cc) { return u_field(cc, 12, 11); }
468 static int sx( int i) { return u_field(i, 12, 12); } // shift x=1 means 64-bit
469 static int opf( int x) { return u_field(x, 13, 5); }
470
471 static bool is_cbcond( int x ) {
472 return (VM_Version::has_cbcond() && (inv_cond(x) > rc_last) &&
473 inv_op(x) == branch_op && inv_op2(x) == bpr_op2);
474 }
475 static bool is_cxb( int x ) {
476 assert(is_cbcond(x), "wrong instruction");
477 return (x & (1<<21)) != 0;
478 }
479 static int cond_cbcond( int x) { return u_field((((x & 8)<<1) + 8 + (x & 7)), 29, 25); }
480 static int inv_cond_cbcond(int x) {
481 assert(is_cbcond(x), "wrong instruction");
482 return inv_u_field(x, 27, 25) | (inv_u_field(x, 29, 29)<<3);
483 }
484
485 static int opf_cc( CC c, bool useFloat ) { return u_field((useFloat ? 0 : 4) + c, 13, 11); }
486 static int mov_cc( CC c, bool useFloat ) { return u_field(useFloat ? 0 : 1, 18, 18) | u_field(c, 12, 11); }
487
488 static int fd( FloatRegister r, FloatRegisterImpl::Width fwa) { return u_field(r->encoding(fwa), 29, 25); };
489 static int fs1(FloatRegister r, FloatRegisterImpl::Width fwa) { return u_field(r->encoding(fwa), 18, 14); };
490 static int fs2(FloatRegister r, FloatRegisterImpl::Width fwa) { return u_field(r->encoding(fwa), 4, 0); };
491 static int fs3(FloatRegister r, FloatRegisterImpl::Width fwa) { return u_field(r->encoding(fwa), 13, 9); };
492
493 // some float instructions use this encoding on the op3 field
494 static int alt_op3(int op, FloatRegisterImpl::Width w) {
495 int r;
496 switch(w) {
497 case FloatRegisterImpl::S: r = op + 0; break;
498 case FloatRegisterImpl::D: r = op + 3; break;
499 case FloatRegisterImpl::Q: r = op + 2; break;
500 default: ShouldNotReachHere(); break;
501 }
502 return op3(r);
503 }
504
505
506 // compute inverse of simm
507 static int inv_simm(int x, int nbits) {
508 return (int)(x << (32 - nbits)) >> (32 - nbits);
509 }
510
511 static int inv_simm13( int x ) { return inv_simm(x, 13); }
512
513 // signed immediate, in low bits, nbits long
514 static int simm(int x, int nbits) {
515 assert_signed_range(x, nbits);
516 return x & (( 1 << nbits ) - 1);
517 }
518
519 // compute inverse of wdisp16
520 static intptr_t inv_wdisp16(int x, intptr_t pos) {
521 int lo = x & (( 1 << 14 ) - 1);
522 int hi = (x >> 20) & 3;
523 if (hi >= 2) hi |= ~1;
524 return (((hi << 14) | lo) << 2) + pos;
525 }
526
527 // word offset, 14 bits at LSend, 2 bits at B21, B20
528 static int wdisp16(intptr_t x, intptr_t off) {
529 intptr_t xx = x - off;
530 assert_signed_word_disp_range(xx, 16);
531 int r = (xx >> 2) & ((1 << 14) - 1)
532 | ( ( (xx>>(2+14)) & 3 ) << 20 );
533 assert( inv_wdisp16(r, off) == x, "inverse is not inverse");
534 return r;
535 }
536
537 // compute inverse of wdisp10
538 static intptr_t inv_wdisp10(int x, intptr_t pos) {
539 assert(is_cbcond(x), "wrong instruction");
540 int lo = inv_u_field(x, 12, 5);
541 int hi = (x >> 19) & 3;
542 if (hi >= 2) hi |= ~1;
543 return (((hi << 8) | lo) << 2) + pos;
544 }
545
546 // word offset for cbcond, 8 bits at [B12,B5], 2 bits at [B20,B19]
547 static int wdisp10(intptr_t x, intptr_t off) {
548 assert(VM_Version::has_cbcond(), "This CPU does not have CBCOND instruction");
549 intptr_t xx = x - off;
550 assert_signed_word_disp_range(xx, 10);
551 int r = ( ( (xx >> 2 ) & ((1 << 8) - 1) ) << 5 )
552 | ( ( (xx >> (2+8)) & 3 ) << 19 );
553 // Have to fake cbcond instruction to pass assert in inv_wdisp10()
554 assert(inv_wdisp10((r | op(branch_op) | cond_cbcond(rc_last+1) | op2(bpr_op2)), off) == x, "inverse is not inverse");
555 return r;
556 }
557
558 // word displacement in low-order nbits bits
559
560 static intptr_t inv_wdisp( int x, intptr_t pos, int nbits ) {
561 int pre_sign_extend = x & (( 1 << nbits ) - 1);
562 int r = pre_sign_extend >= ( 1 << (nbits-1) )
563 ? pre_sign_extend | ~(( 1 << nbits ) - 1)
564 : pre_sign_extend;
565 return (r << 2) + pos;
566 }
567
568 static int wdisp( intptr_t x, intptr_t off, int nbits ) {
569 intptr_t xx = x - off;
570 assert_signed_word_disp_range(xx, nbits);
571 int r = (xx >> 2) & (( 1 << nbits ) - 1);
572 assert( inv_wdisp( r, off, nbits ) == x, "inverse not inverse");
573 return r;
574 }
575
576
577 // Extract the top 32 bits in a 64 bit word
578 static int32_t hi32( int64_t x ) {
579 int32_t r = int32_t( (uint64_t)x >> 32 );
580 return r;
581 }
582
583 // given a sethi instruction, extract the constant, left-justified
584 static int inv_hi22( int x ) {
585 return x << 10;
586 }
587
588 // create an imm22 field, given a 32-bit left-justified constant
589 static int hi22( int x ) {
590 int r = int( juint(x) >> 10 );
591 assert( (r & ~((1 << 22) - 1)) == 0, "just checkin'");
592 return r;
593 }
594
595 // create a low10 __value__ (not a field) for a given a 32-bit constant
596 static int low10( int x ) {
597 return x & ((1 << 10) - 1);
598 }
599
600 // AES crypto instructions supported only on certain processors
601 static void aes_only() { assert( VM_Version::has_aes(), "This instruction only works on SPARC with AES instructions support"); }
602
603 // SHA crypto instructions supported only on certain processors
604 static void sha1_only() { assert( VM_Version::has_sha1(), "This instruction only works on SPARC with SHA1"); }
605 static void sha256_only() { assert( VM_Version::has_sha256(), "This instruction only works on SPARC with SHA256"); }
606 static void sha512_only() { assert( VM_Version::has_sha512(), "This instruction only works on SPARC with SHA512"); }
607
608 // instruction only in VIS1
609 static void vis1_only() { assert( VM_Version::has_vis1(), "This instruction only works on SPARC with VIS1"); }
610
611 // instruction only in VIS2
612 static void vis2_only() { assert( VM_Version::has_vis2(), "This instruction only works on SPARC with VIS2"); }
613
614 // instruction only in VIS3
615 static void vis3_only() { assert( VM_Version::has_vis3(), "This instruction only works on SPARC with VIS3"); }
616
617 // instruction only in v9
618 static void v9_only() { } // do nothing
619
620 // instruction deprecated in v9
621 static void v9_dep() { } // do nothing for now
622
623 // v8 has no CC field
624 static void v8_no_cc(CC cc) { if (cc) v9_only(); }
625
626 protected:
627 // Simple delay-slot scheme:
628 // In order to check the programmer, the assembler keeps track of deley slots.
629 // It forbids CTIs in delay slots (conservative, but should be OK).
630 // Also, when putting an instruction into a delay slot, you must say
631 // asm->delayed()->add(...), in order to check that you don't omit
632 // delay-slot instructions.
633 // To implement this, we use a simple FSA
634
635 #ifdef ASSERT
636 #define CHECK_DELAY
637 #endif
638 #ifdef CHECK_DELAY
639 enum Delay_state { no_delay, at_delay_slot, filling_delay_slot } delay_state;
640 #endif
641
642 public:
643 // Tells assembler next instruction must NOT be in delay slot.
644 // Use at start of multinstruction macros.
645 void assert_not_delayed() {
646 // This is a separate overloading to avoid creation of string constants
647 // in non-asserted code--with some compilers this pollutes the object code.
648 #ifdef CHECK_DELAY
649 assert_not_delayed("next instruction should not be a delay slot");
650 #endif
651 }
652 void assert_not_delayed(const char* msg) {
653 #ifdef CHECK_DELAY
654 assert(delay_state == no_delay, msg);
655 #endif
656 }
657
658 protected:
659 // Insert a nop if the previous is cbcond
660 void insert_nop_after_cbcond() {
661 if (UseCBCond && cbcond_before()) {
662 nop();
663 }
664 }
665 // Delay slot helpers
666 // cti is called when emitting control-transfer instruction,
667 // BEFORE doing the emitting.
668 // Only effective when assertion-checking is enabled.
669 void cti() {
670 // A cbcond instruction immediately followed by a CTI
671 // instruction introduces pipeline stalls, we need to avoid that.
672 no_cbcond_before();
673 #ifdef CHECK_DELAY
674 assert_not_delayed("cti should not be in delay slot");
675 #endif
676 }
677
678 // called when emitting cti with a delay slot, AFTER emitting
679 void has_delay_slot() {
680 #ifdef CHECK_DELAY
681 assert_not_delayed("just checking");
682 delay_state = at_delay_slot;
683 #endif
684 }
685
686 // cbcond instruction should not be generated one after an other
687 bool cbcond_before() {
688 if (offset() == 0) return false; // it is first instruction
689 int x = *(int*)(intptr_t(pc()) - 4); // previous instruction
690 return is_cbcond(x);
691 }
692
693 void no_cbcond_before() {
694 assert(offset() == 0 || !cbcond_before(), "cbcond should not follow an other cbcond");
695 }
696 public:
697
698 bool use_cbcond(Label& L) {
699 if (!UseCBCond || cbcond_before()) return false;
700 intptr_t x = intptr_t(target_distance(L)) - intptr_t(pc());
701 assert( (x & 3) == 0, "not word aligned");
702 return is_simm12(x);
703 }
704
705 // Tells assembler you know that next instruction is delayed
706 Assembler* delayed() {
707 #ifdef CHECK_DELAY
708 assert ( delay_state == at_delay_slot, "delayed instruction is not in delay slot");
709 delay_state = filling_delay_slot;
710 #endif
711 return this;
712 }
713
714 void flush() {
715 #ifdef CHECK_DELAY
716 assert ( delay_state == no_delay, "ending code with a delay slot");
717 #endif
718 AbstractAssembler::flush();
719 }
720
721 inline void emit_int32(int); // shadows AbstractAssembler::emit_int32
722 inline void emit_data(int x) { emit_int32(x); }
723 inline void emit_data(int, RelocationHolder const&);
724 inline void emit_data(int, relocInfo::relocType rtype);
725 // helper for above fcns
726 inline void check_delay();
727
728
729 public:
730 // instructions, refer to page numbers in the SPARC Architecture Manual, V9
731
732 // pp 135 (addc was addx in v8)
733
734 inline void add(Register s1, Register s2, Register d );
735 inline void add(Register s1, int simm13a, Register d );
736
737 void addcc( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(add_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
738 void addcc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(add_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
739 void addc( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(addc_op3 ) | rs1(s1) | rs2(s2) ); }
740 void addc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(addc_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
741 void addccc( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(addc_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
742 void addccc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(addc_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
743
744
745 // 4-operand AES instructions
746
747 void aes_eround01( FloatRegister s1, FloatRegister s2, FloatRegister s3, FloatRegister d ) { aes_only(); emit_int32( op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(aes4_op3) | fs1(s1, FloatRegisterImpl::D) | fs3(s3, FloatRegisterImpl::D) | op5(aes_eround01_op5) | fs2(s2, FloatRegisterImpl::D) ); }
748 void aes_eround23( FloatRegister s1, FloatRegister s2, FloatRegister s3, FloatRegister d ) { aes_only(); emit_int32( op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(aes4_op3) | fs1(s1, FloatRegisterImpl::D) | fs3(s3, FloatRegisterImpl::D) | op5(aes_eround23_op5) | fs2(s2, FloatRegisterImpl::D) ); }
749 void aes_dround01( FloatRegister s1, FloatRegister s2, FloatRegister s3, FloatRegister d ) { aes_only(); emit_int32( op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(aes4_op3) | fs1(s1, FloatRegisterImpl::D) | fs3(s3, FloatRegisterImpl::D) | op5(aes_dround01_op5) | fs2(s2, FloatRegisterImpl::D) ); }
750 void aes_dround23( FloatRegister s1, FloatRegister s2, FloatRegister s3, FloatRegister d ) { aes_only(); emit_int32( op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(aes4_op3) | fs1(s1, FloatRegisterImpl::D) | fs3(s3, FloatRegisterImpl::D) | op5(aes_dround23_op5) | fs2(s2, FloatRegisterImpl::D) ); }
751 void aes_eround01_l( FloatRegister s1, FloatRegister s2, FloatRegister s3, FloatRegister d ) { aes_only(); emit_int32( op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(aes4_op3) | fs1(s1, FloatRegisterImpl::D) | fs3(s3, FloatRegisterImpl::D) | op5(aes_eround01_l_op5) | fs2(s2, FloatRegisterImpl::D) ); }
752 void aes_eround23_l( FloatRegister s1, FloatRegister s2, FloatRegister s3, FloatRegister d ) { aes_only(); emit_int32( op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(aes4_op3) | fs1(s1, FloatRegisterImpl::D) | fs3(s3, FloatRegisterImpl::D) | op5(aes_eround23_l_op5) | fs2(s2, FloatRegisterImpl::D) ); }
753 void aes_dround01_l( FloatRegister s1, FloatRegister s2, FloatRegister s3, FloatRegister d ) { aes_only(); emit_int32( op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(aes4_op3) | fs1(s1, FloatRegisterImpl::D) | fs3(s3, FloatRegisterImpl::D) | op5(aes_dround01_l_op5) | fs2(s2, FloatRegisterImpl::D) ); }
754 void aes_dround23_l( FloatRegister s1, FloatRegister s2, FloatRegister s3, FloatRegister d ) { aes_only(); emit_int32( op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(aes4_op3) | fs1(s1, FloatRegisterImpl::D) | fs3(s3, FloatRegisterImpl::D) | op5(aes_dround23_l_op5) | fs2(s2, FloatRegisterImpl::D) ); }
755 void aes_kexpand1( FloatRegister s1, FloatRegister s2, int imm5a, FloatRegister d ) { aes_only(); emit_int32( op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(aes4_op3) | fs1(s1, FloatRegisterImpl::D) | u_field(imm5a, 13, 9) | op5(aes_kexpand1_op5) | fs2(s2, FloatRegisterImpl::D) ); }
756
757
758 // 3-operand AES instructions
759
760 void aes_kexpand0( FloatRegister s1, FloatRegister s2, FloatRegister d ) { aes_only(); emit_int32( op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(aes3_op3) | fs1(s1, FloatRegisterImpl::D) | opf(aes_kexpand0_opf) | fs2(s2, FloatRegisterImpl::D) ); }
761 void aes_kexpand2( FloatRegister s1, FloatRegister s2, FloatRegister d ) { aes_only(); emit_int32( op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(aes3_op3) | fs1(s1, FloatRegisterImpl::D) | opf(aes_kexpand2_opf) | fs2(s2, FloatRegisterImpl::D) ); }
762
763 // pp 136
764
765 inline void bpr(RCondition c, bool a, Predict p, Register s1, address d, relocInfo::relocType rt = relocInfo::none);
766 inline void bpr(RCondition c, bool a, Predict p, Register s1, Label& L);
767
768 // compare and branch
769 inline void cbcond(Condition c, CC cc, Register s1, Register s2, Label& L);
770 inline void cbcond(Condition c, CC cc, Register s1, int simm5, Label& L);
771
772 protected: // use MacroAssembler::br instead
773
774 // pp 138
775
776 inline void fb( Condition c, bool a, address d, relocInfo::relocType rt = relocInfo::none );
777 inline void fb( Condition c, bool a, Label& L );
778
779 // pp 141
780
781 inline void fbp( Condition c, bool a, CC cc, Predict p, address d, relocInfo::relocType rt = relocInfo::none );
782 inline void fbp( Condition c, bool a, CC cc, Predict p, Label& L );
783
784 // pp 144
785
786 inline void br( Condition c, bool a, address d, relocInfo::relocType rt = relocInfo::none );
787 inline void br( Condition c, bool a, Label& L );
788
789 // pp 146
790
791 inline void bp( Condition c, bool a, CC cc, Predict p, address d, relocInfo::relocType rt = relocInfo::none );
792 inline void bp( Condition c, bool a, CC cc, Predict p, Label& L );
793
794 // pp 149
795
796 inline void call( address d, relocInfo::relocType rt = relocInfo::runtime_call_type );
797 inline void call( Label& L, relocInfo::relocType rt = relocInfo::runtime_call_type );
798
799 public:
800
801 // pp 150
802
803 // These instructions compare the contents of s2 with the contents of
804 // memory at address in s1. If the values are equal, the contents of memory
805 // at address s1 is swapped with the data in d. If the values are not equal,
806 // the the contents of memory at s1 is loaded into d, without the swap.
807
808 void casa( Register s1, Register s2, Register d, int ia = -1 ) { v9_only(); emit_int32( op(ldst_op) | rd(d) | op3(casa_op3 ) | rs1(s1) | (ia == -1 ? immed(true) : imm_asi(ia)) | rs2(s2)); }
809 void casxa( Register s1, Register s2, Register d, int ia = -1 ) { v9_only(); emit_int32( op(ldst_op) | rd(d) | op3(casxa_op3) | rs1(s1) | (ia == -1 ? immed(true) : imm_asi(ia)) | rs2(s2)); }
810
811 // pp 152
812
813 void udiv( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(udiv_op3 ) | rs1(s1) | rs2(s2)); }
814 void udiv( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(udiv_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
815 void sdiv( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(sdiv_op3 ) | rs1(s1) | rs2(s2)); }
816 void sdiv( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(sdiv_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
817 void udivcc( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(udiv_op3 | cc_bit_op3) | rs1(s1) | rs2(s2)); }
818 void udivcc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(udiv_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
819 void sdivcc( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(sdiv_op3 | cc_bit_op3) | rs1(s1) | rs2(s2)); }
820 void sdivcc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(sdiv_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
821
822 // pp 155
823
824 void done() { v9_only(); cti(); emit_int32( op(arith_op) | fcn(0) | op3(done_op3) ); }
825 void retry() { v9_only(); cti(); emit_int32( op(arith_op) | fcn(1) | op3(retry_op3) ); }
826
827 // pp 156
828
829 void fadd( FloatRegisterImpl::Width w, FloatRegister s1, FloatRegister s2, FloatRegister d ) { emit_int32( op(arith_op) | fd(d, w) | op3(fpop1_op3) | fs1(s1, w) | opf(0x40 + w) | fs2(s2, w)); }
830 void fsub( FloatRegisterImpl::Width w, FloatRegister s1, FloatRegister s2, FloatRegister d ) { emit_int32( op(arith_op) | fd(d, w) | op3(fpop1_op3) | fs1(s1, w) | opf(0x44 + w) | fs2(s2, w)); }
831
832 // pp 157
833
834 void fcmp( FloatRegisterImpl::Width w, CC cc, FloatRegister s1, FloatRegister s2) { emit_int32( op(arith_op) | cmpcc(cc) | op3(fpop2_op3) | fs1(s1, w) | opf(0x50 + w) | fs2(s2, w)); }
835 void fcmpe( FloatRegisterImpl::Width w, CC cc, FloatRegister s1, FloatRegister s2) { emit_int32( op(arith_op) | cmpcc(cc) | op3(fpop2_op3) | fs1(s1, w) | opf(0x54 + w) | fs2(s2, w)); }
836
837 // pp 159
838
839 void ftox( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) { v9_only(); emit_int32( op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(fpop1_op3) | opf(0x80 + w) | fs2(s, w)); }
840 void ftoi( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) { emit_int32( op(arith_op) | fd(d, FloatRegisterImpl::S) | op3(fpop1_op3) | opf(0xd0 + w) | fs2(s, w)); }
841
842 // pp 160
843
844 void ftof( FloatRegisterImpl::Width sw, FloatRegisterImpl::Width dw, FloatRegister s, FloatRegister d ) { emit_int32( op(arith_op) | fd(d, dw) | op3(fpop1_op3) | opf(0xc0 + sw + dw*4) | fs2(s, sw)); }
845
846 // pp 161
847
848 void fxtof( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) { v9_only(); emit_int32( op(arith_op) | fd(d, w) | op3(fpop1_op3) | opf(0x80 + w*4) | fs2(s, FloatRegisterImpl::D)); }
849 void fitof( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) { emit_int32( op(arith_op) | fd(d, w) | op3(fpop1_op3) | opf(0xc0 + w*4) | fs2(s, FloatRegisterImpl::S)); }
850
851 // pp 162
852
853 void fmov( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) { emit_int32( op(arith_op) | fd(d, w) | op3(fpop1_op3) | opf(0x00 + w) | fs2(s, w)); }
854
855 void fneg( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) { emit_int32( op(arith_op) | fd(d, w) | op3(fpop1_op3) | opf(0x04 + w) | fs2(s, w)); }
856
857 void fabs( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) { emit_int32( op(arith_op) | fd(d, w) | op3(fpop1_op3) | opf(0x08 + w) | fs2(s, w)); }
858
859 // pp 163
860
861 void fmul( FloatRegisterImpl::Width w, FloatRegister s1, FloatRegister s2, FloatRegister d ) { emit_int32( op(arith_op) | fd(d, w) | op3(fpop1_op3) | fs1(s1, w) | opf(0x48 + w) | fs2(s2, w)); }
862 void fmul( FloatRegisterImpl::Width sw, FloatRegisterImpl::Width dw, FloatRegister s1, FloatRegister s2, FloatRegister d ) { emit_int32( op(arith_op) | fd(d, dw) | op3(fpop1_op3) | fs1(s1, sw) | opf(0x60 + sw + dw*4) | fs2(s2, sw)); }
863 void fdiv( FloatRegisterImpl::Width w, FloatRegister s1, FloatRegister s2, FloatRegister d ) { emit_int32( op(arith_op) | fd(d, w) | op3(fpop1_op3) | fs1(s1, w) | opf(0x4c + w) | fs2(s2, w)); }
864
865 // FXORs/FXORd instructions
866
867 void fxor( FloatRegisterImpl::Width w, FloatRegister s1, FloatRegister s2, FloatRegister d ) { vis1_only(); emit_int32( op(arith_op) | fd(d, w) | op3(flog3_op3) | fs1(s1, w) | opf(0x6E - w) | fs2(s2, w)); }
868
869 // pp 164
870
871 void fsqrt( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) { emit_int32( op(arith_op) | fd(d, w) | op3(fpop1_op3) | opf(0x28 + w) | fs2(s, w)); }
872
873 // pp 165
874
875 inline void flush( Register s1, Register s2 );
876 inline void flush( Register s1, int simm13a);
877
878 // pp 167
879
880 void flushw() { v9_only(); emit_int32( op(arith_op) | op3(flushw_op3) ); }
881
882 // pp 168
883
884 void illtrap( int const22a) { if (const22a != 0) v9_only(); emit_int32( op(branch_op) | u_field(const22a, 21, 0) ); }
885 // v8 unimp == illtrap(0)
886
887 // pp 169
888
889 void impdep1( int id1, int const19a ) { v9_only(); emit_int32( op(arith_op) | fcn(id1) | op3(impdep1_op3) | u_field(const19a, 18, 0)); }
890 void impdep2( int id1, int const19a ) { v9_only(); emit_int32( op(arith_op) | fcn(id1) | op3(impdep2_op3) | u_field(const19a, 18, 0)); }
891
892 // pp 170
893
894 void jmpl( Register s1, Register s2, Register d );
895 void jmpl( Register s1, int simm13a, Register d, RelocationHolder const& rspec = RelocationHolder() );
896
897 // 171
898
899 inline void ldf(FloatRegisterImpl::Width w, Register s1, Register s2, FloatRegister d);
900 inline void ldf(FloatRegisterImpl::Width w, Register s1, int simm13a, FloatRegister d, RelocationHolder const& rspec = RelocationHolder());
901
902
903 inline void ldfsr( Register s1, Register s2 );
904 inline void ldfsr( Register s1, int simm13a);
905 inline void ldxfsr( Register s1, Register s2 );
906 inline void ldxfsr( Register s1, int simm13a);
907
908 // 173
909
910 void ldfa( FloatRegisterImpl::Width w, Register s1, Register s2, int ia, FloatRegister d ) { v9_only(); emit_int32( op(ldst_op) | fd(d, w) | alt_op3(ldf_op3 | alt_bit_op3, w) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
911 void ldfa( FloatRegisterImpl::Width w, Register s1, int simm13a, FloatRegister d ) { v9_only(); emit_int32( op(ldst_op) | fd(d, w) | alt_op3(ldf_op3 | alt_bit_op3, w) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
912
913 // pp 175, lduw is ld on v8
914
915 inline void ldsb( Register s1, Register s2, Register d );
916 inline void ldsb( Register s1, int simm13a, Register d);
917 inline void ldsh( Register s1, Register s2, Register d );
918 inline void ldsh( Register s1, int simm13a, Register d);
919 inline void ldsw( Register s1, Register s2, Register d );
920 inline void ldsw( Register s1, int simm13a, Register d);
921 inline void ldub( Register s1, Register s2, Register d );
922 inline void ldub( Register s1, int simm13a, Register d);
923 inline void lduh( Register s1, Register s2, Register d );
924 inline void lduh( Register s1, int simm13a, Register d);
925 inline void lduw( Register s1, Register s2, Register d );
926 inline void lduw( Register s1, int simm13a, Register d);
927 inline void ldx( Register s1, Register s2, Register d );
928 inline void ldx( Register s1, int simm13a, Register d);
929 inline void ldd( Register s1, Register s2, Register d );
930 inline void ldd( Register s1, int simm13a, Register d);
931
932 // pp 177
933
934 void ldsba( Register s1, Register s2, int ia, Register d ) { emit_int32( op(ldst_op) | rd(d) | op3(ldsb_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
935 void ldsba( Register s1, int simm13a, Register d ) { emit_int32( op(ldst_op) | rd(d) | op3(ldsb_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
936 void ldsha( Register s1, Register s2, int ia, Register d ) { emit_int32( op(ldst_op) | rd(d) | op3(ldsh_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
937 void ldsha( Register s1, int simm13a, Register d ) { emit_int32( op(ldst_op) | rd(d) | op3(ldsh_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
938 void ldswa( Register s1, Register s2, int ia, Register d ) { v9_only(); emit_int32( op(ldst_op) | rd(d) | op3(ldsw_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
939 void ldswa( Register s1, int simm13a, Register d ) { v9_only(); emit_int32( op(ldst_op) | rd(d) | op3(ldsw_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
940 void lduba( Register s1, Register s2, int ia, Register d ) { emit_int32( op(ldst_op) | rd(d) | op3(ldub_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
941 void lduba( Register s1, int simm13a, Register d ) { emit_int32( op(ldst_op) | rd(d) | op3(ldub_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
942 void lduha( Register s1, Register s2, int ia, Register d ) { emit_int32( op(ldst_op) | rd(d) | op3(lduh_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
943 void lduha( Register s1, int simm13a, Register d ) { emit_int32( op(ldst_op) | rd(d) | op3(lduh_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
944 void lduwa( Register s1, Register s2, int ia, Register d ) { emit_int32( op(ldst_op) | rd(d) | op3(lduw_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
945 void lduwa( Register s1, int simm13a, Register d ) { emit_int32( op(ldst_op) | rd(d) | op3(lduw_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
946 void ldxa( Register s1, Register s2, int ia, Register d ) { v9_only(); emit_int32( op(ldst_op) | rd(d) | op3(ldx_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
947 void ldxa( Register s1, int simm13a, Register d ) { v9_only(); emit_int32( op(ldst_op) | rd(d) | op3(ldx_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
948
949 // pp 181
950
951 void and3( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(and_op3 ) | rs1(s1) | rs2(s2) ); }
952 void and3( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(and_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
953 void andcc( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(and_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
954 void andcc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(and_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
955 void andn( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(andn_op3 ) | rs1(s1) | rs2(s2) ); }
956 void andn( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(andn_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
957 void andncc( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(andn_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
958 void andncc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(andn_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
959 void or3( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(or_op3 ) | rs1(s1) | rs2(s2) ); }
960 void or3( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(or_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
961 void orcc( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(or_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
962 void orcc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(or_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
963 void orn( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(orn_op3) | rs1(s1) | rs2(s2) ); }
964 void orn( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(orn_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
965 void orncc( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(orn_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
966 void orncc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(orn_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
967 void xor3( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(xor_op3 ) | rs1(s1) | rs2(s2) ); }
968 void xor3( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(xor_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
969 void xorcc( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(xor_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
970 void xorcc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(xor_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
971 void xnor( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(xnor_op3 ) | rs1(s1) | rs2(s2) ); }
972 void xnor( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(xnor_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
973 void xnorcc( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(xnor_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
974 void xnorcc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(xnor_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
975
976 // pp 183
977
978 void membar( Membar_mask_bits const7a ) { v9_only(); emit_int32( op(arith_op) | op3(membar_op3) | rs1(O7) | immed(true) | u_field( int(const7a), 6, 0)); }
979
980 // pp 185
981
982 void fmov( FloatRegisterImpl::Width w, Condition c, bool floatCC, CC cca, FloatRegister s2, FloatRegister d ) { v9_only(); emit_int32( op(arith_op) | fd(d, w) | op3(fpop2_op3) | cond_mov(c) | opf_cc(cca, floatCC) | opf_low6(w) | fs2(s2, w)); }
983
984 // pp 189
985
986 void fmov( FloatRegisterImpl::Width w, RCondition c, Register s1, FloatRegister s2, FloatRegister d ) { v9_only(); emit_int32( op(arith_op) | fd(d, w) | op3(fpop2_op3) | rs1(s1) | rcond(c) | opf_low5(4 + w) | fs2(s2, w)); }
987
988 // pp 191
989
990 void movcc( Condition c, bool floatCC, CC cca, Register s2, Register d ) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(movcc_op3) | mov_cc(cca, floatCC) | cond_mov(c) | rs2(s2) ); }
991 void movcc( Condition c, bool floatCC, CC cca, int simm11a, Register d ) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(movcc_op3) | mov_cc(cca, floatCC) | cond_mov(c) | immed(true) | simm(simm11a, 11) ); }
992
993 // pp 195
994
995 void movr( RCondition c, Register s1, Register s2, Register d ) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(movr_op3) | rs1(s1) | rcond(c) | rs2(s2) ); }
996 void movr( RCondition c, Register s1, int simm10a, Register d ) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(movr_op3) | rs1(s1) | rcond(c) | immed(true) | simm(simm10a, 10) ); }
997
998 // pp 196
999
1000 void mulx( Register s1, Register s2, Register d ) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(mulx_op3 ) | rs1(s1) | rs2(s2) ); }
1001 void mulx( Register s1, int simm13a, Register d ) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(mulx_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1002 void sdivx( Register s1, Register s2, Register d ) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(sdivx_op3) | rs1(s1) | rs2(s2) ); }
1003 void sdivx( Register s1, int simm13a, Register d ) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(sdivx_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1004 void udivx( Register s1, Register s2, Register d ) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(udivx_op3) | rs1(s1) | rs2(s2) ); }
1005 void udivx( Register s1, int simm13a, Register d ) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(udivx_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1006
1007 // pp 197
1008
1009 void umul( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(umul_op3 ) | rs1(s1) | rs2(s2) ); }
1010 void umul( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(umul_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1011 void smul( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(smul_op3 ) | rs1(s1) | rs2(s2) ); }
1012 void smul( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(smul_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1013 void umulcc( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(umul_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
1014 void umulcc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(umul_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1015 void smulcc( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(smul_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
1016 void smulcc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(smul_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1017
1018 // pp 201
1019
1020 void nop() { emit_int32( op(branch_op) | op2(sethi_op2) ); }
1021
1022
1023 // pp 202
1024
1025 void popc( Register s, Register d) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(popc_op3) | rs2(s)); }
1026 void popc( int simm13a, Register d) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(popc_op3) | immed(true) | simm(simm13a, 13)); }
1027
1028 // pp 203
1029
1030 void prefetch( Register s1, Register s2, PrefetchFcn f) { v9_only(); emit_int32( op(ldst_op) | fcn(f) | op3(prefetch_op3) | rs1(s1) | rs2(s2) ); }
1031 void prefetch( Register s1, int simm13a, PrefetchFcn f) { v9_only(); emit_data( op(ldst_op) | fcn(f) | op3(prefetch_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
1032
1033 void prefetcha( Register s1, Register s2, int ia, PrefetchFcn f ) { v9_only(); emit_int32( op(ldst_op) | fcn(f) | op3(prefetch_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
1034 void prefetcha( Register s1, int simm13a, PrefetchFcn f ) { v9_only(); emit_int32( op(ldst_op) | fcn(f) | op3(prefetch_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1035
1036 // pp 208
1037
1038 // not implementing read privileged register
1039
1040 inline void rdy( Register d) { v9_dep(); emit_int32( op(arith_op) | rd(d) | op3(rdreg_op3) | u_field(0, 18, 14)); }
1041 inline void rdccr( Register d) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(rdreg_op3) | u_field(2, 18, 14)); }
1042 inline void rdasi( Register d) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(rdreg_op3) | u_field(3, 18, 14)); }
1043 inline void rdtick( Register d) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(rdreg_op3) | u_field(4, 18, 14)); } // Spoon!
1044 inline void rdpc( Register d) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(rdreg_op3) | u_field(5, 18, 14)); }
1045 inline void rdfprs( Register d) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(rdreg_op3) | u_field(6, 18, 14)); }
1046
1047 // pp 213
1048
1049 inline void rett( Register s1, Register s2);
1050 inline void rett( Register s1, int simm13a, relocInfo::relocType rt = relocInfo::none);
1051
1052 // pp 214
1053
1054 void save( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(save_op3) | rs1(s1) | rs2(s2) ); }
1055 void save( Register s1, int simm13a, Register d ) {
1056 // make sure frame is at least large enough for the register save area
1057 assert(-simm13a >= 16 * wordSize, "frame too small");
1058 emit_int32( op(arith_op) | rd(d) | op3(save_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) );
1059 }
1060
1061 void restore( Register s1 = G0, Register s2 = G0, Register d = G0 ) { emit_int32( op(arith_op) | rd(d) | op3(restore_op3) | rs1(s1) | rs2(s2) ); }
1062 void restore( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(restore_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1063
1064 // pp 216
1065
1066 void saved() { v9_only(); emit_int32( op(arith_op) | fcn(0) | op3(saved_op3)); }
1067 void restored() { v9_only(); emit_int32( op(arith_op) | fcn(1) | op3(saved_op3)); }
1068
1069 // pp 217
1070
1071 inline void sethi( int imm22a, Register d, RelocationHolder const& rspec = RelocationHolder() );
1072 // pp 218
1073
1074 void sll( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(sll_op3) | rs1(s1) | sx(0) | rs2(s2) ); }
1075 void sll( Register s1, int imm5a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(sll_op3) | rs1(s1) | sx(0) | immed(true) | u_field(imm5a, 4, 0) ); }
1076 void srl( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(srl_op3) | rs1(s1) | sx(0) | rs2(s2) ); }
1077 void srl( Register s1, int imm5a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(srl_op3) | rs1(s1) | sx(0) | immed(true) | u_field(imm5a, 4, 0) ); }
1078 void sra( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(sra_op3) | rs1(s1) | sx(0) | rs2(s2) ); }
1079 void sra( Register s1, int imm5a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(sra_op3) | rs1(s1) | sx(0) | immed(true) | u_field(imm5a, 4, 0) ); }
1080
1081 void sllx( Register s1, Register s2, Register d ) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(sll_op3) | rs1(s1) | sx(1) | rs2(s2) ); }
1082 void sllx( Register s1, int imm6a, Register d ) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(sll_op3) | rs1(s1) | sx(1) | immed(true) | u_field(imm6a, 5, 0) ); }
1083 void srlx( Register s1, Register s2, Register d ) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(srl_op3) | rs1(s1) | sx(1) | rs2(s2) ); }
1084 void srlx( Register s1, int imm6a, Register d ) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(srl_op3) | rs1(s1) | sx(1) | immed(true) | u_field(imm6a, 5, 0) ); }
1085 void srax( Register s1, Register s2, Register d ) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(sra_op3) | rs1(s1) | sx(1) | rs2(s2) ); }
1086 void srax( Register s1, int imm6a, Register d ) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(sra_op3) | rs1(s1) | sx(1) | immed(true) | u_field(imm6a, 5, 0) ); }
1087
1088 // pp 220
1089
1090 void sir( int simm13a ) { emit_int32( op(arith_op) | fcn(15) | op3(sir_op3) | immed(true) | simm(simm13a, 13)); }
1091
1092 // pp 221
1093
1094 void stbar() { emit_int32( op(arith_op) | op3(membar_op3) | u_field(15, 18, 14)); }
1095
1096 // pp 222
1097
1098 inline void stf( FloatRegisterImpl::Width w, FloatRegister d, Register s1, Register s2);
1099 inline void stf( FloatRegisterImpl::Width w, FloatRegister d, Register s1, int simm13a);
1100
1101 inline void stfsr( Register s1, Register s2 );
1102 inline void stfsr( Register s1, int simm13a);
1103 inline void stxfsr( Register s1, Register s2 );
1104 inline void stxfsr( Register s1, int simm13a);
1105
1106 // pp 224
1107
1108 void stfa( FloatRegisterImpl::Width w, FloatRegister d, Register s1, Register s2, int ia ) { v9_only(); emit_int32( op(ldst_op) | fd(d, w) | alt_op3(stf_op3 | alt_bit_op3, w) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
1109 void stfa( FloatRegisterImpl::Width w, FloatRegister d, Register s1, int simm13a ) { v9_only(); emit_int32( op(ldst_op) | fd(d, w) | alt_op3(stf_op3 | alt_bit_op3, w) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1110
1111 // p 226
1112
1113 inline void stb( Register d, Register s1, Register s2 );
1114 inline void stb( Register d, Register s1, int simm13a);
1115 inline void sth( Register d, Register s1, Register s2 );
1116 inline void sth( Register d, Register s1, int simm13a);
1117 inline void stw( Register d, Register s1, Register s2 );
1118 inline void stw( Register d, Register s1, int simm13a);
1119 inline void stx( Register d, Register s1, Register s2 );
1120 inline void stx( Register d, Register s1, int simm13a);
1121 inline void std( Register d, Register s1, Register s2 );
1122 inline void std( Register d, Register s1, int simm13a);
1123
1124 // pp 177
1125
1126 void stba( Register d, Register s1, Register s2, int ia ) { emit_int32( op(ldst_op) | rd(d) | op3(stb_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
1127 void stba( Register d, Register s1, int simm13a ) { emit_int32( op(ldst_op) | rd(d) | op3(stb_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1128 void stha( Register d, Register s1, Register s2, int ia ) { emit_int32( op(ldst_op) | rd(d) | op3(sth_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
1129 void stha( Register d, Register s1, int simm13a ) { emit_int32( op(ldst_op) | rd(d) | op3(sth_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1130 void stwa( Register d, Register s1, Register s2, int ia ) { emit_int32( op(ldst_op) | rd(d) | op3(stw_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
1131 void stwa( Register d, Register s1, int simm13a ) { emit_int32( op(ldst_op) | rd(d) | op3(stw_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1132 void stxa( Register d, Register s1, Register s2, int ia ) { v9_only(); emit_int32( op(ldst_op) | rd(d) | op3(stx_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
1133 void stxa( Register d, Register s1, int simm13a ) { v9_only(); emit_int32( op(ldst_op) | rd(d) | op3(stx_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1134 void stda( Register d, Register s1, Register s2, int ia ) { emit_int32( op(ldst_op) | rd(d) | op3(std_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
1135 void stda( Register d, Register s1, int simm13a ) { emit_int32( op(ldst_op) | rd(d) | op3(std_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1136
1137 // pp 230
1138
1139 void sub( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(sub_op3 ) | rs1(s1) | rs2(s2) ); }
1140 void sub( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(sub_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1141
1142 void subcc( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(sub_op3 | cc_bit_op3 ) | rs1(s1) | rs2(s2) ); }
1143 void subcc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(sub_op3 | cc_bit_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1144 void subc( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(subc_op3 ) | rs1(s1) | rs2(s2) ); }
1145 void subc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(subc_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1146 void subccc( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(subc_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
1147 void subccc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(subc_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1148
1149 // pp 231
1150
1151 inline void swap( Register s1, Register s2, Register d );
1152 inline void swap( Register s1, int simm13a, Register d);
1153
1154 // pp 232
1155
1156 void swapa( Register s1, Register s2, int ia, Register d ) { v9_dep(); emit_int32( op(ldst_op) | rd(d) | op3(swap_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
1157 void swapa( Register s1, int simm13a, Register d ) { v9_dep(); emit_int32( op(ldst_op) | rd(d) | op3(swap_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1158
1159 // pp 234, note op in book is wrong, see pp 268
1160
1161 void taddcc( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(taddcc_op3 ) | rs1(s1) | rs2(s2) ); }
1162 void taddcc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(taddcc_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1163
1164 // pp 235
1165
1166 void tsubcc( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(tsubcc_op3 ) | rs1(s1) | rs2(s2) ); }
1167 void tsubcc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(tsubcc_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1168
1169 // pp 237
1170
1171 void trap( Condition c, CC cc, Register s1, Register s2 ) { emit_int32( op(arith_op) | cond(c) | op3(trap_op3) | rs1(s1) | trapcc(cc) | rs2(s2)); }
1172 void trap( Condition c, CC cc, Register s1, int trapa ) { emit_int32( op(arith_op) | cond(c) | op3(trap_op3) | rs1(s1) | trapcc(cc) | immed(true) | u_field(trapa, 6, 0)); }
1173 // simple uncond. trap
1174 void trap( int trapa ) { trap( always, icc, G0, trapa ); }
1175
1176 // pp 239 omit write priv register for now
1177
1178 inline void wry( Register d) { v9_dep(); emit_int32( op(arith_op) | rs1(d) | op3(wrreg_op3) | u_field(0, 29, 25)); }
1179 inline void wrccr(Register s) { v9_only(); emit_int32( op(arith_op) | rs1(s) | op3(wrreg_op3) | u_field(2, 29, 25)); }
1180 inline void wrccr(Register s, int simm13a) { v9_only(); emit_int32( op(arith_op) |
1181 rs1(s) |
1182 op3(wrreg_op3) |
1183 u_field(2, 29, 25) |
1184 immed(true) |
1185 simm(simm13a, 13)); }
1186 inline void wrasi(Register d) { v9_only(); emit_int32( op(arith_op) | rs1(d) | op3(wrreg_op3) | u_field(3, 29, 25)); }
1187 // wrasi(d, imm) stores (d xor imm) to asi
1188 inline void wrasi(Register d, int simm13a) { v9_only(); emit_int32( op(arith_op) | rs1(d) | op3(wrreg_op3) |
1189 u_field(3, 29, 25) | immed(true) | simm(simm13a, 13)); }
1190 inline void wrfprs( Register d) { v9_only(); emit_int32( op(arith_op) | rs1(d) | op3(wrreg_op3) | u_field(6, 29, 25)); }
1191
1192 // VIS1 instructions
1193
1194 void alignaddr( Register s1, Register s2, Register d ) { vis1_only(); emit_int32( op(arith_op) | rd(d) | op3(alignaddr_op3) | rs1(s1) | opf(alignaddr_opf) | rs2(s2)); }
1195
1196 void faligndata( FloatRegister s1, FloatRegister s2, FloatRegister d ) { vis1_only(); emit_int32( op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(faligndata_op3) | fs1(s1, FloatRegisterImpl::D) | opf(faligndata_opf) | fs2(s2, FloatRegisterImpl::D)); }
1197
1198 void fsrc2( FloatRegisterImpl::Width w, FloatRegister s2, FloatRegister d ) { vis1_only(); emit_int32( op(arith_op) | fd(d, w) | op3(fsrc_op3) | opf(0x7A - w) | fs2(s2, w)); }
1199
1200 void stpartialf( Register s1, Register s2, FloatRegister d, int ia = -1 ) { vis1_only(); emit_int32( op(ldst_op) | fd(d, FloatRegisterImpl::D) | op3(stpartialf_op3) | rs1(s1) | imm_asi(ia) | rs2(s2)); }
1201
1202 // VIS2 instructions
1203
1204 void edge8n( Register s1, Register s2, Register d ) { vis2_only(); emit_int32( op(arith_op) | rd(d) | op3(edge_op3) | rs1(s1) | opf(edge8n_opf) | rs2(s2)); }
1205
1206 // VIS3 instructions
1207
1208 void movstosw( FloatRegister s, Register d ) { vis3_only(); emit_int32( op(arith_op) | rd(d) | op3(mftoi_op3) | opf(mstosw_opf) | fs2(s, FloatRegisterImpl::S)); }
1209 void movstouw( FloatRegister s, Register d ) { vis3_only(); emit_int32( op(arith_op) | rd(d) | op3(mftoi_op3) | opf(mstouw_opf) | fs2(s, FloatRegisterImpl::S)); }
1210 void movdtox( FloatRegister s, Register d ) { vis3_only(); emit_int32( op(arith_op) | rd(d) | op3(mftoi_op3) | opf(mdtox_opf) | fs2(s, FloatRegisterImpl::D)); }
1211
1212 void movwtos( Register s, FloatRegister d ) { vis3_only(); emit_int32( op(arith_op) | fd(d, FloatRegisterImpl::S) | op3(mftoi_op3) | opf(mwtos_opf) | rs2(s)); }
1213 void movxtod( Register s, FloatRegister d ) { vis3_only(); emit_int32( op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(mftoi_op3) | opf(mxtod_opf) | rs2(s)); }
1214
1215 // Crypto SHA instructions
1216
1217 void sha1() { sha1_only(); emit_int32( op(arith_op) | op3(sha_op3) | opf(sha1_opf)); }
1218 void sha256() { sha256_only(); emit_int32( op(arith_op) | op3(sha_op3) | opf(sha256_opf)); }
1219 void sha512() { sha512_only(); emit_int32( op(arith_op) | op3(sha_op3) | opf(sha512_opf)); }
1220
1221 // Creation
1222 Assembler(CodeBuffer* code) : AbstractAssembler(code) {
1223 #ifdef CHECK_DELAY
1224 delay_state = no_delay;
1225 #endif
1226 }
1227 };
1228
1229 #endif // CPU_SPARC_VM_ASSEMBLER_SPARC_HPP